MAX5975BETE+ [MAXIM]
Current-Mode PWM Controllers with Frequency Dithering for EMI-Sensitive Power Supplies;
| 型号： | MAX5975BETE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Current-Mode PWM Controllers with Frequency Dithering for EMI-Sensitive Power Supplies |
| 文件： | 总20页 (文件大小：2189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5545; Rev 0; 9/10
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
General Description
Features
S Peak Current-Mode Control, Forward/Flyback
The MAX5975_ current-mode PWM controllers contain
all the control circuitry required for the design of wide-
input-voltage forward and flyback power supplies in
Power-over-Ethernet (PoE) IEEE® 802.3af/at powered
devices. The MAX5975A is well-suited for universal input
(rectified 85V AC to 265V AC) or telecom (-36V DC to
-72V DC) power supplies. The MAX5975B is available for
low-voltage supplies (12V to 24V) such as wall adapters.
PWM Controllers
S Internal 1% Error Amplifier
S 100kHz to 600kHz Programmable ±±% Switching
Frequency
S Switching Frequency Synchronization Up to
1.2MHz
S Programmable Frequency Dithering for Low-EMI
The devices are suitable for both isolated and noniso-
lated designs. Because the devices have an internal error
amplifier with a 1% accurate reference, they can be used
in nonisolated power supplies without the need for an
external shunt regulator.
Spread-Spectrum Operation
S PWM Soft-Start, Current Slope Compensation
S Programmable Feed-Forward Maximum Duty-
Cycle Clamp, ±0% Maximum Limit
An enable input (EN) is used to shut down the devices.
Programmable soft-start eliminates output voltage over-
shoot. The MAX5975A has an internal bootstrap UVLO
with large hysteresis that requires 20V for startup, while
the MAX5975B requires 10V for startup.
S Frequency Foldback for High-Efficiency Light-
Load Operation
S Internal Bootstrap UVLO with Large Hysteresis
S 100µA (typ) Startup Supply Current
The switching frequency for the ICs is programmable
from 100kHz to 600kHz with an external resistor. For
EMI-sensitive design, use the programmable frequency
dithering feature for low-EMI spread-spectrum opera-
tion. The duty cycle is also programmable up to the 80%
maximum duty-cycle limit. These devices are available in
16-lead TQFN packages and are rated for operation over
the -40°C to +85°C temperature range.
S Fast Cycle-by-Cycle Peak Current-Limit, 35ns
Typical Propagation Delay
S 115ns Current-Sense Internal Leading-Edge
Blanking
S Output Short-Circuit Protection with Hiccup Mode
S 3mm x 3mm, Lead-Free, 16-Pin TQFN
Applications
PoE IEEE 802.3af/at Powered Devices
Flyback/Forward DC-DC Converters
IP Phones
Wireless Access Nodes
Security Cameras
Power Devices in PoE/Power-over-MDI
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 TQFN-EP*
16 TQFN-EP*
TOP MARK
+AIC
UVLO THRESHOLD (V)
MAX5975AETE+
MAX5975BETE+
20
10
+AID
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
ABSOLUTE MAXIMUM RATINGS
IN to GND..............................................................-0.3V to +26V
Continuous Power Dissipation (T = +70NC) (Note 1)
A
16-Pin TQFN (derate 20.8mW/NC above +70NC).......1666mW
EN, NDRV to GND......................................-0.3V to (V + 0.3V)
IN
RT, FFB, COMP, SS, DCLMP, DITHER/SYNC
Junction-to-Case Thermal Resistance (B ) (Note 1)
JC
to GND .................................................................-0.3V to +6V
FB to GND...............................................................-0.3V to +6V
CS, CSSC to GND...................................................-0.8V to +6V
PGND to GND ......................................................-0.3V to +0.3V
Maximum Input/Output Current (continuous)
16-Pin TQFN................................................................ +7NC/W
Junction-to-Ambient Thermal Resistance (B ) (Note 1)
JA
16-Pin TQFN.............................................................. +48NC/W
Operating Temperature Range.......................... -40NC to +85NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
NDRV ............................................................................100mA
NDRV (pulsed for less than 100ns) .................................. Q1A
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, C = 1FF, T = -40NC to +85NC, unless otherwise noted. Typical values
RT
IN
A
are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT/STARTUP (IN)
MAX5975A
MAX5975B
19.1
9.4
19.8
9.8
20.4
Bootstrap UVLO Wakeup Level
V
V
V
rising
falling
V
V
INUVR
IN
10.25
Bootstrap UVLO Shutdown
Level
V
6.65
7
7.35
INUVF
IN
V
V
= +18V (for MAX5975A);
= +9V (for MAX597BA),
IN
IN Supply Current in
Undervoltage Lockout
I
100
1.8
150
3
FA
START
IN
when in bootstrap UVLO
IN Supply Current After Startup
I
C
V
IN
= +12V
mA
ENABLE (EN)
V
V
V
rising
falling
1.17
1.09
1.215
1.14
1.26
1.19
1
ENR
EN
Enable Threshold
V
V
ENF
EN
Input Current
I
FA
EN
OSCILLATOR (RT)
RT Bias Voltage
V
1.23
82.5
V
RT
NDRV Switching Frequency
Range
f
100
600
kHz
SW
NDRV Switching Frequency
Accuracy
-8
+8
84
%
%
Maximum Duty Cycle
D
MAX
f
= 250kHz
81
SW
2
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, C = 1FF, T = -40NC to +85NC, unless otherwise noted. Typical values
RT
IN
A
are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.91
1.1 x
TYP
MAX
UNITS
SYNCHRONIZATION (SYNC)
Synchronization Logic-High
Input
V
V
IH-SYNC
SYNCIN
Synchronization Pulse Width
50
ns
Synchronization Frequency
Range
2 x
f
SW
f
kHz
f
SW
Maximum Duty Cycle During
Synchronization
D
x f
SW
/
MAX
SYNC
%
f
DITHERING RAMP GENERATOR (DITHER)
Charging Current
V
V
= 0V
45
43
50
50
2
55
57
FA
FA
V
DITHER
Discharging Current
= 2.2V
DITHER
Ramp’s High Trip Point
Ramp’s Low Trip Point
0.4
V
SOFT-START AND RESTART (SS)
Charging Current
I
I
9.5
10
10.5
2
FA
SS-CH
I
V
= 2V, normal shutdown
0.65
1.34
mA
SS-D
SS
(V < V
or V < V
),
EN
ENF
IN
INUVF
Discharging Current
V
SS
= 2V, hiccup mode discharge for
1.6
2
2.4
FA
SS-DH
t
(Note 3)
RESTART
Discharge Threshold to Disable
Hiccup and Restart
V
0.15
V
SS-DTH
Minimum Restart Time During
Hiccup Mode
Clock
Cycles
t
1024
5
RSTRT-MIN
Normal Operating High Voltage
Duty-Cycle Control Range
DUTY-CYCLE CLAMP (DCLMP)
DCLMP Input Current
V
SS-HI
V
V
V
D
(typ) = (V /2.43V)
SS-DMAX
0
2
SS-DMAX
MAX
I
V
= 0 to 5V
-100
75
0
+100
79.5
60
nA
%
DCLMP
DCLMP
V
= 0.5V
= 1V
77.3
58
DCLMP
DCLMP
DCLMP
Duty-Cycle Control Range
V
V
V
56
DCLMP-R
D
(typ) =
MAX
1 - (V
/2.43V)
DCLMP
= 2V
17
18.6
20.5
NDRV DRIVER
Pulldown Impedance
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
R
I
I
(sinking) = 100mA
1.9
4.7
1
3.4
8.3
I
I
NDRV-N
NDRV
R
(sourcing) = 50mA
NDRV-P
NDRV
A
0.65
14
A
t
C
C
= 1nF
= 1nF
ns
ns
NDRV-F
NDRV
Rise Time
t
27
NDRV-R
NDRV
3
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, C = 1FF, T = -40NC to +85NC, unless otherwise noted. Typical values
RT
IN
A
are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT-LIMIT COMPARATORS (CS)
Cycle-by-Cycle Peak
Current-Limit Threshold
V
375
393
8
410
mV
Events
ns
CS-PEAK
Number of Consecutive Peak
Current-Limit Events to Hiccup
N
HICCUP
Current-Sense Leading-Edge
Blanking Time
t
From NDRV rising edge
115
CS-BLANK
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
Propagation Delay from
Comparator Input to NDRV
t
35
ns
ns
PDCS
Minimum On-Time
t
100
47
150
200
58
ON-MIN
SLOPE COMPENSATION (CSSC)
Slope Compensation Current
Ramp Height
Current ramp’s peak added to CSSC
input per switching cycle
52
FA
PWM COMPARATOR
Comparator Offset Voltage
Current-Sense Gain
V
V
- V
CSSC
1.35
3.1
1.7
2
V
PWM-OS
COMP
A
DV
/DV (Note 4)
COMP CSSC
3.33
3.6
V/V
CS-PWM
Current-Sense Leading-Edge
Blanking Time
t
From NDRV rising edge
Change in V = 10mV (including
115
150
ns
ns
CSSC-BLANK
CSSC
Comparator Propagation Delay
t
PWM
internal leading-edge blanking)
ERROR AMPLIFIER
FB Reference Voltage
FB Input Bias Current
Voltage Gain
V
V
V
when I
= 0, V = 2.5V
COMP
1.202
-500
1.215
1.227
+100
V
REF
FB
COMP
I
= 0 to 1.75V
nA
dB
mS
FB
FB
A
EAMP
80
Transconductance
g
1.8
2.66
3.5
M
Open loop (typical gain = 1) -3dB
frequency
Transconductance Bandwidth
BW
30
MHz
Source Current
V
V
= 1V, V
= 2.5V
300
300
375
375
455
455
FA
FA
FB
FB
COMP
Sink Current
= 1.75V, V
= 1V
COMP
FREQUENCY FOLDBACK (FFB)
V
Gain
-to-FFB Comparator
CSAVG
10
30
V/V
FA
FFB Bias Current
I
V
FFB
= 0V, V = 0V (not in FFB mode)
26
33
FFB
CS
NDRV Switching Frequency
During Foldback
f
f /2
SW
kHz
SW-FB
Note 2: The devices are 100% production tested at T = +25NC. Limits over temperature are guaranteed by design.
A
Note 3: See the Output Short-Circuit Protection with Hiccup Mode section.
Note 4: The parameter is measured at the trip point of latch with V = 0V. Gain is defined as DV
/DV
for 0.15V <
FB
COMP
CSSC
DV
< 0.25V.
CSSC
4
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Operating Characteristics
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
FB
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, unless otherwise noted.)
RT
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE
IN UVLO SHUTDOWN LEVEL
vs. TEMPERATURE
20.1
20.0
19.9
19.8
19.7
19.6
19.5
10.1
10.0
9.9
7.3
7.2
7.1
7.0
6.9
MAX5975A
MAX5975B
9.8
9.7
9.6
9.5
6.8
-40
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
EN RISING THRESHOLD
vs. TEMPERATURE
EN FALLING THRESHOLD
vs. TEMPERATURE
UVLO SHUTDOWN CURRENT
vs. TEMPERATURE
1.220
1.218
1.216
1.214
1.212
1.210
1.150
1.149
1.148
1.147
1.146
1.145
1.144
1.143
1.142
140
120
100
80
MAX5975A
MAX5975B
60
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5975A)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(MAX5975B)
SUPPLY CURRENT
vs. SWITCHING FREQUENCY
10,000
1000
100
10,000
1000
100
2.4
2.0
1.6
1.2
0.8
0.4
0
T
= +85°C
A
T
= +85°C
A
T
= -40°C
A
T
= -40°C
A
10
10
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
0
100 200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
5
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Operating Characteristics (continued)
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
FB
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, unless otherwise noted.)
RT
SWITCHING FREQUENCY
vs. R VALUE
SOFT-START CHARGING CURRENT
vs. TEMPERATURE
SWITCHING FREQUENCY
vs. TEMPERATURE
RT
1000
100
10
10.06
10.05
10.04
10.03
10.02
10.01
10.00
9.99
252
251
250
249
248
247
246
245
9.98
9.97
244
-40
10
100
-40
-15
10
35
60
85
-15
10
35
60
85
R
VALUE (kΩ)
TEMPERATURE (°C)
RT
TEMPERATURE (°C)
FREQUENCY DITHERING
vs. R
MAXIMUM DUTY CYCLE
vs. SWITCHING FREQUENCY
MAXIMUM DUTY CYCLE
vs. TEMPERATURE
DITHER
14
12
10
8
84.0
83.8
83.6
83.4
83.2
83.0
82.8
82.6
82.4
82.2
82.0
83.0
82.9
82.8
82.7
82.6
82.5
82.4
82.3
82.2
82.1
6
4
2
0
82.0
-40
300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800
SWITCHING FREQUENCY (kHz)
-15
10
35
60
85
R
(kΩ)
DITHER
TEMPERATURE (°C)
MAXIMUM DUTY CYCLE
MAXIMUM DUTY CYCLE
vs. SYNC FREQUENCY
vs. V
SS
100
90
80
70
60
50
40
30
20
10
45
40
35
30
25
20
15
10
5
V
= 0.5V
SS
0
0
0
0.5
1.0
1.5
(V)
2.0
2.5
250
300
350
400
450
500
V
SYNC FREQUENCY (kHz)
SS
6
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Operating Characteristics (continued)
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, unless otherwise noted.)
RT
MAXIMUM DUTY CYCLE
SLOPE COMPENSATION CURRENT
vs. TEMPERATURE
PEAK CURRENT-LIMIT THRESHOLD
vs. V
DCLMP
vs. TEMPERATURE
100
90
80
70
60
50
40
30
20
10
0
398
397
396
395
394
393
392
391
390
389
388
54.0
53.5
53.0
52.5
52.0
51.5
51.0
50.5
50.0
0
0.5
1.0
1.5
2.0
2.5
-40
-40
85
-15
10
35
60
85
-40
-15
10
35
60
85
V
(V)
DCLMP
TEMPERATURE (°C)
TEMPERATURE (°C)
NDRV MINIMUM ON-TIME
vs. TEMPERATURE
CURRENT-SENSE GAIN
vs. TEMPERATURE
FEEDBACK VOLTAGE
vs. TEMPERATURE
170
165
160
155
150
145
140
3.40
3.39
3.38
3.37
3.36
3.35
3.34
3.33
3.32
3.31
3.30
1.220
1.219
1.218
1.217
1.216
1.215
1.214
1.213
1.212
1.211
1.210
-40
-15
10
35
60
85
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
TRANSCONDUCTANCE
vs. TEMPERATURE
TRANSCONDUCTANCE HISTOGRAM
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
25
20
15
10
5
0
-40
-15
10
35
60
2.56 2.58 2.60 2.62 2.64 2.66 2.68 2.70 2.72 2.74 2.76
TRANSCONDUCTANCE (mS)
TEMPERATURE (°C)
7
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Operating Characteristics (continued)
(V = 12V (for MAX5975A, bring V up to 21V for startup), V = V
= V
= V = V
= V
= V
, V
GND EN
=
IN
IN
CS
CSSC
DITHER/SYNC
FB
FFB
DCLMP
+2V, NDRV = SS = COMP = unconnected, R = 34.8kI, unless otherwise noted.)
RT
ENABLE RESPONSE
SHUTDOWN RESPONSE
SHUTDOWN RESPONSE
MAX5975A/B toc28
MAX5975A/B toc26
MAX5975A/B toc27
V
2V/V
EN
V
EN
V
EN
2V/V
2V/V
V
NDRV
10V/div
V
NDRV
10V/div
V
NDRV
V
SS
10V/div
5V/div
V
SS
5V/div
10ms/div
10µs/div
1ms/div
V
SS
RAMP RESPONSE
V
RAMP RESPONSE
NDRV 10% TO 90% RISE TIME
MAX5975A/B toc31
DCLMP
MAX5975A/B toc29
MAX5975A/B toc30
V
SS
V
DCLMP
2V/div
27.6ns
2V/div
V
NDRV
2V/div
V
NDRV
V
NDRV
10V/div
10V/div
0ns
10µs/div
10µs/div
10ns/div
NDRV 90% TO 10% FALL TIME
PEAK NDRV CURRENT
SHORT-CIRCUIT BEHAVIOR
MAX5975A/B toc34
MAX5975A/B toc32
MAX5975A/B toc33
PEAK SOURCE CURRENT
V
IN
0ns
V
NDRV
I
NDRV
2V/div
0.5A/div
V
I
NDRV
13.8ns
LX
PEAK SINK CURRENT
10ns/div
200ns/div
40ms/div
±
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Pin Configuration
TOP VIEW
12
11
10
9
CSSC
GND
FB
13
14
IN
8
7
6
5
EN
MAX5975A
MAX5975B
DCLMP 15
16
EP
COMP
SS
+
1
2
3
4
TQFN
Pin Description
PIN
NAME
FUNCTION
1, 12
N.C.
No Connection. Not internally connected.
Frequency Dithering Programming or Synchronization Connection. For spread-spectrum frequency
operation, connect a capacitor from DITHER to GND, and a resistor from DITHER to RT. To
synchronize the internal oscillator to the externally applied frequency, connect DITHER/SYNC to
the synchronization pulse.
DITHER/
SYNC
2
3
Switching Frequency Programming Resistor Connection. Connect resistor R from RT to GND to
RT
set the PWM switching frequency. See the Oscillator/Switching Frequency section to calculate the
RT
resistor value for the desired oscillator frequency.
Frequency Foldback Threshold Programming Input. Connect a resistor from FFB to GND to set the
output average current threshold below which the converter folds back the switching frequency to
1/2 of its original value. Connect to GND to disable frequency foldback.
4
5
FFB
Transconductance Amplifier Output and PWM Comparator Input. COMP is level shifted down and
connected to the inverting input of the PWM comparator.
COMP
9
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Pin Description (continued)
PIN
6
NAME
FB
FUNCTION
Transconductance Amplifier Inverting Input
Signal Ground
7
GND
Current Sense with Slope Compensation Input. A resistor connected from CSSC to CS programs
the amount of slope compensation. See the Programmable Slope Compensation section.
8
9
CSSC
CS
Current-Sense Input. Current-sense connection for average current sense and cycle-by-cycle
current limit. Peak current-limit trip voltage is 400mV.
10
11
PGND
NDRV
Power Ground. PGND is the return path for gate-driver switching currents.
External Switching nMOS Gate-Driver Output
Converter Supply Input. IN has wide UVLO hysteresis, enabling the design of efficient power
supplies. When the enable input EN is used to program a UVLO level for the power source,
connect a zener diode between IN and PGND to ensure that V is always clamped below its
IN
13
14
15
IN
EN
absolute maximum rating of 26V.
Enable Input. The gate drivers are disabled and the device is in a low-power UVLO mode, when
the voltage on EN is below V . When the voltage on EN is above V , the device checks for
ENF ENR
other enable conditions. See the Enable Input section for more information about interfacing to EN.
Feed-Forward Maximum Duty-Cycle Clamp Programming Input. Connect a resistor-divider
between the input supply voltage DCLMP and GND. The voltage at DCLMP sets the maximum
DCLMP
duty cycle (D ) of the converter inversely proportional to the input supply voltage, so that the
MAX
MOSFET remains protected during line transients.
Soft-Start Programming Capacitor Connection. Connect a capacitor from SS to GND to program
the soft-start period. This capacitor also determines hiccup mode current-limit restart time. A
16
—
SS
EP
resistor from SS to GND can also be used to set the D
below 75%.
MAX
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
10
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Block Diagram
11
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Current-Mode Control Loop
Detailed Description
The advantages of current-mode control over voltage-
The MAX5975_ is optimized for controlling a 25W to
mode control are twofold. First, there is the feed-forward
50W forward/flyback converter in continuous-conduction
characteristic brought on by the controller’s ability to adjust
mode. The power MOSFET gate driver (NDRV) is sized
for variations in the input voltage on a cycle-by-cycle basis.
to optimize efficiency for 25W design. The feature-rich
Secondly, the stability requirements of the current-mode
devices are ideal for PoE IEEE 802.3af/at-powered
controller are reduced to that of a single-pole system,
devices.
unlike the double pole in voltage-mode control.
The MAX5975A offers a bootstrap UVLO wakeup level of
The devices use a current-mode control loop where the
20V with a wide hysteresis of 13V. The low startup and
scaled output of the error amplifier (COMP) is compared
operating currents allow the use of a smaller storage
to a slope-compensated current-sense signal at CSSC.
capacitor at the input without compromising startup and
hold times. The device is well-suited for universal input
(rectified 85V AC to 265V AC) or telecom (-36V DC to
-72V DC) power supplies.
Enable Input
The enable input EN is used to enable or disable the
device. Connect EN to IN for always enabled applica-
tions. Connecting EN to ground disables the device and
reduces current consumption to 100FA.
The MAX5975B has a UVLO rising threshold of 10V and
is well-suited for low-input voltage (12V DC to 24V DC)
power sources such as wall adapters.
The enable input has an accurate threshold of 1.26V
(max). For applications that require a UVLO on the
power source, connect a resistive divider from the power
source to EN to GND as shown in Figure 1. A zener
diode between IN and PGND is required to prevent
IN from exceeding its absolute maximum rating of 26V
when the device is disabled. The zener diode should
be inactive below the maximum UVLO rising threshold
Power supplies designed with the MAX5975A use a
high-value startup resistor, R , that charges a reservoir
IN
capacitor, C (see the Typical Applications Circuits).
IN
During this initial period, while the voltage is less than
the internal bootstrap UVLO threshold, the device typi-
cally consumes only 100FA of quiescent current. This
low startup current and the large bootstrap UVLO hys-
voltage V
(21V for the MAX5975A and 10.5V
INUVR(MAX)
teresis help to minimize the power dissipation across R
IN
for the MAX5975B). Design the resistive divider by first
selecting the value of R to be on the order of 100kI.
even at the high end of the universal AC input voltage
(265V AC).
EN1
Then calculate R
as follows:
EN2
Feed-forward maximum duty-cycle clamping detects
changes in line conditions and adjusts the maximum
duty cycle accordingly to eliminate the clamp voltage's
(i.e., the main power FET's drain voltage) dependence
on the input voltage.
V
EN(MAX)
R
= R
EN1
EN2
V
− V
EN(MAX)
S(UVLO)
where V
is the maximum enable threshold volt-
EN(MAX)
For EMI-sensitive applications, the programmable fre-
quency dithering feature allows up to Q10% variation in
the switching frequency. This spread-spectrum modula-
tion technique spreads the energy of switching harmon-
ics over a wider band while reducing their peaks, help-
ing to meet stringent EMI goals.
age and is equal to 1.26V and V
is the desired
S(UVLO)
UVLO threshold for the power source, below which the
devices are disabled.
In the case where EN is externally controlled and UVLO for
the power source is unnecessary, connect EN to IN and an
open-drain or open-collector output as shown in Figure 2.
The digital output connected to EN should be capable of
withstanding IN’s absolute maximum voltage of 26V.
The devices include a cycle-by-cycle current limit that
turns off the driver whenever the internally set threshold
of 400mV is exceeded. Eight consecutive occurrences
of current-limit event trigger hiccup mode, which pro-
tects external components by halting switching for a
Bootstrap Undervoltage Lockout
The device has an internal bootstrap UVLO that is very
useful when designing high-voltage power supplies (see
the Block Diagram). This allows the device to bootstrap
itself during initial power-up. The MAX5975A soft-starts
period of time (t
) and allowing the overload current
RSTRT
to dissipate in the load and body diode of the synchro-
nous rectifier before soft-start is reattempted.
when V exceeds the bootstrap UVLO threshold of
IN
V
(20V typ).
INUVR
12
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Because the MAX5975B is designed for use with low-
voltage power sources such as wall adapters outputting
V
S
12V to 24V, it has a lower UVLO wakeup threshold of 10V.
Startup Operation
The device starts up when the voltage at IN exceeds 20V
(MAX5975A) or 10V (MAX5975B) and the enable input
voltage is greater than 1.26V.
R
IN
IN
During normal operation, the voltage at IN is normally
derived from a tertiary winding of the transformer.
However, at startup there is no energy being deliv-
ered through the transformer; hence, a special boot-
strap sequence is required. In the Typical Applications
C
IN
MAX5975
R
EN1
Circuits, C charges through the startup resistor, R , to
IN
IN
an intermediate voltage. Only 100FA of the current sup-
plied through R is used by the ICs, the remaining input
DIGITAL
CONTROL
EN
IN
current charges C until V reaches the bootstrap
IN
IN
R
N
EN2
UVLO wakeup level. Once V exceeds this level, NDRV
IN
begins switching the n-channel MOSFET and transfers
energy to the secondary and tertiary outputs. If the volt-
age on the tertiary output builds to higher than 7V (the
bootstrap UVLO shutdown level), then startup has been
accomplished and sustained operation commences.
Figure 1. Programmable UVLO for the Power Source
If V drops below 7V before startup is complete, the
IN
device goes back to low-current UVLO. In this case,
increase the value of C to store enough energy to allow
IN
the voltage at the tertiary winding to build up.
V
S
Soft-Start
A capacitor from SS to GND, C , programs the soft-
SS
start time. V controls the oscillator duty cycle during
startup to provide a slow and smooth increase of the
duty cycle to its steady-state value. Calculate the value
SS
R
IN
IN
of C as follows:
SS
C
IN
I
× t
2V
SS-CH SS
C
=
SS
MAX5975
where I
(10FA typ) is the current charging C dur-
SS
SS-CH
ing soft-start and t is the programmed soft-start time.
DIGITAL
CONTROL
SS
EN
A resistor can also be added from the SS pin to GND to clamp
V
SS
< 2V and, hence, program the maximum duty cycle to be
N
less than 80% (see the Duty-Cycle Clamping section).
n-Channel MOSFET Gate Driver
The NDRV output drives an external n-channel MOSFET.
NDRV can source/sink in excess of 650mA/1000mA peak
current; therefore, select a MOSFET that yields acceptable
conduction and switching losses. The external MOSFET
used must be able to withstand the maximum clamp voltage.
Figure 2. External Control of the Enable Input
13
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
The devices implement 115ns of leading-edge blanking
to ignore leading-edge current spikes. These spikes
are caused by reflected secondary currents, current-
discharging capacitance at the FET’s drain, and gate-
charging current. Use a small RC network for additional
filtering of the leading-edge spike on the sense wave-
form when needed. Set the corner frequency between
10MHz and 20MHz.
Oscillator/Switching Frequency
The ICs’ switching frequency is programmable between
100kHz and 600kHz with a resistor R
connected
RT
between RT and GND. Use the following formula to
determine the appropriate value of R needed to gen-
RT
erate the desired output-switching frequency (f ):
SW
9
8.7 ×10
R
=
RT
After the leading-edge blanking time, the device moni-
f
SW
tors V
for any breaches of the peak current limit of
CS
where f
is the desired switching frequency.
400mV. The duty cycle is terminated immediately when
exceeds 400mV.
SW
V
CS
Peak Current Limit
The current-sense resistor (R in the Typical
Application Circuits), connected between the source
of the n-channel MOSFET and PGND, sets the current
limit. The current-limit comparator has a voltage trip level
Output Short-Circuit Protection
with Hiccup Mode
When the device detects eight consecutive peak current-
limit events, the driver output is turned off for a restart
CS
period, t
. After t
RSTRT
, the device undergoes
RSTRT
(V
) of 400mV. Use the following equation to cal-
CS-PEAK
soft-start. The duration of the restart period depends
on the value of the capacitor at SS (C ). During this
culate the value of R
:
CS
SS
period, C
is discharged with a pulldown current of
400mV
SS
R
=
CS
I
(2FA typ). Once its voltage reaches 0.15V, the
SS-DH
I
PRI
restart period ends and the device initiates a soft-start
sequence. An internal counter ensures that the minimum
restart period (t
the time required for C to discharge to 0.15V is less
than 1024 clock cycles. Figure 3 shows the behavior of
the device prior and during hiccup mode.
where I
is the peak current in the primary side of
PRI
) is 1024 clock cycles when
RSTRT-MIN
the transformer, which also flows through the MOSFET.
When the voltage produced by this current (through the
current-sense resistor) exceeds the current-limit com-
parator threshold, the MOSFET driver (NDRV) terminates
the current on-cycle, within 35ns (typ).
SS
V
CS-PEAK
(400mV)
V
CSBL
(BLANKED CS
VOLTAGE)
HICCUP
DISCHARGE WITH I
SS_DS
V
SS_H
SOFT-START
VOLTAGE,
V
SS_SD
V
SS
t
SS
t
RSTRT
Figure 3. Hiccup Mode Timing Diagram
14
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
where R
GND, and I
(10FA typ).
is the resistor connected between SS and
is the current sourced from SS to R
Frequency Foldback for High-Efficiency
Light-Load Operation
The frequency foldback threshold can be programmed
from 0 to 20% of the full load current using a resistor from
FFB to GND.
SS
SS-CH
SS
DCLMP
To set D
using supply voltage feed forward, connect
MAX
Figure 4 shows device operation in frequency foldback
a resistive divider between the supply voltage, DCLMP,
and GND as shown in the Typical Applications Circuits.
This feed-forward duty-cycle clamp ensures that the
external n-channel MOSFET is not stressed during sup-
mode. Calculate the value of R
as follows:
FFB
10 ×I
×R
LOAD(LIGHT)
CS
R
=
FFB
ply transients. V
is calculated as follows:
DCLMP
I
FFB
R
DCLMP2
whereR
istheresistorconnectedtoFFB,I
LOAD(LIGHT)
FFB
V
=
× V
S
DCLMP
R
+ R
is the current at light-load conditions that triggers fre-
quency foldback, R is the value of the sense resistor
DCLMP1
DCLMP2
CS
connected between CS and PGND, and I
is the cur-
FFB
where R
and R
are the resistive divider
DCLMP2
DCLMP1
rent sourced from FFB to R
(30FA typ).
FFB
values shown in the Typical Applications Circuits and V
S
is the input supply voltage.
Duty-Cycle Clamping
The maximum duty cycle is determined by the lowest
of three voltages: 2V, the voltage at SS (V ), and the
Oscillator Synchronization
The internal oscillator can be synchronized to an exter-
nal clock by applying the clock to SYNC/DITHER direct-
ly. The external clock frequency can be set anywhere
between 1.1x to 2x the internal clock frequency.
SS
voltage (2.43V - V
calculated as:
). The maximum duty cycle is
DCLMP
V
MIN
D
=
MAX
2.43V
= minimum (2V, V , 2.43V - V ).
DCLMP
Using an external clock increases the maximum duty
cycle by a factor equal to f
/f . This factor should
SYNC SW
where V
MIN
SS
be accounted for in setting the maximum duty cycle
using any of the methods described in the Duty-Cycle
Clamping section. The formula below shows how the
maximum duty cycle is affected by the external clock
frequency:
SS
By connecting a resistor between SS and ground, the
voltage at SS can be made to be lower than 2V. V is
SS
calculated as follows:
V
= R ×I
SS SS−CH
SS
V
f
SYNC
MIN
D
=
×
MAX
2.43V
f
SW
V
CSAVG
FFB
NDRV
t
t
X 2
t
X 2
SW
SW
SW
COMP
Figure 4. Entering Frequency Foldback
15
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
where V
section, f
is described in the Duty-Cycle Clamping
is the switching frequency as set by the
sense signal for stability of the peak current-mode
control loop. The ramp rate of the slope compensation
signal is given by:
MIN
SW
resistor connected between RT and GND, and f
is
SYNC
the external clock frequency.
R
× 50µA × f
80%
CSSC
SW
Frequency Dithering for
Spread-Spectrum Applications (Low EMI)
The switching frequency of the converter can be dith-
ered in a range of Q10% by connecting a capacitor from
SYNC/DITHER to GND, and a resistor from DITHER to
RT as shown in the Typical Applications Circuits. This
results in lower EMI.
m =
where m is the ramp rate of the slope-compensation
signal, R is the value of the resistor connected
between CSSC and CS used to program the ramp rate,
and f is the switching frequency.
CSSC
SW
Error Amplifier
A current source at SYNC/DITHER charges the capaci-
The MAX5975A/MAX5975B include an internal error
amplifier. The noninverting input of the error ampli-
fier is connected to the internal 1.215V reference and
feedback is provided at the inverting input. High 80dB
open-loop gain and 30MHz unity-gain bandwidth allow
good closed-loop bandwidth and transient response.
Calculate the power-supply output voltage using the fol-
lowing equation:
tor C
to 2V at 50FA. Upon reaching this trip point,
DITHER
it discharges C
to 0.4V at 50FA. The charging
DITHER
and discharging of the capacitor generates a triangular
waveform on SYNC/DITHER with peak levels at 0.4V and
2V and a frequency that is equal to:
50µA
f
=
TRI
C
× 3.2V
DITHER
R
+ R
FB1
R
FB2
Typically, f
should be set close to 1kHz. The resistor
TRI
V
= V
×
OUT
REF
R
connected from SYNC/DITHER to RT deter-
DITHER
FB2
mines the amount of dither as follows:
where V
= 1.215V.
REF
4
3
R
RT
DITHER
%DITHER =
×
Applications Information
R
Startup Time Considerations
where %DITHER is the amount of dither expressed as a
percentage of the switching frequency. Setting R
The bypass capacitor at IN, C , supplies current
IN
DITHER
immediately after the devices wake up (see the Typical
to 10 x R generates Q10% dither.
RT
Application Circuits). Large values of C
increase
IN
the startup time, but also supply gate charge for more
cycles during initial startup. If the value of C is too
Programmable Slope Compensation
The devices generate a current ramp at CSSC such
that its peak is 50FA at 80% duty cycle of the oscillator.
An external resistor connected from CSSC to CS then
converts this current ramp into programmable slope-
compensation amplitude, which is added to the current-
IN
small, V drops below 7V because NDRV does not have
IN
enough time to switch and build up sufficient voltage
across the tertiary output, which powers the device. The
device goes back into UVLO and does not start. Use a
low-leakage capacitor for C .
IN
16
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
MAX5975B
The parameters governing the design of the bootstrap
circuit are different for the MAX5975B. While the above
design equations remain valid, the following values must
MAX5975A
Typically, offline power supplies keep startup times to
less than 500ms even in low-line conditions (85V AC
input for universal offline or 36V DC for telecom applica-
be used when designing for R and C : V
= 3V and
tions). Size the startup resistor, R , to supply both the
IN
IN HYST
IN
V
is the minimum output voltage of the wall adapter.
maximum startup bias of the device (150FA) and the
S(MIN)
charging current for C . C must be charged to 20V
IN
IN
Bias Circuit
within the desired 500ms time period. C must store
IN
An in-phase tertiary winding is needed to power the bias
enough charge to deliver current to the device for at
circuit. The voltage across the tertiary V during the on-
T
least the soft-start time (t ) set by C . To calculate the
SS
SS
time is:
approximate amount of capacitance required, use the
following formula:
N
N
T
S
V
= V
×
T
OUT
I
= Q
f
G
GTOT SW
(I +I )(t )
SS
IN
G
C
=
IN
where V
is the output voltage and N /N is the turns
T S
ratio from the tertiary to the secondary winding. Select the
OUT
V
HYST
turns ratio so that V is above the UVLO shutdown level
(7.5V max).
T
where I is the internal supply current (1.7mA) after
IN
startup, Q
is the total gate charge for the n-channel
GTOT
Layout Recommendations
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain current
often form high di/dt loops. Similarly, the heatsink of the
main MOSFET presents a dV/dt source; therefore, mini-
mize the surface area of the MOSFET heatsink as much
as possible. Keep all PCB traces carrying switching cur-
rents as short as possible to minimize current loops. Use
a ground plane for best results.
FET, f
is the switching frequency, V
is the boot-
SW
HYST
strap UVLO hysteresis (13V typ), and t is the soft-start
time. R is then calculated as follows:
SS
IN
V
− V
S(MIN)
INUVR
R
≅
IN
I
START
where V
is the minimum input supply voltage for
S(MIN)
the application (36V for telecom), V
strap UVLO wake-up level (20V), and I
is the boot-
INUVR
is the IN
START
For universal AC input design, follow all applicable
safety regulations. Offline power supplies may require
UL, VDE, and other similar agency approvals.
supply current at startup (150FA max).
Choose a higher value for R than the one calculated
IN
above if longer startup time can be tolerated in order to
minimize power loss on this resistor.
17
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Application Circuits
V
R
IN
S
L1
D1
N
C
IN
T
C
BULK
D2
C
CLAMP
R
CLAMP
D3
L2
D4
T1
R
R
FB1
FB2
IN
N
P
N
S
C
OUT2
C
OUT3
C
C
OUT1
OUT4
D5
EN
SS
C
SS
R
DT
DT
R
DITHER
MAX5975
DITHER/
SYNC
C
DITHER
(FORWARD
R
OPTO1
C
R
Z
GATE3
CONFIGURATION)
NDRV
N
R
RT
N3
RT
IN
U1
R
FFB
FFB
FB
CS
R
BIAS
R
R
Q1
R
CSSC
Q2
CSSC
COMP
R
CS
C
INT
C
HF
R
OPTO2
SGND
PGND
U2
1±
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Typical Application Circuits (continued)
V
R
IN
S
L1
D1
N
C
T
C
IN
BULK
D2
C
CLAMP
R
CLAMP
D3
D4
T1
R
R
FB1
FB2
IN
N
P
C
C
OUT2
C
OUT3
C
OUT1
OUT4
EN
SS
C
SS
N
S
R
DT
DT
R
DITHER
MAX5975
DITHER/
SYNC
C
DITHER
(FLYBACK
R
OPTO1
C
R
Z
GATE3
CONFIGURATION)
NDRV
N
R
N3
RT
RT
IN
U1
R
FFB
FFB
FB
CS
R
BIAS
C
R
Q1
R
R
CSSC
Q2
CSSC
COMP
R
CS
INT
C
HF
R
OPTO2
SGND
PGND
U2
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TQFN-EP
T1655+4
21-0136
90-0031
19
Current-Mode PWM Controllers with Frequency
Dithering for EMI-Sensitive Power Supplies
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
9/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
20
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
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