MAX5988A [MAXIM]
High Efficiency During Light Loads Reduces Power Consumption;
| 型号： | MAX5988A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High Efficiency During Light Loads Reduces Power Consumption |
| 文件： | 总23页 (文件大小：908K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
General Description
Benefits and Features
● High Integration Saves Space and BOM Cost
• Efficient, Integrated DC-DC Converter (with
Integrated Switches)
The MAX5988A/MAX5988B provide a complete power-
®
supply solution as IEEE 802.3af-compliant Class 1/
Class 2 Powered Devices (PDs) in a Power-over-Ethernet
(PoE) system. The devices integrate the PD interface with
an efficient DC-DC converter, offering a low external part
count PD solution. The devices also include a low-drop-
out regulator, MPS, sleep, and ultra-low-power modes.
• Built-In Output-Voltage Monitoring
• Protects Against Overload, Output Short Circuit,
Output Overvoltage, and Overtemperature
• Integrated TVS Diode Withstands Cable Discharge
Event (CDE)
The PD interface provides a detection signature and
a Class 1/Class 2 classification signature with a single
external resistor. The PD interface also provides an isola-
tion power MOSFET, a 60mA (max) inrush current limit,
and a 321mA (typ) operating current limit.
• Internal LDO Regulator with Up to 100mA Load
● Application-Specific Features Speed Design
• IEEE 802.3af Compliant
• PoE Class 1/Class 2 Classification Set with Single
Resistor
• Intelligent Maintain Power Signature (MPS)
• Simplified Wall Adapter Interface
• Pass 2kV, 200m CAT-6 Cable Discharge Event
The integrated step-down DC-DC converter uses a peak
current-mode control scheme and provides an easy-to-
implement architecture with a fast transient response.
The step-down converter operates in a wide input volt-
age range from 8.8V to 60V and supports up to 6.49W of
input power at 1.3A load. The DC-DC converter operates
at a fixed 215kHz switching frequency, with an efficiency-
boosting frequency foldback that reduces the switching
frequency by half at light loads.
● High Efficiency During Light Loads Reduces Power
Consumption
• Sleep and Ultra-Low-Power Mode
• Frequency Foldback for High-Efficiency Light-Load
Operation
• Back-Bias Capability to Optimize the Efficiency
The devices feature an input undervoltage-lockout
(UVLO) with wide hysteresis and long deglitch time to
compensate for twisted-pair cable resistive drop and to
assure glitch-free transition during power-on/-off condi-
tions. The devices also feature overtemperature shut-
down, short-circuit protection, output overvoltage protec-
tion, and hiccup current limit for enhanced performance
and reliability.
● Robust Performance
• 8.8V to 60V Wide Input Voltage Range
• Hiccup-Mode Runaway Current Limit
• 49mA (typ) Inrush Current Limit
• Open-Drain RESET Output
● Easy to Design With
• 3.0V to 14V Programmable Output Voltage Range
• Internal Compensation
• Fixed 215kHz Switching Frequency
• Fixed 3.3V or Adjustable Output Voltage through
an External Resistive Divider (LDO)
All devices are available in a 20-pin, 4mm x 4mm, TQFN
power package and operate over the -40°C to +85°C
temperature range.
Applications
● IEEE 802.3af-Powered Devices
● IP Phones
Ordering Information/Selector Guide appears at end of data
sheet.
● Wireless Access Nodes
● IP Security Cameras
®
● WiMAX Base Stations
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
WiMAX is a registered certification mark and registered service
mark of WiMAX Forum.
19-6476; Rev 3; 1/15
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Absolute Maximum Ratings
(All voltages referenced to GND, unless otherwise noted.)
VDRV to V ............................................ -0.3V to (V
+ 0.3V)
DD
DD
PGND to GND ......................................................-0.3V to +0.3V
LX Total RMS Current...........................................................1.6A
V
to GND..........................-0.3V to +70V (internally clamped)
DD
(100V, 100ms, R
= 3.3kω) (Note 1)
TEST
Continuous Power Dissipation (T = + 70NC)
V
, WAD, RREF to GND ........................ -0.3V to (V
+ 0.3V)
A
CC
DD
TQFN (derate 28.6mW/NC above +70NC)..............2285.7mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
AUX, LDO_IN, LED to GND .................................... -0.3V to 16V
LDO_OUT to GND.............................. -0.3V to (LDO_IN + 0.3V)
LDO_FB to GND......................................................-0.3V to +6V
LX to GND ................................................ -0.3V to (V
+ 0.3V)
CC
LDO_OUT, VDRV, FB, RESET, WK, SL, ULP, MPS, CLASS2
to GND..............................................................-0.3V to +6V
Note 1: See Figure 1, Test Circuit.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 2)
Junction-to-Ambient Thermal Resistance (q )..............35°C/W
JA
Junction-to-Case Thermal Resistance (q )..................2.7°C/W
JC
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 48V, R
= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
DD
SIG CC
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
AUX
FB
enced to GND, unless otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
A
J
A
PARAMETER
POWER DEVICE (PD) INTERFACE
DETECTION MODE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Offset Current
I
V
V
= 1.4V to 10.1V (Note 4)
8
µA
kω
OFFSET
dR
VDD
Effective Differential Input
Resistance
= 1.4V to 10.1V with 1V step,
VDD
23.95
25.5
(Note 5)
CLASSIFICATION MODE
Classification Enable Threshold
Classification Disable Threshold
Classification Stability Time
V
V
V
rising
rising
10.2
22
11.42
23
12.5
23.8
V
V
TH,CLS,EN
DD
V
TH,CLS,DIS
DD
2
ms
CLASS2 = GND
CLASS2 = VDRV
9.12
16.1
10.5
18
11.88
20.9
V
= 12.6V
DD
Classification Current
I
mA
CLASS
to 20V
POWER MODE
V
V
Supply Voltage Range
Supply Current
V
60
V
DD
DD
I
V
DD
= 60V
3.3
4.5
mA
DD
DD
Maxim Integrated
│ 2
www.maximintegrated.com
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(V
= 48V, R
= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
DD
SIG CC
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
AUX
FB
enced to GND, unless otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
A
J
A
PARAMETER
Turn-On Voltage
SYMBOL
CONDITIONS
MIN
37.2
30
TYP
38.8
31.5
7.3
MAX
UNITS
V
V
V
V
ON
V
V
rising
falling
40
V
V
V
DD
DD
DD
DD
Turn-Off Voltage
V
OFF
HYST_UVLO
DD
Turn-On/Off Hysteresis
V
(Note 6)
falling from 40V to 20V
V
DD
(Note 5)
V
DD
Deglitch Time
t
150
123
µs
ms
ω
OFF_DLY
t
= time after (V )
- V
DELAY
from 1.5V to 0V
DD CC
Inrush to Operating Mode Delay
t
DELAY
T = +25°C
1.2
1.5
Isolation Power MOSFET On-
Resistance
J
R
I
= 100mA
VCC
ON_ISO
T = +85°C
J
MAINTAIN POWER SIGNATURE (MPS = VDRV)
PoE MPS Current Rising
Threshold
I
18
14
28.7
24
40
35
mA
mA
mA
mA
MPS_RISE
PoE MPS Current Falling
Threshold
I
MPS_FALL
PoE MPS Current Threshold
Hysteresis
I
4.3
4.8
MPS_HYS
PoE MPS Output Average
Current
I
MPS_AVE
PoE MPS Peak Output Current
PoE MPS Time High
PoE MPS Time Low
I
10
12.6
95
mA
ms
ms
MPS_PEAK
I
MPS_HIGH
I
190
MPS_LOW
CURRENT LIMIT
During initial turn-on period,
- V = 4V, measured at V
Inrush Current Limit
I
39
49
60
mA
mA
INRUSH
V
DD CC CC
Current Limit During Normal
Operation
After inrush completed, V
- 1.5V, measured at V
= V
CC DD
I
290
321
360
LIM
CC
LOGIC
WAD Detection Rising Threshold
V
8.8
2.9
V
V
WAD_RISE
WAD Detection Falling Threshold
V
5.8
WAD_FALL
WAD Detection Hysteresis
WAD Input Current
0.6
V
I
V
WAD
= 24V
125
µA
WAD
CLASS2, MPS Voltage Rising
Threshold
V
V
CLASS2, RISE
Maxim Integrated
│ 3
www.maximintegrated.com
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(V
= 48V, R
= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
DD
SIG CC
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
AUX
FB
enced to GND, unless otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLASS2, MPS Voltage Falling
Threshold
V
0.4
V
CLASS2, FALL
RESET Output Voltage Low
V
I
= 1mA
SINK
0.2
V
OL_RESET
RESET, CLASS2, MPS Leakage
I
-10
+10
µA
LOG_LEAK
INTERNAL REGULATOR WITH BACK BIAS
V
V
V
Input Voltage Range
Input Current
V
Inferred from V
input current
from 4.75V to 14V
4.75
0.65
4.2
14
3.1
5.5
V
mA
V
AUX
AUX
DRV
AUX
AUX
I
V
V
AUX
AUX
Output Voltage
SLEEP MODE
falling and V
ULP
rising and
WK
WK and ULP Logic Threshold
V
1.6
2.9
0.8
V
TH
falling
SL Logic Threshold
SL Current
Falling
0.55
V
V
SL
= 0V
62.4
10.6
21.2
21.2
µA
R
SL
R
SL
R
SL
= 60.4kω, V
= 30.2kω, V
= 30.2kω, V
= 6.5V
= 6.5V
= 3.5V
9.2
12
LED
LED
LED
LED Current Amplitude
I
19.2
23.5
mA
LED
LED Current Programmable
Range
I
10
20
mA
RANGE
LED Current with Grounded SL
LED Current Frequency
I
V
= 0V
20.6
26
250
25
31.4
mA
Hz
%
LED_MAX
SL
f
Sleep and ultra-low-power modes
Sleep and ultra-low-power modes
ILED
LED Current Duty Cycle
D
ILED
V
DD
Current Amplitude
I
Sleep mode, V
LED
= 6.5V
10
12
14.5
mA
VDD
Internal Current Duty Cycle
Internal Current Enable Time
Internal Current Disable Time
THERMAL SHUTDOWN
D
Sleep and ultra-low-power modes
Ultra-low-power mode
75
88
%
IVDD
MP_ENABLE
t
76
98
ms
ms
t
Ultra-low-power mode
205
237
265
MP_DISABLE
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
LDO
T
T rising
J
151
16
°C
°C
SD
T
SD,HYS
Input Voltage Range
Output Voltage
Inferred from line regulation
4.5
1.2
14
V
V
V
V
LDO_FB = V
DRV
3.3
Max Output Voltage Setting
LDO FB Regulation Voltage
With external divider to LDO_FB
5.5
1.227
1.25
Maxim Integrated
│ 4
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(V
= 48V, R
= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
DD
SIG CC
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
AUX
FB
enced to GND, unless otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO FB Leakage Current
-1
+1
µA
V
= 5V, V
LDO_FB
= V ,
DRV
LDO_IN
Dropout
V
300
mV
DROPOUT
I
= 80mA
LOAD
Load Regulation
Line Regulation
I
from 1mA to 80mA
0.5
1.4
mV/mA
mV/V
LOAD
VLDO_IN from 4.5V to 14V
Overcurrent Protection
Threshold
I
85
mA
OVC
LDO_FB Rising Threshold
LDO_FB Hysteresis
3.3
2.4
3.7
V
V
2.3
DC-DC CONVERTER INPUT SUPPLY
V
V
V
= V
= V
= V
= V
- 0.3V, rising
8
60
60
DD,RISING
CC
DD
WAD
V
Voltage Range
V
V
V
V
DD
V
- 0.3V, falling
7.7
DD,FALLING
CC
DD
WAD
WAD Detection Rising Threshold
WAD Detection Falling Threshold
V
(Note 7)
8.8
WAD,RISE
V
(Note 7)
5.8
WAD,FALL
WAD Detection Hysteresis
POWER MOSFETs
0.6
High-Side pMOS On-Resistance
Low-Side nMOS On-Resistance
R
I
I
= 0.5A (sourcing)
= 0.5A (sinking)
0.54
0.14
ω
ω
DSON-H
LX
LX
R
DSON-L
V
= V
CC
= 28V, V = (V
LX PGND
DD
LX Leakage Current
I
-5
+5
µA
LX-LKG
+ 1V) to (V
CC
- 1V)
SOFT-START (SS)
Soft-Start Time
t
10
ms
SS-TH
FEEDBACK (FB)
FB Regulation Voltage
FB Input Bias Current
OUTPUT VOLTAGE
V
1.203
1.226
10
1.252
200
V
FB-RG
I
V
FB
= 1.224V
nA
FB
MAX5988A
MAX5988B
3.0
5.4
5.6
14
Output Voltage Range
V
OUT
V
Rising (Note 8)
Falling (Note 8)
100.5
98.5
103
108
104
Cycle-by-Cycle Overvoltage
Protection
V
%
OUT-OV
101.1
Maxim Integrated
│ 5
www.maximintegrated.com
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(V
= 48V, R
= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
DD
SIG CC
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
AUX
FB
enced to GND, unless otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERNAL COMPENSATION NETWORK
Compensation Network Zero-
Resistance
R
200
150
kω
pF
ZERO
ZERO
Compensation Network Zero-
Capacitance
C
CURRENT LIMIT
CLASS2 = GND
1.45
1.66
0.75
0.85
1.64
1.79
0.81
0.94
1.9
MAX5988A
MAX5988B
MAX5988A
MAX5988B
CLASS2 = VDRV
CLASS2 = GND
CLASS2 = VDRV
CLASS2 = GND
CLASS2 = VDRV
CLASS2 = GND
CLASS2 = VDRV
Peak Current-Limit Threshold
I
A
A
PEAK-LIMIT
2.2
Runaway Current-Limit
Threshold
I
RUNAWAY-LIMIT
0.93
1.07
1.5
MAX5988A
MAX5988B
Valley Current-Limit Threshold
I
A
VALLEY-LIMIT
0.75
25
ZX Threshold
I
mA
ZX
TIMINGS
Switching Frequency
Frequency Foldback
f
190
95
215
238
119
kHz
kHz
SW
f
107.5
SW-FOLD
Consecutive ZX Events for
Entering Foldback
8
8
Events
Events
%
Consecutive ZX Events for
Exiting Foldback
V
OUT
Undervoltage Trip Level to
V
After soft-start completed (Note 8)
55
60
65
OUT-HICF
Cause HICCUP
HICCUP Timeout
Minimum On-Time
LX Dead Time
RESET
154
113
14
ms
ns
ns
t
140
ON-MIN
V
Threshold for RESET
FB
Assertion
V
V
V
falling (Note 8)
rising (Note 8)
87
90
95
93
98
%
%
FB-OKF
FB
V
FB
Threshold for RESET
V
91.5
FB-OKR
FB
Deassertion
Maxim Integrated
│ 6
www.maximintegrated.com
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Electrical Characteristics (continued)
(V
= 48V, R
= 24.9kω, LED, V , SL, ULP, WK, RESET, LDO_OUT unconnected, WAD = LDO_EN = LDO_IN = PGND = GND,
DD
SIG CC
C1 = 68nF, C2 = 10µF, C3 = 1µF (see Figure 3), V = V
= 0V, LX unconnected, CLASS2 = 0V, MPS = 0V. All voltages are refer-
AUX
FB
enced to GND, unless otherwise noted. T = T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 3)
A
J
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
Threshold for RESET
V
falling, LDO_FB = V
DRV
LDO_FB
Assertion
LDO_FB
(Note 9)
V
90
%
LDO_FB-OKF
V
Threshold for RESET
LDO_FB
V
FB
rising
95
%
Deassertion
RESET Deassertion Delay
4.8
ms
Note 3: All devices are 100% production tested at T = +25°C. Limits over temperature are guaranteed by design.
A
Note 4: The input offset current is illustrated in Figure 2.
Note 5: Effective differential input resistance is defined as the differential resistance between V
and GND, see Figure 2.
DD
Note 6: A 20V glitch on input voltage, which takes V
below V
shorter than or equal to t
does not cause the device to
DD
ON
OFF_DLY
exit power-on mode.
Note 7: The WAD detection rising and falling thresholds control the isolation power MOS transistor. To turn the DC-DC on in WAD
mode, the WAD must be detected and the V
Note 8 Referred to feedback regulation voltage.
must be within the V
voltage range.
DD
DD
Note 9: Referred to LDO feedback regulation voltage.
I
IN
(V
- V
)
1V
R
INi + 1
INi
TEST
dR =
i
=
(I
- I
)
(I
- I
)
INi + 1 INi
INi + 1 INi
V
INi
I
= I
-
OFFSET INi
dR
i
1ms/10ms/100ms
MAX5988A
I
INi + 1
100V
EVALUATION
dR
i
BOARD
I
INi
I
OFFSET
V
IN
V
INi
1V
V
INi + 1
Figure 1. MAX5988A–MAX5988D Internal TVS Test Setup
Figure 2. Effective Differential Resistance and Offset Current
Maxim Integrated
│ 7
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
QUIESCENT CURRENT vs. SUPPLY
VOLTAGE (ULTRA-LOW POWER MODE)
SIGNATURE RESISTANCE
vs. SUPPLY VOLTAGE
DETECTION CURRENT vs. INPUT VOLTAGE
0.50
4.00
3.75
3.50
3.25
3.00
2.75
2.50
28
27
26
25
24
23
22
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1.4
2.9
4.4
5.9
7.4
8.9 10.1
35
40
45
50
55
60
1.4
2.9
4.4
5.9
7.4
8.9 10.1
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
CLASSIFICATION SETTLING TIME
MAX5988A toc06
3
2
25
23
21
19
17
15
13
11
9
CLASS2
CLASS1
V
DD
10V/div
1
GND
0
-1
-2
-3
I
DD
10mA/div
0mA
7
5
1.4
2.9
4.4
5.9
7.4
8.9 10.1
10
12
14
16
18
20
22
24
400µs/div
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
INRUSH CURRENT LIMIT vs. V VOLTAGE
LED CURRENT vs. R
LED CURRENT vs. LED VOLTAGE
CC
SL
60
56
52
48
44
40
28
24
20
18
12
8
25
20
15
10
5
R
= 30.2kI
SL
R
SL
= 60.4kI
0
6
12 18 24 30 36 42 48
(V)
10
20
30
40
R
50
60
70
80
0
1.75
3.50
5.25
7.00
V
(kI)
LED VOLTAGE (V)
CC
SL
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. LOAD CURRENT
(MAX5988A, V = 5V)
EFFICIENCY vs. LOAD CURRENT
(MAX5988B, V
= 12V)
OUT
OUT
100
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
V
= 36V
IN
V
= 48V
IN
V
= 12V
IN
V
= 36V
IN
V
= 57V
IN
V
IN
= 57V
V
= 48V
IN
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
LOAD CURRENT (A)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
LOAD CURRENT (A)
5V LOAD TRANSIENT
5V LOAD TRANSIENT
(50% TO 100%)
(0% TO 50%)
MAX5988A toc12
MAX5988A toc13
V
OUT
V
OUT
AC-COUPLED
50mV/div
AC-COUPLED
50mV/div
I
OUT
I
OUT
500mA/div
500mA/div
0A
0A
100µs/div
100µs/div
DC-DC CONVERTER STARTUP
DC-DC CONVERTER STARTUP
I
= 0A
R
= 6.67I
OUT
OUT
MAX5988A toc14
MAX5988A toc15
V
OUT
V
OUT
1V/div
1V/div
V
GND
V
GND
2ms/div
2ms/div
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Pin Configuration
TOP VIEW
15
14
13
12
11
ULP
SL
10
9
WAD 16
V
V
17
18
19
20
DD
CC
MAX5988A
MAX5988B
8
VDRV
GND
FB
PGND
RREF
7
*EP
+
6
1
2
3
4
5
TQFN
4mm × 4mm
*EXPOSED PAD, CONNECT EP TO GND.
Pin Description
PIN
NAME
FUNCTION
Auxiliary Voltage Input. Auxiliary input to the internal regulator, VDRV. Connect AUX to the output of
the buck converter, if the output voltage is greater than 4.75V, to back bias the internal circuitry and
increase efficiency. Connect to a clean ground when not used.
1
AUX
2
3
LX
Inductor Connection. Inductor connection for the internal DC-DC converter.
LED Driver Output. In sleep mode, LED sources a periodic current (I
cycle.
) at 250Hz with 25% duty
LED
LED
LDO Input Voltage. Connect LDO_IN to output when used; otherwise, connect to GND. Connect a
minimum 1FF bypass capacitor between LDO_IN and GND.
4
5
6
LDO_IN
LDO_OUT LDO Output Voltage. Connect a minimum 1FF output capacitor between LDO_OUT and GND.
Feedback. Feedback input for the DC-DC buck converter. Connect FB to a resistive divider from the
output to GND to adjust the output voltage.
FB
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Pin Description (continued)
PIN
NAME
FUNCTION
Ground. Reference rail for the device. It is also the “quiet” ground for all voltage references (e.g., FB is
referenced to this GND).
7
GND
Internal 5V Regulator Voltage Output. The internal voltage regulator provides 5V to the MOSFET driver
and other internal circuits. VDRV is referenced to GND. Do not use VDRV to drive external circuits.
Connect a 1FF bypass capacitor between VDRV and GND.
8
9
VDRV
Sleep Mode Enable Input. A falling edge on SL brings the device into sleep mode. An external resistor
SL
(R ) connected between SL and GND sets the LED current (I
).
SL
LED
Ultra-Low Power-Mode Enable Input. ULP has an internal 50kω pullup resistor to the internal 5V bias
rail. A falling edge on SL while ULP is asserted low enables ultra-low power mode. When ultra-low
power mode is enabled, the power consumption of the device is reduced even lower than sleep mode
to comply with ultra-low power sleep power requirements while still supporting MPS.
10
ULP
11
12
CLASS2
MPS
Class 2 Selection Pin. Connect to VDRV for Class 2 operation. Connect to GND for Class 1 operation.
MPS Enable Pin. Connect to VDRV to turn the MPS function on. Connect to GND to turn the MPS
function off.
Open-Drain RESET Output. The RESET output is driven low if either LDO_OUT or FB drops below
90% of its set value. RESET goes high 4.8ms after both LDO_OUT and FB rise above 95% of their set
values. Leave unconnected when not used.
13
RESET
LDO Regulator Feedback Input. Connect to VDRV to get the preset LDO output voltage of 3.3V, or
connect to a resistive divider from LDO_OUT to GND for an adjustable LDO output voltage.
14
15
LDO_FB
Wake Mode Enable Input. WK has an internal 50kω pullup resistor to the internal 5V bias rail. A falling
edge on WK brings the device out of sleep mode and into the normal operating mode (wake mode).
WK
Wall Power Adapter Detector Input. Wall adapter detection is enabled when the voltage from WAD
to GND is greater than 8.8V. When a wall power adapter is present, the isolation p-channel power
MOSFET turns off. Connect WAD through a 10kω resistor to GND when the wall power adapter or other
auxiliary power source is not used.
16
WAD
17
18
V
V
Positive Supply Input. Connect a 68nF (min) bypass capacitor between V
and PGND.
DD
DD
DC-DC Converter Power Input. V
is connected to V
by an isolation p-channel MOSFET. Connect a
DD
CC
CC
10FF capacitor in parallel with a 1FF ceramic capacitor between V
and PGND.
CC
Power Ground. Power ground of the DC-DC converter power stage. Connect PGND to GND with a star
connection. Do not use PGND as reference for sensitive feedback circuit.
19
PGND
20
—
RREF
EP
Signature Resistor Connection. Connect a 24.9kω resistor (R ) to GND.
SIG
Exposed Pad. Connect the exposed pad to GND.
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Detailed Description
cation current at 10.5mA (Class 1, CLASS1 = GND) or
18mA (Class 2, CLASS2 = VDRV). The PSE uses this to
determine the maximum power to deliver. The classifica-
tion current includes current drawn by the supply current
of the device so the total current drawn by the PD is with-
in the IEEE 802.3af standard. The classification current
is turned off when the device leaves classification mode.
PD Interface
The MAX5988A/MAX5988B include complete interface
functions for a PD to comply with the IEEE 802.3af stan-
dard as a Class 1/Class 2 PD. The devices provide the
detection and classification signatures using a single
external signature resistor. An integrated MOSFET pro-
vides isolation from the buck converter when the PSE has
not applied power. The devices guarantee a leakage cur-
rent offset of less than 10µA during the detection phase.
The devices feature power-mode undervoltage-lockout
(UVLO) with wide hysteresis and long deglitch time to
compensate for twisted-pair-cable resistive drop and to
ensure glitch-free transitions between detection, classifi-
cation, and power-on/-off modes.
Power Mode (V
> V
)
DD
In power mode, the devices have the isolation MOSFET
between V and V fully on. The devices have the
ON
DD
CC
buck regulator enabled and the LDO enabled. The
devices can be in either wake mode, sleep mode, or
ultra-low-power mode. The buck regulator and LDO are
only enabled in wake mode.
The devices enter power mode when V
rises above
DD
the undervoltage lockout threshold (V ). When V
ON
DD
Operating Modes
The devices operate in three different modes depending
rises above V , the device turns on the internal p-chan-
ON
nel isolation MOSFET to connect V
to V
with inrush
CC
DD
on V . The three modes are detection mode, classifica-
DD
current limit internally set to 49mA (typ). The isolation
MOSFET is fully turned on when V is near V and the
tion mode, and power mode. The device is in detection
CC
DD
mode when V
tion mode when V
power mode when the input voltage exceeds V
is between 1.4V and 10.1V, classifica-
DD
inrush current is below the inrush limit. Once the isola-
tion MOSFET is fully turned on, the device changes the
current limit to 321mA (typ). The buck converter turns on
123ms after the isolation MOSFET turns on fully.
is between 12.6V and 20V, and
DD
.
ON
Detection Mode (1.4V < V
DD
In detection mode, the devices provide a signature
differential resistance to V . During detection, the
power-sourcing equipment (PSE) applies two voltages to
< 10.1V)
Undervoltage Lockout
The devices operate with up to a 60V supply voltage
DD
with a turn-on UVLO threshold (V ) at 38.8V (typ), and
ON
OFF
V , both between 1.4V and 10.1V with a minimum 1V
DD
a turn-off UVLO threshold (V
) at 31.5V (typ). When
increment. The PSE computes the differential resistance
to ensure the presence of the 24.9kω signature resis-
the input voltage is above V , the device enters power
mode and the internal isolation MOSFET is turned on.
ON
tor. Connect the 24.9kω signature resistor (R ) from
RREF to GND for proper signature detection. The device
SIG
When the input voltage is below V
for more than
OFF
t
, the MOSFET and the buck converter are off.
OFF_DLY
applies V
to RREF when in detection mode, and the
DD
V
DD
offset current due to the device is less than 10µA.
LED Driver
The DC offset due to protection diodes does not signifi-
cantly affect the signature resistance measurement.
The devices drive an LED, or multiple LEDs in series, with
a maximum LED voltage of 6.5V. In sleep mode and ultra-
low-power mode, the LED current is pulse width modu-
lated with a duty cycle of 25% and the amplitude is set by
Classification Mode (12.6V < V
< 20V)
DD
In classification mode, the devices sink Class 1/Class 2
classification currents. The PSE applies a classification
voltage between 12.6V and 20V, and measures the clas-
sification currents. The devices use the external 24.9kω
R
. The LED driver current amplitude is programmable
SL
from 10mA to 20mA using R according to the formula:
SL
I
= 646/R (mA)
SL
LED
resistor (R ) and the CLASS2 pin to set the classifi-
SIG
where R is in kω.
SL
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Sleep and Ultra-Low-Power Modes
The application circuit must ensure that the auxiliary
power source can provide power to V
means of external diodes. The voltage on V
and V
by
The devices feature a sleep mode and an ultra-low-
power mode in which the internal p-channel isolation
MOSFET is kept on and the buck regulator is off. In sleep
mode, the LED driver output (LED) pulse width modu-
lates the LED current with a 25% duty cycle. The peak
DD
CC
must be
DD
within the V
voltage range to allow the DC-DC to oper-
DD
ate. To allow operation of the DC-DC converter, the V
DD
and V
voltage must be greater than 8V, on the rising
CC
edge, while on the falling edge the V
down to 7.7V keeping the DC-DC converter on.
and V
may fall
LED current (I
) is set by an external resistor R . To
DD
CC
LED
SL
enable sleep mode, apply a falling edge to SL with ULP
disconnected or high impedance. Sleep mode can only
be entered from wake mode.
Note: When operating solely with a wall power adapter,
the WAD voltage must be able to meet the condition V
> 8.8V, that likely results in WAD > 8.8V.
DD
Ultra-low-power mode allows the devices to reduce
power consumption lower than sleep mode, while main-
taining the power signature of the IEEE standard. The
ultra-low-power-mode enable input ULP is internally held
high with a 50kω pullup resistor to the internal 5V bias of
the device. To enable ultra-low-power mode, apply a fall-
ing edge to SL with ULP = LOW. Ultra-low-power mode
can only be entered from wake mode.
Internal Linear Regulator and Back Bias
An internal voltage regulator provides VDRV to internal
circuitry. The VDRV output is filtered by a 1µF capaci-
tor connected from VDRV to GND. The regulator is for
internal use only and cannot be used to provide power to
external circuits. VDRV can be powered by either V
or
DD
V
, depending on V
. The internal regulator is used
AUX
AUX
To exit from sleep mode or ultra-low-power mode and
resume normal operation, apply a falling edge on the
wake-mode enable input (WK).
for both PD and buck converter operations.
V
can be used to back bias the VDRV voltage regu-
OUT
lator if V
is greater than 4.75V. Back biasing VDRV
OUT
Thermal-Shutdown Protection
increases device efficiency by drawing current from
instead of V . If V is used as back bias,
V
If the devices’ die temperature reaches 151°C, an over-
temperature fault is generated and the device shuts
down. The die temperature must cool down below
+135°C to remove the overtemperature fault condition.
After a thermal shutdown condition clears, the device is
reset.
OUT
DD
OUT
OUT
connect AUX directly to V
VDRV source switches from V
converter’s output has reached its regulation voltage.
. In this configuration, the
to V
after the buck
DD
AUX
Cable Discharge Event Protection (CDE)
A 70V voltage clamp is integrated to protect the internal
circuits from a cable discharge event.
WAD Description
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD, the
devices feature wall power adapter detection.
DC-DC Buck Converter
The DC-DC buck converter uses a PWM, peak current-
mode, fixed-frequency control scheme providing an
easy-to-implement architecture without sacrificing a fast
transient response. The buck converter operates in a
wide input voltage range from 8.8V to 60V and supports
up to 6.49W of output power at 1.3A load. The devices
provide a wide array of protection features including
UVLO, overtemperature shutdown, short-circuit protec-
tion with hiccup runaway current limit, cycle-by-cycle
peak current protection, and cycle-by-cycle output over-
voltage protection, for enhanced performance and reli-
ability. A frequency foldback scheme is implemented to
reduce the switching frequency to half at light loads to
increase the efficiency.
The wall power adapter is connected from WAD to PGND.
The devices detect the wall power adapter when the volt-
age from WAD to PGND is greater than 8.8V. When a wall
power adapter is detected, the internal isolation MOSFET
is turned off, classification current is disabled.
Connect the auxiliar power source to WAD, connect a
diode from WAD to V , and connect a diode from WAD
DD
to V . See the typical application circuit in Figures 3
CC
and 4.
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Frequency Foldback Protection for
High-Efficiency Light-Load Operation
gives priority to the WAD supply over V
supply, and
DD
smoothly switches the power supply to WAD when it is
detected. The wall power adapter is connected from
WAD to PGND. The devices detect the wall power adapt-
er when the voltage from WAD to PGND is greater than
8.8V. When a wall power adapter is detected, the internal
isolation MOSFET is turned off, classification current is
disabled and the device draws power from the auxiliary
The devices enter frequency foldback mode when eight
consecutive inductor current zero-crossings occur. The
switching frequency is 215kHz under loads large enough
that the inductor current does not cross zero. In frequen-
cy foldback mode, the switching frequency is reduced to
107.5kHz to increase power conversion efficiency. The
device returns to normal mode when the inductor current
does not cross zero for eight consecutive switching peri-
ods. Frequency foldback mode is forced during startup
until 50% of the soft-start is completed.
power source through V . Connect the auxiliary power
CC
source to WAD, connect a diode from WAD to V . See
CC
the typical application circuit in Figures 3 and 4.
Adjusting LDO Output Voltage
Hiccup Mode
An uncommitted LDO regulator is available to provide
a supply voltage to external circuits. A preset voltage
of 3.3V is set by connecting LDO_FB directly to VDRV.
For different output voltages connect a resistor divider
from LDO_OUT and LDO_FB to GND. The total feed-
back resistance should be in the range of 100kω. The
minimum output current capability is 85mA and thermal
considerations must be taken to prevent triggering ther-
mal shutdown. The LDO regulator can be powered by
VOUT, a different power supply, or grounded when not
used. The LDO is enabled once the buck converter has
reached the regulation voltage. The LDO is disabled
when the buck converter is turned off or not regulating.
The devices include a hiccup protection feature. When
hiccup protection is triggered, the devices turn off the
high-side and turn on the low-side MOSFET until the
inductor current reaches the valley current limit. The
control logic waits 154ms until attempting a new soft-
start sequence. Hiccup mode is triggered if the current
in the high-side MOSFET exceeds the runaway current-
limit threshold, both during soft-start and during normal
operating mode. Hiccup mode can also be triggered in
normal operating mode in the case of an output under-
voltage event. This happens if the regulated feedback
voltage drops below 60% (typ).
RESET Output
Adjusting Buck Converter Output Voltage
The devices feature an open-drain RESET output that
indicates if either the LDO or the switching regulator drop
out of regulation. The RESET output goes low if either
regulator drops below 90% of its regulated feedback
value. RESET goes high impedance 4.8ms after both
regulators are above 95% of their value.
The buck converter output voltage is set by changing
the feedback resistor-divider ratio. The output voltage
can be set from 3.0V to 5.6V (MAX5988A) or 5.4V to
14V (MAX5988B). The FB voltage is regulated to 1.227V.
Keep the trace from the FB pin to the center of the resis-
tive divider short, and keep the total feedback resistance
around 10kω.
Maintain Power Signature (MPS)
The devices feature the MPS to comply with the IEEE
802.3af standard. It is able to maintain a minimum current
(10mA) of the port to avoid the power disconnection from
the PSE. The devices enter MPS mode when the port
current is lower than 14mA and also exit the MPS mode
when the port current is greater than 40mA. The feature is
enabled by connecting the MPS pin to VDRV, or disabled
by connecting the MPS pin to GND.
Inductor Selection
Choose an inductor with the following equation:
V
× V
− V
OUT
(
)
OUT
× V
CC
× L × I
L =
f
S
CC
IR
OUT MAX
(
)
where L is the ratio of the inductor ripple current to
IR
full load current at the minimum duty cycle. Choose L
IR
between 20% to 40% for best performance and stability.
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the devices.
Applications Information
Operation with Wall Adapter
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD, the
devices feature wall power adapter detection. The device
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
V
Input Capacitor Selection
where the output ripple due to output capacitance, ESR,
and ESL is:
CC
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching noise
in the IC. The total input capacitance must be equal or
greater than the value given by the following equation
to keep the input-ripple voltage within specification and
minimize the high-frequency ripple current being fed
back to the input source:
I
P−P
V
=
RIPPLE(C)
8× C
× f
S
OUT
V
= I
× ESR
RIPPLE(ESR)
P−P
I
P−P
V
=
× ESL
RIPPLE(ESL)
t
ON
D × T × I
S
OUT
or
C
=
IN_MIN
V
IN−RIPPLE
I
P−P
V
=
× ESL
RIPPLE(ESL)
t
OFF
where V
is the maximum allowed input ripple
IN-RIPPLE
voltage across the input capacitors and is recommended
to be less than 2% of the minimum input voltage. D is the
or whichever is larger. The peak-to-peak inductor current
(I
)
P-P
duty cycle (V
/V ) and T is the switching period (1/f ).
OUT IN
S S
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
V
V
OUT
CC − VOUT
I
=
×
P−P
f × L
V
S
CC
Use these equations for initial output capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current is
a factor of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capaci-
tors for low ESR and low ESL at the switching frequency
of the converter. The ripple voltage due to ESL is negli-
gible when using ceramic capacitors.
V
× V
V
OUT
(
)
OUT
CC
I
= I
×
LOAD
RIPPLE
IN
where I
is the input RMS ripple current.
RIPPLE
Output Capacitor Selection
Load-transient response depends on the selected output
capacitance. During a load transient, the output instantly
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored in
the output capacitor, the voltage drop due to the capaci-
tor’s ESR, and the voltage drop due to the capacitor’s
ESL. Estimate the output-voltage ripple due to the output
capacitance, ESR, and ESL:
changes by ESR x I
. Before the controller can
LOAD
respond, the output deviates further, depending on the
inductor and output capacitor values. After a short time,
the controller responds by regulating the output voltage
back to its predetermined value. The controller response
time depends on the closed-loop bandwidth. A higher
bandwidth yields a faster response time, preventing the
output from deviating further from its regulating value.
V
= V
+ V
+V
RIPPLE
RIPPLE(C)
RIPPLE(ESR) RIPPLE(ESL)
Table 1. Design Selection Table
C
C
OUTPUT
(V)
IN
OUT
L
CLASS
CERAMIC
2.2FF/100V
2.2FF/100V
2.2FF/100V
ELECTROLYTIC
10FF/63V
CERAMIC
1 x 100FF/6.3V
1 x 100FF/6.3V
2 x 10FF/16V
3.3
5
33FH/1.4A
47FH/1.6A
220FH/0.8A
1
10FF/63V
1 or 2
1 or 2
12
10FF/63V
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
PCB Layout
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX5988A EV kit layout for optimum performance. If
deviation is necessary, follow these guidelines for good
PCB layout:
4) Connect V , V , and PGND separately to a large
DD CC
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and direct.
Place the feedback resistors and compensation com-
ponents as close as possible to the IC.
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the sig-
nal ground plane.
6) Route high-speed switching nodes, such as LX, away
from sensitive analog areas (FB).
2) Place capacitors on V , V , AUX, VDRV as close
DD CC
as possible to the IC and its corresponding pin using
direct traces. Keep power ground plane (connected
to PGND) and signal ground plane (connected to
GND) separate.
7) Place enough vias in the pad for the EP of the devices
so that heat generated inside can be effectively dis-
sipated by the PCB copper. The recommended spac-
ing for the vias is 1mm to 1.2mm pitch. The thermal
vias should be plated (1oz copper) and have a small
barrel diameter (0.3mm to 0.33mm).
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Application Circuits
C2
2.2µF
C1
68nF
RJ45 AND
BRIDGE
10µF
RECTIFIER
V
V
WAD
DD
CC
AUX
VDRV
L0
47µH
CLASS2
MPS
5V
OUTPUT
C3
1µF
LX
LDO_FB
C4
100µF
R1
7.5kI
WK
ULP
SL
MAX5988A
MAX5988B
TO µP OPEN-DRAIN OUTPUTS
OR PULLDOWN SWITCHES
FB
R2
2.49kI
R
SL
60.4kI
3.3V
TO 5V OUTPUTS
LDO_IN
RREF
LDO_OUT
OUTPUT
C5
1µF
C6
1µF
LED
R
SIG
24.9kI
GND
PGND
0I
Figure 3. MAX5988A/MAX5988B Buck Regulator and Fixed LDO Output
Maxim Integrated
│ 17
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Typical Application Circuits (continued)
C2
2.2µF
C1
68nF
RJ45 AND
BRIDGE
10µF
RECTIFIER
V
V
WAD
DD
CC
AUX
VDRV
CLASS2
MPS
L0
47µH
5V
OUTPUT
C3
1µF
LX
R1
7.5kI
C4
100µF
WK
ULP
SL
MAX5988A
MAX5988B
TO µP OPEN-DRAIN OUTPUTS
OR PULLDOWN SWITCHES
FB
R2
2.49kI
R
SL
60.4kI
ADJ_LDO_OUT
LDO_OUT
LDO_FB
R3
R4
C6
1µF
TO 5V OUTPUTS
LDO_IN
RREF
C5
1µF
LED
GND
PGND
R
SIG
24.9kI
0I
Figure 4. MAX5988A/MAX5988B Buck Regulator and Adjustable LDO Output
Maxim Integrated
│ 18
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Functional Diagram
MAX5988A
MAX5988B
V
V
DD
CC
5V
TVS
HOT-SWAP
CONTROLLER
DETECTION
GND
CLASSIFICATION
5V
RREF
WAD
PD VOLTAGE
MONITOR
AUX
5V
5V
5V
1.5V
VDRV
1
0
5V
REGULATOR
CLK
LX
BANDGAP
CONTROL
DRIVER
V
REF
LDO_IN
VREF
LDO_OUT
LDO
PGND
FB
LDO_FB
OPEN DRAIN
RESET
V
5V
DD
V
DD
CLASS2
MPS
50kI
50kI
CLASS
WK
SL
MPS
LOGIC
ULP
LED
Maxim Integrated
│ 19
www.maximintegrated.com
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
CODE
NO.
20 TQFN-EP
T2044+4
21-0139
90-0409
Ordering Information/Selector Guide
SLEEP/ULP
OUTPUT
(V)
ADJ
PART
PIN-PACKAGE
LDO
UVLO (V)
RESET
MPS/CLASS2
MODE
MAX5988AETP+
MAX5988BETP+
20 TQFN-EP*
20 TQFN-EP*
Yes
Yes
Yes
38.8
38.8
Yes
Yes
Yes
Yes
3 to 5.6
Yes
5.4 to 14
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Maxim Integrated
│ 20
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MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
3
11/12
1/13
4/14
1/15
Initial release
—
20
11
1
Corrected land pattern number
Updated pin 16 in Pin Description table
Updated Benefits and Features section
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 21
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Maxim Integrated
│ 22
www.maximintegrated.com
MAX5988A/MAX5988B
IEEE 802.3af-Compliant, High-Efficiency,
Class 1/Class 2, Powered Devices
with Integrated DC-DC Converter
Maxim Integrated
│ 23
www.maximintegrated.com
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