MAX6303CSA [MAXIM]
+5V, Low-Power uP Supervisory Circuits with Adjustable Reset/Watchdog; + 5V ，低功耗高达监控电路，带有可调复位/看门狗
| 型号： | MAX6303CSA |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | +5V, Low-Power uP Supervisory Circuits with Adjustable Reset/Watchdog |
| 文件： | 总12页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1078; Rev 0; 6/96
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
1–MAX6304
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Adjustable Reset Threshold
The MAX6301/MAX6302/MAX6303/MAX6304* low-
power microprocessor (µP) supervisory circuits provide
maximum adjustability for reset and watchdog functions.
The reset threshold can be adjusted to any voltage
above 1.22V, using external resistors. In addition, the
reset and watchdog timeout periods are adjustable
us ing e xte rna l c a p a c itors . A wa tc hd og s e le c t p in
extends the watchdog timeout period to 500x. The reset
function features immunity to power-supply transients.
♦ Adjustable Reset Timeout
♦ Adjustable Watchdog Timeout
♦ 500x Watchdog Timeout Multiplier
♦ 4µA Supply Current
RESET Output Options
♦ RESET or
♦ Push/Pull or Open-Drain Output Options
♦ Guaranteed RESET Asserted At or Above
These four devices differ only in the structure of their reset
outputs (see Selector Guide). The MAX6301–MAX6304
are available in the space-saving 8-pin µMAX package,
as well as 8-pin DIP/SO.
V
= 1V (MAX6301/MAX6303)
CC
♦ Power-Supply Transient Immunity
♦ Watchdog Function Can Be Disabled
♦ DIP/SO/µMAX Packages Available
________________________Ap p lic a t io n s
Medical Equipment
Intelligent Instruments
Portable Equipment
Embedded Controllers
Critical µP Monitoring
Set-Top Boxes
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 Plastic DIP
8 SO
Battery-Powered
Computers/Controllers
Computers
MAX6301CPA
MAX6301CSA
MAX6301CUA
MAX6301EPA
MAX6301ESA
_____________________S e le c t o r Gu id e
8 µMAX
8 Plastic DIP
8 SO
FEATURE
MAX6301 MAX6302 MAX6303 MAX6304
Active-Low
Reset
✓
✓
—
✓
✓
—
Ordering Information continued at end of data sheet.
Active-High
Reset
✓
—
—
—
✓
__________Typ ic a l Op e ra t in g Circ u it
Open-Drain
Reset Output
✓
—
V
IN
MAX6301
ONLY
Push/Pull
Reset Output
✓
—
—
8-DIP/SO/ 8-DIP/SO/ 8-DIP/SO/ 8-DIP/SO/
µMAX µMAX µMAX µMAX
R1
Pins-Package
1
2
8
7
R
L
V
RESET IN
GND
CC
0.1µF
R2
__________________P in Co n fig u ra t io n
RESET
(RESET)
RESET
TOP VIEW
µP
V
RESET IN
GND
MAX6301
R
L
1
2
3
4
8
7
6
5
CC
MAX6302
ONLY
MAX6302
MAX6303
MAX6304
3
4
WDI
6
5
RESET (RESET)
WDI
SRT
I/O
MAX6301
MAX6302
MAX6303
MAX6304
SWT
WDS
SRT
C
SRT
C
SWT
WDS
SWT
WDS = 0 FOR NORMAL MODE
WDI = 1 FOR EXTENDED MODE
DIP/SO/µMAX
( ) ARE FOR MAX6302/MAX6304.
( ) ARE FOR MAX6302/MAX6304.
* Patents pending
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
ABSOLUTE MAXIMUM RATINGS
V
CC
.......................................................................-0.3V to +7.0V
Continuous Power Dissipation (T = +70°C)
A
RESET IN, SWT, SRT..................................-0.3V to (V + 0.3V)
WDI, WDS..............................................................-0.3V to +7.0V
RESET, RESET
Plastic DIP (derate 9.09mW/°C above +70°C) ............727mW
SO (derate 5.88mW/°C above +70°C).........................471mW
µMAX (derate 4.10mW/°C above +70°C) ....................330mW
Operating Temperature Ranges
CC
MAX6301 ...........................................................-0.3V to +7.0V
MAX6302/6303/6304 ..............................-0.3V to (V + 0.3V)
Input Current
MAX630_C_A......................................................0°C to +70°C
MAX630_E_A ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
CC
V
CC
...............................................................................±20mA
GND..............................................................................±20mA
Output Current
RESET, RESET..............................................................±20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2V to +5.5V, T = T
to T , unless otherwise noted. Typical values are at V = +5V and T = +25°C.)
MAX CC A
CC
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MAX6301C/MAX6303C
MIN
1.00
1.20
1.31
TYP
MAX
5.50
5.50
5.50
7.0
UNITS
V
1–MAX6304
Operating Voltage Range
(Note 1)
V
CC
MAX6301E/MAX6303E
MAX6302/MAX6304
No load
Supply Current (Note 2)
I
CC
4.0
µA
RESET TIMER
V
falling, V = 5.0V
1.195
1.220
1.240
20
1.245
1.265
RESET IN
CC
Reset Input Threshold Voltage
V
V
TH
V
rising, V = 5.0V
CC
RESET IN
Reset Input Hysteresis
V
HYST
mV
nA
Reset Input Leakage Current
I
±0.01
±1
RESET IN
V
≥ 4.5V, I
= 0.8mA
V
- 0.4
CC
SOURCE
CC
Reset Output Voltage High
(MAX6302/MAX6303/MAX6304)
V
OH
V
CC
= 2V, I = 0.4mA
SOURCE
VCC - 0.4
V
MAX6302/MAX6304, V = 1.31V, R = 10kΩ
V
CC
- 0.3
CC
L
V
≥ 4.5V, I
= 3.2mA
0.4
0.4
CC
SINK
V
CC
= 2V, I
= 1.6mA
SINK
Reset Output Voltage Low
(MAX6301/MAX6303/MAX6304)
V
= 1V, I
= 50µA,
CC
SINK
V
OL
0.3
0.3
V
T = 0°C to +70°C
A
MAX6301/
MAX6303
V
= 1.2V, I
= -40°C to +85°C
= 100µA,
CC
SINK
T
A
V
to Reset Delay
t
t
V
falling at 1mV/µs
63
26
µs
µs
CC
RD
CC
Reset Input Pulse Width
t
Comparator overdrive = 50mV
= 1500pF
RI
Reset Timeout Period (Note 3)
C
2.8
4.0
5.2
±1
±1
ms
RP
SRT
MAX6301, V
MAX6302, V
= V
CC
RESET
Reset Output Leakage Current
µA
= GND
RESET
2
_______________________________________________________________________________________
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
1–MAX6304
ELECTRICAL CHARACTERISTICS (continued)
(V = +2V to +5.5V, T = T
to T , unless otherwise noted. Typical values are at V = +5V and T = +25°C.)
MAX CC A
CC
A
MIN
PARAMETER
WATCHDOG TIMER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0.7V
CC
IH
WDI, WDS Input Threshold
WDI Pulse Width
V
V
IL
0.3V
CC
V
= 4.5V to 5.5V
30
60
CC
t
ns
WP
V
CC
= 2V to 4.5V
WDI, WDS Leakage Current
Extended mode disabled
±1
µA
µA
WDI Sink/Source Current
(Note 4)
Extended mode enabled
±70
WDS = GND, C
= 1500pF
2.8
1.4
4.0
2.0
5.2
2.6
ms
SWT
Watchdog Timeout Period
(Note 3)
t
WD
WDS = V , C
= 1500pF
SWT
sec
CC
Note 1: Reset is guaranteed valid from the selected reset threshold voltage down to the minimum V
.
CC
Note 2: VDS = V , WDI unconnected.
CC
Note 3: Precision timing currents of 500nA are present at both the SRT and SWT pins. Timing capacitors connected to these nodes
must have low leakage consistent with these currents to prevent timing errors.
Note 4: The sink/source is supplied through a resistor, and is proportional to V (Figure 8). At V = 2V, it is typically ±24µA.
CC
CC
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(C
= C
= 1500pF, T = +25°C, unless otherwise noted.)
SRT A
SWT
NORMAL-MODE
EXTENDED-MODE
WATCHDOG TIMEOUT PERIOD vs. C
WATCHDOG TIMEOUT PERIOD vs. C
RESET TIMEOUT PERIOD
vs. C
SWT
SWT
(WDS = GND)
(WDS = V )
CC
SRT
10,000
10,000
10,000
V
CC
= 5V
V
CC
= 5V
V
CC
= 5V
1000
100
10
1000
100
10
1000
100
10
1
1
1
0.1
0
0
0.001 0.01
0.1
1
10
100 1000
0.001 0.01
0.1
1
10
100 1000
0.001 0.01
0.1
1
10
100 1000
C
SWT
(nF)
C
SWT
(nF)
C
SRT
(nF)
_______________________________________________________________________________________
3
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(C
= C
= 1500pF, T = +25°C, unless otherwise noted.)
SRT A
SWT
RESET AND NORMAL-MODE
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
SUPPLY CURRENT vs.
SUPPLY VOLTAGE
MAXIMUM TRANSIENT DURATION vs.
RESET THRESHOLD OVERDRIVE (V
)
RST
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
4.20
4.15
4.10
4.05
4.00
3.95
3.90
3.85
120
110
100
90
SEE NEGATIVE-GOING V
RESET DEASSERTED
NO LOAD
CC
V
= 5.0V
CC
TRANSIENTS SECTION
RESET OCCURS
ABOVE THE CURVE
80
70
60
50
40
30
20
10
0
V
RST
= 4.60V
2.6
3.80
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
-60 -40 -20
0
20 40 60 80 100
0
200
400
600
800
1000
1–MAX6304
TEMPERATURE (°C)
RESET THRESHOLD OVERDRIVE (mV)
SUPPLY CURRENT
vs. TEMPERATURE
RESET IN THRESHOLD VOLTAGE
vs. TEMPERATURE
5.00
1.226
RESET DEASSERTED
NO LOAD
4.75
1.224
1.222
1.220
4.50
4.25
V
= 5.0V
= 2.0V
CC
4.00
3.75
3.50
3.25
3.00
2.75
2.50
1.218
1.216
1.214
V
CC
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
V
TO RESET DELAY
RESET AND WATCHDOG
TIMEOUT vs. V
CC
vs. TEMPERATURE (V FALLING)
CC
CC
76
72
68
64
60
56
4.16
4.12
4.08
4.04
4.00
3.96
V
CC
FALLING AT 1mV/µs
52
-60 -40 -20
0
20 40 60 80 100
2
3
4
5
6
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
1–MAX6304
______________________________________________________________P in De s c rip t io n
PIN
NAME
RESET IN
GND
FUNCTION
Reset Input. High-impedance input to the reset comparator. Connect this pin to the center point of an
external resistor voltage-divider network to set the reset threshold voltage. The reset threshold voltage
1
is calculated as follows: V
= 1.22 x (R1 + R2) / R2 (see Typical Operating Circuit).
RST
2
Ground
Set Reset-Timeout Input. Connect a capacitor between this input and ground to select the reset timeout
3
SRT
period (t ). Determine the period as follows: t = 2.67 x C
, with C
SRT
in pF and t in µs (see
SRT RP
RS
RP
Typical Operating Circuit).
Set Watchdog-Timeout Input. Connect a capacitor between this input and ground to select the basic
watchdog timeout period (t ). Determine the period as follows: t = 2.67 x C , with C in pF
4
5
SWT
WDS
WD
WD
SWT
SWT
and t
in µs. The watchdog function can be disabled by connecting this pin to ground.
WD
Watchdog-Select Input. This input selects the watchdog mode. Connect to ground to select normal mode
and the basic watchdog timeout period. Connect to V to select extended mode, multiplying the basic
CC
timeout period by a factor of 500. A change in the state of this pin resets the watchdog timer to zero.
Watchdog Input. A rising or falling transition must occur on this input within the selected watchdog
timeout period, or a reset pulse will occur. The capacitor value selected for SWT and the state of WDS
determine the watchdog timeout period. The watchdog timer clears and restarts when a transition
occurs on WDI or WDS. The watchdog timer is cleared when reset is asserted and restarted after reset
6
WDI
deasserts. In the extended watchdog mode (WDS = V ), the watchdog function can be disabled by
CC
driving WDI with a three-stated driver or by leaving WDI unconnected.
RESET changes from high to low whenever the monitored voltage
Open-Drain, Active-Low Reset
Output (MAX6301)
(V ) drops below the selected reset threshold (V ). RESET
IN
RST
RESET
remains low as long as V is below V . Once V exceeds V
,
IN
RST
IN
RST
(MAX6301/3)
RESET remains low for the reset timeout period and then goes high.
The watchdog timer triggers a reset pulse (t ) whenever the watch-
dog timeout period (t ) is exceeded.
WD
Push/Pull, Active-Low Reset
Output (MAX6303)
RP
7
8
RESET changes from low to high whenever the monitored voltage
Open-Drain, Active-High Reset
Output (MAX6302)
(V ) drops below the selected reset threshold (V ). RESET
IN
RST
RESET
(MAX6302/4)
remains high as long as V is below V . Once V exceeds V
,
IN
RST
IN
RST
RESET remains high for the reset timeout period and then goes low.
The watchdog timer triggers a reset pulse (t ) whenever the watch-
Push/Pull, Active-High Reset
Output (MAX6304)
RP
dog timeout period (t ) is exceeded.
WD
V
CC
Supply Voltage
_______________________________________________________________________________________
5
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
_______________De t a ile d De s c rip t io n
V
IN
Re s e t Fu n c t io n /Ou t p u t
The reset output is typically connected to the reset
input of a microprocessor (µP). A µP’s reset input starts
or restarts the µP in a known state. The MAX6301–
MAX6304 µP supervisory circuits provide the reset
logic to prevent code-execution errors during power-
up, power-down, and brownout conditions (see Typical
Operating Circuit).
R1
R2
RESET IN
V
CC
0.1µF
MAX6301
MAX6302
MAX6303
MAX6304
For the MAX6301/MAX6303, RESET changes from high
to low whenever the monitored voltage (V ) drops
IN
b e low the re s e t thre s hold volta g e (V
). RESET
RST
remains low as long as V is below V
. Once V
R1 + R2
R2
IN
RST
IN
V
RST
= 1.22
(
)
exceeds V , RESET remains low for the reset timeout
RST
period, then goes high. When a reset is asserted due to
a watchdog timeout condition, RESET stays low for the
reset timeout period. Anytime reset asserts, the watch-
dog timer clears. At the end of the reset timeout period,
RESET goes high and the watchdog timer is restarted
from zero. If the watchdog timeout period is exceeded
again, then RESET goes low again. This cycle contin-
ues unless WDI receives a transition.
Figure 1. Calculating the Reset Threshold Voltage (V
)
RST
1–MAX6304
R2 can have very high values to minimize current con-
sumption. Set R2 to some conveniently high value (1MΩ,
for example) and calculate R1 based on the desired
reset threshold voltage, using the following formula:
On power-up, once V reaches 1V, RESET is guaran-
CC
VRST
teed to be a logic low. For information about applica-
R1 = R2 ×
−1
Ω
( )
tions whe re V
is le s s tha n 1V, s e e the s e c tion
V
CC
TH
Ensuring a Valid RESET/RESET Output Down to V
=
CC
0V (MAX6303/MAX6304). As V rises, RESET remains
CC
Wa t c h d o g Tim e r
The watchdog circuit monitors the µP’s activity. If the µP
does not toggle the watchdog input (WDI) within t
(user selected), reset asserts. The internal watchdog
timer is cleared by reset, by a transition at WDI (which
can detect pulses as short as 30ns), or by a transition
at WDS. The watchdog timer remains cleared while
reset is asserted; as soon as reset is released, the timer
starts counting (Figure 2).
low. When V rises above V , the reset timer starts
IN
RST
and RESET remains low. When the reset timeout period
ends, RESET goes high.
WD
On power-down, once V goes below V
goes low and is guaranteed to be low until V droops
, RESET
CC
IN
RST
below 1V. For information about applications where
V
CC
is less than 1V, see the section Ensuring a Valid
RESET/RESET Output Down to V
= 0V (MAX6303/
CC
MAX6304).
The MAX6301–MAX6304 feature two modes of watch-
dog timer operation: normal mode and extended mode.
In normal mode (WDS = GND), the watchdog timeout
period is determined by the value of the capacitor con-
ne c te d b e twe e n SWT a nd g round (s e e the s e c tion
Selecting the Reset and Watchdog Timeout Capacitor).
The MAX6302/MAX6304 active-high RESET output is
the inve rs e of the MAX6301/MAX6303 a c tive -low
RESET output, and is guaranteed valid for V > 1.31V.
CC
Re s e t Th re s h o ld
These supervisors monitor the voltage on RESET IN.
The MAX6301–MAX6304 ha ve a n a d jus ta b le re s e t
In extended mode (WDS = V ), the watchdog timeout
CC
period is multiplied by 500. For example, in the extend-
ed mode, a 1µF capacitor gives a watchdog timeout
period of 22 minutes (see the graph Extended-Mode
threshold voltage (V ) set with an external resistor
RST
voltage divider (Figure 1). Use the following formula to
calculate V (the point at which the monitored volt-
Wa tc hd og Time out Pe riod vs . C
Operating Characteristics).
in the Typ ic a l
RST
SWT
age triggers a reset):
V
× R1+ R2
(
)
V
TH
In extended mode, the watchdog function can be dis-
abled by leaving WDI unconnected or by three-stating
the driver connected to WDI. In this mode, the watch-
dog input is internally driven low during the watchdog
V
( )
RST =
R2
where V
is the desired reset threshold voltage and
RST
V
TH
is the reset input threshold (1.22V). Resistors R1 and
6
_______________________________________________________________________________________
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
1–MAX6304
V
CC
t
t
RP
WD
WDI
0V
V
CC
RESET
0V
NORMAL MODE (WDS = GND)
Figure 2a. Watchdog Timing Diagram, WDS = GND
V
CC
t
x 500
t
RP
WD
WDI
0V
V
CC
RESET
0V
EXTENDED MODE (WDS = V
)
CC
Figure 2b. Watchdog Timing Diagram, WDS = V
CC
timeout period, then momentarily pulses high, resetting
the watchdog counter. When WDI is left unconnected,
the watchdog timer is cleared by this internal driver just
before the timeout period is reached (the internal driver
V
CC
V
CC
GND
pulls WDI high at about 94% of t
). When WDI is
WD
MAX6301
MAX6302
MAX6303
MAX6304
three-stated, the maximum allowable leakage current of
the device driving WDI is 10µA.
0.1µF
SRT
In normal mode (WDS = GND), the watchdog timer
cannot be disabled by three-stating WDI. WDI is a
high-impedance input in this mode. Do not leave WDI
unconnected in normal mode.
SWT
C
SRT
C
SWT
t
t
WD
2.67
RP
C
RST
=
C
SWT
=
2.67
C
RST
in pF
C
SWT
in pF
t
in µs
t
in µs
WD
WD
Figure 3. Calculating the Reset (C
) and Watchdog
SRT
(C
) Timeout Capacitor Values
SWT
_______________________________________________________________________________________
7
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
V
IN
V
CC
V
CC
V
CC
80C51
R1
R2
MAX6302
V
CC
V
CC
RESET IN
V
CC
RST
RESET
*
0.1µF
MAX6301
WDI
I/O
I/O
I/O
MAX6302
MAX6303
MAX6304
WDS
GND
GND
R1 + R2
R2
V
RST
= 1.22
(
)
* THREE-STATE LEAKAGE MUST BE <10µA.
Figure 4. Monitoring a Voltage Other than V
Figure 5. Wake-Up Timer
CC
1–MAX6304
Wa k e -Up Tim e r
__________Ap p lic a t io n s In fo rm a t io n
In some applications, it is advantageous to put a µP
into sleep mode, periodically “wake it up” to perform
checks and/or tasks, then put it back into sleep mode.
The MAX6301 family supervisors can easily accommo-
date this technique. Figure 5 illustrates an example
using the MAX6302 and an 80C51.
S e le c t in g t h e Re s e t a n d
Wa t c h d o g Tim e o u t Ca p a c it o r
The reset timeout period is adjustable to accommodate
a variety of µP applications. Adjust the reset timeout
period (t ) by connecting a specific value capacitor
RS
(C
) between SRT and ground (Figure 3). Calculate
SRT
In Figure 5, just before the µC puts itself into sleep
mode, it pulls WDS high. The µC’s I/O pins maintain
their logic levels while in sleep mode and WDS remains
high. This places the MAX6302 in extended mode,
increasing the watchdog timeout 500 times. When the
watchdog timeout period ends, a reset is applied on
the 80C51, “waking it up” to perform tasks. While the µP
is performing tasks, the 80C51 pulls WDS low (select-
ing normal mode), and the MAX6302 monitors the µP
for hang-ups. When the µP finishes its tasks, it puts
its e lf b a c k into s le e p mod e , d rive s WDS hig h, a nd
starts the cycle over again. This is a power-saving tech-
nique, since the µP is operating only part of the time
and the MAX6302 has very low quiescent current.
the reset timeout capacitor as follows:
C
= t ⁄ 2.67
SRT
RP
with C
in pF and t in µs. C
must be a low-leak-
SRT
SRT
RP
age (<10nA) type capacitor. Ceramic is recommended.
The watchdog timeout period is adjustable to accom-
modate a variety of µP applications. With this feature,
the watchdog timeout can be optimized for software
execution. The programmer can determine how often
the watchdog timer should be serviced. Adjust the
watchdog timeout period (t ) by connecting a specif-
WD
ic value capacitor (C
) between SWT and ground
SWT
(Figure 3). For normal-mode operation, calculate the
watchdog timeout capacitor as follows:
Ad d in g a Ma n u a l Re s e t Fu n c t io n
A manual reset option can easily be implemented by
connecting a normally open momentary switch in paral-
lel with R2 (Figure 6). When the switch is closed, the
voltage on RESET IN goes to zero, initiating a reset.
When the switch is released, reset remains asserted for
the reset timeout period and then is cleared. The push-
button switch is effectively debounced by the reset
timer.
C
= t
⁄ 2.67
WD
SWT
where C
is in pF and t
is in µs. C
must be a
SRT
SWT
WD
low leakage (<10nA) type capacitor. Ceramic is recom-
mended.
Mo n it o rin g Vo lt a g e s Ot h e r t h a n V
The Typical Operating Circuit monitors V . However,
monitoring other voltages is simple, and Figure 4 shows
a circuit that accomplishes this. Calculate V
shown in the Reset Threshold section.
CC
CC
as
RST
8
_______________________________________________________________________________________
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
1–MAX6304
RESET TO
OTHER SYSTEM
COMPONENTS
V
CC
V
CC
V
CC
R1
R2
µP
MAX6301
RESET IN
V
CC
V
CC
0.1µF
0.1µF
4.7k
MAX6301
GND
MAX6302
MAX6303
MAX6304
RESET
RESET
Figure 6. Adding a Manual Reset Function
Figure 7. Interfacing to µPs with Bidirectional Reset I/O Pins
In t e rfa c in g t o µP s w it h
Bid ire c t io n a l Re s e t P in s
Since RESET is open-drain, the MAX6301 interfaces
easily with µPs that have bidirectional reset pins, such
as the Motorola 68HC11 (Figure 7). Connecting RESET
directly to the µP’s reset pin with a single pull-up allows
either device to assert reset.
TO RESET
GENERATOR
WDI
WATCHDOG
TIMER
Ne g a t ive -Go in g V
Tra n s ie n t s
CC
In addition to issuing a reset to the µP during power-up,
power-down, and brownout conditions, these supervisors
are relatively immune to short-duration negative-going
transients (glitches). The graph Maximum Transient
Duration vs. Reset Threshold Overdrive in the Typical
Operating Characteristics shows this relationship.
MAX6301
MAX6302
MAX6303
MAX6304
WDS
TO MODE
CONTROL
The area below the curves of the graph is the region in
which these devices typically do not generate a reset
pulse. This graph was generated using a negative-
Figure 8. Watchdog Input Structure
going pulse applied to V , starting above the actual
IN
watchdog timeout period by a very brief low-high-low
pulse from the counter chain. For minimum watchdog
input current (minimum overall power consumption),
leave WDI low for the majority of the watchdog timeout
period, pulsing it low-high-low (>30ns) once within the
period to reset the watchdog timer. If instead WDI is
externally driven high for the majority of the timeout
period, typically 70µA can flow into WDI.
reset threshold (V ) and ending below it by the mag-
RST
nitude indicated (reset-threshold overdrive). As the
magnitude of the transient increases (farther below the
reset threshold), the maximum allowable pulse width
decreases. Typically, a V transient that goes 100mV
CC
below the reset threshold and lasts 50µs or less will not
cause a reset pulse to be issued.
Wa t c h d o g In p u t Cu rre n t
Normal Mode
In normal mode (WDS = GND), the internal buffer that
drives WDI is disabled. In this mode, WDI is a standard
CMOS input and leakage current is typically 100pA,
regardless of whether WDI is high or low.
Extended Mode
In extended mode (WDS = V ), the WDI input is inter-
nally driven through a buffer and series resistor from
the wa tc hdog c ounte r (Figure 8). Whe n WDI is le ft
unconnected, the watchdog timer is serviced within the
CC
_______________________________________________________________________________________
9
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
V
CC
V
CC
100k
MAX6303
MAX6304
V
CC
V
CC
0.1µF
100k
0.1µF
RESET
RESET
GND
GND
Figure 10. Ensuring RESET Valid to V = 0V
CC
Figure 9. Ensuring RESET Valid to V = 0V
CC
En s u rin g a Va lid RESET/RES ET Ou t p u t
1–MAX6304
Do w n t o V
= 0 V (MAX6 3 0 3 /MAX6 3 0 4 )
CC
When V
falls below 1V, RESET/RESET current sink-
START
CC
ing (sourcing) capabilities decline drastically. In the
case of the MAX6303, high-impedance CMOS-logic
inputs connected to RESET can drift to undetermined
voltages. This presents no problem in most applica-
tions, since most µPs and other circuitry do not operate
SET WDI
LOW
with V below 1V.
CC
SUBROUTINE OR
PROGRAM LOOP
SET WDI HIGH
In those applications where RESET must be valid down
to 0V, adding a pull-down resistor between RESET and
g round s inks a ny s tra y le a ka g e c urre nts , hold ing
RESET low (Figure 9). The value of the pull-down resis-
tor is not critical; 100kΩ is large enough not to load
RESET and small enough to pull RESET to ground. For
applications using the MAX6304, a 100kΩ pull-up resis-
RETURN
END
tor between RESET and V will hold RESET high when
CC
V
CC
falls below 1V (Figure 10).
Wa t c h d o g -S o ft w a re Co n s id e ra t io n s
To help the watchdog timer monitor software execution
more closely, set and reset the watchdog input at differ-
ent points in the program, rather than “pulsing” the
watchdog input high-low-high or low-high-low. This
technique avoids a “stuck” loop in which the watchdog
timer would continue to be reset within the loop, keep-
ing the watchdog from timing out.
Figure 11. Watchdog Flow Diagram
corrected, since the I/O is continually set low and the
watchdog timer is allowed to time out, causing a reset
or interrupt to be issued. When using extended mode,
as described in the Watchdog Input Current section,
this scheme does result in higher average WDI input
current than does the method of leaving WDI low for the
majority of the timeout period and periodically pulsing it
low-high-low.
Figure 11 shows an example of a flow diagram where
the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
every subroutine or loop, then set high again when the
program returns to the beginning. If the program should
“hang” in any subroutine the problem would quickly be
10 ______________________________________________________________________________________
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
1–MAX6304
_____________La yo u t Co n s id e ra t io n s
__Ord e rin g In fo rm a t io n (c o n t in u e d )
SRT and SWT are precision current sources. When
developing the layout for the application, be careful to
minimize b oa rd c a p a c ita nc e a nd le a ka g e c urre nts
around these pins. Traces connected to these pins
should be kept as short as possible. Traces carrying
high-speed digital signals and traces with large voltage
potentials should be routed as far from these pins as
possible. Leakage currents and stray capacitance (e.g.,
a scope probe) at these pins could cause errors in the
reset and/or watchdog timeout period. When evaluating
these parts, use clean prototype boards to ensure accu-
rate reset and watchdog timeout periods.
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 Plastic DIP
8 SO
MAX6302CPA
MAX6302CSA
MAX6302CUA
MAX6302EPA
MAX6302ESA
MAX6303CPA
MAX6303CSA
MAX6303CUA
MAX6303EPA
MAX6303ESA
MAX6304CPA
MAX6304CSA
MAX6304CUA
MAX6304EPA
MAX6304ESA
8 µMAX
8 Plastic DIP
8 SO
8 Plastic DIP
8 SO
8 µMAX
8 Plastic DIP
8 SO
RESET IN is a high-impedance input which is typically
driven by a high-impedance resistor-divider network
(e.g., 1MΩ to 10MΩ). Minimize coupling to transient
signals by keeping the connections to this input short.
Any DC leakage current at RESET IN (e.g., a scope
probe) causes errors in the programmed reset thresh-
old. Note that sensitive pins are located on the GND
side of the device, away from the digital I/O, to simplify
board layout.
8 Plastic DIP
8 SO
8 µMAX
8 Plastic DIP
8 SO
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 580
______________________________________________________________________________________ 11
+5 V, Lo w -P o w e r µP S u p e rvis o ry Circ u it s
w it h Ad ju s t a b le Re s e t /Wa t c h d o g
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.036
MAX
0.044
0.008
0.014
0.007
0.120
0.120
MIN
0.91
0.10
0.25
0.13
2.95
2.95
MAX
1.11
0.20
0.36
0.18
3.05
3.05
A
C
A1 0.004
α
A
B
C
D
E
e
0.010
0.005
0.116
0.116
0.101mm
0.004 in
e
B
A1
L
0.0256
0.65
H
L
0.188
0.016
0°
0.198
0.026
6°
4.78
0.41
0°
5.03
0.66
6°
α
21-0036D
E
H
1–MAX6304
8-PIN µMAX
MICROMAX SMALL-OUTLINE
PACKAGE
D
INCHES
MILLIMETERS
DIM
MIN
MAX
0.069
0.010
0.019
0.010
0.157
MIN
1.35
0.10
0.35
0.19
3.80
MAX
1.75
0.25
0.49
0.25
4.00
A
0.053
D
A1 0.004
B
C
E
e
0.014
0.007
0.150
0°-8°
A
0.101mm
0.004in.
0.050
1.27
e
H
L
0.228
0.016
0.244
0.050
5.80
0.40
6.20
1.27
A1
C
B
L
INCHES
MILLIMETERS
DIM PINS
Narrow SO
SMALL-OUTLINE
PACKAGE
MIN MAX
MIN
MAX
5.00
8.75
8
0.189 0.197 4.80
D
D
D
E
H
14 0.337 0.344 8.55
16 0.386 0.394 9.80 10.00
(0.150 in.)
21-0041A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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