MAX6753KA46_技术文档

19-2530; Rev 2; 8/03

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

General Description

Features

The MAX6746–MAX6753 low-power microprocessor

(µP) supervisory circuits monitor single/dual system

supply voltages from 1.575V to 5V and provide maxi-

mum adjustability for reset and watchdog functions.

ꢀ Factory-Set Reset Threshold Options from 1.575V

to 5V in ~100mV Increments

ꢀ Adjustable Reset Threshold Options

ꢀ Single/Dual Voltage Monitoring

These devices assert a reset signal whenever the V

CC

supply voltage or RESET IN falls below its reset thresh-

old or when manual reset is pulled low. The reset output

ꢀ Capacitor-Adjustable Reset Timeout

ꢀ Capacitor-Adjustable Watchdog Timeout

ꢀ Min/Max (Windowed) Watchdog Option

ꢀ Manual Reset Input Option

remains asserted for the reset timeout period after V

CC

and RESET IN rise above the reset threshold. The reset

function features immunity to power-supply transients.

The MAX6746–MAX6753 have ±±2 factory-trimmed

reset threshold voltages in approximately 100mV incre-

ments from 1.575V to 5.0V and/or adjustable reset

threshold voltages using external resistors.

ꢀ Guaranteed RESET Valid for V

ꢀ 3.7µA Supply Current

≥ 1V

CC

The reset and watchdog delays are adjustable with

external capacitors. The MAX6746–MAX6751 contain a

watchdog select input that extends the watchdog time-

out period by 1±8x. The MAX675±/MAX6753 contain a

window watchdog timer that looks for activity outside an

expected window of operation.

ꢀ Push-Pull or Open-Drain RESET Output Options

ꢀ Power-Supply Transient Immunity

ꢀ Small 8-Pin SOT23 Packages

Ordering Information

The MAX6746–MAX6753 are available with a push-pull

or open-drain active-low RESET output. The MAX6746–

MAX6753 are available in an 8-pin SOT±3 package and

are fully specified over the automotive temperature

range (-40°C to +1±5°C).

PART

TEMP RANGE

-40°C to +125°C

PIN-PACKAGE

8 SOT23-8

MAX6746KA_ _-T

MAX6747KA_ _-T

MAX6748KA-T

Applications

MAX6749KA-T

MAX6750KA_ _-T

MAX6751KA_ _-T

MAX6752KA_ _-T

MAX6753KA_ _-T

Medical Equipment

Automotive

Embedded Controllers

Critical µP Monitoring

Set-Top Boxes

Intelligent Instruments

Portable Equipment

Computers

Note: “_ _” represents the two number suffix needed when

ordering the reset threshold voltage value for the

Battery-Powered

Computers/Controllers

MAX6746/MAX6747 and MAX6750–MAX6753. The reset

threshold voltages are available in approximately 100mV incre-

ments. Table 2 contains the suffix and reset factory-trimmed

voltages. All devices are available in tape-and-reel only. There

is a 2500-piece minimum order increment for standard ver-

sions (see Table 3). Sample stock is typically held on standard

versions only. Nonstandard versions require a minimum order

increment of 10,000 pieces. Contact factory for availability.

Pin Configurations

TOP VIEW

RESET IN (MR)

SWT

1

2

3

4

8

7

6

5

V

CC

RESET

WDI

MAX6746–

MAX6751

SRT

GND

WDS

Selector Guide appears at end of data sheet.

Typical Operating Circuit appears at end of data sheet.

SOT23-8

( ) ARE FOR MAX6746 AND MAX6747 ONLY.

Pin Configurations continued at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

ABSOLUTE MAXIMUM RATINGS

CC

V

to GND...........................................................-0.3V to +6.0V

Continuous Power Dissipation (T = +70°C)

A

SRT, SWT, SET0, SET1, RESET IN, WDS, MR,

WDI, to GND .......................................…-0.3V to (V

RESET (Push-Pull) to GND......................…-0.3V to (V

RESET (Open Drain) to GND.............................…-0.3V to +6.0V

Input Current (All Pins) ..................................................... 20ꢀA

Output Current (RESET) ................................................... 20ꢀA

8-Pin SOT23 (derate 8.9ꢀW/°C above +70°C)............714ꢀW

Operating Teꢀperature Range .........................-40°C to +125°C

Storage Teꢀperature Range ............................-65°C to +150°C

Junction Teꢀperature......................................................+150°C

Lead Teꢀperature (soldering, 10s) .................................+300°C

+ 0.3V)

CC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= +1.2V to +5.5V, T = T

A

to T

, unless otherwise specified. Typical values are at V

= +5V and T = +25°C.) (Note 1)

CC A

CC

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

= 0°C to +125°C

MIN

1.0

TYP

MAX

5.5

10

9

UNITS

T

A

Supply Voltage

V

CC

= -40°C to 0°C

1.2

A

V

≤ 5.5V

≤ 3.3V

≤ 2.0V

5

CC

Supply Current

I

µA

4.2

3.7

CC

8

See V

selection table

V

2%

-

V

2%

+

TH

V

Reset Threshold

V

T = -40°C to+125°C

A

V

CC

TH

Hysteresis

to Reset Delay

V

0.8

20

%

µs

HYST

V

falling froꢀ V + 100ꢀV to V

-

CC

TH

V

CC

100ꢀV at 1ꢀV/µs

C

= 1500pF

5.692

7.590

0.506

250

9.487

SRT

Reset Tiꢀeout Period

t

ꢀs

RP

= 100pF

SRT Raꢀp Current

I

V

= 0 to 1.23V; V

= 1.6V to 5V

200

300

nA

V

RAMP

CC

SRT Raꢀp Threshold

V

= 1.6V to 5V (V

= 1500pF

= 100pF

rising)

RAMP

1.173

5.692

1.235

7.590

0.506

1.297

9.487

RAMP

CC

C

SWT

Norꢀal Watchdog Tiꢀeout Period

(MAX6746–MAX6751)

t

ꢀs

WD

= 1500pF

= 100pF

728.6

971.5 1214.4

64.77

Extended Watchdog Tiꢀeout

(MAX6746–MAX6751)

WD

= 1500pF

= 100pF

971.5 1214.4

64.77

Slow Watchdog Period

(MAX6752/MAX6753)

t

WD2

WD1

Fast Watchdog Tiꢀeout Period,

SET Ratio = 8,

(MAX6752/MAX6753)

C

= 1500pF

= 100pF

= 1500pF

= 100pF

91.08 121.43 151.80

8.09

SWT

t

ꢀs

Fast Watchdog Tiꢀeout Period,

SET Ratio = 16,

(MAX6752/MAX6753)

45.53

60.71

4.05

75.89

t

WD1

2

_______________________________________________________________________________________

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

ELECTRICAL CHARACTERISTICS (continued)

(V

= +1.2V to +5.5V, T = T

A

to T

, unless otherwise specified. Typical values are at V

= +5V and T = +25°C.) (Note 1)

CC A

CC

MIN

MAX

PARAMETER

SYMBOL

CONDITIONS

= 1500pF

MIN

TYP

MAX

UNITS

Fast Watchdog Tiꢀeout Period,

SET Ratio = 64,

(MAX6752/MAX6753)

C

11.38

15.18

18.98

SWT

t

ꢀs

WD1

= 100pF

1.01

Fast Watchdog Miniꢀuꢀ Period

(MAX6752/MAX6753)

2000

ns

SWT Raꢀp Current

I

V

= 0 to 1.23V, V = 1.6V to 5V

200

250

300

1.297

0.3

nA

V

RAMP

SWT

CC

SWT Raꢀp Threshold

V

= 1.6V to 5V (V

rising)

1.173

1.235

RAMP

CC

RAMP

≥ 1.0V, I

≥ 2.7V, I

≥ 4.5V, I

≥ 1.8V, I

= 50µA

SINK

RESET Output Voltage LOW

Open-Drain, Push-Pull

(Asserted)

V

= 1.2ꢀA

= 3.2ꢀA

0.3

V

OL

0.4

= 200µA

0.8 x V

SOURCE

CC

RESET Output Voltage HIGH,

Push-Pull (Not Asserted)

V

≥ 2.25V, I

= 500µA

V

OH

SOURCE

≥ 4.5V, I

= 800µA

SOURCE

RESET Output Leakage Current,

Open Drain

V

> V , reset not asserted,

CC TH

I

1.0

0.8

µA

LKG

= 5.5V

RESET

DIGITAL INPUTS (MR, SET0, SET1, WDI, WDS)

V

IL

V

≥ 4.0V

CC

V

2.4

IH

Input Logic Levels

V

< 4.0V

0.3 x V

CC

IL

V

0.7 x V

1

IH

CC

MR Miniꢀuꢀ Pulse Width

MR Glitch Rejection

µs

ns

kΩ

ns

100

200

20

MR to RESET Delay

MR Pullup Resistance

WDI Miniꢀuꢀ Pulse Width

RESET IN

Pullup to V

12

28

CC

300

RESET IN Threshold

RESET IN Leakage Current

RESET IN to RESET Delay

V

T

= -40°C to +125°C

A

1.216

-50

1.235

1

1.254

+50

V

RESET IN

I

nA

µs

RESET IN

RESET IN falling at 1ꢀV/µs

20

Note 1: Production testing done at T = +25°C. Over teꢀperature liꢀits are guaranteed by design.

A

_______________________________________________________________________________________

3

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Typical Operating Characteristics

(V

= +5V, T = +25°C, unless otherwise noted.)

A

CC

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

RESET TIMEOUT PERIOD vs. C

WATCHDOG TIMEOUT PERIOD vs. C

SRT

SWT

6

10,000

1000

100

10

100,000

10,000

1000

100

MAX6746–MAX6751

5

4

3

EXTENDED MODE

NORMAL MODE

2

1

10

1

0

0.1

1

2

3

4

5

6

100

1000

10,000

100,000

100

1000

10,000

100,000

SUPPLY VOLTAGE (V)

C

SRT

(pF)

C

SWT

(pF)

NORMALIZED RESET TIMEOUT PERIOD

vs. TEMPERATURE

NORMALIZED WATCHDOG TIMEOUT PERIOD

vs. TEMPERATURE

MAXIMUM TRANSIENT DURATION

vs. RESET THRESHOLD OVERDRIVE

1.20

1.15

1.10

1.05

1.00

0.95

0.90

175

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

150

125

100

75

C

SRT

= 100pF

C

= 100pF

SWT

RESET OCCURS

ABOVE THE CURVE

C

SWT

= 1500pF

C

SRT

= 1500pF

50

25

V

TH

= 2.92V

800

0

-50 -25

0

25

50

75 100 125

0

200

400

600

1000

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

RESET THRESHOLD OVERDRIVE (mV)

TEMPERATURE (°C)

NORMALIZED RESET IN THRESHOLD VOLTAGE

vs. TEMPERATURE

RESET IN THRESHOLD

vs. SUPPLY VOLTAGE

SUPPLY CURRENT

vs. TEMPERATURE

1.010

1.008

1.006

1.004

1.002

1.000

0.998

0.996

0.994

0.992

1.240

1.239

1.238

1.237

1.236

1.235

6

5

4

3

V

CC

= 5V

V

CC

= 5V

V

CC

= 1.8V

V

CC

= 3.3V

2

1

0.990

0

-50 -25

0

25

50

75 100 125

1

2

3

4

5

6

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

4

_______________________________________________________________________________________

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Typical Operating Characteristics (continued)

(V

= +5V, T = +25°C, unless otherwise noted.)

A

CC

RESET AND WATCHDOG

TIMEOUT PERIOD vs. V

V

TO RESET DELAY

RESET AND WATCHING TIMEOUT

CC

vs. TEMPERATURE (V FALLING)

PERIOD vs. V

CC

27.0

0.60

0.56

0.52

0.48

0.44

0.40

9.0

8.5

8.0

7.5

7.0

6.5

6.0

C

SWT

= C = 100pF

SRT

V

FALLING AT 1mV/µs

C

= C = 1500pF

SRT

CC

SWT

26.6

26.2

25.8

25.4

25.0

RESET

WATCHDOG

-50 -25

0

25

50

75 100 125

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(V)

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

(V)

TEMPERATURE (°C)

V

CC

V

CC

Pin Description

NAME

FUNCTION

MAX6746

MAX6747

MAX6748–

MAX6751

MAX6752

MAX6753

Manual Reset Input. Pull MR low to ꢀanually reset the device. Reset

reꢀains asserted for the reset tiꢀeout period after MR is released.

1

—

1

MR

Reset Input. High-iꢀpedance input to the adjustable reset coꢀparator.

RESET IN Connect RESET IN to the center point of an external resistor-divider to

set the threshold of the externally ꢀonitored voltage.

—

1

Logic Input. SET0 selects watchdog window ratio or disables the

watchdog tiꢀer. See Table 1.

—

SET0

Watchdog Tiꢀeout Input.

MAX6746–MAX6751: Connect a capacitor between SWT and ground to

set the basic watchdog tiꢀeout period (t ). Deterꢀine the period by

WD

the forꢀula t

= 5.06 x 10⁶x C

with t

in seconds and C

in

SWT

WD

SWT

WD

Farads. Extend the basic watchdog tiꢀeout period by using the WDS

input. Connect SWT to ground to disable the watchdog tiꢀer function.

2

SWT

MAX6752/MAX6753: Connect a capacitor between SWT and ground to

set the slow watchdog tiꢀeout period (t

). Deterꢀine the slow

WD2

watchdog period by the forꢀula: t

= 0.65 x 10⁹x C

with t

in

WD2

SWT

WD2

seconds and C

in Farads. The fast watchdog tiꢀeout period is set

SWT

by pinstrapping SET0 and SET1 (Connect SET0 high and SET1 low to

disable the watchdog tiꢀer function.) See Table 1.

Reset Tiꢀeout Input. Connect a capacitor froꢀ SRT to GND to select

3

4

3

4

3

4

SRT

the reset tiꢀeout period. Deterꢀine the period as follows: t = 5.06 x

RP

10⁶x C

with t in seconds and C

in Farads.

SRT

RP

GND

Ground

_______________________________________________________________________________________

5

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Pin Description (continued)

NAME

FUNCTION

MAX6746

MAX6747

MAX6748–

MAX6751

MAX6752

MAX6753

Watchdog Select Input. WDS selects the watchdog ꢀode. Connect

WDS to ground to select norꢀal ꢀode and the watchdog tiꢀeout

5

—

WDS

SET1

period. Connect WDS to V

basic tiꢀeout period by a factor of 128. A change in the state of WDS

clears the watchdog tiꢀer.

to select extended ꢀode, ꢀultiplying the

CC

Logic Input. SET1 selects the watchdog window ratio or disables the

watchdog tiꢀer. See Table 1.

—

5

Watchdog Input.

MAX6746–MAX6751: A falling transition ꢀust occur on WDI within the

selected watchdog tiꢀeout period or a reset pulse occurs. The

watchdog tiꢀer clears when a transition occurs on WDI or whenever

RESET is asserted. Connect SWT to ground to disable the watchdog

tiꢀer function.

6

WDI

MAX6752/MAX6753: WDI falling transitions within periods shorter than

t

or longer than t

force RESET to assert low for the reset tiꢀeout

WD2

WD1

period. The watchdog tiꢀer begins to count after RESET is deasserted.

The watchdog tiꢀer clears when a valid transition occurs on WDI or

whenever RESET is asserted. Connect SET0 high and SET1 low to

disable the watchdog tiꢀer function. See the Watchdog Timer section.

Push/Pull or Open-Drain Reset Output. RESET asserts whenever V

or

CC

RESET IN drops below the selected reset threshold voltage (V or

TH

V

, respectively) or ꢀanual reset is pulled low. RESET reꢀains

RESET IN

7

8

7

8

7

8

RESET

low for the reset tiꢀeout period after all reset conditions are deasserted,

and then goes high. The watchdog tiꢀer triggers a reset pulse (t

whenever a watchdog fault occurs.

)

RP

Supply Voltage. V

threshold V ꢀonitor.

is the power-supply input and the input for fixed

CC

V

CC

6

_______________________________________________________________________________________

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

t

(MIN)

t

(MAX)

t

(MIN)

t (MAX)

WD2

WD1

WD2

GUARANTEED

TO ASSERT

RESET

GUARANTEED TO

NOT ASSERT

GUARANTEED TO

ASSERT

RESET

*UNDETERMINED

WDI CONDITION 1

WDI CONDITION 2

FAST FAULT

NORMAL OPERATION

SLOW FAULT

WDI CONDITION 3

*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION

Figure 1. MAX6752/MAX6753 Detailed Watchdog Input Timing Relationship

RESET is guaranteed to be in the correct logic state for

greater than 1V. For applications requiring valid

Detailed Description

V

CC

The MAX6746–MAX6753 assert a reset signal whenever

reset logic when V

is less than 1V, see the section

CC

the V

supply voltage or RESET IN falls below its reset

CC

Ensuring a Valid RESET Output Down to V

= 0V.

CC

threshold. The reset output reꢀains asserted for the

reset tiꢀeout period after V and RESET IN rise above

CC

RESET IN Threshold

its respective reset threshold. A watchdog tiꢀer triggers

a reset pulse whenever a watchdog fault occurs.

The MAX6748–MAX6751 ꢀonitor the voltage on RESET IN

using an adjustable reset threshold (V ) set with

RESET IN

an external resistor voltage-divider (Figure 2). Use the

following forꢀula to calculate the externally ꢀonitored

The reset and watchdog delays are adjustable with

external capacitors. The MAX6746–MAX6751 contain a

watchdog select input that extends the watchdog tiꢀe-

out period to 128x.

voltage (V

):

MON_TH

V

= V

x (R1 + R2) / R2

MON_TH

RESET IN

The MAX6752 and MAX6753 have a sophisticated

watchdog tiꢀer that detects when the processor is run-

ning outside an expected window of operation. The

watchdog signals a fault when the input pulses arrive too

V

MON_TH

early (faster that the selected t

late (slower than the selected t

Figure 1).

tiꢀeout period) or too

WD2

WD1

tiꢀeout period) (see

R1

R2

V

CC

V

CC

Reset Output

RESET IN

GND

The reset output is typically connected to the reset input

of a µP. A µP’s reset input starts or restarts the µP in a

known state. The MAX6746–MAX6753 µP supervisory

circuits provide the reset logic to prevent code-execu-

tion errors during power-up, power-down, and

brownout conditions (see theTypical Operating Circuit).

RESET changes froꢀ high to low whenever the ꢀoni-

MAX6748

MAX6749

MAX6750

MAX6751

tored voltage, RESET IN and/or V

drop below the

CC

V

= 1.235 x (R1 + R2) / R2

MON_TH

reset threshold voltages. Once V

and/or V

CC

RESET IN

exceeds its respective reset threshold voltage(s),

RESET reꢀains low for the reset tiꢀeout period, then

goes high.

Figure 2. Calculating the Monitored Threshold Voltage

(V

)

MON_TH

_______________________________________________________________________________________

7

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

guarantee RESET IN threshold accuracy and tiꢀing

V

MON_TH

perforꢀance. The MAX6748 and MAX6749 can be con-

figured to ꢀonitor V

V

voltage by connecting V

to

CC

MON_TH.

Dual-Voltage Monitoring

(MAX6750/MAX6751)

R1

V

CC

The MAX6750 and MAX6751 contain both factory-

triꢀꢀed threshold voltages and an adjustable reset

threshold input, allowing the ꢀonitoring of two voltages,

V

CC

RESET IN

GND

V

and V

(see Figure 2). RESET is asserted

MON_TH

when either of the voltages falls below it respective

threshold voltages.

CC

MAX6748

MAX6749

MAX6750

MAX6751

R2

Manual Reset (MAX6746/MAX6747)

Many µP-based products require ꢀanual reset capabil-

ity, to allow an operator or external logic circuitry to initi-

ate a reset. The ꢀanual reset input (MR) can connect

directly to a switch without an external pullup resistor or

debouncing network. MR is internally pulled up to V

CC

and, therefore, can be left unconnected if unused.

Figure 3. Adding an External Manual Reset Function to the

MAX6748–MAX6751

MR is designed to reject fast, falling transients (typically

100ns pulses) and it ꢀust be held low for a ꢀiniꢀuꢀ of

1µs to assert the reset output. A 0.1µF capacitor froꢀ

MR to ground provides additional noise iꢀꢀunity. After

MR transitions froꢀ low to high, reset reꢀains asserted

for the duration of the reset tiꢀeout period.

where V

is the desired reset threshold voltage

MON_TH

and V is the reset input threshold (1.235V). Resistors

TH

R1 and R2 can have very high values to ꢀiniꢀize cur-

rent consuꢀption due to low leakage currents. Set R2

to soꢀe conveniently high value (500kΩ, for exaꢀple)

and calculate R1 based on the desired reset threshold

voltage, using the following forꢀula:

A ꢀanual reset option can easily be iꢀpleꢀented

with the MAX6748–MAX6751 by connecting a norꢀally

open ꢀoꢀentary switch in parallel with R2 (Figure 3).

When the switch is closed, the voltage on RESET IN

goes to zero, initiating a reset. Siꢀilar to the MAX6746/

MAX6747 ꢀanual reset, reset reꢀains asserted while

the voltage at RESET IN is zero and for the reset tiꢀe-

out period after the switch is opened.

R1 = R2 x (V

/V

- 1) (Ω)

MON_TH RESET IN

The MAX6748 and MAX6749 do not ꢀonitor V

ply voltage, therefore, V

sup-

CC

ꢀust be greater than 1.5V to

CC

V

CC

t

RP

WD

WDI

OV

V

CC

RESET

OV

NORMAL MODE (WDS = GND)

Figure 4a. Watchdog Timing Diagram, WDS = GND

8

_______________________________________________________________________________________

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

V

CC

t

RP

t

x 128

WD

WDI

OV

V

CC

RESET

OV

EXTENDED MODE (WDS = V

)

CC

Figure 4b. Watchdog Timing Diagram, WDS = V

CC

Watchdog Timer

Table 1. Min/MAX Watchdog Setting

MAX6746–MAX6751

The watchdog’s circuit ꢀonitors the µP’s activity. It the

µP does not toggle the watchdog input (WDI) within

SET0

LOW

HIGH

SET1

LOW

HIGH

LOW

HIGH

RATIO

8

t

(user-selected), RESET asserts for the reset tiꢀe-

WD

16

out period. The internal watchdog tiꢀer is cleared by

any event that asserts RESET, by a falling transition at

WDI (which can detect pulses as short as 300ns) or by

a transition at WDS. The watchdog tiꢀer reꢀains

cleared while reset is asserted; as soon as reset is

released, the tiꢀer starts counting.

Watchdog Disabled

64

where HIGH is V

trates the SET0 and SET1 configuration for the 8, 16,

and 64 window ratio ( t /t ).

and LOW is GND. Table 1 illus-

CC

WD2 WD1

The MAX6746–MAX6751 feature two ꢀodes of watch-

dog operation: norꢀal ꢀode and extended ꢀode. In nor-

ꢀal ꢀode (Figure 4a), the watchdog tiꢀeout period is

deterꢀined by the value of the capacitor connected

between SWT and ground. In extended ꢀode (Figure

4b), the watchdog tiꢀeout period is ꢀultiplied by 128.

For exaꢀple, in extended ꢀode, a 0.1µF capacitor gives

a watchdog tiꢀeout period of 65s (see the Extended-

For exaꢀple, if C

low, then t

is 1500pF, and SET0 and SET1 are

SWT

is 975ꢀs (typ) and t

is 122ꢀs (typ).

WD2

WD1

RESET asserts if the watchdog input has two falling

edges too close to each other (faster than t ) (Figure

WD1

5a) or falling edges that are too far apart (slower than

) (Figure 5b). Norꢀal watchdog operation is dis-

t

WD2

played in (Figure 5c). The internal watchdog tiꢀer is

cleared when a WDI falling edge is detected within the

valid watchdog window or when RESET is deasserted.

All WDI inputs are ignored while RESET is asserted.

Mode Watchdog Tiꢀeout Period vs. C

graph in the

SWT

Typical Operating Characteristics). To disable the watch-

dog tiꢀer function, connect SWT to ground.

MAX6752/MAX6753

The MAX6752 and MAX6753 have a windowed watch-

dog tiꢀer that asserts RESET for the adjusted reset

tiꢀeout period when the watchdog recognizes a fast

The watchdog tiꢀer begins to count after RESET is

deasserted. The watchdog tiꢀer clears and begins to

count after a valid WDI falling logic input. WDI falling

transitions within periods shorter than t

or longer

WD1

watchdog fault (t

< t

), or a slow watchdog fault

than t

force RESET to assert low for the reset tiꢀe-

WDI

WD1

WD2

(period > t

). The reset tiꢀeout period is adjusted

independently of the watchdog tiꢀeout period.

out period. WDI falling transitions within the t

and

WD1

WD2

t

window do not assert RESET. WDI transitions

WD2

between t

and t

or t

and

WD2(ꢀin)

WD1(ꢀin)

WD1(ꢀax)

The slow watchdog period, t is calculated as follows:

WD2

t

are not guaranteed to assert or deassert the

WD2(ꢀax)

t

= 0.65 x 10⁹x C

SWT

WD2

RESET. To guarantee that the window watchdog does

not assert the RESET, strobe WDI between t

WD1(ꢀax)

with t

in seconds and C

in Farads.

WD2

SWT

and t

. The watchdog tiꢀer is cleared when

WD2(ꢀin)

The fast watchdog period, t

, is selectable as a ratio

WD1

RESET is asserted or after a falling transition on WDI or

after a state change on SET0 or SET1. Disable the

watchdog tiꢀer by connecting SET0 high and SET1 low.

froꢀ the slow watchdog fault period (t

). Select the

WD2

fast watchdog period by pinstrapping SET0 and SET1,

_______________________________________________________________________________________

9

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

t

< t

(MIN)

WDI WD1

5V

3.3V

V

CC

100kΩ

WDI

MAX6747

MAX6749

MAX6451

MAX6753

RESET

V

CC

RESET

(a) FAST FAULT

µP

RESET

N

t

> t

(MAX)

WDI WD2

GND

WDI

Figure 6. Interfacing to Other Voltage Levels

RESET

norꢀal ꢀode operation, calculate the watchdog tiꢀe-

out capacitor as follows:

(b) SLOW FAULT

(MAX) < t < t

C

SWT

= t /(5.06 x 10⁶),

WD

t

(MIN)

WDI WD2

WD1

with t in seconds and C

in Farads.

RP

SRT

For the MAX6752 and MAX6753 windowed watchdog

function, calculate the slow watchdog period, t

follows:

as

WD2

WDI

t

= 0.65 x 10⁹x C

RESET

WD2

SWT

C

and C

ꢀust be a low-leakage (<10nA) type

SWT

SRT

capacitor. Ceraꢀic capacitors are recoꢀꢀended.

(c) NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)

Transient Immunity

In addition to issuing a reset to the µP during power-up,

power-down, and brownout conditions, these supervi-

sors are relatively iꢀꢀune to short-duration supply tran-

sients (glitches). The Maxiꢀuꢀ Transient Duration vs.

Reset Threshold Overdrive graph in the Typical

Operating Characteristics shows this relationship.

Figure 5. MAX6752/MAX6753 Window Watchdog Diagram

Applications Information

Selecting Reset/Watchdog

Timeout Capacitor

The reset tiꢀeout period is adjustable to accoꢀꢀodate

a variety of µP applications. Adjust the reset tiꢀeout

The area below the curves of the graph is the region

in which these devices typically do not generate a reset

pulse. This graph was generated using a falling pulse

period (t ) by connecting a capacitor (C

) between

SRT

RP

SRT and ground. Calculate the reset tiꢀeout capacitor

as folllows:

applied to V , starting above the actual reset threshold

CC

(V ) and ending below it by the ꢀagnitude indicated

TH

C

SRT

= t / (5.06 x 10⁶),

RP

(reset-threshold overdrive). As the ꢀagnitude of the tran-

sient increases (farther below the reset threshold), the

ꢀaxiꢀuꢀ allowable pulse width decreases. Typically, a

with t in seconds and C

in Farads.

RP

SRT

The watchdog tiꢀeout period is adjustable to accoꢀ-

ꢀodate a variety of µP applications. With this feature,

the watchdog tiꢀeout can be optiꢀized for software

execution. The prograꢀꢀer can deterꢀine how often

the watchdog tiꢀer should be serviced. Adjust the

V

transient that goes 100ꢀV below the reset threshold

CC

and lasts 50µs or less does not cause a reset pulse to be

issued.

watchdog tiꢀeout period (t ) by connecting a specif-

WD

ic value capacitor (C

) between SWT and GND. For

SWT

10 ______________________________________________________________________________________

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Interfacing to Other Voltages for

Logic Compatibility

The open-drain RESET output can be used to interface

to a µP with other logic levels. As shown in Figure 6, the

open-drain output can be connected to voltages froꢀ 0

to 6V.

Ensuring a Valid RESET Down to V

= 0V

CC

(Push-Pull RESET)

When V falls below 1V, RESET current sinking capabil-

CC

ities decline drastically. The high-iꢀpedance CMOS-

logic inputs connected to RESET can drift to undeter-

ꢀined voltages. This presents no probleꢀs in ꢀost

applications, since ꢀost µPs and other circuitry do not

Generally, the pullup resistor connected to the RESET

operate with V

below 1V.

connects to the supply voltage that is being ꢀonitored

CC

at the IC’s V

pin. However, soꢀe systeꢀs can use

CC

In those applications where RESET ꢀust be valid down

to 0V, add a pulldown resistor between RESET and

GND for the MAX6746/MAX6748/MAX6750/MAX6752

push/pull outputs. The resistor sinks any stray leakage

currents, holding RESET low (Figure 7). The value of the

pulldown resistor is not critical; 100kΩ is large enough

not to load RESET and sꢀall enough to pull RESET to

ground. The external pulldown can not be used with

the open-drain reset outputs.

the open-drain output to level-shift froꢀ the ꢀonitored

supply to reset circuitry powered by soꢀe other supply.

Keep in ꢀind that as the supervisor’s V

decreases

CC

towards 1V, so does the IC’s ability to sink current at

RESET. Also, with any pullup resistor, RESET is pulled

high as V

decays toward zero. The voltage where

this occurs depends on the pullup resistor value and

the voltage to which it is connected.

CC

V

CC

V

CC

MAX6746

MAX6748

MAX6450

MAX6752

RESET

100kΩ

GND

Figure 7. Ensuring RESET Valid to V

= 0

CC

______________________________________________________________________________________ 11

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Table 2. Reset Threshold Voltage Suffix

(T = -40°C to +125°C)

Table 3. Standard Version Table

A

PART

TOP MARK

AEDI

MAX6746KA16

MAX6746KA23

MAX6746KA26

MAX6746KA29

MAX6746KA46

MAX6747KA16

MAX6747KA23

MAX6747KA26

MAX6747KA29

MAX6747KA46

MAX6748KA

SUFFIX

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

MIN

TYP

MAX

5.100

4.998

4.896

4.794

4.718

4.590

4.463

4.386

4.284

4.182

4.080

3.978

3.876

3.774

3.672

3.570

3.468

3.366

3.264

3.137

3.060

2.984

2.856

2.754

2.678

2.550

2.448

2.359

2.232

2.142

2.040

1.938

1.836

1.698

1.607

AEDJ

AEDK

AALN

AEDL

AALO

AEDM

AEDN

AEDO

AEDP

AALP

AALQ

AEDQ

AALR

AEDR

AEDS

AEDT

AEDU

AEDV

AEDW

AEDX

AEDY

AEDZ

AEEA

AALT

4.900

4.802

4.704

4.606

4.533

4.410

4.288

4.214

4.116

4.018

3.920

3.822

3.724

3.626

3.528

3.430

3.332

3.234

3.136

3.014

2.940

2.867

2.744

2.646

2.573

2.450

2.352

2.267

2.144

2.058

1.960

1.862

1.764

1.632

1.544

5.000

4.900

4.800

4.700

4.625

4.500

4.375

4.300

4.200

4.100

4.000

3.900

3.800

3.700

3.600

3.500

3.400

3.300

3.200

3.075

3.000

2.925

2.800

2.700

2.625

2.500

2.400

2.313

2.188

2.100

2.000

1.900

1.800

1.665

1.575

MAX6749KA

MAX6750KA16

MAX6750KA23

MAX6750KA26

MAX6750KA29

MAX6750KA46

MAX6751KA16

MAX6751KA23

MAX6751KA26

MAX6751KA29

MAX6751KA46

MAX6752KA16

MAX6752KA23

MAX6752KA26

MAX6752KA29

MAX6752KA46

MAX6753KA16

MAX6753KA23

MAX6753KA26

MAX6753KA29

MAX6753KA46

AEEB

AEEC

AEED

AEEE

AEEF

AEEG

AEEH

Note: Standard versions are shown in bold. There is a 2500-

piece minimum order increment for standard versions.

Sample stock is typically held on standard versions only.

Nonstandard versions require a minimum order increment of

10,000 pieces. Contact factory for availability.

12 ______________________________________________________________________________________

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Selector Guide

FIXED V

RESET

THRESHOLD

ADJUSTABLE

RESET

THRESHOLD

STANDARD

WATCHDOG WATCHDOG

MIN/MAX

MANUAL

RESET

INPUT

CC

PUSH/ PULL OPEN-DRAIN

PART

RESET

TIMER

MAX6746

MAX6747

MAX6748

MAX6749

MAX6750

MAX6751

MAX6752

MAX6753

*

—

*

—

*

—

*

—

*

—

*

—

*

—

*

—

*

—

*

—

*

—

*

—

Typical Operating Circuit

Pin Configurations (continued)

V

IN

TOP VIEW

MAX6749

MAX4751

V

CC

SET0

SWT

SRT

1

2

3

4

8

7

6

5

V

CC

R1

R2

RESET

WDI

MAX6752

MAX6753

RESET IN

V

CC

µP

GND

SET1

MAX6748

MAX6749

MAX6750

MAX6751

RESET

GND

SOT23-8

SRT

C

SRT

I/O

WDI

Chip Information

SWT

WDS

C

SWT

TRANSISTOR COUNT: 1100

PROCESS: BiCMOS

WDS = 0 FOR NORMAL MODE

WDS = V FOR EXTENDED MODE

CC

______________________________________________________________________________________ 13

µP Reset Circuits with Capacitor-Adjustable

Reset/Watchdog Timeout Delay

Package Information

(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,

go to www.maxim-ic.com/packages.)

SEE DETAIL "A"

SYMBOL

MIN

MAX

e

b

A

0.90

0.00

0.90

0.28

0.09

2.80

2.60

1.50

0.30

1.45

0.15

1.30

0.45

0.20

3.00

1.75

0.60

C

L

A1

A2

b

C

D

E

C

L

E1

L

E

E1

L

0.25 BSC.

L2

e

PIN 1

I.D. DOT

(SEE NOTE 6)

0.65 BSC.

1.95 REF.

e1

0

8

e1

D

C

L

L2

A2

A

GAUGE PLANE

A1

SEATING PLANE

C

0

L

NOTE:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. FOOT LENGTH MEASURED FROM LEAD TIP TO UPPER RADIUS OF

HEEL OF THE LEAD PARALLEL TO SEATING PLANE C.

DETAIL "A"

3. PACKAGE OUTLINE EXCLUSIVE OF MOLD FLASH & METAL BURR.

4. PACKAGE OUTLINE INCLUSIVE OF SOLDER PLATING.

5. COPLANARITY 4 MILS. MAX.

6. PIN 1 I.D. DOT IS 0.3 MM MIN. LOCATED ABOVE PIN 1.

PROPRIETARY INFORMATION

TITLE:

7. SOLDER THICKNESS MEASURED AT FLAT SECTION OF LEAD

BETWEEN 0.08mm AND 0.15mm FROM LEAD TIP.

8. MEETS JEDEC MO178.

PACKAGE OUTLINE, SOT-23, 8L BODY

APPROVAL

DOCUMENT CONTROL NO.

REV.

1

21-0078

D

1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered tradeꢀark of Maxiꢀ Integrated Products.


型号：	MAX6753KA46
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	UP Reset Circuits with Capacitor-Adjustable Reset/Watchdog Timeout Delay 上电复位电路，带有电容可调的复位/看门狗超时周期电源电路电源管理电路复位电路光电二极管信息通信管理
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MAX6753KA46 [MAXIM]

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