MAX6877ETG+ [MAXIM]
Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors; 双/三电压，电源跟踪器/排序器/监控
| 型号： | MAX6877ETG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-/Triple-Voltage, Power-Supply Trackers/Sequencers/Supervisors |
| 文件： | 总24页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3771; Rev 0; 7/05
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
General Description
Features
♦ Pin-Selectable Tracking or Sequencing Control
The MAX6877/MAX6878/MAX6879 multivoltage power
trackers/sequencers/supervisors monitor up to three
system voltages and provide proper power-up and
power-down control for systems requiring voltage track-
ing or sequencing. These devices ensure controlled
voltage tracking within a specified range or sequencing
in the proper order as system power supplies are
enabled. The MAX6877/MAX6878/MAX6879 generate
all required voltages and timing to control up to three
external n-channel pass FETs for the OUT1/OUT2/
OUT3 supply voltages (see the Selector Guide for dif-
ferent features of each device).
for Up to Three Supply Voltages
♦ Capacitor-Adjustable Power-Up/Down Tracking
Slew Rate
♦ Capacitor-Adjustable Power-Up Sequencing Delay
♦ Internal Charge Pumps to Enhance External
n-Channel FETs
♦ Capacitor-Adjustable Timeout Period Power-Good
Output (MAX6877/MAX6878)
♦ Adjustable Undervoltage Lockout or
Logic-Enable Input
♦ Internal 100Ω Pulldown for Each Output to
The MAX6877/MAX6878/MAX6879 feature adjustable
undervoltage thresholds for each input supply. When all
the voltages are above these adjustable thresholds, the
devices turn on the external n-channel MOSFETs to
either sequence or track the voltages to the system.
During voltage-tracking mode, the voltage at the GATE
of each MOSFET is increased to slowly bring up all
supplies at a controlled slew rate. The MAX6877/
MAX6878/MAX6879 feature an autoretry or latch-off
mode with capacitor-adjusted timing.
Discharge Capacitive Load Quickly
♦ 0.5V to 5.5V Nominal IN_/OUT_ Range
♦ 2.7V to 5.5V Operating Voltage Range
♦ Immune to Short Voltage Transients
♦ Small 4mm x 4mm 24-Pin or 16-Pin Thin QFN
Packages
Ordering Information
PIN-
PKG
These devices also provide a controlled power-down
(tracking mode) when the system shuts off in an orderly
manner. When an unexpected fault occurs, the outputs
are all pulled down simultaneously with an internal
100Ω pulldown to help discharge capactive loads at
the MOSFET’s source. The MAX6877/MAX6878/
MAX6879 feature independent internal charge pumps
to fully enhance the external FETs for low-voltage drop
at highpass current. The MAX6877 and MAX6878 also
feature a power-good output with a selectable timeout
period that can be used for system reset.
PART
TEMP RANGE
PACKAGE
CODE
MAX6877ETG+
-40°C to +85°C 24 Thin QFN T2444-4
-40°C to +85°C 24 Thin QFN T2444-4
MAX6877ETG
Ordering Information continued at end of data sheet.
+Denotes lead-free package.
Pin Configurations
TOP VIEW
The MAX6877/MAX6878/MAX6879 are available in
small 4mm x 4mm 24-pin and 16-pin thin QFN pack-
ages and are fully specified over the -40°C to +85°C
extended operating temperature range.
18
17
16
15
14
13
12
11
10
9
GATE2 19
OUT1 20
GATE1 21
IN3 22
TRK/SEQ
LTCH/RTR
TIMEOUT
Applications
Multivoltage Systems
MAX6877
SLEW
DELAY
GND
EP*
Networking Systems
IN2 23
8
+
Telecom
24
7
IN1
Storage Equipment
1
2
3
4
5
6
Servers/Workstations
4mm x 4mm THIN QFN
*EXPOSED PADDLE CONNECTED TO GND.
Pin Configurations continued at end of data sheet.
Selector Guide appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
IN1, IN2, IN3, V ....................................................-0.3V to +6V
CC
ABP
Input/Output Current (all pins except
OUT_ and GND) ........................................................... 20mA
.....................................-0.3V to the highest of V
- V
or V
IN3
Continuous Power Dissipation (T = +70°C)
16-Pin 4mm x 4mm Thin QFN
CC
IN1
A
SET1, SET2, SET3 ....................................................-0.3V to +6V
GATE1, GATE2, GATE3 .........................................-0.3V to +12V
OUT1, OUT2, OUT3 .................................................-0.3V to +6V
LTCH/RTR, TRK/SEQ, MARGIN ...............................-0.3V to +6V
FAULT, PG/RST, EN/UV ...........................................-0.3V to +6V
DELAY, SLEW, TIMEOUT.........................................-0.3V to +6V
OUT_ Current.................................................................... 50mA
GND Current..................................................................... 50mA
(derate 16.9mW/°C above +70°C).............................1349mW
24-Pin 4mm x 4mm Thin QFN
(derate 20.8mW/°C above +70°C).............................1667mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V , IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, T = -40°C to +85°C, unless otherwise specified. Typical values
CC
A
are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage on ABP (the highest of V
or IN_)
CC
to ensure that PG/RST and FAULT are valid
1.4
and GATE_ = 0V
Operating Voltage Range
V
V
CC
Voltage on ABP (the highest of V
to ensure the device is fully operational
or IN_)
CC
2.7
5.5
Supply Current
I
V
= 5.5V, IN1 = IN2 = IN3 = 3.3V, no load
1.1
0.5
0.5
0.5
1.8
mA
V
CC
CC
SET_ falling, T = +25oC
SET_ falling, T = -40oC to +85oC
A
0.4925
0.4875
0.5075
0.5125
A
SET_ Threshold Range
V
TH
SET_ Threshold Hysteresis
SET_ Input Current
V
SET_ rising
SET_ = 0.5V
Input rising
Input falling
%
TH_HYS
I
-100
+100
nA
SET
V
1.286
1.25
EN_R
EN_F
EN/UV Input Voltage
V
V
1.22
-5
1.28
+5
EN/UV Input Current
I
t
µA
µs
EN
EN
EN/UV Input Pulse Width
DELAY, TIMEOUT Output Current
EN/UV falling, 100mV overdrive
7
I
(Notes 2, 3)
2.12
2.5
1.25
25
2.88
µA
D
DELAY, TIMEOUT Threshold
Voltage
V
= 3.3V
V
CC
SLEW Output Current (Note 4)
I
22.5
-15
27.5
+15
µA
%
S
Track/Sequence Slew-Rate
Timebase Accuracy
SR
C
= 200pF (Note 4)
SLEW
Timebase/C
Ratio
100pF < C
< 1nF (Note 4)
104
kΩ
%
SLEW
SLEW
Slew-Rate Accuracy during Power-
Up and Power-Down
C
= 200pF, ABP = 5.5V (Note 4)
falling
-50
+50
93.5
SLEW
OUT_
Power-Good Threshold
V
V
91.5
92.5
%
TH_PG
2
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(V , IN1, IN2, or IN3 = +2.7V to +5.5V, EN/UV = MARGIN = ABP, T = -40°C to +85°C, unless otherwise specified. Typical values
CC
A
are at T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Good Threshold Hysteresis
V
V
rising
OUT_
0.5
%
HYS_PG
IN_ +
4.2
IN_ +
5.0
IN_ +
5.8
GATE_ Output High
V
I
= 0.5µA
V
GOH
SOURCE
During power-up and power-down,
= 1V
GATE_ Pullup Current
I
2.5
2.5
4
4
µA
µA
GUP
V
GATE_
During power-up and power-down,
= 5V
I
GD
V
GATE_
GATE_ Pulldown Current
When disabled, V
When disabled, V
= 5V, V
= 5V, V
≥ 2.7V
≥ 4V
9.5
20
6
GATE_
GATE_
IN_
IN_
I
mA
µs
V
GDS
SET_ to GATE_ Delay
t
SET falling, 25mV overdrive
D-GATE
V
V
≥ 2.7V, I
≥ 4.0V, I
= 1mA, output asserted
= 4mA, output asserted
0.3
0.4
IN_
IN_
SINK
SINK
FAULT, PG/RST Output Low
V
OL
Differential between each of the OUT_ and
the ramp voltage during power-up and
power-down, Figure 10 (Note 5)
Tracking Differential Voltage Stop
Ramp
V
75
125
180
310
mV
TRK
Differential between each of the OUT_ and
the ramp voltage, Figure 10 (Note 5)
Tracking Differential Fault Voltage
V
200
250
20
mV
%
TRK_F
TH_PL
Tracking Differential Voltage
Hysteresis
Power-Low Threshold
V
OUT_ falling
OUT_ rising
125
142
10
170
mV
mV
Ω
Power-Low Hysteresis
V
TH_PLHYS
OUT to GND Pulldown Impedance
V
> 2.7V (Note 6)
100
ABP
MARGIN, TRK/SEQ, LTCH/RTR
Pullup Current
I
7
10
13
µA
V
IN
V
0.8
IL
MARGIN, TRK/SEQ, LTCH/RTR
Input Voltage
V
2.0
IH
MARGIN, TRK/SEQ, LTCH/RTR
Glitch Rejection
100
ns
Note 1: Specifications guaranteed for the stated global conditions. 100% production tested at T = +25°C and T = +85°C.
A
A
Specifications at T = -40°C to +85°C are guaranteed by design. These devices meet the parameters specified when at
A
least one of V , IN1/IN2/IN3 is between 2.7V to 5.5V, while the remaining IN1/IN2/IN3 are between 0 and 5.5V.
CC
Note 2: A current I = 2.5µA 15% is generated internally and is used to set the DELAY and TIMEOUT periods and used as a refer-
D
ence for t
and t
.
DELAY
TIMEOUT
Note 3: The total DELAY is t
= 200ms + (500kΩ x C
). Leave DELAY unconnected for 200µs delay. The total TIMEOUT is
DELAY
). Leave TIMEOUT unconnected for 200µs timeout.
DELAY
t
= 200µs + (500kΩ x C
TIMEOUT
TIMEOUT
Note 4: A current I = 25µA 10% is generated internally and used as a reference for t
, t
, and slew rate.
S
FAULT RETRY
Note 5: During power-up, only the condition OUT_ < ramp - V
is checked in order to stop the ramp. However, both conditions
TRK
OUT_ < ramp - V
and OUT_ > ramp + V
cause a fault. During power-down, only the condition OUT > ramp +
TRK_F
TRK_F
V
TRK
is checked in order to stop the ramp. However, both conditions OUT_ < ramp - V and OUT_ > ramp + V
TRK_F TRK_F
cause a fault (see Figure 10). Therefore, if OUT1, OUT2, and OUT3 (during power-up tracking and power-down) differ by
more than 2 x V , a fault condition is asserted.
TRK_F
Note 6: A 100Ω pulldown to GND activated by a fault condition. See the Internal Pulldown section.
_______________________________________________________________________________________
3
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_F
V
EN_R
EN/UV
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 2.5V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
DELAY
PG/RST
t
TIMEOUT
Figure 1. Tracking Timing Diagram in Normal Mode
4
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
EN/UV
V
V
EN_F
EN_R
IN1 GOES BELOW
SET1 THRESHOLD
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 2.5V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
DELAY
t
TIMEOUT
PG/RST
FAULT = HIGH
FORCED INTO QUICK SHUTDOWN AFTER NORMAL SHUTDOWN WHEN IN1 GOES BELOW ITS SET VOLTAGE
Figure 2. Tracking in Fast Shutdown Mode
_______________________________________________________________________________________
5
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_R
V
EN_F
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 2.5V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
DELAY
t
DELAY
t
DELAY
t
TIMEOUT
PG/RST
Figure 3. Sequencing in Normal Mode
6
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_R
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
OUT_ FORCED
CAPACITOR-
ADJUSTED
SLEW RATE
BELOW V
TH_PG
OUT1 = 3.3V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
t
DELAY
DELAY
t
DELAY
PG/RST
t
TIMEOUT
FAULT
FORCED INTO QUICK SHUTDOWN WHEN OUT1 FALLS BELOW 92.5% of IN1
Figure 4. Sequencing in Fast Shutdown Mode
_______________________________________________________________________________________
7
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
EN/UV
V
BUS VOLTAGE MONITORED THROUGH EN/UV INPUT
V
EN_F
EN_R
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 2.5V
OUT2 = 1.8V
OUT3 = 0.7V
OUT_
t
DELAY
*t
TIMEOUT
PG/RST = LOW
*ANY POWER-DOWN CONDITION BEFORE t
(PG/RST ASSERTED) CAUSES A SHUTDOWN.
TIMEOUT
Figure 5. Timing Diagram (Aborted Tracking)
8
_______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
EN/UV
BUS VOLTAGE MONITORED
THROUGH EN/UV INPUT
V
EN_R
V
EN_F
IN1 = 2.5V
IN2 = 1.8V
IN3 = 0.7V
IN_
MONITORED THROUGH SET THRESHOLDS ON SET_ INPUTS
CAPACITOR-
ADJUSTED
SLEW RATE
OUT1 = 2.5V
OUT2 = 1.8V
OUT_
OUT3 = 0.7V
t
t
DELAY
DELAY
t
DELAY
*t
TIMEOUT
PG/RST = LOW
*ANY POWER-DOWN CONDITION BEFORE t
(PG/RST ASSERTED) CAUSES A SHUTDOWN.
TIMEOUT
Figure 6. Timing Diagram (Aborted Sequencing)
_______________________________________________________________________________________
9
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
EN/UV
V
EN_R
OUT2 AND OUT3 ARE WAITING
OUT1 IS SLOW
OUT2 AND OUT3 ARE WAITING
OUT1 IS SLOW
125mV
OUT_
t
t
DELAY
DELAY
t
t
FAULT
FAULT
t
RETRY
FAULT
t
AND t
NOT TO SCALE
FAULT
RETRY
ALL SET_ > 0.5V AND V OR IN_ ≥ 2.7V
CC
Figure 7. t
and t
Timing Diagram in Tracking
FAULT
RETRY
EN/UV
OUT1
OUT1
OUT2
OUT2
OUT_
OUT3 IS SLOW
OUT3 IS SLOW
t
t
DELAY
t
FAULT
FAULT
t
DELAY
t
DELAY
t
RETRY
t
t
DELAY
DELAY
t
DELAY
FAULT
t
AND t
NOT TO SCALE
FAULT
RETRY
ALL SET_ > 0.5V AND V OR IN_ ≥ 2.7V
CC
Figure 8. t
and t
Timing Diagram in Sequencing
RETRY
FAULT
10 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Typical Operating Characteristics
(V
= 2.7V to 5.5V, C
= 200pF, EN = MARGIN = ABP, T = +25°C, unless otherwise noted.)
CC_
SLEW A
V
SUPPLY CURRENT
vs. INPUT VOLTAGE
NORMALIZED POWER-GOOD TIMEOUT
vs. TEMPERATURE
POWER-GOOD TIMEOUT
CC
vs. C
TIMEOUT
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
1000
100
10
T
= +85°C
A
T
= +25°C
A
1
T
= -40°C
A
0.1
2.5
3.0
3.5
4.0
4.5
5.0
5.5
85
1
-40
-15
10
35
60
85
0.0001
0.001
0.01
0.1
1
INPUT VOLTAGE (V)
TEMPERATURE (°C)
C
(µF)
TIMEOUT
NORMALIZED SET_ THRESHOLD
vs. TEMPERATURE
NORMALIZED DELAY TIMEOUT
vs. TEMPERATURE
SLEW RATE
vs. C
SLEW
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
10,000
1000
100
10
-40
-15
10
35
60
-40
-15
10
35
60
85
10
100
1000
10,000
TEMPERATURE (°C)
TEMPERATURE (°C)
C
(pF)
SLEW
DELAY TIMEOUT
vs. C
IN_ TRANSIENT DURATION
vs. IN_ THRESHOLD OVERDRIVE
NORMALIZED EN/UV THRESHOLD
vs. TEMPERATURE
DELAY
1000
100
10
30
27
24
21
18
15
12
9
1.005
IN_ = 3.3V
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
PG/RST GOES LOW ABOVE THE CURVE
1
6
3
0.1
0
0.0001
0.001
0.01
(µF)
0.1
0
50
100
150
200
250
300
-40
-15
10
35
60
85
C
DELAY
IN_ THRESHOLD OVERDRIVE (mV)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Typical Operating Characteristics (continued)
(V
= 2.7V to 5.5V, C
= 200pF, EN = MARGIN = ABP, T = +25°C, unless otherwise noted.)
CC_
SLEW
A
GATE_ VOLTAGE LOW
vs. GATE SINK CURRENT
GATE_ OUTPUT VOLTAGE HIGH
vs. GATE SOURCE CURRENT
TRACKING MODE
MAX6877 toc12
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
9
8
7
6
5
4
3
2
1
0
EN/UV
2V/div
OUT1
OUT2
1V/div
OUT3
0
1
2
3
4
5
6
7
8
9
10
0
0.5
1.0
1.5
2.0
2.5
3.0
10ms/div
GATE SINK CURRENT (mA)
GATE SOURCE CURRENT (µA)
SEQUENCING MODE
FAST SHUTDOWN
MAX6877 toc13
MAX6877 toc14
EN/UV
2V/div
EN/UV
2V/div
OUT1
OUT1
OUT2
1V/div
OUT2
1V/div
OUT3
OUT3
FAULT
2V/div
20ms/div
40ms/div
FAST SHUTDOWN WITH RETRY
MAX6877 toc15
OUT1
2V/div
THRESHOLD ERROR
AT OUT1,
OUT1 PULLED BELOW
92.5% OF IN1
OUT2
2V/div
OUT3
2V/div
FAULT
1V/div
100ms/div
12 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Pin Description
PIN
NAME
FUNCTION
Optional Supply Voltage Input. Connect V
MAX6877 MAX6878 MAX6879
to an alternate (i.e., always-on)
CC
supply if desired. Leave V
supplies less than UVLO to be tracked. V
unconnected, if not used. V
allows IN_
CC
CC
1
1
—
V
CC
is internally pulled down by a
CC
100kΩ resistor.
Internal Supply Bypass Input. Bypass ABP with a 1µF capacitor to GND. ABP
maintains the device supply voltage during rapid power-down conditions.
2
2
1
ABP
3
4
—
4
—
2
SET3
SET2
Externally Adjusted IN_ Undervoltage Lockout Threshold. Connect SET_ to
an external resistor-divider network to set the desired undervoltage threshold
for each IN_ supply (see the Typical Application Circuit). All SET_ inputs
must be above the internal SET_ threshold (0.5V) to enable tracking or
sequencing functionality.
5
5
3
SET1
N.C.
3, 16, 17,
22
—
—
No Connection. Not internally connected.
Logic-Enable Input or Undervoltage Lockout Monitor Input. EN/UV must be
high (EN/UV > V
operation. OUT_ begins tracking down when EN/UV < V
to an external resistor-divider network to set the external UVLO threshold.
) to enable voltage tracking or sequencing power-up
EN_R
6
7
6
7
4
5
EN/UV
. Connect EN/UV
EN_F
GND
Ground
Tracking Startup/Sequence Delay Select Input. Connect a capacitor from
DELAY to GND to select the desired delay period before tracking is enabled
(after all SET_ inputs and EN/UV are above their respective thresholds) or
between supply sequences. Leave DELAY unconnected for the default
200µs delay period.
8
8
6
DELAY
Slew-Rate Adjustment Input. Connect a capacitor from SLEW to GND to
select the desired OUT_ slew rate.
9
9
7
SLEW
PG/RST Timeout Period Adjust Input. PG/RST asserts high after the timeout
period when all OUT_ exceed their IN_ referenced threshold. Connect a
capacitor from TIMEOUT to GND to set the desired timeout period. Leave
TIMEOUT unconnected for the default 200µs delay period.
10
10
—
TIMEOUT
Latch/Autoretry Selection Input. Drive LT C H/RTR low to select the latch mode.
Connect LT C H/RTR to ABP or leave unconnected to select autoretry mode.
LT C H/RTR is internally pulled up to ABP through a 10µA current source.
11
12
11
12
8
9
LTCH/RTR
TRK/SEQ
Track/Sequence Select Input. Drive TRK/SEQ low to enable supply tracking
function. Connect TRK/SEQ to ABP or leave it unconnected to enable supply
sequencing. TRK/SEQ is internally pulled to ABP through a 10µA current
source.
Margin Input, Active-Low. Drive MARGIN low to enable margin mode (see
the Margin section). The MARGIN functionality is disabled (returns to normal
monitoring mode) after MARGIN returns high. MARGIN is internally pulled up
to ABP through a 10µA current source.
13
13
—
MARGIN
______________________________________________________________________________________ 13
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Pin Description (continued)
PIN
NAME
FUNCTION
MAX6877 MAX6878 MAX6879
Power-Good Output, Open-Drain. PG_RST asserts high t
after all
TIMEOUT
14
14
15
—
PG/RST
OUT_ voltages exceed the V
thresholds.
TH_PG
Tracking Fault Alert Output, Active Low, Open-Drain. FAULT asserts low if a
tracking failure is present for longer than the selected fault period or if
tracking voltages fail by more than 250mV. FAULT asserts low if any OUT_
falls below the corresponding IN_ voltage.
15
10
FAULT
Channel 3 Monitored Output Voltage. Connect OUT3 to the source of an n-
channel FET. A fault condition activates a 100Ω pulldown to ground.
16
17
18
19
20
21
—
—
18
19
20
21
—
—
11
12
13
14
OUT3
GATE3
OUT2
Gate Drive for External n-Channel FET. An internal charge pump boosts
GATE3 to V
+ 5V to fully enhance the external n-channel FET when power-
IN3
up is complete.
Channel 2 Monitored Output Voltage. Connect OUT2 to the source of an
n-channel FET. A fault condition activates a 100Ω pulldown to ground.
Gate Drive for External n-Channel FET. An internal charge pump boosts
GATE2 to V
+ 5V to fully enhance the external n-channel FET when power-
GATE2
OUT1
IN2
up is complete.
Channel 1 Monitored Output Voltage. Connect OUT1 to the source of an
n-channel FET. A fault condition activates a 100Ω pulldown to ground.
Gate Drive for External n-Channel FET. An internal charge pump boosts
GATE1
GATE1 to V
+ 5V to fully enhance the external n-channel FET when power-
IN1
up is complete.
Supply Input Voltage. IN1, IN2, or IN3 must be greater than the internal
undervoltage lockout (V = 2.7V) to enable the tracking or sequencing
22
23
—
—
IN3
IN2
ABP
functionality. Each IN_ input is simultaneously monitored by SET_ inputs to
ensure all supplies have stabilized before power-up is enabled. If IN_ is
connected to ground or left unconnected and SET_ is above 0.5V, then no-
sequencing control is performed on that channel. Each IN_ is internally
pulled down by a 100kΩ resistor.
23
15
24
EP
24
EP
16
EP
IN1
EP
Exposed Paddle. Connect exposed paddle to ground.
14 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Functional Diagram
IN1
TO LOAD
V
CC
IN2 IN3
OUT1
GATE1
IN1
ABP
INTERNAL
/UVLO
V
IN1
CC
CHARGE
PUMP
MAX6877
SET1
RAMP
GENERATOR
IN2
COMP
GATE
CONTROLLER
SET2
SET3
IN3
COMP
COMP
COMP
CONTROL
LOGIC
GATE2
OUT2
IN2 TO OUT2
CONTROL BLOCK
V
BUS
OUT1
OUT2
OUT3
IN1
GATE3
OUT3
IN3 TO OUT3
CONTROL BLOCK
EN/UVLO
TRACKING
MONITORS
IN2
IN3
V
REF
PG CIRCUIT
MARGIN
GND
DELAY
SLEW
TIMEOUT
PG/RST
C
C
SLEW
TIMEOUT
FAULT
TRK/SEQ
LTCH/RTR
______________________________________________________________________________________ 15
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
ty to the device in a variety of different applications. As
an example, the MAX6877 can track or sequence two
voltages using IN1 and IN2 while IN3 is left disabled.
Detailed Description
The MAX6877/MAX6878/MAX6879 multivoltage power
trackers/sequencers/supervisors monitor up to three
system voltages and provide proper power-up and
power-down control for systems requiring voltage
tracking or sequencing. These devices ensure con-
trolled voltage tracking with a specified range or
sequencing in the proper order as system power sup-
plies are enabled. The MAX6877/MAX6878/MAX6879
generate all required voltages and timing to control up
to three external n-channel pass FETs for the
OUT1/OUT2/OUT3 supply voltages (see the Selector
Guide for different features of each device.)
Powering the
MAX6877/MAX6878/MAX6879
These devices derive power from either the IN1, IN2, or
IN3 voltage inputs or V
CC
ensure full device operation.
(see the Functional Diagram).
CC
V
or one of the IN_ inputs must be at least +2.7V to
The highest input voltage on IN1/IN2/IN3 or V
sup-
CC
plies power to the devices. Internal hysteresis ensures
that the supply input that initially powers these devices
continues to power the MAX6877/MAX6878/MAX6879
when multiple input voltages are within 100mV (typ) of
each other.
The MAX6877/MAX6878/MAX6879 feature adjustable
undervoltage thresholds for each input supply. When
all the voltages are above these adjusted thresholds,
the devices turn on the external n-channel MOSFETs to
either sequence or track the voltages to the system.
During the voltage-tracking mode, the voltage at the
GATE of each MOSFET is increased to slowly bring up
all supplies at a controlled slew rate. The voltage at the
source (output) of each MOSFET is internally compared
to a control ramp to maintain a low differential between
each monitored supply. Tracking is dynamically adjust-
ed to force all outputs to track within 125mV of the ref-
erence ramp. If for any reason any supplies fail to track
within 250mV of the reference ramp, the FAULT out-
put is asserted, the power-up mode is terminated, and
all outputs are quickly powered off. In sequencing
mode, the outputs are turned on one after the other,
OUT1 first and OUT3 last. The MAX6877/MAX6878/
MAX6879 feature an autoretry or latch-off mode with
capacitor-adjusted timing.
ABP
ABP powers the analog circuitry. Bypass ABP to GND
with a 1µF ceramic capacitor installed as close to the
device as possible. ABP takes the highest voltage of
IN_ or V . Do not use ABP to provide power to exter-
CC
nal circuitry. ABP maintains the device supply voltage
during rapid power-down conditions.
Tracking and Sequencing Modes
(TRK/SEQ)
To enable the power-up/power-down voltage-tracking
operation, drive TRK/SEQ low (connect TRK/SEQ to
GND). To enable power-up sequencing and power-
down tracking functions, drive TRK/SEQ high (connect
TRK/SEQ to ABP) or leave it unconnected. TRK/SEQ is
internally pulled to ABP through a 10µA current source
(see Figures 1 and 3).
These devices also provide a controlled power-down
(tracking mode) when the system shuts off in an orderly
manner. When an unexpected fault occurs, the outputs
are all pulled down simultaneously with an internal
100Ω pulldown to help discharge capacitive loads at
the MOSFET’s source.
Tracking
To operate in tracking mode, connect TRK/SEQ to
GND. When V
> 1.25V and all SET_ inputs are
EN/UV
above the internal SET_ threshold (0.5V), the tracking
process is initiated. The MAX6877/MAX6878/MAX6879
generate an internal reference ramp voltage that drives
the control loops for the tracked voltages. The tracking
functionality is monitored with a comparator control
block for each output (see the Functional Diagram).
The comparators monitor each OUT_ voltage with
respect to the common reference ramp voltage to
ensure the OUT_ voltages stay within 125mV of the ref-
erence ramp, monitor each tracked output voltage with
respect to its source input voltage, and monitor each
output voltage with respect to GND during power-
up/retry cycles. If for any reason any supplies fail to
track within 250mV of the reference ramp, the FAULT
output is asserted, the power-up mode is terminated,
and all outputs are quickly powered off.
The MAX6877/MAX6878/MAX6879 feature independent
internal charge pumps to fully enhance the external
FETs for low-voltage drops at highpass currents. The
MAX6877/MAX6878 also feature a power-good output
with a selectable timeout period that can be used for
system reset.
The MAX6877/MAX6878/MAX6879 monitor up to three
voltages. Devices may be configured to exclude any
IN_. To disable the tracking or sequencing operation of
any IN_, connect the IN_ to ground (or leave uncon-
nected) and connect SET_ to a voltage greater than
0.5V. The channel exclusion feature adds more flexibili-
16 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
During ramp up, if an OUT_ voltage is less than the ref-
or less than the reference ramp voltage by more than
V , a fault is signaled and the fast-shutdown mode
TRK_F
erence ramp voltage by more than 125mV, the control
loop dynamically stops the control ramp voltage from
rising until the slow OUT_ voltage catches up. If an
OUT_ voltage is greater or less than the reference ramp
voltage by more than 250mV, a fault is signaled and a
power-down phase is initiated.
is initiated. In fast-shutdown mode, a 100Ω pulldown
resistor is connected from OUT_ to GND to quickly dis-
charge capacitance at OUT_ and GATE _ is pulled low
with a strong I
current (see Figures 2 and 4).
GDS
Figures 5 and 6 show aborted tracking and sequencing
modes. When EN/UV goes low before t
The slew rate for the reference ramp voltage is capaci-
tor adjustable. Connect a capacitor from SLEW to
ground to select the desired OUT_ slew rate. When all
TIMEOUT
expires, all the outputs go low and the device goes into
fast shutdown.
OUT_ voltages have exceeded the V
percentage
TH_PG
Internal Pulldown
To ensure that the OUT_ voltages are not held high by
a large output capacitance after a fault has occurred,
there is a 100Ω internal pulldown at OUT_. The pull-
of the IN_ voltage (external n-channel FET is saturated),
PG/RST asserts high after t
indicating success-
TIMEOUT
ful tracking.
Sequencing
down ensures that all OUT_ voltages are below V
TH_PL
The sequencing operation can be initiated after all
(referenced to GND) before power-up cycling is initiat-
ed. The internal pulldown also ensures a fast discharge
of the output capacitor during fast shutdown and fault
modes. The pulldowns are not present during normal
operation.
input conditions for power-up are met V
> 1.25V
EN/UV
and all SET_ inputs are above the internal SET_ thresh-
old (0.5V). In sequencing mode, the outputs are turned
on sequentially, OUT1 first and OUT3 last. Before turn-
ing on each channel, a delay period occurs as in
Figure 3 (programmable by connecting a capacitor
from DELAY to ground). The power-up phase for each
channel ends when its output voltage exceeds a fixed
Stability Comment
No external compensation is required for tracking or
slew-rate control.
percentage (V
) of the corresponding IN_ voltage.
TH_PG
Inputs
IN1/IN2/IN3
When all channels have exceeded these thresholds,
PG/RST asserts high after t
cessful sequence.
, indicating a suc-
TIMEOUT
The highest voltage on V , IN1, IN2, or IN3 supplies
CC
power to the device. The undervoltage threshold for
each IN_ supply is set with an external resistor-divider
from each IN_ to SET_ to ground.
If there is a fault condition during the initial power-up
sequence, the process is aborted.
When powering down, all outputs turn off simultaneous-
ly, tracking each other. No reverse power-down
sequencing occurs.
Undervoltage Lockout Threshold Inputs (SET_)
The MAX6877 features three and the MAX6878/
MAX6879 feature two externally adjustable IN_ under-
voltage lockout (UVLO) thresholds (SET1, SET2, SET3) to
enable sequencing/tracking functionality. The undervolt-
age threshold for each IN_ supply is set with an exter-
nal resistor-divider from each IN_ to SET_ to ground
(see Figure 9). All SET_ inputs must be above the inter-
nal SET_ threshold (0.5V) to enable tracking/sequenc-
ing functionality. Use the following formula to set the
UVLO threshold:
Power-Up and Power-Down
During power-up, the OUT_ is forced to follow the internal
reference ramp voltage by an internal loop that controls
the GATE_ of the external MOSFET. This phase must be
completed within the adjustable fault timeout period; oth-
erwise, the part forces a shutdown on all GATE_.
Once the power-up is completed, a power-down phase
can be initiated by forcing V
below V
. The
EN_F
EN/UV
reference voltage ramp ramps down at the capacitor-
adjusted slew rate. The control-loop comparators moni-
tor each OUT_ voltage with respect to the common
reference ramp voltage. During ramp down, if an OUT_
voltage is greater than the reference ramp voltage by
V
= V (R1 + R2) / R2
TH
IN_
where V
TH
is the undervoltage lockout threshold and
is the 500mV SET threshold.
IN_
V
Margin Input (MARGIN)
more than V
, the control loop dynamically stops the
TRK
MARGIN allows system-level testing while power sup-
plies are below the normal ranges as adjusted by the
SET_ inputs. Drive MARGIN low before varying system
control ramp voltage from decreasing until the slow
OUT_ voltage catches up. If an OUT_ voltage is greater
______________________________________________________________________________________ 17
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Limiting Inrush Current
The capacitor connected at SLEW controls the OUT_S
slew rate, thus controlling the inrush current required to
charge the load capacitor at the outputs (OUT_). Using
the programmed slew rate, limit the inrush current by
using the following formula:
V
IN_
IN_
MAX6877
MAX6878
MAX6879
R1
R2
I
= C
x SR
OUT
INRUSH
SET_
where I
is in amperes, C
is in farads, and SR
INRUSH
is in V/s.
OUT
Delay Time Input (DELAY)
To adjust the desired delay period (t ) before
DELAY
tracking/sequencing is enabled, connect a capacitor
(C ) between DELAY to ground (see Figures 1 to 8).
The selected delay time is also enforced when EN/UV
rises from low to high when all the input voltages
(IN1/IN2/IN3) are present. Use the following formula to
calculate the delay time:
DELAY
Figure 9. Setting the Undervoltage (UVLO) Thresholds
voltages below the adjusted thresholds to avoid signal-
ing an error. The state of PG/RST and FAULT outputs
does not change while MARGIN is low. PG/RST,
FAULT, and all monitoring functions are disabled while
MARGIN is low. MARGIN makes it possible to vary the
supplies without a need to adjust the thresholds to pre-
vent tracker/sequencer alerts or faults. Drive MARGIN
high or leave it unconnected for normal operating
mode.
t
= 200µs + (500kΩ x C
)
DELAY
DELAY
where t
is in µs and C
is in farads. Leave
DELAY
DELAY
DELAY unconnected for the default 200µs delay.
Timeout Period Input (TIMEOUT)
These devices feature a PG/RST timeout period.
Connect a capacitor (C
) from TIMEOUT to
TIMEOUT
ground to program the PG/RST timeout period. After all
Slew-Rate Control Input (SLEW)
The reference ramp voltage slew rate during any con-
trolled power-up/down phase can be programmed in
the 90V/s to 950V/s range by connecting a capacitor
OUT_ outputs exceed their IN_ referenced thresholds
(V
), PG/RST remains low for the selected timeout
TH_PG
period, t
(see Figure 3):
TIMEOUT
(C
) from SLEW to ground. Use the following for-
SLEW
t
= 200µs + (500kΩ x C
)
TIMEOUT
TIMEOUT
mula to calculate the typical slew rate:
Slew Rate = (9.35 x 10-8)/ C
where t
is in µs and C
is in farads.
TIMEOUT
TIMEOUT
SLEW
Leave TIMEOUT unconnected for the default 200µs
timeout delay.
where slew rate is in V/s and C
is in farads.
SLEW
The capacitor at C
also sets the FAULT timeout
SLEW
Logic-Enable Input (EN/UV)
period (t
) and FAULT retry timeout period
FAULT
) (see Table 1).
Drive logic EN/UV input above V
to initiate voltage
EN_R
(t
RETRY
tracking/sequencing during the power-up operation.
Drive logic EN/UV below V to initiate tracking
For example, if C
= 100pF, we have t
=
RETRY
EN_F
SLEW
power-down operation. Connect EN/UV to an external
resistor-divider network to set the external undervoltage
lockout threshold.
350ms, t
= 21.91ms, slew rate = 935V/s. For
FAULT
example, if C
FAULT
= 1nF, we have t
= 3.5s,
RETRY
SLEW
t
= 219ms, slew rate = 93.5V/s.
C
is the capacitor on the SLEW pad, and must be
SLEW
OUT1/OUT2/OUT3
The MAX6877 monitors three and MAX6878/MAX6879
monitor two OUT_ outputs to control the tracking/
sequencing performance. After the internal supply
(ABP) exceeds the minimum voltage (2.7V) require-
large enough to make the parasitic capacitance negli-
gible. C should be in the range of 100pF <
SLEW
< 1nF.
C
TSaLbElWe 1. CSLEW Timing Formulas
ments, EN/UV > V
, and IN1/IN2/IN3 are all greater
EN_R
TIME PERIOD
FORMULAS
than their adjusted SET_ thresholds, OUT1/OUT2/OUT3
begin to track or sequence.
Slew Rate
(9.35 x 10-8) / C
3.506 x 109 x C
2.191 x 108 x C
SLEW
SLEW
SLEW
t
RETRY
t
FAULT
18 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
During fault conditions, an internal pulldown resistor
Power-supply tracking operation should be completed
within the selected fault timeout period (t ). The
(100Ω) on OUT_ is enabled to help discharge load
capacitance (100Ω is connected for fast power-down
control).
FAULT
total tracking time is extended when the devices must
vary the control slew rate to allow slow supplies to
catch up. If the external FET is too small (RDS is too
high for the selected load current and IN_ source cur-
rent), the OUT_ voltage may never reach the control
ramp voltage. For a slew rate of 935V/s, a fault is sig-
naled if all outputs have not stabilized within 22ms. For
a slew rate of 93.5V/s, a fault is signaled if tracking
takes too long (more than 219ms).
Outputs
GATE_
The MAX6877/MAX6878/MAX6879 feature up to three
GATE_ outputs to drive up to three external n-channel
FET gates. The following conditions must be met before
GATE_ begins enhancing the external n-channel FET_:
During power-up, only the condition, OUT_ < ramp -
1) All SET_ inputs (SET1–SET3) are above their 0.5V
thresholds.
V
, is monitored in order to stop the ramp. However,
TRK
both conditions OUT < ramp - V
ramp + V
the condition OUT > ramp + V
and OUT_ >
TRK_F
2) At least one IN_ input or V
operating voltage (2.7V).
is above the minimum
CC
cause a fault. During power-down, only
TRK_F
is checked in order
TRK
3) EN/UV > 1.25V.
to stop the ramp. However, both conditions OUT_ <
ramp - V and OUT_ > ramp + V cause a
At power-up mode, GATE_ voltages are enhanced by
control loops so that all OUT_ voltages track together at
a capacitor-adjusted slew rate. Each GATE_ is internal-
ly pulled up to 5V above its relative IN_ voltage to fully
enhance the external n-channel FET when power-up is
complete.
TRK_F
TRK_F
fault (see Figure 10). OUT1, OUT2, and OUT3 are
tracked within V (mV) (power-up tracking and
TRK_F
power-down), and if they differ by more than 2 x V
a fault condition is asserted.
TRK_F
Retry time period (t
) is defined as 16 x t
. To
RETRY
FAULT
calculate the retry time period use the following formula:
FAULT
The MAX6877/MAX6878/MAX6879 include an open-
drain, active-low tracking fault alarm output (FAULT).
FAULT asserts low when a power-up phase is not com-
pleted within the specified fault period or if OUT_ volt-
t
= 3.506 x 109 x C
RETRY
SLEW
where t
is in µs and C
is in farads.
RETRY
SLEW
Autoretry and Latch-Off Functions (LTCH/RTR)
The MAX6877/MAX6878/MAX6879 feature latch-off or
autoretry modes to power-on again after a fault condi-
tion has been detected. Connect LTCH/RTR to ground
to set the latch-off mode. To select autoretry mode,
connect LTCH/RTR to ABP or leave unconnected.
ages are more than V
.
TRK_F
The fault time period (t
) is set through the capaci-
FAULT
tor at SLEW (C
). Use the following formula to esti-
SLEW
mate the fault timeout period:
= 2.191 x 108 x C
t
FAULT
SLEW
250mV UP =
250mV UP =
FAULT THRESHOLD
FAULT THRESHOLD
125mV UP =
STOP RAMP THRESHOLD
125mV DOWN =
STOP RAMP THRESHOLD
250mV DOWN =
FAULT THRESHOLD
250mV DOWN =
FAULT THRESHOLD
REFERENCE RAMP
REFERENCE RAMP
POWER-UP
POWER-DOWN
Figure 10. Stop Ramp FAULT Window During Power-Up and Power-Down
______________________________________________________________________________________ 19
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
When a fault is detected, for a period of t
, GATE_
RETRY
Applications Information
remains off and the 100Ω pulldowns are turned on.
MOSFET Selection
The external pass MOSFET is connected in series with
the sequenced power-supply source. Since the load
current and the MOSFET drain-to-source impedance
After the t period, the device waits t and
RETRY
DELAY
retries power-up if all power-up conditions are met (see
Figure 8). These include all V > 0.5V, EN/UV >
SET_
V
t
, OUT_ voltages < V
RETRY
. The autoretry period,
TH_PL
EN_R
(R ) determine the voltage drop, the on characteris-
DS
, is a function of C
; see Table 1.
SLEW
tics of the MOSFET affect the load supply accuracy.
The MAX6877/MAX6878/MAX6879 fully enhance the
external MOSFET out of its linear range to ensure the
lowest drain-to-source on-impedance. For highest sup-
ply accuracy/lowest voltage drop, select a MOSFET
with an appropriate drain-to-source on-impedance with
a gate-to-source bias of 4.5V to 6.0V.
When the device is in latch mode and a fault occurs,
FAULT asserts and all outputs are latched off. To
unlatch OUT_ after a fault disappears, cycle EN/UV or
cycle V
and the inputs (IN_) below the 2.7V UVLO
CC
threshold. After EN/UV goes high, the device waits a
period then tries to power-up again. If V and
t
RETRY
CC
all IN_ are cycled below 2.7V, the device tries to power-
up immediately.
Layout and Bypassing
For better noise immunity, bypass each of the IN_
inputs to GND with 0.1µF capacitors installed as close
to the device as possible. Bypass ABP to GND with a
1µF capacitor installed as close to the device as possi-
ble. ABP is an internally generated voltage and must
not be used to supply power to external circuitry.
Power-Good Output (PG/RST)
The MAX6877/MAX6878 include a power-good (PG/RST)
output. PG/RST is an open-drain output and requires an
external pullup resistor.
All the OUT_ outputs must exceed their IN_ referenced
thresholds (IN_ x V
) for the selected reset timeout
TH_PG
period t
(see the TIMEOUT Period Input sec-
TIMEOUT
tion) before PG/RST asserts high. PG/RST stays low for
the selected reset timeout period (t ) after all
TIMEOUT
the OUT_ voltages exceed their IN_ referenced thresh-
olds. PG/RST goes low when V
EN_R
< V or V
<
SET_
TH
EN/UV
V
(see Figure 3).
Selector Guide
TIMEOUT
SELECTABLE
PART
CHANNEL
PG/RST
MARGIN
V
CC
MAX6877
MAX6878
MAX6879
3
2
2
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
20 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Typical Application Circuit
OUT1
IN1
IN2
IN3
OUT2
OUT3
0.1µF
0.1µF
0.1µF
IN1
IN2
IN3
GATE1 GATE2 GATE3
SET1
OUT1
OUT2
OUT3
SET2
SET3
EN/UV
MAX6877
V
BUS
FAULT
PG/RST
V
CC
LTCH/RTR
ABP
MARGIN
SLEW
GND
TRK/SEQ DELAY TIMEOUT
1µF
______________________________________________________________________________________ 21
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Ordering Information (continued)
Chip Information
PROCESS: BiCMOS
PIN-
PKG
PART
TEMP RANGE
PACKAGE
CODE
MAX6878ETG+*
MAX6878ETG*
MAX6879ETE+
MAX6879ETE
-40°C to +85°C 24 Thin QFN T2444-4
-40°C to +85°C 24 Thin QFN T2444-4
-40°C to +85°C 16 Thin QFN T1644-4
-40°C to +85°C 16 Thin QFN T1644-4
*Future product—contact factory for availability.
+Denotes lead-free package.
Pin Configurations (continued)
TOP VIEW
18
17
16
15
14
13
12
11
10
9
12
11
10
9
GATE2 19
OUT1 20
GATE1 21
N.C. 22
TRK/SEQ
LTCH/RTR
TIMEOUT
LTCH/RTR
8
7
6
5
OUT1 13
GATE1 14
SLEW
DELAY
GND
MAX6878
MAX6879
SLEW
DELAY
GND
IN2
IN1
15
16
EP*
EP*
IN2
IN1
8
23
24
+
+
7
1
2
3
4
5
6
1
2
3
4
4mm x 4mm THIN QFN
4mm x 4mm THIN QFN
*EXPOSED PADDLE CONNECTED TO GND.
22 ______________________________________________________________________________________
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
21-0139
D
2
______________________________________________________________________________________ 23
Dual-/Triple-Voltage, Power-Supply
Trackers/Sequencers/Supervisors
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
21-0139
D
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Heaney
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