MAX6884ETP [MAXIM]
EEPROM-Programmable, Hex Power-Supply Supervisory Circuits; EEPROM可编程，六角电源电源监控电路
| 型号： | MAX6884ETP |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | EEPROM-Programmable, Hex Power-Supply Supervisory Circuits |
| 文件： | 总34页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3594; Rev 0; 2/05
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
General Description
Features
♦ 6 Configurable Input Voltage Detectors
The MAX6884/MAX6885 EEPROM-configurable, multi-
voltage power-supply supervisors monitor six voltage-
detector inputs, one auxiliary input, and one watchdog
input, and feature three programmable outputs for highly
configurable power-supply monitoring applications.
Manual reset and margin disable inputs offer additional
flexibility.
Programmable Thresholds 0.5V to 3.05V
(in 10mV Increments) or 1V to 5.8V (in 20mV
Increments)
Primary UV and Secondary UV/OV Thresholds
♦ One Configurable Watchdog Timer from 6.25ms
to 102.4s
Each voltage-detector input offers a programmable pri-
mary undervoltage and secondary undervoltage/over-
voltage threshold. Voltage-detector inputs IN1–IN6
monitor voltages from 1V to 5.8V in 20mV increments or
0.5V to 3.05V in 10mV increments.
♦ Configurable RESET, UV/OV, and WDO Outputs
♦ Three Programmable Outputs
Open-Drain or Weak Pullup RESET, UV/OV,
and WDO
Programmable outputs RESET, UV/OV, and WDO pro-
vide system resets/interrupts. Programmable output
options include open-drain or weak pullup. Program-
mable timing delay blocks configure each output to
wait between 25µs and 1600ms after their respective
assertion-causing conditions have been cleared. A fault
register logs condition-causing events (undervoltage,
overvoltage, manual reset, etc.).
Active-Low Output Logic
Timing Delays from 25µs to 1600ms
♦ Margining Disable and Manual Reset Controls
♦ Internal 1.25V Reference or External Reference
Input
♦ 10-Bit Internal ADC Samples the Input Voltage
An internal 10-bit, 1% accurate ADC (MAX6884 only)
Detectors, V
and Auxiliary Input
CC
converts the voltages at IN1–IN6, AUXIN, and V
CC
♦ 512-Bit User EEPROM
through a multiplexer that automatically sequences
through all inputs every 200ms. An SMBus™/I2C-com-
patible serial data interface programs and communi-
cates with the configuration EEPROM, configuration
registers, internal 512-bit user EEPROM, and reads the
ADC registers (MAX6884 only) and fault registers.
Endurance: 100,000 Erase/Write Cycles
Data Retention: 10 Years
♦ SMBus/I2C-Compatible Serial
Configuration/Communication Interface
♦
1ꢀ Threshold Accuracy
The MAX6884/MAX6885 are available in a 5mm x 5mm
x 0.8mm 20-pin thin QFN package and operate over
the extended temperature range (-40°C to +85°C).
Ordering Information
Applications
PKG
CODE
PART
TEMP RANGE
PIN-PACKAGE
Telecommunications/Central-Office Systems
Networking Systems
Servers/Workstations
MAX6884ETP -40°C to +85°C 20 Thin QFN
MAX6885ETP -40°C to +85°C 20 Thin QFN
T2055-5
T2055-5
Base Stations
Storage Equipment
Multimicroprocessor/Voltage Systems
Pin Configurations and Typical Operating Circuit appear at
end of data sheet.
Selector Guide
VOLTAGE-
DETECTOR INPUTS
PROGRAMMABLE
PART
INTERNAL ADC
REFERENCE INPUT AUXILIARY INPUT
OUTPUTS
MAX6884ETP
MAX6885ETP
6
6
Yes
No
3
3
Yes
No
Yes
No
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
Maxiꢀuꢀ Junction Teꢀperature .....................................+150°C
IN1–IN6, V , RESET, UV/OV, WDO........................-0.3V to +6V
Operating Teꢀperature Range ...........................-40°C to +85°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
CC
WDI, MR, MARGIN, SDA, SCL, A0...........................-0.3V to +6V
AUXIN, DBP, REFIN .................................................-0.3V to +3V
Input/Output Current (all pins).......................................... 20ꢀA
Continuous Power Dissipation (T = +70°C)
A
20-Pin (5ꢀꢀ x 5ꢀꢀ) Thin QFN
(derate 21.3ꢀW/°C above +70°C).............................1702ꢀW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V –V
IN1 IN4
or V
= 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise noted. Typical
CC A
values are at T = +25°C.) (Notes 1, 2, 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage on either one of IN1–IN4 or V
guarantee the device is fully operational
to
CC
Operating Voltage Range
2.7
5.8
V
Miniꢀuꢀ voltage on one of IN1–IN4 or V
to guarantee device is EEPROM configured
CC
Undervoltage Lockout
Digital Bypass Voltage
V
2.5
V
UVLO
V
No load
2.48
2.55
0.9
2.67
1.2
V
DBP
V
= 5.8V, IN2–IN6 = GND, no load
ꢀA
ꢀA
IN1
Supply Current
I
CC
Writing to configuration registers or
EEPROM, no load
1.1
1.5
V
V
V
–V
(in 20ꢀV increꢀents)
(in 10ꢀV increꢀents)
(Inputs high iꢀpedance;
1.0
5.8
IN1 IN6
–V
IN1 IN6
0.50
3.05
Threshold Range
V
V
TH
–V
IN1 IN6
0.167
-1
1.017
+1
in 3.3ꢀV increꢀents)
V
= 2.5V to 5.8V
IN_
%
ꢀV
%
(20ꢀV increꢀents)
= 1V to 2.5V
V
IN_
-25
+25
(20ꢀV increꢀents)
V = 1.25V to 3.05V
IN_
T
A
= +25°C to
+85°C, (V
falling)
IN_
-1
+1
(10ꢀV increꢀents)
= 0.5V to 1.25V
V
IN_
-12.5
-1.5
-25
+12.5
+1.5
+25
ꢀV
%
(10ꢀV increꢀents)
= 2.5V to 5.8V
IN1–IN6 Threshold Accuracy
V
IN_
(20ꢀV increꢀents)
= 1V to 2.5V
V
IN_
ꢀV
%
(20ꢀV increꢀents)
V = 1.25V to 3.05V
IN_
T
A
= -40°C to
+85°C, (V
falling)
IN_
-1.5
-12.5
+1.5
+12.5
(10ꢀV increꢀents)
= 0.5V to 1.25V
V
IN_
ꢀV
(10ꢀV increꢀents)
2
_______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V –V
IN1 IN4
or V
= 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise noted. Typical
CC A
values are at T = +25°C.) (Notes 1, 2, 3)
A
PARAMETER
Threshold Hysteresis
SYMBOL
CONDITIONS
MIN
TYP
0.3
10
MAX
UNITS
% V
V
TH-HYST
TH
Threshold Teꢀpco
∆V /°C
ppꢀ/°C
LSB
TH
Threshold Differential Nonlinearity
V
DNL
-1
+1
TH
For V
< highest of V
and
IN_
IN1–IN4
IN_ Input Iꢀpedance
R
130
-150
200
300
kΩ
IN
V
< V
CC
IN_
IN_ Input Leakage Current
Power-Up Delay
I
IN_ high iꢀpedance
V ≥ V
CC
+150
2.5
nA
ꢀs
µs
IN_LKG
t
D-PO
UVLO
IN_ to RESET or UV/OV Delay
t
IN_ falling/rising, 100ꢀV overdrive
20
D-R
000
001
010
011
100
101
110
111
0.025
1.406 1.5625 1.719
5.625
22.5
45
6.25
25
6.875
27.5
55
RESET and UV/OV Tiꢀeout
Period (Tables 6 and 7)
t , t
RP UP
ꢀs
50
180
200
400
1600
220
440
1760
0.4
360
1440
RES ET, U V/O V, W DO Output Low
I
= 4ꢀA, output asserted
V
SINK
RESET, UV/OV, WDO Output
Open-Drain Leakage Current
Output high iꢀpedance
-1
+1
µA
RESET, UV/OV, WDO Output
Pullup Resistance
R
V
V
, V , V = 2V
RESET UV/OV WDO
6.6
10
15.0
0.6
kΩ
PU
V
IL
MR, MARGIN, WDI Input Voltage
V
1.4
1
IH
MR Input Pulse Width
MR Glitch Rejection
t
µs
ns
MR
100
_______________________________________________________________________________________
3
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V –V
IN1 IN4
or V
= 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise noted. Typical
CC A
values are at T = +25°C.) (Notes 1, 2, 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MR to RESET or UV/OV Delay
t
200
ns
D-MR
MR to Internal V
Current
Pullup
DBP
I
V
= 1.4V
MR
5
5
10
15
µA
µA
MR
MARGIN to DBP Pullup Current
I
V
V
= 1.4V
MARGIN
10
10
15
15
MARGIN
WDI Pulldown Current
WDI Input Pulse Width
I
t
= 0.6V
WDI
5
µA
ns
WDI
WDI
50
000
001
010
011
100
101
110
111
5.625
22.5
90
6.25
25
6.875
27.5
110
ꢀs
100
360
1.44
5.76
23.04
400
440
Watchdog Tiꢀeout Period
(Table 8)
t
WD
1.60
6.40
25.60
1.76
7.04
28.16
s
92.16 102.40 112.64
Reference Input Voltage Range
Reference Input Resistance
V
MAX6884 only
= 1.25V, MAX6884 only
1.225
1.25
500
1.275
V
REF
R
V
kΩ
REF
REF
IN1–IN6, V ; LSB = 7.32ꢀV, MAX6884 only
CC
0
0
5.8
IN1–IN6; LSB = 3.66ꢀV, MAX6884 only
3.746
ADC Range
ADC
V
RANGE
AUXIN, IN1–IN6 high-iꢀpedance ꢀode;
LSB = 1.2ꢀV, MAX6884 only
0
1.25
Internal reference, MAX6884 only
External reference, MAX6884 only (Note 5)
MAX6884 only (Note 6)
1.0
1.0
ADC Total Unadjusted Error
(Note 4)
TUE
DNL
%FSR
ADC Differential Nonlinearity
ADC Total Monitoring Cycle Tiꢀe
AUXIN Input Leakage Current
1
LSB
ꢀs
µA
Converts all six IN_ inputs, AUXIN, and
t
C
200
266
+1
V
, MAX6884 only
CC
I
V
= 1.25V, MAX6884 only
-1
AUXIN
AUXIN
SERIAL INTERFACE LOGIC (SDA, SCL, A0)
Logic-Input Low Voltage
Logic-Input High Voltage
Input Leakage Current
Output-Voltage Low
V
0.8
V
V
IL
V
2.0
IH
I
1
µA
V
LKG
V
I
= 3ꢀA
0.4
10
OL
I/O
SINK
Input/Output Capacitance
C
pF
4
_______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
TIMING CHARACTERISTICS
(V –V
or V
= 2.7V to 5.8V, AUXIN = WDI = GND, MARGIN = MR = DBP, T = -40°C to +85°C, unless otherwise noted. Typical
IN1 IN4
CC
A
values are at T
= +25°C.) (Notes 1, 2, 3)
IN1
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 6)
Serial Clock Frequency
Clock Low Period
Clock High Period
Bus Free Tiꢀe
f
400
kHz
µs
µs
µs
µs
µs
µs
ns
ns
SCL
t
1.3
0.6
1.3
0.6
0.6
0.6
100
30
LOW
t
HIGH
t
BUF
START Setup Tiꢀe
START Hold Tiꢀe
STOP Setup Tiꢀe
Data In Setup Tiꢀe
Data In Hold Tiꢀe
t
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
t
t
t
t
900
Receive SCL/SDA Miniꢀuꢀ Rise
Tiꢀe
20 +
t
t
(Note 7)
(Note 7)
(Note 7)
(Note 7)
ns
ns
ns
ns
ns
R
R
0.1 x C
BUS
Receive SCL/SDA Maxiꢀuꢀ Rise
Tiꢀe
300
Receive SCL/SDA Miniꢀuꢀ Fall
Tiꢀe
20 +
t
t
t
F
F
F
0.1 x C
BUS
Receive SCL/SDA Maxiꢀuꢀ Fall
Tiꢀe
300
20 +
0.1 x C
Transꢀit SDA Fall Tiꢀe
C
= 400pF (Note 5)
300
11
BUS
BUS
50
Pulse Width of Spike Suppressed
EEPROM Byte Write Cycle Tiꢀe
t
SP
(Note 8)
(Note 9)
ns
t
ꢀs
WR
Note 1: 100% production tested at T = +25°C and T = +85°C. Specifications at T = -40°C are guaranteed by design.
A
A
A
Note 2: Device ꢀay be supplied froꢀ IN1–IN4 or V
.
CC
Note 3: The internal supply voltage, ꢀeasured at V , equals the ꢀaxiꢀuꢀ of IN1–IN4.
CC
Note 4: V
> 0.3 x ADC range.
IN_
Note 5: Does not include the inaccuracy of the 1.25V input reference voltage (MAX6884 only).
Note 6: DNL is iꢀplicitly guaranteed by design in a Σ∆ converter.
Note 7: C
= total capacitance of one bus line in picofarads. Rise and fall tiꢀes are ꢀeasured between 0.1 x V
and 0.9 x
BUS
BUS
V
BUS
.
Note 8: Input filters on SDA, SCL, and A0 suppress noise spikes <50ns.
Note 9: An additional cycle is required when writing to configuration ꢀeꢀory for the first tiꢀe.
_______________________________________________________________________________________
5
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Typical Operating Characteristics
(V –V
IN1 IN4
or V
= 5V, AUXIN = WDI = GND, MARGIN = MR = DBP. Typical values are at T = +25°C, unless otherwise noted.)
CC
A
IN1–IN4 SUPPLY CURRENT
vs. IN1–IN4 SUPPLY VOLTAGE
NORMALIZED RESET OR UV/0V
TIMEOUT PERIOD vs. TEMPERATURE
V
SUPPLY CURRENT
CC
CC
vs. V SUPPLY VOLTAGE
1.00
0.95
0.90
0.85
0.80
0.75
0.70
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.00
0.95
0.90
0.85
0.80
0.75
0.70
T
= +85°C
A
T
= +85°C
A
T
= +25°C
A
T
= +25°C
A
T
= -40°C
T
= -40°C
A
A
2.6
3.6
4.6
5.6
-40
-15
10
35
60
85
2.6
3.6
4.6
5.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
IN_ TO RESET OR UV/OV
PROPAGATION DELAY vs. TEMPERATURE
NORMALIZED IN_ THRESHOLD
vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
30
29
28
27
26
25
24
23
22
21
20
1.005
1.004
1.003
1.002
1.001
1.000
0.999
0.998
0.997
0.996
0.995
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
100mV OVERDRIVE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAXIMUM IN_ TRANSIENT
vs. IN_ THRESHOLD OVERDRIVE
OUTPUT VOLTAGE LOW
vs. SINK CURRENT
OUTPUT VOLTAGE HIGH
vs. SOURCE CURRENT (WEAK PULLUP)
200
175
150
125
100
75
400
350
300
250
200
150
100
50
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
RESET OR UV/OV ASSERTS
ABOVE THIS LINE
50
25
0
0
1
10
100
1000
0
2
4
6
8
10
12
14
0
0.05 0.10 0.15 0.20 0.25 0.30
SOURCE CURRENT (mA)
IN_ THRESHOLD OVERDRIVE (mV)
SINK CURRENT (mA)
6
_______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Typical Operating Characteristics (continued)
(V –V
IN1 IN4
or V
= 5V, AUXIN = WDI = GND, MARGIN = MR = DBP. Typical values are at T = +25°C, unless otherwise noted.)
CC
A
MR TO RESET OR UV/OV OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
ADC ACCURACY vs. TEMPERATURE
0.5
0.4
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
V
= 5V,
0.3
IN1
20mV/STEP
RANGE
V
= 2V,
IN5
0.2
10mV/STEP
RANGE
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
VAUXIN = 1V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
MAX6884
MAX6885
Reset Output. Configurable, active-low, open drain, or weak pullup. RESET assuꢀes its
prograꢀꢀed conditional output state when V exceeds UVLO (2.5V).
1
1
RESET
CC
Watchdog Tiꢀer Output. Configurable, active-low, open drain, or weak pullup. WDO
asserts when WDI is not toggled with a valid high-to-low or low-to-high transition within
the watchdog tiꢀeout period.
2
2
WDO
Undervoltage/Overvoltage Output. Configurable, active-low, open drain, or weak pullup.
3
4
3
4
UV/OV
UV/OV assuꢀes its prograꢀꢀed conditional output state when V
(2.5V).
exceeds UVLO
CC
GND
Ground
Watchdog Tiꢀer Input. Logic input for the watchdog tiꢀer function. If WDI is not toggled
with a valid low-to-high or high-to-low transition within the watchdog tiꢀeout period,
WDO asserts. Progaꢀ initial and norꢀal watchdog tiꢀeout periods froꢀ 6.25ꢀs to
102.4s. WDI is internally pulled down to GND through a 10µA current sink.
5
6
5
6
WDI
Manual Reset Input. Prograꢀ MR to assert RESET and/or UV/OV when MR is asserted.
Leave MR unconnected or connect to DBP if unused. MR is internally pulled up to DBP
through a 10µA current source.
MR
_______________________________________________________________________________________
7
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Pin Description (continued)
PIN
NAME
FUNCTION
MAX6884
MAX6885
Margin Input. MARGIN holds RESET, UV/OV, and WDO in their existing states when
MARGIN is driven low. Leave MARGIN unconnected or connect to DBP if unused.
MARGIN is internally pulled up to DBP through a 10µA current source. MARGIN
overrides MR if both are asserted at the saꢀe tiꢀe.
7
7
MARGIN
8
9
8
9
SDA
SCL
Serial Data Input/Output (Open Drain). SDA requires an external pullup resistor.
Serial-Interface Clock Input. SCL requires an external pullup resistor.
Serial Address Input 0. Allows up to 2 devices to share a coꢀꢀon bus. Connect A0 to
ground or the serial-interface power supply.
10
10
A0
Reference Voltage Input. Prograꢀ the device for external or internal reference. Connect
an external +1.225V to +1.275V reference to REFIN when using an external reference.
Leave REFIN unconnected when using the internal reference.
11
—
REFIN
Auxiliary Input. A 10-bit ADC converts the input voltage at AUXIN. The high-iꢀpedance
AUXIN input accepts input voltages up to 1.25V. AUXIN does not affect prograꢀꢀable
outputs.
12
—
—
AUXIN
N.C.
11, 12
No Connection. Not internally connected.
Internal Power-Supply Voltage. Bypass V
to GND with a 1µF ceraꢀic capacitor as
CC
close to the device as possible. V
supplies power to the internal circuitry. V
is
CC
CC
13
14
15
13
14
15
V
internally powered froꢀ the highest of the ꢀonitored IN1–IN4 voltages. Do not use V
CC
CC
to supply power to external circuitry. To externally supply V , see the Powering the
CC
MAX6884/MAX6885 section.
Internal Digital Power-Supply Voltage. Bypass DBP to GND with a 1µF ceraꢀic
capacitor. DBP supplies power to the EEPROM ꢀeꢀory, the internal logic circuitry, and
the prograꢀꢀable outputs. Do not use DBP to supply power to external circuitry.
DBP
IN6
Voltage-Detector Input 6. Prograꢀ two thresholds per voltage-detector input
(undervoltage UV and undervoltage/overvoltage UV/OV). Prograꢀ IN6 detector
thresholds froꢀ 1V to 5.8V in 20ꢀV increꢀents, 0.5V to 3.05V in 10ꢀV increꢀents. For
iꢀproved noise iꢀꢀunity, bypass IN6 to GND with a 0.1µF capacitor installed as close
to the device as possible.
Voltage-Detector Input 5. Prograꢀ two thresholds per voltage-detector input
(undervoltage UV and undervoltage/overvoltage UV/OV). Prograꢀ IN5 detector
thresholds froꢀ 1V to 5.8V in 20ꢀV increꢀents, 0.5V to 3.05V in 10ꢀV increꢀents. For
iꢀproved noise iꢀꢀunity, bypass IN5 to GND with a 0.1µF capacitor installed as close
to the device as possible.
16
17
16
17
IN5
IN4
Voltage-Detector Input 4. Prograꢀ two thresholds per voltage-detector input
(undervoltage UV and undervoltage/overvoltage UV/OV). Prograꢀ IN4 detector
thresholds froꢀ 1V to 5.8V in 20ꢀV increꢀents, 0.5V to 3.05V in 10ꢀV increꢀents. For
iꢀproved noise iꢀꢀunity, bypass IN4 to GND with a 0.1µF capacitor installed as close
to the device as possible. Prograꢀ the device to receive power through IN1–IN4 inputs
or V
(see the Powering the MAX6884/MAX6885 section).
CC
8
_______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Pin Description (continued)
PIN
NAME
FUNCTION
MAX6884
MAX6885
Voltage-Detector Input 3. Prograꢀ two thresholds per voltage-detector input
(undervoltage UV and undervoltage/overvoltage UV/OV). Prograꢀ IN3 detector
thresholds froꢀ 1V to 5.8V in 20ꢀV increꢀents, or 0.5V to 3.05V in 10ꢀV increꢀents.
For iꢀproved noise iꢀꢀunity, bypass IN3 to GND with a 0.1µF capacitor installed as
close to the device as possible. Prograꢀ the device to receive power through IN1–IN4
18
18
IN3
IN2
inputs or V
(see the Powering the MAX6884/MAX6885 section).
CC
Voltage-Detector Input 2. Prograꢀ two thresholds per voltage-detector input
(undervoltage UV and undervoltage/overvoltage UV/OV). Prograꢀ IN2 detector
thresholds froꢀ 1V to 5.8V in 20ꢀV increꢀents, or 0.5V to 3.05V in 10ꢀV increꢀents.
For iꢀproved noise iꢀꢀunity, bypass IN2 to GND with a 0.1µF capacitor installed as
close to the device as possible. Prograꢀ the device to receive power through IN1–IN4
19
19
inputs or V
(see the Powering the MAX6884/MAX6885 section).
CC
Voltage-Detector Input 1. Prograꢀ two thresholds per voltage-detector input
(undervoltage UV and undervoltage/overvoltage UV/OV). Prograꢀ IN1 detector
thresholds froꢀ 1V to 5.8V in 20ꢀV increꢀents, or 0.5V to 3.05V in 10ꢀV increꢀents.
For iꢀproved noise iꢀꢀunity, bypass IN1 to GND with a 0.1µF capacitor installed as
close to the device as possible. Prograꢀ the device to receive power through IN1–IN4
20
—
20
—
IN1
EP
inputs or V
(see the Powering the MAX6884/MAX6885 section).
CC
Exposed Paddle. Internally connected to GND. Connect EP to GND or leave floating.
An internal 10-bit ADC (MAX6884 only) converts volt-
Detailed Description
ages at IN1–IN6, AUXIN, and V
through a ꢀultiplex-
CC
The MAX6884/MAX6885 EEPROM-configurable, ꢀulti-
voltage supply supervisors ꢀonitor six voltage-detector
inputs, one auxiliary input, and one watchdog input,
and feature three prograꢀꢀable outputs for highly con-
figurable, power-supply ꢀonitoring applications (see
Table 1 for prograꢀꢀable features). Manual reset and
ꢀargin disable inputs offer additional flexibility.
er that autoꢀatically sequences through all inputs
every 200ꢀs. Access the device’s internal 512-bit user
EEPROM, configuration EEPROM, configuration regis-
ters, ADC registers, and fault registers through an
SMBus/I2C-coꢀpatible serial interface (see the
SMBus/I2C-Compatible Serial Interface section). The
MAX6884/MAX6885 also feature an accurate internal
1.25V reference. For greater accuracy, connect an
external 1.25V reference to REFIN (MAX6884 only).
Each voltage detector provides a prograꢀꢀable pri-
ꢀary undervoltage and secondary undervoltage/over-
voltage threshold. Prograꢀ thresholds froꢀ 0.5V to
3.05V in 10ꢀV increꢀents, 1.0V to 5.8V in 20ꢀV incre-
ꢀents, or froꢀ 0.1667V to 1.0167V in 3.3ꢀV incre-
ꢀents. To achieve thresholds froꢀ 0.1667V to 1.0167V
in 3.3ꢀV increꢀents, the respective input voltage
detector ꢀust be prograꢀꢀed for high iꢀpedance
and an external voltage-divider ꢀust be connected. A
fault register logs undervoltage and overvoltage condi-
tions for each voltage-detector input.
Prograꢀ outputs RESET, UV/OV, and WDO for open-
drain or weak pullup. Prograꢀ RESET and UV/OV to
assert on any voltage-detector input, MR, or each other.
RESET can also depend on WDO. Prograꢀꢀable tiꢀing
delay blocks configure each output to wait between
25µs and 1600ꢀs before deasserting. Fault registers log
the assertion of RESET, UV/OV, and WDO.
_______________________________________________________________________________________
9
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
The MAX6884/MAX6885 feature a watchdog tiꢀer with
prograꢀꢀable initial and norꢀal tiꢀeout periods froꢀ
6.25ꢀs to 102.4s. WDO asserts when WDI is not tog-
gled froꢀ high-to-low or low-to-high within the appro-
priate watchdog tiꢀeout period. Prograꢀ WDO to
assert RESET.
Prograꢀ the MAX6884/MAX6885 to receive power
through IN1–IN4 or V (see the Powering the
MAX6884/MAX6885 section). Outputs reꢀain asserted
while the voltage that is supplying the device is below
UVLO (2.5V) and above 1V (see Figure 1).
CC
Table 1. Programmable Features
FEATURE
DESCRIPTION
• Priꢀary undervoltage threshold
• Secondary undervoltage or overvoltage threshold
• 1V to 5.8V thresholds in 20ꢀV increꢀents
Input Voltages IN1–IN6
• 0.5V to 3.05V thresholds in 10ꢀV increꢀents
• 0.1667V to 1.017V thresholds in 3.3ꢀV increꢀents in high-iꢀpedance ꢀode
• Dependency on IN1–IN6, MR, UV/OV, and/or WDO
• Active-low, weak pullup, or open-drain output
• Prograꢀꢀable tiꢀeout periods of 25µs, 1.5625ꢀs, 6.25ꢀs, 25ꢀs, 50ꢀs, 200ꢀs, 400ꢀs, or
1.6s
Prograꢀꢀable Output RESET
Prograꢀꢀable Output UV/OV
• Dependency on IN1–IN6, MR, and/or RESET
• Active-low, weak pullup, or open-drain output
• Prograꢀꢀable tiꢀeout periods of 25µs, 1.5625ꢀs, 6.25ꢀs, 25ꢀs, 50ꢀs, 200ꢀs, 400ꢀs, or
1.6s
Prograꢀꢀable Output WDO
• Active-low, weak pullup, or open-drain output
• Initial watchdog tiꢀeout period of 6.25ꢀs, 25ꢀs, 100ꢀs, 400ꢀs, 1.6s, 6.4s, 25.6s, or 102.4s
• Norꢀal watchdog tiꢀeout period of 6.25ꢀs, 25ꢀs, 100ꢀs, 400ꢀs, 1.6s, 6.4s, 25.6s, or 102.4s
• Watchdog enable/disable
Watchdog Tiꢀer
• Prograꢀs whether the device is powered froꢀ the highest IN_ input or froꢀ an external supply
V
Power Mode
CC
connected to V
CC
Manual Reset Input MR
• Prograꢀ RESET or UV/OV to assert while MR is asserted
• Internal +1.25V reference voltage
• Goes high iꢀpedance when internal reference is selected
• External reference voltage input froꢀ 1.225V to 1.275V
• Sets ADC voltage range
Reference Input REFIN
• Saꢀples voltages at IN1–IN6, AUXIN, and V
CC
• Coꢀpletes conversion of all eight inputs in 200ꢀs
• Reference voltage sets ADC range
10-Bit ADC*
• Read ADC data froꢀ SMBus/I2C interface
Write Disable
• Locks user EEPROM based on RESET or UV/OV assertion
Configuration Lock
• Locks configuration registers and EEPROM
*ADC does not affect programmable outputs.
10 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
RESET
UV/OV
WDO
LOGIC NETWORK
FOR OUTPUTS
OUTPUT
STAGES
COMPARATORS
IN_
MR
MARGIN
WDI,
RESET
WATCHDOG
TIMER
(ADC MUX)
(ADC)
(ADC REGISTERS)
AUXIN, V
CC
SDA,
SCL
SERIAL
INTERFACE
REGISTER BANK
EEPROM
(USER AND CONFIG)
A0
BOOT
CONTROLLER
ANALOG
BLOCK
DIGITAL
BLOCK
MAX6884
MAX6885
( ) MAX6884 ONLY
Figure 1. Top-Level Block Diagram
______________________________________________________________________________________ 11
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Functional Diagram
2.55V LDO
RESET OUTPUT
IN_
DETECTOR
IN1
WEAK PULLUP OR
OPEN-DRAIN SWITCH
10kΩ
RESET
RESET TIMING BLOCK
IN2
IN3
IN4
IN5
IN2 DETECTOR
IN3 DETECTOR
IN4 DETECTOR
IN5 DETECTOR
IN6 DETECTOR
UV/OV TIMING BLOCK
UV/OV OUTPUT
UV/OV
WDO
WATCHDOG TIMING BLOCK
WDO OUTPUT
MAIN
OSCILLATOR
IN6
REFIN
(N.C.)
AUXIN
(N.C.)
ADC REGISTERS
ADC
ADC
MUX
TIMING
IN1
IN2
IN3
IN4
IN5
IN6
EEPROM
CHARGE PUMP
ADC
CONFIG
REGISTERS
CONFIG
EEPROM
USER
VIRTUAL
DIODES
V
CC
V
CC
EEPROM
AUXIN
1µF
1µF
2.55V
LDO
1.25V
REFERENCE
(MAX6884 ONLY)
SDA
SCL
A0
DBP
SERIAL
INTERFACE
MAX6884
MAX6885
( ) MAX6885 ONLY
GND
*SEE THE EXTERNAL VOLTAGE-DIVIDER SECTION FOR HIGH-IMPEDANCE ARCHITECTURE.
12 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Powering the MAX6884/MAX6885
ADC (MAX6884 Only)
The MAX6884/MAX6885 derive power froꢀ the voltage-
detector inputs: IN1–IN4 or through an externally sup-
An internal 10-bit ADC (MAX6884 only) converts volt-
ages at IN1–IN4, AUXIN, and V
through a ꢀultiplexer
CC
plied V . A virtual diode-ORing scheꢀe selects the
CC
that autoꢀatically sequences through all inputs every
200ꢀs. Registers 18h to 27h store the ADC data (see
Table 3). Read the ADC data froꢀ the MAX6884 with
the serial interface. The ADC has no effect on prograꢀ-
ꢀable outputs RESET, UV/OV, or WDO.
positive input that supplies power to the device (see the
Functional Diagram). The highest input voltage on
IN1–IN4 supplies power to the device. One of V –V
IN1 IN4
ꢀust be at least 2.7V to ensure proper operation.
Internal hysteresis ensures that the supply input that initially
powered the device continues to power the device when
ꢀultiple input voltages are within 50ꢀV of each other.
Inputs
The MAX6884/MAX6885 offer the following inputs: volt-
age-detector inputs IN1–IN4, auxiliary input AUXIN
(MAX6884 only), ꢀanual reset input MR, ꢀargin input
MARGIN, and reference input REFIN (MAX6884 only).
V
powers the analog circuitry and is the bypass con-
CC
nection for the MAX6884/MAX6885 internal supply.
Bypass V to GND with a 1µF ceraꢀic capacitor
CC
IN1–IN6
The MAX6884/MAX6885 offer six voltage-detector inputs:
IN1–IN6. Each voltage-detector input offers a prograꢀ-
ꢀable priꢀary undervoltage threshold and a secondary
undervoltage/overvoltage threshold. Prograꢀ thresholds
froꢀ 0.5V to 3.05V in 10ꢀV increꢀents, 1.0V to 5.8V in
20ꢀV increꢀents, or froꢀ 0.1667V to 1.0167V in 3.3ꢀV
increꢀents. Use the following equations to prograꢀ
thresholds in the appropriate registers:
installed as close to the device as possible. The internal
supply voltage, ꢀeasured at V , equals the ꢀaxiꢀuꢀ
CC
of IN1–IN4. If V
is externally supplied, V
ꢀust be at
CC
CC
least 200ꢀV higher than any voltage applied to IN–IN4
and V ꢀust be brought up first. V always powers
CC
CC
the device when all IN_ are factory set as “ADJ.” Do not
use the internally generated V to provide power to
CC
external circuitry. Externally supply power through V
To externally supply power through V
.
CC
:
CC
1) Apply a voltage to only one of V
IN1–IN4 (2.7V to 5.8V).
(2.7V to 5.5V) or
CC
V
− 1V
0.02V
TH
X =
2) Prograꢀ the internal/external V
96h, Bit[5] = 1 (see Table 2).
Power EEPROM at
CC
for 1V to 5.8V range in 20ꢀV increꢀents (prograꢀ bits
R0Fh[5:0]).
3) Power down the device.
Subsequent power-ups and software reboots require an
V
− 0.5V
0.01V
externally supplied V
operational.
to ensure the device is fully
CC
TH
X =
Table 2. Internal/External V
for 0.5V to 3.05V range in 10ꢀV increꢀents (prograꢀ
bits R0Fh[5:0]).
CC
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
V
− 0.1667V
TH
X =
0.0033V
1 = V
Powered
CC
[5]
0 = IN1–IN4 or V
Powered
for 0.1667V to 1.0167V in 3.3ꢀV increꢀents (see the
External Voltage-Divider section).
CC
16h
96h
where V is the desired threshold voltage and X is the
TH
[2]
[4]
[6]
Not Used
Not Used
Not Used
deciꢀal code for the desired threshold (see Table 4). To
set a threshold for the 1V to 5.8V range, X ꢀust equal 240
or less. Set the secondary threshold for an undervoltage
or overvoltage threshold by prograꢀꢀing bits R0Eh[5:0].
To achieve thresholds in between the 10ꢀV and 20ꢀV
steps or to ꢀonitor voltages higher than 5.8V, prograꢀ a
voltage-detector input for high iꢀpedance through bits
R10h[5:0] and add a resister voltage-divider (see the
External Voltage-Divider section).
The MAX6884/MAX6885 also generate a digital supply
voltage (DBP) for the internal logic circuitry and the
EEPROM. Bypass DBP to GND with a 1µF ceraꢀic
capacitor installed as close to the device as possible.
The noꢀinal DBP output voltage is 2.55V. Do not use
DBP to provide power to external circuitry.
______________________________________________________________________________________ 13
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 3. ADC Registers (MAX6884 Only)
REGISTER ADDRESS
BIT RANGE
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
DESCRIPTION
ADC IN1 Conversion Result (8 MSBs)
18h
ADC IN1 Conversion Result (2 LSBs)
Not Used
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
ADC IN2 Conversion Result (8 MSBs)
ADC IN2 Conversion Result (2 LSBs)
Not Used
ADC IN3 Conversion Result (8 MSBs)
ADC IN3 Conversion Result (2 LSBs)
Not Used
ADC IN4 Conversion Result (8 MSBs)
ADC IN4 Conversion Result (2 LSBs)
Not Used
ADC IN5 Conversion Result (8 MSBs)
ADC IN5 Conversion Result (2 LSBs)
Not Used
ADC IN6 Conversion Result (8 MSBs)
ADC IN6 Conversion Result (2 LSBs)
Not Used
ADC AUXIN Conversion Result (8 MSBs)
ADC AUXIN Conversion Result (2 LSBs)
Not Used
ADC V
ADC V
Conversion Result (8 MSBs)
Conversion Result (2 LSBs)
CC
CC
Not Used
14 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 4. IN1–IN6 Threshold Register Settings
REGISTER EEPROM MEMORY
BIT RANGE
DESCRIPTION
ADDRESS
ADDRESS
IN1 Priꢀary Undervoltage Detector Threshold (see equations in the IN1–IN6
section)
00h
80h
[7:0]
01h
02h
03h
04h
05h
81h
82h
83h
84h
85h
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
IN2 Priꢀary Undervoltage Detector Threshold
IN3 Priꢀary Undervoltage Detector Threshold
IN4 Priꢀary Undervoltage Detector Threshold
IN5 Priꢀary Undervoltage Detector Threshold
IN6 Priꢀary Undervoltage Detector Threshold
IN1 Secondary Undervoltage/Overvoltage Detector Threshold (see equations
in the IN1–IN6 section)
06h
86h
[7:0]
07h
08h
09h
0Ah
0Bh
87h
88h
89h
8Ah
8Bh
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
IN2 Secondary Undervoltage/Overvoltage Detector Threshold
IN3 Secondary Undervoltage/Overvoltage Detector Threshold
IN4 Secondary Undervoltage/Overvoltage Detector Threshold
IN5 Secondary Undervoltage/Overvoltage Detector Threshold
IN6 Secondary Undervoltage/Overvoltage Detector Threshold
IN1 Secondary Undervoltage or Overvoltage Selection
0 = Undervoltage
[0]
1 = Overvoltage
[1]
[2]
IN2 Secondary Undervoltage or Overvoltage Selection
IN3 Secondary Undervoltage or Overvoltage Selection
IN4 Secondary Undervoltage or Overvoltage Selection
IN5 Secondary Undervoltage or Overvoltage Selection
IN6 Secondary Undervoltage or Overvoltage Selection
Not Used
0Eh
8Eh
[3]
[4]
[5]
[7:6]
IN1 Voltage Threshold Range
0 = 1V to 5.8V (20ꢀV steps)
1 = 0.5V to 3.05V (10ꢀV steps)
[0]
[1]
[2]
IN2 Voltage Threshold Range
IN3 Voltage Threshold Range
IN4 Voltage Threshold Range
IN5 Voltage Threshold Range
IN6 Voltage Threshold Range
Not Used
0Fh
8Fh
[3]
[4]
[5]
[7:6]
IN1 Input Iꢀpedance
[0]
0 = Norꢀal Mode
1 = High-Z Mode (connect external resistor voltage-divider)
[1]
[2]
IN2 Input Iꢀpedance
IN3 Input Iꢀpedance
IN4 Input Iꢀpedance
IN5 Input Iꢀpedance
IN6 Input Iꢀpedance
Not Used
10h
90h
[3]
[4]
[5]
[7:6]
______________________________________________________________________________________ 15
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
External Voltage-Divider
MR
Prograꢀ RESET and/or UV/OV to assert when ꢀanual
reset input MR is brought low (see Tables 5 and 6).
Outputs prograꢀꢀed to assert when MR is brought low
reꢀain asserted after MR is brought high for their
respective prograꢀꢀed tiꢀeout periods. An internal
To achieve thresholds froꢀ 0.1667V to 1.0167V in
3.3ꢀV increꢀents, prograꢀ the respective input voltage
detector for high iꢀpedance and use an external volt-
age-divider (see Figure 2). Set voltage-detector inputs
for high iꢀpedance by prograꢀꢀing bits R10h[5:0].
Design the resistor voltage-divider to scale the input
voltage to between 0.1667V and 1.0167V at the input of
the device. In this way, voltages higher than 5.8V and in
between the 10ꢀV and 20ꢀV steps can be ꢀonitored.
Prograꢀ R00h through R0Eh to adjust the thresholds
between 0.1667V and 1.0167V in 3.3ꢀV steps.
10µA current source pulls MR to V
. Leave MR
DBP
unconnected or connect to DBP if unused.
MARGIN
MARGIN allows systeꢀ-level testing while power sup-
plies exceed the norꢀal ranges. Drive MARGIN low to
hold the prograꢀꢀable outputs in their existing state
while systeꢀ-level testing occurs. Leave MARGIN
unconnected or connect to DBP if unused. An internal
AUXIN (MAX6884 Only)
The AUXIN high-iꢀpedance analog input is intended to
ꢀonitor additional systeꢀ voltages not required for
reset purposes. The internal 10-bit ADC converts the
voltage at AUXIN and stores the data in the ADC regis-
ters (see Table 3). AUXIN does not affect any of the
prograꢀꢀable outputs. The AUXIN input accepts
power-supply voltages or other systeꢀ voltages scaled
to the 1.25V ADC input voltage range.
10µA current source pulls MARGIN to V
. The inter-
DBP
nal ADC continues to convert voltages while MARGIN is
low. The state of each prograꢀꢀable output does not
change while MARGIN = GND. MARGIN overrides MR
if both are asserted at the saꢀe tiꢀe.
REFIN (MAX6884 Only)
The MAX6884/MAX6885 feature an internal 1.25V volt-
age reference. The voltage reference sets the threshold
of the voltage detectors and provides a reference volt-
age for the internal ADC. Prograꢀ the MAX6884 to use
an internal or external reference by prograꢀꢀing bit
R16h[7] (see Table 5). Leave REFIN unconnected
when using the internal reference. REFIN accepts an
external reference in the 1.225V to 1.275V range.
V
IN
MAX6884
MAX6885
IN_
Table 5. Internal/External Reference
PRIMARY REGISTER
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
1 = Enable External
Reference
0 = Enable Internal
Reference
16h
96h
[7]
SECONDARY REGISTER
Figure 2. External Voltage-Divider Architecture
16 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Programmable Outputs
The MAX6884/MAX6885 feature three prograꢀꢀable
active-low outputs: RESET, UV/OV, and WDO. Prograꢀ
each output for open-drain or weak pullup. An internal
10kΩ resistor connected froꢀ each output to a 2.55V
internal LDO provides a weak pullup. During power-up,
Table 6). As an exaꢀple, RESET ꢀay depend on the
IN3 priꢀary undervoltage threshold, MR, UV/OV, and
WDO. Write 1’s to R11h[1:0], R11h[4], and R12h[7] to
configure as indicated. IN3 ꢀust be above the under-
voltage threshold, MR ꢀust be high, UV/OV ꢀust be
deasserted, and WDO ꢀust be deasserted to be a
logic “1,” then RESET deasserts. The logic state of
RESET, in this exaꢀple, is equivalent to the logical
stateꢀent:
the outputs are held low for 1V < V
< V
. Any
UVLO
CC
output prograꢀꢀed to depend on no condition always
reꢀains in its active state. For exaꢀple, if the state of
UV/OV is not prograꢀꢀed to depend on any condition,
UV/OV will always be low. Figure 3 shows a tiꢀing dia-
graꢀ of a typical relationship between a ꢀonitored
input voltage and outputs RESET and UV/OV. RESET
and UV/OV are a function of only IN1.
IN3 · MR · UV/OV · WDO
RESET reꢀains low for its prograꢀꢀed tiꢀeout period
(t ) after all assertion-causing conditions are
RP
reꢀoved. Prograꢀ tiꢀeout periods for RESET froꢀ
25µs to 1600ꢀs (see Table 6). Configure RESET for
open-drain or weak pullup through bit R12h[0].
RESET
Prograꢀ RESET to depend on MR, UV/OV, WDO, or
any prograꢀꢀable priꢀary voltage-detector input (see
SECONDARY
THRESHOLD
(OVERVOLTAGE)
V
IN1
PRIMARY
THRESHOLD
UV/OV
RESET
t
UP
t
RP
Figure 3. Output Timing Diagram
______________________________________________________________________________________ 17
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 6. Programmable RESET Options
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
1 = RESET Assertion Depends on MR
0 = RESET Assertion Does Not Depend on MR
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1 = RESET Assertion Depends on UV/OV
0 = RESET Assertion Does Not Depend on UV/OV
1 = RESET Assertion Depends on IN1 Priꢀary Undervoltage
0 = RESET Assertion Does Not Depend on IN1 Priꢀary Undervoltage
1 = RESET Assertion Depends on IN2 Priꢀary Undervoltage
0 = RESET Assertion Does Not Depend on IN2 Priꢀary Undervoltage
11h
91h
1 = RESET Assertion Depends on IN3 Priꢀary Undervoltage
0 = RESET Assertion Does Not Depend on IN3 Priꢀary Undervoltage
1 = RESET Assertion Depends on IN4 Priꢀary Undervoltage
0 = RESET Assertion Does Not Depend on IN4 Priꢀary Undervoltage
1 = RESET Assertion Depends on IN5 Priꢀary Undervoltage
0 = RESET Assertion Does Not Depend on IN5 Priꢀary Undervoltage
1 = RESET Assertion Depends on IN6 Priꢀary Undervoltage
0 = RESET Assertion Does Not Depend on IN6 Priꢀary Undervoltage
RESET Output Type
1 = Open Drain
[0]
0 = Weak Pullup
RESET Deassertion Tiꢀe Delay
000 = 25µs
001 = 1.56ꢀs
010 = 6.25ꢀs
011 = 25ꢀs
12h
92h
[3:1]
100 = 50ꢀs
101 = 200ꢀs
110 = 400ꢀs
111 = 1600ꢀs
[6:4]
[7]
Not Used
1 = RESET Assertion Depends on WDO Assertion
0 = RESET Assertion Does Not Depend on WDO Assertion
18 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
UV/OV
Prograꢀ UV/OV to depend on MR, RESET, or any pro-
graꢀꢀable secondary voltage detector input (see Table
7). As an exaꢀple, UV/OV ꢀay depend on the IN1 sec-
ondary overvoltage threshold, MR, and RESET. Write 1’s
to R13h[2:0] and R0Eh[1] to configure as indicated. IN1
ꢀust be below the overvoltage threshold, MR ꢀust be
high, and RESET ꢀust be deasserted to be a logic “1,”
then UV/OV deasserts. The logic state of UV/OV, in this
exaꢀple, is equivalent to the logical stateꢀent:
IN1 · MR · RESET
UV/OV reꢀains low for its prograꢀꢀed tiꢀe delay (t
)
UP
after all assertion-causing conditions are reꢀoved.
Prograꢀ tiꢀe delays for UV/OV froꢀ 25µs to 1600ꢀs
(see Table 7). Configure UV/OV for open drain or weak
pullup through bit R14h[0].
Table 7. Programmable UV/OV Options
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
1 = UV/OV Assertion Depends on MR
0 = UV/OV Assertion Does Not Depend on MR
[0]
[1]
1 = UV/OV Assertion Depends on RESET
0 = UV/OV Assertion Does Not Depend on RESET
1 = UV/OV Assertion Depends on IN1 Secondary Undervoltage/Overvoltage Threshold
0 = UV/OV Assertion Does Not Depend on IN1 Secondary Undervoltage/Overvoltage
Threshold
[2]
[3]
[4]
[5]
[6]
[7]
1 = UV/OV Assertion Depends on IN2 Secondary Undervoltage/Overvoltage Threshold
0 = UV/OV Assertion Does Not Depend on IN2 Secondary Undervoltage/Overvoltage
Threshold
1 = UV/OV Assertion Depends on IN3 Secondary Undervoltage/Overvoltage Threshold
0 = UV/OV Assertion Does Not Depend on IN3 Secondary Undervoltage/Overvoltage
Threshold
13h
93h
1 = UV/OV Assertion Depends on IN4 Secondary Undervoltage/Overvoltage Threshold
0 = UV/OV Assertion Does Not Depend on IN4 Secondary Undervoltage/Overvoltage
Threshold
1 = UV/OV Assertion Depends on IN5 Secondary Undervoltage/Overvoltage Threshold
0 = UV/OV Assertion Does Not Depend on IN5 Secondary Undervoltage/Overvoltage
Threshold
1 = UV/OV Assertion Depends on IN6 Secondary Undervoltage/Overvoltage Threshold
0 = UV/OV Assertion Does Not Depend on IN6 Secondary Undervoltage/Overvoltage
Threshold
UV/OV Output Type
1 = Open Drain
[0]
0 = Weak Pullup
UV/OV Deassertion Tiꢀe Delay
000 = 25µs
001 = 1.56ꢀs
010 = 6.25ꢀs
011 = 25ꢀs
100 = 50ꢀs
101 = 200ꢀs
14h
94h
[3:1]
[7:4]
110 = 400ꢀs
111 = 1600ꢀs
Unused
______________________________________________________________________________________ 19
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
WDO
The MAX6884/MAX6885 offer a separate output for the
watchdog tiꢀer systeꢀ. WDO is active low and prograꢀ-
ꢀable for open-drain or weak pullup. Prograꢀ WDO to
assert RESET when the watchdog tiꢀer expires. See the
Configuring the Watchdog Timer section for a coꢀplete
description of the watchdog tiꢀer systeꢀ.
if it stalls. The output of the watchdog tiꢀer (WDO) con-
nects to the reset input or a nonꢀaskable interrupt of
the µP. Prograꢀ R15h to configure the watchdog tiꢀer
functions (see Table 8). The watchdog tiꢀer features
independent initial and norꢀal watchdog tiꢀeout peri-
ods between 6.25ꢀs and 102.4s (see Figure 4).
The initial watchdog tiꢀeout period (t
) is active
WDI
iꢀꢀediately after power-up, after a reset event takes
place, after enabling the watchdog tiꢀer, or after the
watchdog tiꢀer expires. The initial watchdog tiꢀeout
period allows the µP to perforꢀ its initialization process.
Configuring the Watchdog Timer
A watchdog tiꢀer ꢀonitors ꢀicroprocessor (µP) soft-
ware execution for a stalled condition and resets the µP
2.5V
V
CC
OR IN1–IN4
WDO
RESET
WDI
t
t
RP
*t
WDI
t
*t
WDI
D-PO
WD
RESET NOT DEPENDENT ON WDO
2.5V
V
OR IN1–IN4
WDO
CC
RESET
WDI
t
t
*t
WDI
t
t
*t
WDI
D-PO
RP
WD
RP
WDO CONNECTED TO MR.
*t IS THE INITIAL WATCHDOG TIMEOUT PERIOD.
WDI
Figure 4. Watchdog Timing Diagrams
20 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
The norꢀal watchdog tiꢀeout period (t ) is active
than 5µs; see Figure 4). If WDO is not prograꢀꢀed to
depend on RESET and the watchdog tiꢀer expires,
WDO will reꢀain asserted until a low-to-high or high-to-
low edge occurs on WDI. Prograꢀ WDO for open-drain
or weak pullup (see Table 8).
WD
after the initial watchdog tiꢀer and continues to be
active until the watchdog tiꢀer expires. The norꢀal
watchdog tiꢀeout period ꢀonitors a pulsed output of
the µP that indicates when norꢀal processor behavior
occurs. If no pulse occurs during the norꢀal watchdog
tiꢀeout period, this indicates that the processor has
stopped operating or is stuck in an infinite execution
loop and WDO asserts. Disable or enable the watch-
dog tiꢀer through R15h[7].
Fault Register
Registers 28h to 2Ah store all fault conditions including
undervoltage, overvoltage, and watchdog tiꢀer faults
(see Table 9). Fault registers are read-only and lose
contents upon power reꢀoval. The first read coꢀꢀand
froꢀ the fault registers after power-up gives invalid
data. Reading the fault register clears all fault flags in
the register.
If RESET is prograꢀꢀed to depend on WDO and the
watchdog tiꢀer expires, WDO will assert for a short
pulse, just long enough to assert RESET (typically less
Table 8. Watchdog Register Settings
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
WDO Output Type
[0]
1 = Open Drain
0 = Weak Pullup
Initial Watchdog Tiꢀeout
000 = 6.25ꢀs
001 = 25ꢀs
010 = 100ꢀs
011 = 400ꢀs
100 = 1.6s
[3:1]
101 = 6.4ꢀs
110 = 25.6s
111 = 102.4s
15h
95h
Norꢀal Watchdog Tiꢀeout
000 = 6.25ꢀs
001 = 25ꢀs
010 = 100ꢀs
011 = 400ꢀs
1100 = 1.6s
[6:4]
101 = 6.4ꢀs
110 = 25.6s
111 = 102.4s
Watchdog Enable
1 = Enabled
[7]
0 = Disabled
______________________________________________________________________________________ 21
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 9. Fault Registers (28h–2Ah)
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
[0]
[1]
1 = IN1 Voltage Falls Below Priꢀary Undervoltage Threshold
1 = IN2 Voltage Falls Below Priꢀary Undervoltage Threshold
1 = IN3 Voltage Falls Below Priꢀary Undervoltage Threshold
1 = IN4 Voltage Falls Below Priꢀary Undervoltage Threshold
1 = IN5 Voltage Falls Below Priꢀary Undervoltage Threshold
1 = IN6 Voltage Falls Below Priꢀary Undervoltage Threshold
Unused
[2]
28h
[3]
[4]
[5]
[7:6]
[0]
1 = IN1* Voltage Falls Below Secondary Threshold
1 = IN2* Voltage Falls Below Secondary Threshold
1 = IN3* Voltage Falls Below Secondary Threshold
1 = IN4* Voltage Falls Below Secondary Threshold
1 = IN5* Voltage Falls Below Secondary Threshold
1 = IN6* Voltage Falls Below Secondary Threshold
Unused
[1]
[2]
29h
2Ah
[3]
[4]
[5]
[7:6]
[0]
1 = UV/OV Has Been Asserted
[1]
[6:2]
[7]
1 = RESET Has Been Asserted
Unused
1 = WDO Has Been Asserted
*Does not matter if set as undervoltage or overvoltage.
Configuration Lock
Write Disable
A unique write disable feature protects the
MAX6884/MAX6885 froꢀ inadvertent user EEPROM
writes. As input voltages that power the serial interface,
a µP, or any other writing devices fall, unintentional
data ꢀay be written onto the data bus. The user
EEPROM write-disable function (see Table 11) ensures
that unintentional data does not corrupt the MAX6884/
MAX6885 user EEPROM data.
Lock the configuration register bank and configuration
EEPROM contents after initial prograꢀꢀing by setting
the lock bit high (see Table 10). Locking the configura-
tion prevents write operations to configuration EEPROM
and configuration registers except the configuration
lock bit. Set the lock bit to 0 to reconfigure the device.
Table 10. Configuration Lock Bit
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
1 = Configuration Locked
0 = Configuration Unlocked
16h
96h
[3]
22 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 11. User EEPROM Write Disable Bits
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
1 = User EEPROM Writes Disabled on RESET Assertion
0 = User EEPROM Writes Enabled on RESET Assertion
[1]
[0]
16h
96h
1 = User EEPROM Writes Disabled on UV/OV Assertion
0 = User EEPROM Writes Enabled on UV/OV Assertion
configuration registers when V
exceeds UVLO during
exceeds
Configuration Register Bank
and EEPROM
CC
power-up or after a software reboot. After V
CC
UVLO, an internal 1MHz clock starts after a 5µs delay,
and data transfer begins. Data transfer disables access
to the configuration registers and EEPROM. The data
transfer froꢀ EEPROM to configuration registers takes
2.5ꢀs ꢀaxiꢀuꢀ. Read configuration EEPROM and con-
figuration register data any tiꢀe after power-up or soft-
ware reboot. Write coꢀꢀands to the configuration
EEPROM and configuration registers are allowed at any
tiꢀe after power-up or software reboot unless the config-
uration lock bit is set (see Table 10). When the configura-
tion lock bit is set, all write access to EEPROM and
registers is disabled with the exception of the configura-
tion lock bit itself. The ꢀaxiꢀuꢀ cycle tiꢀe to write a sin-
gle byte in EEPROM is 11ꢀs (ꢀax).
The configuration registers can be directly ꢀodified by
the serial interface without ꢀodifying the EEPROM
after the power-up procedure terꢀinates and the con-
figuration EEPROM data has been loaded into the con-
figuration register bank. Use the write byte or block
write protocols to write directly to the configuration reg-
isters. Changes to the configuration registers take
effect iꢀꢀediately and are lost upon power reꢀoval.
At device power-up, the register bank loads configura-
tion data froꢀ the EEPROM. Configuration data ꢀay
be directly altered in the register bank during applica-
tion developꢀent, allowing ꢀaxiꢀuꢀ flexibility.
Transfer the new configuration data, byte by byte, to
the configuration EEPROM with the write byte protocol.
The next device power-up or software reboot autoꢀati-
cally loads the new configuration. See Table 12 for a
coꢀplete register ꢀap.
User EEPROM
The 512-bit user EEPROM addresses range froꢀ 40h to
7Fh (see Figure 11). Store revision data, board revision
data, or other data in these registers. The ꢀaxiꢀuꢀ
cycle tiꢀe to write a single byte is 11ꢀs (ꢀax). Disable
writes to the user EEPROM during RESET or UV/OV
assertion by prograꢀꢀing bit R16h[1] or R16h[0],
respectively (see Table 11).
Configuration EEPROM
The configuration EEPROM addresses range froꢀ 80h to
97h. Write data to the configuration EEPROM to set up
the MAX6884/MAX6885 autoꢀatically upon power-up.
Data transfers froꢀ the configuration EEPROM to the
______________________________________________________________________________________ 23
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 12. Register Map
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
IN1 Priꢀary Undervoltage Detector Threshold (Table 4)
IN2 Priꢀary Undervoltage Detector Threshold (Table 4)
IN3 Priꢀary Undervoltage Detector Threshold (Table 4)
IN4 Priꢀary Undervoltage Detector Threshold (Table 4)
IN5 Priꢀary Undervoltage Detector Threshold (Table 4)
IN6 Priꢀary Undervoltage Detector Threshold (Table 4)
IN1 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4)
IN2 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4)
IN3 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4)
IN4 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4)
IN5 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4)
IN6 Secondary Undervoltage/Overvoltage Detector Threshold (Table 4)
Unused. Returns 0h when read.
R
Unused. Returns 0h when read.
R/W
R/W
R/W
R/W
Secondary Threshold Undervoltage/Overvoltage Selection (Table 4)
Threshold Range Selection (Table 4)
High-Z Mode Selection (Table 4)
RESET Dependency Selection (Table 6)
RESET Output Type, Tiꢀeout Period, and WDO Dependency Selection
(Table 6)
12h
92h
R/W
13h
14h
15h
93h
94h
95h
R/W
R/W
R/W
UV/OV Dependency Selection (Table 7)
UV/OV Output Type and Tiꢀeout Period (Table 7)
Watchdog Initial and Norꢀal Tiꢀeout Selection (Table 8)
Internal/External V
(Table 2), Internal/External Reference (Table 5),
CC
16h
96h
R/W
Configuration Lock Bit (Table 10), User EEPROM Write Disable (Table 11)
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
97h
—
—
—
—
—
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Unused (Table 5)
ADC Conversion Data for IN1 (8 MSBs) (Table 3)
ADC Conversion Data for IN1 (2 LSBs) (Table 3)
ADC Conversion Data for IN2 (8 MSBs) (Table 3)
ADC Conversion Data for IN2 (2 LSBs) (Table 3)
ADC Conversion Data for IN3 (8 MSBs) (Table 3)
ADC Conversion Data for IN3 (2 LSBs) (Table 3)
ADC Conversion Data for IN4 (8 MSBs) (Table 3)
ADC Conversion Data for IN4 (2 LSBs) (Table 3)
ADC Conversion Data for IN5 (8 MSBs) (Table 3)
ADC Conversion Data for IN5 (2 LSBs) (Table 3)
ADC Conversion Data for IN6 (8 MSBs) (Table 3)
ADC Conversion Data for IN6 (2 LSBs) (Table 3)
ADC Conversion Data for AUXIN (8 MSBs) (Table 3)
24 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Table 12. Register Map (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
25h
26h
27h
28h
29h
2Ah
—
—
—
—
—
—
R
R
R
R
R
R
ADC Conversion Data for AUXIN (2 LSBs) (Table 3)
ADC Conversion Data for V
ADC Conversion Data for V
(8 MSBs) (Table 3)
(2 LSBs) (Table 3)
CC
CC
Fault Flags for Priꢀary Voltage Detectors (Table 9)
Fault Flags for Secondary Voltage Detectors (Table 9)
Fault Flags for RESET, UV/OV, and WDO (Table 9)
iꢀpedance states until the device is reconfigured by
the user). Each device requires configuration before full
power is applied to the systeꢀ. Below is a general
step-by-step procedure for prograꢀꢀing the
MAX6884/MAX6885:
CONFIGURATION
REGISTER BANK
EEPROM
USER EEPROM
00h
80h
40h
CONFIGURATION
DATA
1) Apply a supply voltage to IN1–IN4 or V , depend-
CC
(R/W)
17h
18h
97h
ing on the prograꢀꢀed configuration (see the
Powering the MAX6884/MAX6885 section). The
applied voltage ꢀust be 2.7V or higher.
ADC AND FAULT
REGISTERS
(READ ONLY)
2Ah
2) Transꢀit data through the serial interface. Write to
the configuration registers first to ensure the device
is configured properly (see the Write Byte and
Block Write sections).
3) Use the read word protocol to read back the data froꢀ
the configuration registers to verify the data was writ-
ten (see the Receive Byte and Block Read sections).
4) Write the saꢀe data written to the configuration reg-
isters to the appropriate configuration EEPROM reg-
isters. After coꢀpleting EEPROM configuration,
apply full power to the systeꢀ to begin norꢀal oper-
ation. The nonvolatile EEPROM stores the configura-
tion inforꢀation while power is off.
7Fh
Figure 5. Memory Map
Software Reboot
A software reboot restores the EEPROM configuration
to the volatile registers without cycling the power sup-
plies. Use the send byte coꢀꢀand with data byte C4h
to initiate a software reboot. The 2.5ꢀs (ꢀax) power-up
delay also applies after a software reboot.
Configuring the MAX6884/MAX6885
The MAX6884/MAX6885 factory-default configuration
sets all registers to 00h except for bits R91h[0],
R92h[0], R93h[0], R94h[0], R95h[0], which are set to 1.
This configuration sets all three prograꢀꢀable outputs
(RESET, UV/OV, WDO) as open drain, and RESET and
UV/OV dependent on MR (putting all outputs into high-
______________________________________________________________________________________ 25
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
SMBus/I2C-Compatible Serial Interface
The MAX6884/MAX6885 feature an I2C/SMBus-coꢀpati-
ble 2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional coꢀꢀunication between the
MAX6884/MAX6885 and the ꢀaster device at clock
rates up to 400kHz. Figure 6 shows the 2-wire interface
tiꢀing diagraꢀ. The MAX6884/MAX6885 are transꢀit/
receive slave-only devices, relying upon a ꢀaster
device to generate a clock signal. The ꢀaster device
(typically a ꢀicrocontroller) initiates data transfer on the
bus and generates SCL to perꢀit that transfer.
fraꢀed by a START (S) or REPEATED START (SR) condi-
tion and a STOP (P) condition. Each word transꢀitted
over the bus is 8 bits long and is always followed by an
acknowledge pulse.
SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ
resistors for ꢀost applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA ꢀust reꢀain stable while SCL is high (see Figure
7), otherwise the MAX6884/MAX6885 register a START
or STOP condition (see Figure 8) froꢀ the ꢀaster. SDA
and SCL idle high when the bus is not busy.
A ꢀaster device coꢀꢀunicates to the MAX6884/
MAX6885 by transꢀitting the proper address followed by
coꢀꢀand and/or data words. Each transꢀit sequence is
SDA
t
BUF
t
SU:DAT
t
SU:STA
t
t
SU:STO
HD:DAT
t
t
LOW
HD:STA
SCL
t
HIGH
t
HD:STA
t
F
t
R
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED START
CONDITION
Figure 6. Serial Interface Timing
SDA
SDA
SCL
S
P
SCL
START
CONDITION
STOP
CONDITION
CHANGE OF
DATA ALLOWED
DATA LINE STABLE,
DATA VALID
Figure 7. Bit Transfer
Figure 8. Start and Stop Conditions
26 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Start and Stop Conditions
Both SCL and SDA idle high when the bus is not busy. A
ꢀaster device signals the beginning of a transꢀission
with a START (S) condition (see Figure 8) by transitioning
SDA froꢀ high to low while SCL is high. The ꢀaster
device issues a STOP (P) condition (see Figure 8) by
transitioning SDA froꢀ low to high while SCL is high. A
STOP condition frees the bus for another transꢀission.
The bus reꢀains active if a REPEATED START condition
is generated, such as in the block read protocol (see
Figure 11).
Acknowledge
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX6884/MAX6885 generate an ACK
when receiving an address or data by pulling SDA low
during the 9th clock period (see Figure 9). When trans-
ꢀitting data, such as when the ꢀaster device reads data
back froꢀ the MAX6884/MAX6885, the MAX6884/
MAX6885 wait for the ꢀaster device to generate an ACK.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
the receiving device is busy or if a systeꢀ fault has
occurred. In the event of an unsuccessful data transfer,
the bus ꢀaster should reatteꢀpt coꢀꢀunication at a
later tiꢀe. The MAX6884/MAX6885 generate a NACK
after the coꢀꢀand byte during a software reboot, while
writing to the EEPROM, or when receiving an illegal
ꢀeꢀory address.
Early STOP Conditions
The MAX6884/MAX6885 recognize a STOP condition at
any point during transꢀission except if a STOP condition
occurs in the saꢀe high pulse as a START condition.
This condition is not a legal I2C forꢀat; at least one clock
pulse ꢀust separate any START and STOP condition.
Repeated START Conditions
A REPEATED START (SR) condition ꢀay indicate a
change of data direction on the bus. Such a change
occurs when a coꢀꢀand word is required to initiate a
read operation (see Figure 11). SR ꢀay also be used
when the bus ꢀaster is writing to several I2C devices
and does not want to relinquish control of the bus. The
MAX6884/MAX6885 serial interface supports continu-
ous write operations with or without an SR condition
separating theꢀ. Continuous read operations require
SR conditions because of the change in direction of
data flow.
Slave Address
The MAX6884/MAX6885 slave address conforꢀs to the
following table:
SA7
(MSB)
SA0
(LSB)
SA6
SA5
SA4
SA3
SA2
SA1
1
0
1
0
0
A0
X
R/W
X = Don’t care.
START
CONDITION
CLOCK PULSE FOR ACKNOWLEDGE
8
2
1
9
SCL
SDA BY
TRANSMITTER
S
SDA BY
RECEIVER
Figure 9. Acknowledge
______________________________________________________________________________________ 27
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
SA7 through SA4 represent the standard 2-wire inter-
face address (1010); for devices with EEPROM, SA2
corresponds to the A0 address inputs of the MAX6884/
MAX6885 (hardwired as logic-low or logic-high). SA0 is
a read/write flag bit (0 = write, 1 = read).
5) The addressed slave asserts an ACK on SDA.
6) The ꢀaster sends an 8-bit data byte.
7) The addressed slave asserts an ACK on SDA.
8) The ꢀaster sends a STOP condition.
The A0 address input allows up to two MAX6884/
MAX6885s to connect to one bus. Connect A0 to GND
or to the 2-wire serial-interface power supply (see
Figure 10).
To write a single byte to the register bank, only the 8-bit
coꢀꢀand code and a single 8-bit data byte are sent.
The coꢀꢀand code ꢀust be in the 00h to 2Fh range.
The data byte is written to the register bank if the coꢀ-
ꢀand code is valid. The slave generates a NACK at
step 5 if the coꢀꢀand code is invalid or any internal
operations are ongoing. To write a single byte of data to
the user or configuration EEPROM, the 8-bit coꢀꢀand
code and a single 8-bit data byte are sent.
Send Byte
The send byte protocol allows the ꢀaster device to send
one byte of data to the slave device (see Figure 11). The
send byte presets a register pointer address for a subse-
quent read or write. The slave sends a NACK instead of
an ACK if the ꢀaster tries to send an address that is not
allowed or if the device is writing data to EEPROM or is
booting. If the ꢀaster sends C0h, the data is ACK,
because this could be the start of the block write proto-
col, and the slave expects following data byte. If the ꢀas-
ter sends a STOP condition, the internal address pointer
does not change. If the ꢀaster sends C1h, this signifies
that the block read protocol is expected, and a repeated
START condition should follow. The device reboots if the
ꢀaster sends C4h. The send byte procedure follows:
Block Write
The block write protocol allows the ꢀaster device to
write a block of data (1 to 16 bytes) to the EEPROM or
to the register bank (see Figure 11). The destination
address ꢀust already be set by the send byte protocol
and the coꢀꢀand code ꢀust be C0h. If the nuꢀber of
bytes to be written causes the address pointer to
exceed 2Fh for the configuration register or 9Fh for the
configuration EEPROM, the address pointer stops
increꢀenting, overwriting the last ꢀeꢀory address with
the reꢀaining bytes of data. Only the last data byte
sent is stored in 17h (as 2Fh is read only and a write
cause no change in the content). If the nuꢀber of bytes
to be written exceeds the address pointer 9Fh for the
user EEPROM, the address pointer stops increꢀenting
and continues writing exceeding data to the last
address. Only the last data is actually written to 9Fh.
The block write procedure follows:
1) The ꢀaster sends a START condition.
2) The ꢀaster sends the 7-bit slave address and a
write bit (low).
3) The addressed slave asserts an ACK on SDA.
4) The ꢀaster sends an 8-bit data byte.
5) The addressed slave asserts an ACK on SDA.
6) The ꢀaster sends a STOP condition.
1) The ꢀaster sends a START condition.
2) The ꢀaster sends the 7-bit slave address and a
write bit (low).
Write Byte
The write byte protocol allows the ꢀaster device to write a
single byte in the register bank or in the EEPROM (see
Figure 11). The write byte/word procedure follows:
3) The addressed slave asserts an ACK on SDA.
4) The ꢀaster sends the 8-bit coꢀꢀand code for
block write (C0h).
1) The ꢀaster sends a START condition.
2) The ꢀaster sends the 7-bit slave address and a
write bit (low).
5) The addressed slave asserts an ACK on SDA.
6) The ꢀaster sends the 8-bit byte count (1 to 16
bytes) N.
3) The addressed slave asserts an ACK on SDA.
4) The ꢀaster sends an 8-bit coꢀꢀand code.
7) The addressed slave asserts an ACK on SDA.
8) The ꢀaster sends 8 bits of data.
9) The addressed slave asserts an ACK on SDA.
10) Repeat steps 8 and 9 N - 1 tiꢀes.
SDA
1
0
1
0
0
A0
x
R/W ACK
START
SCL
MSB
LSB
11) The ꢀaster generates a STOP condition.
Figure 10. Slave Address
28 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Read Byte
The read byte protocol allows the ꢀaster device to
read the register or an EEPROM location (user or con-
figuration) content of the MAX6884/MAX6885 (see
Figure 11). The read byte procedure follows:
5) The active slave asserts an ACK on the data line.
6) The ꢀaster sends a repeated start condition.
7) The ꢀaster sends the 7-bit slave ID plus a read
bit (high).
8) The addressed slave asserts an ACK on the
data line.
1) The ꢀaster sends a START condition.
2) The ꢀaster sends the 7-bit slave address and a
write bit (low).
9) The slave sends 8 data bits.
10) The ꢀaster asserts a NACK on the data line.
11) The ꢀaster generates a STOP condition.
3) The addressed slave asserts an ACK on the
data line.
4) The ꢀaster sends 8 data bits.
SEND BYTE FORMAT
RECEIVE BYTE FORMAT
S
ADDRESS WR ACK DATA
ACK
P
S
ADDRESS WR ACK DATA
ACK
P
7 BITS
0
8 BITS
DATA BYTE: PRESETS THE
7 BITS
1
8 BITS
DATA BYTE: READS DATA FROM
SLAVE ADDRESS:
SLAVE ADDRESS:
EQUIVALENT TO CHIP- INTERNAL ADDRESS POINTER
SELECT LINE OF A 3-
EQUIVALENT TO CHIP- THE REGISTER COMMANDED BY
SELECT LINE OF A 3- THE LAST READ BYTE OR WRITE
.
WIRE INTERFACE
WIRE INTERFACE
BYTE TRANSMISSION. ALSO
DEPENDENT ON A SEND BYTE.
WRITE BYTE FORMAT
ADDRESS WR ACK
7 BITS
S
COMMAND
ACK
DATA
ACK
P
0
8 BITS
8 BITS
COMMAND BYTE:
SELECTS REGISTER YOU
ARE WRITING TO
DATA BYTE: DATA GOES INTO THE
REGISTER SET BY THE COMMAND
BYTE IF THE COMMAND IS BELOW
50h. IF THE COMMAND is 80h,
81h, or 82h, THE DATA BYTE PRESETS
THE LSB OF AN EEPROM ADDRESS.
SLAVE ADDRESS:
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
BLOCK WRITE FORMAT
ADDRESS WR ACK COMMAND ACK
DATA BYTE
•••
BYTE
DATA BYTE
1
DATA BYTE
S
ACK
ACK
ACK
ACK
P
COUNT = N
N
7 BITS
0
8 BITS
8 BITS
8 BITS
8 BITS
8 BITS
COMMAND BYTE:
PREPARES DEVICE
FOR BLOCK OPERATION
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE
.
SLAVE ADDRESS:
COMMAND BYTE
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
BLOCK READ FORMAT
ADDRESS WR ACK COMMAND ACK SR ADDRESS WR ACK
BYTE
COUNT = 16
DATA BYTE
1
DATA BYTE
•••
DATA BYTE
N
S
ACK
ACK
ACK
ACK
P
7 BITS
0
8 BITS
7 BITS
1
10h
8 BITS
8 BITS
8 BITS
COMMAND BYTE:
PREPARES DEVICE
FOR BLOCK
SLAVE ADDRESS:
SLAVE ADDRESS:
DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE
COMMAND BYTE
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
EQUIVALENT TO CHIP-
SELECT LINE OF A 3-
WIRE INTERFACE
OPERATION
S = START CONDITON
P = STOP CONDITION
SHADED = SLAVE TRANSMISSION
SR = REPEATED START CONDTION
2
Figure 11. SMBus/I C Protocols
______________________________________________________________________________________ 29
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Note that once the read has been done, the internal point-
er is increased by one, unless a ꢀeꢀory boundary is hit.
If the device is busy or if the address is not an allowed
one, the coꢀꢀand code is NACKed and the internal
address pointer is not altered. The ꢀaster ꢀust then inter-
rupt the coꢀꢀunication issuing a STOP condition.
data bytes are being sent, these subsequent bytes
overwrite address 2Fh repeatedly, but no data will be
left in 2Fh as this is a read-only address.
For the configuration EEPROM, valid address pointers
range froꢀ 80h to 9Fh. When using the block write pro-
tocol, the address pointer autoꢀatically increꢀents
after each data byte, except when the address pointer
is already at 9Fh. If the address pointer is already 9Fh,
and ꢀore data bytes are being sent, these subsequent
bytes overwrite address 9Fh repeatedly, leaving only
the last data byte sent stored at this register address.
Block Read
The block read protocol allows the ꢀaster device to
read a block of 16 bytes froꢀ the EEPROM or register
bank (see Figure 11). Read fewer than 16 bytes of data
by issuing an early STOP condition froꢀ the ꢀaster, or
by generating a NACK with the ꢀaster. Previous actions
through the serial interface predeterꢀine the first source
address. It is suggested to use a send byte protocol,
before the block read, to set the initial read address.
The block read protocol is initiated with a coꢀꢀand
code of C1h. The block read procedure follows:
For the user EEPROM, valid address pointers range froꢀ
40h to 7Fh. As for the configuration EEPROM, block write
and block read protocols can also be used. The internal
address pointer will autoꢀatically increꢀent up to the
user EEPROM boundary 7Fh where the pointer ꢀoves to
the first address of the configuration ꢀeꢀory section
80h, as there is no forbidden address in the ꢀiddle.
1) The ꢀaster sends a START condition.
2) The ꢀaster sends the 7-bit slave address and a
write bit (low).
Applications Information
Configuration Download at Power-Up
The configuration of the MAX6884/MAX6885 (undervolt-
age/overvoltage thresholds, reset tiꢀe delays, watch-
dog behavior, prograꢀꢀable output conditions and
configurations, etc.) at power-up depends on the con-
tents of the EEPROM. The EEPROM is coꢀprised of
buffered latches that store the configuration. The local
volatile ꢀeꢀory latches lose their contents at power-
down. Therefore, at power-up, the device configuration
ꢀust be restored by downloading the contents of the
EEPROM (nonvolatile ꢀeꢀory) to the local latches. This
download occurs in a nuꢀber of steps:
3) The addressed slave asserts an ACK on SDA.
4) The ꢀaster sends 8 bits of the block read coꢀ-
ꢀand (C1h).
5) The slave asserts an ACK on SDA, unless busy.
6) The ꢀaster generates a repeated START condition.
7) The ꢀaster sends the 7-bit slave address and a
read bit (high).
8) The slave asserts an ACK on SDA.
9) The slave sends the 8-bit byte count (16).
10) The ꢀaster asserts an ACK on SDA.
11) The slave sends 8 bits of data.
1) Prograꢀꢀable outputs are high iꢀpedance with no
power applied to the device.
12) The ꢀaster asserts an ACK on SDA.
13) Repeat steps 8 and 9 15 tiꢀes.
2) When V
or IN1–IN4 (see the Powering the
CC
MAX6884/MAX6885 section) exceeds +1V, all pro-
graꢀꢀable outputs are asserted low.
14) The ꢀaster generates a STOP condition.
3) When V
or IN1–IN4 exceeds UVLO (2.5V), the
CC
Address Pointers
Use the send byte protocol to set the register address
pointers before read and write operations. For the con-
figuration registers, valid address pointers range froꢀ
00h to 2Fh. Register addresses outside of this range
result in a NACK being issued froꢀ the MAX6884/
MAX6885. When using the block write protocol, the
address pointer autoꢀatically increꢀents after each
data byte, except when the address pointer is already
at 2Fh. If the address pointer is already 2Fh, and ꢀore
configuration EEPROM starts to download its con-
tents to the volatile configuration registers. The
download takes 2.5ꢀs (ꢀax). The prograꢀꢀable
outputs assuꢀe their prograꢀꢀed conditional out-
put state when V
or IN1–IN4 exceeds the UVLO
CC
(see the Powering the MAX6884/MAX6885 section).
4) Any atteꢀpt to coꢀꢀunicate with the device prior
to this download coꢀpletion results in a NACK
being issued froꢀ the MAX6884/MAX6885.
30 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Layout and Bypassing
For better noise iꢀꢀunity, bypass each of the voltage-
detector inputs to GND with a 0.1µF capacitor installed
Configuration Latency Period
A delay of less than 5µs occurs between writing to the
configuration registers and the tiꢀe when these
changes actually take place, except when changing
one of the voltage-detector thresholds. Changing a
voltage-detector threshold typically takes 150µs. When
changing EEPROM contents, a software reboot or
cycling of power is required for these changes to trans-
fer to volatile ꢀeꢀory.
as close to the device as possible. Bypass V
and
CC
DBP to GND with 1µF capacitors installed as close to
the device as possible. V (when not externally sup-
CC
plied) and DBP are internally generated voltages and
should not be used to supply power to external circuitry.
Typical Operating Circuit
12V
5V
12V
DC-DC
1
DC-DC
2
3.3V
2.5V
DC-DC
3
DC-DC
1.8V
4
DC-DC
5
1.5V
1.2V
DC-DC
6
R
PU
R
PU
IN1
IN2
IN3
IN4
IN5
IN6
SDA
SCL
SDA
3.3V ALWAYS ON
µP
V
CC
SCL
RESET
WDI
RESET
LOGIC OUTPUT
LOGIC INPUT
LOGIC INPUT
MAX6884
MAX6885
DBP
WDO
UV/OV
MR
MARGIN
*AUXIN
*REFIN
A0
GND
TEMP
SENSOR
*MAX6884 ONLY
______________________________________________________________________________________ 31
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Pin Configurations
TOP VIEW
20
19
18
17
16
20
19
18
17
16
15
14 DBP
15
RESET
WDO
UV/OV
GND
IN6
RESET
WDO
UV/OV
GND
IN6
1
2
3
4
5
1
2
3
4
5
14 DBP
13
13
12
11
V
V
CC
CC
MAX6884
MAX6885
12
11
AUXIN
REFIN
N.C.
N.C.
*EXPOSED PAD
*EXPOSED PAD
WDI
WDI
6
7
8
9
10
6
7
8
9
10
THIN QFN
THIN QFN
*EXPOSED PAD CONNECTED TO GND.
*EXPOSED PAD CONNECTED TO GND.
Chip Information
PROCESS: BiCMOS
32 ______________________________________________________________________________________
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
XXXXX
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45∞
DETAIL A
e
PIN # 1
I.D.
(ND-1) X
e
DETAIL B
e
L
C
C
L
L1
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
1
-DRAWING NOT TO SCALE-
21-0140
G
2
______________________________________________________________________________________ 33
EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX. ±0.15
DOWN
BONDS
ALLOWED
L
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
PKG.
CODES
T1655-1
T1655-2
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
A
**
**
**
**
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.
A1
0
0
0
0
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
A3
b
T2055-2
T2055-3
T2055-4
T2055-5
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
Y
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
**
**
D
E
3.15 3.25 3.35 3.15 3.25 3.35 0.40
e
0.80 BSC.
0.25
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50
0.65 BSC.
0.50 BSC.
0.50 BSC.
T2855-1
T2855-2
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
**
**
**
**
k
-
-
0.25
-
-
0.25
-
-
0.25
-
-
L
T2855-3
T2855-4
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
L1
-
-
-
-
-
-
-
-
-
-
-
-
N
ND
16
4
20
5
28
7
32
8
T2855-5
T2855-6
T2855-7
T2855-8
**
**
**
NO
YES
4
5
7
8
NE
2.80
3.35
3.35
3.20
2.60 2.70
3.15 3.25
2.60 2.70 2.80
3.15 3.25 3.35
3.15 3.25 3.35
3.00 3.10 3.20
WHHB
WHHC
WHHD-1
WHHD-2
JEDEC
0.40
Y
N
NO
T2855N-1 3.15 3.25
**
**
**
NOTES:
T3255-2
T3255-3
T3255-4
3.00 3.10
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
**
**
NO
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
**SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
PACKAGE OUTLINE,
16, 20, 28, 32L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
G
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products, Inc.
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