MAX6894ETI-T_技术文档

19-3596; Rev 0; 2/05

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

General Description

Features

♦ Pin-Selectable or User-Adjustable Voltage

The MAX6892/MAX6893/MAX6894 pin-selectable, mul-

tivoltage supply sequencers/supervisors monitor sever-

al voltage-detector inputs and one watchdog input,

asserting the respective voltage detector or watchdog

output when the inputs drop below the configured volt-

age thresholds or the watchdog timer expires. The

MAX6892 features eight voltage detector inputs and 10

outputs. The MAX6893 features six voltage-detector

inputs and eight outputs, while the MAX6894 features

four voltage detector inputs and six outputs. A RESET

output ensures all monitored inputs are above the set

thresholds. The voltage detector outputs are configured

as open drain. Manual reset and margin disable inputs

offer additional flexibility.

Detector Thresholds

♦ Dedicated RESET and WDO Outputs

♦ Capacitor-Adjustable Reset and Watchdog

Timeout Periods

♦ Factory-Default Reset and Watchdog Timeout

Periods

♦ Up to Eight Independent, Open-Drain Power-Good

Outputs

♦ Enable Margining Disable and Manual Reset

Controls

♦ -40°C to +85°C Operating Temperature Range

♦ Small 5mm x 5mm Thin QFN Package

♦ Few External Components

The thresholds of the MAX6892/MAX6893/MAX6894 are

selected through five logic inputs (TH0–TH4). The logic on

these five inputs selects the supply voltage tolerance (5%

or 10%) and one of 32 factory-set thresholds settings.

Watchdog and reset timeout periods can use factory

default settings or are independently adjustable by con-

necting external capacitors.

♦ ±±1 Threshold Accuracy

Ordering Information

PIN-

PACKAGE

PKG

CODE

When any of the monitored voltages falls below its

threshold, the respective output asserts and remains

asserted for 6.25ms (typ) after the monitored voltage

exceeds the threshold. The outputs can be connected

to the shutdown or enable inputs of DC-DC regulators

to provide turn-on power sequencing to ensure proper

system initialization.

PART

TEMP RANGE

MAX6892ETJ

MAX6893ETI

MAX6894ETI

-40°C to +85°C

32 Thin QFN

28 Thin QFN

T3255-4

T2855-8

Pin Configurations

The MAX6892 is available in a 5mm x 5mm x 0.8mm,

32-pin, thin QFN package, while the MAX6893/

MAX6894 are available in a 5mm x 5mm x 0.8mm, 28-

pin, thin QFN package. The MAX6892/MAX6893/

MAX6894 are specified to operate over the extended

temperature range (-40°C to +85°C)

TOP VIEW

32

31

30

29

28

27

26

25

PG2

PG3

PG4

GND

PG5

PG6

PG7

PG8

1

2

3

4

5

6

7

8

24 IN7

23

22

21

IN8

Applications

Telecommunication/Central Office Systems

Networking Systems

DBP

V

CC

MAX6892

20 ENABLE

19

18 SWT

17

Servers/Workstations

SRT

Base Stations

*EXPOSED PADDLE

Storage Equipment

TH4

Multimicroprocessor/Voltage Systems

9

10

11

12

13

14

15

16

Typical Operating Circuit appears at end of data sheet.

THIN QFN

*EXPOSED PAD INTERNALLY CONNECTED TO GND.

Pin Configurations continued at end of data sheet.

________________________________________________________________ Maxim Integrated Products

±

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

ABSOLUTE MAXIMUM RATINGS

(All voltages referenced to GND.)

Continuous Power Dissipation (T = +70°C)

A

PG_, RESET, WDO .................................................-0.3V to +14V

IN1–IN8, TH0–TH4, ENABLE, WDI, MR, MARGIN,

28-Pin Thin QFN (derate 21.3mW/°C

above +70°C).............................................................1702mW

32-Pin Thin QFN (derate 21.3mW/°C

SRT, SWT, V .....................................................-0.3V to +6V

CC

DBP ..........................................................................-0.3V to +3V

Input/Output Current (all pins).......................................... 20mA

above +70°C)............................................................1702mW

Maximum Junction Temperature .....................................+150°C

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= V –V

= GND, V –V

= 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, T = -40°C to

IN1

IN6 IN8

IN2 IN5 A

+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1 and 2)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Operating Voltage Range

(Note 3)

Voltage on either one of IN2–IN5 or V

guarantees the part is fully operational

that

CC

2.7

5.5

V

For 1V < (V or V ) < V

V

,

UVLO

IN2– IN5

CC

Undervoltage Lockout

V

PG_ are pulled down to GND with a 10µA

2.5

V

UVLO

current

Digital Bypass Voltage

Supply Current

V

No load

2.48

2.55

0.9

2.67

1.1

V

DBP

V

= 5.5V, V , V

V

= GND, no

IN2

IN1 IN3– IN8

I

mA

CC

load

T

= +25°C to +85°C

= -40°C to +85°C

-1

-2

+1

+2

A

IN1–IN8,

IN_ falling

Threshold Accuracy (Table 2)

V

% V

TH

A

Threshold Hysteresis

Threshold Tempco

V

0.3

10

TH-HYS

TH

∆V /°C

ppm/°C

TH

IN1, IN6–IN8

Input Leakage Current

I

IN

-50

+50

nA

IN2–IN5 set as adjustable thresholds

For IN_ voltages < the highest IN_ supply or

< V

and thresholds are not set as

IN2–IN5 Input Impedance

R

290

400

555

3

kΩ

CC

IN2–IN5

adjustable

≥ V

UVLO

Power-Up Delay

IN_ to PG_ Delay

PG_ Timeout Period

t

V

ms

µs

D-PO

CC

t

IN_ falling/rising, 100mV overdrive

25

D-R

t

5.625

180

6.25

6.875

220

ms

PG

RESET Default Timeout Period

RESET Adjustable Timeout Period

SRT Adjustable Timeout Current

t

V

= V

CC

200

207

230

ms

nA

RP

SRT

t

C

= 47nF

= GND

135

180

280

RP-ADJ

SRT

I

V

SRT

2

_______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

ELECTRICAL CHARACTERISTICS (continued)

(V

= V –V

= GND, V –V

= 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, T = -40°C to

IN1

IN6 IN8

IN2 IN5 A

+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1 and 2)

A

PARAMETER

SYMBOL

CONDITIONS

, selects reset default

MIN

TYP

MAX

UNITS

V

≥ V

SRT-DEF

SRT

SRT Default Timeout Threshold

V

1.1

1.25

1.5

V

SRT-DEF

SRT-ADJ

timeout

SRT Adjustable Timeout

Threshold

(Note 4)

0.95

0.7

1.0

1.05

V

SRT Adjustable Timeout

Discharge Threshold

V

(Note 5)

100

mV

SRT-DIS

SRT Adjustable Timeout Output

Low Discharge Current

I

V

= 0.3V

mA

V

SRT

PG_, RESET, WDO Output Low

V

I

= 4mA, output asserted

0.4

40

OL

UV

SINK

PG_, RESET, WDO Output Initial

Pulldown Current

I

V

< V

, V , RESET, WDO = 0.8V

UVLO PG_{_}

10

µA

CC

PG_, RESET, WDO Output Open-

Drain Leakage Current

I

Output high impedance

-1

+1

µA

LKG

V

0.6

IL

MR, MARGIN, ENABLE,

V

TH0–TH4, WDI Input Voltage

V

1.4

1

IH

MR Input Pulse Width

T

µs

MR

MR Glitch Rejection

MR to RESET Delay

100

2

ns

µs

t

D-MR

MR to DBP Pullup Current

I

V

= 1.4V

MR

5

10

15

µA

MR

MARGIN to DBP Pullup Current

I

= 1.4V

= 0.6V

MARGIN

ENABLE

ENABLE to PG_ Delay

t

200

10

ns

D-ENPG

ENABLE Pulldown Current

V

5

15

µA

_______________________________________________________________________________________

3

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

ELECTRICAL CHARACTERISTICS (continued)

(V

= V –V

= GND, V –V

= 2.7V to 5.5V, WDI = ENABLE = GND, TH0–TH4 = MARGIN = MR = DBP, T = -40°C to

IN1

IN6 IN8

IN2 IN5 A

+85°C, unless otherwise noted. Typical values are at T = +25°C.) (Notes 1 and 2)

A

PARAMETER

TH0–TH4 Input Current

WDI Pulldown Current

WDI Input Pulse Width

SYMBOL

CONDITIONS

MIN

-1

TYP

MAX

+1

UNITS

µA

I

V

= 0.6V

5

10

15

µA

WDI

SWT

50

ns

Initial mode

92.16

1.44

53.7

102.4 112.64

Watchdog Default Timeout Period

t

= V

s

WD

CC

Normal mode

Initial mode

1.6

1.76

82.5

111.9

Watchdog Adjustable Timeout

Period

t

C

= 0.33µF

= GND

WD-ADJ

SWT

Normal mode

0.93

180

1.43

230

1.94

280

SWT Adjustable Timeout Current

SWT Default Timeout Threshold

I

V

nA

V

SWT

≥ V

, selects watchdog default

SWT-DEF

V

1.1

1.25

1.0

1.5

SWT-DEF

SWT-ADJ

timeout period

SWT Adjustable Timeout

Threshold

(Note 4)

0.95

1.05

V

SWT Adjustable Timeout

Discharge Threshold

V

(Note 5)

100

mV

mA

SWT-DIS

SWT Adjustable Timeout Output

Low Discharge Current

I

V

= 0.3V

0.7

SWT-DIS

SWT

Note ±: 100% production tested at T = +25°C and T = +85°C. Specifications at T = -40°C are guaranteed by design.

A

Note 2: Device may be supplied from any one of IN2–IN5, or V

.

CC

Note 3: The internal supply voltage, measured at V , equals the maximum of IN2–IN5.

CC

Note 4: External capacitor is charged by I

when V

< V

.

S_T

S_T-DIS

S_T

S_T-ADJ

Note 5: External capacitor is discharged by I

down to V

after V

reaches V

.

S_T-ADJ

S_T-DIS

S_T

4

_______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Typical Operating Characteristics

(V

IN1

= V –V

= GND, V –V

= 2.7V to 5.5V, WDI = GND, TH0–TH4 = MARGIN = MR = DBP. Typical values are at T = +25°C.)

IN6 IN8

IN2 IN5 A

SUPPLY CURRENT

vs. SUPPLY VOLTAGE (IN2–IN5)

SUPPLY CURRENT

vs. SUPPLY VOLTAGE (V

NORMALIZED PG_ TIMEOUT PERIOD

vs. TEMPERATURE

)

CC

1.1

1.0

0.9

0.8

0.7

0.6

0.5

1.1

1.0

0.9

0.8

0.7

0.6

0.5

1.3

1.2

1.1

1.0

0.9

0.8

0.7

T

= +85°C

A

T

= +85°C

A

T

A

= +25°C

T

A

= +25°C

T

A

= -40°C

T

A

= -40°C

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

-40

-15

10

35

60

85

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

IN_TO PG_ PROPAGATION DELAY

vs. TEMPERATURE

NORMALIZED DEFAULT RESET

TIMEOUT PERIOD vs. TEMPERATURE

NORMALIZED ADJUSTABLE RESET

TIMEOUT PERIOD vs. TEMPERATURE

30

28

26

24

22

20

18

16

14

12

10

1.020

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

100mV OVERDRIVE

t

RP

= 200ms

t

RP

= 200ms

V

SRT

= V

CC

C

SRT

= 47nF

-40

-15

10

35

60

85

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

NORMALIZED IN_ THRESHOLD

vs. TEMPERATURE

NORMALIZED DEFAULT WATCHDOG

TIMEOUT PERIOD vs. TEMPERATURE

NORMALIZED ADJUSTABLE WATCHDOG

TIMEOUT PERIOD vs. TEMPERATURE

1.005

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

0.995

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

t

V

= 1.6s

= V

t

= 1.6s

RP

SWT

C

SWT

= 0.33µF

CC

-40

-15

10

35

60

85

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

_______________________________________________________________________________________

5

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Typical Operating Characteristics (continued)

(V

IN1

= V –V

= GND, V –V

= 2.7V to 5.5V, WDI = GND, TH0–TH4 = MARGIN = MR = DBP. Typical values are at T = +25°C.)

IN6 IN8

IN2 IN5 A

MAXIMUM IN_ TRANSIENT

vs. IN_ THRESHOLD OVERDRIVE

OUTPUT VOLTAGE LOW

vs. SINK CURRENT

200

175

150

125

100

75

500

450

400

350

300

250

200

150

100

50

PG_ ASSERTION OCCURS

50

25

0

1

10

100

1000

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

IN_ THRESHOLD OVERDRIVE (mV)

I

(mA)

SINK

MR TO RESET PROPAGATION DELAY

vs. TEMPERATURE

RESET TIMEOUT PERIOD vs. C

SRT

2.20

2.15

2.10

2.05

2.00

1.95

1.90

1.85

1.80

10,000

1000

100

10

1

0.1

-40

-15

10

35

60

85

0.1

1

10

(nF)

100

1000

TEMPERATURE (°C)

C

SRT

WATCHDOG TIMEOUT PERIOD vs. C

SWT

10,000

1000

100

10

1

0.1

1

10

(nF)

100

1000

C

SWT

6

_______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Pin Description

NAME

FUNCTION

MAX6892 MAX6893 MAX6894

Open-Drain, Power-Good Output 2. PG2 asserts low when the voltage input at

IN2 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG2 deasserts with a factory preset timeout period of 6.25ms.

Open-Drain, Power-Good Output 3. PG3 asserts low when the voltage input at

IN3 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG3 deasserts with a factory preset timeout period of 6.25ms.

Open-Drain, Power-Good Output 4. PG4 asserts low when the voltage input at

IN4 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG4 deasserts with a factory preset timeout period of 6.25ms.

Ground

Open-Drain, Power-Good Output 5. PG5 asserts low when the voltage input at

IN5 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG5 deasserts with a factory preset timeout period of 6.25ms.

Open-Drain, Power-Good Output 6. PG6 asserts low when the voltage input at

IN6 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG6 deasserts with a factory preset timeout period of 6.25ms.

Open-Drain, Power-Good Output 7. PG7 asserts low when the voltage input at

IN7 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG7 deasserts with a factory preset timeout period of 6.25ms.

Open-Drain, Power-Good Output 8. PG8 asserts low when the voltage input at

IN8 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG8 deasserts with a factory preset timeout period of 6.25ms.

1

2

1

2

1

2

PG2

PG3

3

4

5

3

4

5

3

4

PG4

GND

PG5

—

6

7

8

6

—

PG6

PG7

PG8

—

Open-Drain, Active-Low Reset Output Stage. RESET asserts low when any

monitored input (IN_) is below the selected threshold or manual reset (MR) is

pulled low. RESET remains low for the reset timeout period after all reset-

causing conditions are cleared, and then deasserts.

9

7

RESET

Open-Drain, Active-Low Watchdog Output Stage. If WDI remains high or low for

longer than the watchdog timeout period, the internal watchdog timer runs out

and the WDO output asserts low. The internal watchdog timer clears whenever

RESET is asserted or WDI sees a rising or falling edge. Connect WDO to MR to

automatically assert the RESET output after each watchdog timeout fault.

Margin Input. MARGIN holds PG_, RESET, and WDO in their existing states

when driven low. Leave MARGIN unconnected or connect to DBP if unused.

MARGIN overrides MR if both assert at the same time. MARGIN is internally

pulled up to DBP through a 10µA current source.

10

11

8

9

8

9

WDO

MARGIN

Active-Low Manual Reset Input. Pull MR low to assert RESET. RESET remains

asserted for its preset/adjustable reset timeout period when MR is driven/pulled

high. MR is internally pulled up to DBP through a 10µA current source.

Threshold Selection Input 0. Logic input to select desired thresholds. Connect

TH0 to GND or DBP. See Table 2 for available thresholds. Input has no internal

pullup or pulldown.

12

13

10

11

10

11

MR

TH0

_______________________________________________________________________________________

7

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Pin Description (continued)

NAME

FUNCTION

MAX6892 MAX6893 MAX6894

Threshold Selection Input 1. Logic input to select desired thresholds. Connect

TH1 to GND or DBP. See Table 2 for available thresholds. Input has no internal

pullup or pulldown.

Threshold Selection Input 2. Logic input to select desired thresholds. Connect

TH2 to GND or DBP. See Table 2 for available thresholds. Input has no internal

pullup or pulldown.

Threshold Selection Input 3. Logic input to select desired thresholds. Connect

TH3 to GND or DBP. See Table 2 for available thresholds. Input has no internal

pullup or pulldown.

Threshold Selection Input 4. Logic input to select desired thresholds. Connect

TH4 to GND or DBP. See Table 2 for available thresholds. Input has no internal

pullup or pulldown.

14

15

16

17

12

13

14

15

12

13

14

15

TH1

TH2

TH3

TH4

Watchdog Timeout Adjust Input. Connect SWT to V

to select the default

CC

watchdog timeout period. Connect an external capacitor between SWT and

GND to adjust the watchdog timeout period. The adjustable timeout period is

18

16

SWT

calculated by t

= 4.348E6 x C

(t

in seconds and C

in Farads).

SWT

WP

SWT WP

Disable the watchdog timer by connecting SWT to GND.

Reset Timeout Adjust Input. Connect SRT to V to select the default reset

CC

timeout period. Connect an external capacitor between SRT and GND to adjust

the reset timeout period. The adjustable timeout period is calculated by t

19

20

17

18

17

18

SRT

=

RP

4.348E6 x C

(t in seconds and C

SWT RP

in Farads).

SRT

Active-Low, PG_ Enable Input. Pull ENABLE high to force all PG_ outputs low.

PG_ outputs remain asserted for their timeout period when ENABLE is

driven/pulled low. ENABLE is internally pulled down to GND through a 10µA

current sink.

ENABLE

Internal Supply Voltage. Bypass V to GND with a 1µF capacitor as close to

CC

the device as possible. V

supplies power to the internal circuitry. V

is

CC

21

19

V

internally powered from the highest of the monitored IN2–IN5 voltages. Do not

use V to supply power to external circuitry. To externally supply V see the

CC

CC,

Powering the MAX6892/MAX6893/MAX6894 section).

Digital Bypass Voltage. DBP supplies power to the output stages. Bypass DBP

to GND with a 1µF capacitor as close to the device as possible. Do not use

DBP to supply power to external circuitry.

Input Voltage 8. Select undervoltage threshold using TH0–TH4. See Table 2.

For improved noise immunity, bypass IN8 to GND with a 0.1µF capacitor as

close to the device as possible.

Input Voltage 7. Select undervoltage threshold using TH0–TH4. See Table 2.

For improved noise immunity, bypass IN7 to GND with a 0.1µF capacitor as

close to the device as possible.

22

23

24

20

—

20

—

DBP

IN8

IN7

8

_______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Pin Description (continued)

NAME

FUNCTION

MAX6892 MAX6893 MAX6894

Input Voltage 6. Select undervoltage threshold using TH0–TH4. See Table 2.

For improved noise immunity, bypass IN6 to GND with a 0.1µF capacitor as

close to the device as possible.

25

21

22

—

IN6

Input Voltage 5. Select undervoltage threshold using TH0–TH4. See Table 2.

Power the device through IN2–IN5 or V

(see the Powering the

CC

26

—

IN5

IN4

IN3

MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass

IN5 to GND with a 0.1µF capacitor as close to the device as possible.

Input Voltage 4. Select undervoltage threshold using TH0–TH4. See Table 2.

Power the device through IN2–IN5 or V

(see the Powering the

CC

27

28

23

24

23

24

MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass

IN4 to GND with a 0.1µF capacitor as close to the device as possible.

Input Voltage 3. Select undervoltage threshold using TH0–TH4. See Table 2.

Power the device through IN2–IN5 or V

(see the Powering the

CC

MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass

IN3 to GND with a 0.1µF capacitor as close to the device as possible.

Input Voltage 2. Select undervoltage threshold using TH0–TH4. See Table 2.

Power the device through IN2–IN5 or V

(see the Powering the

CC

29

30

25

26

25

26

IN2

IN1

MAX6892/MAX6893/MAX6894 section). For improved noise immunity, bypass

IN2 to GND with a 0.1µF capacitor as close to the device as possible.

Input Voltage 1. Select undervoltage threshold using TH0–TH4. See Table 2.

For improved noise immunity, bypass IN1 to GND with a 0.1µF capacitor as

close to the device as possible.

Watchdog Timer Input. Logic input for the watchdog timer function. If WDI is

not strobed with a valid low-to-high or high-to-low transition within the watchdog

timeout period, the watchdog output asserts low. The watchdog timeout period

is externally adjustable with capacitor C

or selectable for a fixed internal

SWT

31

27

WDI

timeout period. The watchdog has a long timeout period (92.16s minimum fixed

or 64x the adjusted short timeout period) after each reset event and a short

timeout period (1.44s minimum or an adjusted timeout period) after the first

valid WDI transition.

Open-Drain, Power-Good Output 1. PG1 asserts low when the voltage input at

IN1 is below the pin-selectable/adjustable input threshold or ENABLE is pulled

high. PG1 deasserts with a factory preset timeout period of 6.25ms.

32

28

PG1

—

5, 6, 21, 22

EP

N.C.

No Connection. Not internally connected.

Exposed Paddle. Internally connected to GND. Connect EP to GND or leave

floating.

EP

GND

_______________________________________________________________________________________

9

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Functional Diagram

IN_

DETECTOR

IN2

OPEN-DRAIN

ACTIVE-LOW

PG_ OUTPUT

PG1

10µA POWER-UP

PULLDOWN

V

REF

SWT

DBP

SRT

IN1

IN3

IN2 DETECTOR

IN3 DETECTOR

IN4 DETECTOR

IN5 DETECTOR

IN6 DETECTOR

IN7 DETECTOR

IN8 DETECTOR

IN4

IN5*

IN6*

DBP

PG2

PG2 OUTPUT

PG3 OUTPUT

IN7**

IN8**

PG3

PG4

PG4 OUTPUT

PG5 OUTPUT

PG6 OUTPUT

PG7 OUTPUT

PG5*

PG6*

PG7**

PG8

(VIRTUAL

DIODES)

PG8 OUTPUT

WDO OUTPUT

WDO

2.55V

LDO

RESET

RESET OUTPUT

TH0

TH1

DBP

THRESHOLD

SELECTION

LOGIC

1µF

TH2

TH3

TH4

MAX6892

MAX6893

MAX6894

V

CC

* FOR MAX6892/MAX6893 ONLY.

** FOR MAX6892 ONLY.

GND

±0 ______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

The MAX6892/MAX6893/MAX6894 also generate a dig-

Detailed Description

ital supply voltage (DBP) for the internal logic circuitry

The MAX6892/MAX6893/MAX6894 pin-selectable, mul-

and the output stages. Bypass DBP to GND with a 1µF

tivoltage supply sequencers/supervisors monitor sever-

ceramic capacitor installed as close to the device as

al voltage detector inputs and one watchdog input,

possible. The nominal DBP output voltage is 2.55V. Do

asserting the outputs when the respective input thresh-

not use DBP to provide power to external circuitry.

olds have been reached or a timeout occurs. All ver-

sions have an enable manual reset and margin input

disable. The MAX6892/MAX6893/MAX6894 voltage

thresholds are selected by logic inputs and/or an exter-

nal voltage-divider. A RESET output ensures all moni-

tored inputs are above the pin-selected/adjustable

thresholds. Watchdog and reset timeout periods can

use factory default settings or are independently

adjustable by connecting external capacitors. In addi-

tion, all devices can be powered through the voltage

detector inputs alone, or externally supplied from a

Inputs

The MAX6892/MAX6893/MAX6894 contain multiple

logic and voltage detector inputs. Each voltage detec-

tor input is monitored for undervoltage thresholds.

Voltage Detector Inputs (IN_)

The MAX6892/MAX6893/MAX6894 offer several moni-

tor options with both pin-selectable and adjustable

reset thresholds. The threshold voltage at each

adjustable IN_ input is typically 0.6V. To monitor a volt-

age >0.6V, connect a resistor-divider network to the

circuit as shown in Figure 1:

constant supply on the V

pin (see the Powering the

CC

MAX6892/MAX6893/MAX6894 section). The outputs

are factory configured as open drain.

V

= V (R + R ) / R

(Equation 1)

is the desired reset threshold voltage for

IN_TH

TH

1

2

where V

IN_TH

Powering the

MAX6892/MAX6893/MAX6894

the respective IN_ and V

(0.6V).

is the input threshold

TH

The MAX6892/MAX6893/MAX6894 derive power from

the voltage detector inputs: IN2–IN5 (MAX6892/

MAX6893), IN2–IN4 (MAX6894), or through an external-

Resistors R and R can have high values to minimize

1

2

current consumption due to low-leakage currents. Set

ly supplied V . A virtual diode-ORing scheme selects

CC

R to some conveniently high value (10kΩ, for exam-

2

the positive input that supplies power to the device

(see the Functional Diagram). The highest input voltage

on IN2–IN5 (MAX6892/MAX6893)/IN2–IN4 (MAX6894)

supplies power to the device. One of IN2–IN5

ple) and calculate R based on the desired reset

1

threshold voltage, using the following formula:

R = R x (V

/V - 1)

IN_TH TH

1

2

(MAX6889/MAX6890)/IN2–IN4 (MAX6891) or V

be at least 2.7V to ensure proper operation.

must

CC

V

1

IN_TH

Internal hysteresis ensures that the supply input that

initially powered the device continues to power the

device when multiple input voltages are within 50mV of

each other.

V

CC

R

V

powers the analog circuitry and is the bypass con-

V

CC

IN_

CC

MAX6892

MAX6893

MAX6894

nection for the MAX6892/MAX6893/MAX6894 internal

supply. Bypass V to GND with a 1µF ceramic capac-

R

2

CC

itor installed as close to the device as possible. The

internal supply voltage, measured at V , equals the

GND

CC

maximum of IN2–IN5. If V

is externally supplied, V

CC

must be at least 200mV higher than any voltage

applied to IN2–IN5 and V must be brought up first.

CC

V

= 0.6 x (R + R ) / R

1 2 2

IN_TH

CC

V

always powers the device when all IN_ are factory

Figure 1. Adjusting the Monitored Threshold

set as “ADJ.” Do not use the internally generated V

to provide power to external circuitry.

CC

______________________________________________________________________________________ ±±

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Threshold Logic Inputs (TH0–TH4)

The TH0–TH4 logic inputs select the undervoltage thresh-

olds and tolerance of the IN1–IN8 inputs (MAX6892),

IN1–IN6 inputs (MAX6893), and IN1–IN4 inputs

(MAX6894). TH0–TH4 define 32 unique options for the

supervisor functionality. Connect the respective TH_ to

GND for a logic 0 or to DBP for a logic 1. Tables 1 and 2

show the 32 unique threshold options available. TH4 sets

the threshold tolerance of the undervoltage threshold. A

logic 1 selects a 5% supply tolerance and a logic 0

selects 10% supply tolerance. The MAX6892/MAX6893/

MAX6894 logic determines which thresholds should be

used for the IN inputs only at power-up. Use the voltage-

divider circuit of Figure 1 and Equation 1 to set the

threshold for the user-adjustable inputs as described in

the Voltage Detector Inputs (IN_) section.

Table ±. Nominal Monitored Supply Voltages

MONITORED SUPPLY VOLTAGES (V)

SUPPLY

TOLERANCE (1)

SELECTION TH4–TH0

IN±

ADJ

IN2

5

IN3

3.3

3

IN4

2.5

IN5

1.8

IN6

ADJ

IN7

ADJ

IN8

ADJ

1

11111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

5

2

5

2.5

1.8

3

5

3.3

3

2.5

ADJ

1.5

5

4

5

2.5

5

3.3

3

1.8

5

6

5

1.8

5

7

5

3.3

3

ADJ

1.8

5

8

5

9

3.3

3

2.5

1.8

2.5

3.3

3

5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

1.8

5

3.3

3

ADJ

1.8

5

3.3

3

5

3.3

3

5

1.8

1.5

5

2.5

1.8

10

—

5

2.5

1.8

5

3.3

3

2.5

ADJ

1.5

5

2.5

5

3.3

3

1.8

5

1.8

5

3.3

3

ADJ

1.8

5

3.3

3

2.5

1.8

2.5

ADJ

1.8

3.3

3

ADJ

1.8

3.3

3

3.3

ADJ

±2 ______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Table 2. Threshold Options

THRESHOLD VOLTAGES (V)

SELECTION

TH4–TH0*

IN±

IN2

IN3

IN4

2.31

1.67

0.60

1.8

IN5

IN6

IN7

IN8

0.60

1

11111

11110

11101

11100

11011

11010

11001

11000

10111

10110

10101

10100

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

4.62

3.06

2.78

3.06

2.78

3.06

2.78

3.06

2.78

4.38

2.88

2.62

2.88

2.62

2.88

2.62

2.88

0.60

3.06

2.78

3.06

2.78

3.06

2.78

3.06

2.78

2.31

1.67

2.31

2.88

2.62

2.88

2.62

2.88

2.62

2.88

2.62

2.19

1.58

2.19

0.60

1.67

0.60

1.39

1.58

0.60

1.31

0.60

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

1.8

0.60

1.67

2.19

1.58

0.60

1.8

0.60

1.58

0.60

*TH4 = ‘1’ selects 7.5% threshold tolerance, TH4= ‘0’ selects 12.5% threshold tolerance.

Contact factory for alternative thresholds.

______________________________________________________________________________________ ±3

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Watchdog Timer

The MAX6892/MAX6893/MAX6894s’ watchdog circuit

monitors the microprocessor’s (µP’s) activity. If the µP

does not toggle the watchdog input (WDI) within the

watchdog timeout period, the watchdog output (WDO)

asserts. The internal watchdog timer is cleared by

RESET, or by a transition at WDI (which can detect

pulses as short as 50ns). The watchdog timer remains

cleared while reset is asserted. The timer starts count-

ing as soon as WDO is released (see Figure 2).

Watchdog Timeout Capacitor section). The initial watch-

dog timeout is approximately 64 times the normal watch-

dog timeout. For example, in initial mode a 1µF capacitor

gives a watchdog timeout period of about 5min.

If WDO is connected to MR, the WDO asserts for a

short duration (~5µs), long enough to assert the RESET

output. Asserting RESET clears the watchdog timer and

WDO goes high. The reset output remains asserted for

its timeout period after a watchdog fault. The watchdog

timer stays cleared as long as RESET is low.

The MAX6892/MAX6893/MAX6894 feature two modes

of watchdog timer operation: normal mode and initial

mode. At power-up, after a reset event, or after the

watchdog timer expires, the initial watchdog timeout is

active. After the first transition on WDI, the normal

watchdog timeout is active. The initial and normal

watchdog timeouts are determined by the value of the

capacitor connected between SWT and ground or by

The watchdog timeout period is determined by the

value of the capacitor connected between SWT and

ground (see the Selecting the Reset/Watchdog Timeout

Capacitor section). Connect SWT to DBP to select fac-

tory-programmed watchdog timeout. To disable the

watchdog timer connect SWT to GND.

connecting SWT to V

(see the Selecting the Reset and

CC

2.5V

V

CC

OR IN2–IN5

WDO

RESET

WDI

t

*t

WDI

t

*t

WDI

D-PO

RP

WD

WDO NOT CONNECTED TO MR

2.5V

V

OR IN2–IN5

WDO

CC

RESET

WDI

t

*t

WDI

t

*t

WDI

D-PO

RP

WD

RP

WDO CONNECTED TO MR.

*t IS THE INITIAL WATCHDOG TIMEOUT PERIOD.

WDI

Figure 2. Watchdog, Reset, and Power-Up Timing Diagram

±4 ______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Manual Reset (MR)

Many µP-based products require manual reset capabil-

ity to allow an operator or external logic circuitry to initi-

ate a reset. The manual reset input (MR) can connect

directly to a switch without an external pullup resistor or

debouncing network. MR is internally pulled up to DBP

through a 10µA current source and, therefore, can be

left unconnected if unused.

RESET changes from high to low whenever one or more

input voltage (IN1–IN8) monitors drop below their

respective reset threshold voltage or when MR is pulled

low for a minimum of 1µs. Once the affected input volt-

age monitor(s) exceeds its respective reset threshold

voltage(s), RESET remains low for the reset timeout

period, then deaaserts.

Applications Information

MR is designed to reject fast falling transients (typically

100ns pulses) and it must be held low for a minimum of

1µs to assert RESET. After MR transitions from low to

high, RESET remains asserted for the duration of the

reset timeout period.

Selecting the Reset/Watchdog

Timeout Capacitor

The reset timeout period can be adjusted to accommo-

date a variety of µP applications. Adjust the reset time-

out period (t ) by connecting a capacitor (C

)

SRT

RP

Margin Output Disable (MARGIN)

MARGIN allows system-level testing while power sup-

plies exceed the normal ranges. Driving MARGIN low

forces PG_, RESET, and WDO to hold the last state

while system-level testing occurs. Leave MARGIN

unconnected or connect to DBP if unused. An internal

10µA current source pulls MARGIN to DBP. The state of

each programmable output, RESET, and WDO does

not change while MARGIN = GND.

between SRT and ground. Calculate the reset timeout

capacitor as follows:

C

= t / (4.348 x 106)

RP

SRT

with t in seconds and C

in Farads. Connect SRT

SRT

RP

to V

for a factory-programmed reset timeout of

CC

200ms (typ).

The watchdog timeout period can be adjusted to

accommodate a variety of µP applications. With this

feature, the watchdog timeout can be optimized for

software execution. The programmer can determine

how often the watchdog timer should be serviced.

Enable Input

ENABLE is an active-high, logic input. Driving ENABLE

high pulls all PG_ low. Drive ENABLE high or leave

floating for normal operation. ENABLE is internally

pulled down to GND through a 10µA current sink.

Adjust the watchdog timeout period (t ) by connect-

WD

ing a specific value capacitor (C

) between SWT

SWT

and GND. For normal mode operation, calculate the

watchdog timeout capacitor as follows:

Power-Good Outputs

The MAX6892 features eight power-good outputs, the

MAX6893 features six power-good outputs, and the

MAX6894 features four power-good outputs. Each out-

put (PG_) responds to its respective input (IN_). Each

PG_ is open drain. During power-up, the outputs pull

down to GND with an internal 10µA current sink for 1V

C

SWT

= t

/ (4.348 x 10⁶)

WD

with t

in seconds and C

in Farads. Connect SWT

SWT

WD

to V

for a factory-programmed watchdog timeout of

CC

1.6s (normal mode) and 102.4s (initial mode).

C

and C

must be a low-leakage (<10nA) type

SWT

SRT

< V

.

capacitor. Ceramic capacitors are recommended.

CC

UVLO

RESET

Layout and Bypassing

For better noise immunity, bypass each of the voltage

detector inputs to GND with 0.1µF capacitors installed

Output

The reset output is typically connected to the reset

input of a µP. A µP’s reset input starts or restarts the µP

in a known state. The MAX6892/MAX6893/MAX6894

supervisory circuits provide the reset logic to prevent

code-execution errors during power-up, power-down,

and brownout conditions.

as close to the device as possible. Bypass V

and

CC

DBP to GND with 1µF capacitors installed as close to

the device as possible.

______________________________________________________________________________________ ±5

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Pin Configuration (continued)

TOP VIEW

28

27

26

25

24

23

22

28

27

26

25

24

23

22

PG2

PG3

1

2

3

4

5

6

7

21 IN6

PG2

PG3

1

2

3

4

5

6

7

21 N.C.

20

19

18

17

16

15

DBP

20

19

18

17

16

15

DBP

V

CC

PG4

V

CC

PG4

ENABLE

SRT

GND

PG5

ENABLE

SRT

GND

N.C.

MAX6893

MAX6894

SWT

PG6

SWT

N.C.

*EXPOSED PADDLE

TH4

RESET

TH4

RESET

8

9

10 11 12 13 14

8

9

10 11 12 13 14

THIN QFN

*EXPOSED PAD INTERNALLY CONNECTED TO GND.

Chip Information

PROCESS: BiCMOS

±6 ______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Typical Operating Circuit

5V

DC-DC

1

3.3V

DC-DC

2

2.5V

DC-DC

3

1.8V

1.5V

DC-DC

4

IN1 IN2

PG2 IN3

PG3 IN4

PG4 IN5

PG5 IN6

µP

V

CC

RESET

WDI

LOGIC OUTPUT

LOGIC INPUT

WDO

DBP

TH0

TH1

MAX6893

MARGIN

MR

TH2

TH3

TH4

ENABLE

SRT

SWT

PG1 PG6

GND

C

SRT

C

SWT

5V BUS INPUT

5V SUPPLY

t

PG2

ENABLE 3.3V DC-DC CONVERTER

3.3V OUTPUT

PG2

3.3V SUPPLY

t

PG3

ENABLE 2.5V DC-DC CONVERTER

2.5V OUTPUT

PG3

2.5V SUPPLY

PG4

t

PG4

ENABLE 1.8V DC-DC CONVERTER

1.8V OUTPUT

1.8V SUPPLY

t

PG5

ENABLE 1.5V DC-DC CONVERTER

PG5

1.5V OUTPUT

1.5V SUPPLY

RESET

t

RESET

SYSTEM RESET

______________________________________________________________________________________ ±7

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

D2

D

b

0.10 M

C A B

C

L

D2/2

D/2

k

L

MARKING

XXXXX

E/2

E2/2

C

(NE-1) X

e

L

E2

E

PIN # 1 I.D.

0.35x45∞

DETAIL A

e

PIN # 1

I.D.

(ND-1) X

e

DETAIL B

e

L

C

L

L1

L

e

0.10

C

A

0.08

C

A3

A1

PACKAGE OUTLINE,

16, 20, 28, 32L THIN QFN, 5x5x0.8mm

1

-DRAWING NOT TO SCALE-

21-0140

G

2

±8 ______________________________________________________________________________________

Pin-Selectable, Octal/Hex/Quad, Power-Supply

Sequencers/Supervisors

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

COMMON DIMENSIONS

20L 5x5 28L 5x5

EXPOSED PAD VARIATIONS

D2 E2

MIN. NOM. MAX. MIN. NOM. MAX. ±0.15

DOWN

BONDS

ALLOWED

L

PKG.

SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.

16L 5x5

32L 5x5

PKG.

CODES

T1655-1

T1655-2

3.00 3.10 3.20 3.00 3.10 3.20

NO

YES

NO

A

**

0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80

0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05

0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.

A1

0

T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20

A3

b

T2055-2

T2055-3

T2055-4

T2055-5

3.00 3.10 3.20 3.00 3.10 3.20

NO

YES

NO

Y

0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30

4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10

**

D

E

3.15 3.25 3.35 3.15 3.25 3.35 0.40

e

0.80 BSC.

0.25

0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50

0.65 BSC.

0.50 BSC.

T2855-1

T2855-2

3.15 3.25 3.35 3.15 3.25 3.35

2.60 2.70 2.80 2.60 2.70 2.80

NO

**

k

-

0.25

-

0.25

-

0.25

-

L

T2855-3

T2855-4

3.15 3.25 3.35 3.15 3.25 3.35

2.60 2.70 2.80 2.60 2.70 2.80

3.15 3.25 3.35 3.15 3.25 3.35

YES

NO

L1

-

N

ND

16

4

20

5

28

7

32

8

T2855-5

T2855-6

T2855-7

T2855-8

**

NO

YES

4

5

7

8

NE

2.80

3.35

3.20

2.60 2.70

3.15 3.25

2.60 2.70 2.80

3.15 3.25 3.35

3.00 3.10 3.20

WHHB

WHHC

WHHD-1

WHHD-2

JEDEC

0.40

Y

N

NO

T2855N-1 3.15 3.25

**

NOTES:

T3255-2

T3255-3

T3255-4

3.00 3.10

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

3.00 3.10 3.20 3.00 3.10 3.20

YES

NO

**

NO

T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL

CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE

OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1

IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

**^{SEE COMMON DIMENSIONS TABLE}

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm

FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,

T2855-3 AND T2855-6.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.

PACKAGE OUTLINE,

16, 20, 28, 32L THIN QFN, 5x5x0.8mm

2

-DRAWING NOT TO SCALE-

21-0140

G

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ ±9

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX6894ETI-T
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Power Supply Management Circuit, Adjustable, 4 Channel, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, TQFN-28 输入元件信息通信管理
文件：	总19页 (文件大小：291K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX6894ETI-T [MAXIM]

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