MAX7304 [MAXIM]
I2C-Interfaced 16-Port, Level-Translating GPIO and LED Driver with High Level of Integrated; I2C接口，16端口电平转换GPIO和LED驱动器，高级的集成
| 型号： | MAX7304 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | I2C-Interfaced 16-Port, Level-Translating GPIO and LED Driver with High Level of Integrated |
| 文件： | 总28页 (文件大小：1443K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5949; Rev 0; 6/11
General Description
Features
The MAX7304 consists of 16 port GPIOs, with 12 push-
pull GPIOs and four open-drain GPIOs configurable as
PWM-controlled LED drivers. The device supports a
1.62V to 3.6V separate power supply for level translation.
An address-select input (AD0) allows up to four unique
slave addresses for the device.
S Four LED Driver Pins on PORT15–PORT12
S Integrated High-ESD Protection
8kV IEC 61000-4-2 Contact Discharge
14kV IEC 61000-4-2 Air-Gap Discharge
S 5V Tolerant, Open-Drain I/O Ports Capable of
Constant-Current LED Drive
Each GPIO can be programmed to one of the two
externally applied logic voltage levels. PORT15–PORT12
can also be configured as LED drivers that feature
constant-current sinks and PWM intensity control with the
internal oscillator. The maximum constant-current level for
each open-drain LED port is 20mA. The intensity of the
LED on each open-drain port can be individually adjusted
through a 256-step PWM control. The port also features
LED fading.
S 256-Step PWM Individual LED Intensity-Control
Accuracy
S Individual LED Blink Rates and Common LED
Fade-In/Out Rates from 256ms to 4096ms
S User-Configurable Debounce Time (1ms to 32ms)
S Configurable Edge-Triggered Port Interrupt (INT)
S 1.62V to 3.6V Operating Supply Voltage
The same index rows and columns in the device can be
used as a direct logic-level translator.
S Individually Programmable GPIOs to Two Logic
Levels
The device is offered in a 24-pin (3.5mm x 3.5mm) TQFN
package with an exposed pad, and a small 25-bump
(2.159mm x 2.159mm) wafer-level package (WLP) for
cell phones, pocket PCs, and other portable consumer
electronic applications.
S 8-Channel Individual Programmable Level
Translators
S Supports Hot Insertion
S 400kbps, 5.5V Tolerant I2C Serial Interface with
Selectable Bus Timeout
The device operates over the -40NC to +85NC extended
temperature range.
Ordering Information appears at end of data sheet.
Applications
For related parts and recommended products to use with this part,
Cell Phones
refer to www.maxim-ic.com/MAX7304.related.
Notebooks
PDAs
Typical Operating Circuit
Handheld Games
Portable Consumer Electronics
+1.8V +2.6V
V
V
LA
CC
14
PORT0
PORT1
GPIO
+5V
MAX7304
INT
MCU
SDA
SCL
PORT13
PORT14
PORT15
AD0
GND
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
ABSOLUTE MAXIMUM RATINGS
V
V
to GND ....................................................-0.3V to +4V
Continuous Power Dissipation (T = +70NC)
CC, LA
A
PORT11–PORT0 to GND.......................... -0.3V to (V
+ 0.3V)
TQFN (derate 15.4mW/NC above +70NC)..................1229mW
WLP (derate 19.2mW/NC above +70NC)......................850mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (TQFN) (soldering, 10s)....................+300NC
Soldering Temperature (reflow) ......................................+260NC
CC
PORT15–PORT12 to GND.......................................-0.3V to +6V
SDA, SCL, AD0, INT to GND ..................................-0.3V to +6V
V
to V
...........................................................-0.3V to +2.3V
LA
CC
DC Current on PORT15–PORT12 to GND .........................25mA
DC Current on PORT11–PORT0 to GND .............................7mA
V
, V , GND Current .....................................................80mA
CC LA
DC Current V , V to PORT11–PORT0 ...........................5mA
CC LA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
WLP
Junction-to-Ambient Thermal Resistance (B ).......52NC/W
Junction-to-Ambient Thermal Resistance (B )....65.1NC/W
JA
JA
Junction-to-Case Thermal Resistance (B )...........5.4NC/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
CC
= 1.62V to 3.6V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC.) (Notes 2, 3)
CC A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3.3
3.3
50
MAX
3.6
3.6
65
UNITS
Operating Supply Voltage
Second Logic Supply
Operating Supply Current
Sleep-Mode Supply Current
POR Threshold
V
1.62
V
V
CC
V
V
CC
LA
I
Oscillator running
Not using GPO or LED configuration
FA
FA
V
CC
I
1.8
1.2
3
SL
V
POR
GPIO SPECIFICATIONS
External Supply Voltage
PORT15–PORT12 (LED Drivers)
V
5
V
LED
LED Port-to-Port Sink Current
Variation
V
= 3.3V, V = 1V, T = +25NC,
CC OL A
Q1.5
Q2.4
%
10mA output mode
T
= +25NC
8.6
11.4
A
V
V
V
V
= 1V
10mA Port Sink Current
PORT15–PORT12
OL
OL
OL
OL
I
V
V
= 3.3V
9.04
10
10.96
mA
mA
OL
OL
CC
CC
= 0.5V
= 1V
= 3.6V, T = +25NC
9.5
A
T
= +25NC
18.13
18.47
21.52
21.34
A
20mA Port Sink Current
PORT15–PORT12
I
V
V
= 3.3V
20
CC
CC
= 0.5V
= 3.6V, T = +25NC
19.05
A
Input High Voltage PORT_
Input Low Voltage PORT_
V
0.7 OV
V
V
V = V
or V depending on
LA
IH
S
S
CC
reference logic level setting
Input voltage = V or V
GND
V
0.3 OV
IL
S
Input Leakage Current
PORT11–PORT0
I
I
-2
-1
+2
FA
FA
LEAKAGE
LEAKAGE
CC
Input Leakage Current
PORT15–PORT12
Input voltage = 5V
+1
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
2
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC.) (Notes 2, 3)
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
20
MAX
UNITS
Input Capacitance PORT_
C
pF
IN
V
V
= 1.62V and I
= 2.5mA
50
100
250
CC
SINK
Output Low Voltage PORT_
V
mV
mV
OL
= 1.62V and I
= 5mA
80
CC
SINK
V
120
-
-
V
-
CC
CC
40
V
= 1.62V and I
= 2.5mA
= 5mA
CC
CC
SOURCE
SOURCE
Output High Voltage
COL3–COL0, ROW_
V
OH
V
V
-
CC
CC
70
V
= 1.62V and I
250
Output Logic-Low Voltage
(INT)
V
I
= 6mA
0.6
V
OL
SINK
PWM Frequency
f
Derived from oscillator clock
500
Hz
PWM
SERIAL-INTERFACE SPECIFICATIONS
Input High Voltage
SDA, SCL, AD0
V
0.7 OV
V
V
IH
CC
Input Low Voltage
SDA, SCL, AD0
V
0.3 OV
CC
IL
Input Leakage Current
SDA, SCL, AD0
I
Input voltage = 5.5V or V
-1
+1
FA
V
LEAKAGE
GND
Output Logic-Low Voltage
SDA
V
I
= 6mA
SINK
0.6
10
OL
Input Capacitance
SDA, SCL, AD0
C
(Notes 4, 5)
pF
IN
I2C TIMING SPECIFICATIONS
Bus timeout enabled
Bus timeout disabled
0.05
0
400
400
SCL Serial-Clock Frequency
f
kHz
Fs
SCL
Bus Free Time Between a STOP
and START Condition
t
1.3
0.6
BUF
Hold Time (Repeated) START
Condition
t
Fs
HD, STA
Repeated START Condition
Setup Time
t
0.6
0.6
Fs
SU, STA
STOP Condition Setup Time
Data Hold Time
t
Fs
Fs
ns
Fs
Fs
SU, STO
t
(Note 6)
0.9
HD, DAT
Data Setup Time
t
100
1.3
0.7
SU, DAT
SCL Clock Low Period
SCL Clock High Period
t
LOW
t
HIGH
Rise Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
(Notes 4, 5)
(Notes 4, 5)
(Notes 4, 7)
300
300
250
ns
ns
ns
R
B
Fall Time of Both SDA and SCL
Signals, Receiving
20 +
0.1C
t
F
B
Fall Time of SDA Signal,
Transmitting
20 +
0.1C
t
F, TX
B
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
3
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 1.62V to 3.6V, T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= 3.3V, T = +25NC.) (Notes 2, 3)
A
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
50
UNITS
ns
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
Bus Timeout
t
(Notes 4, 8)
(Note 4)
SP
C
400
27
pF
B
t
14
19
ms
TIMEOUT
ESD PROTECTION
IEC 61000-4-2 Air-Gap Discharge
IEC 61000-4-2 Contact Discharge
Human Body Model
Q14
Q8
PORT_
kV
kV
All Other Pins
Q1.5
Note 2: All parameters are tested at T = +25NC. Specifications over temperature are guaranteed by design.
A
Note 3: All digital inputs at V
or GND.
CC
Note 4: Guaranteed by design.
Note 5: C = total capacitance of one bus line in pF. t and t measured between 0.8V and 2.1V.
B
R
F
Note 6: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Note 7: I
= 6mA. C = total capacitance of one bus line in pF. t and t measured between 0.8V and 2.1V.
SINK
B R F
Note 8: Input filters on the SDA, SCL, and AD0 inputs suppress noise spikes less than 50ns.
Typical Operating Characteristics
(V
CC
= 2.5V, V = 2.5V, T = +25NC, unless otherwise noted.)
LA A
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (PORT15–PORT12)
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (PORT15–PORT12)
GPO OUTPUT LOW VOLTAGE
vs. SINK CURRENT (PORT15–PORT12)
120
120
100
80
60
40
20
0
120
100
80
60
40
20
0
V
= 2.4V
V
= 3.0V
V
= 3.6V
CC
CC
CC
100
80
60
40
20
0
T
= +85°C
A
T
= +85°C
A
T
= +85°C
A
T
A
= +25°C
T = +25°C
A
T
= +25°C
A
T
= -40°C
A
T
= -40°C
A
T
= -40°C
A
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
SINK CURRENT (mA)
SINK CURRENT (mA)
SINK CURRENT (mA)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
4
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Typical Operating Characteristics (continued)
(V
CC
= 2.5V, V = 2.5V, T = +25NC, unless otherwise noted.)
LA
A
CONSTANT-CURRENT GPIO OUTPUT
SINK CURRENT vs. OUTPUT VOLTAGE
(PORT15–PORT12)
SLEEP-MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.8
25
20
15
10
5
V
= 2.4V
CC
T
= +85°C
A
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
A
= +85°C
T
A
= -40°C
T
= +25°C
A
T
= +25°C
A
T
= -40°C
A
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (V)
CONSTANT-CURRENT GPIO
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE (PORT15–PORT12)
CONSTANT-CURRENT GPIO
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE (PORT15–PORT12)
25
20
15
10
5
25
20
15
10
5
V
= 3.0V
V
= 3.6V
CC
CC
T
A
= +85°C
T
A
= +85°C
T
A
= -40°C
T
A
= -40°C
T
= +25°C
A
T
A
= +25°C
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
5
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Pin Configurations
TOP VIEW
(BUMPS SIDE DOWN)
MAX7304
TOP VIEW
1
2
3
4
5
+
18
17
16
15
14
13
PORT5
PORT7
PORT15
GND
PORT14
PORT13
A
B
C
D
E
PORT4
GND
12
11
10
9
PORT0 19
PORT8
PORT9
PORT10
PORT1 20
PORT2 21
PORT3 22
PORT6
PORT2
PORT12
PORT10
GND
MAX7304
PORT11
GND
PORT11
PORT9
PORT8
PORT3
PORT1
PORT0
GND
8
23
24
*EP
5
+
7
PORT12
PORT4
V
SDA
V
CC
LA
1
2
3
4
6
INT
SCL
AD0
TQFN
*CONNECT EP TO GROUND.
WLP
Pin Description
PIN
NAME
FUNCTION
TQFN
1
WLP
A2
PORT5
PORT6
GPIO Port 5. Push-pull I/O.
GPIO Port 6. Push-pull I/O.
GPIO Port 7. Push-pull I/O.
2
B2
3
A3
PORT7
4
B3
PORT15
PORT14
PORT13
PORT12
GPIO Port 15. Open-drain I/O. PORT15 can be configured as a constant-current sink.
GPIO Port 14. Open-drain I/O. PORT14 can be configured as a constant-current sink.
GPIO Port 13. Open-drain I/O. PORT13 can be configured as a constant-current sink.
GPIO Port 12. Open-drain I/O. PORT12 can be configured as a constant-current sink.
Ground
5
A4
6
A5
7
B4
8, 23
9
B1, B5, C3
GND
C5
C4
D5
E5
D4
E4
D3
E3
E2
PORT11
PORT10
PORT9
PORT8
GPIO Port 11. Push-pull I/O.
10
11
12
13
14
15
16
17
GPIO Port 10. Push-pull I/O.
GPIO Port 9. Push-pull I/O.
GPIO Port 8. Push-pull I/O.
V
Second Logic Level for GPIO Level Shifting (where V
PV P3.6V)
LA
CC LA
AD0
SDA
SCL
INT
Address Input. Selects up to four device slave addresses (Table 2).
I2C-Compatible, Serial-Data I/O
I2C-Compatible Serial-Clock Input
Active-Low Key-Switch Interrupt Output. INT is open-drain and requires a pullup resistor.
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
6
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Pin Description (continued)
PIN
NAME
FUNCTION
TQFN
WLP
Positive Supply Voltage. Bypass to GND with a 0.1FF capacitor as close as possible to
the device.
18
D2
V
CC
19
20
21
22
24
E1
D1
C2
C1
A1
PORT0
PORT1
PORT2
PORT3
PORT4
GPIO Port 0. Push-pull I/O.
GPIO Port 1. Push-pull I/O.
GPIO Port 2. Push-pull I/O.
GPIO Port 3. Push-pull I/
O.
GPIO Port 4. Push-pull I/O.
Exposed Pad (TQFN Only). Internally connected to GND. Connect to a large ground plane
to maximize thermal performance. Not intended as an electrical connection point.
—
—
EP
Functional Diagram
V
V
CC LA
I/0 SUPPLY CONTROL
PWM
LOGIC
LED ENABLE
PWM SIGNAL
MAX7304
128kHz
OSCILLATOR
GPIO ENABLE
GPIO INPUT
OPEN-DRAIN
GPIO/LED
DRIVERS
4
PORT15–PORT12
INT
GPIO OUTPUT
CONTROL
REGISTERS
FIFO
I/O
LOGIC
SDA
SCL
AD0
2
I C
GPIO ENABLE
GPIO INPUT
INTERFACE
PUSH-PULL
GPIO
12
PORT11–PORT10
GPIO OUTPUT
BUS
TIMEOUT
POR
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
7
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
constant-currentandPWMintensitycontrol. Themaximum
constant-current level for each open-drain LED port is
Detailed Description
The MAX7304 is an I2C-interfaced 16-port GPIO expand-
er. The device features 12 push-pull GPIOs configured
for digital I/O and four open-drain GPIOs configurable
as constant-current outputs for LED applications up to
5V. The device supports a second 1.62V to 3.6V power
supply for level translation. The second logic supply
20mA. The intensity of the LED on each open-drain port
can be individually adjusted through a 256-step PWM
control. The port also features LED fading.
The device meets ESD requirements for Q8kV contact
discharge and Q14kV air-gap discharge on all port pins
(configured as GPIO and/or LED drivers).
voltage (V ) must be set equal to or higher than V
.
LA
CC
Initial Power-Up
On power-up, all control registers reset to power-up
values (Table 1) and the device is in sleep mode.
Each GPIO can be programmed to one of the two exter-
nally applied logic voltage levels. PORT15–PORT12
can also be configured as LED drivers that feature
Table 1. Register Address Map and Power-Up Conditions
ADDRESS
CODE (hex)
READ/
WRITE
POWER-UP
VALUE (hex)
REGISTER
FUNCTION
DESCRIPTION
0x01
0x31
0x34
0x35
0x0B
0x00
0x00
0x00
Configuration
LED driver enable
GPIO direction 1
GPIO direction 2
Power-down and I2C timeout enable
R/W
R/W
R/W
R/W
LED driver enable register
GPIO input/output control register 1 for PORT7–PORT0
GPIO input/output control register 2 for PORT15–PORT8
GPO open-drain/push-pull output setting for
PORT7–PORT0
0x36
0x37
0x38
0x39
0xFF
0x0F
0x00
0x00
GPO output mode 1
GPO output mode 2
GPIO supply voltage 1
GPIO supply voltage 2
R/W
R/W
R/W
R/W
GPO open-drain/push-pull output setting for
PORT15–PORT8
GPIO voltages supplied by V
PORT7–PORT0
or V for
LA
CC
GPIO voltages supplied by V
PORT15–PORT8
or V for
LA
CC
0x3A
0x3B
0x3C
0xFF
0xFF
0x00
GPIO values 1
GPIO values 2
Debounced input or output values of PORT7–PORT0
Debounced input or output values of PORT15–PORT8
R/W
R/W
R/W
GPIO level-shifter enable GPIO level-shifter pair enable
GPIO global
0x40
0x42
0x43
0x00
0x00
0xC0
GPIO standby, GPIO reset, LED fade
configuration
R/W
R/W
R/W
GPIO debounce
PORT7–PORT0 debounce time setting
LED constant-current
setting
PORT15–PORT12 constant-current output setting
0x45
0x48
0x50
0x51
0x52
0x53
0x00
0x00
0x00
0x00
0x00
0x00
Common PWM
I2C timeout flag
Common PWM duty-cycle setting
I2C timeout since last POR
R/W
Read only
PORT12 PWM ratio
PORT13 PWM ratio
PORT14 PWM ratio
PORT15 PWM ratio
PORT12 individual duty-cycle setting
PORT13 individual duty-cycle setting
PORT14 individual duty-cycle setting
PORT15 individual duty-cycle setting
R/W
R/W
R/W
R/W
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
8
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 1. Register Address Map and Power-Up Conditions (continued)
ADDRESS
CODE (hex)
READ/
WRITE
POWER-UP
VALUE (hex)
REGISTER
FUNCTION
DESCRIPTION
PORT12 LED
configuration
PORT12 interrupt, PWM mode control, and blink-
period settings
0x54
0x55
0x56
0x57
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
PORT13 LED
configuration
PORT13 interrupt, PWM mode control, and blink-
period settings
PORT14 LED
configuration
PORT14 interrupt, PWM mode control, and blink-
period settings
PORT15 LED
configuration
PORT15 interrupt, PWM mode control, and blink-
period settings
0x58
0x59
0xFF
0xFF
Interrupt mask 1
Interrupt mask 2
Interrupt mask for PORT7–PORT0
Interrupt mask for PORT15–PORT8
R/W
R/W
GPI edge-triggered detection setting for
PORT7–PORT0
0x5A
0x5B
0x00
0x00
GPI trigger mode 1
GPI trigger mode 2
R/W
R/W
GPI edge-triggered detection setting for
PORT15–PORT8
When the port is initially programmed as an input, there
is a delay of one debounce period prior to detecting
a transition on the input port. This is to prevent a false
interrupt from occurring when changing a port from an
output to an input.
GPIOs
The device has 16 GPIO ports, of which four have
LED control functions. The ports can be used as logic
inputs and logic outputs. PORT15–PORT12 are also
configurable as constant-current PWM LED drivers. Each
ports’ logic level is referenced to V
or V . The GPIO
CC
LA
GPO Output Mode 1 and 2 Registers (0x36, 0x37)
These registers configure the pins as an open-drain or
push-pull output. GPO output mode 1 register bits D[7:0]
correspond with PORT7–PORT0 (see Table 9 in the
Register Tables section). GPO output mode 2 register
bits D[7:0] correspond with PORT15–PORT8 (see Table
10 in the Register Tables section). Set the corresponding
bit to 0 to configure the output mode as open-drain and
1 to configure the output mode as push-pull.
port’s inputs can also be debounced. When in PWM
mode, the ports are set up to start their PWM cycle in
45N phase increments. This prevents large current spikes
on the LED supply voltage when driving multiple LEDs.
Configuration Register (0x01)
The configuration register controls the I2C bus timeout
feature (see Table 5 in the Register Tables section). The
bus timeout feature prevents the SDA being held low
when the SCL line hangs.
GPIO Supply Voltage 1 and 2
Registers (0x38, 0x39)
These registers configure input and output voltages
LED Driver Enable Register (0x31)
Bits D[3:0] correspond to PORT15–PORT12 on the
device. Set the corresponding bit to 1 for enabling the
LED driver circuitry and 0 for normal GPIO function (see
Table 6 in the Register Tables section).
to be referenced to V
or V . GPIO supply voltage
CC
LA
1 register bits D[7:0] correspond with PORT7–PORT0
(see Table 11 in the Register Tables section). GPIO
supply voltage 2 register bits D[7:0] correspond with
PORT15–PORT8 (see Table 12 in the Register Tables
section). Set the bit to 0 for input/output voltages
GPIO Direction 1 and 2 Registers (0x34, 0x35)
These registers configure the pin as an input or an
output. GPIO direction 1 register bits D[7:0] correspond
with PORT7–PORT0 (see Table 7 in the Register Tables
section). GPIO direction 2 register bits D[7:0] correspond
with PORT15–PORT8 (see Table 8 in the Register Tables
section). Set the corresponding bit to 0 to configure as
input and 1 to configure as output.
referenced to V
and set the bit to 1 for the input/output
CC
voltage referenced to V
.
LA
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products
9
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
GPIO Values 1 and 2 Registers (0x3A, 0x3B)
The GPIO values 1 and 2 registers contain the debounced
input data for all the GPIOs for PORT7–PORT0 and
PORT15–PORT8, respectively (see Tables 13 and 14
in the Register Tables section). There is one debounce
period delay prior to detecting a transition on the input
port. This prevents a false interrupt from occurring when
changing a port from an output to an input. The GPIO
values 1 and 2 registers reports the state of all input ports
regardless of any interrupt mask settings.
Common PWM Ratio Register (0x45)
The common PWM ratio register stores the common con-
stant-current output PWM duty cycle (see Table 19 in the
Register Tables section). The values stored in this register
translate over to a PWM ratio in the same manner as the
individual PWM ratio registers (0x50 to 0x53). Ports can use
their own individual PWM value or the common PWM value.
Write to this register to change the PWM ratio of several
ports at once.
I2C Timeout Flag Register (0x48) (Read Only)
The I2C timeout flag register contains a single bit (D0),
which indicates if an I2C timeout has occurred (see Table
20 in the Register Tables section). Read this register to
clear an I2C timeout initiated interrupt.
When writing to the GPIO values 1 and 2 registers, the
corresponding PORT_ voltage is set high when written 1
or cleared when written 0. Reading the port when config-
ured as an output always returns the value 0 for the cor-
responding port regardless of the output value.
PORT12–PORT15 Individual PWM Ratio
Registers (0x50 to 0x53)
GPIO Level-Shifter Enable Register (0x3C)
Enabling bit D_ in this register enables the direct
level shifter between GPIO pins PORT15–PORT8 and
PORT7–PORT0 (see Table 15 in the Register Tables sec-
tion). The level-shifting pairs are PORT0/PORT8, PORT1/
PORT9, etc. The direction of the level shifter is con-
trolled by the GPIO direction 2 register (0x35). When the
corresponding bit in the GPIO direction 2 register is set
to 0, PORT15–PORT8 are inputs, while PORT7–PORT0
are outputs. When the bit is set to 1, PORT7–PORT0 are
inputs, while PORT15–PORT8 are outputs.
Each LED driver port has an individual PWM ratio reg-
ister, 0x50 to 0x53 (see Table 21 in the Register Tables
section). Use values 0x00 to 0xFE in these registers to
configure the number of cycles out of 256 the output
sinks current (LED is on), from 0 cycles to 254 cycles.
Use 0xFF to have an output continuously sink current
(always on). For applications requiring multiple ports
to have the same intensity, program a particular port’s
configuration register (0x54 to 0x57) to use the common
PWM ratio register (0x45). New PWM settings take place
at the beginning of a PWM cycle, to allow changes from
common intensity to individual intensity with no interrup-
tion in the PWM cycle.
GPIO Global Configuration Register (0x40)
The GPIO global configuration register controls the main
settings for the GPIO ports (see Table 16 in the Register
Tables section).
PORT12–PORT15 LED Configuration
Registers (0x54 to 0x57)
Bit D5 enables interrupt generation for I2C timeouts. D4
is the main enable/shutdown bit for the GPIOs. Bit D3
functions as a software reset for the GPIO registers
(0x31 to 0x5B). Bits D[2:0] set the fade-in/out time for the
GPIOs configured as constant-current sinks.
Registers 0x54 to 0x57 set individual configurations for
each port (see Table 22 in the Register Tables section).
D5 sets the port’s PWM setting to either the common or
individual PWM setting. Bits D[4:2] enable and set the
port’s individual blink period from 0 to 4096ms. Bits D1
and D0 set a port’s blink duty cycle.
GPIO Debounce Configuration Register (0x42)
The GPIO debounce configuration register sets the
amount of time a GPIO must be held in order for the
device to register a logic transition (see Table 17 in
the Register Tables section). Five bits (D[4:0]) set 32
possible debounce times from 9ms up to 40ms.
Interrupt Mask 1 and 2 Registers (0x58, 0x59)
The interrupt mask 1 and 2 registers control which ports
trigger an interrupt for PORT7–PORT0 and PORT15–
PORT8, respectively (see Tables 23 and 24 in the
Register Tables section). Set the bit to 0 to enable the
interrupt. Set the bit to 1 to mask the interrupt.
LED Constant-Current Setting Register (0x43)
The LED constant-current setting register sets the global
constant-current level (see Table 18 in the Register
Tables section). Bit D0 selects the global current values
between 10mA and 20mA. This setting only applies to the
LED driver enabled pins, PORT15–PORT12.
If the port that has generated the interrupt is not masked,
the interrupt causes the INT signal to assert. A read of the
GPIO values 1 and 2 registers (0x3A, 0x3B) is required
to deassert the INT pin. Note that transitions that occur
while the INT signal is asserted, but before the read of
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 10
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
the values 1 and 2 registers, sets the appropriate bit of
the values 1 and 2 registers only, but has no effect on
the INT pin as it is already asserted. However, transitions
that occur when the I2C is active cannot be latched into
the values 1 and 2 registers until after the read has taken
place. If there are transitions that cause the INT signal to
assert, during the time of an I2C read, they cause the INT
signal to reassert once the read transaction has taken
place. Note that the interrupt configurations only apply
when a port is configured as an input.
1) Change the common PWM register value from any
value to zero to cause all ports using the common
PWM register settings to fade out. No ports using
individual PWM settings are affected.
2) Change the common PWM register value to any value
from zero to cause all ports using the common PWM
register settings to fade in. No ports using individual
PWM settings are affected.
3) Take the part out of sleep mode to cause all ports
to fade in. Changing an individual PWM intensity dur-
ing fade in automatically cancels that port’s fade and
immediately outputs at its newly programmed intensity.
GPI Trigger Mode 1 and 2 Registers (0x5A, 0x5B)
The GPI trigger mode 1 and 2 registers control how
ports can trigger an interrupt for PORT7–PORT0 and
PORT15–PORT8, respectively (see Tables 25 and 26 in
the Register Tables section). Set the bit to 0 for rising-
edge triggering. Set the bit to 1 for rising- and falling-
edge triggering.
4) Put the part into sleep mode to cause all ports to fade
out. Changing an individual PWM intensity during
fade out automatically cancels that port’s fade and
immediately turns off.
LED PWM
Each port has an individual PWM ratio register. The value
stored in this register configures the number of cycles
out of 255 that the output is sinking current (LED is on).
Setting a value of 0xFF in an individual intensity register
sets the output to continuously sink current (always on).
Conversely, setting a value of 0x00 in an individual inten-
sity register sets the output in a high-impedance state
(always off).
The inputs are debounced (if enabled) by taking a snap-
shot of the port state when the transition occurs, and
another after the debounce time has elapsed—ensur-
ing that the state of the port is stable prior to triggering
the interrupt. After the debounce cycle, an interrupt is
generated and the INT pin asserts if it is not masked for
that particular port. Regardless of whether or not the INT
signal is masked, the GPIO values 1 and 2 registers
(0x3A, 0x3B) report the state of all input ports.
For applications requiring multiple ports to have the same
intensity, the common PWM ratio intensity setting can be
used in lieu of the individual intensity setting. To use the
common intensity setting, program bit D5 of the
corresponding port’s configuration register to logic-high.
Setting a port to use the common PWM ratio setting
copies the value of the common intensity register into
the individual intensity register at the beginning of each
PWM cycle. This allows an output port to be seamlessly
changed from common intensity to individual intensity
with no interruption in the PWM cycle.
Sleep Mode
The device is put into sleep mode by clearing bit D4 in
the GPIO global configuration register (0x40). In sleep
mode, the device draws minimal current. The device is
taken out of sleep mode and put into operating mode by
setting bit D4 in the GPIO configuration register. When
the GPIOs are enabled, the part is in operating mode.
In sleep mode, the internal oscillator and I2C timeout
features are disabled.
LED Fade
Set the fade cycle time in the GPIO global configuration
register (0x40) to a non-zero value to enable fade in/out
(see Table 16 in the Register Tables section). Fade in
increases an LED’s PWM intensity in 16 even steps, from
zero to its stored value. Fade out decreases an LED’s
PWM intensity in 16 even steps, from its current value to
zero. Fading occurs automatically in any of the following
scenarios:
Outputs are configured to sink a constant current of either
10mA or 20mA during the period when the output is on.
The setting in the individual constant-current setting
register (0x43) controls the value of the current.
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 11
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
LED Blink
Serial Interface
Each LED driver-supported port has its own blink-control
settings through registers 0x54 to 0x57 (see Table 22
in the Register Tables section). The blink period ranges
from 0 (blink disabled) to 4.096s. Settable blink duty
cycles range from 6.25% to 50%. All blink periods start at
the same PWM cycle for synchronized blinking between
multiple ports.
Figure 1 shows the 2-wire serial interface timing details.
Serial Addressing
The device operates as a slave that sends and receives
data through an I2C-compatible 2-wire interface. The
interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). A master (typically a
microcontroller) initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer.
Each port has its own counter to generate blink
timing. The blink counter can be programmed to cause
the output to gate off and on at a programmable rate. The
blink period can be set to 256ms, 512ms, 1.024s, 2.048s,
or 4.096s using D[4:2] of the port’s individual configura-
tion register. The percentage of time that the LED is on
for one blink cycle is set to 50%, 25%, 12.5%, or 6.25%
by D[1:0] of the individual configuration register.
The device’s SDA line operates as both an input and an
open-drain output. A pullup resistor, typically 4.7kI, is
required on SDA. The device’s SCL line operates only as
an input. A pullup resistor is required on SCL if there are
multiple masters on the 2-wire interface, or if the master
in a single-master system has an open-drain SCL output.
Interrupt
Two possible sources generate INT: I2C timeout or
GPIOs configured as inputs (registers 0x48, 0x5A, and
0x5B). Read the respective data/status registers for each
type of interrupt in order to clear INT. If multiple sources
generate the interrupt, all the related status registers
must be read to clear INT.
Each transmission consists of a START (S) condition
(Figure 2) sent by a master, followed by the device’s 7-bit
slave address plus R/W bit, a register address byte, one
or more data bytes, and finally, a STOP (P) condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START condition by transitioning SDA from high
to low while SCL is high. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
t
R
t
t
F
SDA
F, TX
t
BUF
t
SU, DAT
t
SU, STA
t
HD, STA
t
LOW
t
SU, STO
t
HD, DAT
t
HIGH
SCL
t
HD, STA
t
R
t
F
START
CONDITION
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Two-Wire Serial Interface Timing Details
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 12
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse;
therefore, the SDA line is stable low during the high
period of the clock pulse. When the master is transmit-
ting to the device, the device generates the acknowledge
bit because the device is the recipient. When the device
is transmitting to the master, the master generates the
acknowledge bit because the master is the recipient.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 3). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit (Figure 4), which
the recipient uses to handshake receipt of each byte of
data. Thus, each byte transferred effectively requires 9 bits.
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 2. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 3. Bit Transfer
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA BY
TRANSMITTER
SDA BY
RECEIVER
S
Figure 4. Acknowledge
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 13
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Slave Addresses
The device has two 7-bit long slave addresses. The bit
following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
Bus Timeout
The device features a 20ms (min) bus timeout on the
2-wire serial interface, largely to prevent the device from
holding the SDA I/O low during a read transaction, should
the SCL lock up for any reason before a serial transac-
tion is completed. Bus timeout operates by causing the
device to internally terminate a serial transaction, either
read or write, if the time between adjacent edges on SCL
exceeds 20ms. After a bus timeout, the device waits for a
valid START condition before responding to a consecu-
tive transmission. This feature can be enabled or disabled
under user control by writing to the configuration register.
The first 4 bits (MSBs) of the device slave addresses
are always 0111. Slave address bits A[3:1] correspond,
by the matrix in Table 2, to the states of the device
address input pin AD0, and A0 corresponds to the R/W
bit (Figure 5). The AD0 input can be connected to any of
four signals: GND, V , SDA, or SCL, giving four pos-
CC
sible slave-address pairs, allowing up to four devices to
share the same bus. Because SDA and SCL are dynamic
signals, care must be taken to ensure that AD0 transitions
no sooner than the signals on SDA and SCL.
Message Format for Writing
A write to the device comprises the transmission of the
slave address with the R/W bit set to zero, followed by at
least one byte of information. The first byte of information
is the command byte. The command byte determines
which register of the device is to be written by the next
byte, if received. If a STOP condition is detected after the
command byte is received, the device takes no further
action (Figure 6) beyond storing the command byte.
The device monitors the bus continuously, waiting for a
START condition followed by its slave address. When the
device recognizes its slave address, it acknowledges
and is then ready for continued communication.
Table 2. 2-Wire Interface Address Map
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the device selected by the command byte (Figure 7).
DEVICE ADDRESS
PIN AD0
A7
A6
A5 A4 A3
A2
0
A1
A0
GND
0
0
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent device internal registers, because the
command byte address generally autoincrements.
V
1
CC
0
1
1
1
0
R/W
SDA
SCL
1
1
0
1
0
1
1
1
A3
A2
A1
R/W
ACK
SDA
SCL
MSB
LSB
Figure 5. Slave Address
COMMAND BYTE IS STORED ON RECEIPT OF
ACKNOWLEDGE CONDITION
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX7304
S
SLAVE ADDRESS
COMMAND BYTE
0
A
A
P
R/W
ACKNOWLEDGE FROM MAX7304
Figure 6. Command Byte Received
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 14
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Message Format for Reading
The device is read using the internally stored command
byte as an address pointer, the same way the stored com-
mand byte is used as an address pointer for a write. The
pointer generally autoincrements after each data byte is
read using the same rules as for a write. Thus, a read is
initiated by first configuring the device’s command byte
by performing a write (Figure 6). The master can now
read N consecutive bytes from the device, with the first
data byte being read from the register addressed by the
initialized command byte. When performing read-after-
write verification, remember to reset the command byte’s
address because the stored command byte address is
generally autoincremented after the write (Figure 8).
Command Address Autoincrementing
Address autoincrementing allows the device to be
configured with fewer transmissions by minimizing the
number of times the command address needs to be
sent. The command address (0x31 to 0x5B) stored in the
device increments after each data byte is written or read.
Autoincrement only functions when doing a multiburst
read or write.
Applications Information
Reset from I2C
After a catastrophic event such as ESD discharge or
microcontroller reset, use bit D4 of the GPIO global
configuration register (0x40) as a software reset.
Operation with Multiple Masters
When the device is operated on a 2-wire interface with
multiple masters, a master reading the device uses a
repeated START between the write that sets the device’s
address pointer, and the read(s) that takes the data from
the location(s). This is because it is possible for master 2
to take over the bus after master 1 has set up the device’s
address pointer but before master 1 has read the data. If
master 2 subsequently resets the device’s address pointer,
master 1’s read can be from an unexpected location.
Hot Insertion
The INT, SCL, and AD0 inputs and SDA remain high
impedance with up to 5.5V asserted on them when the
device powers down (V
= 0V). I/O ports remain high
CC
impedance with up to 5.5V asserted on them when not
powered. Use the device in hot-swap applications.
ACKNOWLEDGE FROM MAX7304
ACKNOWLEDGE FROM MAX7304
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7304
SLAVE ADDRESS
S
0
A
COMMAND BYTE
A
DATA BYTE
N BYTES
A
P
R/W
AUTOINCREMENT
COMMAND BYTE ADDRESS
Figure 7. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX7304
ACKNOWLEDGE FROM MAX7304
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7304
SLAVE ADDRESS
S
0
A
COMMAND BYTE
A
DATA BYTE
N BYTES
A
P
R/W
AUTOINCREMENT
COMMAND BYTE ADDRESS
Figure 8. N Data Bytes Received
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 15
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Staggered PWM
The LED’s on-time in each PWM cycle is phase delayed
by 45N into four evenly spaced start positions. Optimize
phasing when using fewer than four ports as constant-
current outputs by allocating the ports with the most
appropriate start positions. For example, if using two
constant-current outputs, choose PORT12 and PORT14
because their PWM start positions are evenly spaced.
In general, choose the ports that spread the current
demand from the ports’ load supply.
ESD Protection
All device pins meet the Q1.5kV Human Body Model ESD
tolerances. The GPIOs meet IEC 61000-4-2 ESD protec-
tion. The IEC test stresses consist of 10 consecutive ESD
discharges per polarity at the maximum specified level
and below (per IEC 61000-4-2). Test criteria include:
1) The powered device does not latch up during the ESD
discharge event.
2) The device subsequently passes the final test used for
prescreening.
Power-Supply Considerations
Tables 3 and 4 are from the IEC 61000-4-2: Edition 1.1
1999-05: Electromagnetic compatibility (EMC) Testing
and measurement techniques—Electrostatic discharge
immunity test.
The device operates with a 1.62V to 3.6V power-supply
voltage. Bypass the power supply V
to GND with a
CC
0.1FF or higher ceramic capacitor as close as possible
to the device. Bypass the logic power supply (V ) to
LA
GND with a 0.1FF or higher ceramic capacitor as close
as possible to the device.
Table 3. ESD Test Levels
1A—CONTACT DISCHARGE
1B—AIR DISCHARGE
LEVEL
TEST VOLTAGE (kV)
LEVEL
TEST VOLTAGE (kV)
1
2
3
4
X
2
1
2
3
4
X
2
4
4
8
6
8
15
Special
Special
X = Open level. The level has to be specified in the dedicated equipment specification. If higher voltages than those shown are
specified, special test equipment could be needed.
Table 4. ESD Waveform Parameters
INDICATED
VOLTAGE
(kV)
FIRST PEAK OF CURRENT
DISCHARGE Q10%
(A)
RISE TIME (t ) WITH
R
DISCHARGE SWITCH
CURRENT (Q30%)
AT 30ns
CURRENT (Q30%)
AT 60ns
LEVEL
(ns)
(A)
(A)
1
2
3
4
2
4
6
8
7.5
15
0.7 to 1
0.7 to 1
0.7 to 1
0.7 to 1
4
8
2
4
6
8
22.5
30
12
16
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 16
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Register Tables
Table 5. Configuration Register (0x01)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
FUNCTION
DEFAULT VALUE
D[7:1]
Reserved
—
0
—
0000101
I2C timeout enabled
I2C timeout disabled
D0
Timeout disable
1
1
Table 6. LED Driver Enable Register (0x31)
REGISTER BIT
DESCRIPTION
VALUE
DEFAULT VALUE
D[7:4]
Reserved
0000
—
0000
0
1
0
1
0
1
0
1
GPIO function
LED driver enable
GPIO function
LED driver enable
GPIO function
LED driver enable
GPIO function
LED driver enable
D3
D2
D1
D0
PORT15
PORT14
PORT13
PORT12
0
0
0
0
Table 7. GPIO Direction 1 Register (0x34)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
D7
PORT7
0
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
0
0
0
0
0
0
0
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 17
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 8. GPIO Direction 2 Register (0x35)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
Set as input pin
Set as output pin
D7
PORT15
0
D6
D5
D4
D3
D2
D1
D0
PORT14
PORT13
PORT12
PORT11
PORT10
PORT9
0
0
0
0
0
0
0
PORT8
Table 9. GPO Output Mode 1 Register (0x36)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
Port is an open-drain output
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7
PORT7
1
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
1
1
1
1
1
1
1
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 18
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 10. GPO Output Mode 2 Register (0x37)
REGISTER BIT
DESCRIPTION
PORT15
VALUE
FUNCTION
Port is an open-drain output
DEFAULT VALUE
D7
D6
D5
D4
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
PORT14
Port is an open-drain output
Port is an open-drain output
Port is an open-drain output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
Port is an open-drain output
Port is a push-pull output
PORT13
PORT12
D3
D2
D1
D0
PORT11
PORT10
PORT9
PORT8
1
1
1
1
Note: When programmed as GPO, PORT15–PORT12 are always open-drain and bits D[7:4] are not writable.
Table 11. GPIO Supply Voltage 1 Register (0x38)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PORT7 supplied by V
PORT7 supplied by V
PORT6 supplied by V
PORT6 supplied by V
PORT5 supplied by V
PORT5 supplied by V
PORT4 supplied by V
PORT4 supplied by V
PORT3 supplied by V
PORT3 supplied by V
PORT2 supplied by V
PORT2 supplied by V
PORT1 supplied by V
PORT1 supplied by V
PORT0 supplied by V
PORT0 supplied by V
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
D7
PORT7
0
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
0
0
0
0
0
0
0
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 19
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 12. GPIO Supply Voltage 2 Register (0x39)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PORT15 supplied by V
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
CC
LA
D7
PORT15
0
PORT15 supplied by V
PORT14 supplied by V
PORT14 supplied by V
PORT13 supplied by V
PORT13 supplied by V
PORT12 supplied by V
PORT12 supplied by V
PORT11 supplied by V
PORT11 supplied by V
PORT10 supplied by V
PORT10 supplied by V
D6
D5
D4
D3
D2
D1
D0
PORT14
PORT13
PORT12
PORT11
PORT10
PORT9
0
0
0
0
0
0
0
PORT9 supplied by V
PORT9 supplied by V
PORT8 supplied by V
PORT8 supplied by V
CC
LA
CC
LA
PORT8
Table 13. GPIO Values 1 Register (0x3A)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clear PORT7 low
Set PORT7 high
Clear PORT6 low
Set PORT6 high
Clear PORT5 low
Set PORT5 high
Clear PORT4 low
Set PORT4 high
Clear PORT3 low
Set PORT3 high
Clear PORT2 low
Set PORT2 high
Clear PORT1 low
Set PORT1 high
Clear PORT0 low
Set PORT0 high
D7
PORT7
1
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
1
1
1
1
1
1
1
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 20
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 14. GPIO Values 2 Register (0x3B)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clear PORT15 low
Set PORT15 high*
Clear PORT14 low
Set PORT14 high*
Clear PORT13 low
Set PORT13 high*
Clear PORT12 low
Set PORT12 high*
Clear PORT11 low
Set PORT11 high
Clear PORT10 low
Set PORT10 high
Clear PORT9 low
Set PORT9 high
D7
PORT15
1
D6
D5
D4
D3
D2
D1
D0
PORT14
PORT13
PORT12
PORT11
PORT10
PORT9
1
1
1
1
1
1
1
Clear PORT8 low
Set PORT8 high
PORT8
*Open-drain output, pullup resistor required.
Table 15. GPIO Level-Shifter Enable (0x3C)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
Level shifting disabled
DEFAULT VALUE
0
D7
PORT7/PORT15
0
Level shift between PORT7 and PORT15 enabled;
direction controlled by GPIO direction 2 register (0x35)
1
0
1
0
1
0
1
0
1
0
1
Level shifting disabled
D6
D5
D4
D3
D2
PORT6/PORT14
PORT5/PORT13
PORT4/PORT12
PORT3/PORT11
PORT2/PORT10
0
0
0
0
0
Level shift between PORT6 and PORT14 enabled;
direction controlled by GPIO direction 2 register (0x35)
Level shifting disabled
Level shift between PORT5 and PORT13 enabled;
direction controlled by GPIO direction 2 register (0x35)
Level shifting disabled
Level shift between PORT4 and PORT12 enabled;
direction controlled by GPIO direction 2 register (0x35)
Level shifting disabled
Level shift between PORT3 and PORT11 enabled;
direction controlled by GPIO direction 2 register (0x35)
Level shifting disabled
Level shift between PORT2 and PORT10 enabled;
direction controlled by GPIO direction 2 register (0x35)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 21
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 15. GPIO Level-Shifter Enable (0x3C) (continued)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
Level shifting disabled
DEFAULT VALUE
0
D1
PORT1/PORT9
0
Level shift between PORT1 and PORT9 enabled;
direction controlled by GPIO direction 2 register (0x35)
1
0
1
Level shifting disabled
D0
PORT0/PORT8
0
Level shift between PORT0 and PORT8 enabled;
direction controlled by GPIO direction 2 register (0x35)
Table 16. GPIO Global Configuration Register (0x40)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
D[7:6]
Reserved
0
0
—
00
Disabled
I2C timeout
interrupt enable
INT is asserted when I2C bus times out.
INT is deasserted when a read is performed on the
I2C timeout flag register (0x48).
D5
D4
D3
0
0
0
1
PWM, constant-current circuits, and GPIs are shut
down. GPO values depend on their setting. Register
0x31 to 0x5B values are stored and cannot be
changed. The entire part is shut down.
0
GPIO enable
GPIO reset
Normal GPIO operation. PWM, constant-current circuits,
and GPIOs are enabled.
1
0
Normal operation.
Return all GPIO registers (registers 0x31 to 0x5B) to
their POR value. This bit is momentary and resets itself
to 0 after the write cycle.
1
000
No fading.
PWM intensity ramps up (down) between the common
PWM value and 0% duty cycle in 16 steps over the
following time period:
D[2:0] = 001 = 256ms
D[2:0] = 010 = 512ms
D[2:0]
Fade-in/out time
000
XXX
D[2:0] = 011 = 1024ms
D[2:0] = 100 = 2048ms
D[2:0] = 101 = 4096ms
D[2:0] = 110/111 = Undefined
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 22
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 17. GPIO Debounce Configuration Register (0x42)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
RESERVED
DEBOUNCE TIME
Power-up default setting
Debounce time is 9ms
0
0
0
0
0
0
0
0
Debounce time is 10ms
Debounce time is 11ms
Debounce time is 12ms
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
⋮
Debounce time is 37ms
Debounce time is 38ms
Debounce time is 39ms
Debounce time is 40ms
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Table 18. LED Constant-Current Setting Register (0x43)
REGISTER BIT
D[7:6]
DESCRIPTION
Reserved
VALUE
FUNCTION
DEFAULT VALUE
11
Set always as 11
—
11
D[5:1]
Reserved
00000
00000
0
1
Constant current is 20mA
Constant current is 10mA
Constant-
current setting
D0
0
Table 19. Common PWM Ratio Register (0x45)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
0
D1
0
D0
0
COMMON PWM
Power-up default setting
Common PWM ratio is 0/256
0
0
0
0
0
Common PWM ratio is 1/256
Common PWM ratio is 2/256
Common PWM ratio is 3/256
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
⋮
Common PWM ratio is 252/256
Common PWM ratio is 253/256
Common PWM ratio is 254/256
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
Common PWM ratio is 256/256
(100% duty cycle)
1
1
1
1
1
1
1
1
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 23
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
2
Table 20. I C Timeout Flag Register (0x48) (Read Only)
REGISTER BIT
DESCRIPTION
VALUE
0000000
0
FUNCTION
DEFAULT VALUE
D[7:1]
Reserved
—
0000000
No I2C timeout has occurred since last read or POR.
I2C timeout has occurred since last read or POR. This
bit is reset to zero when a read is performed on this
register. I2C timeouts must be enabled for this function
to work (see Table 5).
D0
I2C timeout flag
0
1
Table 21. PORT12–PORT15 Individual PWM Ratio Registers (0x50 to 0x53)
REGISTER DATA
REGISTER DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
0
D0
0
PORT PWM
Power-up default setting
PORT PWM ratio is 0/256
0
0
0
0
0
0
PORT PWM ratio is 1/256
PORT PWM ratio is 2/256
PORT PWM ratio is 3/256
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
⋮
PORT PWM ratio is 252/256
PORT PWM ratio is 253/256
PORT PWM ratio is 254/256
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
PORT PWM ratio is 256/256
(100% duty cycle)
1
1
1
1
1
1
1
1
Table 22. PORT12–PORT15 LED Configuration Registers (0x54 to 0x57)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
D[7:6]
Don’t care
00
—
00
Port uses individual PWM intensity register to set the
PWM ratio
0
1
D5
Common PWM
Blink period
0
Port uses common PWM intensity register to set the
PWM ratio
000
001
010
011
100
101
110/111
00
Port does not blink
Port blink period is 256ms
Port blink period is 512ms
Port blink period is 1024ms
Port blink period is 2048ms
Port blink period is 4096ms
Undefined
D[4:2]
D[1:0]
000
00
LED is on for 50% of the blink period
LED is on for 25% of the blink period
LED is on for 12.5% of the blink period
LED is on for 6.25% of the blink period
01
Blink-on time
10
11
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 24
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 23. Interrupt Mask 1 Register (0x58)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
Interrupt is not masked
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7
PORT7
1
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
D6
D5
D4
D3
D2
D1
D0
PORT6
PORT5
PORT4
PORT3
PORT2
PORT1
PORT0
1
1
1
1
1
1
1
Table 24. Interrupt Mask 2 Register (0x59)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
Interrupt is not masked
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7
PORT15
1
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
Interrupt is not masked
Interrupt is masked
D6
D5
D4
D3
D2
D1
D0
PORT14
PORT13
PORT12
PORT11
PORT10
PORT9
1
1
1
1
1
1
1
PORT8
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 25
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Table 25. GPI Trigger Mode 1 Register (0x5A)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rising-edge-triggered interrupts
D7
PORT15
0
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
D6
D5
D4
D3
D2
D1
D0
PORT14
PORT13
PORT12
PORT11
PORT10
PORT9
0
0
0
0
0
0
0
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
PORT8
Rising- and falling-edge-triggered interrupts
Table 26. GPI Trigger Mode 2 Register (0x5B)
REGISTER BIT
DESCRIPTION
VALUE
FUNCTION
DEFAULT VALUE
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rising-edge-triggered interrupts
D7
PORT15
0
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
D6
D5
D4
D3
D2
D1
D0
PORT14
PORT13
PORT12
PORT11
PORT10
PORT9
0
0
0
0
0
0
0
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
Rising- and falling-edge-triggered interrupts
Rising-edge-triggered interrupts
PORT8
Rising- and falling-edge-triggered interrupts
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 26
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Wafer-Level Packaging (WLP)
Applications Information
Chip Information
PROCESS: BiCMOS
For the latest application details on WLP construction,
dimensions, tape-carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profile, as well as the latest information on reliability
testing results, refer to Application Note 1891: Wafer-
Level Packaging (WLP) and Its Applications, available at
www.maxim-ic.com.
Ordering Information
PART
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
PIN-PACKAGE
24 TQFN-EP*
25 WLP
MAX7304ETG+
MAX7304EWA+**
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
PACKAGE TYPE
24 TQFN-EP
25 WLP
PACKAGE CODE
T243A3+1
OUTLINE NO.
21-0188
LAND PATTERN NO.
90-0122
W252F2+1
21-0453
Refer to Application Note 1891
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ Maxim Integrated Products 27
MAX7304
2
I C-Interfaced 16-Port,
Level-Translating GPIO and LED Driver
with High Level of Integrated ESD Protection
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/11
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
28
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明