MAX7311AAG+_技术文档

19-2747; Rev 4; 4/05

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

General Description

Features

♦ 400kbps I²C-Compatible Serial Interface

The MAX7311 2-wire-interfaced expander provides 16-bit

parallel input/output (I/O) port expansion for SMBus™

and I²C applications. The MAX7311 consists of input

port registers, output port registers, polarity inversion reg-

isters, configuration registers, a bus timeout register, and

an I²C-compatible serial interface logic compatible with

SMBus. The system master can invert the MAX7311 input

data by writing to the active-high polarity inversion regis-

ter. The system master can enable or disable bus timeout

by writing to the bus timeout register.

♦ 2V to 5.5V Operation

♦ 5V Overvoltage Tolerant I/Os

♦ Supports Hot Insertion

♦ 16 I/O Pins that Default to Inputs on Power-Up

♦ 100kΩ Pullup on Each I/O

♦ Open-Drain Interrupt Output (INT)

♦ Bus Timeout for Lock-Up-Free Operation

♦ Noise Filter on SCL / SDA Inputs

♦ 64 Slave ID Addresses Available

♦ Low Standby Current (2.9µA typ)

♦ Polarity Inversion

Any of the 16 I/O ports can be configured as an input or

output. A power-on reset (POR) initializes the 16 I/Os

as inputs. Three address select pins configure one of

64 slave ID addresses.

The MAX7311 supports hot insertion. All port pins, the

INT output, SDA, SCL and the slave address inputs

AD0–2 remain high impedance in power down (V+ =

0V) with up to 6V asserted upon them.

♦ 4mm ✕ 4mm, 0.8mm Thin QFN Package

♦ -40°C to +125°C Operation

The MAX7311 is available in 24-pin SO, SSOP, TSSOP,

and thin QFN packages and is specified over the -40°C

to +125°C automotive temperature range.

Ordering Information

For applications requiring I/Os without pullup resistors,

refer to the MAX7312 data sheet.

PKG

CODE

PART

TEMP RANGE PIN-PACKAGE

Applications

MAX7311AWG -40°C to +125°C 24 Wide SO

MAX7311AAG -40°C to +125°C 24 SSOP

—

Servers

RAID Systems

24 Thin QFN

MAX7311ATG -40°C to +125°C

(4mm ✕ 4mm)

T2444-4

—

Industrial Control

Medical Equipment

PLCs

MAX7311AUG -40°C to +125°C 24 TSSOP

SMBus is a trademark of Intel Corp.

Instrumentation and Test Measurement

Pin Configurations

TOP VIEW

18 17 16 15 14 13

+

24 V

INT

AD1

AD2

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

1

2

3

4

5

6

7

8

9

SCL 19

SDA 20

V+ 21

12 I/O10

11 I/O9

10 I/O8

23 SDA

22 SCL

21 AD0

20 I/O15

19 I/O14

18 I/O13

17 I/O12

16 I/O11

15 I/O10

14 I/O9

13 I/O8

MAX7311ATG

INT

AD1

AD2

GND

I/O7

I/O6

22

23

24

9

8

7

MAX7311

1

2

3

4

5

6

THIN QFN

I/O6 10

I/O7 11

GND 12

TSSOP/SSOP/SO

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

ABSOLUTE MAXIMUM RATINGS

+

V

to GND ................................................................-0.3V to +6V

Continuous Power Dissipation (T = +70°C)

A

I/O0–I/O15 as Inputs....................................(GND - 0.3V) to +6V

24-Pin Wide SO (derate 11.±mW/°C above +70°C) ....941mW

24-Pin SSOP (derate ±.0mW/°C above +70°C) ...........640mW

24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......975mW

24-Pin Thin QFN (derate 20.±mW/°C above +70°C) .166±mW

Operating Temperature Range .........................-40°C to +125°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

SCL, SDA, AD0, AD1, AD2, INT...................(GND - 0.3V) to +6V

+

Maximum V Current......................................................+250mA

Maximum GND Current ...................................................-250mA

DC Input Current on I/O0–I/O15.......................................±20mA

DC Output Current on I/O0–I/O15 ....................................±±0mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

+

(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 3.3V, T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

5.5

35

UNITS

+

Supply Voltage

V

2

V

+

V

= 2V

23

43

All I/Os unloaded,

= 400kHz

+

I

Supply Current

Standby Current

V = 3.3V

+

60

µA

f

SCL

V

= 5.5V

= 2V

±0

120

11

+

V

2.3

2.9

3.±

1.4

All I/Os unloaded,

I

= 3.3V

= 5.5V

12

µA

V

STBY

f

= 0

SCL

15.5

1.7

Power-On Reset Voltage

SCL, SDA

V

POR

+

0.3 ✕ V

Input Voltage Low

Input Voltage High

V

IL

+

V

0.7 ✕ V

IH

Low-Level Output Voltage

Leakage Current

Input Capacitance

I/O_

V

I

= 6mA

0.4

+1

V

OL

SINK

I

-1

µA

pF

L

10

Input Voltage Low

Input Voltage High

V

0.±

V

IL

V

1.±

IH

T

= -40°C to +±5°C; includes internal

A

Input Leakage Current

Internal Pullup Current

1

µA

+

pullup current, V = V

IO

T

= -40°C to +±5°C, V = 0

34

17

32

43

41

31

100

A

+

IO

V

= 2V, V = 0.5V

OL

±.5

17

+

Low-Level Output Current

High Output Current

I

mA

= 3.3V, V = 0.5V

OL

SINK

= 5V, V = 0.5V

OL

= 3.3V, V

= 2.4V

29

OH

I

SOURCE

= 5V, V

= 4.5V

OH

AD0, AD1, AD2

+

Input Voltage Low

Input Voltage High

V

0.3 ✕ V

V

IL

+

V

0.7 ✕ V

IH

2

_______________________________________________________________________________________

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

DC ELECTRICAL CHARACTERISTICS (continued)

+

(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 3.3V, T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

-1

TYP

MAX

UNITS

µA

Leakage Current

+1

Input Capacitance

INT

4

pF

Low-Level Output Current

I

V

= 0.4V

OL

6

mA

OL

AC ELECTRICAL CHARACTERISTICS

+

(V = 2V to 5.5V, T = -40°C to +125°C, unless otherwise noted.) (Note 1)

A

PARAMETER

SCL Clock Frequency

Bus Timeout

SYMBOL

CONDITIONS

MIN

TYP

MAX

400

61

UNITS

kHz

f

(Note 2)

SCL

TIMEOUT

t

29

ms

Bus Free Time Between STOP

and START Conditions

t

Figure 2

1.3

µs

BUF

Hold Time (Repeated) START

Condition

t

0.6

HD,STA

Repeated START Condition

Setup Time

t

Figure 2

0.6

SU,STA

STOP Condition Setup Time

Data Hold Time

t

µs

ns

µs

SU,STO

t

Figure 2 (Note 3)

Figure 2

0.9

HD,DAT

Data Setup Time

t

100

1.3

0.7

SU,DAT

SCL Low Period

t

Figure 2

LOW

SCL High Period

t

Figure 2

HIGH

V+ < 3.3V

500

250

SDA Fall Time

t

Figure 2 (Notes 4, 5)

(Note 6)

ns

F

V+ ≥ 3.3V

Pulse Width of Spike Suppressed

PORT TIMING

t

50

SP

PV

Output Data Valid

t

Figure 7

3

µs

Input Data Setup Time

Input Data Hold Time

INTERRUPT TIMING

Interrupt Valid

27

0

t

Figure 9

30.5

2

µs

IV

Interrupt Reset

t

IR

Note 1: All parameters are 100% production tested at T = +25°C. Specifications over temperature are guaranteed by design.

A

Note 2: Minimum SCL clock frequency is limited by the MAX7311 bus timeout feature, which resets the serial bus interface if either

SDA or SCL is held low for a minimum of 25ms. Disable bus timeout feature for DC operation.

Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V of the SCL

IL

signal) in order to bridge the undefined region SCL’s falling edge.

Note 4: C = total capacitance of one bus line in pF.

B

Note 5: The maximum t for the SDA and SCL bus lines is specified at 300ns. The maximum fall time for the SDA output stage t is

F

specified at 250ns. This allows series protection resistors to be connected between the SDA and SCL pins and the

SDA/SCL bus lines without exceeding the maximum specified t .

F

Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

_______________________________________________________________________________________

3

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Typical Operating Characteristics

(T = +25°C, unless otherwise noted.)

A

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

SUPPLY CURRENT

vs. TEMPERATURE

STANDBY SUPPLY CURRENT

vs. TEMPERATURE

100

90

80

70

60

50

40

30

20

10

0

100

9

8

7

6

5

4

3

2

1

0

+

f

= 400kHz

SCL = V

f

= 400kHz

SCL

90

80

70

60

50

40

30

20

10

0

ALL I/Os UNLOADED

+

V = 5V

+

V = 3.3V

+

V = 2V

+

V = 2V

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

-50 -25

0

25

50

75 100 125

-50 -25

0

25

50

75 100 125

TEMPERATURE (°C)

I/O SINK CURRENT

vs. OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs. OUTPUT LOW VOLTAGE

I/O SINK CURRENT

vs. OUTPUT LOW VOLTAGE

24

22

20

18

16

14

12

10

8

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

+

V = 2V

V = 5V

V = 3.3V

T

A

= -40°C

T

A

= -40°C

T

A

= -40°C

T

A

= +25°C

T

= +25°C

A

T

A

= +25°C

A

T

A

= +125°C

T

= +125°C

T

A

= +125°C

6

4

2

0

0.1

0.2

0.3

(V)

0.4

0.5

0.6

0

0.1

0.2

0.3

(V)

0.4

0.5

0.6

0

0.1

0.2

V

0.3

(V)

0.4

0.5

V

OL

I/O OUTPUT LOW VOLTAGE

vs. TEMPERATURE

I/O SOURCE CURRENT

vs. OUTPUT HIGH VOLTAGE

I/O SOURCE CURRENT

vs. OUTPUT HIGH VOLTAGE

400

350

300

250

200

150

100

50

45

40

35

30

25

20

15

10

5

25

20

15

10

5

+

V = 3.3V

V = 2V

+

T = -40°C

A

T

= -40°C

A

V = 5V, I

= 10mA

SINK

T

A

= +25°C

T

= +25°C

A

+

V = 2V, I

= 10mA

SINK

T

= +125°C

A

T

A

= +125°C

+

V = 5V, I

= 1mA

SINK

+

V = 2V, I

= 1mA

25

SINK

0

-50 -25

0

50

75 100 125

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7

+

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7

+

TEMPERATURE (°C)

V - V (V)

OH

V - V (V)

OH

4

_______________________________________________________________________________________

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Typical Operating Characteristics (continued)

(T = +25°C, unless otherwise noted.)

A

I/O SOURCE CURRENT

vs. OUTPUT HIGH VOLTAGE

I/O HIGH VOLTAGE vs. TEMPERATURE

50

45

40

35

30

25

20

15

10

5

500

400

300

200

100

0

+

V = 5V

T

A

= -40°C

+

V = 2V, I

= 10mA

SOURCE

T

= +25°C

A

T

= +125°C

A

+

V = 5V, I

= 10mA

SOURCE

0

0.1

0.2

+

0.3

0.4

0.5

0.6

-50 -25

0

25

50

75 100 125

V - V (V)

TEMPERATURE (°C)

OH

Pin Description

NAME

FUNCTION

TSSOP/

THIN

SSOP/SO

QFN

1

2

22

INT

AD1

AD2

Interrupt Output (Open Drain)

Address Input 1

23

3

24

Address Input 2

4–11

12

1–±

9

I/O0–I/O7 Input/Output Port 1

GND Supply Ground

I/O±–I/O15 Input/Output Port 2

13–20

21

10–17

1±

AD0

SCL

SDA

V⁺

Address Input 0

Serial Clock Line

Serial Data Line

22

19

23

20

24

21

Supply Voltage. Bypass with a 0.047µF capacitor to GND.

Exposed

pad

—

PAD

Exposed Pad on Package Underside. Connect to GND.

_______________________________________________________________________________________

5

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

AD0

AD1

AD2

8 BIT

INPUT/OUTPUT

PORT 1

WRITE PULSE

READ PULSE

SMBus

CONTROL

SCL

SDA

INPUT

FILTER

I/O8

I/O9

8 BIT

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

INPUT/OUTPUT

PORT 2

N

WRITE PULSE

READ PULSE

V⁺

INT

POWER-ON

RESET

MAX7311

GND

Figure 1. MAX7311 Block Diagram

SDA

t

BUF

t

SU, STA

SU, DAT

t

HD, STA

t

LOW

t

SU, STO

HD, DAT

SCL

t

HIGH

t

HD, STA

t

F

R

REPEATED START CONDITION

START CONDITION

STOP CONDITION START CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagram

Detailed Description

Serial Interface

The MAX7311 general-purpose input/output (GPIO)

peripheral provides up to 16 I/O ports, controlled

through an I²C-compatible serial interface. The

MAX7311 consists of input port registers, output port

registers, polarity inversion registers, configuration reg-

isters, and a bus-timeout register. Upon power-on, all

I/O lines are set as inputs. Three slave ID address select

pins, AD0, AD1, and AD2, choose one of 64 slave ID

addresses, including the eight addresses supported by

the Phillips PCA9555. Table 1 is the register address

table. Tables 2–6 show detailed register information.

Serial Addressing

The MAX7311 operates as a slave that sends and

receives data through a 2-wire interface. The interface

uses a serial data line (SDA) and a serial clock line

(SCL) to achieve bidirectional communication between

master(s) and slave(s). A master, typically a microcon-

troller, initiates all data transfers to and from the

MAX7311, and generates the SCL clock that synchro-

nizes the data transfer (Figure 2).

6

_______________________________________________________________________________________

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

SDA

S

P

SCL

START

STOP

CONDITION

Figure 3. START and STOP Conditions

SDA

SCL

DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED

Figure 4. Bit Transfer

START CONDITION

SCL

CLOCK PULSE FOR ACKNOWLEDGMENT

1

2

8

9

SDA

BY TRANSMITTER

S

SDA

BY RECEIVER

Figure 5. Acknowledge

Each transmission consists of a START condition sent by

a master, followed by the MAX7311 7-bit slave address

plus R/W bit, a register address byte, 1 or more data

bytes, and finally a STOP condition (Figure 3).

Bit Transfer

One data bit is transferred during each clock pulse.

The data on SDA must remain stable while SCL is high

(Figure 4).

START and STOP Conditions

Both SCL and SDA remain high when the interface is

not busy. A master signals the beginning of a transmis-

sion with a START (S) condition by transitioning SDA

from high to low while SCL is high. When the master

has finished communicating with the slave, it issues a

STOP (P) condition by transitioning SDA from low to

high while SCL is high. The bus is then free for another

transmission (Figure 3).

Acknowledge

The acknowledge bit is a clocked 9th bit, which the

recipient uses as a handshake receipt of each byte of

data (Figure 5). Thus, each byte transferred effectively

requires 9 bits. The master generates the 9th clock

pulse, and the recipient pulls down SDA during the

acknowledge clock pulse, such that the SDA line is sta-

ble low during the high period of the clock pulse. When

the master is transmitting to the MAX7311, the

_______________________________________________________________________________________

7

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

MAX7311 generates the acknowledge bit since the

MAX7311 is the recipient. When the MAX7311 is trans-

mitting to the master, the master generates the

acknowledge bit.

Slave address pins AD2, AD1, and AD0 choose 1 of 64

slave ID addresses (Table 7).

Data Bus Transaction

The command byte is the first byte to follow the ±-bit

device slave address during a write transmission

(Table 1, Figure 7). The command byte is used to deter-

mine which of the following registers are written or read.

Slave Address

The MAX7311 has a 7-bit-long slave address (Figure 6).

The ±th bit following the 7-bit slave address is the R/W

bit. Set this bit low for a write command and high for a

read command.

Writing to Port Registers

Transmit data to the MAX7311 by sending the device

slave address and setting the LSB to a logic zero. The

command byte is sent after the address and deter-

mines which registers receive the data following the

command byte (Figure 7).

PROGRAMMABLE

SDA

A6

A5

A4

A3

A2

A1

A0

R/W ACK

MSB

LSB

Figure 6. Slave Address

Table 1. Command Byte Register

COMMAND BYTE

ADDRESS (HEX)

POWER-UP

PROTOCOL

FUNCTION

DEFAULT

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x0±

0xFF

Input port 1

Read byte

XXXX XXXX

1111 1111

0000 0000

1111 1111

0000 0001

—

Input port 2

Read byte

Output port 1

Read/write byte

—

Output port 2

Port 1 polarity inversion

Port 2 polarity inversion

Port 1 configuration

Port 2 configuration

Timeout register

Factory reserved. (Do not write to this register.)

SCL

SDA

1

2

3

4

5

6

7

8

9

COMMAND BYTE

PORT 1 DATA

PORT 2 DATA

S

A

0

1

0

A

7

6

5

4

3

2

1

0

A

7

6

5

4

3

2

1

0

A

SLAVE ADDRESS

R/W

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM SLAVE

START

CONDITION

WRITE TO PORT

DATA OUT PORT 1

t

PV

READ FROM PORT 2

t

PV

Figure 7. Writes to Output Registers Through Write Byte Protocol

_______________________________________________________________________________________

8

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Eight of the MAX7311’s nine registers are configured to

operate as four register pairs: input ports, output ports,

polarity inversion ports, and configuration ports. After

sending 1 byte of data to one register, the next byte is

sent to the other register in the pair. For example, if the

first byte of data is sent to output port 2, then the next

byte of data is stored in output port 1. An unlimited

number of data bytes can be sent in one write transmis-

sion. This allows each ±-bit register to be updated inde-

pendently of the other registers.

Reading Port Registers

To read the device data, the bus master must first send

the MAX7311 address with the R/W bit set to zero, fol-

lowed by the command byte, which determines which

register is accessed. After a restart, the bus master

must then send the MAX7311 address with the R/W bit

set to 1. Data from the register defined by the com-

mand byte is then sent from the MAX7311 to the master

(Figures ±, 9).

ACKNOWLEDGE

FROM SLAVE

DATA FROM LOWER OR

UPPER BYTE OF REGISTER

DATA FROM LOWER OR

UPPER BYTE OF REGISTER

S

SLAVE ADDRESS

0

A

COMMAND BYTE

A

S

SLAVE ADDRESS

1

A

MSB

DATA

LSB

A

MSB

DATA

LSB NA

P

ACKNOWLEDGE

FROM SLAVE

R/W

ACKNOWLEDGE

FROM SLAVE

MASTER TRANSMITTER BECOMES

MASTER RECEIVER AND SLAVE

RECEIVER BECOMES SLAVE TRANSMITTER

TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.

Figure 8. Read from Register

SCL

1

2

3

4

5

6

7

8

9

S

SLAVE ADDRESS

R/W

1

A

7

PORT 1 DATA

0

A

7

PORT 2 DATA

0

A

7

PORT 1 DATA

0

A

7

PORT 2 DATA

0

1

P

ACKNOWLEDGE

FROM SLAVE

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NONACKNOWLEDGE

FROM MASTER

READ FROM PORT 1

DATA INTO PORT 1

READ FROM PORT 2

DATA INTO PORT 2

INT

t

IV

t

IR

TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE

STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS

VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.

Figure 9. Read from Input Registers

_______________________________________________________________________________________

9

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Data is clocked into a register on the falling edge of the

acknowledge clock pulse. After reading the first byte,

additional bytes may be read and reflect the content in

the other register in the pair. For example, if input port 1

is read, the next byte read is input port 2. An unlimited

number of data bytes can be read in one read trans-

mission, but the final byte received must not be

acknowledged by the bus master.

Input/Output Port

When an I/O is configured as an input, FETs Q1 and Q2

are off (Figure 10), creating a high-impedance input with

+

a nominal 100kΩ pullup to V . All inputs are overvoltage

protected to 5.5V, independent of supply voltage. When

a port is configured as an output, either Q1 or Q2 is on,

depending on the state of the output port register. When

+

V powers up, an internal power-on reset sets all regis-

ters to their respective defaults (Table 1).

Interrupt (INT)

The open-drain interrupt output, INT, activates when

one of the port pins changes states and only when the

pin is configured as an input. The interrupt deactivates

when the input returns to its previous state or the input

register is read (Figure 9). A pin configured as an out-

put does not cause an interrupt. Each ±-bit port register

is read independently; therefore, an interrupt caused

by port 1 is not cleared by a read of port 2’s register.

Input Port Registers

The input port registers (Table 2) are read-only ports.

They reflect the incoming logic levels of the pins,

regardless of whether the pin is defined as an input or

an output by the respective configuration register. A

read of the input port 1 register latches the current

value of I/O0–I/O7. A read of the input port 2 register

latches the current value of I/O±–I/O15. Writes to the

input port registers are ignored.

Changing an I/O from an output to an input may cause

a false interrupt to occur if the state of that I/O does not

match the content of the input port register.

OUTPUT PORT

REGISTER DATA

CONFIGURATION

REGISTER

V

DD

SET

Q1

DATA FROM

SHIFT REGISTER

100kΩ

D

Q

I/O PIN

WRITE

CONFIGURATION

PULSE

CLR

SET

CLR

DATA FROM

SHIFT REGISTER

D

Q

WRITE PULSE

Q2

OUTPUT PORT

REGISTER

V

SS

INPUT PORT

REGISTER

SET

D

Q

INPUT PORT

READ PULSE

REGISTER DATA

Q

CLR

SET

TO INT

POWER-ON

RESET

POLARITY

REGISTER

DATA

DATA FROM

SHIFT REGISTER

D

Q

WRITE POLARITY

PULSE

CLR

POLARITY INVERSION

REGISTER

Figure 10. Simplified Schematic of I/Os

10 ______________________________________________________________________________________

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Table 2. Registers 0x00, 0x01—Input Port Registers

I7

I6

I5

I4

I3

I2

I1

I0

BIT

I15

I14

I13

I12

I11

I10

I9

I±

Table 3. Registers 0x02, 0x03—Output Port Registers

O7

O15

1

O6

O14

1

O5

O13

1

O4

O12

1

O3

O11

1

O2

O10

1

O1

O9

1

O0

O8

1

BIT

Power-up default

Table 4. Registers 0x04, 0x05—Polarity Inversion Registers

I/O7

I/O15

0

I/O6

I/O14

0

I/O5

I/O13

0

I/O4

I/O12

0

I/O3

I/O11

0

I/O2

I/O10

0

I/O1

I/O9

0

I/O0

I/O8

0

BIT

Power-up default

Table 5. Registers 0x06, 0x07—Configuration Registers

I/O7

I/O15

1

I/O6

I/O14

1

I/O5

I/O13

1

I/O4

I/O12

1

I/O3

I/O11

1

I/O2

I/O10

1

I/O1

I/O9

1

I/O0

I/O8

1

BIT

Power-up default

Bus Timeout

Table 6. Register 0x08—Timeout Register

Set register 0x0± LSB (bit 0) to enable the bus timeout

function (Table 6) or clear it to disable the bus timeout

function. Enabling the timeout feature resets the

MAX7311 serial bus interface when SCL stops either high

or low during a read or write. If either SCL or SDA is low

for more than 29ms after the start of a valid serial transfer,

the interface resets itself and sets up SDA as an input.

The MAX7311 then waits for another START condition.

BIT

7

6

5

4

3

2

1

0

Power-up default

0

1

Output Port Registers

The output port registers (Table 3) set the outgoing

logic levels of the I/Os defined as outputs by the

respective configuration register. Reads from the out-

put port registers reflect the value that is in the flip-flop

controlling the output selection, not the actual I/O value.

Standby

The MAX7311 goes into standby when the I²C bus is

idle. Standby supply current is typically 2.9µA.

Polarity Inversion Registers

The polarity inversion registers (Table 4) enable polarity

inversion of pins defined as inputs by the respective

port configuration registers. Set the bit in the polarity

inversion register to invert the corresponding port pin’s

polarity. Clear the bit in the polarity inversion register to

retain the corresponding port pin’s original polarity.

Applications Information

Hot Insertion

The I/O ports I/O0–I/O15, interrupt output INT, and serial

interface SDA, SCL, AD0–2 remain high impedance with

up to 6V asserted on them when the MAX7311 is pow-

ered down (V+ = 0V). The MAX7311 can therefore be

used in hot-swap applications. Note that each I/O’s

100kΩ pullup effectively becomes a 100kΩ pulldown

when the MAX7311 is powered down.

Configuration Registers

The configuration registers (Table 5) configure the

directions of the I/O pins. Set the bit in the respective

configuration register to enable the corresponding port

as an input. Clear the bit in the configuration register to

enable the corresponding port as an output.

Power-Supply Consideration

The MAX7311 operates from a supply voltage of 2V to

5.5V. Bypass the power supply to GND with a 0.047µF

capacitor as close to the device as possible. For the

QFN version, connect the exposed pad to GND.

______________________________________________________________________________________ 11

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Table 7. MAX7311 Address Map

AD2

GND

V⁺

AD1

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

GND

V⁺

AD0

GND

V⁺

A6

0

A5

0

1

A4

1

0

A3

0

1

0

1

A2

0

1

0

1

0

1

0

1

A1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADDRESS (HEX)

0x20

0x22

GND

V⁺

0x24

0x26

GND

V⁺

0x2±

0x2A

0x2C

0x2E

0x30

0x32

GND

V⁺

GND

V⁺

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

GND

V⁺

0x34

0x36

0x3±

0x3A

0x3C

0x3E

0x40

0x42

V⁺

GND

V⁺

GND

V⁺

0x44

V⁺

0x46

GND

V⁺

GND

V⁺

0x4±

0x4A

0x4C

0x4E

0x50

0x52

GND

V⁺

GND

V⁺

GND

V⁺

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

0x54

V⁺

0x56

GND

V⁺

0x5±

0x5A

0x5C

0x5E

V⁺

12 ______________________________________________________________________________________

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Table 7. MAX7311 Address Map (continued)

AD2

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

AD1

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

GND

V⁺

AD0

GND

V⁺

A6

1

A5

0

1

A4

1

0

A3

0

1

0

1

A2

0

1

0

1

0

1

0

1

A1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ADDRESS (HEX)

0xA0

0xA2

GND

V⁺

0xA4

0xA6

GND

V⁺

0xA±

0xAA

0xAC

0xAE

0xB0

0xB2

GND

V⁺

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

GND

V⁺

0xB4

0xB6

0xB±

0xBA

0xBC

0xBE

0xC0

0xC2

0xC4

0xC6

0xC±

0xCA

0xCC

0xCE

0xD0

0xD2

0xD4

0xD6

0xD±

0xDA

0xDC

0xDE

GND

V⁺

GND

V⁺

GND

V⁺

GND

V⁺

GND

V⁺

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

V⁺

GND

V⁺

Chip Information

TRANSISTOR COUNT: 12,994

PROCESS: BiCMOS

______________________________________________________________________________________ 13

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

INCHES

MILLIMETERS

N

MAX

2.65

0.30

0.49

0.32

DIM

A

MIN

2.35

0.10

0.35

0.23

0.093

0.004

0.014

0.009

0.104

0.012

0.019

0.013

A1

B

C

e

0.050

1.27

H

E

0.291

0.394

0.016

0.299

0.419

0.050

7.40

10.00

0.40

7.60

10.65

1.27

H

L

VARIATIONS:

INCHES

1

MILLIMETERS

TOP VIEW

DIM

D

MIN

MAX

0.413

0.463

0.512

0.614

0.713

MIN

10.10

11.35

12.60

15.20

17.70

MAX

N MS013

0.398

0.447

0.496

0.598

0.697

10.50 16 AA

11.75 18 AB

13.00 20 AC

15.60 24 AD

18.10 28 AE

D

C

A

B

e

0∞-8∞

A1

L

FRONT VIEW

SIDE VIEW

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, .300" SOIC

APPROVAL

DOCUMENT CONTROL NO.

REV.

1

21-0042

B

1

14 ______________________________________________________________________________________

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

2

1

INCHES

MILLIMETERS

DIM

A

MIN

0.068

MAX

MIN

1.73

0.05

0.25

0.09

MAX

1.99

0.21

0.38

0.20

INCHES

MIN

MAX

MILLIMETERS

MIN

6.07

7.07

8.07

MAX

6.33

N

0.078

A1

B

D

0.239 0.249

0.278 0.289

0.317 0.328

14L

0.002 0.008

0.010 0.015

0.004 0.008

6.33 16L

7.33

8.33 24L

20L

C

E

H

D

SEE VARIATIONS

0.205 0.212 5.20

0.0256 BSC

0.397 0.407 10.07 10.33 28L

E

5.38

e

0.65 BSC

H

0.301 0.311 7.65

0.025 0.037 0.63

7.90

0.95

8∞

L

0∞

8∞

0∞

N

A

C

B

L

e

A1

D

NOTES:

1. D&E DO NOT INCLUDE MOLD FLASH.

2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").

3. CONTROLLING DIMENSION: MILLIMETERS.

4. MEETS JEDEC MO150.

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, SSOP, 5.3 MM

APPROVAL

DOCUMENT CONTROL NO.

REV.

5. LEADS TO BE COPLANAR WITHIN 0.10 MM.

1

21-0056

C

1

PACKAGE OUTLINE, TSSOP 4.40mm BODY

1

21-0066

I

1

______________________________________________________________________________________ 15

2-Wire-Interfaced 16-Bit I/O Port Expander

with Interrupt and Hot-Insertion Protection

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 16

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX7311AAG+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Parallel I/O Port, 16-Bit, 16 I/O, BICMOS, PDSO24, 5.30 MM, MO-150, SSOP-24 信息通信管理光电二极管
文件：	总16页 (文件大小：303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX7311AAG+ [MAXIM]

相关型号：

MAX7311AAG+T

MAX7311AAG-T

MAX7311ATG

MAX7311ATG+

MAX7311ATG+

MAX7311ATG+GH7

MAX7311ATG+T

MAX7311ATG+T

MAX7311ATG+TGH7

MAX7311ATG-T

MAX7311AUG

MAX7311AUG+T