MAX7314AEG+ [MAXIM]
Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24;
| 型号： | MAX7314AEG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Parallel I/O Port, 8-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24 信息通信管理 光电二极管 外围集成电路 |
| 文件： | 总25页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3170; Rev 4; 4/05
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
General Description
Features
The MAX7314 I2C-compatible serial interfaced periph-
eral provides microprocessors with 16 I/O ports plus one
output-only port and one input-only port. Each I/O port
can be individually configured as either an open-drain
current-sinking output rated at 50mA and 5.5V, or a logic
input with transition detection. The output-only port can
be assigned as an interrupt output for transition detec-
tion. The outputs are capable of driving LEDs, or provid-
ing logic outputs with external resistive pullup up to 5.5V.
♦ 400kbps, 2-Wire Serial Interface, 5.5V Tolerant
♦ 2V to 3.6V Operation
♦ Overall 8-Bit PWM LED Intensity Control
Global 16-Step Intensity Control
Individual 16-Step Intensity Controls
♦ 2-Phase LED Blinking
♦ 50mA Maximum Port Output Current
♦ Supports Hot Insertion
Eight-bit PWM current control is built in for all 17 output
ports. A 4-bit global control applies to all LED outputs
and provides coarse adjustment of current from fully off
to fully on with 14 intensity steps in between. Each out-
put has an individual 4-bit control, which further divides
the globally set current into 16 more steps.
Alternatively, the current control can be configured as a
single 8-bit control that sets all outputs at once.
♦ Outputs are 5.5V-Rated Open Drain
♦ Inputs are Overvoltage Protected to 5.5V
♦ Transition Detection with Interrupt Output
♦ 1.2µA (typ), 3.6µA (max) Operating Current
♦ Small 4mm x 4mm, Thin QFN Package
♦ -40°C to +125°C Temperature Range
Each output has independent blink timing with two blink
phases. All LEDs can be individually set to be on or off
during either blink phase, or to ignore the blink control.
The blink period is controlled by a clock input (up to 1kHz)
on BLINK or by a register. The BLINK input can also be
used as a logic control to turn the LEDs on and off, or as a
general-purpose input.
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
24 Thin QFN
MAX7314ATG -40°C to +125°C 4mm x 4mm T2444-4
x 0.8mm
The MAX7314 supports hot insertion. All port pins, the
INT output, SDA, SCL, RST, BLINK, and the slave
address input ADO remain high impedance in power-
down (V+ = 0V) with up to 6V asserted upon them.
MAX7314AEG -40°C to +125°C 24 QSOP
—
Typical Application Circuit
The MAX7314 is controlled through a 2-wire serial inter-
face, and uses four-level logic to allow four I2C
addresses from only one select pin.
5V
Applications
3.3V
LCD Backlights
0.047μF
LED Status Indication
Relay Drivers
V+
SDA
P0
P1
μC
SDA
SCL
I/O
P2
MAX7314
SCL
P3
Keypad Backlights
RGB LED Drivers
System I/O Ports
BLINK
RST
P4
I/O
INT
P5
INT/O16
P6
P7
P8
AD0
P9
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
Pin Configurations continued at end of data sheet.
P10
P11
P12
P13
P14
P15
3.3V
5V
GND
OUTPUT
OUTPUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V+.............................................................................-0.3V to +4V
SCL, SDA, AD0, BLINK, RST, P0–P15 .....................-0.3V to +6V
INT/O16 ...................................................................-0.3V to +8V
DC Current on P0–P15, INT/O16 ........................................55mA
DC Current on SDA.............................................................10mA
Maximum GND Current ....................................................350mA
24-Pin QSOP (derate 9.5mW/°C over +70°C)..............761mW
24-Pin QFN (derate 20.8mW/°C over +70°C) ............1666mW
Operating Temperature Range
(T
to T ) .............................................-40°C to +125°C
MIN
MAX
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2V to 3.6V, T = T
to T , unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)
MAX A
A
MIN
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Operating Supply Voltage
V+
2
3.6
V
Output Load External Supply
Voltage
V
0
5.5
V
EXT
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= +25°C
1.2
8.5
50
2.3
2.8
SCL and SDA at V+; other
digital inputs at V+ or GND;
PWM intensity control disabled
Standby Current
(Interface Idle, PWM Disabled)
I
I
I
I
= -40°C to +85°C
µA
µA
µA
µA
+
+
+
= T
to T
3.6
MIN
MAX
= +25°C
= -40°C to +85°C
= T to T
15.1
16.5
17.2
95.3
99.2
102.4
110.2
117.4
122.1
SCL and SDA at V+; other
digital inputs at V+ or GND;
PWM intensity control disabled
Supply Current
(Interface Idle, PWM Enabled)
MIN
MAX
= +25°C
= -40°C to +85°C
= T to T
Supply Current
(Interface Running, PWM
Disabled)
f
= 400kHz; other digital
SCL
inputs at V+ or GND; PWM
intensity control enabled
MIN
MAX
= +25°C
= -40°C to +85°C
= T to T
57
Supply Current
(Interface Running, PWM
Enabled)
f
= 400kHz; other digital
SCL
inputs at V+ or GND; PWM
intensity control enabled
+
MIN
MAX
Input High Voltage
SDA, SCL, AD0, BLINK, P0–P15
0.7 x
V+
V
V
V
IH
Input Low Voltage
SDA, SCL, AD0, BLINK, P0–P15
0.3 x
V+
V
IL
Input Leakage Current
SDA, SCL, AD0, BLINK, P0–P15
I , I
IH IL
0 ≤ input voltage ≤ 5.5V
-0.2
+0.2
µA
pF
Input Capacitance
SDA, SCL, AD0, BLINK, P0–P15
8
2
_______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2V to 3.6V, T = T
to T , unless otherwise noted. Typical values are at V+ = 3.3V, T = + 25°C.)
MAX A
A
MIN
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
T
A
= +25°C
0.15
0.26
V+ = 2V, I
= 20mA
V
V
V
= -40°C to +85°C
0.3
SINK
= T
to T
0.32
0.23
0.26
0.28
0.23
0.24
0.26
0.4
MIN
MAX
= +25°C
= -40°C to +85°C
= T to T
0.13
0.12
Output Low Voltage
P0–P15, INT/O16
V
V+ = 2.5V, I
V+ = 3.3V, I
= 20mA
= 20mA
OL
SINK
MIN
MAX
= +25°C
= -40°C to +85°C
= T to T
SINK
MIN
MAX
Output Low-Voltage SDA
PWM Clock Frequency
V
I
= 6mA
V
OLSDA
SINK
f
32
kHz
PWM
TIMING CHARACTERISTICS
(Typical Operating Circuit, V+ = 2V to 3.6V, T = T
to T , unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)
MAX A
A
MIN
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Serial Clock Frequency
f
400
kHz
SCL
Bus Free Time Between a STOP and a START
Condition
t
1.3
µs
BUF
Hold Time, Repeated START Condition
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
t
0.6
0.6
0.6
µs
µs
µs
µs
ns
µs
µs
HD, STA
t
SU, STA
SU, STO
HD, DAT
t
t
(Note 2)
0.9
Data Setup Time
t
180
1.3
0.7
SU, DAT
SCL Clock Low Period
t
LOW
SCL Clock High Period
t
HIGH
20 +
Rise Time of Both SDA and SCL Signals, Receiving
Fall Time of Both SDA and SCL Signals, Receiving
Fall Time of SDA Transmitting
t
(Notes 3, 4)
(Notes 3, 4)
(Notes 3, 5)
300
300
250
ns
ns
ns
R
0.1C
b
20 +
0.1C
t
F
b
20 +
t
F.TX
0.1C
b
Pulse Width of Spike Suppressed
Capacitive Load for Each Bus Line
RST Pulse Width
t
(Note 6)
(Note 3)
50
ns
pF
µs
SP
C
400
b
t
1
W
_______________________________________________________________________________________
3
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
TIMING CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2V to 3.6V, T = T
to T
, unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)
A
MIN
MAX A
(Note 1)
PARAMETER
Interrupt Valid
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
t
Figure 10
Figure 10
Figure 10
Figure 10
Figure 10
6.5
1
µs
µs
µs
ns
µs
IV
IR
Interrupt Reset
t
Output Data Valid
t
t
5
DV
DS
DH
Input Data Set-Up Time
Input Data Hold Time
100
1
t
Note 1: All parameters tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: C = total capacitance of one bus line in pF. t and t measured between 0.3 x V
and 0.7 x V
.
b
R
F
DD
DD
Note 5: I
≤ 6mA. C = total capacitance of one bus line in pF. t and t measured between 0.3 x V
and 0.7 x V
.
SINK
b
R
F
DD
DD
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
__________________________________________Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
STANDBY CURRENT vs. TEMPERATURE
(PWM DISABLED; f
= 400kHz)
(PWM ENABLED; f
= 400kHz)
SCL
SCL
10
70
60
50
40
30
20
10
0
70
65
60
55
50
45
40
35
30
25
20
15
10
5
V+ = 3.6V
PWM ENABLED
9
8
7
6
V+ = 3.6V
V+ = 3.6V
V+ = 2.7V
V+ = 2V
5
4
3
2
1
0
V+ = 2V
PWM ENABLED
V+ = 2.7V
V+ = 2V
V+ = 2.7V
PWM ENABLED
V+ = 3.6V
PWM
DISABLED
V+ = 2V
V+ = 2.7V
PWM DISABLED PWM DISABLED
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
PORT OUTPUT LOW VOLTAGE WITH 20mA
LOAD CURRENT vs. TEMPERATURE
PWM CLOCK FREQUENCY
vs. TEMPERATURE
PORT OUTPUT LOW VOLTAGE WITH 50mA
LOAD CURRENT vs. TEMPERATURE
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
ALL OUTPUTS LOADED
V+ = 3.6V
V+ = 2.7V
V+ = 2V
V+ = 2V
V+ = 2V
V+ = 2.7V
V+ = 3.6V
V+ = 3.6V
V+ = 2.7V
NORMALIZED TO V+ = 3.3V, T = +25°C
A
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SINK CURRENT vs. V
SCOPE SHOT OF 2 OUTPUT PORTS
SCOPE SHOT OF 2 OUTPUT PORTS
OL
MAX7314 toc08
MAX7314 toc07
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
MASTER INTENSITY SET TO 1/15
MASTER INTENSITY SET TO 14/15
OUTPUT 1,
2V/div
OUTPUT 1
2V/div
V+ = 2V
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16
OUTPUT 1 INDIVIDUAL INTENSITY
SET TO 1/16
V+ = 2.7V
V+ = 3.3V
OUTPUT 2
2V/div
V+ = 3.6V
OUTPUT 2,
2V/div
OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 14/15
OUTPUT 2 INDIVIDUAL INTENSITY
SET TO 15/16
ONLY ONE OUTPUT LOADED
0
5
10 15 20 25 30 35 40 45 50
SINK CURRENT (mA)
2ms/div
2ms/div
_______________________________________________________________________________________
5
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Pin Description
PIN
NAME
INT/O16
RST
FUNCTION
QSOP
QFN
Output Port. Open-drain output rated at 7V, 50mA. Configurable as interrupt
output or general-purpose output.
1
22
Reset Input. Active low clears the 2-wire interface and puts the device in the
same condition as power-up reset.
2
3
23
24
Address Input. Sets device slave address. Connect to either GND, V+, SCL,
or SDA to give four logic combinations. See Table 1.
AD0
4–11, 13–20
1–8, 10–17
P0–P15
GND
Input/Output Ports. P0–P15 are open-drain I/Os rated at 5.5V, 50mA.
Ground. Do not sink more than 350mA into the GND pin.
Input Port Configurable as Blink Control or General-Purpose Input
I2C-Compatible Serial Clock Input
12
21
22
23
9
18
19
20
BLINK
SCL
SDA
I2C-Compatible Serial Data I/O
Positive Supply Voltage. Bypass V+ to GND with a 0.047µF ceramic
capacitor.
24
—
21
V+
PAD
Exposed Pad Exposed Pad on Package Underside. Connect to GND.
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
OUTPUT PORT
REGISTER DATA
DATA FROM
SHIFT REGISTER
D
Q
OUTPUT
PORT
REGISTER
FF
WRITE
CONFIGURATION
PULSE
C
Q
K
D
Q
FF
C
Q
WRITE PULSE
K
I/O PIN
GND
Q2
INPUT PORT
REGISTER
INPUT PORT
REGISTER DATA
D
Q
FF
TO INT
READ PULSE
C
Q
K
Figure 1. Simplified Schematic of I/O Ports
All output ports sink loads up to 50mA connected to
external supplies up to 5.5V, independent of the
MAX7314’s supply voltage. The MAX7314 is rated for a
ground current of 350mA, allowing all 17 outputs to sink
20mA at the same time. Figure 1 shows the output
structure of the MAX7314. The ports default to inputs on
power-up.
Functional Overview
The MAX7314 is a general-purpose input/output (GPIO)
peripheral that provides 16 I/O ports, P0–P15, con-
trolled through an I2C-compatible serial interface. A
17th output-only port, INT/O16, can be configured as
an interrupt output or as a general-purpose output port.
6
_______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Port Inputs and Transition Detection
Input ports registers reflect the incoming logic levels of
the port pins, regardless of whether the pin is defined
as an input or an output. Reading an input ports regis-
ter latches the current-input logic level of the affected
eight ports. Transition detection allows all ports config-
ured as inputs to be monitored for changes in their
logic status. The action of reading an input ports regis-
ter samples the corresponding 8 port bits’ input condi-
tion. This sample is continuously compared with the
actual input conditions. A detected change in input
condition causes the INT/O16 interrupt output to go
low, if configured as an interrupt output. The interrupt is
cleared either automatically if the changed input
returns to its original state, or when the appropriate
input ports register is read.
PWM Intensity Control
The MAX7314 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity control.
PWM intensity control can be enabled on an output-by-
output basis, allowing the MAX7314 to provide any mix
of PWM LED drives and glitch-free logic outputs (Table
10). PWM can be disabled entirely, in which case all out-
put ports are static and the MAX7314 operating current
is lowest because the internal oscillator is turned off.
PWM intensity control uses a 4-bit master control and 4
bits of individual control per output (Tables 13, 14). The
4-bit master control provides 16 levels of overall intensi-
ty control, which applies to all PWM-enabled output
ports. The master control sets the maximum pulse
width from 1/15 to 15/15 of the PWM time period. The
individual settings comprise a 4-bit number, further
reducing the duty cycle to be from 1/16 to 15/16 of the
time window set by the master control.
The INT/O16 pin can be configured as either an inter-
rupt output or as a 17th output port with the same static
or blink controls as the other 16 ports (Table 4).
For applications requiring the same PWM setting for all
output ports, a single global PWM control can be used
instead of all the individual controls to simplify the con-
trol software and provide 240 steps of intensity control
(Tables 10 and 13).
Port Output Control and LED Blinking
The two blink phase 0 registers set the output logic lev-
els of the 16 ports P0–P15 (Table 8). These registers
control the port outputs if the blink function is disabled.
A duplicate pair of registers, the blink phase 1 registers,
are also used if the blink function is enabled (Table 9).
In blink mode, the port outputs can be flipped between
using the blink phase 0 registers and the blink phase 1
registers using hardware control (the BLINK input)
and/or software control (the blink flip flag in the configu-
ration register) (Table 4). The logic level of the BLINK
input can be read back through the blink status bit in
the configuration register (Table 4). The BLINK input,
therefore, can be used as a general-purpose logic input
(GPI port) if the blink function is not required.
Standby Mode
When the serial interface is idle and the PWM intensity
control is unused, the MAX7314 automatically enters
standby mode. If the PWM intensity control is used, the
operating current is slightly higher because the internal
PWM oscillator is running. When the serial interface is
active, the operating current also increases because
the MAX7314, like all I2C slaves, has to monitor every
transmission.
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
t
HIGH
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
_______________________________________________________________________________________
7
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
The MAX7314 SDA line operates as both an input and
Serial Interface
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX7314 SCL line oper-
ates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master sys-
tem has an open-drain SCL output.
Serial Addressing
The MAX7314 operates as a slave that sends and
receives data through an I2C-compatible 2-wire inter-
face. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional commu-
nication between master(s) and slave(s). A master (typ-
ically a microcontroller) initiates all data transfers to and
from the MAX7314 and generates the SCL clock that
synchronizes the data transfer (Figure 2).
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7314
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
SDA
SCL
S
P
START
STOP
CONDITION
CONDITION
Figure 3. Start and Stop Conditions
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
SDA
SCL
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7314, the device gen-
erates the acknowledge bit because the MAX7314 is
the recipient. When the MAX7314 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
DATA LINE STABLE; CHANGE OF DATA
DATA VALID
ALLOWED
Figure 4. Bit Transfer
CLOCK PULSE
FOR ACKNOWLEDGE
START
CONDITION
SCL
1
2
8
9
SDA BY
TRANSMITTER
Slave Address
The MAX7314 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
SDA BY
RECEIVER
S
Figure 5. Acknowledge
SDA
SCL
A6
1
0
0
A2
0
0
R/W
ACK
LSB
MSB
Figure 6. Slave Address
_______________________________________________________________________________________
8
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
The second (A5), third (A4), fourth (A3), sixth (A1), and
Message Format for Writing the MAX7314
A write to the MAX7314 comprises the transmission of
the MAX7314’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The com-
mand byte determines which register of the MAX7314
is to be written to by the next byte, if received (Table 2).
If a STOP condition is detected after the command byte
is received, then the MAX7314 takes no further action
beyond storing the command byte.
last (A0) bits of the MAX7314 slave address are always
1, 0, 0, 0, and 0. Slave address bits A6 and A2 are
selected by the address input AD0. AD0 can be con-
nected to GND, V+, SDA, or SCL. The MAX7314 has four
possible slave addresses (Table 1), and therefore a
maximum of four MAX7314 devices can be controlled
independently from the same interface.
Table 1. MAX7314 Address Map
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register
of the MAX7314 selected by the command byte (Figure
8). If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX7314 internal registers because the
command byte address autoincrements (Table 2). A
diagram of a write to the output ports registers (blink
phase 0 registers or blink phase 1 registers) is given in
Figure 10.
DEVICE ADDRESS
PIN AD0
A6
1
A5
1
A4
0
A3
0
A2
0
A1
0
A0
0
SCL
SDA
GND
V+
1
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
COMMAND BYTE IS STORED ON RECEIPT OF
STOP CONDITION
D15 D14 D13 D12 D11 D10
D9
D8
ACKNOWLEDGE FROM MAX7314
S
SLAVE ADDRESS
0
A
COMMAND BYTE
ACKNOWLEDGE FROM MAX7314
A
P
R/W
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7314
D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM MAX7314
HOW COMMAND BYTE AND DATA BYTE MAP INTO
MAX7314's REGISTERS
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MAX7314
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
1
BYTE
R/W
AUTOINCREMENT MEMORY ADDRESS
Figure 8. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX7314
D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM MAX7314
HOW COMMAND BYTE AND DATA BYTE MAP INTO
D7 D6 D5 D4 D3 D2 D1 D0
MAX7314's REGISTERS
ACKNOWLEDGE FROM MAX7314
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
N
BYTES
R/W
AUTOINCREMENT MEMORY ADDRESS
Figure 9. n Data Bytes Received
_______________________________________________________________________________________
9
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
WRITE TO OUTPUT PORTS REGISTERS (BLINK PHASE 0 REGISTERS/BLINK PHASE 1 REGISTERS)
SCL
SDA
1
2
3
4
5
6
7
8
0
9
SLAVE ADDRESS
A6 A5 A4 A3 A2 A1 A0
COMMAND BYTE
S
A
0
0
0
0
0
0
0
1
A MSB
DATA1
LSB
A
MSB
DATA2
LSB
A
P
ACKNOWLEDGE FROM SLAVE
START CONDITION
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
DATA1 VALID
STOP
CONDITION
R/W
P7–P0
t
DV
P15– P8
DATA2 VALID
t
DV
READ FROM INPUT PORTS REGISTERS
SCL
1
2
3
4
5
6
7
8
9
SLAVE ADDRESS
A6 A5 A4 A3 A2 A1 A0
COMMAND BYTE
DATA1
SDA
S
1
A
A
NA P
LSB
MSB
LSB
MSB
DATA6
STOP CONDITION
ACKNOWLEDGE FROM MASTER
START CONDITION
DATA1
ACKNOWLEDGE FROM SLAVE
NO ACKNOWLEDGE FROM
MASTER
R/W
P7–P0
DATA2
DATA3
DATA4
DATA6
t
DH
DATA5
P15–P8
t
DS
INTERRUPT VALID/RESET
SCL
1
2
3
4
5
6
7
8
1
9
SLAVE ADDRESS
A6 A5 A4 A3 A2 A1 A0
COMMAND BYTE
DATA2
SDA
S
A
MSB
LSB
A
MSB
DATA4
LSB NA
P
STOP CONDITION
START CONDITION
DATA1
ACKNOWLEDGE FROM SLAVE
DATA2
ACKNOWLEDGE FROM MASTER
DATA4
NO ACKNOWLEDGE FROM
MASTER
R/W
P7–P0
P15–P8
INT
DATA3
t
IV
t
IV
t
IR
t
IR
Figure 10. Read, Write, and Interrupt Timing Diagrams
Message Format for Reading
The MAX7314 is read using the MAX7314’s internally
stored command byte as an address pointer the same
way the stored command byte is used as an address
pointer for a write. The pointer autoincrements after
each data byte is read using the same rules as for a
write (Table 2). Thus, a read is initiated by first configur-
ing the MAX7314’s command byte by performing a
write (Figure 7). The master can now read n consecu-
tive bytes from the MAX7314 with the first data byte
being read from the register addressed by the initial-
ized command byte. When performing read-after-write
verification, remember to reset the command byte’s
address because the stored command byte address
has been autoincremented after the write (Table 2). A
diagram of a read from the input ports registers is
shown in Figure 10 reflecting the states of the ports.
Operation with Multiple Masters
If the MAX7314 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7314 should
use a repeated start between the write, which sets the
MAX7314’s address pointer, and the read(s) that takes
the data from the location(s) (Table 2). This is because it
is possible for master 2 to take over the bus after master
1 has set up the MAX7314’s address pointer but before
master 1 has read the data. If master 2 subsequently
changes the MAX7314’s address pointer, then master
1’s delayed read can be from an unexpected location.
Command Address Autoincrementing
The command address stored in the MAX7314 circu-
lates around grouped register functions after each data
byte is written or read (Table 2).
10 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 2. Register Address Map
ADDRESS CODE
(hex)
AUTOINCREMENT
ADDRESS
REGISTER
Read input ports P7–P0
Read input ports P15–P8
Blink phase 0 outputs P7–P0
Blink phase 0 outputs P15–P8
Ports configuration P7–P0
Ports configuration P15–P8
Blink phase 1 outputs P7–P0
Blink phase 1 outputs P15–P8
Master, O16 intensity
0x00
0x01
0x02
0x03
0x06
0x07
0x0A
0x0B
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x01
0x00
0x03
0x02
0x07
0x06
0x0B
0x0A
0x0E (no change)
0x0F (no change)
0x11
Configuration
Outputs intensity P1, P0
Outputs intensity P3, P2
Outputs intensity P5, P4
Outputs intensity P7, P6
Outputs intensity P9, P8
Outputs intensity P11, P10
Outputs intensity P13, P12
Outputs intensity P15, P14
0x12
0x13
0x14
0x15
0x16
0x17
0x10
Device Reset
Configuration Register
The configuration register is used to configure the PWM
intensity mode, interrupt, and blink behavior, operate
the INT/O16 output, and read back the interrupt status
(Table 4).
The reset input RST is an active-low input. When taken
low, RST clears any transaction to or from the MAX7314
on the serial interface and configures the internal regis-
ters to the same state as a power-up reset (Table 3),
which resets all ports as inputs. The MAX7314 then
waits for a START condition on the serial interface.
Ports Configuration
The 16 I/O ports P0 through P15 can be configured to
any combination of inputs and outputs using the ports
configuration registers (Table 5). The INT/O16 output
can also be configured as an extra general-purpose
output, and the BLINK input can be configured as an
extra general-purpose input using the configuration
register (Table 4).
Detailed Description
Initial Power-Up
On power-up, and whenever the RST input is pulled
low, all control registers are reset and the MAX7314
enters standby mode (Table 3). Power-up status makes
all ports into inputs and disables both the PWM oscilla-
tor and blink functionality. RST can be used as a hard-
ware shutdown input, which effectively turns off any
LED (or other) loads and puts the device into its lowest
power condition.
Input Ports
The input ports registers are read only (Table 6). They
reflect the incoming logic levels of the ports, regardless of
whether the port is defined as an input or an output by the
ports configuration registers. Reading an input ports reg-
ister latches the current-input logic level of the affected
eight ports. A write to an input ports register is ignored.
______________________________________________________________________________________ 11
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 3. Power-Up Configuration
ADDRESS
CODE
REGISTER DATA
REGISTER FUNCTION
POWER-UP CONDITION
(hex)
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Blink phase 0 outputs P7–P0
Blink phase 0 outputs P15–P8
Ports configuration P7–P0
High-impedance outputs
High-impedance outputs
Ports P7–P0 are inputs
Ports P15–P8 are inputs
High-impedance outputs
High-impedance outputs
0x02
0x03
0x06
0x07
0x0A
0x0B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Ports configuration P15–P8
Blink phase 1 outputs P7–P0
Blink phase 1 outputs P15–P8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PWM oscillator is disabled;
O16 is static logic output
Master, O16 intensity
0x0E
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
INT/O16 is interrupt output;
blink is disabled;
Configuration
0x0F
global intensity is enabled
Outputs intensity P1, P0
Outputs Intensity P3, P2
Outputs intensity P5, P4
Outputs intensity P7, P6
Outputs intensity P9, P8
Outputs intensity P11, P10
Outputs intensity P13, P12
Outputs intensity P15, P14
P1, P0 are static logic outputs
P3, P2 are static logic outputs
P5, P4 are static logic outputs
P7, P6 are static logic outputs
P9, P8 are static logic outputs
P11, P10 are static logic outputs
P13, P12 are static logic outputs
P15, P14 are static logic outputs
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Transition Detection
INT/O16 Output
All ports configured as inputs are always monitored for
changes in their logic status. The action of reading an
input ports register or writing to the configuration regis-
ter samples the corresponding 8 port bits’ input condi-
tion (Tables 4, 6). This sample is continuously
compared with the actual input conditions. A detected
change in input condition causes an interrupt condition.
The interrupt is cleared either automatically if the
changed input returns to its original state, or when the
appropriate input ports register is read, updating the
compared data (Figure 10). Randomly changing a port
from an output to an input may cause a false interrupt
to occur if the state of the input does not match the
content of the appropriate input ports register. The
interrupt status is available as the interrupt flag INT in
the configuration register (Table 4).
The INT/O16 output pin can be configured as either the
INT output that reflects the interrupt flag logic state or as
a general-purpose output O16. When used as a general-
purpose output, the INT/O16 pin has the same blink and
PWM intensity control capabilities as the other ports.
Set the interrupt enable I bit in the configuration register
to configure INT/O16 as the INT output (Table 4). Clear
interrupt enable to configure INT/O16 as the O16. The
O16 logic state is set by the 2 bits O1 and O0 in the
configuration register. O16 follows the rules for blinking
selected by the blink enable flag E in the configuration
register. If blinking is disabled, then interrupt output
control O0 alone sets the logic state of the INT/O16 pin.
If blinking is enabled, then both interrupt output con-
trols O0 and O1 set the logic state of the INT/O16 pin
according to the blink phase. PWM intensity control for
O16 is set by the 4 global intensity bits in the master
and O16 intensity register (Table 13).
The input status of all ports is sampled immediately
after power-up as part of the MAX7314’s internal initial-
ization, so if all the ports are pulled to valid logic levels
at that time, an interrupt does not occur at power-up.
12 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 4. Configuration Register
ADDRESS
CODE
REGISTER DATA
REGISTER
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
R/W
CONFIGURATION
0x0F
Write device configuration
Read back device configuration
Disable blink
0
INT
BLINK
O1
O0
I
G
B
E
1
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
1
1
Enable blink
Flip blink register (see text)
Disable global intensity control—intensity
is set by registers 0x10–0x17 for ports P0
through P15 when configured as outputs,
and by D3–D0 of register 0x0E for
INT/O16 when INT/O16 pin is configured
as an output port
—
X
X
X
X
X
0
X
X
Enable global intensity control—intensity
for all ports configured as outputs is set
by D3–D0 of register 0x0E
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
Disable data change interrupt—INT/O16
output is controlled by the O0 and O1 bits
Enable data change interrupt—INT/O16
output is controlled by port input data
change
INT/O16 output is low (blink is disabled)
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
X
X
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
1
INT/O16 output is high impedance (blink
is disabled)
INT/O16 output is low during blink phase 0
INT/O16 output is high impedance during
blink phase 0
INT/O16 output is low during blink phase 1
INT/O16 output is high impedance during
blink phase 1
X = Don’t care.
______________________________________________________________________________________ 13
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 4. Configuration Register (continued)
ADDRESS
CODE
REGISTER DATA
REGISTER
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
R/W
CONFIGURATION
Write device configuration
0
1
INT
X
BLINK
O1
X
O0
X
I
G
X
X
B
X
X
E
X
X
Read back device configuration
Read back BLINK input pin status—
input is low
1
1
0
1
X
X
0x0F
Read back BLINK input pin status—
input is high
X
X
X
Read back data change interrupt status
—data change is not detected, and
INT/O16 output is high when interrupt
enable (I bit) is set
1
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read back data change interrupt status
—data change is detected, and INT/O16
output is low when interrupt enable (I bit) is set
X = Don’t care.
The blink mode is disabled by clearing the blink enable
flag E in the configuration register (Table 4). When blink
mode is disabled, the state of the blink flip flag is
ignored, and the blink phase 0 registers alone control
the output ports.
Blink Mode
In blink mode, the output ports can be flipped between
using either the blink phase 0 registers or the blink
phase 1 registers. Flip control is both hardware (the
BLINK input) and software control (the blink flip flag B
in the configuration register) (Table 4).
Blink Phase Registers
When the blink function is disabled, the two blink phase
0 registers set the logic levels of the 16 ports (P0
through P15) when configured as outputs (Table 8). A
duplicate pair of registers called the blink phase 1 reg-
isters are also used if the blink function is enabled (Table
9). A logic high sets the appropriate output port high
impedance, while a logic low makes the port go low.
The blink function can be used for LED effects by pro-
gramming different display patterns in the two sets of
output port registers, and using the software or hard-
ware controls to flip between the patterns.
If the blink phase 1 registers are written with 0xFF, then
the BLINK input can be used as a hardware disable to,
for example, instantly turn off an LED pattern pro-
grammed into the blink phase 0 registers. This tech-
nique can be further extended by driving the BLINK
input with a PWM signal to modulate the LED current to
provide fading effects.
BLINK ENABLE FLAG E
BLINK PHASE REGISTERS
BLINK FLIP FLAG B
The blink mode is enabled by setting the blink enable flag
E in the configuration register (Table 4). When blink mode
is enabled, the states of the blink flip flag and the BLINK
input are EXOR’ed to set the phase, and the output ports
are set by either the blink phase 0 registers or the blink
phase 1 registers (Figure 11) (Table 7).
BLINK INPUT
Figure 11. Blink Logic
14 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 5. Ports Configuration Registers
ADDRESS
CODE
REGISTER DATA
REGISTER
R/W
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
Ports configuration P7–P0
(1 = input, 0 = output)
0
1
0
1
0x06
0x07
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Read back ports configuration P7–P0
Ports configuration P15–P8
(1 = input, 0 = output)
OP15 OP14 OP13 OP12 OP11 OP10
OP9
OP8
Read back ports configuration P15–P8
Table 6. Input Ports Registers
ADDRESS
CODE
REGISTER DATA
REGISTER
R/W
(hex)
D7
IP7
D6
IP6
D5
IP5
D4
IP4
D3
IP3
D2
IP2
D1
IP1
IP9
D0
IP0
IP8
Read input ports P7–P0
Read input ports P15–P8
1
1
0x00
0x01
IP15
IP14
IP13
IP12
IP11
IP10
Table 7. Blink Logic
BLINK FLIP FLAG
EXOR
BLINK INPUT PIN
BLINK ENABLE
FLAG E
BLINK FLIP
FLAG B
BLINK INPUT
PIN
BLINK FUNCTION OUTPUT REGISTERS USED
0
1
X
0
0
1
1
X
0
1
0
1
X
0
1
1
0
Disabled
Enabled
Blink phase 0 registers
Blink phase 0 registers
Blink phase 1 registers
Blink phase 1 registers
Blink phase 0 registers
Reading a blink phase register reads the value stored
in the register, not the actual port condition. The port
output itself may or may not be at a valid logic level,
depending on the external load connected.
The MAX7314 can be configured to provide any combi-
nation of PWM outputs and glitch-free logic outputs.
Each PWM output has an individual 4-bit intensity con-
trol (Table 14). When all outputs are to be used with the
same PWM setting, the outputs can be controlled
together instead using the global intensity control
(Table 13). Table 10 shows how to set up the MAX7314
to suit a particular application.
The 17th output, O16, is controlled through 2 bits in the
configuration register, which provide the same static or
blink control as the other 16 output ports.
PWM Intensity Control
The MAX7314 includes an internal oscillator, nominally
32kHz, to generate PWM timing for LED intensity con-
trol or other applications such as PWM trim DACs.
PWM can be disabled entirely for all the outputs. In this
case, all outputs are static and the MAX7314 operating
current is lowest because the internal PWM oscillator is
turned off.
PWM Timing
The PWM control uses a 240-step PWM period, divided
into 15 master intensity timeslots. Each master intensity
timeslot is divided further into 16 PWM cycles (Figure 12).
The master intensity operates as a gate, allowing the indi-
vidual output settings to be enabled from 1 to 15 timeslots
per PWM period (Figures 13, 14, 15) (Table 13).
______________________________________________________________________________________ 15
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 8. Blink Phase 0 Registers
ADDRESS
CODE
(hex)
REGISTER DATA
REGISTER
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Write outputs P7–P0 phase 0
Read back outputs P7–P0 phase 0
Write outputs P15–P8 phase 0
0
1
0
1
0x02
0x03
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP15 OP14 OP13 OP12 OP11 OP10
OP9
OP8
Read back outputs P15–P8 phase 0
Table 9. Blink Phase 1 Registers
ADDRESS
CODE
REGISTER DATA
REGISTER
R/W
(hex)
D7
D6
D5
D4
D3
D2
D1
D0
Write outputs P7–P0 phase 1
Read back outputs P7–P0 phase 1
Write outputs P15–P8 phase 1
0
1
0
1
0x0A
0x0B
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP15 OP14 OP13 OP12 OP11 OP10
OP9
OP8
Read back outputs P15–P8 phase 1
Each output’s individual 4-bit intensity control only
operates during the number of timeslots gated by the
master intensity. The individual controls provide 16
intensity settings from 1/16 through 16/16 (Table 14).
Using PWM Intensity Controls with Blink Enabled
When blink is enabled (Table 7), the blink phase 0 regis-
ters and blink phase 1 registers specify each output’s
logic level during the PWM on-time during the respective
blink phases (Tables 8 and 9). The effect of setting an
output’s blink phase x register bit to zero or 1 is shown in
Table 12. LEDs can be flipped between either directly on
and off, or between a variety of high/low PWM intensities.
Figures 16, 17, and 18 show examples of individual
intensity control settings. The highest value an individ-
ual or global setting can be set to is 16/16. This setting
forces the output to ignore the master control, and fol-
low the logic level set by the appropriate blink phase
register bit. The output becomes a glitch-free static out-
put with no PWM.
Global/O16 Intensity Control
The 4 bits used for output O16’s PWM individual inten-
sity setting also double as the global intensity control
(Table 13). Global intensity simplifies the PWM settings
when the application requires them all to be the same,
such as for backlight applications, by replacing the 17
individual settings with 1 setting. Global intensity is
enabled with the global intensity flag G in the configura-
tion register (Table 4). When global PWM control is
used, the 4 bits of master intensity and 4 bits of global
intensity effectively combine to provide an 8-bit, 240-
step intensity control applying to all outputs.
Using PWM Intensity Controls with Blink Disabled
When blink is disabled (Table 7), the blink phase 0 reg-
isters specify each output’s logic level during the PWM
on-time (Table 8). The effect of setting an output’s blink
phase 0 register bit to zero or 1 is shown in Table 11.
With its output bit set to zero, an LED can be controlled
with 16 intensity settings from 1/16th duty through fully
on, but cannot be turned fully off using the PWM inten-
sity control. With its output bit set to 1, an LED can be
controlled with 16 intensity settings from fully off
through 15/16th duty.
It is not possible to apply global PWM control to a sub-
set of the ports, and use the others as logic outputs. To
mix static logic outputs and PWM outputs, individual
PWM control must be selected (Table 10).
16 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 10. PWM Application Scenarios
APPLICATION
RECOMMENDED CONFIGURATION
Set the master, O16 intensity register 0x0E to any value 0x00 to 0xOF.
The global intensity G bit in the configuration register is don't care.
The output intensity registers 0x10 through 0x17 are don't care.
All outputs static without PWM
Set the master and global intensity register 0x0E to any value from 0x10 to 0xFF.
Clear global intensity G bit to zero in the configuration register to disable global
intensity control.
For the static outputs, set the output intensity value to 0xF.
For the PWM outputs, set the output intensity value in the 0x0 to 0xE range.
A mix of static and PWM outputs, with PWM
outputs using different PWM settings
A mix of static and PWM outputs, with PWM As above. Global intensity control cannot be used with a mix of static and PWM
outputs all using the same PWM setting
outputs, so write the individual intensity registers with the same PWM value.
Set the master, O16 intensity register 0x0E to any value from 0x10 to 0xFF.
Set global intensity G bit to 1 in the configuration register to enable global intensity
control.
The master, O16 intensity register 0x0E is the only intensity register used.
The output intensity registers 0x10 through 0x17 are don't care.
All outputs PWM using the same PWM
setting
ONE PWM PERIOD IS 240 CYCLES OF THE 32kHz PWM
OSCILLATOR. A PWM PERIOD CONTAINS 15 MASTER
INTENSITY TIMESLOTS
14
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
2
15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
EACH MASTER INTENSITY
TIMESLOT CONTAINS 16
PWM CYCLES
Figure 12. PWM Timing
.
14 15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1
2
14 15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1
2
.
.
Figure 13. Master Set to 1/15
Figure 15. Master Set to 15/15
.
14 15
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1
2
.
Figure 14. Master Set to 14/15
______________________________________________________________________________________ 17
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
MASTER INTENSITY TIMESLOT
10 11 12 13 14 15 16
NEXT MASTER INTENSITY TIMESLOT
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Figure 16. Individual (or Global) Set to 1/16
MASTER INTENSITY TIMESLOT
10 11 12 13 14 15 16
NEXT MASTER INTENSITY TIMESLOT
7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
Figure 17. Individual (or Global) Set to 15/16
MASTER INTENSITY TIMESLOT CONTROL IS IGNORED
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Figure 18. Individual (or Global) Set to 16/16
Table 11. PWM Intensity Settings (Blink Disabled)
OUTPUT
(OR
GLOBAL)
INTENSITY
SETTING
LED BEHAVIOR WHEN
OUTPUT BLINK PHASE 0
REGISTER BIT = 0
LED BEHAVIOR WHEN
OUTPUT BLINK PHASE 0
REGISTER BIT = 1
PWM DUTY CYCLE
OUTPUT BLINK PHASE 0
REGISTER BIT = 0
PWM DUTY CYCLE
OUTPUT BLINK PHASE 0
REGISTER = 1
(LED IS ON WHEN
OUTPUT IS LOW)
(LED IS ON WHEN
OUTPUT IS LOW)
LOW TIME HIGH TIME
LOW TIME HIGH TIME
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
1/16
2/16
15/16
14/16
13/16
12/16
11/16
10/16
9/16
Lowest PWM intensity
15/16
14/16
13/16
12/16
11/16
10/16
9/16
1/16
2/16
Highest PWM intensity
3/16
3/16
4/16
4/16
5/16
5/16
6/16
6/16
7/16
7/16
8/16
8/16
8/16
8/16
9/16
7/16
7/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
6/16
6/16
10/16
11/16
12/16
13/16
14/16
15/16
5/16
5/16
4/16
4/16
3/16
3/16
2/16
2/16
1/16
Highest PWM intensity
1/16
Lowest PWM intensity
LED off continuously
Full intensity, no PWM
(LED on continuously)
Static high
impedance impedance
Static high
0xF
Static low
Static low
18 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 12. PWM Intensity Settings (Blink Enabled)
EXAMPLES OF LED BLINK BEHAVIOR
(LED IS ON WHEN OUTPUT IS LOW)
PWM DUTY CYCLE
OUTPUT BLINK
PHASE X
PWM DUTY CYCLE
OUTPUT BLINK
PHASE X
OUTPUT
(OR
GLOBAL)
INTENSITY
SETTING
BLINK PHASE 0
REGISTER BIT = 0
BLINK PHASE 0
REGISTER BIT = 1
REGISTER BIT = 0
REGISTER = 1
BLINK PHASE 1
REGISTER BIT = 1
BLINK PHASE 1
REGISTER BIT = 0
LOW
TIME
HIGH
TIME
LOW
TIME
HIGH
TIME
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
1/16
2/16
15/16
14/16
13/16
12/16
11/16
10/16
9/16
15/16
14/16
13/16
12/16
11/16
10/16
9/16
1/16
2/16
3/16
3/16
Phase 0: LED on at low intensity
Phase 1: LED on at high intensity
Phase 0: LED on at high intensity
Phase 1: LED on at low intensity
4/16
4/16
5/16
5/16
6/16
6/16
7/16
7/16
8/16
8/16
8/16
8/16
Output is half intensity during both blink phases
9/16
7/16
7/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
6/16
6/16
10/16
11/16
12/16
13/16
14/16
15/16
5/16
5/16
Phase 0: LED on at high intensity
Phase 1: LED on at low intensity
Phase 0: LED on at low intensity
Phase 1: LED on at high intensity
4/16
4/16
3/16
3/16
2/16
2/16
1/16
1/16
Static high Static high Phase 0: LED on continuously
impedance impedance Phase 1: LED off continuously
Phase 0: LED off continuously
Phase 1: LED on continuously
0xF
Static low Static low
Driving LED Loads
When driving LEDs, a resistor in series with the LED
must be used to limit the LED current to no more than
50mA. Choose the resistor value according to the fol-
lowing formula:
Applications Information
Hot Insertion
I/O ports P0–P15, interrupt output INT/O16, RST input,
BLINK input, and serial interface SDA, SCL, AD0 remain
high impedance with up to 6V asserted on them when
the MAX7314 is powered down (V+ = 0V). The MAX7314
can therefore be used in hot-swap applications.
R
LED
= (V
- V
- V ) / I
LED OL LED
SUPPLY
where:
is the resistance of the resistor in series with the
Output Level Translation
The open-drain output architecture allows the ports to
level translate the outputs to higher or lower voltages
than the MAX7314 supply. An external pullup resistor
can be used on any output to convert the high-imped-
ance logic-high condition to a positive voltage level.
The resistor can be connected to any voltage up to
5.5V. For interfacing CMOS inputs, a pullup resistor
value of 220kΩ is a good starting point. Use a lower
resistance to improve noise immunity, in applications
where power consumption is less critical, or where a
faster rise time is needed for a given capacitive load.
R
LED
LED (Ω).
V
V
V
is the supply voltage used to drive the LED (V).
SUPPLY
is the forward voltage of the LED (V).
LED
is the output low voltage of the MAX7314 when
OL
sinking I
LED
(V).
LED
I
is the desired operating current of the LED (A).
For example, to operate a 2.2V red LED at 14mA from a
5V supply, R = (5 - 2.2 - 0.25) / 0.014 = 182Ω.
LED
______________________________________________________________________________________ 19
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 13. Master, O16 Intensity Register
ADDRESS
CODE
(hex)
REGISTER DATA
REGISTER
R/W
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
MSB
LSB
MASTER AND GLOBAL INTENSITY
MASTER INTENSITY
O16 INTENSITY
Write master and global intensity
0
1
M3
0
M2
M1
M0
0
G3
—
G2
G1
G0
—
Read back master and global intensity
Master intensity duty cycle is 0/15 (off);
internal oscillator is disabled;
—
0
0
—
—
all outputs will be static with no PWM
Master intensity duty cycle is 1/15
Master intensity duty cycle is 2/15
Master intensity duty cycle is 3/15
—
—
—
—
—
—
—
—
0
0
0
0
0
1
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
1
1
—
1
—
1
—
0
—
1
0X0E
Master intensity duty cycle is 13/15
Master intensity duty cycle is 14/15
Master intensity duty cycle is 15/15 (full)
1
1
1
0
1
1
1
1
O16 intensity duty cycle is 1/16
O16 intensity duty cycle is 2/16
O16 intensity duty cycle is 3/16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
1
0
0
1
0
—
1
—
1
—
0
—
1
O16 intensity duty cycle is 14/16
O16 intensity duty cycle is 15/16
1
1
1
0
O16 intensity duty cycle is 16/16
(static output, no PWM)
—
—
—
—
—
1
1
1
1
20 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 14. Output Intensity Registers
ADDRESS
CODE
REGISTER DATA
REGISTER
(hex)
R/W
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
MSB
LSB
OUTPUTS P1, P0 INTENSITY
OUTPUT P1 INTENSITY
OUTPUT P0 INTENSITY
Write output P1, P0 intensity
Read back output P1, P0 intensity
Output P1 intensity duty cycle is 1/16
Output P1 intensity duty cycle is 2/16
Output P1 intensity duty cycle is 3/16
—
0
P1I3
P1I2
P1I1
P1I0
P0I3
P0I2
P0I1
P0I0
1
—
—
—
—
—
—
0
0
0
0
0
0
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
1
0
—
1
—
1
—
0
—
1
Output P1 intensity duty cycle is 14/16
Output P1 intensity duty cycle is 15/16
1
1
1
0
0X10
Output P1 intensity duty cycle is 16/16
(static logic level, no PWM)
—
1
1
1
1
—
—
—
—
Output P0 intensity duty cycle is 1/16
Output P0 intensity duty cycle is 2/16
Output P0 intensity duty cycle is 3/16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
1
0
0
1
0
—
1
—
1
—
0
—
1
Output P0 intensity duty cycle is 14/16
Output P0 intensity duty cycle is 15/16
1
1
1
0
Output P0 intensity duty cycle is 16/16
(static logic level, no PWM)
—
—
—
—
—
1
1
1
1
MSB
LSB
MSB
LSB
OUTPUTS P3, P2 INTENSITY
OUTPUT P3 INTENSITY
OUTPUT P2 INTENSITY
0x11
0x12
0x13
Write output P3, P2 intensity
0
1
P3I3
P3I2
P3I1
P3I0
P2I3
P2I2
P2I1
P2I0
Read back output P3, P2 intensity
MSB
LSB
MSB
LSB
OUTPUTS P5, P4 INTENSITY
OUTPUT P5 INTENSITY
OUTPUT P4 INTENSITY
Write output P5, P4 intensity
0
1
P5I3
P5I2
P5I1
P5I0
P4I3
P4I2
P4I1
P4I0
Read back output P5, P4 intensity
MSB
LSB
MSB
LSB
OUTPUTS P7, P6 INTENSITY
OUTPUT P7 INTENSITY
OUTPUT P6 INTENSITY
Write output P7, P6 intensity
0
1
P7I3 P7I2 P7I1 P7I0
P6I3 P6I2 P6I1 P6I0
Read back output P7, P6 intensity
_______________________________________________________________________________________ 21
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Table 14. Output Intensity Registers (continued)
ADDRESS
CODE
(hex)
REGISTER DATA
REGISTER
R/W
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
MSB
LSB
OUTPUTS P9, P8 INTENSITY
OUTPUT P9 INTENSITY
OUTPUT P8 INTENSITY
0x14
0x15
0x16
0x17
Write output P9, P8 intensity
0
1
P9I3
P9I2
P9I1
P9I0
P8I3
P8I2
P8I1
P8I0
Read back output P9, P8 intensity
MSB
LSB
MSB
LSB
OUTPUTS P11, P10 INTENSITY
OUTPUT P11 INTENSITY
OUTPUT P10 INTENSITY
Write output P11, P10 intensity
0
1
P11I3 P11I2 P11I1 P11I0 P10I3 P10I2 P10I1 P10I0
Read back output P11, P10 intensity
MSB
LSB
MSB
LSB
OUTPUTS P13, P12 INTENSITY
OUTPUT P13 INTENSITY
OUTPUT P12 INTENSITY
Write output P13, P12 intensity
0
1
P13I3 P13I2 P13I1 P13I0 P12I3 P12I2 P12I1 P12I0
Read back output P13, P12 intensity
MSB
LSB
MSB
LSB
OUTPUTS P15, P14 INTENSITY
OUTPUT P15 INTENSITY
OUTPUT P14 INTENSITY
Write output P15, P14 intensity
0
1
P15I3 P15I2 P15I1 P15I0 P14I3 P14I2 P14I1 P14I0
See master, O16 intensity register (Table 13).
Read back output P15, P14 intensity
OUTPUT O16 INTENSITY
The MAX7314 must be protected from the negative
voltage transient generated when switching off induc-
tive loads, such as relays, by connecting a reverse-
biased diode across the inductive load (Figure 19). The
peak current through the diode is the inductive load’s
operating current.
Driving Load Currents Higher than 50mA
The MAX7314 can be used to drive loads drawing more
than 50mA, like relays and high-current white LEDs, by
paralleling outputs. Use at least one output per 50mA of
load current; for example, a 5V 330mW relay draws
66mA and needs two paralleled outputs to drive it.
Ensure that the paralleled outputs chosen are controlled
by the same blink phase register, i.e., select outputs
from the P0 through P7 range, or the P8 through P15
range. This way, the paralleled outputs are turned on
and off together. Do not use output O16 as part of a
load-sharing design. O16 cannot be switched at the
same time as any of the other outputs because it is con-
trolled by a different register.
Power-Supply Considerations
The MAX7314 operates with a power-supply voltage of
2V to 3.6V. Bypass the power supply to GND with at
least 0.047µF as close to the device as possible. For
the QFN version, connect the underside exposed pad
to GND.
22 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Pin Configurations
TOP VIEW
TOP VIEW
INT/O16
RST
AD0
P0
1
2
3
4
5
6
7
8
9
24 V+
23 SDA
22 SCL
21 BLINK
20 P15
19 P14
18 P13
17 P12
16 P11
15 P10
14 P9
18 17 16 15 14 13
19
12
SCL
P10
MAX7314AEG
SDA 20
11 P9
P1
21
22
23
24
10
9
V+
P8
P2
MAX7314ATG
INT/O16
GND
P3
RST
AD0
P7
P6
8
P4
7
P5
1
2
3
4
5
6
P6 10
P7 11
THIN QFN
GND 12
13 P8
QSOP
Chip Information
TRANSISTOR COUNT: 25,991
2V TO 3.6V
PROCESS: BiCMOS
5V
0.047μF
V+
P0
P1
μC
BAS16
SDA
SCL
I/O
I/O
INT
P2
SDA
SCL
MAX7314
P3
BLINK
RST
P4
P5
INT/O16
P6
P7
P8
P9
AD0
P10
P11
P12
P13
P14
P15
GND
Figure 19. Diode-Protected Switching Inductive Load
______________________________________________________________________________________ 23
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
24 ______________________________________________________________________________________
18-Port GPIO with LED Intensity Control,
Interrupt, and Hot-Insertion Protection
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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