MAX7356ETG+ [MAXIM]
1-to-8 I2C Bus Switches/Multiplexers with Bus Lock-Up Detection, Isolation, and Notification;
| 型号： | MAX7356ETG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1-to-8 I2C Bus Switches/Multiplexers with Bus Lock-Up Detection, Isolation, and Notification |
| 文件： | 总22页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4207; Rev 0; 9/08
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
General Description
Features
The MAX7356/MAX7357/MAX7358 8-channel I2C
switches/multiplexers expand the main I2C bus to any
combination of 8 extended I2C buses. They enable a
master on the main bus to isolate and communicate
with devices or groups of devices that may otherwise
have slave address conflicts. Any extended bus can be
connected or disconnected by control packets from the
main I2C bus writing to the main control register of
these I2C switches.
o Bus Lock-Up Detection and Isolation (MAX7357,
MAX7358)
o Host Notification on Detection of Lock-Up
(MAX7357, MAX7358)
o Maintain Fault Diagnostic Information (MAX7357,
MAX7358)
o Dual-Function RST/INT Provides Lock-Up
Notification and Hardware Reset (MAX7357,
MAX7358)
2
o RST Input Resets I C Interface (MAX7358)
The MAX7357 and MAX7358 feature an enhanced
mode that includes a built-in timer used to monitor all
extended buses for lock-up conditions. If the clock or
data line of any of these buses is low for more than
25ms (typ), a lock condition is detected. An optional
interrupt can be generated through the bidirectional
RST/INT. The master can read the bus lock-up register
to find out which extended bus is locked up. The mas-
ter can also enable the MAX7357 or the MAX7358 to
send a “flush-out” sequence on the faulty channel.
There is an optional preconnection check that
can be enabled to toggle the extended bus clock and
data line low then high to ensure the downstream bus is
not locked high prior to connecting it to the host bus.
o 3 Address Control Inputs
o Low R
Switches
ON
o Logic-Level Translation
o Low 0.1µA (typ) Standby Current
o Support Hot Insertion
o 100kbps Standard-Mode or 400kbps Fast-Mode
2
I C Interface
o Address Translation Allows Multiple Device with
Same ID
o 5.5V-Tolerant Inputs
o 2.3V to 5.5V Supply
The MAX7356/MAX7357/MAX7358 are transparent
to signals sent and received at each channel, allowing
multiple masters. Any device connected to an I2C
bus can transmit and receive signals; however, only the
master connected to the host side of the MAX7356/
MAX7357/MAX7358 should address the device.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 TQFN-EP*
24 TSSOP
MAX7356ETG+
MAX7356EUG+**
MAX7357ETG+
MAX7357EUG+**
MAX7358ETG+
MAX7358EUG+**
The MAX7356/MAX7357/MAX7358 are available in 24-pin
TSSOP and TQFN packages and are specified over the
extended -40°C to +85°C temperature range.
24 TQFN-EP*
24 TSSOP
24 TQFN-EP*
24 TSSOP
Applications
Servers
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
RAID
Base Stations
Control and Automation Devices
SFP Control Interface
Networking Equipment
Selector Guide
ENHANCED
MODE
PRECONNECTION
WIGGLE TEST
POWER-UP
STATE
RST/INT
BIDIRECTIONAL
PART
MAX7356
MAX7357
MAX7358
No
Yes
Yes
No
Basic mode
Enhanced mode
Basic mode
RST only
Yes
Yes, enhanced mode only
Yes, enhanced mode only
Yes
Typical Operating Circuit and Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
Junction-to-Case Thermal Resistance (θJC) (Note 1)
V
.................................................................. -0.3V to +6.0V
24-Pin TSSOP...............................................................13°C/W
24-Pin TQFN................................................................3.0°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 1)
DD
All Other Pins.....................................................-0.3V to +6.0V
Input Currents
V
DD
...............................................................................100mA
24-Pin TSSOP............................................................72.0°C/W
24-Pin TQFN..............................................................36.0°C/W
Operating Temperature Range ......................... -40°C to +85°C
Junction Temperature .................................................... +150°C
Storage Temperature Range ........................... -65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
GND ..............................................................................100mA
All Input Pins..................................................................... 20mA
Output Current ....................................................................25mA
Continuous Power Dissipation (T = +70°C)
A
24-Pin TSSOP (derate 13.9mW/°C above +70°C) .....1111mW
24-Pin TQFN (derate 27.8mW/°C above +70°C) .......2222mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (3.3V SUPPLY)
(V
= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.) (Notes 2–5)
DD A
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
Supply Voltage
V
I
2.3
3.6
50
V
DD
Basic mode
30
45
V
= 3.6V;
DD
no load, f
400kHz
=
Supply Current
µA
SCL
DD
Enhanced mode
(MAX7357/MAX7358 only)
6/MAX7358
70
Standby Current
I
No load, V = V or GND, V = 3.6V
DD
0.1
1.4
0.4
1
µA
V
STB
I
DD
Power-On Reset Voltage
Power-On Reset Hysteresis
INPUT SCL, INPUT/OUTPUT SDA
V
V
rising
0.9
2.1
POR
DD
V
V
HYST
0.3 x
Low-Level Input Voltage
High-Level Input Voltage
V
V
V
IL
V
DD
0.7 x
V
IH
V
DD
3
V
V
V
= 0.4V
= 0.6V
OL
Low-Level Output Current
I
mA
OL
6
OL
Input Leakage Current
Input Capacitance
I
, I
LH LI
and V
= V or GND
DD
-1
+1
µA
pF
SCL
SDA
C
V = GND
15
I
I
SELECT INPUTS A0 to A2, RST
0.3 x
Low-Level Input Voltage
High-Level Input Voltage
V
V
V
IL
V
DD
0.7 x
V
IH
V
DD
Input Leakage Current
Input Capacitance
I
A0 to A2, and RST at V or GND
-1
+1
µA
pF
LI
DD
C
V = GND
I
2
I
2
_______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
ELECTRICAL CHARACTERISTICS (3.3V SUPPLY) (continued)
(V
= +2.3V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, T = +25°C.) (Notes 2–5)
DD
A
DD A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PASS GATE
V
V
V
V
V
V
= 3.0V to 3.6V, V = 0.4V, I = 15mA
5
7
11
16
30
55
DD
O
O
Switch Resistance
R
Ω
ON
= 2.3V to 2.7V, V = 0.4V, I = 10mA
DD
O
O
= V
= 3.3V, I
= -100µA
1.9
SWin
SWin
SWin
SWin
DD
SWout
= V = 3.0V to 3.6V, I
= -100µA
1.6
2.8
DD
SWout
Switch Output Voltage
V
V
SW
= V
= 2.5V, I
= -100µA
1.5
DD
SWout
= V = 2.3V to 2.7V, I
= -100µA
1.1
-1
2.0
+1
DD
SWout
Basic mode
Leakage Current
I
V = V or GND
DD
µA
pF
Enhanced mode
(MAX7357/MAX7358)
L
I
-2
+2
+1
Input/Output Capacitance
OUTPUT RST/INT
C
V = GND
I
3
IO
Low-Level Output Current
Leakage Current
I
V
V
= 0.4V (MAX7357/MAX7358)
3
mA
µA
OL
OL
I
, I
= V or GND
DD
-1
LH LI
RST/INT
ELECTRICAL CHARACTERISTICS (5V SUPPLY)
(V
= +4.5V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +5V, T = +25°C.) (Notes 2–5)
DD A
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER SUPPLY
Supply Voltage
V
I
4.5
5.5
DD
Basic mode
65
90
100
V
= 5V;
DD
Supply Current
no load, f
400kHz
=
SCL
µA
Enhanced mode
(MAX7357/MAX7358 only)
DD
130
Standby Current
I
No load, V = V or GND, V = 5.5V
DD
0.2
1.4
0.4
1
µA
V
STB
I
DD
Power-On Reset Voltage
Power-On Reset Hysteresis
INPUT SCL, INPUT/OUTPUT SDA
V
V
rising
0.9
2.1
POR
DD
V
V
HYST
0.3 x
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Current
V
V
V
IL
V
DD
0.7 x
V
IH
V
DD
V
V
V
= 0.4V
= 0.6V
3
OL
I
mA
OL
6
OL
Input Leakage Current
I
, I
LH LI
= V
= V or GND
DD
-1
+1
µA
pF
SCL
SDA
Input Capacitance
C
V = GND
15
I
I
SELECT INPUTS A0 TO A2, RST
0.3 x
Low-Level Input Voltage
V
V
IL
V
DD
0.7 x
High-Level Input Voltage
Input Leakage Current
V
V
IH
V
DD
I
A0 to A2, and RST pins at V
or GND
-1
+1
µA
LI
DD
_______________________________________________________________________________________
3
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
ELECTRICAL CHARACTERISTICS (5V SUPPLY) (continued)
(V
= +4.5V to +5.5V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +5V, T = +25°C.) (Notes 2–5)
DD A
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Capacitance
PASS GATE
C
V = GND
I
2
pF
I
Switch Resistance
R
V
V
V
= 4.5V to 5.5V, V = 0.4V, I = 15mA
4
9
24
Ω
ON
DD
O
O
= V
= 5.0V, I
= -100µA
3.6
SWin
SWin
DD
SWout
Switch Output Voltage
V
V
SW
= V = 4.5V to 5.5V, I
= -100µA
2.6
-1
4.5
+1
DD
SWout
MAX7356
Leakage Current
I
V = V or GND
DD
µA
pF
Enhanced mode
(MAX7357/MAX7358)
L
I
-2
+2
+1
Input/Output Capacitance
OUTPUT RST/INT
C
V = GND
I
3
IO
Low-Level Output Current
Leakage Current
I
V
V
= 0.4V (MAX7357/MAX7358)
3
mA
µA
OL
OL
I
, I
= V or GND
DD
-1
LH LI
RST/INT
TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3)
(V
= 2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.3
UNITS
ns
Propagation Delay from SDA to
SD_ or SCL to SC_
t
(Note 7)
PD
SCL Clock Frequency
f
0
100
kHz
µs
SCL
BUF
Bus Free Time Between a STOP
and START Condition
6/MAX7358
t
4.7
Hold Time (Repeated) START
Condition After this Period, the
First Clock Pulse is Generated
t
t
4.0
µs
HD;STA
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
t
4.7
4.0
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
4.7
µs
SU;STA
Setup Time for a STOP Condition
Data Hold Time
t
4.0
0
µs
µs
ns
SU;STO
t
(Note 8)
3.45
HD;DAT
Data Setup Time
t
250
SU;DAT
Rise Time of Both SDA and SCL
Signals
t
1000
300
400
50
ns
ns
pF
ns
R
Fall Time of Both SDA and SCL
Signals
t
F
Capacitive Load for Each Bus
Line
C
b
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
t
SP
4
_______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
TIMING CHARACTERISTICS (STANDARD-MODE) (Figures 1, 2, 3) (continued)
(V
= 2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
1
UNITS
(High to low)
(Low to high)
Data Valid Time
t
µs
VD;DAT
VD:ACK
0.6
1
Data Valid Acknowledge
Low-Level Reset Time
Reset Time
t
µs
ns
ns
ns
t
5
WL(rst)
t
500
0
rst
t
REC;STA
Recovery to Start
TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3)
(V
= 2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.3
UNITS
Propagation Delay from SDA to
SD_ or SCL to SC_
t
(Note 7)
ns
PD
SCL Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between a STOP
and START Condition
t
1.3
BUF
Hold Time (Repeated) START
Condition After this Period,
the First Clock Pulse is Generated
t
t
0.6
µs
HD;STA
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
µs
SU;STA
SU;STO
Setup Time for a STOP Condition
Data Hold Time
t
0.6
0
µs
µs
ns
t
(Note 8)
0.9
HD;DAT
Data Setup Time
t
100
SU;DAT
Rise Time of Both SDA and SCL
Signals
20 +
t
300
300
400
50
ns
ns
pF
ns
µs
R
0.1C
b
Fall Time of Both SDA and SCL
Signals
20 +
0.1C
t
F
b
Capacitive Load for Each Bus
Line
C
b
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
t
SP
(High to low)
(Low to high)
1
0.6
1
Data Valid Time
t
VD;DAT
Data Valid Acknowledge
Low-Level Reset Time
Reset Time
t
µs
ns
ns
ns
VD;ACK
t
5
WL(rst)
t
500
0
rst
t
REC;STA
Recovery to START
_______________________________________________________________________________________
5
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
TIMING CHARACTERISTICS (FAST-MODE) (Figures 1, 2, 3) (continued)
(V
= 2.3V to 5.5V, T = -40°C to +85°C, unless otherwise noted.) (Notes 2, 6)
A
DD
Note 2: All devices are 100% production tested at T = +25°C. Specifications are over -40°C to +85°C and are guaranteed by
A
design.
Note 3: Subscript SW refers to all SC_ and SD_ pins.
Note 4: V
= Switch input voltage; I
= Current between SD_ and SDA or SC_ and SCL. See Figure 4.
SWin
SWout
Note 5: V = V
or V
.
I
SD_
SC_
Note 6: All timing is measured using 20% and 80% levels, unless otherwise noted.
and the 15pF load capacitance.
Note 7: Pass gate propagation delay is calculated from the 20Ω typical R
ON
Note 8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
of the SCL signed)
IH(min)
to bridge the undefined region of the falling edge of SCL.
SDA
t
t
HD;STA
t
R
t
SP
t
BUF
F
t
LOW
SCL
t
t
SU;STO
t
t
HIGH
SU;STA
HD;STA
t
t
SU;DAT
HD;DAT
Sr
P
S
P
Figure 1. 2-Wire Serial-Interface Timing Diagram
6/MAX7358
SCL
SDA
t
t
rst
REC;STA
RESET
t
WL(rst)
Figure 2. RST Timing Diagram
6
_______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
START
CONDITION
(S)
BIT 7
MSB
(A7)
STOP
CONDITION
(P)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
t
t
t
SU;STA
LOW
HIGH
1/f
SCL
SCL
t
BUF
t
r
t
f
SDA
t
t
t
t
t
SU;STO
HD;STA
t
HD;DAT
VD;DAT
VD;ACK
SU;DAT
2
Figure 3. I C Bus Timing Diagram
DEVICE
V
SW
+
V
SWin
I
SWout
-
Figure 4. Switch Output Voltage and Current
Typical Operating Characteristics
(V
= +5V, T = +25°C, unless otherwise noted.)
A
DD
V
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SCL FREQUENCY
SW
5.5
100
80
60
40
20
0
100
80
60
40
20
0
f
= 400kHz
SCL
I
= 100µA
SWout
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ENHANCED MODE
ENHANCED MODE
BASIC MODE
BASIC MODE
2.3
3.1
3.9
(V)
4.7
5.5
2.3
3.1
3.9
(V)
4.7
5.5
0
100
200
(kHz)
300
400
V
V
f
DD
DD
SCL
_______________________________________________________________________________________
7
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
Pin Description
PIN
NAME
FUNCTION
TQFN
1
TSSOP
4
SD0
SC0
SD1
SC1
SD2
SC2
SD3
SC3
GND
SD4
SC4
SD5
SC5
SD6
SC6
SD7
SC7
A2
I2C Bus0 Serial Data
I2C Bus0 Serial Clock
I2C Bus1 Serial Data
I2C Bus1 Serial Clock
I2C Bus2 Serial Data
I2C Bus2 Serial Clock
I2C Bus3 Serial Data
I2C Bus3 Serial Clock
Supply Ground
I2C Bus4 Serial Data
I2C Bus4 Serial Clock
I2C Bus5 Serial Data
I2C Bus5 Serial Clock
I2C Bus6 Serial Data
I2C Bus6 Serial Clock
I2C Bus7 Serial Data
I2C Bus7 Serial Clock
Device Address Bit 2
Main I2C Bus Clock
Main I2C Bus Data
2
5
3
6
4
7
5
8
6
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SCL
SDA
6/MAX7358
V
Supply Voltage
DD
A0
Device Address Bit 0
Device Address Bit 1
2
A1
Active-Low Reset Input and Interrupt Output. RST resets the MAX7356 by a host. RST/INT on
the MAX7357 or MAX7358 is bidirectional. RST/INT is used to reset the device by a host or by
the device to send an interrupt signal to the host.
RST
(RST/INT)
24
3
—
—
EP
Exposed Pad (TQFN Only). Connect EP to ground. Do not use EP as the only ground connection.
( ) For the MAX7357/MAX7358 only.
8
_______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
Functional Diagram
SC0
SC1
SC2
SC3
SC6
SC7
SD0
SD1
SD2
SD3
SD6
SD7
SWITCH ENABLE/DISABLE
LOCK-UP DETECTION
AND WIGGLE TEST
REGISTER BANK WITH SWITCH CONTROL LOGIC
POWER-ON
RESET
V
DD
A0
A1
A2
SCL
SDA
2
GLITCH FILTER
I C BUS
CONTROL
RST (RST/INT)
INT LOGIC
GND
( ) ONLY FOR THE MAX7357 AND MAX7358
_______________________________________________________________________________________
9
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
Enhanced Mode of Operation
Detailed Description
(MAX7357/MAX7358)
The MAX7356/MAX7357/MAX7358 devices are 1-to-8
The MAX7357 and MAX7358 feature an enhanced
I2C multiplexers/switches for connecting a large num-
mode of operation that enable features and registers
ber of I2C components to a single master. The circuits
that are unavailable in the basic mode of operation.
connect a main I2C bus to any combination of 8 extend-
When operating in enhanced mode, there are 7 regis-
ed I2C buses. They enable a master on the main bus to
ters available to the host. Features such as bus lock-up
isolate and communicate with devices or groups of
detection, preconnection fault tests, and diagnostic
devices that may otherwise have slave address con-
information are made available to the user. A special
flicts. Any extended bus can be connected or discon-
sequence of commands can switch the MAX7357 or
nected by control packets from the main I2C bus writing
MAX7358 from basic mode to enhanced mode, and a
to the main control register of these I2C switches.
simple write to the configuration register can switch the
The MAX7357/MAX7358 feature a built-in timer used to
monitor all extended buses, for lock-up conditions. If the
data line of any of these buses is low for more than
25ms, a lock condition is detected. An optional interrupt
can be generated through the bidirectional RST/INT pin.
The master can read the bus lock-up register to find out
which extended bus is locked up. The master can also
optionally enable the MAX7357 or MAX7358 to send a
flush-out sequence on the faulty channel. There is an
optional preconnection check that can be enabled,
which toggles the extended bus clock and data line low
then high to ensure that the downstream bus is not
locked high prior to connecting it to the host bus.
devices from enhanced mode back to basic mode.
Entering Basic Mode from
Enhanced Mode
(MAX7357/MAX7358)
When the 7 registers of Table 2 are enabled, the
MAX7357 and MAX7358 can be put into basic mode by
setting bit B6 of the configuration register. When basic
mode is entered, the value of all registers return to their
POR value. B6 of the configuration register is also main-
tained to allow operation in basic mode. When in basic
mode, the MAX7357 and MAX7358 can be returned to
full feature mode by receiving a special sequence of
commands from the host as described below.
The bus lock-up detection and isolation features are
enabled by writing a unique series of I2C commands to
the MAX7357/MAX7358.
The sequence of I2C commands for enabling the
MAX7357 or MAX7358 enhanced features (bus lock-up
detection, isolation, and notification) as well as access
to the additional 6 registers consists of a write byte, a
read byte, another write byte, and another read byte
with no data bytes following any of these write or read
bytes, as shown in Figure 5. A write byte consists of
the 7-bit MAX7357 or MAX7358 device address fol-
lowed by a 0. A read byte consists of the 7-bit
MAX7357 or MAX7358 device address followed by a 1.
The special sequence begins with a START condition
and ends with a STOP condition. Repeated START
conditions are used to interconnect these write and
read bytes.
6/MAX7358
Power-On Reset
When power is applied to V , an internal power-on
DD
reset (POR) holds the MAX7356/MAX7357/MAX7358 in
a reset state until V
has reached V
. At this point,
DD
POR
the reset condition is released and the MAX7356/
MAX7357/MAX7358 registers and I2C state machine
are initialized to their default states.
Basic Mode of Operation
The MAX7356/MAX7357/MAX7358 feature a basic
mode of operation. In basic mode, the device operates
solely as a collection of analog switches that enable
any combination of the extended buses (SC_, SD_)
to be connected to the host-side bus (SCL, SDA). Only
the switch control register is accessible in basic mode
of operation.
The complete special sequence of I2C commands
needs to be received by the MAX7357 or MAX7358 to
activate the enhanced mode.
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
S
ADDRESS OF MUX/SWT PART
START
0
A
Sr
ADDRESS OF MUX/SWT PART
1
A
Sr
ADDRESS OF MUX/SWT PART
0
A
Sr
ADDRESS OF MUX/SWT PART
1
A
P
W
R
W
R
STOP
2
Figure 5. The Special Sequence of I C Commands for Turning on the Full Feature
10 ______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
Bus Lock-Up Detection, Isolation,
and Notification Operation
(MAX7357/MAX7358)
Preconnection Wiggle Test
(Stuck High Fault)
(MAX7357/MAX7358)
By setting bit B7 in the configuration register to 1, a pre-
connection wiggle test is enabled for all downstream
buses. This test only runs on the downstream bus when
the bus is selected through the switch control register.
Enabling this test does not affect any bus that is already
connected to the host bus; however, deselecting and
subsequently reselecting the bus will cause the test to
occur. The test is performed when the switch control reg-
ister bit (or bits if multiple buses are selected in the same
I2C transaction) toggles from 0 to 1 and a stop condition
is received. It consists of the MAX7357 or MAX7358
pulling the downstream clock line low, then the down-
stream data line low. Both lines are checked for a nomi-
nal low value, and then the clock line is released followed
by the data line (Note: This is an I2C stop condition and
is seen by any I2C devices connected to the extended
bus). If either the clock or data line (or both) fail to pull
low during the test, the MAX7357 or MAX7358 do not
allow that downstream bus to connect to the host. If the
optional interrupt notification bit is set (B0), the device
notifies the host that a fault has occurred. The I2C master
can then read the MAX7357 or MAX7358 registers to find
out which bus or buses caused the fault. Faults detected
by this test are stored in the preconnection fault register
(0x06). The stuck high Fault register is cleared once this
register is read, resetting the device, or disabling the
preconnection test.
SDA Stuck Low
If either line of any downstream bus is low for a period
exceeding 25ms between t and t in Figure 6, the
1
2
MAX7357/MAX7358 detect a lock-up fault on that bus
and takes the action configured by the user. If the lock-
up is not on the main bus, SDA and SCL return to the
high state at the same time. The MAX7357 or MAX7358
then identifies which SD_ or SC_ is still pulled low. If the
optional interrupt function is enabled (by setting B0 of
the configuration register), an active-low interrupt is
generated at RST/INT.
If B4 in the configuration register is set to 1, then only
faults on connected buses cause the MAX7357 or
MAX7358 to disconnect all buses from each other.
When this is the case, faults detected on disconnected
buses set the flag in the lock-up status register, and, if
enabled, notify the host of the fault, but do not discon-
nect the buses from one another.
B1 of the configuration register enables the flush-out
sequence. If this bit is set to 1, the MAX7357 or
MAX7358 attempts to send a flush-out sequence over
the locked SD_ and SC_ pair (the sequence begins at
t in Figure 6). If the flush-out sequence is successful,
5
the locked bus (SD_ and SC_) is released at t (Figure
6
6). The I2C master (at SDA and SCL) reads the
MAX7357 or MAX7358 lock-up status register to iden-
tify the locked-up bus. If RST/INT is enabled as an
interrupt, it is released once a read command to the
lock-up indication register is received by the MAX7357
Device Address
The MAX7356/MAX7357/MAX7358 family of devices
has selectable device addresses through three external
inputs. The slave address consists of 4 fixed bits
(A6–A3 set to 1110); followed by 3 pin-programmable
bits (A2, A1, A0), as shown in Figure 7. The addresses
A2, A1, and A0 can also be driven dynamically if
required, but the values must be stable when they are
expected in the address sequence.
or MAX7358 (shown at t in Figure 6). The RST/INT
7
can also be automatically released after a 1.6s delay
by setting bit 2 of the configuration register.
t
3
t
1
t
t
t
4
t
6
7
5
t
2
BYTE1
BYTE4
SDA
SCL
SD_
SC_
FLUSH-OUT DATA
RST/INT
NOTE: THE FLUSH-OUT SEQUENCE RUNS AT AN SC_ FREQUENCY OF 40kHz.
THE HOST MAY COMMUNICATE AT UP TO 400kHz. THE TIMING SHOWN IS NOT TO SCALE.
Figure 6. Bus Lock-Up Detection, Isolation, and Notification Timing Diagram
______________________________________________________________________________________ 11
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
Register Map (MAX7357/MAX7358)
PIN-SELECTABLE BITS
The MAX7357 and MAX7358 have 7 registers (shown in
Table 2) that can be accessed through the I2C bus. The
MAX7357 powers up with all of these registers accessi-
A6 A5 A4 A3 A2 A1 A0 R/W
ble. The initial register address counter is at 0x00. The
MAX7358 powers up in basic mode with only the switch
FIXED
control register available. Writing to a MAX7358
changes only the contents of the switch control register.
By sending a unique I2C sequence to the MAX7358, all
7 registers become available.
Figure 7. MAX7356/MAX7357/MAX7358 Slave Address
Available addresses depend on the hardware connec-
tions of pins A2, A1, and A0 as shown in Table 1.
Register Access Protocol (MAX7356)
Only the MAX7356 device address is required to gain
access to its registers. A typical I2C command to com-
municate with the MAX7356 starts with its device
address followed directly by data bytes.
The last bit following the slave address bit A0 on an I2C
command defines the operation to be performed. When
the last bit sets to logic 1, a read is selected while logic
0 selects a write operation.
Table 1. MAX7356/MAX7357/MAX7358 Switch Multiplexer Device Address
A2
A1
A0
A6
A5
A4
A3
A2
A1
A0
CONNECTION
CONNECTION
CONNECTION
GND
GND
GND
GND
GND
GND
GND
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V
DD
V
V
GND
DD
DD
V
DD
V
V
V
V
GND
GND
GND
DD
DD
DD
DD
V
DD
V
GND
6/MAX7358
DD
V
V
DD
DD
Table 2. MAX7357/MAX7358 Enhanced-Mode Register Map
POR DEFAULT SETTING
INTERNAL
ADDRESS
NEXT
ADDRESS
REGISTER NAME
ACCESS
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
Switch Control
Configuration
0x00
0x01
0x01
0x02
R/W
R/W
0
0
0
0
0
0
0
1
0x00 (W)
0x03 (R)
Flush-Out Sequence
Lock-Up Indication
Traffic Prior to Lock-Up
Stuck High Fault
0x02
1
1
1
1
1
1
1
1
R/W
0x03
0x04
0x05
0x06
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x04
0x05
0x06
0x00
R
R
R
R
Table 3. MAX7357 and MAX7358 Basic-
Mode Register Map
POR DEFAULT SETTING
REGISTER
NAME
ACCESS
B7 B6 B5 B4 B3 B2 B1 B0
Switch
Control
0
0
0
0
0
0
0
0
R/W
12 ______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
Table 4. Switch Control Register Channel Selection
B7
B6
X
X
X
X
X
X
X
X
X
X
X
X
0
B5
X
X
X
X
X
X
X
X
X
X
0
B4
X
X
X
X
X
X
X
X
0
B3
X
X
X
X
X
X
0
B2
X
X
X
X
0
B1
X
X
0
B0
0
COMMAND
Channel 0 disabled
X
X
1
Channel 0 enabled
Channel 1 disabled
Channel 1 enabled
Channel 2 disabled
Channel 2 enabled
Channel 3 disabled
Channel 3 enabled
Channel 4 disabled
Channel 4 enabled
Channel 5 disabled
Channel 5 enabled
Channel 6 disabled
Channel 6 enabled
Channel 7 disabled
Channel 7 enabled
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
1
0
X
X
1
X = Don’t care.
Only the switch control register can be accessed through
an I2C write or read command. All data bytes are for
the switch control register. The last data byte in an I2C
write command is retained by the switch control register.
For basic mode, only the switch control register can be
accessed through an I2C write or read command. All
data bytes are for the switch control register. The last
data byte in an I2C write command is retained by the
switch control register. Incomplete bytes are ignored.
Register Access Protocol
(MAX7357/MAX7358)
Switch Control Register
The switch control register (Figure 8) selects which
channels will be connected to the main I2C bus. This
register can be written and read through the main I2C
bus. The POR value for the switch control register is
0x00—all switches disconnected.
Only the MAX7357 or MAX7358 I2C device address is
required to gain access to its registers. A typical I2C
command to communicate with the MAX7357 or
MAX7358 starts with its device address and is followed
directly by data bytes. Internal register addresses are
not used in an I2C write or read command.
A SC_/SD_ downstream pair, or channel, is selected by
the contents of the switch control register. All bits of the
control byte are used to determine which channel is to
For enhanced mode, all registers are accessed in
sequence starting with the switch control register and
follows the order defined by internal register addresses
as shown in Table 2. Internal register addresses are
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, and 0x06 for
switch control, configuration, flush-out sequence, lock-
up indication, first and second bytes of the traffic prior
to lock-up, and preconnection fault registers, respec-
tively. When writing data to the register(s), addressing
starts with address 0x00 and goes one higher in each
subsequent byte and comes back to 0x00 again after
0x02 since the next four higher addressed registers are
read only. Read access also starts with the internal reg-
ister address 0x00 and goes one higher in each subse-
quent byte and comes back to 0x00 again after 0x06.
CHANNEL SELECTION BITS (READ/WRITE)
B7 B6 B5 B4 B3 B2 B1 B0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
Figure 8. Switch Control Register
______________________________________________________________________________________ 13
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
Table 5. Configuration Register Definition
B7
B6
B5
B4
B3
B2
B1
X
B0
0
COMMAND
Interrupt with RST/INT disabled
Interrupt with RST/INT enabled
Flush-out disabled
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
X
Flush-out enabled
X
X
X
X
X
0
X
X
RST/INT released after a register read
RST/INT released after 1.6 seconds
X
X
X
X
X
1
X
X
The lock-up register shows the current
condition
X
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
The lock-up register data is not cleared
until a read
X
X
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Disconnect all channels on bus lock-up
Disconnect only the locked up bus
Bus lock-up detection enabled
Bus lock-up detection disabled
Enhanced mode
Basic mode enabled
Preconnect test is disabled
Preconnect test is enabled
X = Don’t care.
be selected. More than one channel can be selected
simultaneously. When a channel is selected, the channel
becomes active immediately after a stop condition has
been placed on the I2C bus. This ensures that all
SC_/SD_ lines are in a HIGH state when the channel is
made active, so that no false conditions are generated at
the time of connection.
Flush-Out Sequence Register
(MAX7357/MAX7358)
6/MAX7358
A flush-out sequence can be sent to a particular auxil-
iary bus automatically after the identification of the lock-
up condition. The flush-out sequence consists of 18
SC_ clock cycles. An 8-bit sequence for the SD_ to fol-
low during the flush-out cycle can also be defined by
writing to the flush-out sequence register. By default,
the flush-out sequence register is all ones. The
MAX7357 or MAX7358 attempt to send the one-byte
sequence followed by an additional clock cycle (NACK)
two times sequentially, followed by a stop condition.
The effectiveness of sending the flush-out sequence
depends on the behavior of the locked-up device. For
an auxiliary bus with only slave devices, it is more likely
that the SCL line can still be driven by the MAX7357 or
MAX7358. In this case, a slave device may respond to
a particular flush-out sequence. After the release of the
SD_ line by a “stuck” device, the remaining sequence
on the SD_ line can be used to reset itself.
Configuration Register
(MAX7357/MAX7358)
B0 = RST/INT serves as an interrupt when a bus lock-
up condition is detected.
B1 = Flush-out sequence is sent automatically on locked-
up channels when a lock-up condition is detected.
B2 = When B0 = 1, release the RST/INT output after
asserting for 1.6 seconds.
B3 = Data in the lock-up indication register cleared only
after reading the register.
B4 = Connected channels remain connected on detec-
tion of lock-up if the lock-up condition is present only on
a channel that is not connected.
Bus Lock-Up Indication Register
(MAX7357/MAX7358)
The bus master can read the lock-up indication byte to
identify the stuck channels. A bit set to ”1” indicates
that the associated channel is stuck. The indication for
a given channel remains as long as the lock-up condi-
B5 = Disable bus lock-up detection.
B6 = Basic mode.
B7 = Enables the preconnection wiggle test for SC_
and SD_.
14 ______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
Table 6. Lock-Up Register Channel Indication
B7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
B6
X
X
X
X
X
X
X
X
X
X
X
X
0
B5
X
X
X
X
X
X
X
X
X
X
0
B4
X
X
X
X
X
X
X
X
0
B3
X
X
X
X
X
X
0
B2
X
X
X
X
0
B1
X
X
0
B0
0
COMMAND
Channel 0 no lock-up
1
Channel 0 lock-up
Channel 1 no lock-up
Channel 1 lock-up
Channel 2 no lock-up
Channel 2 lock-up
Channel 3 no lock-up
Channel 3 lock-up
Channel 4 no lock-up
Channel 4 lock-up
Channel 5 no lock-up
Channel 5 lock-up
Channel 6 no lock-up
Channel 6 lock-up
Channel 7 no lock-up
Channel 7 lock-up
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
1
X
X
1
X = Don’t care.
tion exists on that channel. If the interrupt feature is
selected (B0 of the configuration register is 1), howev-
er, the interrupt signal, RST/INT, deasserts (goes to
high) once this bus lock-up indication register is read.
If desired, setting bit B3 of the configuration register to
1 can latch the lock-up data. When B3 is set, the lock-
up bits remain set (even if a channel becomes
“unstuck”) until the lock-up indication register is read
by the master. Lock-up conditions on unconnected aux-
iliary buses are also detected. When this happens, oper-
ation is the same as when lock-ups are detected on
connected buses, except that, if desired, bus connec-
tions may be maintained as long as any detected lock-
ups are present only on unconnected channels. This
option is selected using bit B4 of the configuration regis-
ter. (Figure 9)
Traffic Prior to Lock-Up Register
(MAX7357/MAX7358)
The I2C bus traffic information per SCL clock is moni-
tored and stored into the two-byte traffic prior to lock-up
register. The first two bytes of information after a START
are stored in this register. This I2C bus traffic informa-
tion is frozen upon a bus lock-up detection. A host can
read these two bytes of traffic information upon the
reception of an interrupt signal. The contents of the traf-
fic prior to lock-up register is released and refreshed
once it is read.
The traffic prior to lock-up register can be used to iden-
tify the device address as well as the following byte
involved in a bus lock-up.
When troubleshooting an I2C bus, a scope is usually
used to capture traffic leading to the problem. The con-
tents of the traffic prior to the bus fault can usually be
determined by identifying a device address, a register
address, or a part of this data.
CHANNEL LOCK-UP INDICATION BITS (READ)
B7 B6 B5 B4 B3 B2 B1 B0
Table 7 shows contents of the traffic prior to the lock-up
register corresponding to a lock-up situation as demon-
strated by Figure 10.
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
Figure 9. Lock-Up Indication Bits
______________________________________________________________________________________ 15
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
Table 7. A Traffic Prior to Lock-Up Register Contents Example
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
NOTE
0x04
0
1
1
0
1
0
0
0
Write to the troubled device address
The first data byte with trailing 0’s due to lock-up
0x05
0
1
1
0
0
0
0
0
Table 8. Stuck HIGH Fault Register Channel Indication
B7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
B6
X
X
X
X
X
X
X
X
X
X
X
X
0
B5
X
X
X
X
X
X
X
X
X
X
0
B4
X
X
X
X
X
X
X
X
0
B3
X
X
X
X
X
X
0
B2
X
X
X
X
0
B1
X
X
0
B0
COMMAND
Channel 0 not stuck high
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Channel 0 stuck high
Channel 1 not stuck high
Channel 1 stuck high
Channel 2 not stuck high
Channel 2 stuck high
Channel 3 not stuck high
Channel 3 stuck high
Channel 4 not stuck high
Channel 4 stuck high
Channel 5 not stuck high
Channel 5 stuck high
Channel 6 not stuck high
Channel 6 stuck high
Channel 7 not stuck high
Channel 7 stuck high
1
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
1
X
X
1
6/MAX7358
X = Don’t care.
Stuck HIGH Fault Register
(MAX7357/MAX7358)
RST/INT (MAX7357/MAX7358)
The RST/INT on the MAX7357 or MAX7358 is bidirec-
tional. It can be used to reset the device by a host or by
the device to send an interrupt signal to the host. The
RST/INT input is an active-low signal. By asserting
Following an interrupt when bit B0 and B7 are enabled,
the bus master can read the stuck high fault byte to
identify stuck channels. A bit set to ”1” indicates that
the associated channel is stuck, and will not be allowed
to be connected to the host bus. The stuck high fault
register is cleared, and, if the interrupt feature is
enabled, RST/INT deasserts (goes to high) once this
register is read. However, while B7 is set to one, any
time a disconnected bus is selected for connection, the
preconnect test runs. If the fault still exists, the fault
handling sequence repeats and the faulty bus will not
be allowed to connect to the host bus.
RST/INT low for a minimum of t
externally, the
WL(rst)
device resets its registers and I2C state machine and
deselects all channels. When RST/INT is configured to
notify the host of fault conditions, and while RST/INT
is being used as an output by the MAX7357 or
MAX7358 (sending an interrupt to the host), it does not
function as a reset input. RST/INT is overvoltage-tolerant
to +6V. RST/INT must be connected to V
through a
DD
pullup resistor.
RST (MAX7356)
The RST on the MAX7356 can be used to reset the
MAX7356 by a host. The RST input is an active-low sig-
Interrupt Signal (MAX7357/MAX7358)
A bus lock-up-caused interrupt signal can be sent to a
host through the bidirectional RST/INT pin depending
on whether or not bit B0 of the configuration register is
set. Configuration register bit B2 controls how the inter-
rupt signal is reset. When B2 = 0, the interrupt signal
asserts (stays low) until the lock-up indication register is
read. When B2 = 1, the interrupt signal deasserts after
nal. By asserting this signal low for a minimum of t
WL(rst)
externally, the MAX7356 resets its I2C state machine
and deselects all channels. RST is overvoltage-tolerant
to +6V. The RST input must be connected to V
through a pullup resistor.
DD
16 ______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
ACKNOWLEDGE FROM
THE TROUBLED DEVICE
LOCK-UP
OCCURS
S
0
1
1
0
1
0
0
0
A
0
1
1
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
START
W
FIRST DATA BYTE
SECOND DATA BYTE
Figure 10. Bus Lock-Up During a 3-Byte Write Command
The interface uses a serial-data line (SDA) and a serial-
clock line (SCL) to achieve bidirectional communication
between master(s) and slave(s). The master initiates all
data transfers to and from the MAX7357 or MAX7358
and generates the SCL clock that synchronizes the
data transfer.
SDA
SCL
S
P
SDA operates as both an input and an open-drain out-
put. A pullup resistor (4.7kΩ, typ) is required on SDA.
SCL operates only as an input. A pullup resistor (4.7kΩ,
typ) is required on SCL if there are multiple masters on
the 2-wire interface, or if the master in a single-master
system has an open-drain SCL output.
STOP
CONDITION
START
CONDITION
Figure 11. Start and Stop Conditions
Each transmission consists of a START condition sent
by a master, followed by the MAX7356/MAX7357/
MAX7358’s 7-bit slave address plus R/W bit, and then
optionally 1 or more data bytes, and finally a STOP con-
dition (Figure 10).
SDA
SCL
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. The master signals the beginning of a trans-
mission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 11).
DATA STABLE
CHANGE OF
DATA VALID DATA ALLOWED
Figure 12. Bit Transfer
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 12).
SDA
ACKNOWLEDGE
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient
uses to handshake receipt of each byte of data (Figure
13). Each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the
high period of the clock pulse. When the master is
transmitting to the MAX7356/MAX7357/MAX7358, the
MAX7356/MAX7357/MAX7358 generate the acknowl-
Figure 13. Acknowledge
2 seconds. The interrupt signal asserts again once a
new lock-up is detected. The interrupt signal does not
activate the reset function.
Serial Interface
Serial Addressing
The MAX7356/MAX7357/MAX7358 operate as a slave
that sends and receives data through an I2C interface.
______________________________________________________________________________________ 17
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
edge bit because the device is the recipient. When the
MAX7356/MAX7357/MAX7358 are transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
A multibyte read from the MAX7357 or MAX7358 returns
contents of all 7 registers in sequence and repeats.
The internal register address count always begins with
the switch control register, 0x00.
Slave Address
The MAX7356/MAX7357/MAX7358 have 7-bit-long
slave addresses (Figure 6). The eighth bit following the
7-bit slave address is the R/W bit. It is low for a write
command, and high for a read command.
Accessing the MAX7357/MAX7358
in Basic Mode
In basic mode, only the switch control register is
enabled.
A single-byte write to the MAX7357 or MAX7358 sets
the switch control register.
Accessing the MAX7356
A single-byte write to the MAX7356 sets the switch
control register.
A multibyte write to the MAX7357 or MAX7358 in basic
mode writes repeatedly to the switch control register.
The last byte written determines the contents of the reg-
ister.
A multibyte write to the MAX7356 writes repeatedly to
the switch control register. The last byte written deter-
mines the contents of the register.
A single-byte read from the MAX7357 or MAX7358
returns the contents of the switch control register.
A multibyte read (2 or more bytes before the I2C STOP
bit) from the MAX7357 or MAX7358 returns the contents
of the switch control register repeatedly.
A single-byte read from the MAX7356 returns the con-
tents of the switch control register.
A multibyte read (2 or more bytes before the I2C STOP
bit) from the MAX7356 returns the contents of the
switch control register repeatedly.
Writing to the MAX7356
The MAX7356’s switch control register can be written by
an I2C write command starting with the device address
for the MAX7356 and followed by data bytes. The last
data byte is stored into the switch control register.
Accessing the MAX7357/MAX7358 in
Enhanced Mode
In enhanced mode, all 7 registers are enabled. These
registers are autoincremented starting with the switch
control register during each I2C transaction. When a
new transaction begins, the switch control register is
the first register accessed.
A write to the MAX7356 starts with the master transmitting
the slave address with the R/W bit set low. The MAX7356
acknowledges the slave address. The master can then
issue a STOP condition after the acknowledge (Figure 14),
but typically the master proceeds to transmit one or more
bytes of data. The MAX7356 acknowledges these subse-
quent bytes of data and updates the switch control regis-
ter when the master issues a STOP condition (Figure 14).
6/MAX7358
A single-byte write to the MAX7357 or MAX7358 sets
the switch control register.
A 2-byte write to the MAX7357 or MAX7358 sets the
switch control and configuration registers.
A 3-byte write to the MAX7357 or MAX7358 sets the
switch control, configuration, and flush-out sequence
registers.
Writing to the MAX7357/MAX7358 in
Enhanced Mode
The MAX7357 and MAX7358 registers can be written
by an I2C write command starting with the device
address for the MAX7357 or MAX7358 and followed by
data bytes. The first data byte is stored into the switch
control register and subsequent data bytes are stored
into the subsequent registers.
A multibyte write to the MAX7357 or MAX7358 with
more than three bytes sets the first three registers, then
resets the pointer back to the switch control register
(0x00) since the remaining registers are read only.
Subsequent bytes of data, after 3 bytes, begin overwrit-
ing the first set of data starting with 0x00, 0x01, 0x02,
then looping back to 0x00 again, and continuing until a
STOP condition is received.
A write to the MAX7357 or MAX7358 starts with the
master transmitting the slave address with the R/W bit
set low. The MAX7357 or MAX7358 acknowledge the
slave address. The master can then issue a STOP con-
dition after the acknowledge (Figure 15), but typically
A single-byte read from the MAX7357 or MAX7358
returns the contents of the switch control register.
18 ______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
the master proceeds to transmit one or more bytes of
data. The MAX7357 or MAX7358 acknowledge these
subsequent bytes of data and update corresponding
registers with each new byte until the master issues a
STOP condition (Figure 15).
Reading from the MAX7356
A read from the MAX7356 starts with the master trans-
mitting the slave address with the R/W bit set high. The
MAX7356 acknowledges the slave address. The master
can read 1 byte from the switch control register and
then issue a STOP condition (Figure 17). If the master
reads more than one byte, the master upon reception
acknowledges each byte. All bytes return the contents
of the switch control register.
Writing to the MAX7357/MAX7358
in Basic Mode
The MAX7357 and MAX7358 switch control register can
be written by an I2C write command starting with the
device address for the MAX7357 or MAX7358 and fol-
lowed by data bytes. The last data byte is stored in the
switch control register.
Reading from the MAX7357/MAX7358
in Enhanced Mode
A read from the MAX7357 or MAX7358 starts with the
master transmitting the slave address with the R/W bit
set high. The device acknowledges the slave address.
The master can read 1 byte from the device and then
issue a STOP condition (Figure 18). In this case, the
device transmits the data byte from the switch control
register. Typically, the master reads 1 or 2 bytes with
each byte being acknowledged by the master upon
reception. The first data byte comes from the switch
control register and subsequent data bytes come from
the subsequent registers in order.
A write to the MAX7357 or MAX7358 starts with the
master transmitting the slave address with the R/W bit
set low. The device acknowledges the slave address.
The master can then issue a STOP condition after the
acknowledge (Figure 16), but typically the master pro-
ceeds to transmit one or more bytes of data. The
MAX7357 or MAX7358 acknowledge these subsequent
bytes of data and update the switch control register
when the master issues a STOP condition (Figure 16).
ACKNOWLEDGE FROM THE
MAX7356
ACKNOWLEDGE FROM THE
ACKNOWLEDGE FROM THE
MAX7356
MAX7356
S
ADDRESS OF MUX/SWT PART
START
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
R/W
STOP
DATA BYTE TO THE SWITCH
CONTROL REGISTER
DATA BYTE TO THE SWITCH
CONTROL REGISTER
Figure 14. Writing to the MAX7356
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7358
ACKNOWLEDGE FROM THE
MAX7358
S
ADDRESS OF MUX/SWT PART
START
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
R/W
STOP
DATA BYTE TO THE SWITCH
CONTROL REGISTER
DATA BYTE TO THE CONFIGURATION
REGISTERS
DATA BYTE TO THE FLUSH-OUT
SEQUENCE
Figure 15. Writing to the MAX7357 or MAX7358 in Enhanced Mode
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
S
ADDRESS OF MUX/SWT PART
START
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
R/W
STOP
DATA BYTE TO THE SWITCH
CONTROL REGISTER
DATA BYTE TO THE SWITCH
CONTROL REGISTER
Figure 16. Writing to the MAX7357 or MAX7358 in Basic Mode
______________________________________________________________________________________ 19
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
S
ADDRESS OF MUX/SWT PART
START
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
R/W
STOP
DATA BYTE TO THE SWITCH
CONTROL REGISTER
DATA BYTE TO THE SWITCH
CONTROL REGISTER
Figure 17. Reading the MAX7356
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE
FROM A HOST
ACKNOWLEDGE FROM A
HOST
S
ADDRESS OF MUX/SWT PART
START
1
A
D7 D6
D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
R/W
STOP
DATA BYTE FROM THE SWITCH DATA BYTE FROM
DATA BYTE FROM THE
CONTROL REGISTER
REGISTERS
STUCK HIGH FAULT REGISTER
0X01 TO 0X06
Figure 18. Reading the MAX7357 or MAX7358 in Enhanced Mode
ACKNOWLEDGE FROM THE
MAX7357 OR MAX7358
ACKNOWLEDGE FROM A
ACKNOWLEDGE FROM A
HOST
HOST
S
ADDRESS OF MUX/SWT PART
START
1
A
D7 D6 D5 D4 D3 D2 D1 D0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
R/W
STOP
DATA BYTE FROM THE SWITCH
CONTROL REGISTER
DATA BYTE FROM THE SWITCH
CONTROL REGISTER
Figure 19. Reading the MAX7357 or MAX7358 in Basic Mode
6/MAX7358
Reading from the MAX7357/MAX7358
in Basic Mode
Applications Information
Voltage Level Translation
A read from the MAX7357 or MAX7358 in basic mode
starts with the master transmitting the slave address
with the R/W bit set high. The device acknowledges the
slave address. The master can read 1 byte from the
switch control register and then issue a STOP condition
(Figure 19). If the master reads more than one byte, the
master upon reception acknowledges each byte. All
bytes return the contents of the switch control register.
The pass gates of the MAX7356/MAX7357/MAX7358
are designed so V
can be used to limit the voltage
DD
levels transferred from one bus to another. The power-
supply voltage of the part should be selected to be no
larger than one VGS
(0.7V, typ) above the lowest
ON
bus voltage in the system. This ensures that the analog
switches do not allow current to flow from higher volt-
age buses to lower voltage buses.
Chip Information
PROCESS: CMOS
20 ______________________________________________________________________________________
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
6/MAX7358
Typical Operating Circuit
V
V
V
DD
CC
DD
V
DD
SD0
SC0
SDA
SCL
RST
SDA
SCL
V
DD
RST(RST/INT)
INT
MAX7356
MAX7357
MAX7358
MASTER
SD1
SC1
V
DD
A0
A1
A2
SD7
SC7
GND
( ) ONLY FOR THE MAX7357 AND MAX7358
Pin Configurations
+
A0
1
2
3
4
5
6
7
8
9
24 V
DD
TOP VIEW
A1
23 SDA
24
23
22
21
20
19
RST (RST/INT)
SD0
22 SCL
21 A2
MAX7356
MAX7357
MAX7358
+
18
17
16
15
14
13
SD0
SC0
SD1
SC1
SD2
1
2
3
4
5
6
A2
SC0
20 SC7
19 SD7
18 SC6
17 SD6
16 SC5
15 SD5
14 SC4
13 SD4
SC7
SD7
SD1
MAX7356
MAX7357
MAX7358
SC1
SC6
SD6
SC5
SD2
SC2
*EP
SC2
SD3 10
SC3 11
GND 12
7
8
9
10
11
12
TQFN-EP
*CONNECT EXPOSED PAD TO GND.
TSSOP
( ) ONLY FOR THE MAX7357 AND MAX7358
( ) ONLY FOR THE MAX7357 AND MAX7358
______________________________________________________________________________________ 21
2
1-to-8 I C Bus Switches/Multiplexers with Bus
Lock-Up Detection, Isolation, and Notification
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
24 TSSOP
PACKAGE CODE
U24+1
DOCUMENT NO.
21-0066
24 TQFN-EP
T2444+4
21-0139
6/MAX7358
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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