MAX7470 [MAXIM]
HDTV Continuously Variable Anti-Aliasing Filters; HDTV连续可变的抗混叠滤波器
| 型号： | MAX7470 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | HDTV Continuously Variable Anti-Aliasing Filters |
| 文件： | 总17页 (文件大小：803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0548; Rev 0; 5/06
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
General Description
Features
ꢀ Continuously Variable Anti-Aliasing Filter
The MAX7469/MAX7470 triple-channel, anti-aliasing fil-
ters and buffers are ideal for high-definition (HD) and
standard-definition (SD) television (TV) applications.
Compatible with 1080i, 720p, 720i, 480p, and 480i
scanning system standards and computer format sig-
nals, the MAX7469/MAX7470 support component video
5MHz to 34MHz in 256 Steps
ꢀ Supports All Standard Video and Computer Input
Formats
480i, 480p, 720i, 720p, 1080i
QVGA, VGA, SVGA, XGA, SXGA, UXGA
Y P P , G BR, RGBHV, Y/C, CVBS
(Y P P , G BR, and RGBHV), as well as composite
(CVBS) and S-video (Y/C).
b
r
s
b
r
s
ꢀ Accepts Any Input Sync Format
Sync on Y, Sync on G, External Sync (Positive
or Negative)
The MAX7469/MAX7470 limit the input bandwidth for
anti-aliasing and out-of-band noise reduction prior to
digital conversion by an ADC or video decoder. The
MAX7469/MAX7470 frequency response can be contin-
uously varied in 256 linear steps through an I2C* inter-
face from below SD resolution to beyond HD resolution.
Sync on All Channels
ꢀ Buffered Outputs Drive Standard 150Ω Video
Load
The output buffers of the MAX7469/MAX7470 drive a
0dB (MAX7469)
+6dB (MAX7470)
2V
video signal into a standard 150Ω load. The inputs
P-P
are AC-coupled, and the outputs can be either DC- or
AC-coupled. The MAX7469 has a gain of 0dB, and the
MAX7470 has a gain of +6dB. Both devices are available
in a 20-pin TQFN package and are fully specified over
the 0°C to +85°C upper-commercial temperature range.
ꢀ DC- or AC-Coupled Outputs
ꢀ Single +5V Analog and +3.3V Digital Supplies
ꢀ 5mW Power-Down Mode
ꢀ 20-Pin TQFN Lead-Free Package
Applications
HDTV (LCD, PDP, DLP, CRT)
Set-Top Boxes
Personal Video Recorders
Home Theaters
2
*Purchase of I C components from Maxim Integrated Products,
Inc., or one of its sublicensed Associate Companies, conveys a
license under the Philips I C Patent Rights to use these compo-
nents in an I C system, provided that the system conforms to the
I C Standard Specification defined by Philips.
Pin Configuration
2
2
2
TOP VIEW
15
14
13
12
11
Ordering Information
OUT1
10
9
IN1 16
GND 17
IN2 18
BUFFER
PKG
PART
PIN-PACKAGE
GAIN (dB)
CODE
AV
DD
MAX7469UTP+
20 TQFN-EP*
20 TQFN-EP*
0
T2055-4
T2055-4
8
OUT2
MAX7469
MAX7470
MAX7470UTP+**
+6
GND
IN3
7
AV
DD
19
20
Note: All devices are specified over the 0°C to +85°C operating
temperature range.
+ Indicates lead-free packaging.
*EP
6
OUT3
+
*EP = Exposed pad.
**Future product—contact factory for availability.
1
2
3
4
5
TQFN (5mm x 5mm)
*EXPOSED PAD.
SEE PIN DESCRIPTION FOR CONNECTION.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
HDTV Continuously Variable
Anti-Aliasing Filters
ABSOLUTE MAXIMUM RATINGS
AV
to GND............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DV
to DGND.........................................................-0.3V to +4V
20-Pin TQFN (derate 33.3mW/°C above +70°C) ...2666.7mW
Maximum Current into IN_, A_, GND,
DD
IN_, EXTSYNC to GND .................................................................
..................................-0.3V to the lower of (AV + 3V) and +6V
OUT_ to GND ...............................................................................
SCL, SDA, and EXTSYNC............................................ 50mA
Operating Temperature Range...............................0°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
..................................-0.3V to the lower of (AV + 3V) and +6V
DD
A_ to GND ....................................................................................
..................................-0.3V to the lower of (AV + 3V) and +6V
DD
SCL, SDA to DGND..................................................-0.3V to +6V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= +5V 5ꢀ, DV
= 2.7V to 3.6V, R
= 150Ω to GND, C = 0.1µF, T = 0°C to +85°C, unless otherwise noted. Typical
DD
DD
LOAD
IN
A
values are at AV
= 5V, DV
= 3.3V, T = +25°C.)
DD A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
69/MAX470
HD: f = 100kHz to 30MHz, relative to
100kHz (Note 1)
-3
-0.6
+1
Filter Passband Response
A
dB
PB
SB
SD: f = 100kHz to 5.75MHz, relative to
100kHz (Note 2)
0.1
1.0
HD: f = 74MHz (Note 1)
SD: f = 27MHz (Note 2)
45
52
57
63
Filter Stopband Attenuation
Group Delay Deviation
A
dB
ns
HD: 100kHz to 30MHz, relative to 100kHz
(Note 1)
20
15
5
Δt
G
SD: 100kHz to 5.75MHz, relative to 100kHz
(Note 2)
HD: channel to channel, 100kHz to 2MHz,
(Note 1)
Group Delay Matching
t
ns
G(MATCH)
SD: channel to channel, 100kHz to 500kHz,
(Note 2)
1.5
100
-3dB, bypass mode, independent of filter
setting
Bypass Frequency Response
MHz
SD Differential Gain
SD Differential Phase
dG
Five-step modulated staircase (Note 2)
Five-step modulated staircase (Note 2)
0.25
0.25
ꢀ
dφ
Degrees
Output signal (2V ) to RMS noise (100kHz
P-P
to 30MHz), f = 30MHz
Signal-to-Noise Ratio
SD Line-Time Distortion
SD Field-Time Distortion
SNR
69
dB
ꢀ
Deviations in a line with an 18µs, 100 IRE
bar; 1 line = 63.5µs (Note 2)
H
0.3
0.3
DIST
Deviations in 130 lines with 18µs, 100 IRE
bars (Note 2)
V
ꢀ
DIST
2
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
ELECTRICAL CHARACTERISTICS (continued)
(AV
= +5V 5ꢀ, DV
= 2.7V to 3.6V, R
= 150Ω to GND, C = 0.1µF, T = 0°C to +85°C, unless otherwise noted. Typical
DD
DD
LOAD
IN
A
values are at AV
= 5V, DV
= 3.3V, T = +25°C.)
DD A
DD
PARAMETER
Clamp Settling Time
SYMBOL
CONDITIONS
MIN
TYP
350
650
MAX
UNITS
Positive
To 1ꢀ with 100 IRE step
H
(Note 4)
Negative
Minimum Functional Input Sync
Amplitude
125
mV
MAX7469
MAX7470
100kHz
-0.5
5.5
0
6
+0.5
6.5
Low-Frequency Gain (Note 1)
Low-Frequency Gain Matching
dB
dB
0.05
Maximum Output Voltage
Amplitude
DC to 30MHz
2.4
V
V
P-P
P-P
MAX7469
MAX7470
2.4
1.2
62
Maximum Input Voltage
Amplitude
Channel-to-Channel Isolation
Output Clamping Level Variation
Power-Supply Rejection Ratio
DIGITAL INPUTS (EXTSYNC, A1, A0)
Input Logic-High Voltage
dB
mV
dB
(Notes 1, 4)
DC
100
PSRR
50
V
2.0
V
V
IH
Input Logic-Low Voltage
V
0.8
10
IL
Input Leakage Current
I
V
= 0 to DV
1
6
µA
pF
IN
IN
DD
Input Capacitance
C
IN
IH
DIGITAL INPUTS (SDA, SCL)
0.7 x
Input Logic-High Voltage
Input Logic-Low Voltage
V
V
V
V
DV
DD
0.3 x
V
IL
DV
DD
0.05 x
DV
Input Hysteresis
V
HYST
DD
Input Leakage Current
I
V
= 0 to DV
0.1
6
10
µA
pF
IN
IN
DD
Input Capacitance
C
IN
DIGITAL OUTPUT (SDA)
Output Logic-Low Voltage
Tri-State Leakage Current
Tri-State Output Capacitance
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
V
I
= 3mA
0.4
10
V
OL
SINK
I
V
= 0 to DV
IN
0.1
6
µA
pF
L
DD
C
OUT
AV
DV
4.75
2.7
5
3.3
180
1
5.25
3.6
V
V
DD
DD
Normal operation, no load
Power-down mode, no load
200
1.5
Analog Supply Current
Digital Supply Current
I
mA
µA
AVDD
I
f
= 400kHz
25
DVDD
SCL
_______________________________________________________________________________________
3
HDTV Continuously Variable
Anti-Aliasing Filters
TIMING CHARACTERISTICS
(AV
= +5V 5ꢀ, DV
= 2.7V to 3.6V, R
= 150Ω to GND, C = 0.1µF, T = 0°C to +85°C, unless otherwise noted. Typical
DD
DD
LOAD
IN
A
values are at AV
= 5V, DV
= 3.3V, T = +25°C.)
DD A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between STOP (P)
and START (S) Condition
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START (Sr)
Condition
After this period, the first clock pulse is
generated
t
t
HD;STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START (Sr) Condition
0.6
µs
SU;STA
Data Hold Time
Data Setup Time
t
(Note 5)
0.0
0.9
µs
ns
HD;DAT
t
100
SU;DAT
69/MAX470
Rise Time of Both SDA and SCL
Signals, Receiving
t
0
300
300
250
ns
ns
ns
µs
pF
ns
r
Fall Time of Both SDA and SCL
Signals, Receiving
t
t
0
f
f
Fall Time of SDA Signal,
Transmitting
20 +
0.1C
(Note 6)
(Note 7)
b
Setup Time for STOP (P)
Condition
t
0.6
SU;STO
Capacitive Load for Each Bus
Line
C
400
50
b
Pulse Width of Spikes that Are
Suppressed by the Input Filter
t
0
SP
Note 1: The filter passband edge is set to code 255.
Note 2: The filter passband edge is set to code 40.
Note 3: 1H is the total line period, depending on the video standard. For NTSC, this is 63.5µs; for HDTV, the line period is 29.64µs.
Note 4: The clamp level is at the sync tip for signals with sync pulses, and at the blanking level otherwise.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge
IL
the undefined region of SCL’s falling edge.
Note 6: C = total capacitance of one bus line in pF. t and t measured between 0.3V
and 0.7V
.
b
R
F
DD
DD
Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
SDA
SCL
t
SU;DAT
t
f
t
t
t
f
t
t
t
t
SP
LOW
r
HD;STA
SP
r
t
t
SU;STA
SU;STO
t
HD;STA
t
t
HIGH
HD;DAT
Sr
S
P
S
Figure 1. 2-Wire, Serial-Interface Timing Diagram
Typical Operating Characteristics
(AV
= +5V, DV = 3.3V, R
= 150Ω to GND, C
= 0 to 20pF to GND, C = 0.1µF, T = +25°C, unless otherwise noted.)
DD
DD
LOAD
LOAD
IN
A
FREQUENCY RESPONSE (MAX7470)
FREQUENCY RESPONSE (MAX7469)
PASSBAND FLATNESS (MAX7469)
10
0
10
0
1.0
0.5
0
-10
-10
-20
CODE 40
CODE 40
CODE 220
CODE 255
-20
-30
-40
-50
-60
-70
-80
CODE 220
-0.5
-1.0
CODE 40
-30
CODE 255
CODE 90
CODE 90
CODE 220
CODE 255
CODE 90
-40
-50
-60
-70
-1.5
-2.0
-2.5
-3.0
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2T RESPONSE (1 IRE = 7.14mV)
GROUP DELAY
PASSBAND FLATNESS (MAX7470)
MAX7469 toc06
90
80
70
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
300mV/div
300mV/div
SD
CODE 40
CODE 90
60
50
40
30
20
HD
CODE 220
CODE 255
10
0
0.1
1
10
100
200ns/div
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
5
HDTV Continuously Variable
Anti-Aliasing Filters
Typical Operating Characteristics (continued)
(AV
= +5V, DV = 3.3V, R
= 150Ω to GND, C
= 0 to 20pF to GND, C = 0.1µF, T = +25°C, unless otherwise noted.)
LOAD IN A
DD
DD
LOAD
MODULATED 12.5T RESPONSE
(1 IRE = 7.14mV)
-3dB FREQUENCY
vs. CONTROL CODE
DIFFERENTIAL GAIN
MAX7469 toc07
36
0.2
0.1
30
24
18
12
6
300mV/div
0
-0.1
-0.2
1
2
3
4
5
6
7
DIFFERENTIAL PHASE
0.2
300mV/div
0.1
0
-0.1
69/MAX470
-0.2
1
0
0
51
102
153
204
255
400ns/div
2
3
4
5
6
7
CODE
BYPASS-MODE FREQUENCY RESPONSE
BYPASS-MODE GROUP DELAY
10
5
20
16
12
8
MAX7470
MAX7469
0
-5
-10
-15
-20
-25
-30
-35
-40
4
0
0.1
1
10
100
1000
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
6
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
Pin Description
PIN
1
NAME
FUNCTION
DGND
Digital Ground. See the Power-Supply Bypassing and Layout Considerations section.
2
EXTSYNC External Sync Input. EXTSYNC has an internal 3MΩ resistor to ground. Connect to ground if not used.
2
3
SCL
SDA
I C-Compatible Serial-Clock Input
2
4
I C-Compatible Serial-Data Input/Output
Digital Power Supply. Bypass to DGND with a 0.1µF capacitor. See the Power-Supply Bypassing and
Layout Considerations section.
5
6
DV
DD
OUT3
AV
Video Output 3. OUT3 can be either DC- or AC-coupled.
Analog Power Supply. Bypass to GND with a 0.1µF capacitor. See the Power-Supply Bypassing and
Layout Considerations section.
7, 9, 11
DD
8
OUT2
OUT1
A0
Video Output 2. OUT2 can be either DC- or AC-coupled.
Video Output 1. OUT1 can be either DC- or AC-coupled.
10
12
13
2
I C Device Address Bit 0
2
A1
I C Device Address Bit 1
Ground. Connect all GND pins to the ground plane. See the Power-Supply Bypassing and Layout
Considerations section.
14, 15, 17, 19
GND
16
18
20
IN1
IN2
IN3
Video Input 1. AC-couple IN1 with a series 0.1µF capacitor.
Video Input 2. AC-couple IN2 with a series 0.1µF capacitor.
Video Input 3. AC-couple IN3 with a series 0.1µF capacitor.
Exposed Pad. Internally connected to GND. Do not route any PC board traces under package. Connect
EP to the ground plane. See the Power-Supply Bypassing and Layout Considerations section.
—
EP
An I2C interface allows a microcontroller (µC) to config-
Detailed Description
ure the MAX7469/MAX7470s’ performance and func-
tionality, including the clamp voltage, the filter corner
frequency, the sync source (internal/external), filter
bypassing, etc.
The MAX7469/MAX7470 are complete video anti-alias-
ing solutions, ideal for fixed-pixel HDTV display tech-
nologies, such as plasma and LCD, which digitize the
input video signal and then scale the resolution to
match the native pixel format of the display. With a soft-
ware-selectable corner frequency ranging from 5MHz
to 34MHz, the MAX7469/MAX7470 support both SD
and HD video signals, including 1080i, 720p, 720i,
480p, and 480i. Higher bandwidth computer resolution
signals are also supported.
The Typical Operating Circuit shows the MAX7469/
MAX7470 block diagram and typical external connections.
Sync Detector and Clamp Settings
The MAX7469/MAX7470 use a video clamp circuit to
establish a DC offset for the incoming video signal after
the AC-coupling capacitor. This video clamp sets the DC
bias level of the circuit at the optimum operating point.
Integrated lowpass filters limit the analog video input
bandwidth for anti-aliasing and out-of-band noise
reduction prior to sampling by an ADC or video
decoder. By allowing the corner frequency to be adjust-
ed from below SD resolution to beyond HD resolutions
in 256 linear steps, the filter’s corner frequency can be
optimized dynamically for a specific input video signal
and the sampling frequency of the ADC or video
decoder. For applications requiring a passband greater
than the maximum frequency setting, a filter bypass
mode is also provided.
The MAX7469/MAX7470 support both internal and
external sync detection. Selection of internal vs. external
detection is achieved by programming the command
byte (see Table 3). After extracting the sync information
from channel 1 (or an external sync: SYNCA, SYNCB, or
SYNC), the MAX7469/MAX7470 clamp the video signal
during the sync tip portion of the video. Select one of
two possible clamp levels according to the input signal
format. Use the low level when the input signal contains
sync information, such as a Y (luma) or CVBS signal.
_______________________________________________________________________________________
7
HDTV Continuously Variable
Anti-Aliasing Filters
data word that corresponds to the desired frequency. See
Table 1. Clamp Levels
the Frequency Register section for more details.
CLAMP LEVEL
INPUT SIGNAL
The frequency set by the MAX7469/MAX7470 is the
-3dB point. Set the frequency according to the desired
flat passband response.
FORMAT
CHANNEL 1 CHANNEL 2 CHANNEL 3
Y P P
Low
Low
Low
High
High
Low
High
High
High
b
r
G BR
S
Optimizing the Frequency Response
Select the frequency response according to the resolution
of the video-signal format. High-definition signals require
higher bandwidth, while standard-definition signals
require less bandwidth. The actual bandwidth contained
in the video signal is a function of the visual resolution of
the signal. This bandwidth is typically less than what is
indicated by the format resolution (1080i, 720p, etc.). For
more information, see Maxim Application Note 750:
Bandwidth Versus Video Resolution, which is available on
www.maxim-ic.com.
CVBS Y C
Y P P (sync on
b
r
Low
Low
Low
all signals)
R G B H V
High
High
High
Use the high level for bipolar signals, such as C (chro-
ma) or P /P . See Table 1 for more details.
b
r
Component/Composite Selection
The MAX7469/MAX7470 accept component or com-
posite inputs. When configured for composite video
inputs, the color-burst filter is enabled; if configured for
component video inputs, the color-burst filter is dis-
abled. This filter is separate from the main filter and not
in the direct signal path so that it has no effect on the
overall frequency response. With normal video signals
and levels, the use of this color-burst filter has a negligi-
ble effect on the sync detection. It has a more signifi-
cant effect under conditions of low-signal amplitude
coupled with higher relative amplitude color burst.
The frequency response can be optimized to improve
the overall performance. It is important, at a minimum, to
meet the Nyquist criterion. Beyond this, the frequency
response can be further optimized. In oversampled sys-
tems, the sample rate is significantly more than the
desired passband response. The extra frequency span
between the passband and the sample rate contains
noise and other undesirable interferers that can be elimi-
nated by setting the corner frequency of the filter to just
pass the desired bandwidth. This results in a higher sig-
nal-to-noise ratio of the overall system.
69/MAX470
External Sync Detection (EXTSYNC)
When filtering a video signal without embedded sync
information, such as computer formats (RGBHV) with
separate sync signals, use the external sync mode (see
Table 3) and apply the horizontal sync source to the
EXTSYNC pin. The sync detector determines when the
clamp circuit is turned on.
Filter Bypass
The MAX7469/MAX7470 offer selectable filter bypass-
ing that allows the input video signals to bypass the
internal filters and reach the output buffers unfiltered.
Write the appropriate command byte to enable (0Eh) or
disable (0Fh) filter-bypass mode as shown Table 3.
The MAX7469/MAX7470 are able to detect positive or
negative polarity external syncs with TTL logic levels.
Use the I2C interface to program the polarity of the
external sync signal.
Output Buffer
Each output buffer can drive a 2V
signal into a 150Ω
P-P
video load. The MAX7469/MAX7470 can drive a DC- or
AC-coupled load. Output AC-coupling capacitors can
be eliminated when driving a cable, thereby eliminating
the normal adverse effects caused by these large
capacitors, such as line, and field-time distortion, also
known as droop. The output DC level is controlled to
limit the DC voltage on the cable so that the blanking
level of the video signal is always less than 1V, meeting
digital TV specification. See the Output Considerations
section for more information.
Filter
The internal video filter delivers an optimized response
with a steep transition band to achieve a wide pass-
band along with excellent stopband rejection. In addi-
tion, the filter is optimized to provide an excellent time
domain response with low overshoot.
Setting the Filter Frequency
Use the I2C interface to vary the frequency response
(-3dB cutoff frequency) of the filter in the MAX7469/
MAX7470 from less than the SD passband to beyond the
HD passband in 256 linear steps. Write command byte
12h to access the frequency register, followed by an 8-bit
Gain Options
The MAX7469 features an overall gain of 0dB, while the
MAX7470 features an overall gain of +6dB. Use the
MAX7470 when driving a back-matched cable and the
8
________________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
MAX7469 when driving an ADC or video decoder with an
Power-On Reset (POR)
The MAX7469/MAX7470 include a POR circuit that
resets the internal registers and I2C interface to their
default conditions (see Tables 4, 5, and 6).
input range the same as the input to the MAX7469. For
added flexibility, the MAX7469 accepts input signals with
twice the standard video-signal range, which can be
used for driving an ADC or video decoder with an input
signal range that accepts a larger signal swing. The
MAX7470 can also be used to drive an ADC or video
decoder when a gain of two is desired.
Serial Interface
The MAX7469/MAX7470 feature an I2C-compatible, 2-wire
serial interface consisting of a bidirectional serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facilitate
bidirectional communication between the MAX7469/
MAX7470 and the master at rates up to 400kHz.
Output Clamp Level
The MAX7469/MAX7470 output can be DC- or AC-
coupled. The nominal output clamp level in the
DC-coupled case depends on the clamp voltage set-
ting and can be determined according to Table 2.
The MAX7469/MAX7470 have a command interpreter
that is accessed by writing a valid command byte.
Once a command byte is written to the MAX7469/
MAX7470, the command interpreter updates the con-
trol/status register accordingly. See the Control/Status
Register section for more information. The command
interpreter also controls access to the frequency regis-
ter through a command byte (see the Command Byte
(Write Cycle) section).
Table 2. Output Clamp Level
CLAMP SETTING
OUTPUT CLAMP LEVEL (V)
1.0 (typ)
Low
High
1.6 (typ)
The MAX7469/MAX7470 are transmit/receive slave-only
devices, relying upon a master to generate a clock sig-
nal. The master (typically a µC) initiates data transfer on
the bus and generates SCL.
As shown in the Sync Detector and Clamp Settings
section, the low clamp level is used for signals with
sync information and determines the voltage level of the
sync tip, while the high clamp level is used for signals
without sync information and sets the blanking level.
A master device communicates to the MAX7469/
MAX7470 by transmitting the proper address (see the
Slave Address section) followed by a command and/or
data words. Each transmit sequence is framed with a
START (S) or REPEATED START (Sr) condition and a
STOP (P) condition.
The absolute voltage level of the output signal is rela-
tive to the output clamp level. A video signal containing
sync information (i.e., CVBS or Y) is unipolar above the
clamp level and conversely, a video signal without sync
(i.e., P P or C) is bipolar around the clamp level.
b
r
The SDA driver is an open-drain output, requiring a
pullup resistor (2.4kΩ or greater) to generate a logic-
high voltage. Optional resistors (24Ω) in series with
SDA and SCL protect the device inputs from high-volt-
age spikes on the bus lines. Series resistors also mini-
mize crosstalk and undershoot of the bus signals.
Power-Down Mode
The MAX7469/MAX7470 include a power-down mode
that reduces the supply current from 180mA (typ) to 1mA
(typ) by powering down the analog circuitry. The I2C
interface remains active, allowing the device to return to
full-power operation. The clamp settling time (see the
Electrical Characteristics section) limits the wake-up time
of the MAX7469/MAX7470. After exiting the power-down
mode, the MAX7469/MAX7470 resume normal operation
using the settings stored prior to power-down. The
power-down and wake-up modes are controlled through
the command byte (see Table 3). A software reset sets
the control/status register to its default conditions, but
the frequency register is not affected.
Bit Transfer
Each SCL rising edge transfers 1 data bit. Nine clock
cycles are required to transfer the data into or out of the
MAX7469/MAX7470. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes in
SDA while SCL is high are read as control signals (see the
START and STOP Conditions section). When the serial
interface is inactive, SDA and SCL idle high.
_______________________________________________________________________________________
9
HDTV Continuously Variable
Anti-Aliasing Filters
START and STOP Conditions
A master device initiates communication by issuing a
START condition, a high-to-low transition on SDA with SCL
high (Figure 2). The master terminates transmission by a
STOP condition (see the Acknowledge Bit (ACK) and Not-
Acknowledge Bit (NACK) section). A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure 2).
The STOP condition frees the bus. If a repeated START
condition is generated instead of a STOP condition, the
bus remains active. When a STOP condition or incorrect
condition occurs in the same high pulse as a START
condition (Figure 3). This condition is not a legal I2C for-
mat; at least one clock pulse must separate any START
and STOP conditions. The MAX7469/MAX7470 discard
any data received during a data transfer aborted by an
early STOP condition.
Repeated START (S ) Conditions
r
An Sr condition is used to indicate a change in direc-
tion of data flow (see the Read Cycle section). Sr can
also be used when the bus master is writing to several
I2C devices and does not want to relinquish control of
the bus. The MAX7469/MAX7470 serial interface sup-
ports continuous write operations with (or without) an Sr
condition separating them.
address
is
detected,
the
MAX7469/
MAX7470 then ignore all communication on the I2C bus
until the next START or REPEATED START condition,
minimizing digital noise and feedthrough.
Early STOP Conditions
The MAX7469/MAX7470 recognize a STOP condition at
any point during transmission except when a STOP
69/MAX470
S
Sr
P
SCL
SDA
Figure 2. START/STOP Conditions
LEGAL STOP CONDITION
ILLEGAL STOP CONDITION
SCL
SCL
SDA
SDA
ILLEGAL STOP
START
STOP
START
Figure 3. Early STOP Conditions
10 _______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
Acknowledge Bit (ACK) and Not-Acknowledge Bit
Slave Address
A bus master initiates communication with a slave device
by issuing a START condition, followed by the 7-bit slave
address (Figure 5). When idle, the MAX7469/MAX7470
wait for a START condition, followed by their slave
address. The serial interface compares each address bit
by bit, allowing the interface to power down and discon-
nect from SCL immediately if an incorrect address is
detected. After recognizing a START condition followed
by the correct address, the MAX7469/MAX7470 are
ready to accept or send data. The least significant bit
(LSB) of the address byte (R/W) determines whether the
master is writing to or reading from the
MAX7469/MAX7470 (R/W = 0 selects a write condition,
R/W = 1 selects a read condition). After receiving the
proper address, the MAX7469/MAX7470 (slave) issue an
ACK by pulling SDA low for one clock cycle.
(NACK)
Successful data transfers are acknowledged with an
acknowledge bit (ACK) or a not-acknowledge bit
(NACK). Both the master and the MAX7469/MAX7470
(slave) generate acknowledge bits. To generate an
acknowledge, the receiving device must pull SDA low
before the rising edge of the acknowledge-related clock
pulse (ninth pulse) and keep it low during the high period
of the clock pulse (Figure 4). To generate a NACK, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and leaves it high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuccess-
ful data transfer happens if a receiving device is busy or
if a system fault has occurred. In the event of an unsuc-
cessful data transfer, the master should reattempt com-
munication at a later time.
The MAX7469/MAX7470 slave address consists of 5
fixed bits, A6–A2 (set to 10010), followed by 2 pin-pro-
grammable bits, A1 and A0. The most significant
address bit (A6) is transmitted first, followed by the
remaining bits. Addresses A1 and A0 can also be driven
dynamically if required, but the values must be stable
when they are expected in the address sequence.
The MAX7469/MAX7470 generate an acknowledge bit
when receiving an address or data by pulling SDA low
during the ninth clock pulse. When transmitting data
during a read, the MAX7469/MAX7470 do not drive
SDA during the ninth clock pulse (i.e., the external
pullups define the bus as a logic-high) so that the
receiver of the data can pull SDA low to acknowledge
receipt of data.
S
NOT ACKNOWLEDGE
ACKNOWLEDGE
SDA
SCL
9
8
1
Figure 4. Acknowledge and Not-Acknowledge Bits
.
R/W
1
0
0
1
0
A1
A0
ACK
SDA
SCL
MSB
LSB
Figure 5. Slave-Address Byte Definition
______________________________________________________________________________________ 11
HDTV Continuously Variable
Anti-Aliasing Filters
Command Byte (Write Cycle)
A write cycle begins with the bus master issuing a
START condition followed by 7 address bits (Figure 5)
and 1 write bit (R/W = 0). After successfully receiving its
address, the MAX7469/MAX7470 (slave) issue an ACK.
The slave recognizes the next byte after a successfully
received address as the command byte (Table 3).
Use the command byte to configure the MAX7469/
MAX7470. While most of the commands listed in Table
3 modify the functionality of the MAX7469/MAX7470,
some commands prepare the device for further data
transfers (see the Control/Status Register and
Frequency Register sections). If the write cycle is pre-
maturely aborted, the register is not updated, and the
Table 3. Command Byte Definition
COMMAND BYTE:
INDIVIDUAL BIT DEFINITIONS
DESCRIPTION
C7 C6 C5 C4 C3 C2 C1 C0
0
0
0
0
0
0
0
0
Enters power-down mode.
Wake-up; resumes normal operation using the frequency/status previously stored
(unless power has been cycled).
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sets IN1 clamp voltage level to low.
Sets IN1 clamp voltage level to high.
Sets IN2 clamp voltage level to low.
Sets IN2 clamp voltage level to high.
Sets IN3 clamp voltage level to low.
Sets IN3 clamp voltage level to high.
Selects component input, color-burst filter disabled.
Selects composite input, color-burst filter enabled.
Selects internal sync.
69/MAX470
Selects external sync.
Selects positive polarity external sync.
Selects negative polarity external sync.
Enables filters.
Disables filters, enters bypass mode.
Resets the control/status register to the default values as described in the Control/
Status Register section. This command does not affect the frequency register.
0
0
0
1
0
0
0
0
Requests a control/status register read. The interface expects an Sr condition to
follow with address and read/write set to read so data can be driven onto the bus.
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
1
Loads the frequency register with the data byte following the command byte.
Requests a frequency register read. The interface expects an Sr condition to follow
with address and read/write set to read so data can be driven onto the bus.
12 _______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
write sequence must be repeated. Figures 6 and 7
show examples of write sequences.
follow the command byte. After sending an Sr, the mas-
ter sends the MAX7469/MAX7470 slave address byte
followed by a R/W bit (set to 1 to indicate a read). The
slave device (MAX7469/MAX7470) generates an ACK
for the second address word and immediately after the
ACK clock pulse, the direction of data flow reverses.
The slave (MAX7469/MAX7470) then transmits 1 byte of
data containing the value of the register that was
Read Cycle
In read mode (R/W = 1), the MAX7469/MAX7470 write
the contents of the control/status or frequency registers
to the bus. When the command byte indicates a read
operation of either the control/status or the frequency
register, the serial interface expects an Sr condition to
SCL
SDA
0
0
0
1
0
0
1
0
1
0
0
1
0
A1
A0
ACK
OUT
ACK
R/W
C7
C6
C5
C4
C3
C2
C1
C0
SDA
IN TO MAX7469/MAX7470
IN
OUT
DIRECTION
START
SCL (CONT)
SDA (CONT)
F7
F6
F5
F4
F3
F2
F1
F0
ACK
SDA
IN
OUT
IN
DIRECTION
COMMAND BYTE C7–C0 IS 0010010.
STOP
Figure 6. Write Sequence to Update the Frequency Register
SCL
SDA
1
0
0
1
0
A1
A0
R/W
ACK
ACK
0
0
0
0
0
0
0
0
C4
C3
C2
C1
C7
C6
C5
C0
SDA
IN TO MAX7469/MAX7470
OUT
IN
OUT
IN
DIRECTION
START
THE COMMAND BYTE IS FOR POWER-DOWN.
STOP
Figure 7. Write Sequence for a Command Byte
______________________________________________________________________________________ 13
HDTV Continuously Variable
Anti-Aliasing Filters
SCL
SDA
1
0
0
1
0
A1
A0
R/W
ACK
OUT
0
0
0
1
0
0
1/0
C1
ACK
OUT
1
C7
C6
C5
C4
C3
C2
C0
SDA
DIRECTION
IN TO MAX7469/MAX7470
IN
START
SCL (CONT)
SDA (CONT)
1
0
0
1
0
A1
A0
R/W ACK
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SDA
DIRECTION
IN
OUT
IN
Sr
STOP
Figure 8. Basic Read Sequence
69/MAX470
selected in the command byte. Figure 8 shows a basic
read sequence.
Table 5. Control/Status Register Bit
Description
Note: The master has to write a command byte,
requesting to read the control/status or frequency reg-
ister, to the slave (MAX7469/MAX7470) before the mas-
ter can read the contents of the selected register.
BIT
DESCRIPTION
0 = component input signal selected (default).
1 = composite input signal selected.
S7
Control/Status Register
The MAX7469/MAX7470 store their status in an 8-bit
register that can be read back by the master. The indi-
vidual bits of the control/status register are summarized
in Tables 4 and 5. The power-on default value of this
register is 03h.
0 = internal sync enabled (default).
1 = external sync enabled.
S6
S5
S4
S3
S2
S1
S0
0 = external sync: positive polarity (default).
1 = external sync: negative polarity.
0 = normal operation mode (default).
1 = power-down mode.
Frequency Register
The frequency response (-3dB passband edge) of the
MAX7469/MAX7470 can be continuously varied in 256
linear steps by changing the codes in the frequency reg-
ister (Table 6). See the Command Byte (Write Cycle) sec-
tion for a write sequence to update the frequency register.
0 = filters enabled (default).
1 = bypass mode—no filtering.
0 = clamp voltage for IN1 set to low (default).
1 = clamp voltage for IN1 set to high.
0 = clamp voltage for IN2 set to low.
1 = clamp voltage for IN2 set to high (default).
Table 4. Control/Status Register
CONTROL/STATUS REGISTER
0 = clamp voltage for IN3 set to low.
1 = clamp voltage for IN3 set to high (default).
S7
S6
S5
S4
S3
S2
S1
S0
Table 6. Frequency Register Setting for Different Video-Signal Formats
APPROXIMATE FREQUENCY
(-3dB) MHz
VIDEO-SIGNAL FORMAT
F7 F6 F5
F4 F3 F2
F1 F0 CODE NO.
Standard Definition (Interlaced)
Standard Definition (Progressive)
High-Definition Low Bandwidth
High-Definition High Bandwidth
0
0
1
1
0
1
1
1
1
0
0
1
0
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
40
90
10
15
220
255
30
34 (default)
14 _______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
I2C Compatibility
Power-Supply Bypassing and Layout
Considerations
The MAX7469/MAX7470 are compatible with existing
I2C systems supporting standard I2C 8-bit communica-
tions. The general call address is ignored, and CBUS
formats are not supported. The device’s address is
compatible with 7-bit I2C addressing protocol only; 10-
bit address formats are not supported.
The MAX7469/MAX7470 operate from a single +5V ana-
log supply and a +3.3V digital supply. Bypass AV
to
DD
GND with a 0.1µF capacitor and an additional 1µF
capacitor in parallel for additional low-frequency decou-
pling. Determine the proper power-supply bypassing
necessary by taking into account the desired distur-
bance level tolerable on the output, the power-supply
rejection of the MAX7469/MAX7470, and the amplitude
and frequency of the disturbance signals present in the
vicinity of the MAX7469/MAX7470. Use an extensive
ground plane to ensure optimum performance. The three
Applications Information
Input Considerations
Use 0.1µF ceramic capacitors to AC-couple the inputs.
The inputs cannot be DC-coupled. The internal clamp
circuit stores a DC voltage across the input capacitors
to obtain the appropriate output DC voltage level.
Increasing the value of these capacitors to improve line-
time distortion is not necessary due to the extremely low
input leakage current yielding a very low line-time dis-
tortion performance.
AV
pins (pins 7, 9, and 11) that supply the individual
channels can be connected together and bypassed as
one, provided the components are close to the pins.
DD
Bypass DV
to DGND with a 0.1µF capacitor. All
DD
ground pins (GND) must be connected to a low imped-
ance ground plane as close as possible to the device.
The MAX7469/MAX7470 provide a high input imped-
ance to allow a nonzero source impedance to be used,
such as when the input is connected directly to a back-
matched video cable, ensuring the external resistance
determines the termination impedance.
Place the input termination resistors as close as possi-
ble to the device. Alternatively, the terminations can be
placed further from the device if the PC board traces
are designed to be a controlled impedance of 75Ω.
Minimize parasitic capacitance as much as possible to
avoid performance degradation in the upper frequency
range possible with the MAX7469/MAX7470.
Output Considerations
The MAX7469/MAX7470 outputs can be DC- or AC-
coupled. The MAX7470, with its +6dB gain, is typically
connected to a 75Ω series back-match resistor fol-
lowed by the video cable. Because of the inherent
divide-by-two of this configuration, the blanking level of
the video signal is always less than 1V, which complies
with digital TV requirements.
Refer to the MAX7469/MAX7470 evaluation kit for a
proven PC board layout.
Exposed Pad and Heat Dissipation
The MAX7469/MAX7470 TQFN package has an
exposed pad on its bottom. This pad is electrically con-
nected, internal to the device, to GND. Do not route any
PC board traces under the package.
The MAX7469, with its 0dB gain, is typically connected
to an ADC or video decoder. This can be a DC or AC
connection. If a DC connection is used, ensure that the
DC input requirements of the ADC or video decoder
are compatible.
The MAX7469/MAX7470 typically dissipate 900mW of
power, therefore, pay careful attention to heat disper-
sion. The use of at least a two-layer board with a good
ground plane is recommended. To maximize heat dis-
persion, place copper directly under the MAX7469/
MAX7470 package so that it matches the outline of the
plastic encapsulated area. Do the same thing on the
bottom ground plane layer and then place as many
vias as possible connecting the top and bottom layers
to thermally connect it to the ground plane.
If an AC connection is used, choose an AC-coupling
capacitor value that ensures that the lowest frequency
content in the video signal is passed and the line-time
distortion is kept within desired limits. The selection of
this value is a function of the input impedance and,
more importantly, the input leakage of the circuit being
driven. Use a video clamp to reestablish the DC level, if
not already included in the subsequent circuit.
Maxim has evaluated a four-layer board using FR-4
material and 1oz copper with equal areas of metal on
the top and bottom side coincident with the plastic
encapsulated area of the 20-pin TQFN package. The
two middle layers are used as power and ground
The outputs of the MAX7469/MAX7470 are fully protected
against a short-circuit condition either to ground or the
positive supply of the device.
______________________________________________________________________________________ 15
HDTV Continuously Variable
Anti-Aliasing Filters
planes. The board has 21, 15-mil, plated-through via
holes between the top, bottom, and ground plane lay-
ers. Thermocouple measurements confirm device tem-
Chip Information
PROCESS: BiCMOS
peratures to be safely within maximum limits.
Typical Operating Circuit
AV
DD
EXT SYNC
SYNC DETECTOR
MAX7469
DECODER
A/D
MAX7470
0dB
(+6dB)
OUT1
Y/G
IN1
IN2
IN3
5MHz TO 34MHz
PROGRAMMABLE PASSBAND
LOWPASS FILTER
CLAMP/
BIAS
69/MAX470
0.1μF
0.1μF
75Ω
75Ω
75Ω
0dB
(+6dB)
OUT2
P /B
b
A/D
CLAMP/
BIAS
5MHz TO 34MHz
PROGRAMMABLE PASSBAND
LOWPASS FILTER
0.1μF
0.1μF
0dB
(+6dB)
OUT3
P /R
r
A/D
CLAMP/
BIAS
5MHz TO 34MHz
PROGRAMMABLE PASSBAND
LOWPASS FILTER
0.1μF
0.1μF
FREQUENCY
SELECT
BYPASS
CLAMP LEVEL
2
I C
INTERFACE
EXT SYNC
ENABLE
( ) FOR MAX7470
GND
SCL SDA
DV
A1 A0
DD
DGND
16 _______________________________________________________________________________________
HDTV Continuously Variable
Anti-Aliasing Filters
69/MAX470
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Heslington
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