MAX77504AAFC+T [MAXIM]
14V Input, 3A High-Efficiency Buck Converter in WLP or QFN;
| 型号： | MAX77504AAFC+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 14V Input, 3A High-Efficiency Buck Converter in WLP or QFN |
| 文件： | 总37页 (文件大小：1872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
General Description
Benefits and Features
The MAX77504 is a synchronous 3A step-down DC-DC
converter optimized for portable 2-cell and 3-cell battery-
operated applications. The converter operates on an input
supply between 2.6V and 14V. Output voltage is ad-
justable between 0.6V and 6V with external feedback re-
● 3A Single-Channel Buck Regulator
● 2.6V to 14V Input Voltage
● 0.6V to 6V Output Voltage Range
● 0.5MHz to 1.5MHz Fixed-Frequency Switching
Options
sistors. The device features a low-I SKIP mode that al-
● High Efficiency, Low I Extends Battery Life
Q
Q
lows excellent efficiency at light loads. The MAX77504
can be sychronized by driving the FPWM pin with an ex-
ternal clock.
• 94% Peak Efficiency at 7.4V , 3.3V
IN
(2520
OUT
Inductor)
• 10μA I
(12V , 1.8V
)
OUT
SUP
IN
Dedicated enable, power-OK, and FPWM pins allow sim-
ple hardware control. The SEL input easily configures
switching frequency, gain, and output active discharge op-
tion. Built-in undervoltage lockout (UVLO), output active
discharge, cycle-by-cycle inductor current limit, thermal
shutdown, and short-circuit protection ensure safe opera-
tion under abnormal operating conditions.
• OUT Powers V Automatically (V
> 1.7V) for
OUT
L
Low I
Q
● Enable Pin (EN) for Direct Hardware Control
● Extenal Clock Synchronization Is Available Through
the FPWM/SYNC Pin
● Power-OK Output (POK) Monitors V
Ordering Information)
Quality (See
OUT
The MAX77504 is offered in a small 1.7mm x 1.7mm,
16-bump, 0.4mm pitch wafer-level package (WLP) or a
2.5mm x 2.5mm, 12-lead, 0.5mm pitch flip-chip QFN
(FC2QFN).
● Protection Features
• Cycle-by-Cycle Inductor Current Limit
• Short-Circuit Hiccup Mode, UVLO, and Thermal
Shutdown Protection
• Soft-Start
Applications
● FC2QFN or WLP Package Option
• 2.5mm x 2.5mm (0.6mm max. height) 12-Lead
FC2QFN, 0.5mm Pitch
● 1- to 3-Cell Li+/Li-ion Battery-Powered Devices
● Professional Radio, Handheld Computers
● Mirrorless Cameras, DSLR, and Notebook Computers
● Portable Scanners, POS Terminals, Printers
● Space-Constrained Portable Electronics
• 1.7mm x 1.7mm (0.7mm max. height) 16-Bump
WLP, 0.4mm Pitch, 4 x 4 Array
● All WLP Package Bumps (Except POK) Routeable on
a Non-HDI PCB
Ordering Information appears at end of data sheet.
Simplified Application Circuit
EFFICIENCY vs. LOAD
7.4V SUPPLY
100
MAX77504
2.6V TO 14V
DC INPUT
BST
SUP
0.22μF
10μF
L
90
LX
V
OUT
80
70
60
50
40
30
20
10
0
0.6V TO 6V
3A MAX
OUT
C
C
OUT
FF
ENABLE
EN
R
R
TOP
BOT
VOUT = 5.0V
VOUT = 3.3V
FPWM/SYNC
POWER-OK
FPWM
POK
SEL
FB
VOUT = 1.8V
R
SEL
V
L
2.2μF
AGND
PGND
R
SEL
CONTROLS:
● SWITCHING FREQ.
● ACTIVE DISCHARGE
● GAIN
SKIP MODE
1
0.001
0.01
0.1
14V, 3A HIGH-EFFICIENCY BUCK CONVERTER
OPTIMIZED FOR 2 OR 3 CELL BATTERY APPLICATIONS
LOAD CURRENT (A)
19-100678; Rev 2; 7/20
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
TABLE OF CONTENTS
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
16 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 FC2QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bump/Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
16 WLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12 FC2QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bump/Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Buck Regulator Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Mode Control (FPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SKIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FPWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External Clock Synchronization (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Buck Enable Control (EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
V Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-OK (POK) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Output Voltage Connection (OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Configuration Selection Resistor (SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Active Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Short-Circuit Protection and Hiccup Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Buck Enable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Always-On. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Hardware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FPWM/SYNC Clock Pulse Width Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Design Procedure (Choosing R
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SEL
Switching Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Example A (9V to 3.3V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
IN
OUT
Example B (12V to 1.8V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
OUT
IN
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Maxim Integrated | 2
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
TABLE OF CONTENTS (CONTINUED)
Gain Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SUP Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Setting the Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
0.6V Output, 0.75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
0.82V Output, 0.75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.0V Output, 0.75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2V Output, 0.75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.8V Output, 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.5V Output, 1.5MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3V Output, 1.5MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5V Output, 1.5MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6V Output, 1.5MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Maxim Integrated | 3
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
LIST OF FIGURES
Figure 1. Buck Control Scheme Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 2. External Clock Synchronization Behavioral State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3. Buck Enable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. External Feedback Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 5. PCB Top-Metal and Component Layout Example (WLP Version). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 6. PCB Top-Metal and Component Layout Example (FC2QFN Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Maxim Integrated | 4
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
LIST OF TABLES
Table 1. Buck Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 2. Resistor-Set Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3. Configuration Selection Resistor (R
) Lookup Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SEL
Table 4. Inductor Value vs. Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5. Common Feedback Resistor Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6. Typical Application Circuit Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Maxim Integrated | 5
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Absolute Maximum Ratings
SUP to PGND......................................................... -0.3V to +16V
LX to PGND (DC) ................................................... -0.3V to +16V
AGND to PGND .....................................................-0.3V to +0.3V
OUT Short-Circuit Duration.........................................Continuous
EN to PGND ............................................... -0.3V to V
+ 0.3V
LX Continuous Current (Note 1) .................................... 3.2A
SUP
RMS
BST to LX .............................................................. -0.3V to +2.2V
Continuous Power Dissipation (Multilayer Board, T = +70°C)
A
V to PGND........................................................... -0.3V to +2.2V
16 WLP (derate 17.26mW/°C above +70°C)...............1381mW
12 FC2QFN (derate 14.23mW/°C above +70°C)........1139mW
Operating Junction Temperature Range.............-40°C to +125°C
Junction Temperature.......................................................+150°C
Soldering Temperature (reflow) ........................................+260°C
L
SEL to AGND .................................................. -0.3V to V + 0.3V
L
POK, FPWM/SYNC to PGND.. -0.3V to V
(V
+ 0.3V, +6V)
MIN SUP
OUT to AGND........................................................... -0.3V to +8V
FB to AGND.............................................................. -0.3V to +6V
Note 1: LX has internal clamp diodes to PGND and SUP. Applications that forward bias these diodes should not exceed the ICs
package power dissipation limits.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
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Maxim Integrated | 6
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Package Information
16 WLP
Package Code
W161L1+1
21-100334
Outline Number
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Refer to Application Note 1891
Junction to Ambient (θ
)
57.93°C/W
JA
COMMON DIMENSIONS
Pin 1
Indicator
E
see Note 7
Marking
A
0.05
0.03
0.64
0.19
1
A1
A2
A
0.45 REF
AAAA
D
A3
b
BASIC
0.04
0.27
0.03
0.025
0.025
BASIC
BASIC
D
1.688
1.688
TOP VIEW
SIDEVIEW
E
D1
E1
1.20
1.20
A3
e
0.40 BASIC
0.20 BASIC
0.20 BASIC
A1
S
SD
SE
A2
A
0.05
S
DEPOPULATED BUMPS:
NONE
FRONTVIEW
E1
SE
NOTES:
e
1. Terminal pitch isdefined by terminal center to center value.
2. Outer dimension isdefined by center linesbetween scribe lines.
3. All dimensionsin millimeter.
4. Marking shown isfor package orientation reference only.
5. Tolerance is± 0.02 unlessspecified otherwise.
6. All dimensionsapply to PbFree (+) package codesonly.
7. Front - side finish can be either Black or Clear.
SD
D
C
B
A
B
D1
1
2 3 4
b
M
S
AB
0.05
maxim
A
TM
integrated
TITLE
PACKAGEOUTLINE16 BUMPS
BOTTOM VIEW
WLP PKG. 0.4 mm PITCH,
W161L1+1
REV.
APPROVAL
DOCUMENTCONTROL NO.
1
- DRAWING NOTTO SCALE-
21-100334
A
1
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Maxim Integrated | 7
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
12 FC2QFN
Package Code
F122A2F+2
21-100406
90-100140
Outline Number
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
70.23°C/W
JA
1
·
1
maxim
integratedTM
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates
RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal
considerations, refer to www.maximintegrated.com/thermal-tutorial.
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Maxim Integrated | 8
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Electrical Characteristics
(V
= V
= 12V, V
= 0V (SKIP mode), V = 1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C, unless
SUP
EN
FPWM
L
A
J
A
J
otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STEP-DOWN CONVERTER
SUP Valid Voltage
Range
V
2.6
2.4
14
V
V
SUP
SUP Undervoltage
Lockout
V
V
rising
SUP
2.5
300
1.2
2.6
SUP-UVLO
SUP Undervoltage
Lockout Hysteresis
mV
μA
V
EN
= 0V (device disabled), T = -40°C to
J
SUP Shutdown Current
I
3
SUP-SHDN
+85°C
V
OUT
= 1.2V,
R
R
= 49.9kΩ,
= 49.9kΩ
33
12
14
TOP
BOT
V
OUT
= 1.8V,
= 46.4kΩ,
= 23.2kΩ
I
= 0mA, SKIP
LOAD
R
TOP
R
BOT
μA
mode
Supply Current
I
SUP
V
OUT
= 3.3V,
= 459kΩ,
= 102kΩ
R
TOP
R
BOT
I
= 0mA, FPWM mode, no switching
= 2.3V to 14V
1
1.5
mA
V
LOAD
V Regulator Voltage
L
V
L
V
1.8
SUP
OUT
V
rising, 100mV hysteresis, POK = 1,
V Power Input Switch-
L
Over Threshold
V
V input switches from SUP to OUT
above this threshold
1.6
1.7
0.6
1.75
V
SWO
L
V
SUP
= 12V, I
LOAD
= 250mA, T =
0.594
0.606
J
25°C
FB Voltage Accuracy
V
FB
FPWM mode
V
V
SUP
= 2.6V to
14V, I
to 3A, T = -40°C to
= 0mA
LOAD
0.588
0.6
0.612
J
+125°C
FB Input Current
I
V
= 0.6V
0.02
1.25
μA
ms
FB
FB
Measured from EN
rising edge to POK
rising edge
SFT_STRT = 0
(1ms ramp)
Total Startup Time
t
1.5
TSU
High-Side DMOS On-
Resistance
R
V = 1.8V, I = 180mA, V
= 4.5V
= 4.5V
50
27
4
100
54
mΩ
mΩ
A
ON-HS
L
LX
SUP
SUP
Low-Side DMOS On-
Resistance
R
V = 1.8V, I = 180mA, V
L LX
ON-LS
High-Side DMOS Peak
Current Limit
I
3.6
4.4
LX-PLIM
Output overloaded (V
target), threshold below where on-times
are allowed to start
< 67% of
OUT
Low-Side DMOS Valley
Current Threshold
I
2
A
LX-VALLEY
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Maxim Integrated | 9
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Electrical Characteristics (continued)
(V
= V
= 12V, V
= 0V (SKIP mode), V = 1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C, unless
SUP
EN
FPWM
L
A
J
A
J
otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
High-Side DMOS
Minimum Current
Threshold
Inductor current ramps to at least
in SKIP mode
I
500
mA
LX-PK-MIN
I
LX-PK-MIN
Low-Side DMOS Zero-
Crossing Threshold
I
SKIP mode
40
mA
A
ZX
Low-Side DMOS
Negative Current Limit
Threshold
I
mFPWM Mode
-1.5
NEG
Dropout condition (V
< V
target);
OUT
SUP
Maximum Duty Cycle
D
f
on-times extend for 16 clocks before LX
drives low for 200ns to refresh C
99
%
MAX
BST
FSW[1:0] = 0b00
FSW[1:0] = 0b01
FSW[1:0] = 0b10
FSW[1:0] = 0b11
0.475
0.7125
0.95
0.5
0.75
1
0.525
0.7875
1.05
FPWM mode, T =
J
-40°C to +85°C
Switching Frequency
MHz
SW
1.425
1.5
1.575
Minimum Switching
Frequency
F
SKIP mode
1.2
1.43
66.7
1.7
kHz
%
SW-MIN
Soft-Short Output
Voltage Monitor
Threshold
Expressed as a percentage of target
V
OUT-OVRLD
V
OUT
Switching stopped because output
voltage has fallen to less than 67% of
target and 15 LX cycles ended by current
limit; time before converter attempts to
soft-start again
Output-Overloaded
Retry Timer
t
15
100
92
ms
Ω
RETRY
Active Discharge
Resistor
Between OUT and PGND, buck output
disabled, ADEN = 1
R
AD
POWER-OK OUTPUT (POK)
V
of V
rising, expressed as a percentage
OUT-REG
OUT
V
90
88
94
92
POK_RISE
POK Threshold
%
V
OUT
falling, expressed as a percentage
V
90
12
POK_FALL
of V
OUT-REG
POK Debounce Timer
POK Leakage Current
t
V
OUT
rising or falling
μs
μA
V
POK-DB
POK = high (high impedance), V
=
POK
I
1
POK
5V, T = 25°C
A
POK Low Voltage
V
POK = low, sinking 1mA
0.4
POK
ENABLE INPUT (EN)
EN Logic-High
Threshold
V
1.1
V
EN_HI
EN Logic-Low Threshold
EN Leakage Current
V
0.4
1
V
EN_LO
I
V
EN
= V = 14V
SUP
0.1
μA
EN
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Maxim Integrated | 10
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Electrical Characteristics (continued)
(V
= V
= 12V, V
= 0V (SKIP mode), V = 1.8V, T = T = -40°C to +125°C, typical values are at T = T = +25°C, unless
SUP
EN
FPWM
L
A
J
A
J
otherwise noted.) (Note 2)
PARAMETER
FPWM/SYNC
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FPWM/SYNC Logic-
High Threshold
V
1.1
V
V
FPWM_HI
FPWM/SYNC Logic-Low
Threshold
V
0.4
FPWM_LO
FSW[1:0] = 0b00
(0.5MHz)
0.394
0.526
0.789
1.05
0.690
0.920
1.38
FSW[1:0] = 0b01
(0.75MHz)
Valid Synchronization
Range (Note 3)
T = -40ºC to
J
+85ºC
F
MHz
SYNC-VALID
FSW[1:0] = 0b10
(1.0MHz)
FSW[1:0] = 0b11
(1.5MHz)
1.84
THERMAL PROTECTION
Thermal Shutdown
T
Junction temperature rising
+165
+15
°C
°C
SHDN
Thermal Shutdown
Hysteresis
Note 2: The MAX77504 is tested under pulsed load conditions such that T ≈ T . Min/Max limits are 100% production tested at T
A
A
J
= +25°C. Limits over the operating temperature range are guaranteed by design and characterization using statistical quality
control methods. Note that the maximum ambient temperature consistent with this specification is determined by specific
operating conditions, board layout, rated package thermal impedance, and other environmental factors.
Note 3: Synchronization specifications are only valid for product variants that include the feature. See the Ordering Information table
to find the availability of synchronization for each orderable part number.
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Maxim Integrated | 11
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Operating Characteristics
(V
= 7.4V, V
= 3.3V, FPWM = 0, I
= 4A, T = +25°C, unless otherwise noted. See the Typical Application Circuits
SUP
OUT
LX-PLIM
A
section for each V
configuration.)
OUT
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Maxim Integrated | 12
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Operating Characteristics (continued)
(V
= 7.4V, V
= 3.3V, FPWM = 0, I
= 4A, T = +25°C, unless otherwise noted. See the Typical Application Circuits
SUP
OUT
LX-PLIM
A
section for each V
configuration.)
OUT
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Maxim Integrated | 13
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Operating Characteristics (continued)
(V
= 7.4V, V
= 3.3V, FPWM = 0, I
= 4A, T = +25°C, unless otherwise noted. See the Typical Application Circuits
SUP
OUT
LX-PLIM
A
section for each V
configuration.)
OUT
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Maxim Integrated | 14
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Operating Characteristics (continued)
(V
= 7.4V, V
= 3.3V, FPWM = 0, I
= 4A, T = +25°C, unless otherwise noted. See the Typical Application Circuits
SUP
OUT
LX-PLIM
A
section for each V
configuration.)
OUT
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Maxim Integrated | 15
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Operating Characteristics (continued)
(V
= 7.4V, V
= 3.3V, FPWM = 0, I
= 4A, T = +25°C, unless otherwise noted. See the Typical Application Circuits
SUP
OUT
LX-PLIM
A
section for each V
configuration.)
OUT
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Maxim Integrated | 16
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Bump/Pin Configurations
16 WLP
TOP VIEW
(BUMP SIDE DOWN)
MAX77504
1
2
3
4
+
A
BST
SUP
SUP
POK
LX
PGND
PGND
OUT
FB
B
EN
LX
C
FPWM/SYNC
AGND
AGND
D
SEL
V
L
16 WLP
(1.7mm x 1.7mm x 0.7mm, 0.4mm BUMP PITCH)
12 FC2QFN
TOP VIEW
SUP
12
LX
11
PGND
10
1
2
3
4
BST
EN
MAX77504
FPWM/
SYNC
9
8
OUT
FB
POK
5
6
7
SEL
AGND
V
L
12 FC2QFN
(2.5mm x 2.5mm x 0.6mm, 0.5mm LEAD PITCH)
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Maxim Integrated | 17
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Bump/Pin Descriptions
PIN
NAME
FUNCTION
16 WLP
12 FC2QFN
High-Side FET Driver Supply. Connect a 0.22μF ceramic capacitor between BST
and LX.
A1
1
BST
SUP
Buck Supply Input. Bypass to PGND with a 10μF ceramic capacitor as close to the
IC as possible.
A2, B2
12
A3, B3
A4, B4
C3, D3
11
10
7
LX
Switching Node. LX is high-impedance when the converter is disabled.
Power Ground. Connect to AGND on the PCB.
PGND
AGND
Quiet Ground. Connect to PGND on the PCB.
Open-Drain, Power-OK Output. An external pullup resistor (10kΩ to 100kΩ) is
required to use this pin. Leave this pin unconnected if unused.
C2
D2
4
6
POK
Low-Voltage Internal IC Supply Output. Powered from SUP or OUT depending on
V
L
V
OUT
. Bypass to AGND with a 2.2μF ceramic capacitor. Do not load this pin
externally.
Feedback Sense Input. Connect a resistor voltage divider between the converter's
output and AGND to set the output voltage. Do not route FB close to sources of
EMI or noise.
D4
B1
8
2
FB
EN
Enable Input. Drive EN above V
to enable the buck output. Drive EN to
EN_HI
PGND to disable. EN is compatible with the SUP voltage domain.
Buck Mode Control and External Clock Synchronization Input. Drive FPWM/SYNC
above V
to enable forced-PWM mode. Connect to ground to enable SKIP
FPWM_HI
mode. See the Mode Control (FPWM) section for more information.
Provide an external clock signal with a frequency inside the valid range (f
SYNC-
C1
3
FPWM/SYNC
) to enable externally synchronized forced-PWM mode while the buck is
VALID
enabled. See the External Clock Synchronization (SYNC) section for more
information.
Not all MAX77504 versions include the synchronization feature. Consult the
Ordering Information.
Output Voltage Sense Input. Connect to the buck output capacitor. Do not connect
anywhere else.
C4
D1
9
5
OUT
SEL
Configuration Selection Input. Connect a ±1% selection resistor (R
) between
SEL
SEL and AGND to configure MAX77504 options. See the Configuration Selection
Resistor (SEL) section for more information.
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Maxim Integrated | 18
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Detailed Description
The MAX77504 is a small, high-efficiency 3A step-down (buck) DC-DC converter. The step-down converter uses
synchronous rectification and internal current-mode compensation. The buck operates on a supply voltage between
2.6V and 14V. Output voltage is set by external feedback resistors between 0.6V and 6V. The buck utilizes an ultra-low
quiescent current (I ) SKIP mode (10μA typ for 1.8V
Q
) that maintains very high efficiency at light loads.
OUT
Buck Regulator Control Scheme
The step-down converter uses a PWM peak current-mode control scheme with a high-gain architecture. Peak current-
mode control provides precise control of the inductor current on a cycle-by-cycle basis and inherent compensation for
supply voltage variation.
On-times (MOSFET Q1 on) are started by a fixed-frequency clock and terminated by a PWM comparator. See Figure
1. When an on-time ends (starting an off-time) current conducts through the low-side MOSFET (Q2 on). Shoot-through
current from SUP to PGND is avoided by introducing a brief period of dead time between switching events when neither
MOSFET is on. The inductor current is conducted through Q2's intrinsic body diode during dead time.
The PWM comparator regulates V
by controlling duty cycle. The negative input of the PWM comparator is a voltage
OUT
proportional to the actual output voltage error. The positive input is the sum of the current-sense signal through MOSFET
Q1 and a slope-compensation ramp. The PWM comparator ends an on-time when the error voltage becomes less than
the slope-compensated current-sense signal. On-times begin again due to a fixed-frequency clock pulse. The controller's
compensation components and current-sense circuits are integrated. This reduces the risk of routing sensitive control
signals on the PCB.
A high-gain architecture is present in the controller design. The feedback uses an integrator to eliminate steady-state
output voltage error while the converter is conducting heavy loads. See the Typical Operating Characteristics sections
for information about the converter's typical voltage regulation behavior versus load.
SUP
V
L
SWITCH-OVER CONTROL
V LDO
L
EN
AGND
I
V
LX-PLIM
ILIM
L
OUT
BST
SLOPE
COMPENSATION
SEL
CONFIGURATION
DECODER
Q1
FPWM/SYNC
CLOCK
REFERENCE
S
R
Q
Q
DIGITAL
LX
PWM
LOGIC
SOFT-START
RAMP
V
L
Q2
g
m
FB
R
COMP
I
ZX
C
COMP
I
LX-VALLEY
AGND
PGND
POK
Figure 1. Buck Control Scheme Diagram
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Maxim Integrated | 19
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Mode Control (FPWM)
FPWM is an active-high digital input that controls the buck converter's mode. Raise FPWM above V
to enable
FPWM_HI
forced-PWM (FPWM) mode. Lower FPWM to AGND to enable SKIP mode. Always drive this pin to prevent mode chatter.
Some MAX77504 versions use the FPWM input for external clock synchronization (FPWM/SYNC). See the Ordering
Information to find which MAX77504 part numbers include the synchronization feature. See the External Clock
Synchronization (SYNC) section of the data sheet for a functional description of this feature.
SKIP Mode
SKIP mode causes discontinuous inductor current at light loads by forcing the low-side MOSFET (Q2) off if inductor
current falls below I (40mA typ) during an off-time. This prevents inductor current from sourcing back to the input (SUP)
ZX
and enables high-efficiency by reducing the total number of switching cycles required to regulate the output voltage.
When the load is very light and the output voltage is in regulation, then the converter automatically transitions to
standby mode. In this mode, the LX node is high-impedance and the converter's internal circuit blocks are deactivated
to reduce I consumption. Output voltage typically rests 2.5% above the regulation target in standby mode. A low-power
Q
comparator monitors the output voltage during standby. The converter reactivates and starts switching again when V
OUT
drops below 102% of regulation target. Inductor current ramps to at least I
cycle.
(500mA typ) upon every switching
LX-PK-MIN
FPWM Mode
The low-side MOSFET (Q2) current-limit threshold is I
(-1.5A typ) in FPWM mode, which allows the converter to
NEG
switch at constant frequency at light loads. The buck has the best possible load-transient response in this mode at the
cost of higher I consumption. Use FPWM for applications that do not require low-I and/or when heavy load transients
Q
Q
are expected. Switching frequency is fixed by an internal oscillator in FPWM mode. See Table 1.
Table 1. Buck Switching Frequency
FSW[1:0]
SWITCHING FREQUENCY (f ) (MHz)
SW
00
01
10
11
0.5
0.75
1.0
1.5
A configuration resistor between SEL and AGND programs FSW[1:0]. See the Configuration Selection Register (SEL) section and
Table 2.
External Clock Synchronization (SYNC)
Select MAX77504 versions use the FPWM/SYNC input for external clock synchronization. See the Ordering Information
to find which MAX77504 part numbers include the synchronization feature.
Provide an external clock signal to FPWM/SYNC with a frequency inside the valid range (f
) to enable
SYNC-VALID
externally synchronized forced-PWM (FPWM) mode. The valid lockable range shifts depending on the chosen internal
switching frequency (FSW[1:0] programmed by R ). See the FPWM/SYNC section of the Electrical Characteristics
SEL
table for the guaranteed valid lock ranges versus FSW[1:0] choice. External synchronization can only happen after the
converter enables, soft-start finishes, and the external signal's frequency is valid.
An internal digital state machine (drawn in Figure 2) evaluates the external clock frequency on a cycle-by-cycle basis
to determine if the signal's frequency is within the valid range. If the logic detects 16 consecutive cycles within the valid
range then the buck immediately synchronizes the beginning of the next on-time with the rising edge of the external clock
on FPWM/SYNC. The converter maintains on-time synchronization as long as each subsequent external clock cycle
remains within the valid range. If the logic detects a single invalid external clock cycle (a rising edge that comes too fast
or too slow), then the converter immediately reverts back to its internal oscillator (FSW[1:0] programmed by R
). The
SEL
converter returns to SKIP mode when FPWM/SYNC asserts low for the debounce time, t
(5μs typ).
DB-SKIP
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Maxim Integrated | 20
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
FPWM/SYNC RISING EDGE
INSIDE VALID RANGE
FPWM/SYNC = 0
FPWM/SYNC = 1
16 CONSECUTIVE
FPWM/SYNC VALID RISING
EDGES
FPWM/SYNC RISING EDGE
FPWM/SYNC DEBOUNCED 0
SKIP MODE
FPWM MODE
INTERNAL CLOCK
FPWM MODE
INTERNAL CLOCK
EXTERNAL CLOCK
ONE INVALID FPWM/SYNC
RISING EDGE
(FPWM/SYNC = 0 FOR t
)
DB-SKIP
Figure 2. External Clock Synchronization Behavioral State Machine
Applications using the external synchronization function must consider minimum on-time restrictions when providing the
external clock. The Switching Frequency Selection section details these restrictions. Minimum on-time restrictions are
valid regardless of whether the switching frequency is controlled with an internal or external clock.
Buck Enable Control (EN)
Raise the EN pin voltage above V
(or tie to SUP) to enable the buck output. Lower EN to PGND to disable.
EN_HI
V Regulator
L
An integrated 1.8V linear regulator (V ) provides power to low-voltage internal circuit blocks and switching FET gate
L
drivers.
SUP powers V when V
is set less than the switch-over threshold (V
, 1.7V typical). If V
> V , then the V
SWO L
L
OUT
SWO
OUT
regulator power input switches from SUP to OUT after the buck soft-start ramp finishes and POK = 1. Switching V 's input
L
to OUT utilizes the buck's high-efficiency to power the linear regulator (as opposed to SUP) and improves the device's
total power efficiency.
Do not load V externally. The V regulator activates whenever EN is high. Connect a 2.2μF ceramic capacitor from V
L
L
L
to ground on the PCB.
Soft-Start
The device has an internal soft-start timer (t ) that controls the ramp time of the output as the converter is starting.
SS
Soft-start limits inrush current during buck startup. The converter soft-starts every time the buck enables, exits a UVLO
condition, and/or retries from an overcurrent (hiccup) or overtemperature condition. 1ms ramp time is available and only
programmable at the factory.
Power-OK (POK) Output
The device features an active-high, open-drain POK output to monitor the output voltage. POK requires an external pullup
resistor (typically 10kΩ to 100kΩ). POK goes high (high-impedance) after the buck converter output increases above
92% (V
) of the target regulation voltage and the soft-start ramp is done. POK goes low when the output drops
POK_RISE
below 90% (V
) of target or when the buck is disabled.
POK_FALL
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Maxim Integrated | 21
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Output Voltage Connection (OUT)
OUT is an analog power input used to sense the buck's output voltage and optionally power the dedicated internal V
regulator.
L
● The buck adjusts its own internal compensation ramp based on V
.
OUT
● The V regulator's power input switches to OUT when V
> V
. See the V Regulator section.
SWO L
L
OUT
● The active discharge resistor (R ) discharges the buck's output through the OUT pin when the buck is disabled and
AD
ADEN = 1. See the Active Discharge Resistor section.
Connect OUT to the buck converter's nearest output capacitor. Do not connect OUT anywhere else. See the PCB Layout
Guidelines section for a layout example.
Configuration Selection Resistor (SEL)
Connect a ±1% tolerance (or better) configuration selection resistor (R
) between SEL and AGND to configure five
SEL
bits of options decoded in Table 2. See the Design Procedure (Choosing R
) section for the procedure to select the
SEL
best configuration options for the buck converter's intended application.
The device evaluates the resistance between SEL and AGND whenever SUP is valid and EN transitions from logic 0 to
1. The decoded value of R latches until the next EN rising edge.
SEL
Active Discharge Resistor
The device integrates a 100Ω active discharge resistor (R ) between OUT and PGND that discharges the output
AD
capacitor when the buck is disabled. This function is enabled/disabled using the ADEN bit. Use a configuration resistor
between SEL and AGND to program ADEN. See Table 2.
R
discharges the output capacitor for 15ms when ADEN = 1 and the buck is disabled. The OUT pin returns to a high-
AD
impedance state after this time.
Short-Circuit Protection and Hiccup Mode
The device has fault protection designed to protect itself from abnormal conditions. If the output is overloaded, cycle-by-
cycle current limit prevents inductor current from increasing beyond I
.
LX-PLIM
The buck stops switching if V
falls to less than 67% of target and 15 consecutive on-times are ended by current limit.
OUT
After switching stops, the buck waits for t
before attempting to soft-start again (hiccup mode). While V
is less
RETRY
OUT
than 67% of target, the converter prevents new on-times if the inductor current has not fallen below I
. This
LX-VALLEY
prevents inductor current from increasing uncontrollably due to the short-circuited output.
Thermal Shutdown
The device has an internal thermal protection circuit that monitors die temperature. The temperature monitor disables the
buck if the die temperature exceeds T
approximately 15°C.
(165°C typ). The buck soft-starts again after the die temperature cools by
SHDN
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Maxim Integrated | 22
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Applications Information
Buck Enable Options
The MAX77504 offers two control options using the EN pin. See Figure 3 for suggested methods of controlling the buck
converter.
ALWAYS-ON
HARDWARE CONTROL
CONFIGURATION
CONFIGURATION
BUCK
INPUT
BUCK
INPUT
MAX77504
MAX77504
SUP
SUP
EN
EN
CONNECT
EN TO SUP
DRIVE EN PIN
Figure 3. Buck Enable Options
Always-On
Strap the EN pin to SUP to configure the device in an always-on configuration. See Figure 3 (left). The buck converter
activates whenever V
is valid and T < T
.
SHDN
SUP
J
Hardware Control
Drive the EN pin externally to control the buck. See Figure 3 (right). The buck converter activates whenever V
>
EN
V
EN_HI
(1.1V min), T < T
, and V
is valid.
SUP
J
SHDN
FPWM/SYNC Clock Pulse Width Requirements
Applications using an external clock should choose a clock with close to 50% duty cycle. Keep clock duty cycles within
±25% of the clock period. For example, if the input clock has a period of 1μs (i.e., 1MHz), a 50% duty cycle has a 500ns
pulse width and the clock should not exceed ±250ns away from this. Valid on times in this specific case include 250ns to
750ns within the 1μs period.
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Maxim Integrated | 23
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Design Procedure (Choosing R
)
SEL
The configuration selection resistor (RSEL) sets five bits of configuration options decoded in Table 2. Choose RSEL[4:0]
carefully by following the procedure outlined in this section. See the Typical Application Circuits section for a list of known
good RSEL choices for common applications. Contact Maxim for help or questions with this procedure.
Table 2. Resistor-Set Configuration Bits
RSEL[4:0]
NAME
DESCRIPTION
DECODE
MSB Bit 4
00 = 0.5MHz
01 = 0.75MHz
10 = 1.0MHz
11 = 1.5MHz
Switching Frequency Control. Sets f
.
SW
FSW[1:0]
Lower f
requires more C
to maintain stability.
Bit 3
Bit 2
Bit 1
SW
OUT
00 = 75kΩ
01 = 100kΩ
10 = 150kΩ
11 = 200kΩ
Mid-band Gain Control. Sets R
.
COMP
GAIN[1:0] Higher R
increases gain and improves transient response, but requires
COMP
more C
to maintain stability.
OUT
0 = Disabled
1 = Enabled
LSB Bit 0
ADEN
Active discharge resistor enable.
Program these bits by choosing a configuration selection resistor (R
) with a tolerance of ±1% or better using lookup Table 3.
SEL
Follow the design procedure to determine RSEL[4:0]. Use Table 3 to choose the corresponding R
value.
SEL
Table 3. Configuration Selection Resistor (R
) Lookup Table
SEL
R
(Ω) → RSEL[4:0]
SEL
95.3Ω or SHORT → 0x00
200Ω → 0x01
1620Ω → 0x0B
1870Ω → 0x0C
2150Ω → 0x0D
2490Ω → 0x0E
2870Ω → 0x0F
3740Ω → 0x10
8060Ω → 0x11
12400Ω → 0x12
16900Ω → 0x13
21500Ω → 0x14
26100Ω → 0x15
30900Ω → 0x16
36500Ω → 0x17
309Ω → 0x02
42200Ω → 0x18
422Ω → 0x03
48700Ω → 0x19
536Ω → 0x04
56200Ω → 0x1A
649Ω → 0x05
64900Ω → 0x1B
768Ω → 0x06
75000Ω → 0x1C
86600Ω → 0x1D
100000Ω → 0x1E
115000Ω or OPEN → 0x1F
909Ω → 0x07
1050Ω → 0x08
1210Ω → 0x09
1400Ω → 0x0A
For example, choose a 30.9kΩ (±1% TOL) resistor to program RSEL[4:0] to 0x16. 0x16 (0b10110) decodes with the
following configuration:
● FSW[1:0] = 0b10 (1MHz switching frequency)
● GAIN[1:0] = 0b11 (200kΩ R
)
COMP
● ADEN = 0b0 (active discharge disabled)
Table 3 indicates that a 30.9kΩ selection resistor selects code 0b10110 (0x16).
The device evaluates R
whenever SUP is valid and EN transitions from logic 0 to 1. The decoded value of R
is
SEL
SEL
latched until the next EN rising edge.
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Maxim Integrated | 24
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Switching Frequency Selection
See the Typical Application Circuits section of the data sheet for a list of known good switching frequency choices for
common output voltages.
Program the converter's switching frequency (f ) using the external selection resistor (R
SW
) to set the bits in FSW[1:0].
SEL
See Table 2, bits 3 and 4.
The converter's minimum on-time (t
) limits the maximum f
choice. The required on-time (t
) to regulate
ON-MIN
SW
ON(REQ)
a desired output voltage must be greater than the converter's minimum on-time to ensure stable operation.
t
≥ t
ON(REQ) ON‐MIN
Large step-down ratios (high V , low V
switching period) results in shorter on-times compared to lower F
frequency converters are desired due to their low output voltage ripple, small external component size, and high closed-
loop bandwidth.
) result in low duty cycles and require short on-times. High F
(short
SW
IN
OUT
(long switching period). Generally, fast switching
SW
Determine the application's target output voltage (V
) and maximum expected input voltage (V
). Start with the
OUT
IN(MAX)
highest F
option (1.575MHz with tolerance) and compute the on-time required for stable operation (t
) using
ON(REQ)
SW
Equation 1.
Equation 1:
V
OUT
t
=
ON(REQ)
V
× F
IN(MAX)
SW
Compare t
with t
(100ns max). If t
is less than 100ns, then reduce the F
to the next
SW
ON(REQ)
ON-MIN
ON(REQ)
slowest option and recompute. Always consider f
with tolerance using the guaranteed upper limit. See the Electrical
SW
Characteristics table for more information.
If the slowest f
choice (525kHz with tolerance) results in a required on-time that is less than t
, then reduce the
ON-MIN
SW
application's maximum expected input voltage using external methods.
Example A (9V to 3.3V
)
OUT
IN
for a 3.3V power supply operating from a 2s Li+ battery stack (9V max).
Choose f
SW
● Target V
= 3.3V
OUT
● V
= 9V
IN(MAX)
Try the highest switching frequency first (1.5MHz typ, 1.575MHz max). Use Equation 1 to compute required on-time
(t
):
ON(REQ)
3.3V
9V×1.575MHz
t
=
= 232.8ns (OK)
ON(REQ)
The choice of 1.5MHz typical switching frequency is OK because t
(100ns max).
is greater than the upper limit of t
ON-MIN
ON(REQ)
Example B (12V to 1.8V
)
OUT
IN
for a 1.8V power supply operating from a 12V (±5%) supply rail.
Choose f
SW
● Target V
= 1.8V
OUT
● V
= 12V + 5% = 12.6V
IN(MAX)
Try the highest switching frequency first (1.5MHz typ, 1.575MHz max). Use Equation 1 to compute required on-time
(t
):
ON(REQ)
1.8V
12.6V×1.575MHz
t
=
= 90.7ns (not OK)
ON(REQ)
The choice of 1.5MHz typical switching frequency is not OK because t
is shorter than the upper limit of t
ON-MIN
ON(REQ)
(100ns). Choose the next slowest f
(1MHz typ, 1.05MHz max) and recompute Equation 1.
SW
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Maxim Integrated | 25
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
1.8V
12.6V×1.05MHz
t
=
= 136.1ns (OK)
ON(REQ)
The choice of 1MHz typical switching frequency is OK because t
is greater than 100ns.
ON(REQ)
Gain Selection
See the Typical Application Circuits section of the data sheet for a list of known good gain choices for common output
voltages and C values.
OUT
Program the converter's mid-band gain by changing R
using the GAIN[1:0] bitfield. Program GAIN[1:0] using the
COMP
external selection resistor (R
). See Table 2, bits 1 and 2.
SEL
The converter's mid-band gain is limited by the switching frequency (f ) choice and effective output capacitance (C
)
SW
OUT
requirement. High gain (large R
) results in better transient performance but requires additional C
for stability.
COMP
OUT
Low gain (small R
) requires less C
at the expense of transient performance. Generally, converters with higher
COMP
OUT
gain are desired due to their fast transient response and high V
regulation quality versus disturbances.
OUT
The choice of R
and C
must not allow the closed-loop unity-gain bandwidth (f ) of the converter to exceed
OUT BW
COMP
20% of the switching frequency.
f
≤ 0.2 × f
BW
SW
SUP Capacitor Selection
Choose the input capacitor (C
) to be a 10μF nominal ceramic decoupling capacitor and place it as close to the SUP
SUP
pin as possible. Larger values improve the decoupling of the buck converter, but increase inrush current from the voltage
supply when connected. C reduces the current peaks drawn from the input power source during buck operation and
SUP
reduces switching noise in the system. The ESR/ESL of C
and its series PCB trace should be very low. Ceramic
SUP
capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small temperature
coefficients.
All ceramic capacitors derate with DC bias voltage (effective capacitance goes down as DC bias goes up). Generally,
small case size capacitors derate heavily compared to larger case sizes (0603 case size performs better than 0402).
Consider the effective capacitance value carefully by consulting the manufacturer's data sheet. Refer to Application Note
5527: Temperature and Voltage Variation of Ceramic Capacitors, or Why Your 4.7µF Capacitor Becomes a 0.33µF
Capacitor for more information.
Output Capacitor Selection
Choose an output capacitance (COUT) based on the transient performance requirements with a minimum of 8μF
effective capacitance for stable operation.
Effective C
is the actual capacitance value seen by the buck output during operation. Choose effective C
OUT
OUT
carefully by considering the capacitor's initial tolerance, variation with temperature, and derating with DC bias.
See the Typical Application Circuits section for recommended output capacitors for each use case.
Larger values of C
(above the required effective minimum) improve load transient performance, but increase the input
OUT
surge currents during soft-start and output voltage changes. The output filter capacitor must meet output ripple and load
transient requirements. The output capacitance must be high enough to absorb the inductor energy while transitioning
from full-load to no-load conditions. Calculate output voltage ripple (V
) to ensure the requirements are met:
RIPPLE(P-P)
V
= (LIR) (8xf xC
)
SW OUT
/
RIPPLE P ‐ P
(
)
where LIR is the inductor current ripple. Compute LIR with Equation 2.
Equation 2:
V
× V − V
(
)
OUT
IN
OUT
LIR =
V
× f
× L
IN SW
where V is the application's input voltage and f
IN
is the switching frequency. See Table 1.
SW
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Maxim Integrated | 26
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
After taking careful consideration of the output voltage ripple, finalize the selection of the output capacitance based on
the transient performance requirements. See the Typical Application Circuits section for recommended output capacitors
for each use case that have a load transient performance of ±5% overshoot and undershoot with a 1.5A load step (5A/
μs slew rate).
Ceramic capacitors with X5R or X7R dielectric are highly recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate with DC bias voltage (effective capacitance goes down as DC bias
goes up). Generally, small case size capacitors derate heavily compared to larger case sizes (0603 case size performs
better than 0402). Consider the effective capacitance value carefully by consulting the manufacturer's data sheet.
Inductor Selection
Choose an inductor with a saturation current greater than or equal to the maximum peak current limit (I
). Inductors
LX-PLIM
with lower saturation current and higher DCR ratings tend to be physically small. Higher values of DCR reduce buck
efficiency. Choose the RMS current rating of the inductor (the current at which temperature rises appreciably) based on
the system's expected load current.
Choose an inductor value based on the V
setting. See Table 4.
OUT
Table 4. Inductor Value vs. Output Voltage
SUGGESTED COMPONENT
PART NUMBERS*
V
OUT
RANGE
INDUCTOR VALUE (μH)
MURATA DFE252012F-1R0M
MURATA DFE252010F-1R0M
SAMSUNG CIGT252010EH1R0MNE
COILCRAFT XGL4020-102ME
V
≤ 1.3V
1
OUT
MURATA DFE252012F-1R5M
MURATA FDSD0412-H-1R5M
TDK SPM3015T-1R5M-LR
1.3V < V
≤ 4.5V
1.5
2.2
OUT
COILCRAFT XGL4020-152ME
MURATA FDSD0415-H-2R2M
COILCRAFT XGL4020-222ME
V
OUT
> 4.5V
*List compiled circa 2019. Always consider the most recent inductor offerings for new designs to achieve best possible MAX77504
circuit performance.
The chosen inductor value (L) should ensure that the peak inductor ripple current (I
) is below the high-side MOSFET
PEAK
peak current limit (I
, 4A typ) so that the buck can maintain voltage regulation over load.
LX-PLIM
Use Equation 3 and Equation 4 to compute I
value.
. If I
is greater than the limit (I ) then increase the inductor
LX-PLIM ,
PEAK
PEAK
Equation 3:
V
× V
(
− V
OUT
)
OUT
V
IN(MAX)
× f
I
=
P-P
× L
IN(MAX) SW
Equation 4:
I
P‐P
I
= I
+
PEAK
LOAD
2
where I
is the buck's output current in the particular application (3A max), V
expected input voltage (up to 14V), and f
section.
is the application's largest
IN(MAX)
is the chosen switching frequency. See the Switching Frequency Selection
LOAD
SW
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Maxim Integrated | 27
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Setting the Output Voltage
The IC uses external feedback resistors (R
and R
) to set V between 0.6V and 6V. Connect a resistor divider
OUT
TOP
BOT
between V
, FB, and AGND as shown in Figure 4. One percent tolerance resistors (or better) are recommended to
OUT
maintain high output accuracy. Choose R
to be 10kΩ or greater. Calculate the value of R
for a desired output
TOP
BOT
voltage with Equation 5.
Equation 5:
V
OUT
R
= R
×
BOT
− 1
TOP
V
[
]
FB
where V is 0.6V and V
is the desired output voltage.
FB
OUT
V
OUT
R
OUT
C
FF
TOP
MAX77504
FB
R
BOT
AGND
Figure 4. External Feedback Network
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Maxim Integrated | 28
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Table 5 lists common feedback resistor combinations for various output voltages. For voltages not listed, see the closest
output voltage in the table and take the RBOT value as a starting point. Then calculate RTOP using Equation 5.
See the Typical Application Circuits section of the data sheet for a list of known configurations for these output voltages.
Table 5. Common Feedback Resistor Values
OUTPUT VOLTAGE TARGET (V)
R
TOP
(kΩ)
R
BOT
(kΩ)
0.6
0.7
0.82
1.0
1.2
1.5
1.8
1.85
2.05
2.5
3.0
3.3
3.6
5.0
5.6
6.0
SHORT
1.84
4.07
75
OPEN
11.1
11.1
49.9
49.9
23.2
23.2
23.2
23.2
23.2
11.1
11.1
11.1
62.6
20
49.9
34.8
46.4
48.1
56.2
73.2
44.2
49.9
55.6
459
167
180
20
Table 6 suggests which typical application circuit corresponds to which range of output voltages. Use this table to
determine the C , R , and C values.
FF SEL
OUT
Table 6. Typical Application Circuit Reference
OUTPUT VOLTAGE TARGET (V)
TYPICAL APPLICATION CIRCUIT REFERENCE
0.6
0.6V
0.82V
1.0V
1.2V
1.8V
2.5V
3.3V
5.0V
6.0V
0.6 < V
0.9 < V
1.1 < V
1.4 < V
2.1 < V
2.9 < V
4.0 < V
5.5 < V
≤ 0.9
≤ 1.1
≤ 1.4
≤ 2.1
≤ 2.9
≤ 4.0
≤ 5.5
≤ 6.0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
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Maxim Integrated | 29
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
PCB Layout Guidelines
Careful circuit board layout is critical to achieve low switching power losses and clean, stable operation. Figure 5 shows
an example PCB top-metal layout for the WLP version device, and Figure 6 shows an example PCB top-metal layout for
the FC2QFN version of the device.
Follow these guidelines when designing the PCB:
1. Place the SUP capacitor immediately next to the SUP pin of the device. Since the device can operate up to 1.5MHz
switching frequency, this placement is critical for effective decoupling of high-frequency noise from the SUP pin.
2. Place the inductor and output capacitor close to the device and keep the loop area of switching current small.
3. Make the trace between LX and the inductor short and wide. Do not take up an excessive amount of area. The voltage
on this node switches very quickly and additional area creates more radiated emissions.
4. The trace between BST and C
should be as short as possible.
BST
5. Connect PGND and AGND together on the PCB. They must be the same net. Connect them together through a low-
impedance inner PCB ground layer close to the IC.
6. Keep the power traces and load connections short and wide. Use both top and inner PCB copper floods to reduce
trace impedance. This practice is essential for high-efficiency.
7. Place the V capacitor ground next to the AGND pin.
L
8. Do not neglect ceramic capacitor DC voltage derating. Choose capacitor values and sizes carefully. See the Output
Capacitor Selection section and refer to Application Note 5527: Temperature and Voltage Variation of Ceramic
Capacitors, or Why Your 4.7µF Capacitor Becomes a 0.33µF Capacitor for more information.
LX
L
OUT
1008 (2520)
C
SUP
SUP
BST
EN
LEGEND
0603
FPWM
POK
PGND
OUT
FB
R
SEL
C
VL
0402
R
BOT
V
AGND
L
AGND
SEL
VIAS
COMPONENT SIZES LISTED
IN IMPERIAL (METRIC)
● WAFER-LEVEL PACKAGE VERSION (WLP)
● POK PULLUP NOT DRAWN.
● CHOOSE C
CAREFULLY. SEE OUTPUT CAPACITOR SELECTION.
OUT
● CHOOSE PHYSICAL INDUCTOR CASE SIZE CAREFULLY. SEE INDUCTOR
SELECTION.
Figure 5. PCB Top-Metal and Component Layout Example (WLP Version)
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Maxim Integrated | 30
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
LX
L
OUT
1008 (2520)
C
SUP
SUP
LEGEND
0603
BST
EN
PGND
FPWM
POK
OUT
FB
0402
VIAS
R
BOT
R
C
VL
SEL
COMPONENT SIZES LISTED
IN IMPERIAL (METRIC)
V
AGND
L
SEL
AGND
● FLIP-CHIP QUAD FLAT NO-LEADS PACKAGE VERSION (FC2QFN)
● POK PULLUP NOT DRAWN.
● CHOOSE C
CAREFULLY. SEE OUTPUT CAPACITOR SELECTION.
OUT
● CHOOSE PHYSICAL INDUCTOR CASE SIZE CAREFULLY. SEE INDUCTOR
SELECTION.
Figure 6. PCB Top-Metal and Component Layout Example (FC2QFN Version)
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Maxim Integrated | 31
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Application Circuits
Typical Application Circuits
All output voltage use cases are configured to optimize load transient performance (±5% overshoot and undershoot at a
5A/μs slew rate) and phase margin of at least 45° across the entire input voltage range specified.
0.6V Output, 0.75MHz
C
0.22μF
BST
DC INPUT
2.6V TO 7.5V
SUP
BST
10V (0402)
C
SUP
10μF
L 1μH
25V (0603)
MAX77504
0.6V OUTPUT
MAX DC INPUT
DERATED
0.6V
3A MAX
OUT
LX
OUT
ENABLE
EN
C
OUT
4x 47μF
FPWM/SKIP/SYNC
FPWM/SYNC
SEL
6V (0603)
FB
R
1210Ω
(1% TOL)
SEL
BIAS
RSEL[1:0] = 0x09
= 0.75MHz
100kΩ
POWER-OK
f
SW
POK
V
L
R
COMP
= 75kΩ
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
0.82V Output, 0.75MHz
C
0.22μF
BST
DC INPUT
2.6V TO 10V
SUP
EN
BST
10V (0402)
C
10μF
SUP
L 1μH
25V (0603)
MAX77504
0.82V OUTPUT
MAX DC INPUT
DERATED
0.82V
OUT
LX
3A MAX
OUT
ENABLE
R
TOP
C
OUT
4x 47μF
C
15pF
FF
FPWM/SKIP/SYNC
FPWM/SYNC
SEL
4.07kΩ
6V (0603)
(0402)
FB
R
1210Ω
(1% TOL)
SEL
BIAS
R
BOT
11.1kΩ
RSEL[1:0] = 0x09
= 0.75MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 75kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
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Maxim Integrated | 32
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Application Circuits (continued)
1.0V Output, 0.75MHz
C
0.22μF
BST
DC INPUT
SUP
BST
10V (0402)
2.6V TO 13V
C
SUP
10μF
L 1μH
25V (0603)
MAX77504
1.0V
3A MAX
OUT
LX
1.0V OUTPUT
OUT
ENABLE
FPWM/SKIP/SYNC
EN
R
TOP
C
OUT
3x 47μF
C
15pF
FF
FPWM/SYNC
SEL
49.9kΩ
6V (0603)
(0402)
FB
R
SEL
2870Ω
BIAS
R
BOT
(1% TOL)
75kΩ
RSEL[1:0] = 0x0F
= 0.75MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 200kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
1.2V Output, 0.75MHz
C
0.22μF
BST
DC INPUT
2.6V TO 14V
SUP
EN
BST
10V (0402)
C
10μF
SUP
L 1μH
25V (0603)
MAX77504
1.2V
OUT
LX
1.2V OUTPUT
3A MAX
OUT
ENABLE
FPWM/SKIP/SYNC
R
TOP
C
OUT
3x 47μF
C
15pF
FF
FPWM/SYNC
SEL
49.9kΩ
6V (0603)
(0402)
FB
R
SEL
2870Ω
BIAS
R
BOT
(1% TOL)
49.9kΩ
RSEL[1:0] = 0x0F
= 0.75MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 200kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
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Maxim Integrated | 33
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Application Circuits (continued)
1.8V Output, 1MHz
C
0.22μF
BST
DC INPUT
SUP
BST
10V (0402)
2.6V TO 14V
C
SUP
10μF
L 1.5μH
25V (0603)
MAX77504
1.8V
3A MAX
OUT
LX
1.8V OUTPUT
OUT
ENABLE
FPWM/SKIP/SYNC
EN
R
TOP
C
OUT
3x 22μF
C
15pF
FF
FPWM/SYNC
SEL
46.4kΩ
10V (0603)
(0402)
FB
R
SEL
36.5kΩ
BIAS
R
BOT
(1% TOL)
23.2kΩ
RSEL[1:0] = 0x17
= 1MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 200kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
2.5V Output, 1.5MHz
C
0.22μF
BST
DC INPUT
2.6V TO 14V
SUP
EN
BST
10V (0402)
C
10μF
SUP
L 1.5μH
25V (0603)
MAX77504
2.5V
OUT
LX
2.5V OUTPUT
3A MAX
OUT
ENABLE
FPWM/SKIP/SYNC
R
TOP
C
OUT
3x 22μF
C
2.2pF
FF
FPWM/SYNC
SEL
73.2kΩ
10V (0603)
(0402)
FB
R
SEL
115kΩ
BIAS
R
BOT
(1% TOL)
23.2kΩ
RSEL[1:0] = 0x1F
= 1.5MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 200kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
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Maxim Integrated | 34
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Application Circuits (continued)
3.3V Output, 1.5MHz
C
0.22μF
BST
DC INPUT
SUP
BST
10V (0402)
2.6V TO 14V
C
SUP
10μF
L 1.5μH
25V (0603)
MAX77504
3.3V
3A MAX
OUT
LX
3.3V OUTPUT
OUT
ENABLE
FPWM/SKIP/SYNC
EN
R
TOP
C
OUT
3x 22μF
C
2.2pF
FF
FPWM/SYNC
SEL
49.9kΩ
10V (0603)
(0402)
FB
R
115kΩ
SEL
BIAS
R
BOT
(1% TOL)
11.1kΩ
RSEL[1:0] = 0x1F
= 1.5MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 200kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
5V Output, 1.5MHz
C
0.22μF
BST
DC INPUT
2.6V TO 14V
SUP
EN
BST
10V (0402)
C
10μF
SUP
L 2.2μH
25V (0603)
MAX77504
5V
OUT
LX
5V OUTPUT
3A MAX
OUT
ENABLE
FPWM/SKIP/SYNC
R
TOP
C
OUT
2x 22μF
C
2.2pF
FF
FPWM/SYNC
SEL
459kΩ
10V (0603)
(0402)
FB
R
SEL
86.6kΩ
BIAS
R
BOT
(1% TOL)
62.6kΩ
RSEL[1:0] = 0x1D
= 1.5MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 150kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
www.maximintegrated.com
Maxim Integrated | 35
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Typical Application Circuits (continued)
6V Output, 1.5MHz
C
0.22μF
BST
DC INPUT
SUP
BST
10V (0402)
2.6V TO 14V
C
SUP
10μF
L 2.2μH
25V (0603)
MAX77504
6V
3A MAX
OUT
LX
6V OUTPUT
OUT
ENABLE
FPWM/SKIP/SYNC
EN
R
TOP
C
2x 22μF
OUT
C
2.2pF
FF
FPWM/SYNC
SEL
252kΩ
10V (0603)
(0402)
FB
R
SEL
86.6kΩ
BIAS
R
BOT
(1% TOL)
28kΩ
RSEL[1:0] = 0x1D
= 1.5MHz
100kΩ
f
SW
POK
POWER-OK
V
L
R
= 150kΩ
COMP
C
2.2μF
VL
ACTIVE DISCHARGE ON
AGND
PGND
6V (0402)
Ordering Information
SOFT-START RAMP EXTERNAL CLOCK
PART NUMBER
PIN-PACKAGE
TIME (ms)
SYNC
Available
Unavailable
Available
MAX77504AAFC+T
MAX77504AAWE+T
MAX77504BAWE+T
1
1
1
12 FC2QFN
16 WLP
16 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
www.maximintegrated.com
Maxim Integrated | 36
MAX77504
14V Input, 3A High-Efficiency
Buck Converter in WLP or QFN
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
10/19
Initial release
Updated the Electrical Characteristics table, Bump/Pin Descriptions table, Configuration
Selection Resistor (SEL) section, Design Procedure (Choosing R ) section, Output
Capacitor Selection section, Setting the Output Voltage section, PCB Layout Guidelines
section, Figure 5, Typical Application Circuits section, and the Ordering Information table;
added FPWM/SYNC Clock Pulse Width Requirements section, Table 6, and Figure 6
—
9, 11, 18,
22–24, 26,
29–34, 36
SEL
1
2
3/20
7/20
Updated the Ordering Information table
36
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2020 Maxim Integrated Products, Inc.
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