MAX77650AEWVT [MAXIM]
Ultra-Low Power PMIC with 3-Output SIMO and Power Path Charger for Small Li;
| 型号： | MAX77650AEWVT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low Power PMIC with 3-Output SIMO and Power Path Charger for Small Li 集成电源管理电路 |
| 文件： | 总82页 (文件大小：2610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
General Description
Benefits and Features
● Highly Integrated
The MAX77650/MAX77651 provide highly-integrated bat-
tery charging and power supply solutions for low-power
wearable applications where size and efficiency are
critical. Both devices feature a SIMO buck-boost regulator
that provides three independently programmable power
rails from a single inductor to minimize total solution
size. A 150mA LDO provides ripple rejection for audio
and other noise-sensitive applications. A highly configu-
rable linear charger supports a wide range of Li+ battery
capacities and includes battery temperature monitoring
for additional safety (JEITA).
• Smart Power Selector™ Li+/Li-Poly Charger
• 3 Output, Single-Inductor Multiple-Output (SIMO)
Buck-Boost Regulator
• 150mA LDO
• 3-Channel Current Sink Driver
• Analog MUX Output for Power Monitoring
● Low Power
• 0.3μA Shutdown Current
• 5.6μA Operating Current (3 SIMO Channels +
LDO)
The devices include other features such as current sinks
for driving LED indicators and an analog multiplexer that
switches several internal voltage and current signals to an
external node for monitoring with an external ADC. A bidi-
● Charger Optimized for Small Battery Size
• Programmable Fast-Charge Current from 7.5mA to
300mA
• Programmable Battery Regulation Voltage from
3.6V to 4.6V
2
rectional I C interface allows for configuring and check-
ing the status of the devices. An internal on/off controller
provides a controlled startup sequence for the regulators
and provides supervisory functionality when the devices
are on. Numerous factory programmable options allow
the device to be tailored for many applications, enabling
faster time to market.
• Programmable Termination Current from 0.375mA
to 45mA
• JEITA Battery Temperature Monitors Adjust Charge
Current and Battery Regulation Voltage for Safe
Charging
● Flexible and Configurable
2
• I C Compatible Interface and GPIO
Simplified Application Circuit
• Factory OTP Options Available
IN_SBB
SYS
V
BUS
● Small Size
CHGIN
BATT
V
SYS
• 2.75mm x 2.15mm x 0.7mm WLP Package
• 30-Bump, 0.4mm-Pitch WLP, 6x5 Array
• Small Total Solution Size (19.2mm )
+
2
IN_LDO
SBB0
GND
2.05V
1.2V
3.3V
Applications
● Bluetooth Headphones/Hearables
● Fitness, Health, and Activity Monitors
● Portable Devices
TBIAS
THM
SBB1
SBB2
SYSTEM
RESOURCES
PGND
GPIO
1.5µH
● Internet of Things (IoT)
GPIO
1.85V
LXA
LXB
BST
VIO
LDO
Ordering Information appears at end of data sheet.
MAX77650
SYS
Smart Power Selector is a trademark of Maxim Integrated
Products, Inc.
LED0
LED1
LED2
VIO/Power
*
*
*
*
SDA
SCL
nRST
SDA
SCL
nRST
nIRQ
PWR_HLD
AMUX
PROCESSOR
ADC INPUT
nIRQ
PWR_HLD
AMUX
nEN
*PULLUP RESISTORS NOT DRAWN
19-8550; Rev 7; 9/18
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—Top Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—Global Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Characteristics—Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Characteristics—Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Characteristics—SIMO Buck-Boost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Characteristics—LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Electrical Characteristics—Current Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
Electrical Characteristics—I C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Support Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Global Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Features and Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Voltage Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SYS POR Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SYS Undervoltage Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
SYS Overvoltage Lockout Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
nEN Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
nEN Manual Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
nEN Dual-functionality: Push-Button vs. Slide-Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Interrupts (nIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Reset Output (nRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power Hold Input (PWR_HLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
General-Purpose Input Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
On/Off Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Flexible Power Sequencer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Debounced Inputs (nEN, GPI, CHGIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Maxim Integrated
│ 2
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(
)
TABLE OF CONTENTS CONTINUED
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Charger Symbol Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Smart Power Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Input Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Minimum Input Voltage Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Minimum System Voltage Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Die Temperature Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Charger State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Charger Off State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Prequalification State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Fast-Charge States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Top-Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Done State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Prequalification Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Fast-Charge Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Battery Temperature Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
JEITA-Modified States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Typical Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Charger Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Configuring a Valid System Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
CHGIN/SYS/BATT Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Thermistor Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Configurable Temperature Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Thermistor Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Using Different Thermistor β . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
NTC Thermistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Analog Multiplexer & Power Monitor AFEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Measuring Battery Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Method for Measuring Discharging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Method for Measuring Charging Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
SIMO Buck-Boost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
SIMO Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
SIMO Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SIMO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SIMO Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SIMO Active Discharge Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
SIMO Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
SIMO Available Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Maxim Integrated
│ 3
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
(
)
TABLE OF CONTENTS CONTINUED
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Input Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Boost Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
SIMO Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Unused Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
LDO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LDO Active Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LDO Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
LDO Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Input and Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Current Sinks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Current Sink Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LED Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Unused Current Sink Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2
I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2
I C System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2
I C Interface Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2
I C Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2
I C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
2
I C Acknowledge Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2
I C Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
2
I C Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
I C General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
I C Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
I C Communication Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
2
I C Communication Protocols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Writing to a Single Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Writing Multiple Bytes to Sequential Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reading from a Single Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Reading from Sequential Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Engaging HS-mode for operation up to 3.4MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Maxim Integrated
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
LIST OF FIGURES
Figure 1. Top-Level Interconnect Simplified Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 2. nEN Usage Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 3. GPIO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 4. Top-Level On/Off Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 5. Power-Up/Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 6. Flexible Power Sequencer Basic Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Startup Timing Diagram Due to nEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8. Startup Timing Diagram Due to Charge Source Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Debounced Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 10. Linear Charger Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 11. Charger Simplified Control Loops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 12. Charger State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 13. Example Battery Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 14. Thermistor Logic Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 15. Safe-Charging Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 16. Thermistor Bias State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. Thermistor Circuit with Adjusting Series and Parallel Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. SIMO Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. LDO Capacitance for Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 20. LDO Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 21. Current Sink Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 22. I2C Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 23. I2C System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 24. I2C Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25. Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 26. Slave Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 27. Writing to a Single Register with the Write Byte Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 28. Writing to Sequential registers X to N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 29. Reading from a Single Register with the Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 30. Reading Continuously from Sequential Registers X to N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 31. Engaging HS Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
LIST OF TABLES
Table 1. Regulator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 2. On/Off Controller Transition/State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 3. Charger Quick Symbol Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 4. Trip Temperatures vs. Trip Voltages for Different NTC β. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 5. Example R and R Correcting Values for NTC β Above 3380K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
S
P
Table 6. NTC Thermistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 7. AMUX Signal Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 8. Battery Current Direction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 9. SIMO Available Output Current for Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 10. Example Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2
Table 11. I C Slave Address Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Maxim Integrated
│ 6
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Absolute Maximum Ratings
nEN, PWR_HLD, nIRQ, nRST to GND.....-0.3V to V
+ 0.3V
IN_SBB to PGND.................................................-0.3V to +6.0V
SYS
SCL, SDA, GPIO to GND.............................-0.3V to V + 0.3V
LXA Continuous Current (Note 3) .................................1.2A
LXB Continuous Current (Note 4).................................1.2A
IO
RMS
RMS
CHGIN to GND...................................................-0.3V to +30.0V
SYS, BATT to GND ..............................................-0.3V to +6.0V
SYS to IN_SBB ....................................................-0.3V to +0.3V
SBB0, SBB1, SBB2 to PGND (Note 2)................-0.3V to +6.0V
BST to IN_SBB.....................................................-0.3V to +6.0V
BST to LXB...........................................................-0.3V to +6.0V
SBB0, SBB1, SBB2 Short-Circuit Duration...............Continuous
PGND to GND......................................................-0.3V to +0.3V
LGND to GND ......................................................-0.3V to +0.3V
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Continuous Power Dissipation (Multilayer Board)
V to GND ............................................................-0.3V to +6.0V
L
AMUX, THM, TBIAS to GND................................-0.3V to +6.0V
nIRQ, nRST, SDA, AMUX, GPIO Continous Current.......±20mA
CHGIN Continuous Current...........................................1.2A
SYS Continuous Current...............................................1.2A
BATT Continuous Current (Note 1)...............................1.2A
RMS
RMS
RMS
LDO to GND (Note 2)...........................-0.3V to V
+ 0.3V
IN_LDO
IN_LDO, V to GND ................................. -0.3V to the lower of
IO
(V
+ 0.3V) and +6.0V
SYS
LED0, LED1, LED2 to LGND...............................-0.3V to +6.0V
(T = +70°C, derate 20.4mW/°C above +70°C)........1632mW
A
Note 1: Do not repeatedly hot-plug a source to the BATT terminal at a rate greater than 10Hz. Hot plugging low-impedance sources
results in an ~8A momentary (~2µs) current spike.
Note 2: When the active discharge resistor is engaged, limit its power dissipation to an average of 10mW.
Note 3: LXA has internal clamping diodes to PGND and IN_SBB. It is normal for these diodes to briefly conduct during switching
events. Avoid steady-state conduction of these diodes.
Note 4: Do not externally bias LXB. LXB has an internal low-side clamping diode to PGND, and an internal high-side clamping
diode that dynamically shifts to the selected SIMO output. It is normal for these internal clamping diodes to briefly conduct
during switching events. When the SIMO regulator is disabled, the LXB to PGND absolute maximum voltage is -0.3V to
V
+ 0.3V.
SBB0
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE CHARACTERISTICS
Package Code
VALUES
W302H2+1
Outline Number
21-100047
Land Pattern Number
Refer to Application Note 1891
49°C/W (2s2p board)
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θ
)
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Package Information (continued)
Pin 1
Indicator
see Note 7
Marking
E
1
COMMON DIMENSIONS
A
0.05
0.03
0.64
0.19
A
A1
A2
0.45 REF
D
AAAA
A3
b
BASIC
0.040
0.27
0.03
0.025
0.025
BASIC
BASIC
D
2.148
2.748
E
D1
E1
TOP VIEW
SIDE VIEW
1.60
2.00
A3
e
0.40 BASIC
0.00 BASIC
0.20 BASIC
A1
SD
SE
S
A
A2
DEPOPULATED BUMPS:
NONE
0.05
S
FRONT VIEW
E1
SE
e
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
E
D
C
B
B
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
SD
D1
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
A
maxim
1
2
3
4
5
6
TM
integrated
A
b
TITLE
PACKAGE OUTLINE 30 BUMPS
S
AB
M
0.05
WLP PKG. 0.4 mm PITCH, W302H2+1
BOTTOM VIEW
REV.
DOCUMENT CO2NT1RO-L1N0O.0047
APPROVAL
1
- DRAWING NOT TO SCALE -
A
1
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Top Level
(V
= 0V, V
= V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over
CHGIN
SYS
BATT
IN_SBB
IN_LDO IO A
the operating temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage
Range
V
2.7
5.5
V
SYS
Main bias is off
(SBIA_EN = 0). This
is the standby state
0.3
1
1
Current measured
into BATT and SYS
and IN_SBB and
IN_LDO, all
Main bias is on in
low-power mode
(SBIA_EN = 1,
Shutdown Supply
Current
I
μA
SHDN
resources are off
(LDO, SBB0, SBB1, SBIA_LPM = 1)
SBB2, LED0, LED1,
LED2), T = 25°C
A
Main bias is on in
normal-power mode
(SBIA_EN = 1,
28
5.6
40
SBIA_LPM = 0)
Current measured
into BATT and SYS
and IN_SBB and
IN_LDO. LDO,
SBB0, SBB1, and
SBB2 are enabled
with no load. LED0,
LED1, and LED2
are disabled
Main bias is in
low-power mode
(SBIA_LPM = 1)
13
60
Quiescent Supply
Current
I
μA
Q
Main bias is in
normal-power mode
(SBIA_LPM = 0)
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Global Resources
(V
= 3.7V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to +85°C) are
SYS
A
A
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
POWER-ON RESET (POR)
POR Threshold
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
falling
1.6
1.9
2.1
V
POR
SYS
POR Threshold
Hysteresis
100
mV
UNDERVOLTAGE LOCKOUT (UVLO)
V
V
falling, UVLO_F[3:0] = 0xA
falling, UVLO_F[3:0] = 0xF
2.5
2.6
2.7
SYS
UVLO Threshold
V
V
SYSUVLO
2.75
2.85
2.95
SYS
UVLO Threshold
Hysteresis
V
UVLO_H[3:0] = 0x5
300
mV
SYSUVLO_HYS
OVERVOLTAGE LOCKOUT (OVLO)
OVLO Threshold
V
V
rising
5.70
5.85
6.00
V
SYSOVLO
SYS
THERMAL MONITORS
Overtemperature
Lockout Threshold
T
T rising
165
80
°C
°C
°C
°C
OTLO
J
Thermal Alarm
Temperature 1
T
T rising
J
JAL1
JAL2
Thermal Alarm
Temperature 2
T
T rising
100
15
J
Thermal Alarm
Temperature Hysteresis
ENABLE INPUT (nEN)
T = +25°C
-1
±0.001
±0.01
+1
A
nEN Input Leakage
Current
V
= 5.5V, V
=
SYS
nEN
I
μA
nEN_LKG
0V, and 5.5V
T = +85°C
A
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Global Resources (continued)
(V
= 3.7V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to +85°C) are
SYS
A
A
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
nEN Input Falling
Threshold
V
- 1.4
V
SYS
- 1.0
SYS
V
nEN falling
nEN falling
V
TH_nEN_F
nEN Input Rising
Threshold
V
V
SYS
- 0.6
SYS
V
V
TH_nEN_F
- 0.9
DBEN_nEN = 0
DBEN_nEN = 1
MRT_OTP = 0
MRT_OTP = 1
100
30
16
8
μs
Debounce Time
t
DBNC_nEN
ms
14
7
20
Manual Reset Time
t
s
MRST
10.5
POWER HOLD INPUT (PWR_HLD)
V
V
= V = 5.5V,
IO
SYS
T = +25°C
-1
±0.001
±0.01
+1
A
PWR_HLD Input
Leakage Current
I
= 0V,
μA
PWR_HLD_LKG
PWR_HLD
T = +85°C
and 5.5V
A
PWR_HLD Input
Voltage Low
0.3 x
V
V
V
V
= 1.8V
= 1.8V
= 1.8V
V
V
IL
IO
IO
IO
V
IO
PWR_HLD Input
Voltage High
0.7 x
V
IH
V
IO
PWR_HLD Input
Hysteresis
V
50
mV
HYS
PWR_HLD Glitch Filter
t
Both rising and falling edges are filtered
100
μs
PWR_HLD_GF
Maximum time for PWR_HLD input to assert
after nRST deasserts during the power-up
sequence
PWR_HLD Wait Time
t
3.5
4.0
5.0
0.4
s
PWR_HLD_WAIT
OPEN-DRAIN INTERRUPT OUTPUT (nIRQ)
Output Voltage Low
V
I
= 2mA
= 25pF
V
OL
SINK
Output Falling Edge
Time
t
C
2
ns
f_nIRQ
IRQ
V
= V = 5.5V,
IO
SYS
T = +25°C
-1
±0.001
+1
A
nIRQ set to be high
impedance (i.e., no
interrupts), VnIRQ =
0V and 5.5V
Leakage Current
I
μA
nIRQ_LKG
T = +85°C
±0.01
A
OPEN-DRAIN RESET OUTPUT (nRST)
Output Voltage Low
V
I
= 2mA
= 25pF
0.4
V
OL
SINK
Output Falling Edge
Time
t
C
2
ns
f_nRST
RST
nRST Deassert Delay
Time
See Figure 5 and Figure 7 for more
information
t
5.12
10.24
±0.001
ms
ms
RSTODD
nRST Assert Delay Time
t
See Figure 5 for more information
RSTOAD
V
= V = 5.5V,
IO
SYS
T = +25°C
-1
+1
A
nRST set to be high
Leakage Current
I
impedance (i.e., not
μA
nRST_LKG
reset), V
and 5.5V
= 0V
nRST
T = +85°C
±0.01
A
Maxim Integrated
│ 11
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Global Resources (continued)
(V
= 3.7V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to +85°C) are
SYS
A
A
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
0.3 x
Input Voltage Low
Input Voltage High
V
V
V
= 1.8V
= 1.8V
V
V
IL
IO
V
IO
0.7 x
V
IH
IO
V
IO
DIR = 1, V = 5.5V,
T = +25°C
-1
±0.001
±0.01
+1
IO
A
Input Leakage Current
I
V
= 0V and
μA
GPI_LKG
GPIO
T = +85°C
A
5.5V
Output Voltage Low
Output Voltage High
Input Debounce Time
V
I
= 2mA
0.4
V
V
OL
SINK
0.8 x
V
I
= 1mA
OH
SOURCE
V
IO
t
DBEN_GPI = 1
30
3
ms
ns
DBNC_GPI
Output Falling Edge
Time
t
C
= 25pF
= 25pF
f_GPIO
GPIO
GPIO
Output Rising Edge
Time
t
C
3
ns
r_GPIO
FLEXIBLE POWER SEQUENCER
Power-Up Event Periods
t
See Figure 6
See Figure 6
1.28
2.56
ms
ms
EN
Power-Down Event
Periods
t
DIS
Electrical Characteristics—Smart Power Selector Charger
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
DC INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHGIN Valid Voltage
Range
Initial CHGIN voltage before enabling
charging
V
4.10
7.25
V
V
CHGIN
CHGIN Standoff Voltage
Range
V
DC rising
DC rising
28
7.50
100
4.0
STANDOFF
CHGIN Overvoltage
Threshold
V
7.25
3.9
95
7.75
4.1
V
CHGIN_OVP
CHGIN Overvoltage
Hysteresis
mV
V
CHGIN Undervoltage
Lockout
V
DC rising
CHGIN_UVLO
CHGIN Undervoltage
Lockout Hysteresis
500
mV
mA
Input Current Limit
Range
V
= V
- 100mV, programmable
SYS
SYS-REG
I
475
CHGIN-LIM
in 95mA steps
Maxim Integrated
│ 12
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Smart Power Selector Charger (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
= 95mA, V = V
MIN
TYP
MAX
UNITS
Input Current Limit
Accuracy
I
-
SYS-REG
CHGIN-LIM
SYS
90
95
100
mA
100mV
V
falling due to loading conditions
CHGIN
Minimum Input Voltage
Regulation Range
and/or high-impedance charge source,
programmable in 100mV increments with
VCHGIN_MIN[2:0].
V
4.0
4.7
V
CHGIN-MIN
Minimum Input Voltage
Regulation Accuracy
V
= 4.5V (VCHGIN_MIN[2:0] =
CHGIN-MIN
4.32
100
4.50
120
4.68
140
V
0b101), I
reduced by 10%
CHGIN
Charger Input
Debounce Timer
V
= 5V, time before CHGIN is
CHGIN
t
ms
CHGIN-DB
allowed to deliver current to SYS or BATT
SUPPLY AND QUIESCENT CURRENTS
V
= 5V, charger is not in USB
CHGIN
BATT Bias Current
I
suspend (USBS = 0), charging is finished
5
μA
BATT-BIAS
(CHG_DTLS indicate done), I = 0mA
SYS
V
= 5V, charger is not in USB
CHGIN
suspend (USBS = 0), Charging is finished
1.0
1.8
mA
(CHG_DTLS indicate done), I = 0mA
CHGIN Supply Current
I
SYS
CHGIN
V
0A
= 0V to 1V, V
= 3.3V, I
=
CHGIN
BATT
SYS
50
50
μA
μA
CHGIN Suspend Supply
Current
V
= 5V, charger in USB suspend
CHGIN
I
CHGIN
(USBS = 1)
PREQUALIFICATIONS
Charge Current
Soft-Start Slew Time
Zero to full scale
Zero to full scale
1
1
ms
ms
Input Current
Soft-Start Slew Time
Charger is in prequalification mode when
V < V this threshold has 100mV of
BATT
hysteresis, programmable in 100mV steps
Prequalification Voltage
Threshold Range
PQ,
V
2.3
-3
3.0
+3
V
PQ
with CHG_PQ[2:0]
Prequalification Voltage
Threshold Accuracy
V
V
= 3.0V
%
PQ
= 2.5V, V
= 3.0V, expressed as a
, I_PQ = 0
BATT
PQ
10
20
30
percentage of I
Prequalification Mode
Charge Current
FAST-CHG
I
t
%
PQ
V
= 2.5V, V
= 3.0V, expressed as a
BATT
PQ
percentage of I
, I_PQ = 1
FAST-CHG
Prequalification Safety
Timer
V
< V
= 3.0V
27
33
minutes
PQ
BATT
PQ
Maxim Integrated
│ 13
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Smart Power Selector Charger (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
FAST CHARGE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast-Charge Voltage
Range
I
= 0mA, programmable in 25mV
BATT
V
3.6
4.6
+0.5
1.0
V
FAST-CHG
steps with CHG_CV[5:0]
I
= 0mA, V
= 4.3V, V
=
BATT
FAST-CHG
SYS
-0.5
±0.15
4.5V, T = +25°C
Fast-Charge Voltage
Accuracy
A
%
mA
%
I
= 0mA, V = 3.6V to 4.6V,
FAST-CHG
BATT
V
= 4.8V
SYS
Fast-Charge Current
Range
Programmable in 7.5mA steps with CHG_
CC[5:0]
I
7.5
-1.5
-1.5
300
+1.5
+1.5
FAST-CHG
I
= 15mA, T = 25°C, V
=
BATT
FAST-CHG
A
V
- 300mV
Fast-Charge Current
Accuracy
FAST-CHG
I
= 300mA, T = 25°C, V
A
=
FAST-CHG
BATT
V
- 300mV
FAST-CHG
Fast-Charge Current
Accuracy over
Temperature
Across all current settings, V
= V
FAST-
BATT
-10
+10
%
- 300mV
CHG
Programmable in 2 hour increments or
disabled with T_FAST_CHG[1:0], from
prequal done to timer fault
Fast-Charge Safety
Timer Range
t
3
7
hours
%
FC
Fast-Charge Safety
Timer Accuracy
t
= 3 hours
-10
+10
FC
Fast-charge CC mode, loading conditions
and/or a weak charging source caused
charge current to drop below this threshold,
Fast-Charge Safety
Timer Suspend
Threshold
20
%
°C
expressed as a percentage of I
FAST-CHG
Junction Temperature
Regulation Setting
Range
Programmable in 10°C steps with
TJ_REG[2:0]
T
60
100
J-REG
Rate at which I
/I
is reduced to
FAST-CHG PQ
Junction Temperature
Regulation Loop Gain
maintain T
, expressed a percentage
per degree centigrade
J-REG
/I
G
-5.4
%/°C
TJ-REG
of I
FAST-CHG PQ
rise
TERMINATION AND TOPOFF
I_TERM = 0b00 (expressed as a percentage
of I
5
)
FAST-CHG
I_TERM = 0b01 (expressed as a percentage
of I
7.5
10
15
)
End-of-Charge
Termination Current
FAST-CHG
I
%
TERM
I_TERM = 0b10 (expressed as a percentage
of I
)
FAST-CHG
I_TERM = 0b11 (expressed as a percentage
of I
)
FAST-CHG
Maxim Integrated
│ 14
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Smart Power Selector Charger (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
= 15mA, I
= 1.5mA (10%
FAST-CHG
TERM
1.35
1.5
1.65
of I
), T = +25°C
A
End-of-Charge Termina-
tion Current Accuracy
FAST-CHG
mA
I
= 300mA, I
= 30mA (10%
FAST-CHG
TERM
27
30
33
of I
), T = +25°C
A
FAST-CHG
I
< I
, programmable in 5 minute
BATT
TERM
Top-Off Timer Range
t
0
35
minutes
%
TO
steps with T_TOPOFF[2:0]
Top-Off Timer Accuracy
t
= 10 minutes
-10
+10
TO
CHG = 0 (charging done), charging re-
Charge Restart Thresh-
old
V
sumes when V
< V
- V
RE-
65
150
mV
RESTART
BATT
FAST-CHG
START
DEVICE ON-RESISTANCE AND LEAKAGE
BATT to SYS
On-Resistance
V
= 3.7V, I
= 300mA, V
=
BATT
BATT
CHGIN
100
0.1
1
mΩ
μA
0V, battery is discharging to SYS
V
= 4.5V, V = 0V, T = 25°C,
SYS
BATT
A
1.0
1.0
charger disabled
Charger FET Leakage
Current
V
= 4.5V, V
= 0V, T = 85°C,
A
SYS
BATT
charger disabled
CHGIN to SYS
On-Resistance
V
V
= 4.65V
600
0.1
1
mΩ
μA
CHGIN
= 0V, V
= 4.2V, T = +25°C,
A
CHGIN
SYS
body-switched diode reverse biased
Input FET Leakage
Current
V
= 0V, V = 4.2V, T = +85°C,
CHGIN
SYS
A
body-switched diode is reverse biased
SYSTEM NODE
System Voltage
Regulation Range
Programmable in 25mV steps with VSYS_
REG[4:0]
V
4.1
4.41
4.365
4.8
4.59
4.635
V
V
SYS-REG
V
V
= 4.5V, I
= 4.5V, I
= 1mA, T = +25°C
A
4.50
SYS-REG
SYS
System Voltage
Regulation Accuracy
V
= 1mA, T = -40°C
A
SYS
SYS-REG
SYS
4.500
to +85°C
V
V
= 5V, V
= 4.5V, V
<
(in-
CHGIN
SYS-REG
SYS
Minimum System
Voltage Regulation
Loop Setpoint
due to I
= I
SYS-REG
CHGIN
CHGIN-LIM
V
put in current-limit), battery charging, I
reduced to 50% of I
4.34
4.4
4.45
V
V
SYS-MIN
BATT
(minimum
FAST-CHG
system voltage regulation active)
Supplement Mode Sys-
tem Voltage Regulation
V
BATT
- 0.15V
I
= 150mA
SYS
Maxim Integrated
│ 15
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Adjustable Thermistor Temperature Monitors
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JEITA TEMPERATURE MONITORS
TBIAS Voltage
V
THM_EN = 1, V
= 5V
1.25
V
V
TBIAS
CHGIN
Voltage rising threshold, programmable
with THM_COLD[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Cold Threshold
Range
V
V
0.867
0.747
0.367
0.291
1.024
0.923
0.511
0.411
COLD
COOL
WARM
Voltage rising threshold, programmable
with THM_COOL[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Cool Threshold
Range
V
V
V
Voltage falling threshold, programmable
with THM_WARM[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Warm Threshold
Range
V
Voltage falling threshold, programmable
with THM_HOT[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Hot Threshold
Range
V
HOT
Temperature Threshold
Accuracy
Voltage threshold accuracy expressed as
temperature for an NTC β = 3380K
±3
3
°C
°C
V
Temperature Threshold
Hysteresis
Temperature hysteresis set on each volt-
age threshold for an NTC β = 3380K
JEITA Modified Fast-
Charge Voltage Range
V
I
= 0mA, programmable in 25mV
FAST-CHG_
JEITA
BATT
3.6
7.5
4.6
steps, battery is either cool or warm
JEITA Modified Fast-
Charge Current Range
I
Programmable in 7.5mA steps, battery is
either cool or warm
FAST-CHG_JEI-
TA
300
mA
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG MULTIPLEXER AND POWER MONITOR AFEs
Full-Scale Voltage
V
1.25
0.26
V
FS
SYS Voltage Monitor
Gain
V
corresponds to maximum V
FS
SYS-REG
G
V/V
VSYS
setting
CHGIN POWER
CHGIN Current Monitor
Gain
V
corresponds to maximum I
FS CHGIN-LIM
G
2.632
0.167
V/A
V/V
ICHGIN
setting
CHGIN Voltage Monitor
Gain
G
V
corresponds to V
CHGIN_OVP
VCHGIN
FS
BATT MONITOR
Battery Charge Current
Monitor Gain
V
corresponds to 100% of I
FAST-CHG
FS
G
12.5
mV/%
IBATT-CHG
setting (CHG_CC[5:0])
Maxim Integrated
│ 16
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Analog Multiplexer and Power Monitor AFEs (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
V
= 15mA, T = 25°C, V
A
=
FAST-CHG
BATT
-3.5
+3.5
- 300mV
Charge Current Monitor
Accuracy
FAST-CHG
%
I
V
= 300mA, T = +25°C, V
=
BATT
FAST-CHG
A
-3.5
-10
+3.5
+10
- 300mV
FAST-CHG
Charge Current Monitor
Accuracy over
Temperature
Across all current settings, V
= V
FAST-
BATT
%
mA
%
- 300mV
CHG
Battery Discharge
Monitor Full-Scale
Current Range
Programmable with IMON_DISCHG_
SCALE[3:0]
I
8.2
300
DISCHG-SCALE
Battery Discharge
Current Monitor
Accuracy
15mA to 300mA battery discharge current,
-15
+15
I
= 300mA
DISCHG-SCALE
Battery Discharge
Current Monitor Offset
I
= 0mA
-0.5
+0.65
mA
V/V
BATT
Battery Voltage Monitor
Gain
V
corresponds to maximum V
FS FAST-CHG
G
0.272
VBATT
setting
ANALOG MULTIPLEXER
Channel Switching Time
0.3
1
μs
nA
μA
T = +25°C
500
V
= 0V, AMUX
A
AMUX
Off Leakage Current
is high impedance
T = +85°C
1
A
THM AND TBIAS
THM Voltage Monitor
Gain
G
1
1
V/V
V/V
VTHM
TBIAS Voltage Monitor
Gain
G
VTBIAS
Maxim Integrated
│ 17
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—SIMO Buck-Boost
(V
= 3.7V, V
= 3.7V, C
= 10μF, L = 1.5μH, limits are 100% production tested at T = +25°C, limits over the operating
SYS
IN_SBB
SBBx A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT VOLTAGE RANGE (SBB0)
Minimum Output
Voltage
0.8
V
V
Maximum Output
Voltage
2.375
Output DAC Bits
6
bits
mV
Output DAC LSB Size
25
OUTPUT VOLTAGE RANGE (SBB1)
MAX77650
MAX77651
MAX77650
MAX77651
0.8
2.4
Minimum Output
Voltage
V
1.5875
5.25
6
Maximum Output
Voltage
V
Output DAC Bits
bits
mV
MAX77650
MAX77651
12.5
50
Output DAC LSB Size
OUTPUT VOLTAGE RANGE (SBB2)
MAX77650
MAX77651
MAX77650
MAX77651
0.8
2.4
3.95
5.25
6
Minimum Output
Voltage
V
V
Maximum Output
Voltage
Output DAC Bits
bits
mV
Output DAC LSB Size
OUTPUT VOLTAGE ACCURACY
50
V
falling,
SBBx
T
T
= +25°C
-2.5
-4.0
+2.5
+4.0
threshold where LXA
switches high. Speci-
fied as a percentage
of target output volt-
age (Note 3)
A
A
Output Voltage
Accuracy
%
= -40°C to
+85°C
TIMING CHARACTERISTICS
Delay time from the SIMO receiving its first
enable signal to when it begins to switch in
order to service that output.
Enable Delay
60
μs
Soft-Start Slew Rate
dV/dt
3.3
5.0
6.6
mV/μs
SS
Maxim Integrated
│ 18
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—SIMO Buck-Boost (continued)
(V
= 3.7V, V
= 3.7V, C
= 10μF, L = 1.5μH, limits are 100% production tested at T = +25°C, limits over the operating
SYS
IN_SBB
SBBx A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER STAGE CHARACTERISTICS
SBB0, SBB1, SBB2
are disabled,
T = +25°C
-1.0
±0.1
±1.0
+1.0
A
LXA Leakage Current
μA
V
V
= 5.5V,
= 0V, or 5.5V
IN_SBB
T = +85°C
A
LXA
SBB0, SBB1, SBB2
T = +25°C
-1.0
±0.1
±1.0
+1.0
A
are disabled, V
IN_
LXB Leakage Current
BST Leakage Current
= 5.5V, V
=
μA
μA
SBB
LXA
0V or 5.5V, all V
SBBx
T = +85°C
A
= 5.5V
V
V
V
= 5.5V,
= 5.5V,
= 11V
T = +25°C
A
+0.01
+0.1
+1.0
+1.0
IN_SBB
LXB
BST
T = +85°C
A
SBB0, SBB1, SBB2
are disabled, active-
discharge disabled
(ADE_SBBx = 0),
T = +25°C
+0.1
A
Disabled Output
Leakage Current
μA
V
V
V
= 5.5V,
SBBx
= 0V, V
=
=
LXB
SYS
BST
T = +85°C
+0.2
140
A
= V
IN_SBB
5.5V
Active Discharge
Impedance
SBB0, SBB1, SBB2 are disabled, active
discharge enabled (ADE_SBBx = 1)
R
80
260
Ω
AD_SBBx
CONTROL SCHEME
IP_SBBx = 0b11
IP_SBBx = 0b10
IP_SBBx = 0b01
IP_SBBx = 0b00
0.414
0.589
0.713
0.892
0.500
0.707
0.866
1.000
0.586
0.806
0.947
1.108
Peak Current Limit
(Note 4)
I
A
P_SBB
Note 3: Measured in an open-loop test that determines the output voltage falling threshold where LXA switches high.
Note 4: Typical values align with bench observations using the stated conditions. Minimum and maximum values are tested in pro-
duction with DC currents. See the Typical Operating Characteristics SIMO switching waveforms to gain more insight on this
specification.
Maxim Integrated
│ 19
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—LDO
(V
= 3.7V, V
= 2.05V, V
= 1.85V, C
= 10μF, limits are 100% production tested at T = +25°C, limits over the operating
SYS
IN_LDO
LDO
LDO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
IN_LDO cannot exceed SYS voltage
(Note 5)
Input Voltage
V
1.8
5.5
1
V
IN_LDO
Current measured into IN_LDO, LDO
output disabled (Note 6)
LDO Shutdown Current
I
I
0.1
1.7
μA
IN_LDO
LDO output enabled
and in regulation,
5.15
V
V
= 2.05V,
= 1.85V
IN_LDO
Current measured
into IN_LDO,
LDO Quiescent Supply
Current (Note 6)
LDO
μA
IN_LDO
LDO output enabled
and in dropout, V
I
= 0mA
LDO
IN_
LDO
2.3
= 1.8V, V
LDO
target is 1.85V
Maximum Output
Current
I
150
165
mA
mA
OUT
Current Limit
V
externally forced to 1.3V
255
375
LDO
OUTPUT VOLTAGE RANGE
Programmable with TV_LDO[6:0] in
12.5mV steps
Output Voltage Range
1.3500
2.9375
V
Output DAC Bits
7
bits
mV
Output DAC LSB Size
STATIC CHARACTERISTICS
12.5
Initial Output Voltage
Accuracy
I
= 75mA, T = +25°C
-2.5
-3
+2.5
+3
%
%
LDO
A
V
V
out, I
programmed from 1.35V to 2.9375V,
LDO
Output Voltage
Accuracy
= 1.8V to 5.5V, LDO not in drop-
IN_LDO
= 0mA to 150mA, T = -5°C to
A
LDO
+85°C
Main bias circuits
f = 10Hz to
100kHz, I
are in normal-power
mode (SBIA_LPM
= 0)
550
800
=
=
=
OUT
15mA, V
SYS
Output Noise
μV
RMS
3.7V, V
2.05V, V
1.85V
IN_LDO
Main bias circuits are
in low-power mode
(SBIA_LPM = 1)
=
LDO
Maxim Integrated
│ 20
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—LDO (continued)
(V
= 3.7V, V
= 2.05V, V
= 1.85V, C
= 10μF, limits are 100% production tested at T = +25°C, limits over the operating
SYS
IN_LDO
LDO
LDO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
TIMING CHARACTERISTICS
Enable Delay
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
T
= +25°C
0.6
1.25
2.50
ms
A
V
from 10% to 90% of final value.
LDO
= +25°C
Soft-Start Slew Rate
dV/dt
0.5
1.25
mV/μs
SS
T
A
POWER STAGE CHARACTERISTICS
V
= 3.7V, 1.85V programmed output
SYS
Dropout Voltage
V
voltage (TV_LDO[6:0] = 0x20), V
=
IN_LDO
90
180
mV
LDO_DO
1.8V, I
= 150mA (Note 5)
LDO
Active-Discharge
Impedance
Regulator disabled, active discharge
enabled (ADE_LDO = 1)
R
50
100
200
Ω
AD_LDO
Regulator disabled,
active discharge
disabled (ADE_
T = +25°C (Note 7)
+0.1
+1.0
A
Disabled Output
Leakage Current
LDO = 0), V
=
μA
SYS
V
V
= 5.5V,
= 5.5V and
IN_LDO
T = +85°C
+1.0
0.6
A
LDO
0V
V
= 3.7V,
SYS
1.85V programmed T = +25°C
output voltage
(TV_LDO[6:0] =
0.9
1.2
A
Dropout On-Resistance
R
Ω
DSON
0x20), V
=
IN_LDO
T = +85°C
A
1.8V, I
= I
MAX,
LDO
(Note 5)
Note 5: Dropout is the condition where the input voltage is in its valid input range but the output cannot be properly regulated
because the input voltage is not sufficiently higher than the output voltage. The dropout voltage is the difference between
the input voltage and the output voltage when the regulator is in dropout. The dropout on-resistance is the resistance of the
power MOSFET between the input and the output when the regulator is in dropout. Generally speaking, applications should
avoid dropout by having sufficient input voltage. A dropout detection interrupt is available (DOD_R; see the Programmer’s
Guide for more information). For example, applications with the output voltage target of 1.85V and the maximum load cur-
rent is 80mA (ILDO_MAX), has a dropout voltage of 96mV (V
= ILDO_MAX x RDSON_LDO = 80mA x 1.2Ω =
LDO_DO
96mV). To avoid dropout, the input voltage should be 1.95V (V
= V
+ V
).
IN_LDO
LDO
LDO_DO
Note 6: Guaranteed by design and characterization but not directly production tested. Production test coverage is provided by the
shutdown supply current and quiescent supply current specification in the Electrical Characteristics—Top Level table.
Note 7: Guaranteed by design and characterization but not directly production tested. The ability to disconnect the active discharge
resistance is functionally checked in a production test.
Maxim Integrated
│ 21
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Current Sinks
(V
= 3.7V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to +85°C) are
SYS
A
A
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GENERAL CHARACTERISTICS
Change in supply current at SYS when one
channel is enabled and delivering 12.8mA,
Current Sink Quiescent
Current
I
6
12
µA
Q
V
= 0.2V
LEDx
All current sink
drivers combined,
outputs disabled,
T
T
= +25ºC
= +85ºC
+0.1
+1.0
+1.0
A
Current Sink Leakage
µA
A
V
= 5.5V
LEDx
3.2mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b01, VLEDx = 0.2V)
Minimum Sink Current
Maximum Sink Current
Current Sink DAC Bits
Current Sink DAC LSB
BRT_LEDx[4:0] = 0b00000
BRT_LEDx[4:0] = 0b11111
0.1
3.2
5
mA
mA
bits
mA
0.1
3.20
3.20
35
T
T
= +25ºC
3.10
3.03
3.25
3.36
70
A
Current Sink Accuracy
mA
mV
= -40ºC to +85ºC
A
Dropout Voltage
V
BRT_LEDx[4:0] = 0b11111, I
= 2.9mA
DO
LEDx
6.4mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b10, VLEDx = 0.2V)
Minimum Sink Current
Maximum Sink Current
Current Sink DAC Bits
Current Sink DAC LSB
BRT_LEDx[4:0] = 0b00000
BRT_LEDx[4:0] = 0b11111
0.2
6.4
5
mA
mA
bits
mA
0.2
6.40
6.40
T
T
= +25ºC
6.30
6.06
6.50
6.72
A
Current Sink Accuracy
Dropout Voltage
mA
mV
= -40ºC to +85ºC
A
LED_FSx[1:0] = 0b11, BRT_LEDx[4:0] =
0b11111, I = 5.75mA
V
35
70
DO
LEDx
12.8mA CURRENT SINK RANGE (LED_FSx[1:0] = 0b11, VLEDx = 0.2V)
Minimum Sink Current
Maximum Sink Current
Current Sink DAC Bits
Current Sink DAC LSB
BRT_LEDx[4:0] = 0b00000
BRT_LEDx[4:0] = 0b11111
0.4
12.8
5
mA
mA
bits
mA
0.4
T
T
= +25ºC
12.6
12.8
12.80
35
13.0
13.44
70
A
Current Sink Accuracy
mA
mV
= -40ºC to +85ºC
12.16
A
Dropout Voltage
V
BRT_LEDx[4:0] = 0b11111, I
= 11.5mA
DO
LEDx
TIMING CHARACTERISTICS
Root Clock Frequency
25.6
32.0
38.4
Hz
Maxim Integrated
│ 22
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Electrical Characteristics—Current Sinks (continued)
(V
= 3.7V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to +85°C) are
SYS
A
A
guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS/BLINK PERIOD SETTINGS
0.5
16
s
Minimum Blink Period
clocks
s
8
Maximum Blink Period
256
0.5
16
clocks
s
Blink Period LSB
clocks
TIMING CHARACTERISTICS/BLINK DUTY CYCLE
Minimum Blink Duty Cycle
Maximum Blink Duty Cycle
Blink Duty Cycle LSB
D_LEDx[3:0] = 0b0000
D_LEDx[3:0] = 0b1111
6.25
100
%
%
%
6.25
2
Electrical Characteristics—I C Serial Interface
(V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to
SYS
IO A A
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
V
Voltage Range
V
1.7
-1
1.8
0
3.6
+1
+1
V
IO
IO
IH
V
= 3.6V, V
= V
= V
= 0V or 3.6V,
= 0V or 1.7V
IO
SDA
SCL
T = +25°C
V
Bias Current
μA
A
IO
V
= 1.7V, V
-1
0
IO
SDA
SCL
SDA AND SCL I/O STAGE
SCL, SDA Input High
Voltage
0.7 x
V
V
V
= 1.7V to 3.6V
= 1.7V to 3.6V
V
V
IO
V
IO
SCL, SDA Input Low
Voltage
0.3 x
V
IL
IO
V
IO
SCL, SDA Input
Hysteresis
0.05 x
V
V
HYS
V
IO
SCL, SDA Input
Leakage Current
I
V
= 3.6V, V
= V
= 0V and 3.6V
-10
+10
0.4
μA
V
I
IO
SCL
SDA
SDA Output Low
Voltage
V
Sinking 20mA
OL
SCL, SDA Pin
Capacitance
C
10
pF
ns
I
Output Fall Time from
t
120
OF
V
to V (Note 2)
IL
IH
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│ 23
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
2
Electrical Characteristics—I C (continued)
(V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to
SYS
IO A A
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C-COMPATIBLE INTERFACE TIMING (STANDARD, FAST AND FAST MODE PLUS) (Note 8)
Clock Frequency
f
0
1000
kHz
SCL
Hold Time (REPEATED)
START Condition
t
0.26
μs
HD;STA
SCL Low Period
SCL High Period
t
0.5
μs
μs
LOW
t
0.26
HIGH
Setup Time REPEATED
START Condition
t
0.26
μs
SU_STA
Data Hold Time
Data Setup Time
t
0
μs
HD_DAT
t
50
ns
SU_DAT
Setup Time for STOP
Condition
t
0.26
μs
μs
ns
SU_STO
Bus Free Time between
STOP and START
Condition
t
0.5
BUF
Pulse Width of Sup-
pressed Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
50
SP
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, C = 100pF) (Note 8)
B
Clock Frequency
f
3.4
MHz
ns
SCL
Setup Time REPEATED
START Condition
t
160
160
SU_STA
Hold Time (REPEATED)
START Condition
t
ns
HD_STA
SCL Low Period
SCL High Period
Data Setup Time
Data Hold Time
SCL Rise Time
t
160
60
10
0
ns
ns
ns
ns
ns
LOW
t
HIGH
t
SU_DAT
HD_DAT
t
70
40
t
T
T
= +25°C
= +25°C
10
rCL
A
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
t
10
80
ns
rCL1
A
SCL Fall Time
SDA Rise Time
SDA Fall Time
t
T
T
T
= +25°C
= +25°C
= +25°C
10
10
10
40
80
80
ns
ns
ns
fCL
A
A
A
t
rDA
t
fDA
Setup Time for STOP
Condition
t
160
ns
pF
ns
SU_STO
Bus Capacitance
C
100
B
Pulse Width of Sup-
pressed Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
10
SP
Maxim Integrated
│ 24
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
2
Electrical Characteristics—I C (continued)
(V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to
SYS
IO A A
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C-COMPATIBLE INTERFACE TIMING (HIGH-SPEED MODE, C = 400pF) (Note 8)
B
Clock Frequency
f
1.7
MHz
ns
SCL
Setup Time REPEATED
START Condition
t
160
160
SU_STA
Hold Time (REPEATED)
START Condition
t
ns
HD_STA
SCL Low Period
SCL High Period
Data Setup Time
Data Hold Time
SCL Rise Time
t
320
120
10
0
ns
ns
ns
ns
ns
LOW
t
HIGH
t
SU_DAT
HD_DAT
t
150
80
t
T
T
= +25°C
= +25°C
20
RCL
A
Rise Time of SCL
Signal after REPEATED
START Condition and
after Acknowledge Bit
t
20
80
ns
RCL1
A
SCL Fall Time
SDA Rise Time
SDA Fall Time
t
T
T
T
= +25°C
= +25°C
= +25°C
20
20
20
80
ns
ns
ns
FCL
A
A
A
t
160
160
RDA
t
FDA
Setup Time for STOP
Condition
t
160
ns
pF
ns
SU_STO
Bus Capacitance
C
400
B
Pulse Width of
Suppressed Spikes
Maximum pulse width of spikes that must
be suppressed by the input filter
t
10
SP
Note 8: Design guidance only. Not production tested.
Maxim Integrated
│ 25
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, T = +25°C, unless otherwise noted.)
CHGIN
SYS
IN_SBB
BATT IO A
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. BATTERY VOLTAGE
toc03
toc01
toc02
6
5
4
3
2
1
0
6
60
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS OFF (SBIA_EN = 0)
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
LDO, SIMO, LED'S ARE DISABLED
MAIN-BIAS ON (SBIA_EN = 1)
NORMAL-POWER MODE (SBIA_LPM = 0)
5
4
3
2
1
0
50
TA = +85°C
40 TA = +25°C
TA = -40°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +85°C
TA = +25°C
TA = -40°C
30
20
10
0
2.5
3.5
4.5
VBATT (V)
5.5
2.5
3.5
4.5
VBATT (V)
5.5
2.5
3.5
4.5
VBATT (V)
5.5
QUIESCENT SUPPLY CURRENT
vs. BATTERY VOLTAGE
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
toc04
toc05
10
9
8
7
6
5
4
3
2
1
0
10
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
MAIN-BIAS ON (SBIA_EN = 1)
LOW-POWER MODE (SBIA_LPM = 1)
9
8
7
6
5
4
3
2
1
0
SBB0, SBB1, SBB2, LDO ENABLED
SBB0, SBB1, SBB2, LDO ENABLED
SBB0, SBB1, SBB2 ENABLED
SBB0, SBB1 ENABLED
SBB0, SBB1, SBB2 ENABLED
SBB0, SBB1 ENABLED
SBB0 ENABLED
SBB0 ENABLED
2.5
3.5
4.5
VBATT (V)
5.5
-40
-15
10
35
60
85
TEMPERATURE (°C)
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER PEAK CURRENT LIMIT)
SBB2 EFFICIENCY vs. OUTPUT CURRENT
(VSBB2 = 3.3V, PER PEAK CURRENT LIMIT)
toc07
toc06
3.50
3.45
3.40
3.35
3.30
3.25
3.20
88
86
84
82
80
78
76
74
72
70
DRV_SBB = 0, VIN_SBB = 3.7V
IP_SBB2 = 1000mA
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
CSBB2_EFFECTIVE = 3µF
IP_SBB2 = 866mA
IP_SBB2 = 700mA
IP_SBB2 = 500mA
IP_SBB2 = 500mA
IP_SBB2 = 700mA
IP_SBB2 = 866mA
IP_SBB2 = 1000mA
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Maxim Integrated
│ 26
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
CHGIN
SYS
IN_SBB
BATT IO
127mΩ, 2.0mm x 1.2mm x 1.0mm), T = +25°C, unless otherwise noted.)
A
SBB0 EFFICIENCY vs. OUTPUT CURRENT
SBB0 LOAD REGULATION
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 2.05V, PER PEAK CURRENT LIMIT)
(VSBB0 = 2.05V, PER PEAK CURRENT LIMIT)
(VSBB1 = 1.2V, PER PEAK CURRENT LIMIT)
toc08
toc09
toc10
88
86
84
82
80
78
76
74
72
70
2.25
2.20
2.15
2.10
2.05
2.00
1.95
88
86
84
82
80
78
76
74
72
70
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB0_EFFECTIVE = 5µF
DRV_SBB = 0, VIN_SBB = 3.7V
DRV_SBB = 0, VIN_SBB = 3.7V
IP_SBB1 = 500mA
IP_SBB1 = 700mA
IP_SBB1 = 866mA
CSBB0_EFFECTIVE = 5µF
CSBB1_EFFECTIVE = 8µF
IP_SBB0 = 1000mA
IP_SBB0 = 866mA
IP_SBB0 = 700mA
IP_SBB0 = 500mA
IP_SBB1 = 1000mA
IP_SBB0 = 500mA
IP_SBB0 = 700mA
IP_SBB0 = 866mA
IP_SBB0 = 1000mA
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB2 EFFICIENCY
vs. OUTPUT CURRENT
(VSBB2 = 3.3V, PER DRIVE STRENGTH)
SBB1 LOAD REGULATION
(VSBB1 = 1.2V, PER PEAK CURRENT LIMIT)
toc11
toc12
1.24
1.23
1.22
1.21
1.20
1.19
1.18
88
86
84
82
80
78
76
74
DRV_SBB = 0, VIN_SBB = 3.7V
CSBB1_EFFECTIVE = 8µF
IP_SBB2 = 3, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
IP_SBB1 = 1000mA
IP_SBB1 = 866mA
IP_SBB1 = 700mA
IP_SBB1 = 500mA
DRV_SBB = 0
DRV_SBB = 1
72 DRV_SBB = 2
DRV_SBB = 3
70
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
CHGIN SUPPLY CURRENT vs.
CHGIN VOLTAGE
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER DRIVE STRENGTH)
(USB SUSPENDED)
toc13
toc14
3.38
3.36
3.34
3.32
3.30
3.28
3.26
100
90
80
70
60
50
40
30
20
10
0
VCHGIN RISING
IP_SBB2 = 3, VIN_SBB = 3.7V
CSBB2_EFFECTIVE = 3µF
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
0.1
1
10
100
1000
3.5
4.0
4.5
5.0
5.5
6.0
OUTPUT CURRENT (mA)
VCHGIN (V)
Maxim Integrated
│ 27
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
CHGIN
SYS
IN_SBB
BATT IO
127mΩ, 2.0mm x 1.2mm x 1.0mm), T = +25°C, unless otherwise noted.)
A
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER DRIVE STRENGTH)
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER DRIVE STRENGTH)
CHARGE PROFILE, 40mAh BATTERY
toc15
toc16
toc17
2.09
2.08
2.07
2.06
2.05
2.04
2.03
88
86
84
82
80
78
76
74
72
70
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.060
0.054
0.048
0.042
0.036
0.030
0.024
0.018
0.012
0.006
0.000
IP_SBB0 = 3, VIN_SBB = 3.7V
CSBB0_EFFECTIVE = 5µF
IP_SBB1 = 3, VIN_SBB = 3.7V
CSBB1_EFFECTIVE = 8µF
VPQ = 3V, IPQ = 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
DRV_SBB = 0
DRV_SBB = 1
DRV_SBB = 2
DRV_SBB = 3
VBATT (V)
IBATT (A)
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BEHAVIOR
0.1
1
10
100
1000
0.1
1
10
100
1000
0.0
1.0
2.0
3.0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
TIME (hr)
SBB2 LOAD REGULATION
(VSBB2 = 3.3V, PER INPUT VOLTAGE)
CHARGE PROFILE, 110mAh BATTERY
toc18
toc19
3.38
3.36
3.34
3.32
3.30
3.28
3.26
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.150
0.135
0.120
0.105
0.090
0.075
0.060
0.045
0.030
0.015
0.000
DRV_SBB=0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 3µF
VPQ = 3V, IPQ = 10%
IFAST-CHG = 75mA, VFAST-CHG = 4.2V
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
VBATT (V)
IBATT (A)
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BEHAVIOR
0.1
1
10
100
1000
0.0
1.0
2.0
TIME (hr)
3.0
OUTPUT CURRENT (mA)
SBB2 EFFICIENCY vs. OUTPUT CURRENT
SBB2 LOAD REGULATION
(VSBB2 = 2.5V, PER INPUT VOLTAGE)
(VSBB2 = 2.5V, PER INPUT VOLTAGE)
toc20
toc21
88
2.58
2.56
2.54
2.52
2.50
2.48
2.46
DRV_SBB = 0, IP_SBB2 = 3
DRV_SBB = 0, IP_SBB2 = 3
CSBB2_EFFECTIVE = 5µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
86 CSBB2_EFFECTIVE = 5µF
84
82
80
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 5.0V
VIN_SBB = 3.3V
VIN_SBB = 5.5V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
78
76
74
72
70
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Maxim Integrated
│
28
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
CHGIN
SYS
IN_SBB
BATT
IO
127mΩ, 2.0mm x 1.2mm x 1.0mm), T = +25°C, unless otherwise noted.)
A
SBB0 EFFICIENCY vs. OUTPUT CURRENT
(VSBB0 = 2.05V, PER INPUT VOLTAGE)
SBB0 LOAD REGULATION
(VSBB0 = 2.05V, PER INPUT VOLTAGE)
toc22
88
toc23
2.09
DRV_SBB = 0, IP_SBB0 = 3
86 CSBB0_EFFECTIVE = 5µF
DRV_SBB = 0, IP_SBB0 = 3
VIN_SBB = 5.5V
CSBB0_EFFECTIVE = 5µF
VIN_SBB = 5.0V
2.08
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 3.0V
84
82
2.07
80
VIN_SBB = 2.8V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
2.06
78
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
76
74
72
70
2.05
2.04
2.03
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB0 EFFICIENCY vs. OUTPUT CURRENT
SBB0 LOAD REGULATION
(VSBB0 = 1.85V, PER INPUT VOLTAGE)
(VSBB0 = 1.85V, PER INPUT VOLTAGE)
toc24
toc25
88
1.89
1.88
1.87
1.86
1.85
1.84
1.83
DRV_SBB = 0, IP_SBB0 = 3
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 5µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
86 CSBB0_EFFECTIVE = 5µF
84
82
80
VIN_SBB = 3.7V
78
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
76
74
72
70
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB0 EFFICIENCY vs. OUTPUT CURRENT
SBB0 LOAD REGULATION
(VSBB0 = 1.5V, PER INPUT VOLTAGE)
(VSBB0 = 1.5V, PER INPUT VOLTAGE)
toc26
toc27
88
1.54
1.53
1.52
1.51
1.50
1.49
1.48
DRV_SBB = 0, IP_SBB0 = 3
DRV_SBB = 0, IP_SBB0 = 3
CSBB0_EFFECTIVE = 6µF
VIN_SBB = 5.5V
86 CSBB0_EFFECTIVE = 6µF
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
84
82
80
78
76
74
72
70
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Maxim Integrated
│ 29
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 2.2µF (TOKO DFE201210S-2R2M,
CHGIN
SYS
IN_SBB
BATT
IO
127mΩ, 2.0mm x 1.2mm x 1.0mm), T = +25°C, unless otherwise noted.)
A
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 1.2V, PER INPUT VOLTAGE)
SBB1 LOAD REGULATION
(VSBB1 = 1.2V, PER INPUT VOLTAGE)
toc28
toc29
88
1.24
DRV_SBB = 0, IP_SBB1 = 3
VIN_SBB = 5.5V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
86
84
82
80
78
76
74
72
70
CSBB1_EFFECTIVE = 8µF
VIN_SBB = 5.0V
1.23
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
1.22
1.21
1.20
1.19
1.18
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB1 EFFICIENCY vs. OUTPUT CURRENT
SBB1 LOAD REGULATION
(VSBB1 = 1.0V, PER INPUT VOLTAGE)
(VSBB1 = 1.0V, PER INPUT VOLTAGE)
toc30
toc31
88
86
84
82
80
78
76
74
72
70
1.04
1.03
1.02
1.01
1.00
0.99
0.98
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 8µF
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SBB1 LOAD REGULATION
(VSBB1 = 0.8V, PER INPUT VOLTAGE)
SBB1 EFFICIENCY vs. OUTPUT CURRENT
(VSBB1 = 0.8V, PER INPUT VOLTAGE)
toc32
toc33
88
0.84
0.83
0.82
0.81
0.80
0.79
0.78
DRV_SBB = 0, IP_SBB1 = 3
VIN_SBB = 3.7V
DRV_SBB = 0, IP_SBB1 = 3
CSBB1_EFFECTIVE = 9µF
VIN_SBB = 5.5V
VIN_SBB = 5.0V
VIN_SBB = 4.2V
VIN_SBB = 3.7V
VIN_SBB = 3.3V
VIN_SBB = 2.8V
86 CSBB1_EFFECTIVE = 9µF
VIN_SBB = 3.3V
VIN_SBB = 4.2V
VIN_SBB = 3.0V
VIN_SBB = 2.8V
VIN_SBB = 5.0V
VIN_SBB = 5.5V
84
82
80
78
76
74
72
70
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Maxim Integrated
│ 30
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 1.5µF, T = +25°C, unless otherwise noted.)
CHGIN
SYS
IN_SBB
BATT
IO
A
SIMO LINE TRANSIENT
SBB2 LOAD TRANSIENT
toc34
toc35
3.3V CSBB2_EFF =6µF
ISBB0 = ISBB1 = ISBB2 = 10mA
L=2.2µH
4.2V
VSBB2
50mV/div
3.2V
VIN_SBB
1V/div
IP_SBBx SET TO 500mA
LOW-POWER MODE
IP_SBB2 = 866mA,VSBB2 = 3.3V, CSBB2_EFF =6µF
IP_SBB1 = 500mA,VSBB1 = 1.2V, CSBB1_EFF =8µF
IP_SBB0 = 707mA,VSBB0 = 2.05V, CSBB0_EFF = 5µF
1.2V
CSBB1_EFF =8µF
CSBB0_EFF =5µF
ISBB1 = 10mA
ISBB0 = 10mA
VSBB1
VSBB0
50mV/div
50mV/div
2.05V
VSBB2
VSBB1
VSBB0
50mV/div
50mV/div
50mV/div
80mA
10mA
ISBB2
100mA/div
40µs/div
10µs/div
SBB1 LOAD TRANSIENT
SBB0 LOAD TRANSIENT
toc36
toc37
3.3V
3.3V
CSBB2_EFF =6µF
CSBB2_EFF =6µF
ISBB2 = 10mA
ISBB2 = 10mA
VSBB2
VSBB2
50mV/div
50mV/div
IP_SBBx SET TO 500mA
LOW-POWER MODE
IP_SBBx SET TO 500mA
LOW-POWER MODE
ISBB1 = 10mA
CSBB1_EFF =8µF
1.2V
1.2V CSBB1_EFF =8µF
VSBB1
VSBB0
VSBB1
VSBB0
50mV/div
50mV/div
50mV/div
50mV/div
ISBB0 = 10mA
2.05V
CSBB0_EFF =5µF
CSBB0_EFF =5µF
2.05V
100mA
100mA
10mA
10mA
ISBB0
ISBB1
100mA/div
100mA/div
40µs/div
40µs/div
SIMO SWITCHING WAVEFORMS
HEAVY UTILIZATION 75mA PER CHANNEL
SIMO SWITCHING WAVEFORMS
MEDIUM UTILIZATION 25mA PER CHANNEL
SIMO SWITCHING WAVEFORMS
LIGHT UTILIZATION 10mA PER CHANNEL
toc39
toc40
toc38
IL
IL
VSBB2
VSBB1
VSBB0
500mA/div
500mA/div
50mV/div
IL
500mA/div
IP_SBB2 = 1000mA,VSBB2= 3.3V, CSBB2_EFF =3µF
IP_SBB2 = 866mA,VSBB2= 3.3V, CSBB2_EFF =3µF
IP_SBB2 = 500mA,VSBB2= 3.3V, CSBB2_EFF =3µF
VSBB2
VSBB1
VSBB0
IP_SBB1 = 1000mA,VSBB1= 1.2V, CSBB1_EFF =8µF
IP_SBB2 = 1000mA,VSBB0= 2.05V, CSBB0_EFF =5µF
VSBB2
VSBB1
VSBB0
50mV/div
50mV/div
50mV/div
50mV/div
50mV/div
50mV/div
50mV/div
50mV/div
IP_SBB1 = 500mA,VSBB1= 1.2V, CSBB1_EFF =8µF
IP_SBB2 = 500mA,VSBB0= 2.05V, CSBB0_EFF =5µF
IP_SBB1 = 500mA,VSBB1= 1.2V, CSBB1_EFF =8µF
IP_SBB2 = 707mA,VSBB0= 2.05V, CSBB0_EFF =5µF
4µs/div
4µs/div
4µs/div
Maxim Integrated
│ 31
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 1.5µF, T = +25°C, unless otherwise noted.)
CHGIN
SYS
IN_SBB
BATT
IO
A
LDO LINE REGULATION
LDO LOAD REGULATION
LDO LINE TRANSIENT
toc43
toc41
toc42
1.95
1.93
1.91
1.89
1.87
1.85
1.83
1.81
1.79
1.77
1.75
1.95
NO LOAD
VLDO TARGET VOLTAGE = 1.85V
TA= +85°C
TA= +25°C
TA= -20°C
1.93
1.91
1.89
1.87
1.85
1.83
1.81
1.79
1.77
1.75
3.0 VIN_LDO
4.2 VIN_LDO
5.5 VIN_LDO
2.35V
2.05V
VIN_LDO
200mV/div
1mV/div
VLDO
0.000 0.025 0.050 0.075 0.100 0.125 0.150
3.0
4.0
5.0
6.0
200µs/div
ILDO (A)
VIN_LDO (V)
LDO LOAD TRANSIENT
LDO LOAD TRANSIENT
toc45
toc44
1.85V
1.85V
VLDO
VLDO
50mV/div
50mV/div
135mA
80mA
15mA
5mA
ILDO
50mV/div
ILDO
50mV/div
100µs/div
100µs/div
LDO POWER-SUPPLY
REJECTION RATIO
LDO LOAD TRANSIENT
toc46
toc47
60
50
40
30
20
10
VIN_LDO AVERAGE = 2.05V
V
AVERAGE = 1.85V
LOAD = 15mA
LDO
1.85V
VLDO
50mV/div
150mA
2mA
ILDO
50mV/div
0
100µs/div
0.1
1
10
100
1000
INPUT FREQUENCY (kHz)
Maxim Integrated
│ 32
www.maximintegrated.com
MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 1.5µF, T = +25°C, unless otherwise noted.)
CHGIN
SYS
IN_SBB
BATT
IO
A
CHGIN SUPPLY CURRENT
vs. CHGIN VOLTAGE
CHGIN SUPPLY CURRENT
vs. CHGIN VOLTAGE
toc49
toc48
100
90
80
70
60
50
40
30
20
10
0
1.8
VCHGIN RISING
USB SUSPENDED
ISYS = 0mA
VCHGIN RISING
VBATT = 2.7V
VBATT = 3.6V
VBATT = 4.4V
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.5
4.0
4.5
5.0
5.5
6.0
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
VCHGIN (V)
VCHGIN (V)
SYS TO BATT IMPEDANCE
BATT BIAS CURRENT vs. BATT
toc50
toc51
10
9
8
7
6
5
4
3
2
1
0
0.16
0.15
0.14
0.13
0.12
0.11
0.10
0.09
0.08
CHARGER DISABLED
VCHGIN = 5V
TA = +85°C
TA = +25°C
TA = -40°C
IBATT = 10mA
IBATT = 100mA
IBATT = 300mA
2.5
3.0
3.5
4.0
4.5
2.5
3.0
3.5
4.0
4.5
5.0
VBATT (V)
VBATT (V)
SYS LOAD TRANSIENT
CAUSING BATTERY SUPPLEMENT
CHARGE PROFILE, 40mAh BATTERY
CHARGE PROFILE, 110mAh BATTERY
toc54
toc52
toc53
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0.000
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
2.7
2.5
0.150
VPQ = 3V, IPQ = 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
VPQ = 3V, IPQ = 10%
IFAST-CHG = 90mA, VFAST-CHG = 4.2V
125mA
ICHGIN_LIM = 95mA
0.135
0.120
0.105
0.090
0.075
0.060
0.045
0.030
0.015
0.000
ICHGIN = 30mA
VSYS_REG = 4.5V
VBATT (V)
0mA
VBATT (V)
ISYS
100mA/div
100mA/div
IBATT (A)
95mA
30mA
IBATT (A)
ICHGIN
0mA
0mA
30mA DISCHARGING
BATTERY
LOADED DURING
THE "DONE"
STATE TO SHOW
THE RESTART
BEHAVIOR
IBATT
100mA/div
1V/div
30mA CHARGING
3.7V
4.5V
VSYS
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
1ms/div
TIME (hr)
TIME (hr)
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Operating Characteristics (continued)
(Typical Application Circuit, V
= 0V, V
= V
= 3.7V, V
= 3.7V, V = 1.8V, L = 1.5µF, T = +25°C, unless otherwise noted.)
CHGIN
SYS
IN_SBB
BATT
IO
A
POWER UP
NO LOAD
POWER DOWN
NO LOAD
toc55
toc56
VSBB2
VSBB2
1V/div
1V/div
VSBB0
VSBB1
VSBB0
VLDO
1V/div
1V/div
1V/div
2V/div
1V/div
1V/div
VSBB1
VnRST
VLDO
1V/div
2V/div
VnRST
IBATT
IBATT
50mA/div
50mA/div
2ms/div
4ms/div
POWER DOWN
POWER UP
10mA LOAD PER CHANNEL
10mA LOAD PER CHANNEL
toc57
toc58
VSBB2
VSBB2
1V/div
1V/div
VSBB0
VSBB0
VSBB1
1V/div
1V/div
1V/div
1V/div
VSBB1
VnRST
VLDO
VLDO
1V/div
2V/div
1V/div
2V/div
VnRST
IBATT
50mA/div
50mA/div
IBATT
2ms/div
4ms/div
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
6
+
PWR_
HLD
nEN
nRST
nIRQ
SDA
LGND
GND
LED2
SCL
LED1
LDO
BST
LED0
IN_LDO
SBB0
A
B
GPIO
C
AMUX
V
IO
D
THM
SYS
TBIAS
BATT
LXA
LXB
SBB1
SBB2
V
L
CHGIN
IN_SBB PGND
E
WLP
(2.75mm x 2.15mm)
Bump Description
PIN
NAME
FUNCTION
TYPE
TOP LEVEL
Active-Low Enable Input. nEN supports push-button or slide-switch configurations. An external
pullup resistor (10kΩ to 100kΩ) to SYS is required.
A2
nEN
digital input
digital output
digital output
Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between nIRQ and a
C2
B2
nIRQ
nRST
voltage equal to or less than V
.
SYS
Active-Low, Open-Drain Reset Output. Connect a 100kΩ pullup resistor between nRST and a
voltage equal to or less than V
.
SYS
Active-High Power Hold Input. Assert PWR_HLD to keep the on/off controller in its on through
A1
PWR_HLD on/off controller state. If PWR_HLD is not needed, connect it to SYS and use the SFT_RST bits digital input
to power down the device.
B1
C4
B4
A3
GPIO
General-Purpose Input/Output. The GPIO I/O stage is internally biased with V
.
digital I/O
power input
digital input
digital I/O
IO
2
V
I C Interface and GPIO Driver Power
IO
2
SCL
SDA
I C Clock
2
I C Data
Quiet Ground. Connect GND to PGND, LGND, and the low-impedance ground plane of the
PCB.
C3
GND
ground
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Ultra-Low Power PMIC with 3-Output SIMO
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Bump Description (continued)
PIN
NAME
FUNCTION
TYPE
CHARGER
E1
CHGIN
SYS
Charger Input. Connect to a DC charging source. Bypass to GND with a 4.7μF ceramic capacitor.
power input
System Power Output. SYS provides power to the system resources as well as the control logic
of the device. Connect SYS to IN_SBB and bypass to GND with a 22μF ceramic capacitor.
E2
E3
D1
power output
Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with a 4.7μF
ceramic capacitor.
BATT
power I/O
power
Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a 1μF ceramic
capacitor. Do not load V externally.
L
V
L
Thermistor Bias Supply. Connect a resistor equal to the NTC's room temperature resistance
between TBIAS and THM. Do not load TBIAS with any other external circuitry.
D3
D2
C1
TBIAS
THM
analog
Thermistor Monitor. Thermally couple an NTC to the battery and connect between THM and GND.
analog input
analog output
Analog Multiplexer Output. Connect to system ADC to perform conversions on charger power
signals.
AMUX
LDO
B5
LDO
Linear Regulator Output
power output
power input
B6
IN_LDO Linear Regulator Input
RGB LED DRIVER
Current Sink Port 0. LED0 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused.
A6
A5
A4
B3
LED0
LED1
LED2
LGND
power
power
power
ground
Current Sink Port 1. LED1 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused.
Current Sink Port 2. LED2 is typically connected to the cathode of an LED and is capable of
sinking up to 12.5mA. Connect to ground if unused.
Current Sink Ground. Connect LGND to GND, PGND, and the low-impedance ground plane of
the PCB.
SIMO BUCK BOOST
SIMO Power Input. Connect IN_SBB to SYS and bypass to PGND with a 10uF ceramic
capacitor as close as possible to the IN_SBB pin.
E4
C6
D6
E6
C5
IN_SBB
SBB0
SBB1
SBB2
BST
power input
power output
power output
power output
power input
SIMO Buck-Boost Output 0. SBB0 is the power output for channel 0 of the SIMO buck-boost.
Bypass SBB0 to PGND with a 10μF ceramic capacitor.
SIMO Buck-Boost Output 1. SBB1 is the power output for channel 1 of the SIMO buck-boost.
Bypass SBB1 to PGND with a 10μF ceramic capacitor.
SIMO Buck-Boost Output 2. SBB2 is the power output for channel 2 of the SIMO buck-boost.
Bypass SBB2 to PGND with a 10μF ceramic capacitor.
SIMO Power Input for the High-Side Output NMOS Drivers. Connect a 3300pF ceramic capaci-
tor between BST and LXB.
Switching Node A. LXA is driven between PGND and IN_SBB when any SIMO channel is en-
abled. LXA is driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor
between LXA and LXB.
D4
LXA
power I/O
Switching Node B. LXB is driven between PGND and SBBx when SBBx is enabled. LXB is
driven to PGND when all SIMO channels are disabled. Connect a 1.5μH inductor between LXA
and LXB.
D5
E5
LXB
power I/O
ground
Power ground for the SIMO low-side FETs. Connect PGND to GND, LGND, and the low-imped-
ance ground plane of the PCB.
PGND
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Ultra-Low Power PMIC with 3-Output SIMO
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Support Materials
Detailed Description
Support materials are available to assist engineering
teams in designing with this device. For example, a full
description of the register bits along with software advice
is available in the Programmer’s Guide. Visit the product
page at www.maximintegrated.com/MAX77650 and/
or contact Maxim for more information on support docu-
ments.
The MAX77650/MAX77651 provide a highly-integrated
battery charging and power management solution for low-
power applications. The linear charger provides a wide
range of charge current and charger termination voltage
options to charge various Li+ batteries. Temperature
monitoring and JEITA compliance settings add additional
functionality and safety to the charger. Four regulators
are integrated within this device (see Table 1). A single-
inductor, multiple output (SIMO) buck-boost regulator
efficiently provides three independently programmable
power rails. A 150mA LDO provides ripple rejection for
audio and other low-noise applications.
Top-Level Interconnect Simplified Diagram
Figure 1 shows the same major blocks as the Typical
Application Circuit with an increased emphasis on the
routing between each block. This diagram is intended
to familiarize the user with the landscape of the device.
Many of the details associated with these signals are
discussed throughout the data sheet. At this stage of
the data sheet, note the addition of the main bias and
clock block that are not shown in the Typical Applications
Circuit. The main bias and clock block provides voltage,
current, and clock references for other blocks as well as
many resources for the top-level digital control.
The system includes other features such as current sinks
for driving LED indicators and an analog multiplexer that
switches several internal voltage and current signals to
an external node for monitoring with an external ADC.
2
A bidirectional I C serial interface allows for configuring
and checking the status of the device. An internal on/off
controller provides regulator sequencing and supervisory
functionality for the device.
Table 1. Regulator Summary
MAX77650 V
RANGE/
RESOLUTION
MAX77651 V
RANGE/
RESOLUTION
OUT
OUT
REGULATOR
NAME
REGULATOR
TOPOLOGY
MAXIMUM I
OUT
V
RANGE (V)
IN
(mA)
0.8V to 2.375V in
25mV steps
0.8 to 2.375V in
25mV steps
SBB0
SBB1
SBB2
LDO
SIMO
SIMO
Up to 300*
Up to 300*
Up to 300*
150
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
1.8 to 5.5
0.8V to 1.5875V in
12.5mV steps
2.4 to 5.25V in
50mV steps
0.8V to 3.95V in
50mV steps
2.4 to 5.25V in
50mV steps
SIMO
1.35V to 2.9375V in
12.5mV steps
1.35 to 2.9375V in
12.5mV steps
PMOS LDO
*Shared capacity with other SBBx channels. See the SIMO Available Output Current section for more information.
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Ultra-Low Power PMIC with 3-Output SIMO
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IRQ_CHG
V
V
REF
REF
MAX77650/MAX77651
V
V
IREF
SYSRST
IREF
SYSRST
CHGINPOK
SIMO
CHARGER
and
MUX
nEN
COMM
FPS
COMM
AMUX
IRQ_CHG
V
REF
V
IREF
SYSRST
LDO
CLK
FPS
COMM
V
REF
V
IREF
SYS
SYSUVLO
SYSOVLO
OTLO
POR
BOK
MAIN BIAS
AND CLOCK
CLK
V
REF
CURRENT
SINK
V
IREF
SYSRST
FPS
SYSRST
COMM
BIAS_EN
SBIA_LPM
IRQ_CHG
SYS
100us/30ms
DEBOUNCE
TIMER
DBEN_nEN
DBNEN
nEN
t
DBNC_nEN
AMUX
nRST
AMUX
VIO
TOP-LEVEL
DIGITAL
CONTROL
100us
GLITCH FILTER
PWR_HLD
STAT_PWR_HLD
PWR_HLD2
RST
t
PWR_HLD_GF
nIRQ
IRQ_TOP
CHGINPOK
VIO
SDA
SCL
10ns/30ms
DEBOUNCE
TIMER
DBEN_GPI
DI
2
COMM
I C
t
GPIO
DBNC_nEN
DO
Figure 1. Top-Level Interconnect Simplified Diagram
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Ultra-Low Power PMIC with 3-Output SIMO
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and Table 2 for additional information regarding the UVLO
comparator:
Global Resources
The global resources encompass a set of circuits that
serve the entire device and ensure safe, consistent, and
reliable operation.
● When the device is in the STANDBY state, the UVLO
comparator is disabled.
● When transitioning out of the STANDBY state, the
UVLO comparator is enabled allowing the device to
check for sufficient input voltage. If the device has
sufficient input voltage, it can transition to the on
state; if there is insufficient input voltage, the device
transitions back to the STANDBY state.
Features and Benefits
● Voltage Monitors
• SYS POR (power-on-reset) comparator generates
a reset signal upon power-up
• SYS undervoltage ensures repeatable behavior when
power is applied to and removed from the device
• SYS overvoltage monitor inhibits operation with
overvoltage power sources to ensure reliability in
faulty environments
SYS Overvoltage Lockout Comparator
The device is rated for 5.5V maximum operating voltage
(V ) with an absolute maximum input voltage of 6.0V.
SYS
An overvoltage lockout monitor increases the robustness
of the device by inhibiting operation when the supply volt-
● Thermal Monitors
• 165°C junction temperature shutdown
● Manual Reset
age is greater than V . See Figure 4 and Table 2
SYSOVLO
for additional information regarding the OVLO comparator:
• 8s or 16s period
● Wakeup Events
● When the device is in the STANDBY state, the OVLO
• Charger insertion (with 120ms debounce)
• nEN input assertion
● Interrupt Handler
comparator is disabled.
nEN Enable Input
nEN is an active-low internally debounced digital input
that typically comes from the system’s on key. The
debounce time is programmable with DBEN_nEN. The
primary purpose of this input is to generate a wake-up
signal for the PMIC that turns on the regulators. Maskable
rising/falling interrupts are available for nEN (nEN_R and
nEN_F) for alternate functionality. nEN requires an exter-
nal pullup resistor (10kΩ to 100kΩ) to SYS.
• Interrupt output (nIRQ)
• All interrupts are maskable
● Push-button/Slide-Switch Onkey (nEN)
• Configurable push-button/slide-switch functionality
• 100μs or 30ms debounce timer interfaces directly
with mechanical switches
● On/Off Controller
• Startup/shut-down sequencing
• Programable sequencing delay
● PWR_HLD, GPIO, RST Digital I/Os
The nEN input can be configured to work either with a
push-button (nEN_MODE = 0) or a slide-switch (nEN_
MODE = 1). See Figure 2 for more information. In both
push-button mode and slide-switch mode, the on/off con-
troller looks for a falling edge on the nEN input to initiate
a power-up sequence.
Voltage Monitors
The device monitors the system voltage (V
proper operation using three comparators (POR, UVLO,
and OVLO). These comparators include hysteresis to
prevent their outputs from toggling between states during
noisy system transitions.
) to ensure
SYS
nEN Manual Reset
nEN works as a manual reset input when the on/off con-
troller is in the on via on/off controller state. The manual
reset function is useful for forcing a power-down in case
the communication with the processor fails. When nEN is
configured for a push-button mode and the input is assert-
SYS POR Comparator
The SYS POR comparator monitors V
a power-on reset signal (POR). When V
and generates
SYS
is below
SYS
V
V
, the device is held in reset (SYSRST = 1). When
POR
ed (nEN = low) for an extended period (t
), the on/off
MRST
rises above V
, internal signals and on-chip
POR
SYS
controller initiates a power-down sequence and goes to
standby mode. When nEN is configured for a slide-switch
mode and the input is deasserted (nEN = high) for an
memory stabilize and the device is released from reset
(SYSRST = 0).
extended period (t
power-down sequence and goes to standby mode.
), the on/off controller initiates a
MRST
SYS Undervoltage Lockout Comparator
The SYS undervoltage lockout (UVLO) comparator moni-
A dedicated internal oscillator is used to create the 30ms
tors V
and generates a SYSUVLO signal when the
falls below UVLO threshold. The SYSUVLO signal
SYS
(t
) and 16s (t
) timers for nEN. Whenever
V
SYS
DBNC_nEN
MRST
the device is actively counting either of these times, the
is provided to the top-level digital controller. See Figure 4
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Ultra-Low Power PMIC with 3-Output SIMO
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supply current increases by the oscillator's supply current
(65μA when the battery voltage is at 3.7V). As soon as
the event driving the timer goes away or is fulfilled, the
oscillator automatically turns off and its supply current
goes away.
A pullup resistor to a voltage less than or equal to V
SYS
is required for this node. nIRQ is the logical NOR of all
unmasked interrupt bits in the register map
All interrupts are masked by default. Masked interrupt bits
do not cause the nIRQ pin to change. Unmask the inter-
rupt bits to allow nIRQ to assert.
nEN Dual-functionality:
Push-Button vs. Slide-Switch
Reset Output (nRST)
The nEN digital input can be configured to work with
a push-button switch or a slide-switch. The timing dia-
gram below shows nEN's dual functionality for power-on
sequencing and manual reset. The default configuration
of the device is push-button mode (nEN_MODE = 0) and
no additional programming is necessary. Applications
that use a slide-switch on-key configuration must set
nRST is an open-drain, active-low output that is typically
used to hold the processor in a reset state when the device
is powered down. During a power-up sequence, the nRST
deasserts after the last regulator in the power-up chain
is enabled (t
). During a power-down sequence,
RSTODD
the nRST output asserts before any regulator is powered
down (t ). See Figure 5 for nRST timing.
RSTOAD
nEN_MODE = 1 within t
.
MRST
A pullup resistor to a voltage less than or equal to V
is required for this node.
SYS
Interrupts (nIRQ)
nIRQ is an active-low, open-drain output that is typically
routed to the host processor’s interrupt input to signal
an important change in the device’s status. Refer to the
Programmer’s Guide for a comprehensive list of all inter-
rupt bits and status registers.
Power Hold Input (PWR_HLD)
PWR_HLD is an active-high digital input. PWR_HLD has a
100μs glitch filter (t ). As shown in Figure 1, the
PWR_HLD_GF
output of this glitch filter is logically ORed with the wakeup
signal coming from the charger to create a signal called
PWR_HLD2 that drives the top-level digital control.
NOT DRAWN TO SCALE
STATE
STANDBY
POWER-ON SEQUENCE
ON
POWER-DOWN SEQUENCE
BATTERY
INSERTION
V
SYS
SYS
t
DBNC_nEN
nEN
t
t
DBNC_nEN
DBNC_nEN
t
MRST
PUSH-BUTTON MODE
SYS
t
DBNC_nEN
nEN
t
MRST
t
DBNC_nEN
SLIDE-SWITCH MODE
Figure 2. nEN Usage Timing Diagram
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Ultra-Low Power PMIC with 3-Output SIMO
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● When there is no valid charge voltage at CHGIN
(CHGINPOK = 0):
● The open-drain mode requires an external pullup
resistor (typically 10kΩ–100kΩ). Connect the external
pullup resistor to a bias voltage that is less than or
• After the power-up sequence, the system proces-
sor must assert PWR_HLD within the PWR_HLD
equal to V .
IO
wait time (t
) to hold the power
PWR_HLD_WAIT
• The open-drain mode can be used to communicate
supply in the on state. If the PWR_HLD input is
not asserted within the t period, a
to different logic domains. For example, to send a
signal from the GPO on a 1.8V logic domain (V
=
PWR_HLD_WAIT
IO
power-down sequence is initiated.
1.8V) to a device on a 1.2V logic domain, connect
the external pullup resistor to 1.2V.
• The open-drain mode can be used to connect sever-
al open-drain (or open-collector) devices together on
the same bus to create wired logic (wired AND logic
is positive-true; wired OR logic is negative-true).
• While in the on state, the system processor must
assert PWR_HLD as long as power is required. If
the system processor wants to turn off, it can either
pull PWR_HLD low or it can write the SFT_RST
bits to execute the SFT_CRST or SFT_OFF func-
tions to execute the power-down sequence.
The general-purpose input (GPI) functions are still avail-
able while the pin is configured as a GPO. In other words,
the DI (input status) bit still functions properly and does
not collide with the state of the DIR bit.
● If there is a valid charge voltage at CHGIN
(CHGINPOK = 1):
• The charger sends a wakeup signal to the on/off
controller which is also logically ORed with PWR_
HLD to assert PWR_HLD2. PWR_HLD2 being
asserted satisfies the on/off controller such that the
PWR_HLD signal is a don't care.
Set DIR to disable the output drivers associated with the
GPO and have the device function as a GPI. The GPI
features a 30ms debounce timer (t
) that can be
DBNC_GPI
enabled or disabled with DBEN_GPI.
See the Figure 7, Top-Level On/Off Controller section,
and Table 2 for additional information regarding PWR_
HLD. If the power hold function is not used, connect
PWR_HLD to SYS and then use the SFT_RST bits to
power the device down.
● Enable the debounce timer (DBEN_GPI = 1) if the
GPI is connected to a device that can bounce or
chatter (like a mechanical switch).
● If the GPI is connected to a circuit with clean logic
transitions and no risk of bounce, disable the
debounce timer (DBEN_GPI = 0) to eliminate unnec-
essary logic delays. With no debounce timer, the GPI
input logic propagates to nIRQ in 10ns.
General-Purpose Input Output (GPIO)
A general-purpose input/output (GPIO) is provided to
increase system flexibility. See Figure 3 for the GPIO
Block Diagram.
A dedicated internal oscillator is used to create the 30ms
(t
) debounce timer. Whenever the device is
DBNC_GPI
Clear DIR to configure GPIO as a general-purpose output
(GPO). The GPO can either be in push-pull mode (DRV =
1) or open-drain mode (DRV = 0).
actively counting this time, the supply current increases
by the oscillator's supply current (65μA when the battery
voltage is at 3.7V). As soon as the event driving the timer
goes away or is fulfilled, the oscillator automatically turns
off and its supply current goes away.
● The push-pull output mode is ideal for applications that
need fast (~2ns) edges and low power consumption.
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Ultra-Low Power PMIC with 3-Output SIMO
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SYS
DRV
DIR
DO
GPI_RM
GPI_FM
DBNC_EN
DI
V
IO
COMM
CNFG_GPIO
GPI_R
GPI_F
GPI_R
GPI_RM
Q
Q
D
R
1
1
DRV
nIRQ
DBNC_EN
READ
(GPI_R)
IRQ
GPIO
GND
0
1
30ms DEBOUNCE
DI
(t
)
DBNC_GPI
GPI_FM
GPI_F
D
R
DIR
DO
LOGIC
OTHER nIRQ ASSERTION
SOURCES NOT SHOWN
READ
(GPI_F)
Figure 3. GPIO Block Diagram
Maskable rising and falling interrupts (GPI_R and GPI_F)
are available to signal a change in the GPI’s status.
edge interrupt and mask the rising edge interrupt
(GPI_RM = 1, GPI_FM = 0).
● To interrupt on either rising or falling edge: unmask
both rising and falling edge interrupts (GPI_RM = 0,
GPI_FM = 0). Consult the Register Map for more
details.
●
To interrupt on a rising edge only: unmask the rising
edge interrupt and mask the falling edge interrupt (GPI_
RM = 0, GPI_FM = 1).
●
To interrupt on a falling edge only: unmask the falling
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Some systems have several power management blocks,
a main processor, and subprocessors. These systems
can use this device as a subpower management block for
On/Off Controller
The on/off controller monitors multiple power-up (wakeup)
and power-down (shutdown) conditions to enable or dis-
able resources that are necessary for the system and its
processor to move between its operating modes.
2
a peripheral portion of circuitry as long as there is an I C
port available from a higher level processor. To concep-
tualize this slave operation, see Figure 4 and Table 2. A
typical path through the on/off controller in slave mode is:
Many systems have one power management controller
and one processor and rely on the on/off controller to be
the master controller. In this case, the on/off controller
receives the wakeup events and enables some or all of
the regulators in order to power up a processor. That pro-
cessor then manages the system. To conceptualize this
master operation see Figure 4 and Table 2. A typical path
through the on/off controller in master mode is:
● Start in the no power state.
● Apply a battery to the system and transition through
path 1 and 2 to the standby state.
● When the higher level processor wants to turn on this
device's resources, it enables the main bias circuits
2
through I C (SBIA_EN = 1) to transition along path
2A to the on through software state.
● Start in the no power state.
● Apply a battery to the system and transition through
path 1 and 2 to the standby state.
● The higher level processor can now control this
2
device's resources with I C commands (i.e., turn on/
off regulators).
● Press the system's on key (nEN = low) and transition
through path 3A and 4 to the "PWR_HLD?" state.
● The processor boots up and drives PWR_HLD high,
which drives the transition through path 4C to the on
through the on/off controller state.
● The device performs its desired functions in the on
through on/off controller state. When it is ready to turn
off, the processor drives PWR_HLD low that drives the
transition through path 5B and 8 to the standby state.
● When the higher level processor is ready to turn
2
this device off, it turns off everything through I C
and then disables the main bias circuits through I C
2
(SBIA_EN = 0) to transition along path 2B to the
standby state.
Note that in this slave style of operation, the SFT_RST
bits should not be used to turn the device off. The SFT_
RST bits establish directives to the on/off controller itself
that does not make sense in slave mode. In slave mode,
2
since the I C commands enable the device's resources,
they should also disable them.
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Ultra-Low Power PMIC with 3-Output SIMO
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NO POWER
CHGIN=0, VSYS<VPOR
ANY
STATE
STATE
0
V
ACTION
1
DECISION
POWER-ON
RESET (POR)
2
X
TRANSITION NAME.
SEE TABLE 2
2A
STANDBY
3
11
DISABLE MAIN BIAS
ENABLE MAIN BIAS
12
ENABLE MAIN BIAS
3A
6
6
8
2B
9
POWER UP
SEQUENCE
(FIGURE 5)
POWER DOWN
SEQUENCE
(FIGURE 5)
IMMEDIATE
SHUTDOWN
(FIGURE 5)
3
4
7
4B
PWR_HLD?
4C
4A
10
3
5A
ON VIA
SOFTWARE
ON VIA ON/OFF
CONTROLLER
5B
10
2B
Figure 4. Top-Level On/Off Controller
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Table 2. On/Off Controller Transition/State
TRANSITION/STATE
CONDITION
0
1
2
System voltage is below the POR threshold (V
< V
).
SYS
POR
System voltage is above the POR threshold (V
> V
).
SYS
POR
Internal signals and on-chip memory stabilize and the device is released from reset.
2
The device is waiting for a wake-up signal or an I C command to enable the main bias circuits.
* This is the lowest current state of the device (I ~0.3μA).
Q
* Main bias circuits are off, POR comparator is on.
STANDBY
2
* I C is on when V is valid.
IO
* Peripheral functions (LDO, SIMO, LEDs, AMUX) do not operate in this state because the main bias circuits
are off. To utilize a function enter the on through software or on through on/off controller states.
2
2A
2B
Main bias circuits enabled through I C (SBIA_EN = 1).
2
Main bias circuits disabled through I C (SBIA_EN = 0).
The main bias circuits are enabled through software and all peripheral functions (LDO, SIMO, LEDs, AMUX)
can be manually enabled or disabled through I C.
ON VIA
SOFTWARE*
2
A wake-up signal has been received.
* A debounced onkey (nEN) falling edge has been detected (DBNEN = 1) or
* A charge source has been applied and a rising edge on CHGIN has been detected and debounced
3
(t
~120ms) or
CHGIN-DB
* Internal wake-up flag has been set due to SFT_RST = 0b01 (WKUP = 1)
3A
4
Main bias circuits are OK (BOK = 1)
Power-up sequence complete.
4A
4B
4C
PWR_HLD wait time has expired and PWR_HLD2 is low (t > t
&& PWR_HLD2 = 0).
PWR_HLD_WAIT
PWR_HLD wait time has not expired and PWR_HLD2 is low (t < t
PWR_HLD2 = 1
&& PWR_HLD2 = 0).
PWR_HLD_WAIT
On state.
* All flexible power sequencers (FPS) are on.
* The main bias circuits are enabled.
ON VIA ON/OFF
CONTROLLER*
* I ~5.6µA (typ) with all regulators enabled (no load) and the main bias circuits in low power mode.
Q
5A
5B
PWR_HLD2 = 1
PWR_HLD2 = 0 OR
System overtemperature lockout (T >T
Software cold reset (SFT_RST[1:0] = 0b01) or
) or
J
OTLO
Software power off (SFT_RST[1:0] = 0b10) or
Manual reset occurred. See the nEN Manual Reset section for more information.
System overtemperature lockout (T >T
) or
J
OTLO
6
7
System undervoltage lockout (V
< V
+ V
) or
SYSUVLO_HYS
SYS
SYSUVLO
System overvoltage lockout (V
> V
)
SYS
SYSOVLO
System undervoltage lockout (V
System overvoltage lockout (V
< V
SYSUVLO
) or
SYS
> V
)
SYS
SYSOVLO
Note: The overvoltage lockout transition does not apply to the ON VIA SOFTWARE state.
8
Finished with the power-down sequence.
9
Finished with immediate shutdown.
10
11
12
System overtemperature lockout (T > T
J
).
OTLO
Done disabling main bias.
Done enabling main bias.
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Ultra-Low Power PMIC with 3-Output SIMO
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POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
START FROM TOP LEVEL
#4A OR #5B
START
FROM TOP LEVEL #3A
CLEAR WAKEUP
FLAG (WKUP = 0)
CLEAR WAKEUP FLAGS
FPS ENABLE SLOT 0
TEMPERATURE IS
NOT OKAY
(T >T
J
)
OTLO
OTLO?
TEMPERATURE IS OKAY
(T <T
WAIT t
EN
)
OTLO
J
WAIT 60ms
FPS ENABLE SLOT 1
SFT_RST = 0b00
OR PWR_HLD2 = 1
SFT_RST = 0b01
WAIT t
EN
SFT_RST = 0b10
OR PWR_HLD2 = 0
SET WAKEUP
FLAG (WKUP = 1)
FPS ENABLE SLOT 2
WAIT t
EN
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER DOWN EVENT.
FPS ENABLE SLOT 3
WAIT t
RSTODD
ASSERT nRST
DE-ASSERT nRST
WAIT t
RSTOAD
END
TO TOP LEVEL #4
FPS DISABLE SLOT 3
WAIT t
DIS
IMMEDIATE SHUTDOWN
FPS DISABLE SLOT 2
START
FROM TOP LEVEL #7
WAIT t
DIS
SET THE APPROPRIATE BIT IN THE EVENT
RECORDER REGISTER (ERCFLAG) TO INDICATE
THE SOURCE OF THE POWER DOWN EVENT.
FPS DISABLE SLOT 1
WAIT t
DIS
ASSERT nRST
DISABLE FPS3, FPS2, FPS1, FPS0
FPS DISABLE SLOT 0
WAIT 125ms
WAIT 125ms
RESET DEVICE
RESET DEVICE
(PULSE SYSRST FOR 5µs)
(PULSE SYSRST FOR 5µs)
END
END
RETURN BACK TO
THE ON STATE
TO TOP LEVEL #9
TO TOP LEVEL #8
Figure 5. Power-Up/Power-Down Sequence
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The flexible sequencing structure consists of 1 master
sequencing timer and 4 slave resources (SBB0, SBB1,
SBB2, and LDO). When the FPS is enabled, a master
timer generates four sequencing events for device power-
up and power-down.
Flexible Power Sequencer
The flexible power sequencer (FPS) allows resources to
power up under hardware or software control. Additionally,
each resource can power up independently or among a
group of other regulators with adjustable power-up and pow-
er-down delays (sequencing). Figure 6 shows four resources
powering up under the control of flexible power sequencer.
NOT DRAWN TO SCALE
ENFPS
t
t
SAME FOR ALL FPS DISABLE PULSES
DIS
t
SAME FOR ALL FPS ENABLE PULSES
EN
= 2x t
DIS
EN
0
1
2
3
3
2
1
0
PLSFPS
FPS RESOURCES
SBB0
LDO
SBB1
SBB2
Figure 6. Flexible Power Sequencer Basic Timing Diagram
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Ultra-Low Power PMIC with 3-Output SIMO
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NOT DRAWN TO SCALE
ON THROUGH ON/OFF
CONTROLLER
NO POWER
STATE
POR
STANDBY
POWER-UP SEQUENCE
PWR_HLD?
BATTERY
INSERTION
V
SYS
V
~1.9V
POR
t
~100µs
POR
t
t
DBNC_nEN
DBNC_nEN
nEN
NOTE 1
NOTE 2
STAT_EN
nEN_F
t
SBIA_EN
nEN_R
BIAS EN
(INTERNAL)
INTERNAL WAKE-UP
SIGNAL NOTE 3
FPS0
FPS1
FPS2
FPS3
t
t
t
EN
EN
EN
REGULATORS
nIRQ
NOTE 4
t
RSTODD
nRST
t
PWR_HLD_WAIT
SYSTEM
SOFTWARE
PWR_HLD
NOTES:
1 – nEN LOGIC INPUT IS CONFIGURED TO PUSH-BUTTON MODE AND HAS AN EXTERNAL PULLUP TO SYS.
2 – nEN ASSERTION RESULTS IN A WAKE-UP EVEN AFTER A DEBOUNCE TIME (t ).
DBNCEN
NOTE
5
NOTE
6
3 – INTERNAL WAKE-UP SIGNAL CAN ALSO BE GENERATED BY CHARGER PLUG-IN EVENT.
4 – nIRQ HAS AN EXTERNAL PULLUP TO V WHICH IS ENABLED IN FLEXIBLE POWER SEQUENCER SLOT #1
IO
5 – SYSTEM PROCESSOR ASSERTS PWR_HLD INPUT TO PLACE THE DEVICE IN THE ON THROUGH ON/OFF CONTROLLER STATE.
6 – AS PART OF ITS INITIALIZATION ROUTINE, SOFTWARE READS THE INTERRUPT REGISTERS (CLEAR ON READ) AND PROGRAMS THE INTERRUPT MASKS AS DESIRED.
Figure 7. Startup Timing Diagram Due to nEN
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Ultra-Low Power PMIC with 3-Output SIMO
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STATE
CHGIN DEBOUNCE
CHGINOK=1
POWER-UP SEQUENCE
PWR_HLD?
ON THROUGH ON/OFF CONTROLLER
PRE-QUAL
FAST CHARGE (CC)
TOP-OFF (CV)
DONE
CHARGER
INSERTION
5V
V
CHGIN
0V
V
SYS-REG
V
FAST-CHG
V
SYS
V
~2.9V
SYSUVLO
t
(~120ms)
CHGIN-DB
V
~2.0V
POR
0V
V
FAST-CHG
INTERNAL CHARGER GENERATED
WAKE SIGNAL
NOTE 3
V
BATT
V
PQ
0V
FAST-CHG
NOTE 4
V
I
BATT
I
TOPOFF
PQ
I
0mA
NOTE 5
CHG_EN = 1
CHARGER ENABLED
NOTE 1
nEN
FPS0
FPS1
FPS2
FPS3
NOTES: 1 – nEN LOGIC INPUT IN CONFIGURED TO PUSH-BUTTON MODE AND HAS AN
EXTERNAL PULLUP TO SYS.
t
t
t
EN
EN
EN
2 – IF PWR_HLD IS NOT ASSERTED BY THE END OF THE t
INITIATES A POWER-DOWN SEQUENCE.
PERIOD, DEVICE
PWR_HLD_WAIT
REGULATORS
3 - IF CHG_EN = 1 (@ OTP) THEN THE CHARGER ENABLED EVENT COINCIDES WITH THE WAKE
EVENT (CHARGING START ALONG WITH POWER-UP SEQUENCE).
t
SBIA_EN
t
RSTODD
4 – THIS INFLECTION POINT IS SYMBOLIC OF BATTERY PROTECTION FET CLOSING
nRST
5 – SOFTWARE SETS CHG_EN = 1 TO ENABLE CHARGING. IF CHG_EN = 1 AT OTP, SEE NOTE 3.
t
PWR_HLD_WAIT
- - - - BLUE DOTTED LINES ARE USER INITIATED EVENTS
NOTE 2
PWR_HLD2
Figure 8. Startup Timing Diagram Due to Charge Source Insertion
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Ultra-Low Power PMIC with 3-Output SIMO
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Over-temperature lockout (OTLO) is entered if the junc-
Debounced Inputs (nEN, GPI, CHGIN)
tion temperature exceeds T
(approximately 165°C,
OTLO
nEN, CHGIN, and GPIO (when operating as an input), are
debounced on both rising and falling edges to reject unde-
sired transitions. The input must be at a stable logic level
for the entire debounce period for the output to change its
logic state. Figure 9 shows an example timing diagram for
the nEN debounce.
typ). OTLO causes transition 10 in Figure 4 which causes
resources to immediately shutdown from the on via on/
off controller state. Resources may not enable until the
temperature falls below T
by approximately 15°C.
OTLO
The TJAL1_S and TJAL2_S status bits continuously
indicate the junction temperature alarm status. Maskable
interrupts are available to signal a change in either of
these bits. Refer to the Programmer’s Guide for details.
Thermal Alarms and Protection
The device has thermal alarms to monitor if the junction
temperature rises above 80°C (T
) and 100ºC (T
).
JAL1
JAL2
STABLE
STABLE
SIGNAL IS
ACCEPTED
SIGNALS IS
ACCEPTED
BOUNCING IS
REJECTED
BOUNCING IS
REJECTED
nEN
tDBUF
tDBUF
EN
(INTERNAL)
DBEN
tDBNCEN
tDBNCEN
(INTERNAL)
Figure 9. Debounced Inputs
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Ultra-Low Power PMIC with 3-Output SIMO
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Additionally, the robust charger input withstands overvoltag-
es up to 28V. To enhance charger safety, an NTC thermis-
tor provides temperature monitoring in accordance with the
JEITA recommendations. See the Adjustable Thermistor
Temperature Monitors section for more information.
Smart Power Selector Charger
The linear Li+ charger implements power path with
Maxim's smart power selector. This allows separate input
current limit and battery charge current settings. Batteries
charge faster under the supervision of the smart power
selector because charge current is independently regu-
lated and not shared with variable system loads. See the
Smart Power Selector section for more information.
Features
● 7.25V maximum operating input voltage with 28V
input standoff
The programmable constant-current charge rate (7.5mA
to 300mA) supports a wide range of battery capacities.
The programmable input current limit (0mA to 475mA)
supports a range of charge sources, including USB. The
charger's programmable battery regulation voltage range
(3.6V–4.6V) supports a wide variety of cell chemistries.
Small battery capacities are supported; the charger accu-
rately terminates charging by detecting battery currents as
low as 0.375mA.
● 7.5mA to 300mA programmable fast-charge current
● Programmable termination current from 0.375mA to
45mA
● Programmable battery regulation voltage from 3.6V
to 4.6V
● < 1μA battery-only supply current
● Instant-on functionality
● Analog multiplexer enables power monitoring
● JEITA battery temperature monitor adjusts current
and battery regulation voltage for safe charging
● Programmable die temperature regulation
Figure 10. Linear Charger Simplified Block Diagram
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Ultra-Low Power PMIC with 3-Output SIMO
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Figure 11 indicates the high-level functions of each control
circuit within the linear charger.
Charger Symbol Reference Guide
Table 3 lists the names and functions of charger-specific
signals and if they can be programmed through I C.
2
Consult the Electrical Characteristics and Programmer’s
Guide for more information.
Table 3. Charger Quick Symbol Reference Guide
2
SYMBOL
NAME
I C PROGRAMMABLE?
V
V
V
CHGIN overvoltage threshold
No
No
CHGIN_OVP
CHGIN undervoltage lockout threshold
Minimum CHGIN voltage regulation setpoint
CHGIN input current limit
CHGIN_UVLO
CHGIN-MIN
CHGIN-LIM
Yes, through VCHGIN_MIN[2:0]
Yes, through ICHGIN_LIM[2:0]
Yes, through VSYS_REG[4:0]
I
V
V
V
SYS voltage regulation target
Minimum SYS voltage regulation setpoint
Fast-charge constant-voltage level
Fast-charge constant-current level
Prequalification current level
Prequalification voltage threshold
Termination current level
SYS-REG
SYS-MIN
FAST-CHG
FAST-CHG
PQ
No, tracks V
SYS-REG
Yes, through CHG_CV[5:0]
Yes, through CHG_CC[5:0]
Yes, through I_PQ
I
I
V
Yes, through CHG_PQ[2:0]
Yes, through I_TERM[1:0]
Yes, through TJ_REG[2:0]
No
PQ
I
TERM
T
Die temperature regulation setpoint
Prequalification safety timer
J-REG
t
t
t
PQ
Fast-charge safety timer
Yes, through T_FAST_CHG[1:0]
Yes, through T_TOPOFF[2:0]
FC
TO
Top-off timer
BODY-
SWITCH
CHGIN
SYS
V
SYS-MIN
I
V
CHGIN-LIM
SYS-REG
INPUT
CONTROLLER
CHARGE CONTROLLER
V
CHGIN-MIN
V
CHGIN_OVP
V
CHGIN_UVLO
I
I
I
FAST-CHG
V
V
FAST-CHG
PQ
DIE TEMP
MONITOR
PQ
T
J-REG
TERM
BATT
TIMER
t
PQ
t
FC
TO
t
Figure 11. Charger Simplified Control Loops
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Ultra-Low Power PMIC with 3-Output SIMO
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regulation loop also prevents V
from dropping
Smart Power Selector
CHGIN
below V
if the cable between the charge
CHGIN_UVLO
The smart power selector seamlessly distributes power
from the input (CHGIN) to the battery (BATT) and the sys-
tem (SYS). The smart power selector basic functions are:
source and the charger's input is long or highly resistive.
The input voltage regulation loop improves performance
with current limited adapters. If the charger’s input current
limit is programmed above the current limit of the given
adapter, the input voltage loop allows the input to regulate
at the current limit of the adapter. The input voltage regu-
lation loop also allows the charger to perform well with
adapters that have poor transient load response times.
● When the system load current is less than the input
current limit, the battery is charged with residual
power from the input.
● When a valid input source is connected, the sys-
tem regulates to V
to power system loads
SYS-REG
regardless of the battery's voltage (instant on).
● When the system load current exceeds the input cur-
rent limit, the battery provides additional current to
the system (supplement mode).
A maskable interrupt (CHGIN_CTRL_I) signals when the
minimum input voltage regulation loop engages. The state
of this loop is reflected by VCHGIN_MIN_STAT.
● When the battery is finished charging and an input
source is present to power the system, the battery
remains disconnected from the system.
● When the battery is connected and there is no input
power, the system is powered from the battery.
Minimum System Voltage Regulation
The minimum system voltage regulation loop ensures that
the system rail remains close to the programmed SYS
regulation voltage (V
) regardless of system load-
SYS-REG
ing. The loop engages when the combined battery charge
current and system load current causes the CHGIN input
Input Current Limiter
The input current limiter limits CHGIN current so as not to
to current-limit at I
. When this happens, the
CHGIN-LIM
exceed I
(programmed by I
[2:0]). A
CHGIN-LIM
CHGIN_LIM
minimum system voltage loop reduces charge current in
an attempt to keep the input out of current limit, thereby
maskable interrupt (CHGIN_CTRL_I) is available to signal
when the input current limit engages. The state of this
loop is reflected by the ICHGIN_LIM_STAT bit.
keeping the system voltage above V
(V
SYS-MIN SYS-REG
- 100mV typical). If this loop reduces battery current to 0
and the system is in need of more current than the input
can provide, then the smart power selector overrides the
minimum system voltage regulation loop and allows SYS
to collapse to BATT for the battery to provide supplement
current to the system. The smart power selector automati-
cally reenables the minimum system voltage loop when
the supplement event has ended.
The input circuit is capable of standing off 28V from
ground. CHGIN suspends power delivery to the sys-
tem and battery when V
exceeds V
CHGIN
CHGIN_OVP
(7.5V typical). The input circuit also suspends when
falls below V minus 500mV of hys-
V
CHGIN
CHGIN_UVLO
teresis (3.5V typical). While in OVP or UVLO, the charger
remains off, and the battery provides power to the system.
When an valid charge source is connected to CHGIN,
SYS begins delivering power to the system after a 120ms
A maskable interrupt (SYS_CTRL_I) asserts to signal a
change in VSYS_MIN_STAT. This status bit asserts when
the minimum system voltage regulation loop is active.
debounce timer (t
).
CHGIN-DB
A maskable interrupt (CHGIN_I) signals changes in the
state of CHGIN's voltage quality. The state of CHGIN is
reflected by CHGIN_DTLS[1:0].
Die Temperature Regulation
In case the die temperature exceeds T
(pro-
J-REG
grammed by TJ_REG[2:0]) the charger attempts to limit
the temperature increase by reducing battery charge
current. The TJ_REG_STAT bit asserts whenever charge
current is reduced due to this loop. The charger's cur-
rent sourcing capability to SYS remains unaffected when
TJ_REG_STAT is high. A maskable interrupt (TJ_REG_I)
asserts to signal a change in TJ_REG_STAT. It is advis-
able that the TJ_REG_I interrupt be used to signal the
system processor to reduce loads on SYS to reduce total
system temperature.
Minimum Input Voltage Regulation
In the event of a poor-quality charge source, the mini-
mum input voltage regulation loop works to reduce input
current if V
falls below V
(programmed
CHGIN
CHGIN-MIN
by VCHGIN_MIN[2:0]). This is important because many
commonly used charge adapters feature foldback protec-
tion mechanisms where the adapter completely shuts off
if its output droops too low. The minimum input voltage
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bitfield, CHG_DTLS[3:0], reflects the charger's current
operational state. A maskable interrupt (CHG_I) is avail-
able to signal a change in CHG_DTLS[3:0].
Charger State Machine
The battery charger follows a strict state-to-state progres-
sion to ensure that a battery is charged safely. The status
CHGIN INVALID
(CHGIN_DTLS[1:0] = 0b00 or 0b01)
OR
CHGIN INSERTED
(CHGIN_DTLS[1:0] = 0b10)
CHARGER DISABLED
DE-BOUNCE
CHG_DTLS[3:0] = 0b0000
CHG = 0
CHARGER OFF
CHG_DTLS[3:0] = 0b0000
CHG = 0
(CHG_EN = 0)
ANY STATE
CHGIN DE-BOUNCED
TIME ELAPSED >= t
THM_EN = 1
CHGIN-DB
RETURNS TO SAME STATE WHEN:
THM_EN = 0
OR
AND
CHG_EN = 1
AND
(CHGIN_DTLS[1:0] = 0b11)
CHARGER ENABLED (CHG_EN = 1)
AND
TIME ELAPSED < t
CHGIN-DB
(T
BATT
< T
AND T
> T
)
COLD
HOT
BATT
(T
> T
OR T
< T
)
COLD
BATT
HOT
BATT
CHGIN DE-BOUNCED & VALID (CHGIN_DTLS[1:0] = 0b11)
AND
BATTERY TEMPERATURE
FAULT
BATTERY LOW BY V
(V
< V
– 150mV)
FAST-CHG
RESTART BATT
CHG_DTLS[3:0] = 0b1100
CHG = 0
TIMERS PAUSE IN THIS STATE,
RESUME ON EXIT.
PREQUALIFICATION
CHG_DTLS[3:0] = 0b0001
CHG = 1
PREQUALIFICATION
TIMER FAULT
CHG_DTLS[3:0] = 0b1010
CHG = 0
TIME ELAPSED > t
PQ
I
= I
BATT PQ
V
< V – 100mV
PQ
BATT
V
> V
PQ
BATT
V
< V – 100mV
PQ
BATT
THM_EN = 1 AND
(T > T OR T
< T )
COOL
BATT
WARM
BATT
JEITA-MODIFIED
ANY FAST-CHARGE OR
JEITA-MODIFIED FAST-CHARGE
STATE
CHG_DTLS[3:0] = 0b0010-0b0101
CHG = 1
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0010
CHG = 1
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0011
CHG = 1
I
= I
**
BATT FAST-CHG
I
= I
**
THM_EN = 0 OR
(T < T
BATT FAST-CHG_JEITA
AND T
> T
)
COOL
BATT
WARM
BATT
BATT
V
<
BATT
V
= V
TIME ELAPSED* > t
FC
BATT
FAST-CHG_JEITA
V
< V
V
= V
FAST-CHG
BATT
FAST-CHG
BATT
V
FAST-CHG_JEITA
THM_EN = 1 AND
(T > T OR T
< T
)
BATT
WARM
COOL
JEITA-MODIFIED
FAST-CHARGE
TIMER FAULT
CHG_DTLS[3:0] = 0b1011
CHG = 0
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0100
CHG = 1
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0101
CHG = 1
V
= V
FAST-CHG
BATT
V
= V
FAST-CHG_JEITA
BATT
THM_EN = 0 OR
(T < T
AND T
> T
)
COOL
BATT
WARM
BATT
BATT
I
> I
I
< I
BATT TERM
BATT TERM
I
< I
BATT TERM
I
> I
BATT TERM
THM_EN = 1 AND
(T > T OR T
< T )
COOL
BATT
WARM
JEITA-MODIFIED
TOP-OFF
CHG_DTLS[3:0] = 0b0111
CHG = 1
TOP-OFF
CHG_DTLS[3:0] = 0b0110
CHG = 1
*TIME ELAPSED IS AGGREGATED
THROUGHOUT THE FAST-CHARGE AND
JEITA-MODIFIED FAST-CHARGE
STATES. ALL FAST-CHARGE STATES
(REGARDLESS OF JEITA STATUS)
SHARE THE SAME SAFETY TIMER.
V
= V
FAST-CHG
BATT
V
= V
FAST-CHG_JEITA
BATT
THM_EN = 0 OR
(T < T
AND T
> T
)
COOL
BATT
WARM
BATT
TIME ELAPSED > t
TO
TIME ELAPSED > t
TO
**I
MAY BE REDUCED BY THE
FAST-CHG
MINIMUM INPUT VOLTAGE REGULATION
LOOP, THE MINIMUM SYSTEM VOLTAGE
REGULATION LOOP, OR THE DIE
JEITA-MODIFIED DONE
CHG_DTLS[3:0] = 0b1001
CHG = 0
DONE
CHG_DTLS[3:0] = 0b1000
CHG = 0
TEMPERATURE REGULATION LOOP.
THM_EN = 0 OR
(T < T
AND T
> T
)
COOL
BATT
WARM
BATT
Figure 12. Charger State Diagram
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Ultra-Low Power PMIC with 3-Output SIMO
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A fast-charge safety timer starts when the state machine
enters fast-charge (CC) or JEITA-modified fast-charge
(CC) from a non-fast-charge state. The timer continues to
run through all fast-charge states regardless of JEITA sta-
Charger Off State
The charger is off when CHGIN is invalid, the charger is
disabled, or the battery is fresh.
CHGIN is invalid when the CHGIN input is invalid
tus. The timer length (t ) is programmable from 3 hours
FC
(V
< V
or V
> V
).
CHGIN
CHGIN_UVLO
CHGIN
CHGIN_OVP
to 7 hours in 2 hour increments with T_FAST_CHG[1:0].
If it is desired to charge without a safety timer, program
T_FAST_CHG[1:0] with 0b00 to disable the feature. If the
timer expires before the fast-charge states are exited, the
charger faults. See the Fast-Charge Timer Fault State
section for more information.
While CHGIN is invalid, the battery is connected to the
system. CHGIN voltage quality can be separately moni-
tored by the CHGIN_DTLS[1:0] status bitfield. Refer to
the Programmer’s Guide for details.
The charger is disabled when the charger enable bit is 0
(CHG_EN = 0). The battery is connected or disconnected
to the system depending on the validity of V
If the charge current falls below 20% of the programmed
value during fast-charge (CC), the safety timer pauses.
The timer also pauses for the duration of supplement
mode events. The TIME_SUS bit indicates the status of
the fast-charge safety timer. Refer to the Programmer’s
Guide for more details.
while
CHGIN
CHG_EN = 0. See the Smart Power Selector section.
The battery is fresh when CHGIN is valid and the charger
is enabled (CHG_EN = 1) and the battery is not low by
V
(V
BATT
> V
- V
). The bat-
RESTART
FAST-CHG
RESTART
tery is disconnected from the system and not charged
while the battery is fresh. The charger state machine exits
this state and begin charging when the battery becomes
Top-Off State
Top-off state is entered when the battery charge cur-
rent falls below I
during the fast-charge (CV) state.
low by V
(150mV typical). This condition is func-
TERM
RESTART
I
is a percentage of I
and is program-
tionally similar to done state. See Done State section.
TERM
FAST-CHG
mable through I_TERM[1:0]. While in the top-off state,
the battery charger continues to hold the battery's voltage
Prequalification State
The prequalification state is intended to assess a low-volt-
age battery's health by charging at a reduced rate. If the
battery voltage is less than the V
at V . A programmable top-off timer starts when
FAST-CHG
the charger state machine enters the top-off state. When
the timer expires, the charger enters the done state. The
threshold, the charger
PQ
is automatically in prequalification. If the cell voltage does
not exceed V in 30 minutes (t ), the charger faults.
top-off timer value (t ) is programmable from 0 minutes
to 35 minutes with T_TOPOFF[2:0]. If it is desired to stop
TO
PQ
PQ
The prequalification charge rate is a percentage of I
charging as soon as battery current falls below I
,
FAST-
TERM
and is programmable with I_PQ. The prequalifica-
program t
to 0 minutes.
CHG
TO
tion voltage threshold (V ) is programmable through
PQ
Done State
CHG_PQ[2:0].
The charger enters the done state when the top-off timer
expires. The battery remains disconnected from the
system during done. The charger restarts if the battery
Fast-Charge States
When the battery voltage is above V , the charger
PQ
transitions to the fast-charge (CC) state. In this state, the
charger delivers a constant current (I
cell. The constant current level is programmable from
7.5mA to 300mA by CHG_CC[5:0].
voltage falls more than V
(150mV typ) below the
RESTART
value.
) to the
programmed V
FAST-CHG
FAST-CHG
Prequalification Timer Fault State
The prequalification timer fault state is entered when the
When the cell voltage reaches V
state machine transitions to fast-charge (CV). V
, the charger
FAST-CHG
battery's voltage fails to rise above V
in t
(30 min-
PQ
TO
FAST-
utes typical) from when the prequalification state was first
entered. If a battery is too deeply discharged, damaged,
or internally shorted, the prequalification timer fault state
can occur. During the timer fault state, the charger stops
delivering current to the battery and the battery remains
disconnected from the system. To exit the prequalification
timer fault state, toggle the charger enable (CHG_EN)
bit or unplug and replug the external voltage source con-
nected to CHGIN.
is programmable with CHG_CV[5:0] from 3.6V to
CHG
4.6V. The charger holds the battery's voltage constant
at V while in the fast-charge (CV) state. As
FAST-CHG
the battery approaches full, the current accepted by the
battery reduces. When the charger detects that battery
charge current has fallen below I
machine enters the top-off state.
, the charger state
TERM
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The THM_DTLS[2:0] bitfield reports battery tempera-
ture status. See the Adjustable Thermistor Temperature
Monitors section and refer to the Programmer’s Guide for
more information.
Fast-Charge Timer Fault State
The charger enters the fast-charge timer fault state if the
fast-charge safety timer expires. While in this state, the
charger stops delivering current to the battery and the
battery remains disconnected from the system. To exit
the fast-charge timer fault state, toggle the charger enable
bit (CHG_EN) or unplug and replug the external voltage
source connected to CHGIN.
JEITA-Modified States
If the thermistor is enabled (THM_EN = 1), then the char-
ger state machine is allowed to enter the JEITA-modified
states. These states are entered if the charger's tem-
perature monitors indicate that the battery temperature
Battery Temperature Fault State
is either warm (greater than T
) or cool (lesser than
WARM
If the thermistor monitoring circuit reports that the battery
is either too hot or too cold to charge (as programmed by
THM_HOT[1:0] and THM_COLD[1:0]), the state machine
enters the battery temperature fault state. While in this
state, the charger stops delivering current to the battery
and the battery remains disconnected from the system.
This state can only be entered if the thermistor is enabled
(THM_EN = 1). Battery temperature fault state has prior-
ity over any other fault state, and can be exited when the
thermistor is disabled (THM_EN = 0) or when the battery
returns to an acceptable temperature. When this fault
state is exited, the state machine returns to the last state it
was in before battery temperature fault state was entered.
T
). See the Adjustable Thermistor Temperature
COOL
Monitors section for more information about setting the
temperature thresholds.
The charger's current and voltage parameters change
from I
and V
to I
and
FAST-CHG
FAST-CHG
FAST-CHG_JEITA
V
while in the JEITA-modified states. The
FAST-CHG_JEITA
JEITA modified parameters can be independently set to
lower voltage and current values so that the battery can
charge safely over a wide range of ambient tempera-
tures. If the battery temperature returns to normal, or the
thermistor is disabled (THM_EN = 0) the charger exits the
JEITA-modified states.
All active charger timers (fast-charge safety timer,
prequalification timer, or top-off timer) are paused in this
state. Active timers resume when the state is exited.
Typical Charge Profile
A typical battery charge profile (and state progression) is
illustrated in Figure 13.
(V)
(mA)
500
400
CHGIN
5
SYS
V
= 4.5V
SYS-REG
BATT
V
= 4.25V
FAST-CHG
4
3
2
1
I
= 300mA
FAST-CHG
300
200
V
= 2.3V
PQ
I
BATT
100
t
TO
I
= 30mA
PQ
I
= 30mA
TERM
(TIME)
DONE
FAST-CHARGE (CV)
TOP-OFF
CHGIN
FAST-CHARGE (CC)
INVALID
PREQUALIFICATION
Figure 13. Example Battery Charge Profile
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10μF). The effective value of the CHGIN capacitor must
be greater than 1µF when biased with 5V.
Charger Applications Information
Configuring a Valid System Voltage
Bypass SYS to GND with a 22μF ceramic capacitor.
This capacitor is needed to ensure stability of SYS while
it is being regulated from CHGIN. Since SYS must be
connected to IN_SBB, then one capacitor can be used
to bypass this node as long as it is physically close to
the device. Larger values of SYS capacitance increase
decoupling for all SYS loads. When biased with 4.5V, the
effective value of the SYS capacitor must be greater than
4μF and no more than 100μF.
The smart power selector begins to regulate SYS to
V
when CHGIN is connected to a valid source. To
SYS-REG
ensure the charger's accuracy specified in the Electrical
Characteristics table, the system voltage must always
be programmed at least 200mV above the charger's
constant-voltage level (V
). If this condition is not
FAST-CHG
met, then the charger's internal configuration logic forces
to reduce to satisfy the 200mV requirement. If
V
FAST-CHG
this happens, the charger asserts the SYS_CNFG_I inter-
rupt to alert the user that a configuration error has been
made and that the bits in CHG_CV[5:0] have changed to
Bypass BATT to GND with a 4.7μF ceramic capacitor.
This capacitor is required to ensure stability of the BATT
voltage regulation loop. When biased with 4.5V, the effec-
tive value of the BATT capacitor must be greater than 1μF.
reduce V
.
FAST-CHG
CHGIN/SYS/BATT Capacitor Selection
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufac-
turer's data sheet.
Bypass CHGIN to GND with a 4.7μF ceramic capacitor to
minimize inductive kick caused by long cables between
the DC charge source and the device. Larger values
increase decoupling for the linear charger, but increase
inrush current from the DC charge source when the
device is first connected to a source through a cable/plug.
If the DC charging source is an upstream USB device,
limit the maximum CHGIN input capacitance based on
the appropriate USB specification (typically no more than
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enables the charger to operate safely over the JEITA tem-
perature range. When the thermistor is enabled (THM_EN
= 1), the charger continuously monitors the voltage at the
THM pin in order to sense the temperature of the battery
being charged.
Adjustable Thermistor Temperature
Monitors
The optional use of a negative temperature coeffi-
cient (NTC) thermistor (thermally coupled to the battery)
MAX77650/
MAX77651
CHG_CV[5:0]
D0
D1
1.25V
V
FAST-CHG
TBIAS
CHG_CV_JEITA[5:0]
S0
S0
TBIAS SWITCH
CONTROL
(FIGURE 16)
CHG_CC[5:0]
D0
D1
R
BIAS
I
FAST-CHG
CHG_CC_JEITA[5:0]
THM
INTERNAL COOL/WARM SIGNAL
THM_DTLS[2:0] = 0b000 OR 0b101 (NTC
DISABLED OR BATTERY NORMAL).
CHARGER V&I PARAMETERS FOLLOW
THM_COLD[1:0]
0b0
NTC
NORMAL SETTINGS.
THM_DTLS[2:0] = 0b010 OR 0b011
(BATTERY COOL OR WARM). CHARGER
V&I PARAMETERS SWITCH TO JEITA
THM_EN
THM_COOL[1:0]
THM_WARM[1:0]
THM_HOT[1:0]
0b1
SETTINGS.
INTERNAL HOT/COLD SIGNAL
THM_DTLS[2:0] ≠ 0b001 OR 0b100
(BATTERY NOT COLD OR HOT). CHARGER
V&I PARAMETERS FOLLOW NORMAL OR
0b0
JEITA SETTINGS.
THM_DTLS[2:0] = 0b001 OR 0b100
0b1 (BATTERY COLD OR HOT). CHARGING IS
PAUSED REGARDLESS OF CHG_EN.
Figure 14. Thermistor Logic Functional Diagram
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Ultra-Low Power PMIC with 3-Output SIMO
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See Figure 15 for a visual example of what is described
here in text.
● If the battery temperature is either above T
or below
HOT
T , the charger follows the JEITA recommendation
COLD
and pauses charging. The charger state machine enters
battery temperature fault state while charging is paused
due to extreme high or low temperatures.
● If the battery temperature is higher than T
and
COOL
lower than T , the battery charges normally with
WARM
the normal values for V
and I
. The
FAST-CHG
FAST-CHG
The battery's temperature status is reflected by the
THM_DTLS[2:0] status bitfield. A maskable interrupt
(THM_I) signals a change in THM_DTLS[2:0]. Refer to
the Programmer’s Guide for more information. To com-
pletely disable the charger's automatic response to bat-
tery temperature, disable the feature by programming
THM_EN = 0.
charger state machine does not enter JEITA-modified
states while the battery temperature is normal.
● If the battery temperature is either above T
WARM
but below T
, or, below T
but above T
,
HOT
COOL
COLD
the battery charges with the JEITA-modified volt-
age and current values. These modified values,
V
and I , are pro-
FAST-CHG_JEITA
FAST-CHG_JEITA
grammable through CHG_CV_JEITA[5:0] and
CHG_CC_JEITA[5:0], respectively. These values are
independently programmable from the nonmodified
The voltage thresholds corresponding to the JEITAtemper-
ature thresholds are independently programmable through
THM_HOT[1:0], THM_WARM[1:0], THM_COOL[1:0], and
THM_COLD[1:0]. Each threshold can be programmed
to one of four voltage options spanning 15°C for an
NTC beta of 3380K. See the Configurable Temperature
Thresholds section and refer to the Programmer’s Guide
for more information.
V
and I
values and can even
FAST-CHG
FAST-CHG
be programmed to the same values if an automatic
response to a warm or cool battery is not desired. The
charger state machine enters JEITA-modified states
while the battery temperature is outside of normal.
EXAMPLE TEMPERATURES
FOR NTC β = 3380K
THM_COLD[1:0] = 0b10 (0°C)
THM_COOL[1:0] = 0b11 (15°C)
THM_WARM[1:0] = 0b10 (45°C)
THM_HOT[1:0] = 0b11 (60°C)
4.4V
4.3V
4.2V
4.1V
4.0V
V
= 4.2V
FAST-CHG
(CHG_CV[5:0] = 0b011000)
V
= 4.075V
FAST-CHG_JEITA
(CHG_CV_JEITA[5:0] = 0b010011)
COLD
COOL
NORMAL
25°C
WARM
HOT
75°C
-40°C
-25°C
0°C
15°C
45°C
60°C
85°C
T
COLD
T
T
T
HOT
COOL
WARM
BATTERY TEMPERATURE
I
= 150mA
FAST-CHG
(CHG_CC[5:0] = 0b010011)
0.15
0.1
0.05
0
I
= 75mA
FAST-CHG_JEITA
(CHG_CC_JEITA[5:0] = 0b001001)
COLD
COOL
NORMAL
WARM
HOT
-40°C
-25°C
0°C
15°C
25°C
45°C
60°C
75°C
85°C
T
T
COOL
T
T
HOT
COLD
WARM
BATTERY TEMPERATURE
Figure 15. Safe-Charging Profile Example
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The NTC thermistor's bias source (TBIAS) follows the
simple operation outlined below:
Thermistor Bias
An external ADC can optionally perform conversions on
the THM and TBIAS pins to measure the battery's tem-
perature. An on-chip analog multiplexer is used to route
these nodes to the AMUX pin. The operation of the analog
multiplexer does not interfere with the charger's tempera-
ture monitoring comparators or the charger's automatic
JEITA response. See the Analog Multiplexer & Power
Monitor AFEs section for more information.
● If CHGIN is valid and the thermistor is enabled
(THM_EN = 1), then the thermistor is biased so the
charger can automatically respond to battery tem-
perature changes.
●
If the analog multiplexer is connecting THM or
TBIAS to AMUX, then the thermistor is biased so an
external ADC can perform a meaningful temperature
conversion.
The AMUX pin is a buffered output. The operation of the
analog multiplexer and external ADC does not collide with
the function of the on-chip temperature monitors. Both
functions may be used simultaneously with no ill effect.
THERMISTOR BIASED
TBIAS = 1.25V
Configurable Temperature Thresholds
Temperature thresholds for different NTC thermistor beta
values are listed in Table 4. The largest possible program-
mable temperature range can be realized by using an NTC
with a beta of 3380K. Using a larger beta compresses the
temperature range. The trip voltage thresholds are pro-
grammable with the THM_HOT[1:0], THM_WARM[1:0],
THM_COOL[1:0], and THM_COLD[1:0] bitfields. All pos-
sible programmable trip voltages are listed in Table 4.
MUX_SEL ≠ 0b0111 or 0b1000
AND
(THM_EN = 0 OR CHGIN INVALID)
MUX_SEL = 0b0111 or 0b1000
OR
(THM_EN = 1 AND CHGIN VALID)
THERMISTOR OFF
TBIAS = GND
These are theoretical values computed by a formula.
Refer to the particular NTC's data sheet for more accurate
measured data. In all cases, select the value of R
to
BIAS
be equal to the NTC's effective resistance at +25°C.
Figure 16. Thermistor Bias State Diagram
Table 4. Trip Temperatures vs. Trip Voltages for Different NTC β
TRIP TEMPERATURES (°C)
TRIPVOLTAGE
(V)
3380K
-10.0
-5.0
3435K
-9.5
3940K
-5.6
4050K
-4.8
4100K
-4.5
4250K
-3.5
0.6
1.024
0.976
0.923
0.867
0.807
0.747
0.511
0.459
0.411
0.367
0.327
0.291
-4.6
-1.1
-0.5
-0.2
0.0
0.3
3.3
3.8
4.1
4.8
5.0
5.3
7.7
8.1
8.3
8.9
10.0
15.0
35.0
40.0
45.0
50.0
55.0
60.0
10.2
15.1
34.8
39.8
44.7
49.6
54.5
59.4
12.0
16.4
33.5
37.8
42.0
46.2
50.4
54.6
12.4
16.6
33.3
37.4
41.5
45.6
49.7
53.7
12.5
16.7
33.2
37.3
41.3
45.3
49.3
53.3
12.9
17.0
32.9
36.8
40.7
44.6
48.4
52.2
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Figure 17
Thermistor Applications Information
Using Different Thermistor β
TBIAS
If an NTC with a beta larger than 3380K is used and the
resulting available programmable temperature range is
undesirably small, then two adjusting resistors can be
R
BIAS
used to expand the temperature range. R and R can
S
P
THM
be optionally added to the NTC thermistor circuit shown
in Figure 17 to expand the range of programmable tem-
perature thresholds.
R
S
R
P
Select values for R and R based on the information
S
P
shown in Table 5.
NTC
NTC Thermistor Selection
Popular NTC thermistor options are listed in Table 6.
Figure 17. Thermistor Circuit with Adjusting Series and Parallel
Resistors
Table 5. Example R and R Correcting Values for NTC β Above 3380K
S
P
PARAMETER
NTC thermistor beta
25°C NTC resistance
UNIT DESIGN TARGET CASE
CASE 1
3940
10
CASE 2
4050
47
CASE 3
4250
100
K
3380
10
R
10
10
47
100
BIAS
Adjusting parallel resistor, R
open
short
45.24
22.61
5.81
open
200
0.62
open
680
3.3
open
1300
9.1
P
Adjusting series resistor, R
short
45.24
22.61
5.81
short
212.6
106.3
27.3
short
452.4
226.1
58.1
S
kΩ
R
R
R
R
at 1.024V
at 0.867V
at 0.459V
at 0.291V
threshold
threshold
threshold
578.5
248.8
5.36
306.1
122.7
25.1
684.8
264.7
51.7
NTC
COLD
COOL
WARM
NTC
NTC
threshold
HOT
3.04
3.04
2.46
14.3
112.7
-11.14
5.33
30.4
22.0
NTC
T
T
T
T
at V
at V
at V
at V
(-10°C expected)
(5°C expected)
(40°C expected)
-10.03
4.98
-5.56
7.66
-9.96
5.76
-4.82
8.10
-3.55
8.86
-10.46
5.94
ACTUAL
ACTUAL
ACTUAL
ACTUAL
COLD
COOL
WARM
°C
40.02
60.04
37.79
54.56
39.76
60.37
37.43
53.68
39.40
60.02
36.82
52.21
39.48
60.4
(60°C expected)
HOT
Table 6. NTC Thermistors
Β-CONSTANT
(25°C/50°C)
MANUFACTURER
PART
R (Ω) AT 25°C
CASE SIZE
TDK
NTCG063JF223HTBX
NCP03XH103F05RL
NCP15XH103F03RC
NTCG103JX103DT1
CMFX3435103JNT
3380K
3380K
3380K
3380K
3435K
3900K
4050K
4100K
4250K
22k
10k
10k
10k
10k
10k
47k
47k
100k
0201
0201
0402
0402
0402
0402
0201
0402
0402
Murata
Murata
TDK
Cantherm
Murata
Panasonic
Panasonic
Murata
NCP15XV103J03RC
ERT-JZEP473J
ABNTC-0402-473J-4100F-T
NCP15WF104F03RC
Maxim Integrated
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
device's main bias is active and a channel is selected
(MUX_SEL[3:0] ≠ 0b0000). Disable the buffer by pro-
gramming to MUX_SEL[3:0] to 0b0000 when not actively
converting the voltage on AMUX.
Analog Multiplexer & Power Monitor AFEs
An external ADC can be used to measure the chip's vari-
ous signals for general functionality or on-the-fly power
monitoring. The MUX_SEL[3:0] bitfield controls the inter-
nal analog multiplexer responsible for connecting the
proper channel to the AMUX pin. Each measurable signal
is listed below with its appropriate multiplexer channel.
The voltage on the AMUX pin is a buffered output that
Table 7 shows how to translate the voltage signal on the
AMUX pin to the value of the parameter being measured.
See the Electrical Characteristics—Analog Multiplexer and
Power Monitor AFEs table and refer to the Programmer’s
Guide for more details.
ranges from 0V to V
(1.25V typ). The buffer has a
FS
50μA quiescent current draw and is only active when the
Table 7. AMUX Signal Transfer Functions
MUX_SEL
FULL-SCALE
SIGNAL
MEANING
ZERO-SCALE
SIGNAL
MEANING
SIGNAL
TRANSFER FUNCTION
[3:0]
(V
= 1.25V)
(V
= 0V)
AMUX
AMUX
V
CHGIN pin
voltage
AMUX
0b0001
7.5V
0V
V
=
=
=
CHGIN
G
VCHGIN
V
CHGIN pin
current
AMUX
0b0010
0b0011
0b0100
0.475A
4.6V
0A
0V
I
CHGIN
G
ICHGIN
V
BATT pin
voltage
AMUX
V
BATT
G
VBATT
BATT pin
charging
current
V
100% of I
0% of
AMUX
FAST-CHG
I
=
× I
FAST − CHG
BATT CHG
(
)
V
(CHG_CC[5:0])
I
FAST-CHG
FS
BATT pin
discharge
current
100% of
V
− V
(
)
AMUX
NULL
)
0% of
0b0101
0b0110
I
I
=
)
× I
DISCHG-SCALE
DISCHG − SCALE
BATT DISCHG
(
I
DISCHG-SCALE
0V
V
− V
(
FS
NULL
(IMON_DISCHG_SCALE[3:0])
BATT pin
discharge
current NULL
1.25V
V
= V
AMUX
NULL
THM pin
voltage
0b0111
0b1000
0b1001
1.25V
1.25V
1.25V
0V
0V
0V
V
= V
AMUX
THM
TBIAS pin
voltage
V
= V
TBIAS
AMUX
AGND pin
voltage*
V
= V
AGND
AMUX
V
SYS pin
voltage
AMUX
0b1010
4.8V
0V
V
=
SYS
G
VSYS
*AGND pin voltage is accessed through a 100Ω (typ) pulldown resistor. Setting MUX_SEL[3:0] to 0b0000 disables the multiplexer
and changes the AMUX pin to a high-impedance state.
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
● Convert the voltage on AMUX pin and use the following
Measuring Battery Current
transfer function to determine the discharge current.
It is possible to sample the current in the BATT pin at any
time or in any mode with an external ADC. For improved
accuracy, the analog circuitry used for monitoring battery
discharge current is different from the circuitry monitoring
battery charge current. Table 8 outlines how to determine
the direction of battery current.
V
−
V
(
)
AMUX
V
NULL
I
=
)
× I
DISCHG − SCALE
BATT DISCHG
(
− V
(
)
FS
NULL
V
is 1.25V (typ). I
is programmable
FS
DISCHG-SCALE
through IMON_DISCHG_SCALE[3:0]. The default value
is 300mA. If smaller currents are anticipated, then
Method for Measuring Discharging Current
I
can be reduced for improved measure-
● Program the multiplexer to switch to the discharge
NULL measurement by changing MUX_SEL[3:0] to
0b0110. A NULL conversion must always be per-
formed first to cancel offsets.
● Wait the appropriate channel switching time (0.3μs
typ).
DISCHG-SCALE
ment accuracy.
Method for Measuring Charging Current
● Program the multiplexer to switch to the charge
current measurement by changing MUX_SEL[3:0] to
0b0100.
● Wait the appropriate channel switching time (0.3μs
typ).
● Convert the voltage on the AMUX pin and store as
V
NULL
.
● Program the multiplexer to switch to the battery
discharge current measurement by changing MUX_
SEL[3:0] to 0b0101. A nonnulling conversion should
be done immediately after a NULL conversion.
● Wait the appropriate channel switching time (0.3μs
typ).
● Convert the voltage on the AMUX pin and use the fol-
lowing transfer function to determine charging current.
V
AMUX
I
=
)
× I
FAST − CHG
BATT CHG
(
V
FS
V
is 1.25V (typ). I
the charger's fast-charge
FS
FAST-CHG
constant-current setting and is programmable through
CHG_CC[5:0].
Table 8. Battery Current Direction Decode
CHARGING OR DISCHARGING INDICATORS
MEASUREMENT
CHG BIT
CHG_DTLS[3:0]
CHGIN_DTLS[1:0]
Discharging Battery Current
(Positive Battery Terminal Sourcing Current
into the BATT pin of MAX77650/MAX77651)
0b00
0b01
0b10
Don't care
1
Don't care
Charging Battery Current
(Positive Battery Terminal Sinking Current from
the BATT pin of MAX77650/MAX77651)
0b0001–0b0111
0b11
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
SIMO Benefits and Features
● 3 Output Channels
● Ideal for Low-Power Designs
• Delivers > 300mA at 1.8V from a 3.7V Input
• ±3% Accurate Output Voltage
● Small Solution Size
• Multiple Outputs from a Single 1.5μH (0603) Inductor
• Small 10μF (0402) Output Capacitors
● Flexible and Easy to Use
SIMO Buck-Boost
The device has a micropower single-inductor, multiple-out-
put (SIMO) buck-boost DC-to-DC converter designed for
applications that emphasize low supply current and small
solution size. A single inductor is used to regulate three
separate outputs, saving board space while delivering
better total system efficiency than equivalent power solu-
tions using one buck and linear regulators.
The SIMO configuration utilizes the entire battery voltage
range due to its ability to create output voltages that are
above, below, or equal to the input voltage. Peak induc-
tor current for each output is programmable to optimize
the balance between efficiency, output ripple, EMI, PCB
design, and load capability.
• Single Mode of Operation
• Programmable Peak Inductor Current
• Programmable On-Chip Active Discharge
● Long Battery Life
• High Efficiency, > 87% at 3.3V Output
• Better Total System Efficient than Buck + LDOs
• Low Quiescent Current, 1μA per Output
• Low Input Operating Voltage, 2.7V (min)
3300pF
(0201)
1.5µH
LXA
LXB
BST
IN_SBB
SBB0
MAX77650/MAX77651
SYNCHRONOUS RECTIFIER
MAIN POWER STAGE
IN_SBB
REVERSE
BLOCKING
SYS
10µF
(0402)
PGND
M1
BST
10µF
(0402)
DRV_SBB
M3_0
DIS_SBB1
IZX
ERROR COMPARATOR
ACTIVE-DISCHARGE
ILIM
DRV_SBB
CHG
M2
M4
REG0
DIS
R
AD_SSB0
AD_SBB0
(140Ω)
SBB1
SBB2
I.LIM
I.ZX
REG[2:0]
SYNCHRONOUS
RECTIFIER (M3_1)
AND
ERROR COMPARATOR
AND
CHG
DIS
DIS_SBB[2:0]
BST
DRV_SBB
DIS_SBB1
10µF
(0402)
SIMO
CONTROLLER
REG1
VREF
VIREF
AD_SBB1
ACTIVE-DISCHARGE
DIGITAL AND
REGISTERS
CNFG_SBB_TOP,
CNFG_SBBX_A,
CNFG_SBBX_B
SYNCHRONOUS
RECTIFIER (M3_2)
AND
ERROR COMPARATOR
AND
COMM
FPS
DRV_SBB
AD_SBB[2:0]
BST
DRV_SBB
DIS_SBB2
10µF
(0402)
REG2
SYS_RST
AD_SBB2
ACTIVE-DISCHARGE
Figure 18. SIMO Detailed Block Diagram
Maxim Integrated
│ 64
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
For example, given the following conditions, the peak
SIMO Control Scheme
input current (I ) during soft-start is ~71mA:
IN
The SIMO buck-boost is designed to service multiple out-
puts simultaneously. A proprietary controller ensures that
all outputs get serviced in a timely manner, even while
multiple outputs are contending for the energy stored in
the inductor. When no regulator needs service, the state
machine rests in a low-power rest state.
Given:
● V is 3.5V
IN
● V
● C
is 3.3V
= 10µF
SBB2
SBB2
● dV/dt = 5mV/µs
SS
● R
● ξ is 80%
= 330Ω (I
= 3.3V/330Ω = 10mA)
LOAD2
LOAD2
When the controller determines that a regulator requires
service, it charges the inductor (M1 + M4) until the peak
current limit is reached (I
= I
). The inductor
Calculation:
LIM
P_SBB
energy then discharges (M2 + M3_x) into the output until
● I
● I
= 10µF x 5mV/µs (from Equation 1)
= 50mA
CSBB
CSBB
the current reaches zero (I ). In the event that multiple
ZX
output channels need servicing at the same time, the con-
troller ensures that no output utilizes all of the switching
cycles. Instead, cycles interleave between all the outputs
that are demanding service, while outputs that do not
need service are skipped.
3.3V
3.5V
50mA + 10mA
=
0.85
(
)
●
(from Equation1)
I
IN
● I ~ 71mA
IN
SIMO Registers
SIMO Soft-Start
The soft-start feature of the SIMO limits inrush current dur-
ing startup. The soft-start feature is achieved by limiting
the slew rate of the output voltage during startup to dV/dt
(5mV/μs typ).
Each SIMO buck-boost channel has a dedicated register
to program its target output voltage (TV_SBBx) and its
peak current limit (IP_SBBx). Additional controls are avail-
able for enabling/disabling the active discharge resistors
(ADE_SBBx), as well as enabling/disabling the SIMO
buck-boost channels (EN_SBBx). For a full description of
bits, registers, default values, and reset conditions, refer
to the Programmer’s Guide.
SS
More output capacitance results in higher input current
surges during startup. The following set of equations and
example describes the input current surge phenomenon
during startup.
SIMO Active Discharge Resistance
The current into the output capacitor (I ) during soft-start is:
CSBB
Each SIMO buck-boost channel has an active-discharge
resistor (R
) that is automatically enabled/dis-
AD_SBBx
abled based on a ADE_SBBx and the status of the SIMO
regulator. The active discharge feature can be enabled
(ADE_SBBx = 1) or disabled (ADE_SBBx = 0) indepen-
dently for each SIMO channel. Enabling the active dis-
charge feature helps ensure a complete and timely power
down of all system peripherals. If the active-discharge
resistor is enabled by default, then the active-discharge
dV
I
= C
(Equation 1)
CSBB
SBB
dt
SS
where C
is the capacitance on the output of the regula-
tor, and dV/dt is the voltage change rate of the output.
SBB
SS
The input current (I ) during soft-start is:
IN
resistor is on whenever V
is below V
and
SYS
SYSUVLO
above V
.
POR
V
SBBx
I
+ I
These resistors discharge the output when ADE_SBBx
= 1, and their respective SIMO channel is off. Note if
the regulator is forced on through EN_SBBx = 0b110 or
0b111, then the resistors do not discharge the output even
if the regulator is disabled by the main-bias.
(
)
CSBB LOAD
V
IN
I
=
(Equation 2)
IN
ξ
where I
is from the calculation above, I
is cur-
LOAD
CSBB
rent consumed from the external load, V
is the output
Note that when V
tors that control the active discharge resistors lose their
gate drive and become open.
is less than 1.0V, the NMOS transis-
SBBx
SYS
voltage, and V is the input voltage, ξ is the efficiency of
IN
the regulator.
Maxim Integrated
│ 65
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Choose the inductor saturation current to be greater than
or equal to the maximum peak current limit setting that is
SIMO Applications Information
SIMO Available Output Current
used for all of the SIMO buck-boost channels (I
).
P_SBB
The available output current on a given SIMO channel is
a function of the input voltage, output voltage, peak cur-
rent limit setting, and the output current of the other SIMO
channels. Maxim offers a SIMO calculator that outlines
the available capacity for specific conditions. See Support
Materials for more information on this and other engineer-
ing resources. Table 9 is an extraction from the calculator.
For example, if SBB0 is set for 0.5A, SBB1 is set for
0.866A, and SBB2 is set for 1.0A, then choose the satura-
tion current to be greater than or equal to 1.0A.
Choose the RMS current rating of the inductor (typically
the current at which the temperature rises appreciably)
based on the expected load currents for the system. For
systems where the expected load currents are not well
known, be conservative and choose the RMS current to
be greater than or equal to the half of higher maximum
Inductor Selection
Choose an inductance from 1.0μH to 2.2uH; 1.5μH induc-
tors work best for most designs. Larger inductances
transfer more energy to the output for each cycle and
typically result in larger output voltage ripple and better
efficiency. See the Output Capacitor Selection section for
more information on how to size your output capacitor in
order to control ripple.
peak current limit setting [I
>=MAX(IP_SBB0, IP_
RMS
SBB1, IP_SBB2)/2]. This is a safe/conservative choice
because the SIMO buck-boost regulator implements a
discontinuous conduction mode (DCM) control scheme,
which returns the inductor current to zero each cycle.
Consider the DC-resistance (DCR), AC-resistance (ACR)
and solution size of the inductor. Typically, smaller
sized inductors have larger DC-resistance and larger
AC-resistance that reduces efficiency and the available
output current. Note that many inductor manufacturers
have inductor families which contain different versions
of core material in order to balance trade-offs between
DCR, ACR (i.e., core losses), and component cost. For
this SIMO regulator, inductors with the lowest ACR in
the 1.0MHz to 2.0MHz region tend to provide the best
efficiency.
Table 9. SIMO Available Output Current
for Common Applications
PARAMETERS EXAMPLE 1 EXAMPLE 2 EXAMPLE 3
V.IN.MIN
R.L.DCR
SBB1
2.7V
3.2V
3.4V
0.1Ω
0.1Ω
0.12Ω
1V at 100mA 1.2V at 50mA 1.2V at 20mA
2.05V at
SBB0
1.2V at 75mA
2.05V at 80mA
100mA
1.8V at 50mA 3.3V at 30mA 3.3V at 10mA
SBB2
See Table 10 for examples of inductors that work well
with this device. This table was created in 2016. Inductor
technology advances rapidly. Always consider the most
current inductor technology for new designs to achieve
the best possible performance.
I.PEAK.0
I.PEAK.1
I.PEAK.2
1A
1A
1A
0.866A
0.707A
1A
0.5A
0.5A
0.5A
Utilized
Capacity
73
79
73
*R.C.IN = R.C.OUT = 5mΩ, L = 1.5μH
Table 10. Example Inductors
MANUFACTURER
Samsung
Murata
PART
CIGT201610EH2R2MN
DFE201610E-2R2M
DFE201610E-1R5M
DFE201210S-2R2M
DFE201210S-1R5M
CIGT201208EH2R2MN
DFE201208S-1R5M
DFE201208S-2R2M
L (µH)
2.2
I
(A)
I
(A) DCR (Ω) X (mm) Y (mm) Z (mm)
RMS
SAT
2.9
2.7
0.073
0.117
0.076
0.127
0.086
0.095
0.110
0.170
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
1.6
1.6
1.6
1.2
1.2
1.25
1.2
1.2
1.0
1.0
1.0
1.0
1.0
0.8
0.8
0.8
2.2
2.6
2.4
2.3
2.2
2.0
2.4
2.0
1.9
3.2
1.80
2.6
1.8
2.0
1.6
Murata
1.5
Murata
2.2
Murata
1.5
Samsung
Murata
2.2
1.5
Murata
2.2
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Note that most designs concern themselves with having
Input Capacitor Selection
enough capacitance on the output but there is also a
maximum capacitance limitation that is calculated within
the SIMO Calculator; take care not to exceed the maxi-
mum capacitance.
Choose the input bypass capacitance (C
) to be
IN_SBB
10µF. Larger values of C
for the SIMO regulator.
improve the decoupling
IN_SBB
C
reduces the current peaks drawn from the battery
IN_SBB
C
is required to keep the output voltage ripple small.
SBBx
or input power source during SIMO regulator operation and
reduces switching noise in the system. The ESR/ESL of the
input capacitor should be very low (i.e., ≤ 5mΩ + ≤ 500pH)
for frequencies up to 2MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
The impedance of the output capacitor (ESR, ESL) should
be very low (i.e., ≤ 5mΩ + ≤ 500pH) for frequencies up to
2MHz. Ceramic capacitors with X5R or X7R dielectric are
highly recommended due to their small size, low ESR,
and small temperature coefficients.
A capacitor's effective capacitance decreases with
increased DC bias voltage. This effect is more pro-
nounced as capacitor case sizes decrease. Due to this
characteristic, it is possible for an 0603 case size capaci-
tor to perform well, while an 0402 case size capacitor of
the same value performs poorly. The SIMO regulator is
stable with low output capacitance (1μF) but the output
voltage ripple would be large; consider the effective out-
put capacitance value after initial tolerance, bias voltage,
aging, and temperature derating.
To fully utilize the available input voltage range of the
SIMO (5.5V max), use a 6.3V capacitor voltage rating.
IN_SBB is a critical discontinuous current path that
requires careful bypassing. When the SIMO detects that
an output is below its regulation threshold, a switching
cycle begins and the IN_SBB current ramps up as a func-
tion of the input voltage and inductor (di/dt = V
/L)
IN_SBB
until it reaches the peak current limit (I
). Once
P_SBB
I
is reached, the IN_SBB current falls to zero
P_SBB
rapidly (~5ns). This rapid current decrease makes the
parasitic inductance in the PGND to input capacitor to
SBBx is a critical discontinuous current path that requires
careful bypassing. When the SIMO detects that an output
is below its target, it charges the inductor to a peak cur-
IN_SBB path critical. In the PCB layout, place C
as
IN_SBB
close as possible to the power pins (IN_SBB and PGND)
to minimize parasitic inductance. If making connections
to the input capacitor through vias, ensure that the vias
are rated for the expected input current so they do not
contribute excess inductance and resistance between the
bypass capacitor and the power pins.
rent limit (I
) and then discharges that inductor into
P_SBB
the output. At the moment the charge is applied to the
output, the current increases rapidly and then decays
relatively slowly (dt/dt = V
/L). This rapid current
OUT
increase is a function of the drive strength setting (DRV_
SBB) and makes the parasitic inductance in the SBBx to
output capacitor to PGND path critical. In the PCB layout,
Boost Capacitor Selection
Choose the boost capacitance (C
) to be 3.3nF. Smaller
place C
as close as possible to SBBx and PGND
BST
SBBx
values of C
(< 1nF) result in insufficient gate drive for
to minimize parasitic inductance. If making connections
to the output capacitor through vias, ensure that the vias
are rated for the expected output current so they do not
contribute excess inductance and resistance.
BST
M3. Larger values of C
(> 10nF) have the potential
BST
to degrade the startup performance. Ceramic capacitors
with 0201 or 0402 case size are recommended.
Output Capacitor Selection
SIMO Switching Frequency
Choose each output bypass capacitance (C
) based
The SIMO buck-boost regulator utilizes a pulse frequency
modulation (PFM) control scheme. The switching fre-
quency for each output is a function of the input voltage,
output voltage, load current, and inductance. Maxim
offers a SIMO calculator to aid in the understanding of the
switching frequency.
SBBx
on the desired output voltage ripple; typical values are
10µF. Larger values of C improve the output volt-
SBBx
age ripple but increase the input surge currents during
soft-start and output voltage changes. The output voltage
ripple is a function of the inductance, the output voltage,
and the peak current limit setting. Maxim offers a SIMO
calculator to aid in the selection of the output capacitance.
See Support Materials for more information on this and
other engineering resources.
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
At no load, switching frequencies can be as low as 10Hz.
It is possible to get SIMO switching frequencies that are
high (5.7MHz) with all of the worst-case conditions: high
input voltage (4.5V), low inductance (1.0µH), high output
voltage (5.0V), low peak current limit (0.5A), and high
utilization (80% which is 90mA with these conditions).
With these high switching frequencies, the SIMO effi-
ciency is poor. The maximum switching frequencies for
designs should be no more than 3MHz. For example, in
the 5.7MHz example above if we change the inductance
to peak current limit from 0.5A to 0.707A while leaving the
load current at 90mA, then the switching frequency drops
to 2.4MHz. If we put the peak current limit at 0.866A and
change the inductance to 1.5µH, then the switching fre-
quency drops to 1MHz which provides a “nice” efficiency.
external component for the unused output. Unlike the
option above, this connection is preferred in cases
where the unused output voltage bias level is always
above the unused output voltage target because no
energy packages are provided to the unused output.
• Note that some OTP options of the device have the
active-discharge resistors enabled by default (ADE_
SBBx). If the other power output used to bias the
unused output is normally off, then the active-dis-
charge resistor of the unused output does not cre-
ate a continuous current draw. Remember that once
the system is enabled, it should turn off the unused
output's active-discharge resistor (ADE_SBBx = 0).
LDO
The device includes one on-chip low-dropout linear regu-
lator (LDO). This LDO is optimized to have low-quiescent
current and low dropout voltage. The input voltage range
Unused Outputs
Do not leave unused outputs unconnected. If an output
left unconnected is accidentally enabled, inductor current
dumps into an open pin, and the output voltage can soar
above the absolute maximum rating, potentially causing
damage to the device. If the unused output is always
disabled (EN_SBBx = 0x4 or 0x5), connect that output to
ground. If an unused output can be enabled at any point
during operation (such as startup or accidental software
access), then implement one of the following:
of this LDO (V
) allows it to be powered directly
IN_LDO
from the main energy source such as a Li-Poly battery or
from an intermediate regulator. The linear regulator deliv-
ers up to 150mA.
Features
● 150mA LDO
● 1.8V to 5.5V Input Voltage Range
● Adjustable Output Voltage
● 180mV Maximum Dropout Voltage
● Programmable On-Chip Active Discharge
● Bypass the unused output with a 1µF ceramic capacitor
to ground.
● Connect the unused output to the power input (IN_
SBB). This connection is beneficial because it does
not require an external component for the unused
output. The power input and its capacitance receives
the energy packets when the regulator is enabled
LDO Simplified Block Diagram
The LDO has one input (IN_LDO) and one output (LDO)
and several ports that exchange information with the rest
of the device (VREF, EN_LDO, ADE_LDO). VREF comes
from the main bias circuits. EN_LDO and ADE_LDO
are register bits for controlling the enable and active-
discharge feature of the LDO. Refer to the Programmer’s
Guide for more information.
and V
is below the target output voltage of
IN_SBB
the unused output. Circulating the energy back to the
power input ensures that the unused output voltage
does not fly high.
• Note that some OTP options of the device have the
active-discharge resistors enabled by default (ADE_
SBBx) such that connecting an unused output SBBx
LDO Active Discharge Resistor
The LDO has an active-discharge resistor (R
that automatically enables/disables based on a configura-
tion bit (ADE_LDO) and the status of the LDO regulator.
Enabling the active discharge feature helps ensure a
complete and timely power down of all system peripherals.
The default condition of the active-discharge resistor fea-
)
AD_LDO
to IN_SBB creates a 140Ω (R
) to ground
AD_SBBx
until software can be ran to disable the active-dis-
charge resistor. Connecting an unused SBBx to
IN_SBB is not recommended if the regulator's
active-discharge resistor is enabled by default.
ture is enabled such that whenever V
is above V
SYS
POR
● Connect the unused output to another power output
that is above the target voltage of the unused output.
In the same way as the option listed above, this con-
nection is beneficial because it does not require an
and V
is above 1.0V, the LDO active discharge
IN_LDO
resistor is turned on. Note that when V
is less than
IN_LDO
1.0V, the NMOS transistor that controls the LDO active
discharge resistor loses its gate drive and becomes open.
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the LDO, then the two nodes can share the SBB0 output
LDO Soft-Start
The soft-start feature of the LDO limits inrush current dur-
ing startup. The soft-start feature is achieved by limiting the
capacitor (C
). C
SBB0
reduces the current peaks
IN_LDO
drawn from the battery or input power source during LDO
regulator operation.
slew rate of the output voltage during startup (dV/dt ).
SS
Choose the output capacitor (C
) so that the effective
LDO
More output capacitance results in higher input cur-
rent surges during startup. The equation and example
describes the input current surge phenomenon during
startup.
capacitance is equal to or greater than the value found
in Figure 19, based on expected load conditions for the
application. A single 10μF, 1005/0402 (mm/inch) capacitor
is recommended for typical applications, but ensure that
the load current and derated capacitance does not com-
promise the stability curve in Figure 19. Larger values of
The input current (I ) during soft-start is:
IN
dV
I
= C
+ I
LDO
IN
LDO
dt
C
improve stability and output PSRR, but increases
SS
LDO
the input surge currents during soft-start and output volt-
age changes. The effective output capacitance should not
exceed 100μF to maintain LDO stability.
where C
tor, and dV/dt
is the capacitance on the output of the regula-
LDO
is the voltage change rate of the output.
SS
For example, given the following conditions, the input
current (I ) during soft-start is 22.5mA:
For example, consider the case of the MAX77650A
where:
IN
Given:
1. Size is very important.
• C
= 10µF
LDO
• dV/dt = 1.25mV/µs
2. The LDO input is powered by SBB0, which is 2.05V.
3. The LDO output is 1.85V.
SS
• R
= 185Ω (I
= 1.85V/185Ω = 10mA)
LDO
LDO
Calculation:
• I = 10µF x 1.25mV/µs + 10mA
4. The LDO output current is ≤80mA.
IN
A small 1005/0402 (mm/inch) capacitor such as the
GRM155R60J106ME15 (Murata, 10μF, 6.3V X5R) gives
5.7μF at 60°C and 5.4μF at -20°C with the 1.85V bias
voltage and has a ± 20% tolerance, so the worst-case
effective capacitance is 4.3μF (5.4μF derated by 20%
tolerance). With just 4.3μF of capacitance at the output,
Figure 19 shows the LDO is stable with load currents of
≤35mA. To get stability at 80mA, 6μF is required. There
are a few options to consider:
• I = 22.5mA
IN
LDO Applications Information
Input and Output Capacitor Selection
Sufficient input bypass capacitance (C
) and output
IN_LDO
capacitance (C
) is required for stable operation of the
LDO
LDO. Figure 19 provides guidance on capacitor selection
and refers to required effective capacitance, which is the
actual value of capacitance seen by the LDO during oper-
ation. Effective capacitance is almost always lower than
the nominal capacitance and is a commonly overlooked
design parameter. Determine the effective capacitance
by assessing the capacitor’s initial tolerance, variation
with temperature, and variation with DC bias. Consult the
capacitor manufacturer for specific details of derating.
● Add more capacitors to the design.
● Replace the 1005/0402 (mm/inch) capacitor with a
1608/0603 (mm/inch) capacitor.
● Consider point-of-load capacitance in your assess-
ment of effective capacitance. For example, if there
is a point-of-load capacitor downstream from the
LDO that is sufficiently close to the local LDO output
capacitor, it can cover the gap. The capacitor can be
considered “sufficiently close” if the PCB does not
add more than 25nH and 25mΩ of extra ESR and
ESL (more or less within 1”).
Choose the input capacitor (C
) so that the effective
IN_LDO
capacitance is equal to or greater than the value found in
Figure 19, based on expected load conditions for the
application. A single 10μF, 1005/0402 (mm/inch) capaci-
tor, is recommended for typical applications but ensure
that the load current and derated capacitance does not
compromise the stability curve in Figure 19. Larger values
Note the impedance of either the input or output capacitor
(ESR, ESL) should be very low (i.e., ≤ 50mΩ + ≤ 5nH) for
frequencies up to 0.5MHz. Ceramic capacitors with X5R
or X7R dielectric are highly recommended due to their
small size, low ESR, and small temperature coefficients.
of C
improve stability and decoupling for the LDO
IN_LDO
regulator. The floorplan of the device is such that SBB0
is adjacent to IN_LDO, and if SBB0 powers the input of
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EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
EFFECTIVE LDO CAPACITANCE
REQUIRED FOR STABILITY
8
7
6
5
4
3
2
1
0
8
STABLE REGION
STABLE REGION
7
6
5
INPUT CAPACITANCE
OUTPUT CAPACITANCE
4
3
2
1
UNSTABLE REGION
UNSTABLE REGION
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 19. LDO Capacitance for Stability
IN_LDO
SBB0
10µF*
(0402)
*THE FLOORPLAN IS SUCH
THAT THE SBB0 OUTPUT
CAPACITOR IS ALSO THE
IN_LDO INPUT CAPACITOR.
VREF
EN_LDO
150mA
LDO
ADE_LDO
LDO
LDO
10µF
(0402)
R
ADE_LDO
Figure 20. LDO Simplified Block Diagram
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Current Sink Applications Information
LED Assignment
The three current sinks (LED0, LED1, LED2) are identi-
cal. In a typical application where a red, green, blue LED
cluster is used (RGB), the assignment of the RGB ele-
ments to the LED0/1/2 pins should be done in whatever
way makes the PCB layout the easiest.
Current Sinks
The device has a 3-channel current sink driver designed
to drive LED's in portable devices. This block can also be
used as a general-purpose current sink driver for other
applications. The driver's on-time and frequency are
independently programmable for each output to achieve
a desired blink pattern. Alternatively, the LEDs can be
continuously on (i.e., not blinking). The blink period is
programmable from 0.5s to 8s,with an on-time duty cycle
from 6.25% to 100%.
Unused Current Sink Ports
If a current sink port is not utilized in a given applica-
tion, connect that port to ground. Additionally, software
should ensure that the unused current sink is not enabled
(EN_LEDx = 0).
Figure 21 utilizes a common set of clock dividers to
drive three identical current sink modules. Refer to the
Programmer’s Guide for more information.
BIAS
CLK_64_S
CLK
CLOCK
DIVIDER
CLOCK DIVIDER
AND INVERTER
CLK_64
CLK_32
EN_LED_MSTR
CURRENT SINK
LED0
BRT_LED0[4:0]
DAC
INV_LED0
P_LED0[3:0]
D_LED0[3:0]
CLK_32
EN_LED0
PWM
LOGIC
2/4/8Ω
LED_FS0[1:0]
CURRENT SINK
LED1
BRT_LED1[4:0]
INV_LED0
P_LED1[3:0]
D_LED1[3:0]
CLK_32
LED_FS1[1:0]
CURRENT SINK
LED2
BRT_LED24:0]
INV_LED0
P_LED2[3:0]
D_LED2[3:0]
CLK_32
LGND
LED_FS2[1:0]
Figure 21. Current Sink Block Diagram
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2
2
functional diagram for the I C based communications
I C Serial Interface
2
controller. For additional information on I C, refer to the
I C Bus Specification and User Manual that is available
2
The MAX77650 features a revision 3.0 I C-compatible,
2-wire serial interface consisting of a bidirectional serial
data line (SDA) and a serial clock line (SCL). The
MAX77650/MAX77651 act as slave-only devices where
they rely on the master to generate a clock signal. SCL
2
for free on the Internet.
Features
2
● I C Revision 3 Compatible Serial Communications
2
clock rates from 0Hz to 3.4MHz are supported. I C is
Channel
an open-drain bus, and therefore, SDA and SCL require
pullups. Optional resistors (24Ω) in series with SDA and
SCL protect the device inputs from high-voltage spikes
on the bus lines. Series resistors also minimize crosstalk
and undershoot on bus signals. Figure 22 shows the
● 0Hz to 100kHz (Standard Mode)
● 0Hz to 400kHz (Fast Mode)
● 0Hz to 1MHz (Fast Mode Plus)
● 0Hz to 3.4MHz (High-Speed Mode)
2
● Does not utilize I C Clock Stretching
COMMUNICATIONS CONTROLLER
V
IO
SCL
SDA
INTERFACE
DECODERS
SHIFT REGISTERS
BUFFERS
GND
PERIPHERAL
0
PERIPHERAL
1
PERIPHERAL
2
PERIPHERAL
N-1
PERIPHERAL
N
2
Figure 22. I C Simplified Block Diagram
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SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER
2
Figure 23. I C System Configuration
V
accepts voltages from 1.7V to 3.6V (V ). Cycling V
IO
IO
IO
2
does not reset the I C registers. When V is less than
IO
S
Sr
P
V
and V
is less than V
, SDA and
IOUVLO
SYS
SYSUVLO
SCL are high impedance.
SDA
SCL
2
I C Data Transfer
tSU;STA
tSU;STO
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while SCL
tHD;STA
tHD;STA
2
is high are control signals. See the I C Start and Stop
Conditions section. Each transmit sequence is framed by
a START (S) condition and a STOP (P) condition. Each
data packet is nine bits long: eight bits of data followed by
the acknowledge bit. Data is transferred with the MSB first.
2
Figure 24. I C Start and Stop Conditions
2
I C System Configuration
2
The I C bus is a multimaster bus. The maximum number
of devices that can attach to the bus is only limited by bus
capacitance.
2
I C Start and Stop Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing a
START condition. A START condition is a high-to low tran-
sition on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA, while SCL is high. See Figure 24.
2
A device on the I C bus that sends data to the bus in
called a transmitter. A device that receives data from the
bus is called a receiver. The device that initiates a data
transfer and generates the SCL clock signals to control
the data transfer is a master. Any device that is being
addressed by the master is considered a slave. The
A START condition from the master signals the beginning
of a transmission to the MAX77650/MAX77651. The mas-
ter terminates transmission by issuing a not-acknowledge
2
2
MAX77650/MAX77651 I C compatible interface oper-
ates as a slave on the I C bus with transmit and receive
2
followed by a STOP condition. See the I C Acknowledge
Bit section for information on the not-acknowledge. The
STOP condition frees the bus. To issue a series of com-
mands to the slave, the master can issue repeated start
(Sr) commands instead of a STOP command to maintain
control of the bus. In general, a repeated start command
is functionally equivalent to a regular start command.
capabilities.
2
I C Interface Power
2
The MAX77650/MAX77651 I C interface derives its
power from V . Typically a power input such as V
would require a local 0.1μF ceramic bypass capacitor to
ground. However, in highly integrated power distribution
systems, a dedicated capacitor might not be necessary. If
the impedance between V and the next closest capaci-
tor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then
a local capacitor is not needed. Otherwise, bypass V to
IO
IO
When a STOP condition or incorrect address is detected,
the MAX77650/MAX77651 internally disconnect SCL
from the serial interface until the next START condition,
minimizing digital noise and feedthrough.
IO
IO
GND with a 0.1µF ceramic capacitor.
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fault has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communication
at a later time.
I C Acknowledge Bit
2
Both the I C bus master and the MAX77650/MAX77651
(slave) generate acknowledge bits when receiving data.
The acknowledge bit is the last bit of each nine bit data
packet. To generate an acknowledge (A), the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and keep it
low during the high period of the clock pulse. See Figure
25. To generate a not-acknowledge (nA), the receiving
device allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
The MAX77650/MAX77651 issue an ACK for all register
addresses in the possible address space even if the par-
ticular register does not exist.
2
I C Slave Address
2
The I C controller implements 7-bit slave addressing. An
2
I C bus master initiates communication with the slave
by issuing a START condition followed by the slave
address. See Figure 26. The slave address is factory
programmable to one of two options. See Table 11. All
slave addresses not mentioned in the Table 11 are not
acknowledged.
Monitoring the acknowledge bits allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a system
NOT ACKNOWLEDGE (NA)
ACKNOWLEDGE (A)
S
SDA
tSU;DAT
tHD;DAT
1
2
8
9
SCL
Figure 25. Acknowledge Bit
S
1
1
0
2
0
3
1
4
0
5
0
6
0
7
R/W
A
9
SDA
ACKNOWLEDGE
8
SCL
Figure 26. Slave Address Example
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Table 11. I C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
(ADDR = 1)*
0x48, 0b 100 1000
0x90, 0b 1001 0000
0x91, 0b 1001 0001
Main Address
(ADDR = 0)*
0x40, 0b 100 0000
0x49, 0b 100 1001
0x80, 0b 1000 0000
0x92, 0b 1001 0010
0x81, 0b 1000 0001
0x93, 0b 1001 0011
Test Mode**
*Perform all reads and writes on the Main Address. ADDR is a factory one-time programmable (OTP) option, allowing for address
changes in the event of a bus conflict. Contact Maxim for more information.
**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test
mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim.
2
pullup resistors. Higher time constants created by the bus
capacitance and pullup resistance (C x R) slow the bus
operation. Therefore, when increasing bus speeds, the
pullup resistance must be decreased to maintain a rea-
sonable time constant. Refer to the Pullup Resistor Sizing
I C Clock Stretching
2
In general, the clock signal generation for the I C bus is
the responsibility of the master device. The I C specifica-
2
tion allows slow slave devices to alter the clock signal by
holding down the clock line. The process in which a slave
device holds down the clock line is typically called clock
stretching. The MAX77650/MAX77651 do not use any
form of clock stretching to hold down the clock line.
2
section of the I C Bus Specification and User Manual
that is available for free on the Internet for detailed guid-
ance on the pullup resistor selection. In general for bus
capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup
resistors, a 400kHz bus needs about a 1.5kΩ pullup resis-
tors, and a 1MHz bus needs 680Ω pullup resistors. Note
that when the open-drain bus is low, the pullup resistor is
dissipating power, lower value pullup resistors dissipate
more power (V2/R).
2
I C General Call Address
2
The MAX77650/MAX77651 do not implement the I C
specifications general call address. If the MAX77650/
MAX77651 see the general call address (0b0000_0000),
they do not issue an acknowledge.
Operating in high-speed mode requires some special con-
siderations. For a full list of considerations, see the I2C
Communication Speed section. The major considerations
with respect to the MAX77650/MAX77651:
2
I C Device ID
2
The MAX77650/MAX77651 do not support the I C Device
ID feature.
2
2
I C Communication Speed
● The I C bus master use current source pull-ups to
shorten the signal rise.
● The I C slave must use a different set of input filters
on its SDA and SCL lines to accommodate for the
higher bus.
● The communication protocols need to utilize the high-
speed master code.
At power-up and after each stop condition, the MAX77650/
MAX77651 input filters are set for standard mode, fast
mode, and fast mode plus (i.e., 0Hz to 1MHz). To switch
the input filters for high-speed mode, use the high-speed
master code protocols that are described in the I2C
Communication Protocols section.
The MAX77650/MAX77651 are compatible with all 4 com-
munication speed ranges as defined by the Revision 3
I C specification:
2
2
● 0Hz to 100kHz (Standard Mode)
● 0Hz to 400kHz (Fast Mode)
● 0Hz to 1MHz (Fast Mode)
● 0Hz to 3.4MHz (High-Speed Mode)
Operating in standard mode, fast mode, and fast mode
plus does not require any special protocols. The main
consideration when changing the bus speed through
this range is the combination of the bus capacitance and
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● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a data byte.
I C Communication Protocols
The MAX77650/MAX77651 supports both writing and
reading from its registers.
Writing to a Single Register
2
Figure 27 shows the protocol for the I C master device to
● The slave updates with the new data
write one byte of data to the MAX77650/MAX77651. This
protocol is the same as the SMBus specification’s write
byte protocol.
● The slave acknowledges or not acknowledges
the data byte. The next rising edge on SDA loads
the data byte into its target register and the data
becomes active.
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation. Issuing
an Sr leaves the bus input filters in their current state.
The write byte protocol is as follows:
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A OR NA P OR SR*
R/nW
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
ACKNOWLEDGE
8
*P FORCES THE BUS FILTERS TO
SWITCH TO THEIR <=1MHZ MODE.
SR LEAVES THE BUS FILTERS IN
THEIR CURRENT STATE.
Figure 27. Writing to a Single Register with the Write Byte Protocol
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● The slave acknowledges the register pointer.
● The master sends a data byte.
Writing Multiple Bytes to Sequential Registers
Figure 28 shows the protocol for writing to a sequential
registers. This protocol is similar to the write byte proto-
col above, except the master continues to write after it
receives the first byte of data. When the master is done
writing it issues a stop or repeated start.
● The slave acknowledges the data byte. The next ris-
ing edge on SDA load the data byte into its target
register and the data will become active.
● Steps 6 to 7 are repeated as many times as the
master requires.
● During the last acknowledge related clock pulse, the
master can issue an acknowledge or a not acknowledge.
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their
current state.
The writing to sequential registers protocol is as follows:
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
● The master sends an 8-bit register pointer.
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X
A
DATA X
A
Α
Α
R/NW
NUMBER
OF BITS
8
1
8
1
DATA X+1
A
DATA X+2
A
Α
Α
REGISTER POINTER = X + 2
REGISTER POINTER = X + 1
8
NUMBER
OF BITS
1
8
1
1
A OR
NA
P OR
SR*
DATA N-1
A
DATA N
Β
REGISTER POINTER = N-1
REGISTER POINTER = N
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
B9
ACKNOWLEDGE
8
1
DETAIL: Α
THE DATA IS LOADED
INTO THE TARGET
REGISTER AND
BECOMES ACTIVE
DURING THIS RISING
EDGE.
SDA
SCL
B1
7
B0
A
9
*P FORCES THE BUS
FILTERS TO SWITCH
TO THEIR <=1MHZ
MODE. SR LEAVES
THE BUS FILTERS IN
THEIR CURRENT
STATE.
ACKNOWLEDGE
8
DETAIL: Β
Figure 28. Writing to Sequential registers X to N
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● The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
● The master issues a not acknowledge (nA).
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a P ensures that the bus
input filters are set for 1MHz or slower operation.
Issuing an Sr leaves the bus input filters in their cur-
rent state.
Reading from a Single Register
2
Figure 29 shows the protocol for the I C master device to
read one byte of data to the MAX77650/MAX77651. This
protocol is the same as the SMBus specification’s read
byte protocol.
The read byte protocol is as follows:
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Note that when the MAX77650/MAX77651 receive a stop
they do not modify their register pointer.
Reading from Sequential Registers
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a repeated start command (Sr).
● The master sends the 7-bit slave address followed by
a read bit (R/W = 1).
Figure 30 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte protocol
except the master issues an acknowledge to signal the
slave that it wants more data: when the master has all the
data it requires it issues a not acknowledge (nA) and a
stop (P) to end the transmission.
● The addressed slave asserts an acknowledge by
pulling SDA low.
LEGEND
*P FORCES THE BUS FILTERS TO SWITCH
TO THEIR <=1MHZ MODE. SR LEAVES THE
BUS FILTERS IN THEIR CURRENT STATE.
MASTER TO SLAVE
SLAVE TO MASTER
8
NUMBER
OF BITS
1
7
1
0
1
1
1
7
1
1
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A Sr SLAVE ADDRESS
R/nW
A
DATA X
nA P or Sr*
R/nW
Figure 29. Reading from a Single Register with the Read Byte Protocol
LEGEND
*P FORCES THE BUS FILTERS TO SWITCH TO
THEIR <=1MHZ MODE. SR LEAVES THE BUS
FILTERS IN THEIR CURRENT STATE.
MASTER TO SLAVE
SLAVE TO MASTER
8
NUMBER
OF BITS
1
7
1
0
1
1
1
7
1
1
1
8
1
S
SLAVE ADDRESS
A
REGISTER POINTER X A SR SLAVE ADDRESS
A
DATA X
A
R/NW
R/nW
NUMBER
OF BITS
8
1
8
1
8
1
DATA X+1
A
DATA X+2
A
DATA X+3
A
REGISTER POINTER = X + 1 REGISTER POINTER = X + 2 REGISTER POINTER = X + 3
NUMBER
OF BITS
8
1
8
1
8
1
1
P OR
SR*
DATA N-2
A
DATA N-1
A
DATA N
NA
REGISTER POINTER =
N-2
REGISTER POINTER =
N-1
REGISTER POINTER =
N
Figure 30. Reading Continuously from Sequential Registers X to N
Maxim Integrated
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
The continuous read from sequential registers protocol is
as follows:
● The master sends a start command (S).
● The master sends the 7-bit slave address followed by
a write bit (R/W = 0).
● The master sends a stop condition (P) or a repeated
start condition (Sr). Issuing a stop (P) ensures that
the bus input filters are set for 1MHz or slower opera-
tion. Issuing an Sr leaves the bus input filters in their
current state.
● The addressed slave asserts an acknowledge (A) by
pulling SDA low.
Note that when the MAX77650/MAX77651 receive a stop,
they do not modify their register pointers.
● The master sends an 8-bit register pointer.
● The slave acknowledges the register pointer.
● The master sends a repeated start command (Sr).
● The master sends the 7-bit slave address followed
by a read bit (R/W = 1). When reading the RTC time-
keeping registers, secondary buffers are loaded with
the timekeeping register data during this operation.
● The addressed slave asserts an acknowledge by
pulling SDA low.
● The addressed slave places 8-bits of data on the bus
from the location specified by the register pointer.
● The master issues an acknowledge (A) signaling the
slave that it wishes to receive more data.
● Steps 9 to 10 are repeated as many times as the
master requires. Following the last byte of data, the
master must issue a not acknowledge (nA) to signal
that it wishes to stop receiving data.
Engaging HS-mode for operation up to 3.4MHz
Figure 31 shows the protocol for engaging HS-mode
operation. HS-mode operation allows for a bus operating
speed up to 3.4MHz.
The engaging HS mode protocol is as follows:
● Begin the protocol while operating at a bus speed of
1MHz or lower
● The master sends a start command (S).
● The master sends the 8-bit master code of 0b0000
1XXX where 0bXXX are don’t care bits.
● The addressed slave issues a not acknowledge (nA).
● The master may now increase its bus speed up to
3.4MHz and issue any read/write operation.
The master can continue to issue high-speed read/write
operations until a stop (P) is issued. To continue opera-
tions in high speed mode, use repeated start (Sr).
LEGEND
MASTER TO SLAVE
SLAVE TO MASTER
1
8
1
1
ANY R/W PROTOCOL
FOLLOWED BY SR
ANY R/W PROTOCOL
FOLLOWED BY SR
ANY READ/WRITE
PROTOCOL
S
HS-MASTER CODE
nA SR
SR
SR
P
FAST-MODE
HS-MODE
FAST-MODE
Figure 31. Engaging HS Mode
Maxim Integrated
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Typical Application Circuit
MAX77650/MAX77651
DC CHARGING SOURCE
CHGIN
SYS
V
SYS
4.7µF
BATT
25V
(0603)
4.7µF
6.3V
(0603)
GND
+
T
LITHIUM ION
BATTERY
LITHIUM ION BATTERY CHARGER
V
L
TBIAS
THM
1µF
10V
(0402)
IN_SBB
PGND
V
SYS
C
SYS
SBB0
SBB1
SBB2
22µF/6.3V
(0603)
V
V
V
SBB0
SBB1
SBB2
SYSTEM
RESOURCES
SIMO BUCK-BOOST
L
LXA
LXB
10µF
6.3V
(0402)
1.5µH
C
BST
BST
3300pF/6.3V
(0201)
GPIO
BIAS
SUCH AS:
SYS, BATT, SBB2
IN_LDO
LDO
LED0
LED1
LED2
LGND
V
SBB0
CURRENT
LDO
SINKS
V
LDO
10µF
6.3V
(0402)
GPIO
V
IO
GPIO
GPIO
V
/POWER
IO
SDA
SCL
2
I C
SDA
SCL
AMUX
ANALOG
MULTIPLEXER
AMUX
PROCESSOR
nRST
nIRQ
*
*
nRST
nIRQ
nEN
TOP LEVEL
PWR_HLD
PWR_HLD
AMUX
ADC INPUT
*THE PROCESSOR HAS INTERNAL
PULLUP RESISTORS FOR NRST AND
NIRQ.
Maxim Integrated
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
OPTIONS
MAX77650EWV+T*
-40°C to +85°C
30 WLP
Samples with various OTP options
SBB0/SBB1/SBB2 values 2.05V/1.2V/3.3V,
production device, DIDM = 0b00, CID = 0b0011**
MAX77650AEWV+T
MAX77650BEWV+T
MAX77650CEWV+T
-40°C to +85°C
30 WLP
SBB0/SBB1/SBB2 values 1.8V/1.2V/3.15V, production device,
DIDM = 0b00, CID = 0b1110**
-40°C to +85°C
-40°C to +85°C
30 WLP
30 WLP
SBB0/SBB1/SBB2 values 1.8V/1.0V/1.2V,
production device, DIDM = 0b00, CID = 0b1010**
SBB0/SBB1/SBB2 values 1.8V/1.2V/3.15V, production device,
DIDM = 0b00, CID = 0b1000**
MAX77650MEWV+T
MAX77651EWV+T*
MAX77651AEWV+T
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
30 WLP
30 WLP
30 WLP
Samples with various OTP options
SBB0/SBB1/SBB2 values 1.8V/4.6V/3.6V,
production device, DIDM = 0b01, CID = 0b0110**
SBB0/SBB1/SBB2 values 1.9V/3.2V/5.2V,
production device, DIDM = 0b01, CID = 0b1000**
MAX77651BEWVA+T
-40°C to +85°C
30 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Custom samples only. Not for production or stock. Contact factory for more information.
**See the Programmer’s Guide for the options associated with a specified DIDM and CID.
Maxim Integrated
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MAX77650/MAX77651
Ultra-Low Power PMIC with 3-Output SIMO
and Power Path Charger for Small Li+
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
2/17
Initial release
—
Updated Electrical Characteristics—SIMO Buck-Boost table, Typical Operating
Characteristics, Table 1. Regulator Summary, Manual Reset in Features and Benefits
section, Inductor Selection section, and LDO Applications Information section, added
1, 9, 19, 25,
26, 30, 32, 36,
1
5/17
new Figure 19, removed future product notation from MAX77651AEWV+T in Ordering 38, 65, 68, 79
Information table
Updated solution size in Benefits and Features section, updated Absolute Maximum
Ratings section and Figure 18
2
3
6/17
7/17
1, 7, 63
7, 10−12, 17,
18, 20, 21, 24,
30, 36, 68, 69,
Fixed typos, added common conditions to Electrical Characteristics tables, updated
Typical Operating Characteristics, updated Figure 19, updated Typical Application
Circuit
79
21, 37, 40, 52,
55, 56, 59, 62,
65, 68, 71, 81
Added hyperlink to Programmer’s Guide, added MAX77650CEWV+ to Ordering
Information table
4
5
7/17
7/18
1, 7, 17-19, 23,
26, 27, 33, 35,
36, 39-42, 44,
48-51, 61, 65,
66, 68, 72, 74,
77, 78, 80, 82
Updated various sections, added and removed part numbers to Ordering Information
table
6
7
7/18
9/18
Updated Ordering Information table
Updated Ordering Information table
81
81
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 82
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