MAX77734CENPT [MAXIM]
Ultra-Low Power Tiny PMIC with Power Path Charger for Small Li and 150mA LDO;
| 型号： | MAX77734CENPT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low Power Tiny PMIC with Power Path Charger for Small Li and 150mA LDO 集成电源管理电路 |
| 文件： | 总76页 (文件大小：1582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
General Description
Benefits and Features
The MAX77734 is a tiny PMIC for applications where size
and simplicity are critical. The IC integrates a linear-mode
Li+ battery charger, low-dropout linear regulator (LDO),
analog multiplexer, and dual-channel current sink driver.
● Extends Battery Life
• 200nA Factory-Ship Mode for Long Shelf Life
• 500nA Shutdown Current
• 4.5μA Quiescent Current with LDO Enabled
• Charger Allows Battery to Relax after Charging
The charger is designed for small-battery systems
that require accurate termination as low as 0.375mA.
The circuit can instantly regulate the system voltage
when an input source is connected even if the battery is
depleted.
● Linear Charger Optimized for Small Battery Size
• 7.5mA to 300mA Fast-Charge Current
• Battery Regulation Voltage from 3.6V to 4.6V
• Accurate Termination Current as low as 0.375mA
• Instant-On Functionality provided by Maxim's
Smart Power Selector™
The 150mA LDO's output is programmable between 0.8V
2
and 3.975V with I C. The analog MUX enables an exter-
• JEITA Battery Temperature Monitors for Safe
Charging
nal ADC to perform conversions on battery V&I signals
for power monitoring. The current sinks are capable of
sinking 12.8mA each and can be programmed for LEDs
to blink in custom patterns.
● Highly Integrated
• 150mA LDO with Power-OK Output
• Dual-Channel Current Sink for LEDs
• Analog Multiplexer for Power Monitoring
• Watchdog Timer
The MAX77734 is available in a 20-bump, 0.4mm pitch
wafer-level package (WLP). For a similar product with
additional regulators, see the MAX77650.
• On-Key Input for LDO Enable and Manual Reset
Applications
● Small Size
● Hearables: Headsets, Headphones, Earbuds
● Fitness Bands and other Bluetooth Wearables
● Action Cameras, Wearable/Body Cameras
● Low-Power Internet of Things (IoT) Gadgets
• 2.23mm x 1.97mm (0.5mm max height) WLP
• 20-Bump, 0.4mm Pitch, 4 x 5 Array
Ordering Information appears at end of data sheet.
Simplified Application Circuit
5V DC INPUT
CHGIN
4.5V
12.25mm2 SOLUTION SIZE
3.43mm
SYS
SYSTEM
V
L
4.7μF
1μF
MAX77734
22μF
INLDO
LDO
GND
1.8V/3.3V
OUTPUT
CCHGIN
CVL
nENLDO
2.2μF
ON-KEY
V
IO
BATT
THM
POKLDO
SDA
POWER-OK
4.7μF
Li+
TBIAS
SCL
SERIAL HOST
NTC
CLDO
nIRQ
SYS
SNK1
SNK2
PMLDO
AMUX
LDO MODE CONTROL
TO SYSTEM ADC
● 0.2mm COMPONENT PITCH
● PULLUP RESISTORS NOT DRAWN
● BLANK SPACE NOT EXCLUDED
POWER PATH LINEAR CHARGER WITH 0.375mA TERMINATION AND DUAL-CHANNEL CURRENT SINKS
Smart Power Selector is a trademark of Maxim Integrated Products, Inc.
19-100062; Rev 5; 7/20
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Characteristics—Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical Characteristics—Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical Characteristics—Linear Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical Characteristics—Dual-Channel Current Sink Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2
Electrical Characteristics—I C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bump Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Bump Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
On/Off Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Factory-Ship Mode State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Shutdown (Bias Off) State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Standby (Bias On) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Resource On State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Hardware Enable (nENLDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Manual Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Push-Button vs. Slide-Switch Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
nENLDO Pullup Resistors to V
(V
Internal). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CCINT
CC
Interrupts (nIRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Thermal Alarms and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Register Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Factory Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Detailed Description—Smart Power Selector Charger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Charger Symbol Reference Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Smart Power Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Input Current Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Minimum Input Voltage Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Maxim Integrated
│ 2
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
(
)
TABLE OF CONTENTS continued
Minimum System Voltage Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Die Temperature Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Charger State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Charger Off State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Prequalification State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fast-Charge States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Top-Off State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Done State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Prequalification Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fast-Charge Timer Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Battery Temperature Fault State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
JEITA-Modified States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Typical Charge Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Charger Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Configuring a Valid System Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
CHGIN/SYS/BATT Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Detailed Description—Adjustable Thermistor Temperature Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Thermistor Bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Configurable Temperature Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermistor Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Using Different Thermistor β . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Detailed Description—Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Measuring Battery Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Method for Measuring Discharging Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Method for Measuring Charging Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Detailed Description—Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LDO Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
LDO Power Mode (PMLDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
LDO Power-OK Output (POKLDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
LDO Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Input/Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Startup Rate and Inrush Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Detailed Description—Dual-Channel Current Sink Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2
Detailed Description—I C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Maxim Integrated
│ 3
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
(
)
TABLE OF CONTENTS continued
MAX77734 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
INT_GLBL (0x00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
INT_CHG (0x01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
STAT_CHG_A (0x02). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
STAT_CHG_B (0x03). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
ERCFLAG (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
STAT_GLBL (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
INTM_GLBL (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
INT_M_CHG (0x07). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
CNFG_GLBL (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
CID (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
CNFG_WDT (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
CNFG_CHG_A (0x20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
CNFG_CHG_B (0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
CNFG_CHG_C (0x22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
CNFG_CHG_D (0x23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
CNFG_CHG_E (0x24). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
CNFG_CHG_F (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
CNFG_CHG_G (0x26). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
CNFG_CHG_H (0x27). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
CNFG_CHG_I (0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
CNFG_LDO_A (0x30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
CNFG_LDO_B (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
CNFG_SNK1_A (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
CNFG_SNK1_B (0x41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
CNFG_SNK2_A (0x42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CNFG_SNK2_B (0x43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
CNFG_SNK_TOP (0x44). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Battery Charger using LDO Hardware Enable Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Battery Charger using LDO Software Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Maxim Integrated
│ 4
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
LIST OF FIGURES
Figure 1. On/Off Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 2. On/Off Controller Action Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 3. nENLDO Dual-Functionality Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4. nENLDO Pullup Resistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 5. Watchdog Timer State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 6. Charger Simplified Control Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 7. Charger State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. Example Battery Charge Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9. Thermistor Logic Functional Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Safe-Charging Profile Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Thermistor Bias State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 12. Thermistor Circuit with Adjusting Series and Parallel Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. LDO Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. Dynamic LDO Power Mode Control Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 15. PCB Top-Metal and Component Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 16. LED Current Sinks Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LIST OF TABLES
Table 1. On/Off Controller Transitions List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 2. On/Off Controller Internal Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 3. On/Off Controller State Transition Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4. Watchdog Timer Factory-Programmed Safety Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5. Register Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 6. Factory-Programmed Defaults (OTP Options). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. Charger Quick Symbol Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. Input Current Limit Factory Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. Trip Temperatures vs. Trip Voltages for Different NTC β. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 10. Example R and R Correcting Values for NTC β Above 3380K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
S
P
Table 11. NTC Thermistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 12. AMUX Signal Transfer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 13. Battery Current Direction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 14. LDO Power Mode Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2
Table 15. I C Slave Address Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Maxim Integrated
│ 5
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Absolute Maximum Ratings
nIRQ, POKLDO to GND............................-0.3V to V
+ 0.3V
LDO to GND.......................................... -0.3V to V
+ 0.3V
+ 0.3V
SYS
INLDO
SCL, SDA, PMLDO to GND.........................-0.3V to V + 0.3V
INLDO, V to GND ..................................-0.3V to V
IO
IO SYS
nENLDO to GND (Note 1)..................... -0.3V to V
CHGIN to GND...................................................-0.3V to +30.0V
SYS, BATT to GND ..............................................-0.3V to +6.0V
+ 0.3V
SNK1, SNK2 to GND ...........................................-0.3V to +6.0V
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
Continuous Power Dissipation (70°C ambient)...........................
WLP (derate 18mW/°C above +70°C) ..........................1440mW
CCINT
V to GND ............................................................-0.3V to +6.0V
L
AMUX, THM, TBIAS to GND................................-0.3V to +6.0V
nIRQ, POKLDO Continuous Current..................................±3mA
SDA, AMUX Continuous Current .....................................±20mA
CHGIN, SYS, BATT Continuous Current ......................1.2A
RMS
Note 1: V
is internally connected to either BATT or V . Refer to nENLDO Pullup Resistors to V
(V
Internal) section.
CCINT
L
CCINT CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
PACKAGE CHARACTERISTICS
Package Code
VALUES
N201B2+1
Outline Number
21-100154
Land Pattern Number
Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
55.49 °C/W
JA
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Maxim Integrated
│ 6
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics
(V
= 0V, V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating
CHGIN
SYS
BATT
INLDO IO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYS Voltage Range
V
2.7
5.5
V
SYS
Factory-ship mode (BATT to SYS
BATT Factory-Ship Mode
Current
I
switch open), T = +25°C, V
0.2
0.5
1
1
μA
μA
BATT-FSM
A
BATT
= 3.7V, V
= V
= 0V
SYS
INLDO
Shutdown state (all resources
and bias off), BATT to SYS switch
closed, T = +25°C, no load
A
BATT Shutdown Current
BATT Standby Current
I
BATT-SHDN
Bias enabled in
low-power mode
(BIAS_REQ = 1,
BIAS_LPM = 1)
Standby state
(all resources
off), BATT to
1.5
30
I
μA
BATT-STDBY
SYS switch
closed, no
load
Bias enabled in
normal mode
(BIAS_REQ = 1,
BIAS_LPM = 0)
Bias is in
low-power mode
(BIAS_LPM = 1),
LDO enabled in
4.5
22
40
10
40
60
Resource on
state, BATT
to SYS switch
closed,
low-power mode
Bias is in
low-power mode
current sinks
(BIAS_LPM = 1),
and analog
LDO enabled in
MUX
BATT Quiescent Current
I
μA
BATT-Q
normal mode
disabled,
V
= 1.2V,
LDO
Bias is in
no load
normal mode
(BIAS_LPM = 0)
LDO enabled in
normal mode
,
POWER-ON RESET (POR)
POR Threshold
V
V
V
falling
falling
1.5
1.9
2.1
V
POR
SYS
POR Threshold Hysteresis
100
mV
UNDERVOLTAGE LOCKOUT (UVLO)
UVLO Threshold
V
2.65
2.85
150
3.05
V
SYSUVLO
SYS
UVLO Threshold Hysteresis
V
mV
SYSUVLO_HYS
Maxim Integrated
│ 7
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics (continued)
(V
= 0V, V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating
CHGIN
SYS
BATT
INLDO IO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OVERVOLTAGE LOCKOUT (OVLO)
OVLO Threshold
V
V
rising
5.55
5.85
6.15
V
SYSOVLO
SYS
THERMAL MONITORS
Over-Temperature Lockout
Threshold
T
T rising
165
°C
OTLO
J
Thermal Alarm Temperature 1
Thermal Alarm Temperature 2
T
T rising
80
°C
°C
JAL1
J
T
T rising
100
JAL2
J
Thermal Alarm Temperature
Hysteresis
15
°C
ENABLE INPUT (nENLDO)
V
V
5.5V
= 5.5V,
T = +25°C
-1
±0.001
±0.01
+1
BATT
A
nENLDO Leakage Current
I
=
μA
nENLDO-LKG
nENLDO
T = +85°C
A
V
V
CCINT
- 1.4
CCINT
- 1.0
nENLDO Falling Threshold
nENLDO Rising Threshold
V
nENLDO Falling
nENLDO Rising
V
V
TH_nENLDO_F
V
V
CCINT
- 0.9
CCINT
- 0.6
V
TH_nENLDO_R
V
= 0V,
CHGIN
battery is present
V
BATT
(V
is valid)
BATT
V
Internal
V
(Note 2)
Pullup to
V
CC
CCINT
V
= 5V, not
CHGIN
USB suspended
(USBS = 0)
V
L
PU_DIS = 0
PU_DIS = 1
200
nENLDO Pullup
Debounce Time
R
kΩ
μs
nEN-PU
V
CCINT
10000
200
DB_nENLDO = 0
(Note 3)
Rising and
falling, not in
factory-ship
mode
t
DBNC_nENLDO
DB_nENLDO = 1
30
ms
Falling only, factory-ship mode
(Note 4)
t
250
FSM-EXDB
T_MRST = 0
5
8
10
20
Manual Reset Time
t
s
s
MRST
T_MRST = 1
10
89
16
Watchdog Timer Period
t
WDT_PER[1:0] = 0b11
128
154
WD
Maxim Integrated
│ 8
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics (continued)
(V
= 0V, V
= V
= V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating
CHGIN
SYS
BATT
INLDO IO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
INTERRUPT OUTPUT (nIRQ)
nIRQ Output Low Voltage
V
Sinking 2mA
V
nIRQ-LO
V
= V
SYS
IO
= 5.5V, nIRQ
set to be high
impedance
(i.e., no
T = +25°C
-1
±0.001
±0.01
+1
A
nIRQ Leakage Current
I
μA
nIRQ-LKG
interrupts),
T = +85°C
A
V
= 0V
nIRQ
and 3.6V
Electrical Characteristics—Smart Power Selector Charger
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
DC INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Initial CHGIN voltage before
enabling charging
CHGIN Valid Voltage Range
V
4.10
7.25
V
V
V
CHGIN
CHGIN Standoff
Voltage Range
V
DC rising
DC rising
28
STANDOFF
CHGIN Overvoltage
Threshold
V
7.25
3.9
7.50
7.75
4.1
CHGIN_OVP
CHGIN Overvoltage
Hysteresis
100
4.0
mV
V
CHGIN Undervoltage Lockout
V
DC rising
CHGIN_UVLO
CHGIN Undervoltage-Lockout
Hysteresis
500
mV
V
= V
- 100mV,
SYS
SYS-REG
Input Current-Limit Range
Input Current-Limit Accuracy
I
95
90
475
100
mA
mA
CHGIN-LIM
programmable in 95mA steps
I
= 95mA,
CHGIN-LIM
95
V
= V
- 100mV
SYS
SYS-REG
V
falling due to loading
CHGIN
conditions and/or high-impedance
charge source, programmable in
100mV increments with
Minimum Input Voltage
Regulation Range
V
4.0
4.7
V
CHGIN-MIN
VCHGIN_MIN[2:0]
V
= 4.5V
CHGIN-MIN
Minimum Input Voltage
Regulation Accuracy
(VCHGIN_MIN[2:0] = 0b101),
4.32
100
4.50
120
4.68
140
V
I
reduced by 10%
CHGIN
V
= 5V, time before CHGIN
CHGIN
Charger Input Debounce
Timer
t
is allowed to deliver current to
SYS or BATT
ms
CHGIN-DB
Maxim Integrated
│ 9
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Smart Power Selector Charger (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY AND QUIESCENT CURRENTS
V
= 5V, charger is not in USB
CHGIN
suspend (USBS = 0), charging is
finished (CHG_DTLS[3:0] indicate
1.0
1.8
mA
CHGIN Supply Current
I
CHGIN
done), I
= 0mA
SYS
V
V
= 0V to 1V,
CHGIN
50
50
μA
μA
= 3.3V, I
= 0mA
BATT
SYS
CHGIN Suspend Supply
Current
V
= 5V, charger in USB
CHGIN
I
CHGIN-SUS
suspend (USBS = 1)
V
= 5V, charger is not in USB
CHGIN
suspend (USBS = 0), charging is
finished (CHG_DTLS[3:0] indicate
BATT Bias Current
I
5
1
μA
BATT-BIAS
done), I
= 0mA
SYS
PREQUALIFICATION
Charge Current Soft-Start
Slew Time
Zero to full-scale
ms
V
Prequalification Voltage
Threshold Range
Programmable in 100mV steps
with CHG_PQ[2:0]
V
2.3
-3
3.0
+3
PQ
Prequalification Voltage
Threshold Accuracy
V
= 3.0V
%
PQ
V
V
= 2.5V,
= 3.0V,
BATT
I_PQ = 0
I_PQ = 1
10
PQ
Prequalification Mode Charge
Current
I
t
expressed as a
percentage of
%
PQ
20
30
I
FAST-CHG
Prequalification Safety Timer
V
< V
= 3.0V
27
33
minutes
V
PQ
BATT
PQ
FAST-CHARGE
I
= 0mA, programmable in
BATT
Fast-Charge Voltage Range
V
3.6
4.6
FAST-CHG
25mV steps with CHG_CV[5:0]
V
FAST-CHG
= 4.3V,
-0.5
+0.5
V
= 4.5V,
SYS
T
= +25°C
A
Fast-Charge Voltage
Accuracy
I
= 0mA
%
BATT
V
FAST-CHG
= 3.6V to
4.6V,
1.0
V
= 4.8V
SYS
Programmable in 7.5mA steps
with CHG_CC[5:0]
Fast-Charge Current Range
I
7.5
300
mA
FAST-CHG
Maxim Integrated
│ 10
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Smart Power Selector Charger (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
FAST-CHG
-1.5
+1.5
T
V
= +25°C,
A
= 15mA
Fast-Charge Current
Accuracy
= V
%
BATT
FAST-
I
FAST-CHG
- 300mV
CHG
-1.5
-10
+1.5
+10
= 300mA
Across all current settings,
= V - 300mV,
Fast-Charge Current
Accuracy over Temperature
V
%
BATT
FAST-CHG
T
= -40°C to +85°C
A
Programmable in 2 hour
increments or disabled with
T_FAST_CHG[1:0], time
measured from prequal done to
timer fault
Fast-Charge Safety Timer
Range
t
3
7
hours
%
FC
Fast-Charge Safety Timer
Accuracy
t
= 3 hours
-10
+10
FC
Fast-charge CC mode, fast-
charge safety timer paused
when charge current drops below
this threshold, expressed as a
Fast-Charge Safety Timer
Suspend Threshold
20
%
°C
percentage of I
FAST-CHG
Junction Temperature Regu-
lation Setting Range
Programmable in 10°C steps
with TJ_REG[2:0]
T
60
100
J-REG
Rate at which I
/I
FAST-CHG PQ
is reduced to maintain T
expressed a percentage of
,
J-REG
Junction Temperature Regu-
lation Loop Gain
G
-5.4
%/°C
TJ-REG
I
/I per degree
FAST-CHG PQ
centigrade rise
TERMINATION AND TOPOFF
I_TERM = 0b00 (expressed as a
percentage of I
5
)
FAST-CHG
I_TERM = 0b01 (expressed as a
percentage of I
7.5
10
15
)
FAST-CHG
End-of-Charge Termination
Current
I
%
TERM
I_TERM = 0b10 (expressed as a
percentage of I
8.5
11.5
)
FAST-CHG
I_TERM = 0b11 (expressed as a
percentage of I
)
FAST-CHG
I
< I
,
BATT
TERM
Top-Off Timer Range
t
programmable in 5 minute steps
with T_TOPOFF[2:0]
0
35
minutes
%
TO
Top-Off Timer Accuracy
t
= 10 minutes
-10
+10
TO
Maxim Integrated
│ 11
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Smart Power Selector Charger (continued)
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
Charging is finished
MIN
TYP
MAX
UNITS
(CHG_DTLS[3:0] indicate done),
charging resumes when
Charge Restart Threshold
V
65
150
mV
RESTART
V
< V
FAST-CHG
- V
RESTART
BATT
I
= 15mA, I
=
FAST-CHG
TERM
1.5mA (10% of I
),
1.35
27
1.5
1.65
33
FAST-CHG
T
= +25°C
A
End-of-Charge Termination
Current Accuracy
mA
I
= 300mA, I
=
FAST-CHG
TERM
30mA (10% of I
),
30
60
FAST-CHG
T
= +25°C
A
End-of-Charge Termination
Current Glitch Filter
μs
DEVICE ON-RESISTANCE AND LEAKAGE
V
V
= 3.7V, I
= 300mA,
BATT
BATT
BATT to SYS On-Resistance
= 0V, battery is
100
150
1.0
mΩ
CHGIN
discharging to SYS
V
V
= 4.5V,
= 0V,
T
T
T
T
= +25°C
= +85°C
= +25°C
0.1
1
SYS
A
A
A
A
BATT
charger disabled
Charger FET Leakage
Current
μA
V
V
= 0V,
= 4.2V,
0.1
1.0
1.0
SYS
BATT
= +85°C
= 400mA
1
factory-ship mode
CHGIN to SYS On-Resistance
Input FET Leakage Current
V
= 4.65V, I
600
mΩ
μA
CHGIN
CHGIN
V
V
= 0V,
= 4.2V,
CHGIN
T
T
= +25°C
= +85°C
0.1
1
A
A
SYS
body-switched
diode reverse
biased
SYSTEM NODE
System Voltage Regulation
Range
Programmable in 25mV steps
with VSYS_REG[4:0]
V
4.1
4.41
4.365
4.8
4.59
4.635
V
V
SYS-REG
V
= 4.5V,
= 1mA
SYS-REG
T
= +25°C
4.50
4.5
A
I
SYS
System Voltage Regulation
Accuracy
V
SYS
VSYS-REG =
T
= -40°C
A
4.5V, ISYS = 1mA to +85°C
V
V
= 5V, V = 4.5V,
SYS-REG
CHGIN
SYS
< V
due to I =
SYS-REG
CHGIN
Minimum System Voltage
Regulation Loop Setpoint
I
(input in current limit),
CHGIN-LIM
V
4.34
4.4
4.45
V
V
SYS-MIN
battery charging, I
reduced to
BATT
(minimum
50% of I
FAST-CHG
system voltage regulation active)
Supplement Mode System
Voltage Regulation
V
BATT
- 0.15V
I
= 150mA
SYS
Maxim Integrated
│ 12
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Adjustable Thermistor Temperature Monitors
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JEITA TEMPERATURE MONITORS
TBIAS Voltage
V
THM_EN = 1, V
= 5V
1.25
V
V
TBIAS
CHGIN
Voltage rising threshold, programmable
with THM_COLD[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Cold Threshold
Range
V
0.867
0.747
0.367
0.291
1.024
0.923
0.511
0.411
COLD
COOL
WARM
Voltage rising threshold, programmable
with THM_COOL[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Cool Threshold
Range
V
V
V
V
Voltage falling threshold, programmable
with THM_WARM[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Warm Threshold
Range
V
Voltage falling threshold, programmable
with THM_HOT[1:0] in 5ºC increments
when using an NTC β = 3380K
JEITA Hot Threshold
Range
V
HOT
Temperature Threshold
Accuracy
Voltage threshold accuracy expressed
as temperature for an NTC β = 3380K
±3
3
°C
°C
Temperature Threshold
Hysteresis
Temperature hysteresis set on each
voltage threshold for an NTC β = 3380K
JEITA Modified
Fast-Charge Voltage
Range
I
= 0mA, programmable in 25mV
BATT
V
3.6
7.5
4.6
V
FAST-CHG_JEITA
steps, battery is either cool or warm
JEITA Modified
Fast-Charge Current
Range
Programmable in 7.5mA steps, battery
is either cool or warm
I
300
mA
FAST-CHG_JEITA
Maxim Integrated
│ 13
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Analog Multiplexer
(V
= 5.0V, V
= 4.5V, V
= 4.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature
CHGIN
SYS
BATT A
range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG MULTIPLEXER
Full-Scale Voltage
V
1.25
0.3
1
V
FS
Channel Switching Time
μs
nA
T = +25°C
500
A
V
= 0V, AMUX is
AMUX
Off Leakage Current
high impedance
T = +85°C
1
μA
A
CHGIN POWER MEASUREMENT
V
corresponds to maximum
FS
CHGIN Current Monitor Gain
CHGIN Voltage Monitor Gain
G
G
2.632
0.167
V/A
V/V
ICHGIN
I
setting
CHGIN-LIM
V
corresponds to V
CHGIN_OVP
VCHGIN
FS
BATT AND SYS POWER MEASUREMENT
Battery Charge Current
Monitor Gain
V
corresponds to 100% of I
FAST-CHG
FS
G
12.5
mV/%
%
IBATT-CHG
setting (CHG_CC[5:0])
I
= 15mA, T = +25°C,
FAST-CHG
A
-3.5
-3.5
-10
8.2
+3.5
+3.5
+10
300
+15
+0.8
V
= V
- 300mV
BATT
FAST-CHG
Charge Current Monitor
Accuracy
I
= 300mA, T = +25°C,
A
FAST-CHG
V
= V
- 300mV
BATT
FAST-CHG
Charge Current Monitor
Accuracy over Temperature
Across all current settings,
V = V - 300mV
BATT
%
FAST-CHG
Battery Discharge Monitor
Full-Scale Current Range
Programmable with
IMON_DISCHG_SCALE[3:0]
I
mA
%
DISCHG-SCALE
Battery Discharge Current
Monitor Accuracy
15mA to 300mA battery discharge
current, I
-15
-0.5
= 300mA
DISCHG-SCALE
Battery Discharge Current
Monitor Offset
I
= 0mA
mA
V/V
V/V
BATT
V
V
corresponds to maximum
FS
Battery-Voltage Monitor Gain
SYS Voltage Monitor Gain
G
0.272
0.26
VBATT
setting
FAST-CHG
V
V
corresponds to maximum
FS
G
VSYS
setting
SYS-REG
THM AND TBIAS VOLTAGE MEASUREMENT
THM Voltage Monitor Gain
TBIAS Voltage Monitor Gain
G
1
1
V/V
V/V
VTHM
G
VTBIAS
Maxim Integrated
│ 14
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Linear Regulator
(V
= V
= 3.7V, C
= 22μF, C
= 2.2μF, limits are 100% production tested at T = +25°C, limits over the operating
SYS
INLDO
SYS
LDO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO
INLDO Voltage Range
V
INLDO cannot exceed V
by 0.3V
1.7
5.5
V
INLDO
SYS
V
= 1.2V, no load
= 1.2V, no load
Low-power mode
1.5
12
LDO
LDO
INLDO Supply Current
I
μA
INLDO-Q
V
Normal mode
Target regulation voltage. Programmable in
25mV steps with LDO_VREG[6:0].
LDO Output Voltage Range
V
0.8
-2
3.975
+2
V
LDO-REG
I
= 0.1mA to
LDO
150mA,
T
= -5°C to +85°C,
A
normal mode
V
= V
+
INLDO
LDO
LDO Output Voltage
Accuracy
0.3V to 5.5V, across
I
= 0.1mA to
LDO
V
%
LDO
all V settings,
150mA, T = -40°C,
normal mode
-3
+3
LDO-REG
A
bias in normal mode
I
= 0.1mA to
LDO
5mA, low-power
-6.5
+6.5
mode
Normal mode (Note 7)
150
5
LDO Maximum Output
Current
I
mA
%
LDO
Low-power mode (Note 7)
I
= 0.1mA to
LDO
150mA, normal
mode
0.5
0.5
V
= V
+
INLDO
LDO
Load Regulation
Line Regulation
0.3V to 5.5V, across
I
= 0.1mA to
LDO
all V settings
LDO-REG
5mA, low-power
mode
I
= 0.1mA,
LDO
Normal mode
0.05
0.05
60
V
= V
+
INLDO
LDO
%/V
0.3V to 5.5V, across
Low-power mode
all V settings
LDO-REG
I
= 150mA, normal
V
V
= 3.0V,
LDO
INLDO
LDO-REG
150
560
mode (Note 6)
= 3.3V
Dropout Voltage
V
mV
mA
DO
I
= 150mA, Nor-
V
V
= 1.7V,
INLDO
LDO
100
mal Mode (Note 6)
= 1.85V
LDO-REG
Normal mode
160
1.1
300
40
V
= 90% of pro-
LDO
LDO Current Limit
I
LDO-LIM
grammed target
Low-power mode
LDO Output Capacitance
for Stability
C
(Note 5)
2.2
20
μF
LDO
LDO Startup Ramp Rate
ΔV
/Δt
10% to 90% of final value
mV/μs
LDO
Maxim Integrated
│ 15
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Linear Regulator (continued)
(V
= V
= 3.7V, C
= 22μF, C
= 2.2μF, limits are 100% production tested at T = +25°C, limits over the operating
SYS
INLDO
SYS
LDO A
temperature range (T = -40°C to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
= V
=
SYS
INLDO
100
2.7V, V
= 0.8V
LDO
LDO
LDO
LDO
V
= V
=
SYS
INLDO
150
200
300
2.7V, V
= 1.0V
LDO and bias in
normal mode,
f = 10Hz to 100kHz,
V
= V
=
SYS
INLDO
2.7V, V
= 2.0V
=
Output Noise
μV
RMS
V
= V
I
= 15mA
SYS
INLDO
LDO
3.7V, V
= 3.0V
V
= V
=
SYS
INLDO
5.5V,
400
V
= 3.975V
LDO
LDO in normal-power mode, bias in
low-power mode, V =3.6V,
Power-Supply Rejection
Ratio
SYS
PSRR
60
dB
V
V
=2.8V+20mVpp, f = 10Hz to 1kHz,
INLDO
=1.8V, I
=15mA
LDO
LDO
Active Discharge Resistance
R
100
Ω
AD_LDO
LDO POWER-OK OUTPUT (POKLDO)
V
V
rising, expressed as a percentage of
LDO
V
82.5
79
87.5
84
92.5
POKLDO_R
LDO-REG
POKLDO Threshold
%
V
V
V
falling, expressed as a percentage of
LDO
V
89
0.4
+1
POKLDO_F
LDO-REG
POKLDO Low Voltage
POKLDO Leakage Current
V
POKLDO = low, sinking 2mA
POKLDO
V
= V = 5.5V,
IO
SYS
T
= +25°C
= +85°C
-1
±0.001
±0.01
A
A
POKLDO is high-Z,
I
μA
POKLDO-LKG
V
= 0V or
POKLDO
T
5.5V
LDO POWER-MODE INPUT (PMLDO)
PMLDO Logic-High
Threshold
0.7 x
V
IO
V
V
PMLDO_HI
0.3 x
PMLDO Logic-Low Threshold
PMLDO Debounce Timer
V
V
PMLDO_LO
V
IO
t
(Note 3)
200
μs
PMLDO-DB
T
T
= +25°C
= +85°C
-1
±0.001
±0.01
+1
A
A
V
V
= V = 5.5V,
IO
SYS
PMLDO Leakage Current
I
μA
PMLDO-LKG
= 0V or 5.5V
PMLDO
Maxim Integrated
│ 16
www.maximintegrated.com
MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Dual-Channel Current Sink Driver
(V
= 3.7V, V
= 0.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C
SYS
SNKx A A
to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DUAL-CHANNEL CURRENT SINK DRIVER
Current Sink Quiescent
Current
Change in supply current when one channel is
ΔI
6
µA
µA
BATT-Q
enabled and delivering 12.8mA, V
= 0.2V
SNKx
All current sink
drivers combined,
outputs disabled,
T
T
= +25ºC
+0.1
+1.0
+1.0
A
Current Sink Leakage
= +85ºC
A
V
= 5.5V,
SNKx
SNK_FSx[1:0] = 0b01
SNK_FSx[1:0] = 0b10
SNK_FSx[1:0] = 0b11
0.1
0.2
0.4
3.2
6.4
Programmable with
BRT_SNKx[4:0]
Sink Current Range
I
mA
SNKx
12.8
3.2mA CURRENT SINK RANGE (SNK_FSx[1:0]=0b01)
Current Sink DAC Bits
5
bits
mA
SNK_FSx[1:0] = 0b01,
3.10
3.20
3.25
3.425
70
T
= +25ºC
A
BRT_SNKx[4:0] =
0b11111
Current Sink Accuracy
SNK_FSx[1:0] = 0b01,
= -40ºC to +85ºC
2.975
3.20
35
T
A
BRT_SNKx[4:0] =
0b11111
SNK_FSx[1:0] = 0b01,
= 2.9mA
Dropout Voltage
V
mV
DO
I
SNKx
6.4mA CURRENT SINK RANGE (SNK_FSx[1:0] =0b10)
SNK_FSx[1:0] = 0b10,
= +25ºC
6.30
5.95
6.40
6.40
35
6.50
6.85
70
T
A
BRT_SNKx[4:0] =
0b11111
Current Sink Accuracy
mA
mV
SNK_FSx[1:0] = 0b10,
= -40ºC to +85ºC
T
A
BRT_SNKx[4:0] =
0b11111
SNK_FSx[1:0] = 0b10,
= 5.75mA
Dropout Voltage
V
DO
I
SNKx
12.8mA CURRENT SINK RANGE (SNK_FSx[1:0]=0b11)
SNK_FSx[1:0] = 0b11,
= +25ºC
12.6
11.9
12.8
12.8
35
13.0
13.7
70
T
A
BRT_SNKx[4:0] =
0b11111
Current Sink Accuracy
Dropout Voltage
mA
SNK_FSx[1:0] = 0b11,
= -40ºC to +85ºC
T
A
BRT_SNKx[4:0] =
0b11111
SNK_FSx[1:0] = 0b11,
= 11.5mA
V
mV
Hz
DO
I
SNKx
TIMING CHARACTERISTICS
Root Clock Frequency
25.6
32.0
38.4
Maxim Integrated
│ 17
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Electrical Characteristics—Dual-Channel Current Sink Driver (continued)
(V
= 3.7V, V
= 0.2V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C
SYS
SNKx A A
to +85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS
TIMING CHARACTERISTICS / BLINK PERIOD SETTINGS
MIN
TYP
MAX
UNITS
0.5
s
Minimum Blink Period
P_SNKx[3:0] = 0b0000
16
8
clocks
s
Maximum Blink Period
Blink Period LSB
P_SNKx[3:0] = 0b1111
256
0.5
16
clocks
s
clocks
TIMING CHARACTERISTICS / BLINK DUTY CYCLE
Minimum Blink Duty Cycle
Maximum Blink Duty Cycle
Blink Duty Cycle LSB
D_SNKx[3:0] = 0b0000
D_SNKx[3:0] = 0b1111
6.25
100
%
%
%
6.25
2
Electrical Characteristics—I C Serial Interface
(V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to
SYS
IO A A
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS
SERIAL INTERFACE/I/O STAGE
MIN
TYP
MAX
UNITS
V
V
Voltage Range
Bias Current
V
1.7
-1
3.6
+1
V
IO
IO
T = +25°C
0
μA
IO
A
SCL, SDA Input High
Voltage
0.7 x
V
V
V
IH
V
IO
SCL, SDA Input Low
Voltage
0.3 x
V
IL
V
IO
0.05 x
SCL, SDA Input Hysteresis
V
V
HYS
V
IO
SCL, SDA Input Leakage
Current
I
V
= 3.6V, V
= V = 0V or 3.6V
SDA
-10
10
0.4
μA
I
IO
SCL
SDA Output Low Voltage
SCL, SDA Pin Capacitance
V
Sinking 20mA
(Note 8)
V
OL
10
pF
Input Filter Suppressed
Spike Maximum Pulse
Width
t
(Note 8)
50
ns
SP
Maxim Integrated
│ 18
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
2
Electrical Characteristics—I C Serial Interface (continued)
(V
= 3.7V, V = 1.8V, limits are 100% production tested at T = +25°C, limits over the operating temperature range (T = -40°C to
SYS
IO A A
+85°C) are guaranteed by design and characterization, unless otherwise noted.)
PARAMETER
SERIAL INTERFACE/TIMING
Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
1
MHz
SCL
Bus Free Time between
STOP and START
Condition
t
0.5
μs
BUF
Setup Time REPEATED
START Condition
t
260
260
ns
ns
SU;STA
Hold Time REPEATED
START Condition
t
HD;STA
SCL Low Period
SCL High Period
Data Setup Time
Data Hold Time
t
500
260
50
ns
ns
ns
μs
LOW
t
HIGH
t
SU;DAT
HD;DAT
t
0
Setup Time for STOP
Condition
t
260
ns
SU;STO
Note 2: See the nENLDO Pullup Resistors to V
(V
Internal) section of the data sheet.
CCINT CC
Note 3: Digitally debounced for two consecutive 100μs clock periods. Typical debounce time is at least 200μs and up to 300μs due
to synchronization to the digital clock.
Note 4: This is the amount of additional debounce time required to exit factory-ship mode (250ms, typ additional time).
Note 5: For stability, guaranteed by design and not production tested.
Note 6: The dropout voltage is the difference between the input voltage and the output voltage when the input voltage is within the
valid input voltage range, but below the output voltage setpoint. For example, if the output voltage setpoint is 1.85V, the
input voltage is 1.7V, and the actual output voltage is 1.65V, then the dropout voltage is 50mV (V
Note 7: The "Maximum Output Current" is guaranteed by the "Output Voltage Accuracy" tests.
Note 8: Design guidance only. Not production tested.
= V
- V
).
DO
INLDO
LDO
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│ 19
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Typical Operating Characteristics
(Typical Application Circuits, V
= 0V, V
= V
= V
= 3.7V, V = 1.8V, V = 4.5V, BIAS in low-power mode,
SYS-REG
CHGIN
SYS
BATT
INLDO
IO
LDO in normal mode, T = +25°C, unless otherwise noted.) (T = +25°C, unless otherwise noted.)
A
A
SHUTDOWN SUPPLY CURRENT vs.
BATTERY VOLTAGE
QUIESCENT SUPPLY CURRENT vs.
BATTERY VOLTAGE
QUIESCENT SUPPLY CURRENT vs.
TEMPERATURE
toc01
toc02
toc03
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
20
18
16
14
12
10
8
20
18
16
14
12
10
8
UVLO FALLING = 2.8V
TA = +25°C
VBATT FALLING
IC IN SHUTDOWN STATE
LDO NORMAL MODE
LDO NORMAL MODE
LDO LOW-POWER MODE
LDO LOW-POWER MODE
VLDO = 1.8V
6
6
TA = +85°C
TA = +25°C
TA = -40°C
4
4
VLDO = 1.8V
VBATT = 3.7V
2
2
0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
VBATT (V)
VBATT (V)
LDO POWER-UP CAUSED BY
BUTTON PRESS (LDO_WAKE)
10mA LOAD
LDO POWER-DOWN CAUSED
BY SOFTWARE
FACTORY-SHIP MODE CURRENT
toc06
toc05
toc04
500
450
400
350
300
250
200
150
100
50
VBATT FALLING
VLDO
VLDO
2V/div
VPOKLDO
2V/div
2V/div
VnENLDO
2V/div
TA = +85°C
TA = +25°C
TA = -40°C
VPOKLDO
IBATT
100mA/div
2V/div
0
800µs/div
2ms/div
2.5
3.0
3.5
4.0
4.5
5.0
VBATT (V)
LDO LOAD REGULATION AND
CURRENT LIMIT
LDO LINE TRANSIENT RESPONSE
LDO LINE REGULATION
toc09
toc07
toc08
1.90
1.88
1.86
1.84
1.82
1.80
1.78
1.76
1.74
1.72
1.70
1.9
1.88
1.86
1.84
1.82
1.8
VLDO-REG = 1.8V
10mALOAD
VLDO-REG = 1.8V
VLDO
20mV/div
TA = +25°C
TA = +85°C
TA = -40°C
4.2V
VINLDO
200mV/div
1.78
1.76
1.74
1.72
1.7
VIN = 3.0
VIN = 3.7
VIN = 4.2
3.7V
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
100
200
300
400
40µs/div
LOAD (mA)
VINLDO (V)
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Typical Operating Characteristics (continued)
(Typical Application Circuits, V
= 0V, V
= V
= V
= 3.7V, V = 1.8V, V = 4.5V, BIAS in low-power mode,
CHGIN
SYS
BATT
INLDO
IO
SYS-REG
LDO in normal mode, T = +25°C, unless otherwise noted.) (T = +25°C, unless otherwise noted.)
A
A
LDO POWER SUPPLY REJECTION
LDO LOAD TRANSIENT RESPONSE
LDO LOAD TRANSIENT RESPONSE
RATIO (PSRR)
toc10
toc11
toc12
90
80
70
60
50
40
30
20
10
0
15mA LOAD
AVERAGE VLDO = 1.8V
AVERAGE VINLDO = 3.7V
1.8V
1.8V
VLDO
VLDO
50mV/div
50mV/div
150mA
75mA
1mA
1mA
ILDO
ILDO
100mA/div
100mA/div
-10
40µs/div
40µs
10
1000
100000
10000000
FREQUENCY (Hz)
CHGIN SUPPLY CURRENT vs.
CHGIN VOLTAGE
(USB NOT SUSPENDED)
CHGIN SUPPLY CURRENT vs.
CHGIN VOLTAGE
BATT BIAS CURRENT vs.
BATT VOLTAGE
(USB SUSPENDED)
toc13
toc14
toc15
1.8
100
90
80
70
60
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
1
0
CHARGER DISABLED
VCHGIN = 5V
ISYS = 0mA
VCHGIN RISING
VBATT = 2.7V
VBATT = 3.6V
VBATT = 4.4V
1.6 VCHGIN RISING
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
TA = +85°C
TA = +25°C
TA = -40°C
3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5
VCHGIN (V)
3.5
4.0
4.5
5.0
5.5
6.0
2.5
3.0
3.5
4.0
4.5
VCHGIN (V)
VBATT (V)
CHARGE PROFILE, 110mAh BATTERY
BATT TO SYS FET IMPEDANCE
CHARGE PROFILE, 40mAh BATTERY
toc17
toc18
toc16
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.150
0.135
0.120
0.105
0.090
0.075
0.060
0.045
0.030
0.015
0.000
150
140
130
120
110
100
90
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.060
0.054
0.048
0.042
0.036
0.030
0.024
0.018
0.012
0.006
0.000
VPQ = 3V, IPQ = 10%
IFAST-CHG = 75mA, VFAST-CHG = 4.2V
VPQ = 3V, IPQ = 10%
IFAST-CHARGE = 30mA, VFAST-CHARGE = 4.2V
VBATT (V)
VBATT (V)
IBATT = 600mA
IBATT = 300mA
IBATT = 150mA
IBATT = 10mA
IBATT (A)
IBATT (A)
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
BATTERY LOADED
DURING THE 'DONE'
STATE TO SHOW
THE RESTART
80
70
60
BEHAVIOR
BEHAVIOR
50
0.0
1.0
2.0
TIME (hr)
3.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0
1.0
2.0
3.0
TIME (hr)
VBATT (V)
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Bump Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX77734
1
2
3
4
5
+
A
CHGIN
AMUX
nENLDO
nIRQ
SDA
SCL
LDO
V
L
B
SYS
THM
TBIAS
SNK1
PMLDO POKLDO
GND
C
BATT
V
IO
D
GND
SNK2
INLDO
WLP
(2.23mm x 1.97mm x 0.5mm, 0.4mm PITCH)
Bump Description
PIN
NAME
FUNCTION
TYPE
CHARGER
Charger Input. Connect to a 5V DC charging source. Bypass to GND with a 4.7μF
ceramic capacitor.
A1
A2
A3
B1
B2
C1
CHGIN
power input
power
Internal Charger 3V Logic Supply Powered from CHGIN. Bypass to GND with a
V
L
1μF ceramic capacitor. Do not load V externally.
L
Analog Multiplexer Output. Connect to system ADC to perform conversions on
charger power signals. Leave this pin unconnected if unused.
AMUX
SYS
analog output
power output
analog input
power i/o
System Power Output. SYS provides power to the system resources as well as
the control logic of the IC. Bypass to GND with a 22μF ceramic capacitor.
Thermistor Monitor. Thermally couple an NTC to the battery and connect between
THM and GND.
THM
Li+ Battery Connection. Connect to positive battery terminal. Bypass to GND with
a 4.7μF ceramic capacitor.
BATT
Thermistor Bias Supply. Connect a resistor equal to the NTC's room
temperature resistance between TBIAS and THM. Do not load TBIAS with other
external circuitry.
C2
TBIAS
GND
analog
ground
Ground. Connect to the negative battery terminal and the low-impedance ground
plane of the PCB.
C3, D1
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Bump Description (continued)
PIN
NAME
FUNCTION
TYPE
LINEAR REGULATOR
Active-Low LDO Enable Input. This digital input also causes the IC to exit
A4
B3
B4
nENLDO
factory-ship mode. Pulled up internally to V
(nENLDO) section.
. See the Hardware Enable
digital input
digital input
digital output
CCINT
LDO Power-Mode Control Input. This digital input causes the LDO to change
between low-power mode and normal mode when the MSB of LDO_PM[1:0] is set.
See the LDO Power Mode (PMLDO) section.
PMLDO
Open-Drain Linear Regulator Power-OK Output. Connect a 100kΩ pullup resistor
between POKLDO and a voltage equal to or less than V
Leave unconnected if unused.
POKLDO
if this pin is used.
SYS
D4
D5
INLDO
LDO
Linear Regulator Input. Connect to GND if unused.
power input
Linear Regulator Output. Bypass to GND with a 2.2μF ceramic capacitor.
Leave unconnected if unused.
power output
DUAL-CHANNEL CURRENT SINK
Current Sink Port 1. SNK1 is typically connected to the cathode of an LED and is
capable of sinking up to 12.8mA. Connect to GND if unused.
D2
D3
SNK1
SNK2
power
power
Current Sink Port 2. SNK2 is typically connected to the cathode of an LED and is
capable of sinking up to 12.8mA. Connect to GND if unused.
2
I C SERIAL INTERFACE
Active-Low, Open-Drain Interrupt Output. Connect a 100kΩ pullup resistor between
A5
nIRQ
digital output
nIRQ and a voltage equal to or less than V
.
SYS
2
B5
C4
C5
SDA
I C Serial Interface Data
digital i/o
power input
digital input
2
V
I C Serial Interface Voltage Supply
IO
2
SCL
I C Serial Interface Clock
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Simplified Block Diagram
MAX77734
BODY-
SWITCH
SYS
4.5V
CHGIN
5V DC INPUT
4.7μF
22μF
SYSTEM LOADS
CHARGE
CONTROLLER
VL REG
V
L
BATT
1μF
TEMPERATURE
4.7μF
MONITORS
TBIAS
THM
GND
NTC
ANALOG MUX
LDO
AMUX
TO SYSTEM ADC
V
IO
V
CCINT
SDA
SCL
nIRQ
nENLDO
INLDO
SYS
2
WAKE SOURCE
SERIAL
HOST
I C CONTROL AND
DIGITAL
LDO
REGULATOR
PMLDO
SNK1
V
(0.8V – 3.975V)
LDO
LDO
SYS
100kΩ
2.2μF
POKLDO
REGULATED
LOADS
SNK2
GND
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
2
Detailed Description—I C Serial Interface). The active-
Detailed Description
The MAX77734 is a tiny power-management integrated
circuit (PMIC) that integrates the following:
low nENLDO input can be used to wake-up the LDO using
an external on-key. See Hardware Enable (nENLDO).
A low-I (0.2μA typ) factory-ship mode can be entered to
Q
● Instant-on linear-mode lithium-ion/lithium-polymer
(Li+) battery charger optimized for small battery cells
(see Detailed Description—Smart Power Selector
Charger)
isolate the battery node (BATT) from the system (SYS)
to prevent slow cell discharge due to a high combined
shutdown current of all external SYS loads (see Factory-
Ship Mode State).
● NTC thermistor monitor for automatic JEITA-safe-
charging (see Detailed Description—Adjustable
Thermistor Temperature Monitors)
2
A watchdog timer can be enabled through I C (or factory-
enabled and locked) to provide supervisory reset in the
event that serial activity from the host controller suddenly
stops (see Watchdog Timer).
● Analog Multiplexer (MUX) which enables an external
ADC to monitor power (see Detailed Description—
Analog Multiplexer)
Additionally, a SYS voltage supervisory function is accom-
plished by the undervoltage (UVLO), overvoltage (OVLO),
and power-on reset (POR) comparators.
● 150mA linear regulator (see Detailed Description—
Linear Regulator)
On/Off Controller
● Dual-channel current sinks with individual pattern
control (see Detailed Description—Dual-Channel
Current Sink Driver)
The IC top-level on/off controller uses a synchronous
digital state machine with a 100μs clock. Asynchronous
inputs to the state machine can take up to 100μs to take
effect due to clock synchronization.
The ICs internal top-level digital logic is described in the
On/Off Controller section of the data sheet. The IC is
The state machine is drawn in Figure 1 and Figure 2.
State transition conditions are listed in Table 1.
2
fully configurable through I C (see the Register Map and
STATE
FACTORY-SHIP MODE
BATT TO SYS SWITCH
FORCED OPEN
ACTION
SEQUENCE
ANY
STATE2
1
X
2
POWER-ON RESET
(SYSPOR = 1)
X AND Y
TRANSITION NAME.
SEE TABLE 3.
SHUTDOWN (BIAS OFF)
SPS1 CONTROL
0A
0C
ALL RESOURCES OFF
0B
0D
RESET ACTIONS
OFF ACTIONS
4
3
STANDBY (BIAS ON)
SPS1 CONTROL
NOTE
ALL RESOURCES OFF
1: SPS = SMART POWER SELECTOR
2: ANY STATE EXCEPT FACTORY-SHIP MODE
6
5
RESOURCE ON
SPS1 CONTROL
BIAS AND AT LEAST ONE
RESOURCE IS ON
8 AND 8A
LDO POWER-DOWN
7 AND 7A
8B
7B
LDO POWER-UP
Figure 1. On/Off Controller State Machine
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Table 1. On/Off Controller Transitions List
TRANSITION
NUMBER
CONDITION (TRANSITION HAPPENS WHEN...)
Software cold reset (SFT_CTRL[1:0] = 0b01) OR
0A
0B
Watchdog timer expired causes reset (WDT_EXP = 1 and WDT_MODE = 1)
Reset actions completed
Software power-off (SFT_CTRL[1:0] = 0b10) OR
Watchdog expired causes power-off (WDT_EXP = 1 and WDT_MODE = 0) OR
Device over-temperature lockout (T >T
) OR
+ V
J
OTLO
0C
SYS undervoltage lockout (V
< V
) OR
SYS
SYSUVLO
SYSUVLO_HYS
SYS overvoltage lockout (V
> V
) OR
SYS
SYSOVLO
Manual reset occurred (MAN_RST = 1)
0D
1
Off Actions completed
CHGIN inserted and debounced valid (CHGIN_DTLS[1:0] = 0b11) OR
nENLDO asserted for 250ms debounce timer (t ) OR
FSM-DB
Power to the IC is removed (V
< approx. 1.8V) and then reapplied (V
> V
)
BATT
BATT
POR
Factory-ship mode requested (SFT_CTRL[1:0] = 0b11) AND
CHGIN unplugged (CHGIN_DTLS[1:0] = 0b00)
2
NOT(4) OR
Factory-ship mode requested (SFT_CTRL[1:0] = 0b11) OR
Software cold reset (SFT_CTRL[1:0] = 0b01) OR
Software power-off (SFT_CTRL[1:0] = 0b10) OR
Watchdog timer expired (WDT_EXP = 1) OR
Manual reset occurred (MAN_RST = 1) OR
3
4
Device over-temperature lockout (T >T
) OR
J
OTLO
SYS undervoltage lockout (V
< V
) OR
SYS
SYSUVLO
SYS overvoltage lockout (V
> V
)
SYS
SYSOVLO
2
Main bias requested enabled through I C (BIAS_REQ = 1) OR 6
NOT(6) OR
Factory-ship mode requested (SFT_CTRL[1:0] = 0b11) OR
Software cold reset (SFT_CTRL[1:0] = 0b01) OR
Software power-off (SFT_CTRL[1:0] = 0b10) OR
Watchdog timer expired (WDT_EXP = 1) OR
Manual reset occurred (MAN_RST = 1) OR
5
Device over-temperature lockout (T >T
) OR
J
OTLO
SYS undervoltage lockout (V
< V
) OR
SYS
SYSUVLO
SYS overvoltage lockout (V
> V
)
SYS
SYSOVLO
At least one current sink is enabled (EN_SNK1 or EN_SNK2 = 1) OR
AMUX is being used (MUX_SEL[3:0] ≠ 0b0000) OR
CHGIN inserted and debounced valid (CHGIN_DTLS[1:0] = 0b11) OR
LDO is forced enabled (LDO_EN[1:0] = 0b01) OR
LDO wake-up flag is set (LDO_WAKE = 1) OR
Internal wake-up flag is set (SFT_WAKE = 1)
6
7
LDO power-up sequence has not happened yet
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Table 1. On/Off Controller Transitions List (continued)
TRANSITION
NUMBER
CONDITION (TRANSITION HAPPENS WHEN...)
LDO is forced enabled (LDO_EN[1:0] = 0b01) OR
LDO wake-up flag is set (LDO_WAKE = 1) OR
Internal wake-up flag is set (SFT_WAKE = 1)
7A
7B
8
Done with LDO power-up
LDO power-down sequence has not happened yet
LDO is forced disabled (LDO_EN[1:0] = 0b00) OR
Software cold reset (SFT_CTRL[1:0] = 0b01) OR
Software power-off (SFT_CTRL[1:0] = 0b10) OR
Watchdog timer expired (WDT_EXP = 1) OR
Factory-ship mode requested (SFT_CTRL[1:0] = 0b11) OR
Manual reset occurred (MAN_RST = 1) OR
8A
8B
Device over-temperature lockout (T >T
) OR
J
OTLO
SYS undervoltage lockout (V
< V
+ V
) OR
SYS
SYSUVLO
SYSUVLO_HYS
SYS overvoltage lockout (V
> V
)
SYS
SYSOVLO
Done with LDO power-down
RESET ACTIONS
OFF ACTIONS
LDO POWER-UP
LDO POWER-DOWN
8 AND 8A
UVLO OR
OVLO OR
OTLO
0A
0C
WAIT 60ms
POKLDO BLANKED1
WAIT 10.24ms
(NO WAITS)
7 AND 7A
EVENT RECORDER
(ERCFLAG) LOGS
RESET CAUSE
EVENT RECORDER
(ERCFLAG) LOGS
POWER-OFF CAUSE
POKLDO BLANKED1
LDO ENABLED
OFF FLAGS CLEARED:
WDT_EXP = 0
RESET FLAGS CLEARED:
WDT_EXP = 0
MAN_RST = 0
WAIT 5.12ms
LDO DISABLED
RESET CONFIG
REGISTERS:
RESET CONFIG
REGISTERS:
PULSE SYSRST = 1
PULSE SYSRST = 1
POKLDO UNBLANKED2
7B
WAKE FLAGS CLEARED:
LDO_WAKE = 0
SFT_WAKE = 0
WAKE FLAG SET:
SFT_WAKE = 1
LDO_WAKE = 0
WAKE FLAGS CLEARED:
SFT_WAKE = 0
LDO_WAKE = 0
WAIT 125ms
8B
0B
0D
NOTE
1: POKLDO = LOW REGARDLESS OF V
LDO
2: POKLDO DETERMINED BY V
LDO
Figure 2. On/Off Controller Action Sequences
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
The on/off controller operates on internally latched signals decoded in Table 2.
Table 2. On/Off Controller Internal Signals
SIGNAL
NAME
TYPE
DESCRIPTION
SET CONDITION
CLEAR CONDITION
Watchdog timer expired flag.
See Watchdog Timer.
During Reset Actions,
Off Actions
WDT_EXP
Off/Reset Flag
Off/Reset Flag
Watchdog timer expires
Manual reset occurred.
See Manual Reset.
MAN_RST
LDO_WAKE
SFT_WAKE
EN_SNKx
nENLDO asserted for t
During Off Actions
MRST
nENLDO debounced low or CHGIN
debounced valid. LDO_EN[1:0]
must be 0b10 for this flag to set.
LDO wakeup flag.
See LDO Enable Control.
During LDO Power-Down,
Off Actions, Reset Actions
Wake Flag
Wake Flag
Wake Flag
LDO software wakeup flag.
See LDO Enable Control.
Software reset (Reset Actions) and During Power-Down,
LDO_EN[1:0] reset value is 0b10.
Off Actions
EN_SNK_MSTR = 1 and either
SNK_FS1[1:0] ≠ 0b00 or
SNK_FS2[1:0] ≠ 0b00
EN_SNK_MSTR = 0 or
both SNK_FS1[1:0] = 0b00
and SNK_FS2[1:0] = 0b00
Final enable signal for
current sink 1 and 2.
The state machine places a higher priority on events that cause shutdown versus events that cause power-on. In other
words, moving the IC to a lower-power state is prioritized over moving the IC to a higher-power state. When two transi-
tions are true at the same time, the state machine prioritizes action according to Table 3.
Table 3. On/Off Controller State Transition Priority
STATE
TRANSITION PRIORITY TO EXIT
N/A (single exit path)
FACTORY-SHIP MODE
SHUTDOWN
2 > 0C > 0A > 4
STANDBY
SYSPOR > 3 > 6
RESOURCE ON
SYSPOR > (8 AND 8A) > 5 >(7 AND 7A)
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
The IC shuts down when V
becomes invalid
Factory-Ship Mode State
SYS
(<V
or >V
) or the ICs junction tem-
SYSUVLO
SYSOVLO
Factory-ship mode internally disconnects the battery
(BATT) from the system (SYS). The battery does not
power the system in this mode. Use this mode to preserve
battery life if external circuits on SYS cause the battery
to leak.
perature exceeds approximately 165°C (T
). A man-
OTLO
ual reset (MAN_RST), watchdog timer expiration (WDT_
EXP), or software power-off request (SFT_CTRL[1:0] =
0b10) also causes shutdown.
The IC exits shutdown when transition 4 in Table 1 is true.
2
Write SFT_CTRL[1:0] = 0b11 using I C to enter factory-
ship mode. The IC responds in two different ways
depending on the state of the charger input (CHGIN):
Standby (Bias On) State
Standby state is a transitional state used to activate the
IC’s central bias supply before a resource is allowed to
operate. Bias activation is automatically managed by the
on/off controller.
●
If CHGIN is valid (CHGIN_DTLS[1:0] = 0b11) while
SFT_CTRL[1:0] = 0b11, then the IC enters factory-
ship mode (internally disconnects BATT from SYS)
but SYS is still powered from CHGIN (regulating
Resource On State
to V
). SYS decays to 0V when CHGIN is
SYS-REG
The IC is in resource on state when at least one resource
is enabled:
disconnected.
●
If CHGIN is invalid (CHG_DTLS[1:0] ≠ 0b11) while
SFT_CTRL[1:0] = 0b11, then the IC enters factory-
ship mode and SYS decays to 0V.
●
CHGIN is valid (CHGIN_DTLS[1:0] = 0b11) indicating
the charger resource is ready to be enabled through
CHG_EN
Factory-ship mode causes many configuration registers
●
The analog multiplexer output buffer is being used
to reset (SYSRST). Consult the Register Map section of
2
(MUX_SEL[3:0] ≠ 0b0000)
the data sheet for details. I C reads and writes can not
happen in factory-ship mode.
●
●
The LDO is enabled
Factory-ship mode only exits after SYS decays below
approximately 1.8V. Once this condition is met, there are
two ways to exit factory-ship mode:
At least one of the current sinks is activated
(EN_SNK_MSTR = 1 and SNK_FS1/2 ≠ 0b00)
The wake flags in Table 2 also cause the on/off controller
to enter this state.
●
Apply a valid DC source at CHGIN for t
CHGIN-DB
(120ms typical). Factory-ship mode is unlatched (exit-
ed) when the charger input becomes valid from
a previously invalid state (CHGIN_DTLS[1:0] =
0b00 → 0b11).
Hardware Enable (nENLDO)
nENLDO is an active-low, internally debounced digital
input with internal pullup resistors. nENLDO's input signal
typically comes from a physical on-key. Asserting nEN-
LDO sets LDO_WAKE (see Table 2). This input is also
used to exit factory-ship mode (see Factory-Ship Mode
State).
●
Assert nENLDO for t
(250ms typical) +
FSM-EXDB
t
(0.2ms or 30ms typical).
DBNC-nENLDO
Furthermore, this state is unlatched if power is removed
from the IC (BATT voltage falls below approximately
1.8V). In all exit cases, the Smart Power Selector controls
the interaction between BATT and SYS until factory-ship
mode is entered again (see Smart Power Selector).
The debounce time is programmable with DB_nENLDO
to either 200μs or 30ms. Both rising and falling edges
are debounced. Maskable rising and falling interrupts
(nENLDO_R and nENLDO_F) are available to signal a
change in nENLDO's status. The debounced status of this
input is continuously mirrored by the STAT_ENLDO bit.
Consult the Register Map for more details.
Shutdown (Bias Off) State
The on/off controller is in shutdown (bias off) state when
2
no resources are enabled and CHGIN is invalid. I C is still
active as long as V is valid.
IO
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The default value of nENLDO_MODE is factory-
Manual Reset
programmable. Figure 3 shows a visual example of how
nENLDO_MODE changes how t is counted.
Asserting nENLDO for an extended period of time causes
the IC to shutdown (MAN_RST = 1).
MRST
nENLDO Pullup Resistors to V
CC
If nENLDO is continuously asserted for t
(8 or 16
CCINT
MRST
(V
Internal)
seconds depending on T_MRST bit), then the on/off con-
troller shuts down the IC and resets configuration registers
(SYSRST). The default value of T_MRST can be factory-
programmed. See the Register Map for additional details.
V
is an always-on internal voltage domain. The
CCINT
nENLDO logic thresholds are referenced to V
.
CCINT
There are internal pullup resistors between nENLDO and
(R ). See Figure 4. The pullup strength can
V
CCINT nEN-PU
The manual reset function is useful for forcing a register
reset and power-down in case communication with the
host controller fails. End-applications frequently call this
a "hard reset".
be modified with the PU_DIS bit. While PU_DIS = 0, the
pullup value is approximately 200kΩ (typ). While PU_DIS
= 1, the pullup value is 10MΩ (typ).
V
is defined by the following conditions:
CCINT
The manual reset timer counts differently based on the
type of on-key (push-button or slide-switch). See Push-
Button vs. Slide-Switch Functionality.
● If CHGIN is valid (CHGIN_DTLS[1:0] = 0b11) and not
USB suspended (USBS = 0), then V
(3V typ).
equals V
CCINT
L
Push-Button vs. Slide-Switch Functionality
● If CHGIN is invalid (CHGIN_DTLS[1:0] ≠ 0b11) or
The nENLDO manual reset ("hard-reset") can be config-
ured to work with a push-button switch or a slide-switch
using the nENLDO_MODE bit.
CHGIN is valid but USB suspended (USBS = 1) then
V
equals V
.
CCINT
BATT
Applications using a slide-switch on-key connected to
nENLDO can optimize quiescent current consumption by
changing pullup strength to 10MΩ by setting PU_DIS to
1. This is because a slide-switch in the "on position" con-
nects nENLDO to ground and creates a path for BATT to
Use nENLDO_MODE = 0 for normally-open, momentary,
and push-buttons. In this mode, the manual reset timer
counts t
while nENLDO is low (a long button press
MRST
and hold).
Use nENLDO_MODE = 1 for persistent slide-switches.
In this mode, the manual reset timer counts t
leak (since V
= V
while CHGIN is not present).
CCINT
BATT
MRST
Applications using normally-open, momentary, and push-
button on-keys (as shown in Figure 4) do not create this
leakage path and should use the stronger 200kΩ pullup
option (PU_DIS = 0).
while nENLDO is high (switch in off position). If the host
controller fails to issue a software shutdown command in
t
after nENLDO goes high, then the on/off controller
MRST
automatically causes a register reset and shutdown.
NOT DRAWN TO SCALE
STATE
SHUTDOWN
LDO POWER-UP
RESOURCE ON
LDO POWER-DOWN
BATTERY
INSERTION
V
/ V
CCINT BATT
t
DBNC_nENLDO
nENLDO
“A LONG PRESS AND HOLD”
t
t
DBNC_nENLDO
DBNC_nENLDO
t
MRST
PUSH-BUTTON MODE (nENLDO_MODE = 0)
t
DBNC_nENLDO
“SWITCHED OFF”
nENLDO
t
MRST
t
DBNC_nENLDO
SLIDE-SWITCH MODE (nENLDO_MODE = 1)
Figure 3. nENLDO Dual-Functionality Timing Diagram
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All interrupts are masked by default. Masked interrupt
bits do not cause the nIRQ pin to change. Unmask the
interrupt bits to allow nIRQ to assert.
Interrupts (nIRQ)
nIRQ is an active-low, open-drain output that is typically
routed to the host processor's interrupt input to signal an
important change in the ICs status. See the Register Map
for a full list of available status and interrupt bits.
Watchdog Timer
The IC features a watchdog timer function for operational
safety. If this timer expires without being cleared, then an
internal signal called WDT_EXP asserts and the on/off
controller causes the IC to enter the shutdown state and
resets configuration registers. See the On/Off Controller
and List of Transitions (transitions 0A and 0C) for more
details.
A pullup resistor to a voltage less than or equal to V
is required for this node. nIRQ is the logical NOR of all
unmasked interrupt bits in the ICs register map.
SYS
V
CCINT
2
Write WDT_EN = 1 through I C to enable the timer. The
watchdog timer period (t ) is configurable from 16 to
128 seconds in 4 steps with WDT_PER[1:0]. The default
WD
SWITCH CONTROL
PU_DIS
0b0
SWITCH
CLOSED
OPEN
R
nEN-PU
10MΩ
~200kΩ
10MΩ
timer period is 128 seconds. The WDT_CLR bit must be
2
200kΩ
0b1
set through I C periodically (within t ) to reset the timer
WD
nENLDO
and prevent shutdown. Consult the Register Map and
Watchdog Timer State Machine (Figure 5) for additional
details.
ON-KEY
Figure 4. nENLDO Pullup Resistor Configuration
SHUTDOWN (BIAS OFF) STATE**
WATCHDOG TIMER
RESET
(THE ON/OFF CONTROLLER FORCES THIS
TRANSITION WHEN THE TIMER EXPIRES)
INTERNAL COUNT = t
WDT_CLR = 0
WD
CLEAR CONTROL SET (WDT_CLR = 1)
CLEAR CONTROL NOT SET (WDT_CLR = 0)
AND
OR
TIMER DISABLED (WDT_EN = 0)
TIMER ENABLED (WDT_EN = 1)
AND
NOT IN SHUTDOWN (BIAS OFF) STATE*
OR
SHUTDOWN (BIAS OFF) STATE*
OR
t
CHANGED (NEW BITS IN WDT_PER[1:0])
WD
WATCHDOG TIMER
ENABLED AND OK
TIMER COUNTING DOWN
WATCHDOG TIMER
EXPIRED
INTERNAL COUNT = 0
INTERNAL WDT_EXP = 1
TIME ELAPSED < t
WD
TIME ELAPSED = t
WD
INTENAL COUNT < t
WD
*WATCHDOG TIMER DOES NOT RUN WHILE IN SHUTDOWN STATE.
WDT_MODE BIT CAN CAUSE THE ON/OFF CONTROLLER TO EXIT
SHUTDOWN AUTOMATICALLY. SEE REGISTER MAP.
**SEE ON/OFF CONTROLLER STATE MACHINE
Figure 5. Watchdog Timer State Machine
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The timer can be factory-programmed to be enabled by
default, disabled by default, or locked from accidental
disable. The WDT_LOCK bit is read-only and must be
configured at the factory. See Table 4 for a full description.
interrupts are available to signal a change in either of
these bits. Consult the Register Map for details.
Register Reset Conditions
The IC's registers reset to default values when the corre-
sponding reset condition for each particular bit becomes
true. Table 5 lists all register reset conditions. See the
Register Map for a list of every configuration and status
bit and the associated reset value and reset condition.
Thermal Alarms and Protection
The IC has thermal alarms to monitor if the junction tem-
perature rises above 80°C (T
) and 100°C (T
).
JAL1
JAL2
Over-temperature lockout (OTLO) is entered if the junc-
tion temperature exceeds T (approximately 165°C,
OTLO
Factory Options
typ). OTLO causes all resources to turn off immediately.
Resources may not enable until the temperature falls
Table 6 shows the factory-programmable (OTP) options
for the IC. Refer to the Ordering Information and Register
Map for more information about the different default
register functions.
below T
by approximately 15ºC.
OTLO
The TJAL1_S and TJAL2_S status bits continuously
indicate the junction temperature alarm status. Maskable
Table 4. Watchdog Timer Factory-Programmed Safety Options
WDT_LOCK
WDT_EN
FUNCTION
2
0
0
0
1
Watchdog timer is disabled by default. Timer can be enabled or disabled by I C writes.
2
Watchdog timer is enabled by default. Timer can be enabled or disabled by I C writes.
2
Watchdog timer is disabled by default. Timer can be enabled by an I C write, but only a
2
1
1
0
1
SYSRST can reset the WDT_EN value back to 0. Timer can not be disabled by direct I C
writes to WDT_EN (write from 1 → 0 is ignored, write from 0 → 1 is accepted).
Watchdog timer is enabled by default. Nothing can disable the timer.
Table 5. Register Reset Conditions
RESET CONDITION
NAME
RESET CAUSE AND DETAILS
SYSPOR
System Power-On Reset
V
SYS
< 1.9V (typ)
SYSPOR OR
SYSRST
System Reset
On/off controller (see transitions 0A and 0C in Table 1)
CHGPOR OR
CHGPOK
CHGPOR
Charger Power-OK
USB suspend (USBS = 1) OR
V
< V
(typ. 4V rising, 3.5V falling)
CHGIN
CHGIN_UVLO
Charger Power-On Reset
V
< 1.9V (typ)
CHGIN
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Table 6. Factory-Programmed Defaults (OTP Options)
MAX77734BENP MAX77734CENP MAX77734GENP MAX77734QENP
Option Letter
B
C
G
Q
Chip Identification
CID[3:0] = 0x1
0x48
CID[3:0] = 0x3
0x48
CID[3:0] = 0x4
0x48
CID[3:0] = 0x7
0x48
2
I C Device Address (7-bit)
V
(falling UVLO threshold)
2.85V
2.85V
2.85V
2.85V
SYSUVLO
V
(UVLO hysteresis)
0.15V
0.15V
0.15V
0.15V
SYSUVLO_HYS
CHG_EN (default charger enable bit)
(default input current limit)
0 (disabled)
475mA
0 (disabled)
95mA
1 (enabled)
95mA
1 (enabled)
475mA
I
CHGIN-LIM
LDO_VREG[6:0] (default LDO voltage)
LDO_EN[1:0] (default LDO enable)
0x28 (1.8V)
0x64 (3.3V)
0x64 (3.3V)
0x64 (3.3V)
0b10 (hardware
enabled)
0b10 (hardware
enabled)
0b10 (hardware
enabled)
0b00 (disabled)
DB_nENLDO (nENLDO input debounce time) 1 (30ms)
1 (30ms)
1 (30ms)
1 (30ms)
nENLDO_MODE (button type)
0 (push-button)
0 (push-button)
0 (8s)
0 (push-button)
0 (8s)
0 (push-button)
0 (8s)
T_MRST (manual reset time)
0 (8s)
WDT_EN (watchdog timer enable)
WDT_LOCK (watchdog timer enable lock)
0 (disabled)
0 (unlocked)
0 (disabled)
0 (unlocked)
0 (disabled)
0 (unlocked)
1 (enabled)
0 (unlocked)
Charger Symbol Reference Guide
Table 7 lists the names and functions of charger-specific
signals and if they can be programmed through I C.
Consult the Electrical Characteristics and Register Map
Detailed Description—Smart Power
Selector Charger
2
The linear Li+ charger implements power path with
Maxim's Smart Power Selector. This allows separate
input current limit and battery charge current settings.
Batteries charge faster under the supervision of the Smart
Power Selector because charge current is independently
regulated and not shared with variable system loads. See
the Smart Power Selector section for more information.
for more information.
Figure 6 indicates the high-level functions of each control
circuit within the linear charger.
Smart Power Selector
The Smart Power Selector seamlessly distributes power
from the input (CHGIN) to the battery (BATT) and the sys-
tem (SYS). The Smart Power Selector basic functions are:
The programmable constant-current charge rate (7.5mA
to 300mA) supports a wide range of battery capacities.
The programmable input current limit (95mA to 475mA)
supports a range of charge sources, including USB. The
charger's programmable battery regulation voltage range
(3.6V–4.6V) supports a wide variety of cell chemistries.
Small battery capacities are supported; the charger
accurately terminates charging by detecting battery
currents as low as 0.375mA.
● When the system load current is less than the input
current limit, the battery is charged with residual power
from the input.
● When a valid input source is connected, the system
regulates to V
to power system loads regard-
SYS-REG
less of the battery's voltage (instant on).
● When the system load current exceeds the input cur-
rent limit, the battery provides additional current to the
system (supplement mode).
Additionally, the robust charger input withstands
overvoltages up to 28V. To enhance charger safe-
ty, an NTC thermistor provides temperature monitor-
ing in accordance with the JEITA recommenda-
tions. See the Detailed Description—Adjustable
Thermistor Temperature Monitors section for more
information.
● When the battery is finished charging and an input
source is present to power the system, the battery
remains disconnected from the system.
● When the battery is connected and there is no input
power, the system is powered from the battery.
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Table 7. Charger Quick Symbol Reference Guide
2
SYMBOL
NAME
CHGIN overvoltage threshold
CHGIN undervoltage-lockout threshold
Minimum CHGIN voltage regulation setpoint
CHGIN input current limit
I C PROGRAMMABLE?
V
No
No
CHGIN_OVP
V
CHGIN_UVLO
V
Yes, through VCHGIN_MIN[2:0]
Yes, through ICHGIN_LIM[2:0]
Yes, through VSYS_REG[4:0]
CHGIN-MIN
CHGIN-LIM
I
V
SYS voltage regulation target
Minimum SYS voltage regulation setpoint
Fast-charge constant-voltage level
Fast-charge constant-current level
Prequalification current level
Prequalification voltage threshold
Termination current level
SYS-REG
V
No, tracks V
SYS-REG
SYS-MIN
V
Yes, through CHG_CV[5:0]
Yes, through CHG_CC[5:0]
Yes, through I_PQ
FAST-CHG
FAST-CHG
I
I
PQ
V
Yes, through CHG_PQ[2:0]
Yes, through I_TERM[1:0]
Yes, through TJ_REG[2:0]
No
PQ
I
TERM
T
Die temperature regulation setpoint
Prequalification safety timer
J-REG
t
PQ
t
Fast-charge safety timer
Yes, through T_FAST_CHG[1:0]
Yes, through T_TOPOFF[2:0]
FC
TO
t
Top-off timer
BODY-
SWITCH
CHGIN
SYS
V
SYS-MIN
I
V
CHGIN-LIM
SYS-REG
INPUT
CONTROLLER
CHARGE CONTROLLER
V
CHGIN-MIN
V
CHGIN_OVP
V
CHGIN_UVLO
I
I
I
FAST-CHG
PQ
V
V
FAST-CHG
PQ
DIE TEMP
MONITOR
T
J-REG
TERM
BATT
TIMER
t
PQ
t
FC
TO
t
Figure 6. Charger Simplified Control Loops
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The input voltage regulation loop improves performance
with current limited adapters. If the charger’s input current
Input Current Limiter
The input current limiter limits CHGIN current to not
exceed I (programmed by ICHGIN_LIM[2:0]).
limit is programmed above the current limit of the given
adapter, the input voltage loop allows the input to regulate
at the current limit of the adapter. The input voltage regu-
lation loop also allows the charger to perform well with
adapters that have poor transient load response times.
CHGIN-LIM
A maskable interrupt (CHGIN_CTRL_I) signals when the
input current limit engages. The ICHGIN_LIM_STAT bit
reflects the state of the current limiter loop.
The default value of I
is factory-programmable
CHGIN-LIM
A maskable interrupt (CHGIN_CTRL_I) signals when the
minimum input voltage regulation loop engages. The state
of this loop is reflected by VCHGIN_MIN_STAT.
to either 95mA or 475mA. The decoding of the ICHGIN_
LIM[2:0] bitfield changes depending on the factory-pro-
grammed default value (see Table 8). The reset value of
this bitfield is always 0b000 regardless of factory option.
Minimum System Voltage Regulation
The minimum system voltage regulation loop ensures that
the system rail remains close to the programmed SYS
CHGIN is capable of standing off 28V from ground.
CHGIN suspends power delivery to the system and bat-
tery when V
exceeds V
(7.5V, typ).
falls below
CHGIN
CHGIN_OVP
regulation voltage (V
) regardless of system load-
SYS-REG
The input circuit also suspends when V
CHGIN
ing. The loop engages when the combined battery charge
current and system load current causes the CHGIN input
V
minus 500mV of hysteresis (3.5V, typ).
CHGIN_UVLO
While in OVP or UVLO, the charger remains off and the
battery provides power to the system.
to current limit at I
. When this happens, the
CHGIN-LIM
minimum system voltage loop reduces charge current in
Power transfer to SYS is delayed by a 120ms debounce
an attempt to keep the input out of current limit, thereby
timer (t
) after a valid DC source is connected to
keeping the system voltage above V
(V
CHGIN-DB
SYS-MIN SYS-REG
CHGIN. SYS does not begin regulating to V
after the timer expires.
until
- 100mV, typ). If this loop reduces battery current to 0
and the system is in need of more current than the input
can provide, then the Smart Power Selector overrides the
minimum system voltage regulation loop and allows SYS
to collapse to BATT for the battery to provide supplement
current to the system. The Smart Power Selector auto-
matically reenables the minimum system voltage loop
when the supplement event has ended.
SYS-REG
The CHGIN_DTLS[1:0] bitfield continuously indicates the
state of CHGIN's voltage quality. A maskable interrupt
(CHGIN_I) asserts when CHGIN_DTLS[1:0] changes.
Minimum Input Voltage Regulation
In the event of a poor-quality charge source, the mini-
mum input voltage regulation loop works to reduce input
A maskable interrupt (SYS_CTRL_I) asserts to signal a
change in VSYS_MIN_STAT. This status bit asserts when
the minimum system voltage regulation loop is active.
current if V
falls below V
(programmed
CHGIN
CHGIN-MIN
by VCHGIN_MIN[2:0]). This is important because many
commonly used charge adapters feature foldback protec-
tion mechanisms where the adapter completely shuts off if
its output drops too low. The minimum input voltage regu-
Die Temperature Regulation
If the die temperature exceeds T
(programmed
J-REG
lation loop also prevents V
from dropping below
CHGIN
by TJ_REG[2:0]) the charger attempts to limit the tem-
perature increase by reducing battery charge current. The
TJ_REG_STAT bit asserts whenever charge current is
reduced due to this loop. The charger's current sourcing
capability to SYS remains unaffected when TJ_REG_
STAT is high. A maskable interrupt (TJ_REG_I) asserts
to signal a change in TJ_REG_STAT. Use the TJ_REG_I
interrupt to signal the system processor to reduce loads
on SYS to reduce total system temperature.
V
if the cable between the charge source
CHGIN_UVLO
and the charger's input is long or highly resistive.
Table 8. Input Current Limit Factory
Options
95mA
475mA
ICHGIN_LIM
[2:0]
FACTORY-
DEFAULT
FACTORY-
DEFAULT
Charger State Machine
0b000
0b001
95mA
190mA
285mA
380mA
475mA
475mA
380mA
285mA
190mA
95mA
The battery charger follows a strict state-to-state progres-
sion to ensure that a battery is charged safely. The status
bitfield CHG_DTLS[3:0], reflects the charger's current
operational state. A maskable interrupt (CHG_I) is avail-
able to signal a change in CHG_DTLS[3:0].
0b010
0b011
0b100 - 0b111
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CHGIN INVALID
(CHGIN_DTLS[1:0] = 0b00 or 0b01)
OR
CHGIN INSERTED
(CHGIN_DTLS[1:0] = 0b10)
CHARGER DISABLED
(CHG_EN = 0)
DEBOUNCE
CHG_DTLS[3:0] = 0b0000
CHG = 0
CHARGER OFF
CHG_DTLS[3:0] = 0b0000
CHG = 0
ANY STATE
CHGIN DEBOUNCED
THM_EN = 1
AND
CHG_EN = 1
AND
TIME ELAPSED >= t
(CHGIN_DTLS[1:0] = 0b11)
CHGIN-DB
RETURNS TO SAME STATE WHEN:
THM_EN = 0
OR
CHARGER ENABLED (CHG_EN = 1)
AND
CHGIN DEBOUNCED AND VALID (CHGIN_DTLS[1:0] = 0b11)
TIME ELAPSED < t
CHGIN-DB
(T
BATT
< T
AND T
> T
)
COLD
HOT
BATT
(T
> T
OR T
< T
)
COLD
BATT
HOT
BATT
AND
BATTERY LOW BY V
(V
< V
– 150mV)
FAST-CHG
RESTART BATT
BATTERY TEMPERATURE
FAULT
CHG_DTLS[3:0] = 0b1100
CHG = 0
PREQUALIFICATION
CHG_DTLS[3:0] = 0b0001
CHG = 1
PREQUALIFICATION
TIMER FAULT
CHG_DTLS[3:0] = 0b1010
CHG = 0
TIME ELAPSED > t
PQ
I
= I
BATT PQ
V
< V – 100mV
PQ
BATT
V
> V
PQ
BATT
V
< V – 100mV
PQ
BATT
THM_EN = 1 AND
(T > T OR T
< T )
COOL
BATT
WARM
BATT
JEITA-MODIFIED
ANY FAST-CHARGE OR
JEITA-MODIFIED FAST-CHARGE
STATE
CHG_DTLS[3:0] = 0b0010-0b0101
CHG = 1
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0010
CHG = 1
FAST-CHARGE (CC)
CHG_DTLS[3:0] = 0b0011
CHG = 1
I
= I
**
BATT FAST-CHG
I
= I
**
THM_EN = 0 OR
(T < T
BATT FAST-CHG_JEITA
AND T
> T
)
COOL
BATT
WARM
BATT
V
<
BATT
V
= V
TIME ELAPSED* > t
FC
BATT
FAST-CHG_JEITA
V
< V
V
= V
FAST-CHG
BATT
FAST-CHG
BATT
V
FAST-CHG_JEITA
THM_EN = 1 AND
(T > T OR T
< T
)
BATT
WARM
BATT
COOL
JEITA-MODIFIED
FAST-CHARGE
TIMER FAULT
CHG_DTLS[3:0] = 0b1011
CHG = 0
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0100
CHG = 1
FAST-CHARGE (CV)
CHG_DTLS[3:0] = 0b0101
CHG = 1
V
BATT
= V
FAST-CHG
V
= V
FAST-CHG_JEITA
BATT
THM_EN = 0 OR
(T < T
AND T
> T
)
COOL
BATT
WARM
BATT
I
> I
I
< I
BATT TERM
BATT TERM
I
< I
BATT TERM
I
> I
BATT TERM
THM_EN = 1 AND
(T > T OR T
< T )
COOL
BATT
WARM
BATT
JEITA-MODIFIED
TOP-OFF
CHG_DTLS[3:0] = 0b0111
CHG = 1
TOP-OFF
CHG_DTLS[3:0] = 0b0110
CHG = 1
*TIME ELAPSED IS AGGREGATED
THROUGHOUT THE FAST-CHARGE AND
JEITA-MODIFIED FAST-CHARGE
V
BATT
= V
FAST-CHG
V
= V
FAST-CHG_JEITA
BATT
THM_EN = 0 OR
(T < T
STATES. ALL FAST-CHARGE STATES
(REGARDLESS OF JEITA STATUS)
SHARE THE SAME SAFETY TIMER.
AND T
> T
)
COOL
BATT
WARM
BATT
TIME ELAPSED > t
TO
TIME ELAPSED > t
TO
**I
CAN BE REDUCED BY THE
FAST-CHG
MINIMUM INPUT VOLTAGE REGULATION
LOOP, THE MINIMUM SYSTEM VOLTAGE
REGULATION LOOP, OR THE DIE
JEITA-MODIFIED DONE
CHG_DTLS[3:0] = 0b1001
CHG = 0
DONE
CHG_DTLS[3:0] = 0b1000
CHG = 0
TEMPERATURE REGULATION LOOP.
THM_EN = 0 OR
(T < T
AND T
> T
)
COOL
BATT
WARM
BATT
Figure 7. Charger State Diagram
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Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
A fast-charge safety timer starts when the state machine
Charger Off State
enters fast-charge (CC) or JEITA-modified fast-charge
(CC) from a non-fast-charge state. The timer continues to
run through all fast-charge states regardless of JEITA sta-
The charger is off when CHGIN is invalid, the charger is
disabled, or the battery is fresh.
CHGIN is invalid when the CHGIN input is invalid
tus. The timer length (t ) is programmable from 3 hours
FC
(V
< V
or V
> V
).
CHGIN
CHGIN_UVLO
CHGIN
CHGIN_OVP
to 7 hours in 2 hour increments with T_FAST_CHG[1:0].
If it is desired to charge without a safety timer, program
T_FAST_CHG[1:0] with 0b00 to disable the feature. If the
timer expires before the fast-charge states are exited, the
charger faults. See the Fast-Charge Timer Fault State
section for more information.
While CHGIN is invalid, the battery is connected to the
system. CHGIN voltage quality can be separately moni-
tored by the CHGIN_DTLS[1:0] status bitfield. Refer to
the Register Map for details.
The charger is disabled when the charger enable bit is 0
(CHG_EN = 0). The battery is connected or disconnected
If the charge current falls below 20% of the programmed
value during fast-charge (CC), the safety timer pauses.
The timer also pauses for the duration of supplement
mode events. The TIME_SUS bit indicates the status of
the fast-charge safety timer. Refer to the Register Map for
more details.
to the system depending on the validity of V
while
CHGIN
CHG_EN = 0. See the Smart Power Selector section.
The battery is fresh when CHGIN is valid and the charger
is enabled (CHG_EN = 1) and the battery is not low by
V
(V
BATT
> V
- V ). The bat-
RESTART
RESTART
FAST-CHG
tery is disconnected from the system and not charged
while the battery is fresh. The charger state machine exits
this state and begins charging when the battery becomes
Top-Off State
Top-off state is entered when the battery charge
current falls below I
during the fast-charge (CV)
low by V
(150mV, typ). This condition is function-
TERM
RESTART
state. I
is a percentage of I
and is
ally similar to done state. See Done State section.
TERM
FAST-CHG
programmable through I_TERM[1:0]. While in the top-off
state, the battery charger continues to hold the battery's
Prequalification State
The prequalification state is intended to assess a low-volt-
age battery's health by charging at a reduced rate. If the
battery voltage is less than the V
voltage at V . A programmable top-off timer
FAST-CHG
starts when the charger state machine enters the top-off
state. When the timer expires, the charger enters the
threshold, the charger
PQ
is automatically in prequalification. If the cell voltage does
not exceed V in 30 minutes (t ), the charger faults.
done state. The top-off timer value (t ) is programmable
TO
from 0 minutes to 35 minutes with T_TOPOFF[2:0]. If it is
desired to stop charging as soon as battery current falls
PQ
PQ
The prequalification charge rate is a percentage of I
FAST-
and is programmable with I_PQ. The prequalifica-
below I
, program t
to 0 minutes.
CHG
TERM
TO
tion voltage threshold (V ) is programmable through
PQ
Done State
CHG_PQ[2:0].
The charger enters the done state when the top-off timer
expires. The battery remains disconnected from the sys-
tem during done. The charger restarts if the battery volt-
Fast-Charge States
When the battery voltage is above V , the charger
transitions to the fast-charge (CC) state. In this state, the
charger delivers a constant current (I
cell. The constant current level is programmable from
PQ
age falls more than V
programmed V
(150mV, typ) below the
RESTART
value.
) to the
FAST-CHG
FAST-CHG
Prequalification Timer Fault State
7.5mA to 300mA by CHG_CC[5:0].
The prequalification timer fault state is entered when the
When the cell voltage reaches V
state machine transitions to fast-charge (CV). V
, the charger
FAST-CHG
battery's voltage fails to rise above V
in t
(30 min-
PQ
TO
FAST-
utes, typ) from when the prequalification state was first
entered. If a battery is too deeply discharged, damaged,
or internally shorted, the prequalification timer fault state
can occur. During the timer fault state, the charger stops
delivering current to the battery and the battery remains
disconnected from the system. To exit the prequalification
timer fault state, toggle the charger enable (CHG_EN)
bit or unplug and replug the external voltage source
connected to CHGIN.
is programmable with CHG_CV[5:0] from 3.6V to
CHG
4.6V. The charger holds the battery's voltage constant
at V while in the fast-charge (CV) state. As
FAST-CHG
the battery approaches full, the current accepted by the
battery reduces. When the charger detects that battery
charge current has fallen below I
machine enters the top-off state.
, the charger state
TERM
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
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The THM_DTLS[2:0] bitfield reports battery temperature
Fast-Charge Timer Fault State
status. See the Electrical Characteristics—Adjustable
Thermistor Temperature Monitors section and refer to the
Register Map for more information.
The charger enters the fast-charge timer fault state if the
fast-charge safety timer expires. While in this state, the
charger stops delivering current to the battery and the
battery remains disconnected from the system. To exit
the fast-charge timer fault state, toggle the charger enable
bit (CHG_EN) or unplug and replug the external voltage
source connected to CHGIN.
JEITA-Modified States
If the thermistor is enabled (THM_EN = 1), then the char-
ger state machine is allowed to enter the JEITA-modified
states. These states are entered if the charger's tem-
perature monitors indicate that the battery temperature
Battery Temperature Fault State
is either warm (greater than T
) or cool (lesser than
WARM
If the thermistor monitoring circuit reports that the battery
is either too hot or too cold to charge (as programmed by
THM_HOT[1:0] and THM_COLD[1:0]), the state machine
enters the battery temperature fault state. While in this
state, the charger stops delivering current to the battery
and the battery remains disconnected from the system.
This state can only be entered if the thermistor is enabled
(THM_EN = 1). Battery temperature fault state has prior-
ity over any other fault state, and can be exited when the
thermistor is disabled (THM_EN = 0) or when the battery
returns to an acceptable temperature. When this fault
state is exited, the state machine returns to the last state it
was in before battery temperature fault state was entered.
T
). See the Electrical Characteristics—Adjustable
COOL
Thermistor Temperature Monitors section for more infor-
mation about setting the temperature thresholds.
The charger's current and voltage parameters change
from I
and V
to I
and
FAST-CHG
FAST-CHG
FAST-CHG_JEITA
V
while in the JEITA-modified states. The
FAST-CHG_JEITA
JEITA modified parameters can be independently set to
lower voltage and current values so that the battery can
charge safely over a wide range of ambient temperatures.
If the battery temperature returns to normal, or the therm-
istor is disabled (THM_EN = 0), the charger exits the
JEITA-modified states.
All active charger timers (fast-charge safety timer,
prequalification timer, or top-off timer) are paused in this
state. When the charger exits this state, the prequalifica-
tion timer resumes while the fast-charge safety and top-off
timers reset.
Typical Charge Profile
A typical battery charge profile (and state progression) is
illustrated in Figure 8.
(V)
(mA)
500
400
CHGIN
5
SYS
V
= 4.5V
SYS-REG
V
= 4.25V
BATT
FAST-CHG
4
3
2
1
I
= 300mA
FAST-CHG
300
200
V
= 2.3V
PQ
I
BATT
100
t
TO
I
= 30mA
PQ
I
= 30mA
TERM
(TIME)
DONE
FAST-CHARGE (CV)
TOP-OFF
CHGIN
FAST-CHARGE (CC)
INVALID
PREQUALIFICATION
Figure 8. Example Battery Charge Profile
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
limit the maximum CHGIN input capacitance based on
the appropriate USB specification (i.e., typically no more
than 10μF).
Charger Applications Information
Configuring a Valid System Voltage
The Smart Power Selector begins to regulate SYS to
when CHGIN is connected to a valid source. To
Bypass SYS to GND with a 22μF ceramic capacitor. This
capacitor is needed to ensure stability of SYS while it
is being regulated from CHGIN. Larger values of SYS
capacitance increase decoupling for all SYS loads. The
effective value of the SYS capacitor must be greater than
4μF and no more than 100μF. Bypass BATT to GND with
a 4.7μF ceramic capacitor. This capacitor is required to
ensure stability of the BATT voltage regulation loop. The
effective value of the BATT capacitor must be greater
than 1μF.
V
SYS-REG
ensure the charger's accuracy specified in the Electrical
Characteristics table, the system voltage must always
be programmed at least 200mV above the charger's
constant-voltage level (V
). If this condition is not
FAST-CHG
met, then the charger's internal configuration logic forces
to reduce to satisfy the 200mV requirement. If
V
FAST-CHG
this happens, the charger asserts the SYS_CNFG_I inter-
rupt to alert the user that a configuration error has been
made and that the bits in CHG_CV[5:0] have changed to
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufac-
turer's data sheet.
reduce V
.
FAST-CHG
CHGIN/SYS/BATT Capacitor Selection
Bypass CHGIN to GND with a 4.7μF ceramic capacitor to
minimize inductive kick caused by long cables between
the DC charge source and the product/IC. Larger values
increase decoupling for the linear charger, but increase
inrush current from the DC charge source when the prod-
uct/IC is first connected to a source through a cable/plug.
If the DC charging source is an upstream USB device,
CHG_CV[5:0]
D0
D1
1.25V
V
FAST-CHG
TBIAS
CHG_CV_JEITA[5:0]
S0
S0
TBIAS SWITCH
CONTROL
(FIGURE 11)
CHG_CC[5:0]
D0
D1
R
BIAS
I
FAST-CHG
CHG_CC_JEITA[5:0]
THM
INTERNAL COOL/WARM SIGNAL
THM_DTLS[2:0] = 0b000 OR 0b101 (NTC
DISABLED OR BATTERY NORMAL).
CHARGER V&I PARAMETERS FOLLOW
THM_COLD[1:0]
0b0
NTC
NORMAL SETTINGS.
THM_DTLS[2:0] = 0b010 OR 0b011
(BATTERY COOL OR WARM). CHARGER
V&I PARAMETERS SWITCH TO JEITA
THM_EN
THM_COOL[1:0]
THM_WARM[1:0]
THM_HOT[1:0]
0b1
SETTINGS.
INTERNAL HOT/COLD SIGNAL
THM_DTLS[2:0] ≠ 0b001 OR 0b100
(BATTERY NOT COLD OR HOT). CHARGER
V&I PARAMETERS FOLLOW NORMAL OR
0b0
JEITA SETTINGS.
THM_DTLS[2:0] = 0b001 OR 0b100
0b1 (BATTERY COLD OR HOT). CHARGING IS
PAUSED REGARDLESS OF CHG_EN.
Figure 9. Thermistor Logic Functional Diagram
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
values, V
and I
, are
FAST-CHG_JEITA
FAST-CHG_JEITA
Detailed Description—Adjustable
Thermistor Temperature Monitors
programmable through CHG_CV_JEITA[5:0] and
CHG_CC_JEITA[5:0], respectively. These values are
independently programmable from the nonmodified
The optional use of a negative temperature coeffi-
cient (NTC) thermistor (thermally coupled to the battery)
enables the charger to operate safely over the JEITA
temperature range. When the thermistor is enabled
(THM_EN = 1), the charger continuously monitors the
voltage at the THM pin to sense the temperature of the
battery being charged.
V
and I
values and can even
FAST-CHG
FAST-CHG
be programmed to the same values if an automatic
response to a warm or cool battery is not desired. The
charger state machine enters JEITA-modified states
while the battery temperature is outside of normal.
●
If the battery temperature is either above T or below
HOT
See Figure 10 for a visual example of the following text:
T , the charger follows the JEITA recommendation
COLD
and pauses charging. The charger state machine enters
battery temperature fault state while charging is paused
due to extreme high or low temperatures.
● If the battery temperature is higher than T
and
COOL
lower than T , the battery charges normally with
WARM
the normal values for V
and I
. The
FAST-CHG
FAST-CHG
charger state machine does not enter JEITA-modified
states while the battery temperature is normal.
The battery's temperature status is reflected by the
THM_DTLS[2:0] status bitfield. A maskable interrupt
(THM_I) signals a change in THM_DTLS[2:0]. Refer to
the Register Map for more information. To completely dis-
able the charger's automatic response to battery tempera-
ture, disable the feature by programming THM_EN = 0.
● If the battery temperature is either above T
WARM
but below T
, or below T
but above
HOT
COOL
T
, the battery charges with the JEITA-modified
COLD
voltage and current values. These modified
EXAMPLE TEMPERATURES
FOR NTC β = 3380K
THM_COLD[1:0] = 0b10 (0°C)
THM_COOL[1:0] = 0b11 (15°C)
THM_WARM[1:0] = 0b10 (45°C)
THM_HOT[1:0] = 0b11 (60°C)
4.4V
4.3V
4.2V
4.1V
4.0V
V
= 4.2V
FAST-CHG
(CHG_CV[5:0] = 0b011000)
V
= 4.075V
FAST-CHG_JEITA
(CHG_CV_JEITA[5:0] = 0b010011)
COLD
COOL
NORMAL
25°C
WARM
HOT
75°C
-40°C
-25°C
0°C
15°C
45°C
60°C
85°C
T
T
T
T
HOT
COLD
COOL
BATTERY TEMPERATURE
WARM
I
= 150mA
FAST-CHG
(CHG_CC[5:0] = 0b010011)
0.15
0.1
0.05
0
I
= 75mA
FAST-CHG_JEITA
(CHG_CC_JEITA[5:0] = 0b001001)
COLD
COOL
NORMAL
WARM
HOT
-40°C
-25°C
0°C
15°C
25°C
45°C
60°C
75°C
85°C
T
T
T
T
HOT
COLD
COOL
BATTERY TEMPERATURE
WARM
Figure 10. Safe-Charging Profile Example
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
The voltage thresholds corresponding to the JEITA
temperature thresholds are independently programma-
ble through THM_HOT[1:0], THM_WARM[1:0], THM_
COOL[1:0], and THM_COLD[1:0]. Each threshold can
be programmed to one of four voltage options spanning
15°C for an NTC beta of 3380K. See the Configurable
Temperature Thresholds section and refer to the Register
Map for more information.
the function of the on-chip temperature monitors. Both
functions can be used simultaneously with no ill effect.
Configurable Temperature Thresholds
Temperature thresholds for different NTC thermistor beta
values are listed in Table 9. The largest possible program-
mable temperature range can be realized by using an NTC
with a beta of 3380K. Using a larger beta compresses the
temperature range. The trip voltage thresholds are pro-
grammable with the THM_HOT[1:0], THM_WARM[1:0],
THM_COOL[1:0], and THM_COLD[1:0] bitfields. All pos-
sible programmable trip voltages are listed in Table 9.
Thermistor Bias
An external ADC can optionally perform conversions on
the THM and TBIAS pins to measure the battery's tem-
perature. An on-chip analog multiplexer is used to route
these nodes to the AMUX pin. The operation of the analog
multiplexer does not interfere with the charger's tempera-
ture monitoring comparators or the charger's automatic
JEITA response. See the Detailed Description—Analog
Multiplexer section for more information.
These are theoretical values computed by a formula.
Refer to the particular NTC's data sheet for more accurate
measured data. In all cases, select the value of R
to
BIAS
be equal to the NTC's effective resistance at +25°C.
The NTC thermistor's bias source (TBIAS) follows the
simple operation outlined as follows:
THERMISTOR BIASED
TBIAS = 1.25V
● If CHGIN is valid and the thermistor is enabled (THM_
EN = 1), then the thermistor is biased so the charger
can automatically respond to battery temperature
changes.
MUX_SEL ≠ 0b0111 OR 0b1000
AND
(THM_EN = 0 OR CHGIN INVALID)
MUX_SEL = 0b0111 OR 0b1000
OR
(THM_EN = 1 AND CHGIN VALID)
●
If the analog multiplexer is connecting THM or TBIAS
to AMUX, then the thermistor is biased so an external
ADC can perform a meaningful temperature conversion.
THERMISTOR OFF
TBIAS = GND
The AMUX pin is a buffered output. The operation of the
analog multiplexer and external ADC does not collide with
Figure 11. Thermistor Bias State Diagram
Table 9. Trip Temperatures vs. Trip Voltages for Different NTC β
TRIP TEMPERATURES (°C)
TRIP
VOLTAGE (V)
3380K
-10.0
-5.0
3435K
-9.5
3940K
-5.6
4050K
-4.8
4100K
-4.5
4250K
-3.5
0.6
1.024
0.976
0.923
0.867
0.807
0.747
0.511
0.459
0.411
0.367
0.327
0.291
-4.6
-1.1
-0.5
-0.2
0.0
0.3
3.3
3.8
4.1
4.8
5.0
5.3
7.7
8.1
8.3
8.9
10.0
15.0
35.0
40.0
45.0
50.0
55.0
60.0
10.2
15.1
34.8
39.8
44.7
49.6
54.5
59.4
12.0
16.4
33.5
37.8
42.0
46.2
50.4
54.6
12.4
16.6
33.3
37.4
41.5
45.6
49.7
53.7
12.5
16.7
33.2
37.3
41.3
45.3
49.3
53.3
12.9
17.0
32.9
36.8
40.7
44.6
48.4
52.2
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Thermistor Applications Information
Using Different Thermistor β
TBIAS
If an NTC with a beta larger than 3380K is used and the
resulting available programmable temperature range is
undesirably small, then two adjusting resistors can be
R
BIAS
THM
used to expand the temperature range. R and R can
S
P
be optionally added to the NTC thermistor circuit (shown
in Figure 12) to expand the range of programmable
temperature thresholds.
R
S
R
P
NTC
Select values for R and R based on the information
S
P
shown in Table 10.
NTC Thermistor Selection
Figure 12. Thermistor Circuit with Adjusting Series and Parallel
Resistors
Popular NTC thermistor options are listed in Table 11.
Table 10. Example R and R Correcting Values for NTC β Above 3380K
S
P
DESIGN
TARGET
CASE
PARAMETER
UNIT
CASE 1
CASE 2
CASE 3
NTC thermistor beta
25°C NTC resistance
K
3380
10
3940
10
4050
47
4250
100
R
10
10
47
100
BIAS
Adjusting parallel resistor, R
open
short
45.24
22.61
5.81
open
200
0.62
open
680
3.3
open
1300
9.1
P
Adjusting series resistor, R
short
45.24
22.61
5.81
short
212.6
106.3
27.3
short
452.4
226.1
58.1
S
kΩ
R
R
R
R
at 1.024V
at 0.867V
at 0.459V
at 0.291V
threshold
threshold
threshold
578.5
248.8
5.36
306.1
122.7
25.1
684.8
264.7
51.7
NTC
COLD
COOL
WARM
NTC
NTC
threshold
HOT
3.04
3.04
2.46
14.3
112.7
-11.14
5.33
30.4
22.0
NTC
T
T
T
T
at V
at V
at V
at V
(-10°C expected)
(5°C expected)
(40°C expected)
-10.03
4.98
-5.56
7.66
-9.96
5.76
-4.82
8.10
-3.55
8.86
-10.46
5.94
ACTUAL
ACTUAL
ACTUAL
ACTUAL
COLD
COOL
WARM
°C
40.02
60.04
37.79
54.56
39.76
60.37
37.43
53.68
39.40
60.02
36.82
52.21
39.48
60.4
(60°C expected)
HOT
Table 11. NTC Thermistors
MANUFACTURER
PART#
Β-CONSTANT (25°C/50°C)
R (Ω) AT 25°C
CASE SIZE
TDK
NTCG063JF223HTBX
NCP03XH103F05RL
NCP15XH103F03RC
NTCG103JX103DT1
CMFX3435103JNT
3380K
3380K
3380K
3380K
3435K
3900K
4050K
4100K
4250K
22k
10k
10k
10k
10k
10k
47k
47k
100k
0201
0201
0402
0402
0402
0402
0201
0402
0402
Murata
Murata
TDK
Cantherm
Murata
NCP15XV103J03RC
ERT-JZEP473J
Panasonic
Panasonic
Murata
ABNTC-0402-473J-4100F-T
NCP15WF104F03RC
Maxim Integrated
│ 42
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
of quiescent current consumption and is only active when
a channel is selected (MUX_SEL[3:0] ≠ 0b0000). Disable
the buffer by programming MUX_SEL[3:0] to 0b0000
when not actively converting the voltage on AMUX. The
AMUX output is high-impedance while MUX_SEL[3:0] is
0b0000.
Detailed Description—Analog
Multiplexer
An external ADC can be used to measure the chip's
various signals for general functionality or on-the-fly power
monitoring. The MUX_SEL[3:0] bitfield controls the inter-
nal analog multiplexer responsible for connecting the prop-
er channel to the AMUX pin. Each measurable signal is
listed in Table 12 with its appropriate multiplexer channel.
Table 12 shows how to translate the voltage signal on the
AMUX pin to the value of the parameter being measured.
See the Electrical Characteristics table and refer to the
Register Map for more details.
The voltage on the AMUX pin is a buffered output that
ranges from 0V to V (1.25V, typ). The buffer has 50μA
FS
Table 12. AMUX Signal Transfer Functions
FULL-SCALE
SIGNAL MEANING
ZERO-SCALE
SIGNAL MEANING
MUX_SEL
SIGNAL
TRANSFER FUNCTION
[3:0]
(V
= 1.25V)
(V
= 0V)
AMUX
AMUX
V
AMUX
V
I
=
=
CHGIN pin voltage
CHGIN pin current
BATT pin voltage
0b0001
7.5V
0V
CHGIN
CHGIN
G
VCHGIN
V
AMUX
0b0010
0b0011
0.475A
4.6V
0A
0V
G
ICHGIN
V
AMUX
I
=
BATT
G
VBATT
V
BATT pin charging
current
100% of I
FAST-CHG
(CHG_CC[5:0])
AMUX
I
=
x I
0b0100
0% of I
FAST-CHG
BATT(CHG)
FAST−CHG
V
FS
V
− V
(
)
BATT pin
discharge current
100% of I
0% of
I
DISCHG-SCALE
AMUX
NULL
DISCHG-SCALE
I
=
x I
0b0101
0b0110
BATT(DISCHG)
DISCHG−SCALE
V
− V
NULL
(
)
FS
(IMON_DISCHG_SCALE[3:0])
BATT pin discharge
current NULL
V
= V
= V
1.25V
0V
NULL
AMUX
THM pin voltage
TBIAS pin voltage
AGND pin voltage*
0b0111
0b1000
0b1001
V
1.25V
1.25V
1.25V
0V
0V
0V
THM
AMUX
V
= V
= V
TBIAS
AGND
AMUX
V
AMUX
V
AMUX
V
=
SYS pin voltage
0b1010
4.8V
0V
SYS
G
VSYS
*AGND pin voltage is accessed through a 100Ω (typ) pulldown resistor.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Measuring Battery Current
I
=
BATT(DISCHG)
It is possible to sample the current in the BATT pin at any
time or in any mode with an external ADC. For improved
accuracy, the analog circuitry used for monitoring battery
discharge current is different from the circuitry monitoring
battery charge current. Table 13 outlines how to deter-
mine the direction of battery current.
V
− V
NULL
(
)
x I
AMUX
DISCHG-SCALE*
V
− V
NULL
(
)
FS
V
is 1.25V typical. I
through IMON_DISCHG_SCALE[3:0]. The default value
is 300mA. If smaller currents are anticipated, then
is programmable
FS
DISCHG-SCALE
Method for Measuring Discharging Current
I
can be reduced for improved measure-
DISCHG-SCALE
● Program the multiplexer to switch to the discharge
NULL measurement by changing MUX_SEL[3:0] to
0b0110. A NULL conversion must always be per-
formed first to cancel offsets.
ment accuracy.
Method for Measuring Charging Current
● Program the multiplexer to switch to the charge
current measurement by changing MUX_SEL[3:0]
to 0b0100.
● Wait the appropriate channel switching time
(0.3μs, typ).
● Wait the appropriate channel switching time
● Convert the voltage on the AMUX pin and store as
(0.3μs, typ).
V
NULL
.
● Convert the voltage on the AMUX pin and use the
following transfer function to determine charging
current.
● Program the multiplexer to switch to the battery
discharge current measurement by changing MUX_
SEL[3:0] to 0b0101. A nonnulling conversion should
be done immediately after a NULL conversion.
V
AMUX
I
=
x I
FAST−CHG
BATT(DISCHG)
V
● Wait the appropriate channel switching time (0.3μs,
FS
typ).
V
is 1.25V typical. I
the charger's fast-charge
FAST-CHG
FS
● Convert the voltage on AMUX pin and use the fol-
lowing transfer function to determine the discharge
current:
constant-current setting and is programmable through
CHG_CC[5:0].
Table 13. Battery Current Direction Decode
CHARGING OR DISCHARGING INDICATORS
CHG_DTLS[3:0]
MEASUREMENT
CHG BIT
CHGIN_DTLS[1:0]
Discharging Battery Current
(Positive Battery Terminal
Sourcing Current)
0b00
0b01
0b10
Don't care
Don't care
Charging Battery Current
(Positive Battery Terminal
Sinking Current)
1
0b0001 - 0b0111
0b11
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
● CHGIN is inserted and debounced valid
Detailed Description—Linear Regulator
The IC integrates a 150mA PMOS low-dropout linear
(CHGIN_DTLS[1:0] = 0b11)
● Software caused a cold reset (SFT_CTRL[1:0] =
0b01) and the reset actions are finished and LDO_
EN[1:0] is factory-programmed to 0b10
(SFT_WAKE internal flag set)
voltage regulator (LDO). Output voltage is programmable
through I C between 0.8V and 3.975V in 25mV steps
using the LDO_VREG[6:0] bitfield. The LDO features a
2
low-I (1.5μA, typ) low-power mode which reduces system
Q
idle power consumption. The LDO input (INLDO) can be
connected directly to SYS or supplied by an external step-
down regulator for increased power efficiency. A 100Ω (typ)
active-discharge resistor is available to quickly discharge
the LDO's output after the regulator has been disabled.
The LDO deactivates regardless of LDO_EN[1:0] when
any of the following conditions are true:
● SYS undervoltage-lockout
● SYS overvoltage-lockout
● Chip over-temperature lockout
LDO Enable Control
● Software causes a power-off
Force the LDO on by writing LDO_EN[1:0] to 0b01 with
(SFT_CTRL[1:0] = 0b10)
2
I C. The on/off controller begins the LDO power-up
sequence when this bit combination is set.
● Software causes a reset (SFT_CTRL[1:0] = 0b01)
Disable the LDO (force off) by writing LDO_EN[1:0] to
0b00 with I C. This bit combination causes the LDO
● Software requests factory-ship mode
2
(SFT_CTRL[1:0] = 0b11)
power-down sequence to happen.
● The watchdog timer is enabled and expires
Setting the bits in LDO_EN[1:0] to 0b10 causes the LDO
to activate due to hardware inputs (nENLDO or CHGIN)
or special software commands. This bit combination
causes the on/off controller to begin the LDO power-up
sequence when:
(WDT_EXP internal flag set)
● Manual reset occurs (MAN_RST internal flag set)
Consult the On/Off Controller section and Table 1 of the
data sheet for more details.
The reset value of the bits in LDO_EN[1:0] is factory-
programmable. Consult the Ordering Information for
details.
● nENLDO is asserted for t
DBNC_nENLDO
(LDO_WAKE internal flag set)
INLDO
SYS
DC INPUT
C
4.7µF
INLDO
(1.7V – V
)
SYS
ADE_LDO
LDO_VREG[6:0]
150mA LDO
LDO
GND
LDO_EN[1:0]
PWR_MODE
LDO_WAKE
V
LDO
ON/OFF
CONTROLLER
(0.8V – 3.975V)
C
2.2µF
LDO
LDO_PM[1:0]
R
AD_LDO
100kΩ
POKLDO
PMLDO
POWER-OK
PMLDO
POWER MODE
Figure 13. LDO Simplified Block Diagram
Maxim Integrated
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
LDO Power Mode (PMLDO)
LDO Applications Information
Program the LDO_PM[1:0] bitfield to 0b00 to configure
the LDO in low-power mode. Program 0b01 to config-
ure the LDO for normal mode. Program 0b10 or 0b11
to enable hardware control of the power mode through
the PMLDO pin. Code 0b10 enables normal mode when
PMLDO is logic-high. Code 0b11 enables normal mode
when PMLDO is logic-low. If the MSB of LDO_PM[1:0] is
set, then always drive the PMLDO pin to prevent mode
chatter. If the MSB is not set, then the PMLDO pin is a
don't care. See Table 14 for a truth table of this behavior.
Input/Output Capacitor Selection
Bypass INLDO to GND with a minimum 10μF ceramic
capacitor. If INLDO is connected to SYS, then a single
22μF bypass capacitor to GND can be used for both pins.
Bypass the LDO output to GND with a minimum 2.2μF
ceramic capacitor that maintains 1.1μF of effective capac-
itance at bias. Larger values of LDO capacitance improve
decoupling but increase inrush current during LDO start-
up. Refer to Startup Rate and Inrush Current for guidance
on managing startup inrush current.
The LDO can support loads of 150mA with an I
INLDO-Q
Ceramic capacitors with X5R or X7R dielectric are highly
recommended due to their small size, low ESR, and small
temperature coefficients. All ceramic capacitors derate
with DC bias voltage (effective capacitance goes down as
DC bias goes up). Generally, small case size capacitors
derate heavily compared to larger case sizes (0603 case
size performs better than 0402). Consider the effective
capacitance value carefully by consulting the manufac-
turer's data sheet.
of 12μA (1.8V
) in normal mode. Loads of 5mA with a
LDO
reduced I
of 1.5μA (1.8V
) are supported in
INLDO-Q
LDO
low-power mode.
A system similar to the block diagram in Figure 14
can dynamically manage the LDO's power mode and
minimize I consumption. When the low-power micro-
Q
controller (U2) disables the dynamic load (U3) then the
PMLDO pin is brought low indicating that the LDO goes
to low-power mode. When the host enables the load,
then the PMLDO pin becomes high and the LDO enters
normal power mode to support the current demand of the
dynamic load.
Startup Rate and Inrush Current
The startup ramp rate of the LDO can be controlled using
the following equation:
I
∆V
LDO Power-OK Output (POKLDO)
LDO – LIM
LDO
=
∆t
8 x C
LDO
The IC features an open-drain LDO Power-OK (POKLDO)
output to monitor the LDO output voltage. POKLDO
requires an external pullup resistor to a voltage equal
where I
is the output current limit of the LDO in
LDO-LIM
normal mode (300mA, typ) and C
capacitor (2.2μF minimum required).
is the LDO output
to or less than V
. This node goes high when
LDO
SYS
V
LDO
rises above V
(typically 87.5% of pro-
POKLDO_R
grammed V
) and goes low when V
falls
LDO-REG
LDO
).
Applications that are sensitive to inrush current from the
battery should select an LDO output capacitor as close
to the minimum stability requirement as possible (2.2μF),
while at the same time, maximizing the INLDO and SYS
capacitance to filter any large current spikes from BATT.
below V
(typically 84% of V
POKLDO_F
LDO-REG
POKLDO is blanked by the on/off controller during the LDO
power-up and power-down sequences (Figure 2). The
blanking signal holds POKLDO low regardless of V
.
LDO
U1
1.8V
Table 14. LDO Power Mode Truth Table
LDO
U2
U3
VCC
IN
MAX77734
PMIC
LDO_PM[1:0]
(BITFIELD)
LDO POWER
MODE
PMLDO (PIN)
LOW-POWER
MICRO
DYNAMIC LOAD
EN
LDO_PM[1:0] = 0b10
X
X
0
1
0
1
00
01
10
10
11
11
Low-Power
Normal
POKLDO
PMLDO
RST
DIG_O
Low-Power
Normal
Normal
Figure 14. Dynamic LDO Power Mode Control Idea
Low-Power
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
PCB Layout Guidelines
Careful printed circuit board (PCB) layout is necessary to achieve optimal performance. Follow these guidelines when
designing the PCB:
1) Place decoupling components (C
, C
, C
, C
, C
) close to the IC.
CHGIN SYS BATT INLDO LDO
2) A single decoupling capacitor can be used to bypass both SYS and INLDO to GND. Use a short and wide copper
flood to connect SYS and INLDO.
3) If INLDO has a different power source (other than SYS), then a separate INLDO decoupling capacitor (not drawn in
Figure 15) is recommended.
4) The value of C
should be larger than C
. If C
= 2.2μF, then choose C
= 4.7μF or greater.
INLDO
INLDO
LDO
LDO
Figure 15 shows an example PCB top-metal layout with 0.2mm component-to-component spacing.
GND
CHGIN
V
L
GND
CCHGIN
CVL
AMUX
nENLDO
PMLDO
POKLDO
SYS
nIRQ
SDA
SCL
BATT
LEGEND
0603
V
IO
GND
LDO
CLDO
SNK1
SNK2
GND
0402
TBIAS
THM
0201
● PULLUPS NOT DRAWN
● INLDO CONNECTS TO SYS
VIAS
COMPONENT SIZES
LISTED IN IMPERIAL
Figure 15. PCB Top-Metal and Component Layout Example
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
2
I C is an open-drain bus and therefore SDA and SCL
Detailed Description—Dual-Channel
Current Sink Driver
require pullups.
2
The device's I C communication controller implements
7-bit slave addressing. An I C bus master initiates com-
The IC has a dual-channel current sink driver designed
to drive LEDs in portable devices (see Figure 16). The
circuit can also be used as a general-purpose current sink
driver for other applications. The driver's on-time and fre-
quency are independently programmable for each output
to achieve a desired blink pattern. Alternatively, the LEDs
can be continuously on (not blinking). The blink period is
programmable from 0.5s to 8s, with an on-time duty cycle
from 6.25% to 100%.
2
munication with the slave by issuing a START condition
followed by the slave address. The slave address is
factory programmable to one of two options (Table 15).
All slave addresses not mentioned in Table 15 are not
acknowledged.
The IC uses 8-bit registers with 8-bit register address-
ing. They support standard communication protocols:
(1) Writing to a single register (2) Writing to multiple
sequential registers with an automatically increment-
ing data pointer (3) Reading from a single register (4)
Reading from multiple sequential registers with an auto-
matically incrementing data pointer. For additional infor-
mation on the I C protocols, refer to the MAX77734 I C
Implementer’s Guide and/or the I C specification that is
freely available on the internet.
2
Detailed Description—I C Serial
Interface
2
The IC features a revision 3.0 I C-compatible, 2-wire
serial interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). The IC is a slave-only
device that relies on an external bus master to generate
SCL. SCL clock rates from 0Hz to 3.4MHz are supported.
2
2
2
SYS
CLK_64_S
EN_SNK_MSTR
BRT_SNK1[4:0]
CLOCK
CLK_64
CURRENT SINK 1
SNK1
DAC
INV_SNK1
P_SNK1[3:0]
D_SNK1[3:0]
CLK_64
PWM
PATTERN
LOGIC
EN_SNK1
2/4/8Ω
SNK_FS1[1:0]
SNK2
GND
CURRENT SINK 2
BRT_SNK2[4:0]
INV_SNK2
P_SNK2[3:0]
D_SNK2[3:0]
CLK_64
SNK_FS2[1:0]
Figure 16. LED Current Sinks Functional Block Diagram
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
2
Table 15. I C Slave Address Options
ADDRESS
7-BIT SLAVE ADDRESS
8-BIT WRITE ADDRESS
8-BIT READ ADDRESS
Main Address
(ADDR = 1)*
0x48, 0b 100 1000
0x90, 0b 1001 0000
0x91, 0b 1001 0001
Main Address
(ADDR = 0)*
0x40, 0b 100 0000
0x49, 0b 100 1001
0x80, 0b 1000 0000
0x92, 0b 1001 0010
0x81, 0b 1000 0001
0x93, 0b 1001 0011
Test Mode**
*Perform all reads and writes on the Main Address. ADDR is a factory one-time programmable (OTP) option, allowing for address
changes in the event of a bus conflict. Contact Maxim for more information.
**When test mode is unlocked, the additional address is acknowledged. Test mode details are confidential. If possible, leave the test
mode address unallocated to allow for the rare event that debugging needs to be performed in cooperation with Maxim.
Register Map
MAX77734
ADDRESS
NAME
MSB
LSB
GLOBAL CONFIGURATION
POKLDO_
I
nENLDO_ nENLDO_
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
INT_GLBL[7:0]
RSVD
RSVD
RSVD
TJAL2_R
TJAL1_R
RSVD
CHG_I
RSVD
THM_I
R
F
SYS_
CNFG_I
SYS_
CTRL_I
CHGIN_
CTRL_I
TJ_
REG_I
INT_CHG[7:0]
CHGIN_I
VCHGIN_
MIN_STAT LIM_STAT MIN_STAT
ICHGIN_
VSYS_
TJ_REG_
STAT
STAT_CHG_A[7:0]
STAT_CHG_B[7:0]
ERCFLAG[7:0]
THM_DTLS[2:0]
TIME_
SUS
CHG_DTLS[3:0]
CHGIN_DTLS[1:0]
CHG
WDT_
RST
SYS-
OVLO
WDT_OFF SFT_RST SFT_OFF
POKLDO_
MRST
SYSUVLO
TOVLD
STAT_EN-
LDO
STAT_
IRQ
STAT_GLBL[7:0]
INTM_GLBL[7:0]
INT_M_CHG[7:0]
DIDM[1:0]
TJAL2_S
TJAL1_S
BOK
S
POKLDO_
IM
TJAL2_
RM
TJAL1_
RM
nENLDO_ nENLDO_
RSVD
RSVD
RSVD
RSVD
RM
FM
SYS_
CNFG_M
SYS_
CTRL_M
CHGIN_
CTRL_M
TJ_
REG_M
CHGIN_M CHG_M THM_M
BIAS_
LPM
BIAS_
REQ
nENLDO_ DB_nEN-
0x08
0x09
0x0A
CNFG_GLBL[7:0]
CID[7:0]
PU_DIS
—
T_MRST
—
SFT_CTRL[1:0]
MODE
LDO
—
—
CID[3:0]
WDT_
MODE
WDT_
EN
WDT_
LOCK
CNFG_WDT[7:0]
RSVD
RSVD
WDT_PER[1:0]
WDT_CLR
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
MAX77734 (continued)
ADDRESS
NAME
MSB
LSB
CHARGER CONFIGURATION
0x20
0x21
CNFG_CHG_A[7:0]
CNFG_CHG_B[7:0]
THM_HOT[1:0]
VCHGIN_MIN[2:0]
THM_WARM[1:0]
THM_COOL[1:0]
ICHGIN_LIM[2:0]
THM_COLD[1:0]
CHG_
I_PQ
EN
0x22
0x23
CNFG_CHG_C[7:0]
CNFG_CHG_D[7:0]
CHG_PQ[2:0]
I_TERM[1:0]
T_TOPOFF[2:0]
VSYS_REG[4:0]
TJ_REG[2:0]
T_FAST_
CHG[1:0]
0x24
0x25
0x26
CNFG_CHG_E[7:0]
CNFG_CHG_F[7:0]
CNFG_CHG_G[7:0]
CHG_CC[5:0]
THM_
RSVD
EN
CHG_CC_JEITA[5:0]
CHG_CV[5:0]
USBS
RSVD
RSVD
RSVD
0x27
0x28
CNFG_CHG_H[7:0]
CNFG_CHG_I[7:0]
CHG_CV_JEITA[5:0]
IMON_DISCHG_SCALE[3:0]
MUX_SEL[3:0]
LDO CONFIGURATION
ADE_
LDO
0x30
0x31
CNFG_LDO_A[7:0]
CNFG_LDO_B[7:0]
LDO_VREG[6:0]
LDO_PM[1:0]
LDO_EN[1:0]
CURRENT SINKS CONFIGURATION
INV_
SNK1
0x40
0x41
0x42
0x43
CNFG_SNK1_A[7:0]
CNFG_SNK1_B[7:0]
CNFG_SNK2_A[7:0]
CNFG_SNK2_B[7:0]
SNK_FS1[1:0]
BRT_SNK1[4:0]
P_SNK1[3:0]
D_SNK1[3:0]
BRT_SNK2[4:0]
D_SNK2[3:0]
INV_
SNK2
SNK_FS2[1:0]
P_SNK2[3:0]
EN_
SNK_
MSTR
CLK_
64_S
0x44
CNFG_SNK_TOP[7:0]
—
—
—
—
—
—
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
INT_GLBL (0x00)
BIT
7
6
5
4
3
2
1
0
Field
RSVD
0b0
POKLDO_I
0b0
TJAL2_R
0b0
TJAL1_R
0b0
nENLDO_R nENLDO_F
0b0 0b0
RSVD
0b0
RSVD
0b0
Reset
Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears
Access Type
All
All
All
All
All
All
All
All
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
SYSRST
Reserved. Reads back 0.
N/A
0 = POKLDO_S has not changed since
the last time this bit was read.
1 = POKLDO_S has changed since the
last time this bit ws read.
POKLDO_I
TJAL2_R
6
5
SYSRST
POKLDO Interrupt
0 = The junction temperature has not
risen above T
since the last time
JAL2
this bit was read.
1 = The junction temperature has risen
above T since the last time this bit
SYSRST
SYSRST
Thermal Alarm 2 Rising Interrupt
Thermal Alarm 1 Rising Interrupt
JAL2
was read.
0 = The junction temperature has not
risen above T since the last time
JAL1
this bit was read.
1 = The junction temperature has risen
above T since the last time this bit
TJAL1_R
4
JAL1
was read.
0 = No nENLDO rising edges have
occurred since the last time this bit
was read.
1 = A nENLDO rising edge as occurred
since the last time this bit was read.
nENLDO_R
nENLDO_F
3
2
SYSRST
SYSRST
nENLDO Rising Interrupt
nENLDO Falling Interrupt
0 = No nENLDO falling edges have
occurred since the last time this bit
was read.
1 = A nENLDO falling edge as occurred
since the last time this bit was read.
RSVD
RSVD
1
0
SYSRST
SYSRST
Reserved. Reads back 0.
Reserved. Reads back 0.
N/A
N/A
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
INT_CHG (0x01)
BIT
7
6
5
4
3
2
1
0
SYS_
CNFG_I
SYS_
CTRL_I
CHGIN_
CTRL_I
Field
RSVD
TJ_REG_I
CHGIN_I
CHG_I
THM_I
Reset
0b1
0b0
0b0
0b0
0b0
0b0
0b0
0b0
Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears Read Clears
Access Type
All
All
All
All
All
All
All
All
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
SYSRST
Reserved. Reads back 0.
System Voltage Configuration Error
Interrupt. Goes high when V
N/A
SYS-REG
0 = No configuration error since the last
time this bit was read.
1 = The bits in CHG_CV[5:0] have been
and V
are programmed too
FAST-CHG
close to each other. Reads back 1 when
the bit combination in CHG_CV[5:0] or
CHG_CV_JEITA[5:0] has been forced
to change (reduce) to ensure
SYS_CNFG_I
SYS_CTRL_I
6
SYSRST
forced to change to ensure V
SYS-REG
is 200mV above V
.
FAST-CHG
V
= V
+ 200mV.
SYS-REG
FAST-CHG
Minimum System Voltage Regulation
Loop Related Interrupt. Signals a
change in VSYS_MIN_STAT.
0 = VSYS_MIN_STAT has not changed
since the last time this bit was read.
1 = VSYS_MIN_STAT has changed.
5
4
SYSRST
SYSRST
CHGIN Control-Loop Related Interrupt.
Signals a change in the minimum input
voltage regulation loop (VCHGIN_MIN_
STAT) or the input current-limit loop
(ICHGIN_LIM_STAT).
0 = Neither VCHGIN_MIN_STAT nor
ICHGIN_LIM_STAT has changed since
the last time this bit was read.
1 = VCHGIN_MIN_STAT or
ICHGIN_LIM_STAT has changed.
CHGIN_
CTRL_I
Die Junction Temperature Regulation
Interrupt. Signals a change in the die
temperature regulation loop
(TJ_REG_STAT).
0 = TJ_REG_STAT has not changed
since the last time this bit was read.
1 = TJ_REG_STAT has changed.
TJ_REG_I
CHGIN_I
3
2
SYSRST
SYSRST
0 = The bits in CHGIN_DTLS[1:0] have
not changed since the last time this bit
was read.
1 = The bits in CHGIN_DTLS[1:0] have
changed.
CHGIN Related Interrupt. Signals a
change in CHGIN_DTLS[1:0].
0 = The bits in CHG_DTLS[3:0] have not
changed since the last time this bit was
read.
1 = The bits in CHG_DTLS[3:0] have
changed.
Charger Related Interrupt. Signals a
change in CHG_DTLS[3:0].
CHG_I
THM_I
1
0
SYSRST
SYSRST
0 = The bits in THM_DTLS[2:0] have not
changed since the last time this bit was
read.
1 = The bits in THM_DTLS[2:0] have
changed.
Thermistor Related Interrupt. Signals a
change in THM_DTLS[2:0].
Maxim Integrated
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
STAT_CHG_A (0x02)
BIT
Field
7
6
5
4
3
2
1
0
VCHGIN_
MIN_STAT
ICHGIN_
LIM_STAT
VSYS_
MIN_STAT
TJ_REG_
STAT
RSVD
THM_DTLS[2:0]
Reset
0b0
0b0
0b0
0b0
0b0
0b000
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
CHGPOK
Reserved. Reads back 0.
N/A
0 = The minimum CHGIN voltage
regulation loop has not engaged.
1 = The loop has engaged to reduce
CHGIN current to regulate
VCHGIN_
MIN_STAT
Minimum Input Voltage Regulation Loop
Status
6
CHGPOK
V
≥ V
.
CHGIN
CHGIN-MIN
0 = The CHGIN current-limit loop is
not engaged.
1 = The loop has engaged to regulate
ICHGIN_
LIM_STAT
5
4
CHGPOK
CHGPOK
Input Current-Limit Loop Status
I
≤ I
CHGIN-LIM
CHGIN
0 = The minimum system voltage
regulation loop is not engaged.
1 = The loop has engaged to regulate
VSYS_
MIN_STAT
Minimum System Voltage Regulation
Loop Status
V
≥ V
.
SYS
SYS-MIN
0 = The maximum junction temperature
regulation loop is not engaged.
1 = The loop has engaged and is
reducing charge current to limit die
temperature.
TJ_REG_
STAT
Maximum Junction Temperature
Regulation Loop Status
3
CHGPOK
0b000 = Thermistor is diabled
(THM_EN = 0).
0b001 = Battery is cold as programmed
by THM_COLD[1:0].
0b010 = Battery is cool as programmed
by THM_COOL[1:0].
0b011 = Battery is warm as programmed
by THM_WARM[1:0].
0b100 = Battery is hot as programmed by
THM_HOT[1:0].
Battery Temperature Details
Valid Only When
CHGIN_DTLS[1:0] = 0b11
THM_DTLS
2:0
CHGPOK
0b101 = Battery temperature is normal
as programmed by CNFG_CHG_A
register.
0b110-0b111 = Reserved.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
STAT_CHG_B (0x03)
BIT
Field
7
6
5
4
3
2
1
CHG
0
CHG_DTLS[3:0]
0b0000
CHGIN_DTLS[1:0]
0b00
TIME_SUS
0b0
Reset
0b0
Access Type
Read Only
Read Only
Read Only
Read Only
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b0000 = Charger off.
0b0001 = Prequalification mode.
0b0010 = Fast-charge constant-current
(CC) mode.
0b0011 = JEITA-modified fast-charge
constant-current mode.
0b0100 = Fast-charge constant-voltage
(CV) mode.
0b0101 = JEITA-modified fast-charge
constant-voltage mode.
0b0110 = Top-off mode.
Charger Details. Indicates the current
state of the charger.
CHG_DTLS
7:4
CHGPOK
0b0111 = JEITA-modified top-off mode.
0b1000 = Done.
0b1001 = JEITA-modified done
(done was entered through the
JEITA-modified fast-charge states).
0b1010 = Prequalification timer fault.
0b1011 = Fast-charge timer fault.
0b1100 = Battery temperature fault.
0b1101-0b1111 = Reserved.
0b00 = CHGIN voltage is below the
UVLO threshold (V
) or
CHGIN_UVLO
USB suspended (USBS = 1).
0b01 = CHGIN voltage is above the
OVP threshold (V ).
0b10 = The CHGIN input is being
debounced (no power drawn from
CHGIN during debounce).
0b11 = The CHGIN input is debounced
and valid.
CHGIN_
DTLS
CHGIN_OVP
3:2
CHGPOK
CHGIN Status Details
0 = Charging is not happening.
1 = Charging is happening.
CHG
1
0
CHGPOK
CHGPOK
Quick Charger Status
Time Suspend Indicator. The fast-charge
safety timer susepnds if any of the
following are true: charge current has
dropped below 20% of I
while
0 = Charger's timers are not active or
not suspended.
1 = Charger's active timer suspended.
FAST-CHG
TIME_SUS
the charger state machine is in FAST
CHARGE (CC) state, the charger is in
suppliment mode, or the charger state
machine is in BATTERY TEMPERATURE
FAULT mode.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
ERCFLAG (0x04)
BIT
7
6
5
4
3
2
1
0
Field
WDT_RST WDT_OFF
SFT_RST
0b0
SFT_OFF
0b0
MRST
0b0
SYSUVLO
0b0
SYSOVLO
0b0
TOVLD
0b0
Reset
0b0
0b0
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read
Clears All
Read Clears
All
Read Clears
All
Access Type
BITFIELD
RESET-
TYPE
BITS
DESCRIPTION
DECODE
Watchdog Timer Reset Flag. This bit
0 = Watchdog timer has not caused a power-
sets when the watchdog timer expires reset since the last time this bit was read.
WDT_RST
WDT_OFF
7
SYSPOR
SYSPOR
and causes a power-reset
(WTD_EXP = 1 and
WTD_MODE = 1).
1 = Watchdog timer has expired and caused
a power-reset since the last time this bit
was read.
0 = Watchdog timer has not caused a power-off
since the last time this bit was read.
1 = Watchdog timer has expired and caused
a power-off since the last time
Watchdog Timer OFF Flag. This bit
sets when the watchdog timer expires
and causes a power-off (WDT_EXP =
1 and WDT_MODE = 0).
6
this bit was read.
0 = No software caused power-reset since
the last time this bit was read.
1 = Software has caused a power-reset since
the last time this bit was read.
Software Reset Flag. This bit sets
when an I C write causes a power-
reset (SFT_RST[1:0] = 0b01).
2
SFT_RST
SFT_OFF
MRST
5
4
3
SYSPOR
SYSPOR
SYSPOR
0 = No software caused power-off since the
last time this bit was read.
1 = Software has caused a power-off since
the last time this bit was read.
Software OFF Flag. This bit sets when
2
an I C write causes a power-off
(SFT_CTRL[1:0] = 0b10).
Manual Reset Timer Flag. This bit sets 0 = Manual reset has not caused power-reset
when a manual reset event
(MAN_RST = 1) causes a power
reset.
since the last time this bit was read.
1 = Manual reset has caused power-reset
since the last time this bit ws read.
0 = SYS domain undervoltage lockout has
not caused a power-off since the last time
this bit was read.
1 = SYS domain undervoltage lockout has
caused a power-off since the last time this bit
was read.
SYS Domain Undervoltage-Lockout
Flag. This bit sets when the SYS
domain voltage falls below
SYSUVLO
2
SYSPOR
V
and causes a power-off.
SYSUVLO
0 = SYS domain overvoltage lockout has
not caused a power-off since the last time
this bit was read.
1 = SYS domain overvoltage lockout has
caused a power-off since the last time this
bit was read.
SYS Domain Overvoltage-Lockout
Flag. This bit sets when the SYS do-
SYSOVLO
TOVLD
1
0
SYSPOR
SYSPOR
main voltage rises above V
SYSOVLO
and causes a power-off.
0 = Thermal overload has not caused a
power-off since the last time this bit was read.
1 = Thermal overload has caused a power-off
since the last time this bit was read.
Thermal Overload Flag. This bit sets
when the junction temperature ex-
ceeds 165°C and causes a power-off.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
STAT_GLBL (0x05)
BIT
Field
7
6
5
4
3
2
1
0
STAT_
ENLDO
DIDM[1:0]
POKLDO_S
TJAL2_S
TJAL1_S
BOK
STAT_IRQ
Reset
0b10
0b0
0b0
0b0
0b0
0b0
0b0
Access Type
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
RESET-
TYPE
BITFIELD
DIDM
BITS
7:6
5
DESCRIPTION
DECODE
0b00 = Reserved for future use.
0b01 = Reserved for future use.
0b10 = MAX77734
Device Identification Bits for
Metal Options
SYSRST
SYSRST
SYSRST
0b11 = Reserved for future use.
LDO Power-OK Status. Continuous
software mirror of the POKLDO pin.
0 = POKLDO is low
1 = POKLDO is high (Hi-Z)
POKLDO_S
TJAL2_S
0 = The junction temperature is less
than T
JAL2
4
Thermal Alarm 2 Status
Thermal Alarm 1 Status
1 = The junction temperature is
greater than T
JAL2
0 = The junction temperature is less
than T
1 = The junction temperature is greater
JAL1
TJAL1_S
3
SYSRST
than T
JAL1
STAT_
ENLDO
Debounced Status for the
nENLDO input
0 = nENLDO is not asserted (logic high)
1 = nENLDO is asserted (logic low)
2
1
SYSRST
SYSRST
0 = Bias not ready or not enabled.
1 = Bias enabled and ready.
BOK
System Bias OK Status Bit
0 = No interrupts pending. nIRQ would
be high if all interrupts were unmasked.
1 = Interrupts pending. nIRQ would be
low if all interrupts were unmasked.
Interrupt Status. Continuous inverted
software mirror of the nIRQ pin as if all
interrupts were unmasked.
STAT_IRQ
0
SYSRST
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
INTM_GLBL (0x06)
BIT
Field
Reset
7
6
5
4
3
2
1
0
POKLDO_
IM
nENLDO_
RM
nENLDO_
FM
RSVD
0b0
TJAL2_RM
0b1
TJAL1_RM
0b1
RSVD
0b0
RSVD
0b0
0b1
0b1
0b1
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
RESET-
TYPE
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
SYSRST
Reserved. Bit is a don't care.
N/A
POKLDO_I Interrupt Mask. Setting this
bit prevents the POKLDO_I bit from
causing hardware interrupts.
0 = POKLDO_I is not masked.
1 = POKLDO_I is masked.
POKLDO_IM
TJAL2_RM
6
5
4
3
2
SYSRST
SYSRST
SYSRST
SYSRST
SYSRST
Thermal Alarm 2 Rising Interrupt Mask.
Setting this bit prevents the TJAL2_R
bit from causing hardware interrupts.
0 = TJAL2_R is not masked.
1 = TJAL2_R is masked.
Thermal Alarm 1 Rising Interrupt Mask.
Setting this bit prevents the TJAL1_R
bit from causing hardware interrupts.
0 = TJAL1_R is not masked.
1 = TJAL1_R is masked.
TJAL1_RM
nENLDO Rising Interrupt Mask. Setting
this bit prevents the nENLDO_R bit
from causing hardware interrupts.
0 = nENLDO_R is unmasked.
1 = nENLDO_R is masked.
nENLDO_RM
nENLDO_FM
nENLDO Falling Interrupt Mask. Setting
this bit prevents the nENLDO_F bit
from causing hardware interrupts.
0 = nENLDO_F is not masked.
1 = nENLDO_F is masked.
RSVD
RSVD
1
0
SYSRST
SYSRST
Reserved. Bit is a don't care.
Reserved. Bit is a don't care.
N/A
N/A
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
INT_M_CHG (0x07)
BIT
Field
Reset
7
6
5
4
3
2
1
0
SYS_
CNFG_M
SYS_
CTRL_M
CHGIN_
CTRL_M
RSVD
0b1
TJ_REG_M
0b1
CHGIN_M
0b1
CHG_M
0b1
THM_M
0b1
0b1
0b1
0b1
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7
6
SYSRST
Reserved. Bit is a don't care.
N/A
SYS_
CNFG_M
Setting this bit prevents the SYS_CNFG_I 0 = SYS_CNFG_I is not masked.
bit from causing hardware interrupts. 1 = SYS_CNFG_I is masked.
SYSRST
SYSRST
SYS_
CTRL_M
Setting this bit prevents the SYS_CTRL_I 0 = SYS_CTRL_I is not masked.
bit from causing hardware interrupts.
5
4
1 = SYS_CTRL_I is masked.
Setting this bit prevents the CHGIN_
CTRL_I bit from causing hardware
interrupts.
CHGIN_
CTRL_M
0 = CHGIN_CTRL_I is not masked.
1 = CHGIN_CTRL_I is masked.
SYSRST
Setting this bit prevents the TJ_REG_I bit 0 = TJ_REG_I is not masked.
TJ_REG_M
CHGIN_M
CHG_M
3
2
1
0
SYSRST
SYSRST
SYSRST
SYSRST
from causing hardware interrupts.
1 = TJ_REG_I is masked.
Setting this bit prevents the CHGIN_I bit
from causing hardware interrupts.
0 = CHGIN_I is not masked.
1 = CHGIN_I is masked.
Setting this bit prevents the CHG_I bit
from causing hardware interrupts.
0 = CHG_I is not masked.
1 = CHG_I is masked.
Setting this bit prevents the THM_I bit
from causing hardware interrupts.
0 = THM_I is not masked.
1 = THM_I is masked.
THM_M
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_GLBL (0x08)
BIT
Field
Reset
7
6
5
4
3
2
1
0
nENLDO_
MODE
DB_nEN-
LDO
PU_DIS
0b0
T_MRST
OTP
BIAS_LPM
0b1
BIAS_REQ
0b0
SFT_CTRL[1:0]
OTP
OTP
0b00
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read
Write, Read
RESET-
TYPE
BITFIELD
PU_DIS
BITS
DESCRIPTION
DECODE
0 = 200kΩ pullup resistor for momentary
push buttons
1 = 10MΩ pullup resistor for persistent
slide switches
nENLDO Internal Pullup Resistor
7
6
SYSRST
Control to V
CCINT
0 = 8 seconds
1 = 16 seconds
T_MRST
SYSRST
SYSRST
Sets the Manual Reset Time (t
)
MRST
0 = Bias requested to be in normal-power
mode whenever it is enabled.
1 = Bias requested to be in low-power
mode whenever it is enabled.
System Bias Low-Power Mode Software
Request
BIAS_LPM
5
0 = Bias not requested on by software.
1 = Bias forced on by software.
BIAS_REQ
4
3
2
SYSRST
SYSRST
SYSRST
System Bias Enable Software Request
nENLDO_
MODE
nENLDO (ONKEY) Default Configuration 0 = Push-button mode
Mode
1 = Slide-switch mode
0 = 200μs debounce
1 = 30ms debounce
DB_nENLDO
Debounce Timer for the nENLDO pin
0b00 = No Action
0b01 = Software Reset. Causes a
power-reset. The IC powers down,
configuration registers reset (SYSRST),
and the IC powers up and turns the LDO
on again.
0b10 = Software Off. The IC powers
down, configuration registers reset, and
the IC remains off and waits for a wake-
up event to turn on again.
SFT_CTRL
1:0
SYSRST
Software Control Functions
0b11 = Factory-Ship Mode Enter (FSM).
The IC powers down, configuration
registers reset, and the internal BATT to
SYS switch opens. The device remains
this way until a factory-ship mode exit
event occurs.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CID (0x09)
BIT
Field
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
CID[3:0]
OTP
Reset
Access Type
Read Only
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
CID
3:0
SYSPOR
Chip Identification Code for OTP Options Varies depending on Factory Options.
CNFG_WDT (0x0A)
BIT
7
6
5
4
3
2
1
0
WDT_
MODE
Field
Reset
RSVD
0b0
RSVD
0b0
WDT_PER[1:0]
0b11
WDT_CLR
0b0
WDT_EN
OTP
WDT_LOCK
OTP
0b0
Write 1 to
Clear, Read
Access Type Write, Read Write, Read
Write, Read
Write, Read
Write, Read
Read Only
RESET-
TYPE
BITFIELD
RSVD
BITS
DESCRIPTION
DECODE
7
6
SYSRST
SYSRST
Reserved. Bit is a don't care.
Reserved. Bit is a don't care.
N/A
N/A
RSVD
Watchdog Timer Period. Sets t
Watchdog timer is reset to the
programmed value as soon as this
.
0b00 = 16 seconds
0b01 = 32 seconds
0b10 = 64 seconds
0b11 = 128 seconds
WD
WDT_PER
5:4
SYSRST
bitfield is changed.
0 = Watchdog timer expire causes
power-off.
1 = Watchdog timer expire causes
power-reset.
Watchdog Timer Expired Action.
Determines what the IC does after the
watchdog timer expires.
WDT_MODE
WDT_CLR
3
2
SYSRST
SYSRST
Watchdog Timer Clear Control. Set this
bit to feed (reset) the watchdog timer.
0 = Watchdog timer period is not reset.
1 = Watchdog timer is reset back to t
.
WD
0 = Watchdog timer is not enabled.
WDT_EXP = 0 always.
1 = Watchdog timer is enabled. If the
timer expires without being fed (reset)
then WDT_EXP = 1.
Watchdog Timer Enable. Write protected
depending on WDT_LOCK.
WDT_EN
1
0
SYSRST
SYSRST
0 = Watchdog timer can be enabled and
disabled with WDT_EN.
1 = Watchdog timer can not be disabled
with WDT_EN. (WDT_EN can still be
used to enable the watchdog timer.)
Factory-Set Safety Bit for the Watchdog
Timer. Determines if the timer can be
disabled through WTD_EN or not.
WDT_LOCK
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_A (0x20)
BIT
Field
7
6
5
4
3
2
1
0
THM_HOT[1:0]
THM_WARM[1:0]
0b00
THM_COOL[1:0]
0b11
THM_COLD[1:0]
0b11
Reset
0b00
Access Type
Write, Read
Write, Read
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b00 = 0.411V
Sets the V
Temperature Threshold
JEITA
0b01 = 0.367V
0b10 = 0.327V
0b11 = 0.291V
HOT
THM_HOT
7:6
SYSRST
0b00 = 0.511V
0b01 = 0.459V
0b10 = 0.411V
0b11 = 0.367V
Sets the V
Temperature Threshold
JEITA
WARM
THM_WARM
THM_COOL
THM_COLD
5:4
3:2
1:0
SYSRST
SYSRST
SYSRST
0b00 = 0.923V
0b01 = 0.867V
0b10 = 0.807V
0b11 = 0.747V
Sets the V
JEITA
COOL
Temperature Threshold
0b00 = 1.024V
0b01 = 0.976V
0b10 = 0.923V
0b11 = 0.867V
Sets the V
JEITA
COLD
Temperature Threshold
Maxim Integrated
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_B (0x21)
BIT
Field
7
6
5
4
3
2
1
0
VCHGIN_MIN[2:0]
0b000
ICHGIN_LIM[2:0]
0b000
I_PQ
0b0
CHG_EN
OTP
Reset
Access Type
Write, Read
Write, Read
Write, Read Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b000 = 4.0V
0b001 = 4.1V
0b010 = 4.2V
0b011 = 4.3V
0b100 = 4.4V
0b101 = 4.5V
0b110 = 4.6V
0b111 = 4.7V
VCHGIN_
MIN
Sets the Minimum CHGIN Regulation
Voltage (V
7:5
SYSRST
)
CHGIN-MIN
This bitfield decoding changes depending
on factory option. See Table 8 for details.
0b000 = 95mA/475mA
0b001 = 190mA/380mA
0b010 = 285mA
Sets the CHGIN Input Current Limit
(I
ICHGIN_LIM
4:2
CHGPOK
)
CHGIN-LIM
0b011 = 380mA/190mA
0b100-0b111 = 475mA/95mA
Sets the prequalification charge current
0 = 10%
1 = 20%
I_PQ
1
0
SYSRST
SYSRST
(I ) as a percentage of I
.
FAST-CHG
PQ
0 = Disabled
1 = Enabled
CHG_EN
Charger enable
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_C (0x22)
BIT
Field
7
6
5
4
3
2
1
0
CHG_PQ[2:0]
0b111
I_TERM[1:0]
0b11
T_TOPOFF[2:0]
0b000
Reset
Access Type
Write, Read
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b000 = 2.3V
0b001 = 2.4V
0b010 = 2.5V
0b011 = 2.6V
0b100 = 2.7V
0b101 = 2.8V
0b110 = 2.9V
0b111 = 3.0V
Sets the Battery Prequalification
Voltage Threshold (V
CHG_PQ
7:5
SYSRST
SYSRST
SYSRST
)
PQ
0b00 = 5%
0b01 = 7.5%
0b10 = 10%
0b11 = 15%
Sets the Battery Charge Termination
Current (I ) as a Percentage of
I_TERM
4:3
2:0
TERM
FAST-CHG
I
0b000 = 0 minutes
0b001 = 5 minutes
0b010 = 10 minutes
0b011 = 15 minutes
0b100 = 20 minutes
0b101 = 25 minutes
0b110 = 30 minutes
0b111 = 35 minutes
T_TOPOFF
Sets the Top-Off Timer Value (t
)
TO
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_D (0x23)
BIT
Field
7
6
5
4
3
2
1
0
TJ_REG[2:0]
0b000
VSYS_REG[4:0]
0b10000
Reset
Access Type
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b000 = 60°C
0b001 = 70°C
0b010 = 80°C
0b011 = 90°C
Sets the Die Junction Temperature
Regulatoin Point (T
TJ_REG
7:5
SYSRST
)
J-REG
0b100-0b111 = 100°C
0b00000 = 4.100V
0b00001 = 4.125V
Sets the System Voltage Regulation Point 0b00010 = 4.150V
While CHGIN is Valid (V ). ...
This 5-bit configuration is a linear transfer 0b10000 = 4.500V
SYS-REG
VSYS_REG
4:0
SYSRST
function that starts at 4.1V and ends at
4.8V, with 25mV increments.
...
0b11010 = 4.750V
0b11011 = 4.775V
0b11100-0b11111 = 4.800V
CNFG_CHG_E (0x24)
BIT
Field
7
6
5
4
3
2
1
0
CHG_CC[5:0]
T_FAST_CHG[1:0]
0b01
Reset
0b000001
Access Type
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
Sets the Fast-Charge Constant Current
Value (I ).
This 6-bit configuration is a linear
transfer function that starts at 7.5mA and
ends at 300mA, with 7.5mA increments.
0b000000 = 7.5mA
0b000001 = 15mA
...
FAST-CHG
CHG_CC
7:2
SYSRST
SYSRST
0b100111-0b111111 = 300mA
0b00 = timer disabled
0b01 = 3 hours
0b10 = 5 hours
T_FAST_
CHG
1:0
Sets the Fast-Charge Safety Timer (t
)
FC
0b11 = 7 hours
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_F (0x25)
BIT
Field
7
6
5
4
3
2
1
0
CHG_CC_JEITA[5:0]
0b000001
THM_EN
0b0
RSVD
0b0
Reset
Access Type
Write, Read
Write, Read Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
for when the
DECODE
Sets I
FAST-CHG_JEITA
battery is either cool or warm as defined
by the T and T temperature
thresholds. This register is a don't care if
the battery temperature is normal or if
THM_EN = 0.
This 6-bit configuration is a linear transfer
function that starts at 7.5mA and ends
at 300mA, with 7.5mA increments.
COOL
WARM
0b000000 = 7.5mA
0b000001 = 15mA
...
CHG_
CC_JEITA
7:2
SYSRST
0b100111-0b111111 = 300mA
Thermistor Enable. Setting this bit causes
the charger to enable the thermistor bias
(TBIAS) and continuously monitor battery
temperature. Does not collide with
0 = Disabled
1 = Enabled
THM_EN
RSVD
1
0
SYSRST
SYSRST
MUX_SEL[3:0] settings 0x7 or 0x8.
Reserved Control Bit. Write to 0.
N/A
CNFG_CHG_G (0x26)
BIT
Field
7
6
5
4
3
2
1
0
CHG_CV[5:0]
USBS
0b0
RSVD
0b0
Reset
0b000000
Access Type
Write, Read
Write, Read Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
Sets fast-charge battery regulation
voltage (V ). Internal logic
FAST-CHG
0b000000 = 3.600V
0b000001 = 3.625V
...
clamps the maximum V
value
FAST-CHG
CHG_CV
7:2
SYSRST
to 200mV less than V
.
SYS-REG
This 6-bit configuration is a linear transfer
function that starts at 3.6V and ends at
4.6V, with 25mV increments.
0b1010000-0b111111 = 4.6V
Setting this bit places CHGIN in USB
suspend mode. CHGIN can not draw
power from an external source while in
USB suspend mode.
0 = CHGIN is not suspended.
1 = CHGIN is suspended.
USBS
RSVD
1
0
CHGPOR
SYSRST
Reserved. Bit is a don't care.
N/A
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_H (0x27)
BIT
Field
7
6
5
4
3
2
1
0
CHG_CV_JEITA[5:0]
0b000000
RSVD
0b0
RSVD
0b0
Reset
Access Type
Write, Read
Write, Read Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
for when the
DECODE
Sets V
FAST-CHG_JEITA
battery is either cool or warm as defined
by the T and T temperature
COOL
WARM
thresholds. This register is a don't care
if the battery temperature is normal or
if THM_EN = 0.
0b000000 = 3.600V
0b000001 = 3.625V
...
CHG_
CV_JEITA
7:2
SYSRST
Internal logic clamps the maximum
V
value to 200mV less
0b1010000-0b111111 = 4.6V
FAST-CHG_JEITA
than V
.
SYS-REG
This 6-bit configuration is a linear transfer
function that starts at 3.6V and ends at
4.6V, with 25mV increments.
RSVD
RSVD
1
0
SYSRST
SYSRST
Reserved. Bit is a don't care.
Reserved. Bit is a don't care.
N/A
N/A
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_CHG_I (0x28)
BIT
Field
7
6
5
4
3
2
1
0
IMON_DISCHG_SCALE[3:0]
0b1111
MUX_SEL[3:0]
Reset
0b0000
Access Type
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b0000 = 8.2mA
0b0001 = 40.5mA
0b0010 = 72.3mA
0b0011 = 103.4mA
0b0100 = 134.1mA
0b0101 = 164.1mA
0b0110 = 193.7mA
0b0111 = 222.7mA
0b1000 = 251.2mA
0b1001 = 279.3mA
0b1010-0b1111 = 300mA
Selects the battery discharge current
full-scale current value.
This 4-bit configuration starts at 8.2
and ends at 300mA.
IMON_
DISCHG_
SCALE
7:4
SYSRST
0b0000 = Multiplexer is disabled and
AMUX is high-impedance.
0b0001 = CHGIN voltage monitor.
0b0010 = CHGIN current monitor.
0b0011 = BATT voltage monitor.
0b0100 = BATT charge current monitor.
Valid only while battery charging is
happening (CHG = 1).
0b0101 = BATT discharge current
monitor normal measurement.
0b0110 = BATT discharge current
monitor nulling measurement.
0b0111 = THM voltage monitor.
0b1000 = TBIAS voltage monitor.
0b1001 = AGND voltage monitor
(through 100Ω pulldown resistor).
0b1010-0b1111 = SYS voltage monitor.
Selects the analog channel to connect to
AMUX. The AMUX output buffer
consumes current unless it is in the
0b0000 state. When measurements are
not needed, configure
MUX_SEL
3:0
SYSRST
MUX_SEL[3:0] = 0b0000.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_LDO_A (0x30)
BIT
Field
Reset
7
6
5
4
3
2
1
0
ADE_LDO
0b1
LDO_VREG[6:0]
OTP
Access Type Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0 = Disabled
1 = Enabled
ADE_LDO
7
SYSRST
LDO Active Discharge Resistor Control
0x00 = 0.800V
0x01 = 0.825V
...
0x27 = 1.775V
0x28 = 1.800V
...
LDO Target Regulation Voltage
(V
).
LDO-REG
LDO_VREG
6:0
SYSRST
This 7-bit configuration is a linear
transfer function that starts at 0.8V and
ends at 3.975V, with 25mV increments.
0x7E = 3.950V
0x7F = 3.975V
CNFG_LDO_B (0x31)
BIT
Field
3
2
1
0
LDO_PM[1:0]
LDO_EN[1:0]
Reset
0b01
OTP
Access Type
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b00 = Forced low-power mode
0b01 = Forced normal mode
0b10 = Pin-controlled, active high
(normal mode when PMLDO pin is high)
0b11 = Pin-controlled, active low
LDO_PM
3:2
SYSRST
SYSRST
LDO Power Mode Control
(normal mode when PMLDO pin is low)
0b00 = LDO is forced disabled
0b01 = LDO is forced enabled
0b10 = LDO enables when nENLDO
asserts or when CHGIN is valid.
0b11 = Same as 0b10.
LDO_EN
1:0
LDO Enable Control
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_SNK1_A (0x40)
BIT
Field
7
6
5
4
3
2
1
0
SNK_FS1[1:0]
INV_SNK1
0b0
BRT_SNK1[4:0]
0b00100
Reset
0b00
Access Type
Write, Read
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b00 = Disabled
0b01 = Enabled with 3.2mA full-scale
range (0.1mA LSB)
0b10 = Enabled with 6.4mA full-scale
range (0.2mA LSB)
SNK1 Enable and Full-Scale Range
Control
SNK_FS1
7:6
SYSRST
0b11 = Enabled with 12.8mA full-scale
range (0.4mA LSB)
0 = Positive-Duty Operation. SNK1 is
on during the beginning of each period
for the programmed duty length.
1 = Negative-Duty Operation. SNK1 is
off during the beginning of each period
for the programmed duty length.
INV_SNK1
5
SYSRST
SNK1 Invert Control
SNK1 Current (Brightness) Control
SNK_FS1[1:0] = 0b00
don't care
0x00 = 0.1mA/0.2mA/0.4mA
0x01 = 0.2mA/0.4mA/0.8mA
...
SNK_FS1[1:0] = 0b01
0.1mA–3.2mA in 0.1mA steps
BRT_SNK1
4:0
SYSRST
SNK_FS1[1:0] = 0b10
0.2mA–6.4mA in 0.2mA steps
0x1F = 3.2mA/6.4mA/12.8mA
SNK_FS1[1:0] = 0b11
0.4mA–12.8mA in 0.4mA steps
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_SNK1_B (0x41)
BIT
Field
7
6
5
4
3
2
1
0
P_SNK1[3:0]
0b0000
D_SNK1[3:0]
0b1111
Reset
Access Type
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0x0 = 0.5s
0x1 = 1.0s
0x2 = 1.5s
0x3 = 2.0s
0x4 = 2.5s
0x5 = 3.0s
0x6 = 3.5s
0x7 = 4.0s
0x8 = 4.5s
0x9 = 5.0s
0xA = 5.5s
0xB = 6.0s
0xC = 6.5s
0xD = 7.0s
0xE = 7.5s
0xF = 8s
P_SNK1
7:4
SYSRST
SNK1 Period Control
0x0 = 6.25%
0x1 = 12.5%
0x2 = 18.75%
0x3 = 25%
0x4 = 31.25%
0x5 = 37.5%
0x6 = 43.75%
0x7 = 50%
0x8 = 56.25%
0x9 = 62.5%
0xA = 68.75%
0xB = 75%
D_SNK1
3:0
SYSRST
SNK1 Duty Cycle Control
0xC = 81.25%
0xD = 87.5%
0xE = 93.75%
0xF = 100%
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_SNK2_A (0x42)
BIT
Field
7
6
5
4
3
2
1
0
SNK_FS2[1:0]
INV_SNK2
0b0
BRT_SNK2[4:0]
0b00100
Reset
0b00
Access Type
Write, Read
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0b00 = Disabled
0b01 = Enabled with 3.2mA full-scale
range (0.1mA LSB)
0b10 = Enabled with 6.4mA full-scale
range (0.2mA LSB)
SNK2 Enable and Full-Scale
Range Control
SNK_FS2
7:6
SYSRST
0b11 = Enabled with 12.8mA full-scale
range (0.4mA LSB)
0 = Positive-Duty Operation. SNK2 is
on during the beginning of each period
for the programmed duty length.
1 = Negative-Duty Operation. SNK2 is
off during the beginning of each period
for the programmed duty length.
INV_SNK2
5
SYSRST
SNK2 Invert Control
SNK2 Current (Brightness) Control
SNK_FS2[1:0] = 0b00
don't care
0x00 = 0.1mA/0.2mA/0.4mA
0x01 = 0.2mA/0.4mA/0.8mA
...
SNK_FS2[1:0] = 0b01
0.1mA–3.2mA in 0.1mA steps
BRT_SNK2
4:0
SYSRST
SNK_FS2[1:0] = 0b10
0x1F = 3.2mA/6.4mA/12.8mA
0.2mA–6.4mA in 0.2mA steps
SNK_FS2[1:0] = 0b11
0.4mA–12.8mA in 0.4mA steps
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_SNK2_B (0x43)
BIT
Field
7
6
5
4
3
2
1
0
P_SNK2[3:0]
0b0000
D_SNK2[3:0]
0b1111
Reset
Access Type
Write, Read
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
0x0 = 0.5s
0x1 = 1.0s
0x2 = 1.5s
0x3 = 2.0s
0x4 = 2.5s
0x5 = 3.0s
0x6 = 3.5s
0x7 = 4.0s
0x8 = 4.5s
0x9 = 5.0s
0xA = 5.5s
0xB = 6.0s
0xC = 6.5s
0xD = 7.0s
0xE = 7.5s
0xF = 8s
P_SNK2
7:4
SYSRST
SNK2 Period Control
0x0 = 6.25%
0x1 = 12.5%
0x2 = 18.75%
0x3 = 25%
0x4 = 31.25%
0x5 = 37.5%
0x6 = 43.75%
0x7 = 50%
0x8 = 56.25%
0x9 = 62.5%
0xA = 68.75%
0xB = 75%
D_SNK2
3:0
SYSRST
SNK2 Duty Cycle Control
0xC = 81.25%
0xD = 87.5%
0xE = 93.75%
0xF = 100%
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
CNFG_SNK_TOP (0x44)
BIT
Field
7
6
5
4
3
2
1
0
EN_SNK_
MSTR
—
—
—
—
—
—
CLK_64_S
Reset
—
—
—
—
—
—
—
—
—
—
—
—
0b0
0b0
Access Type
Read Only
Write, Read
RESET-
TYPE
BITFIELD
BITS
DESCRIPTION
DECODE
RSVD
7:2
—
64Hz Clock Mirror. CLK_64_S is
internally driven by the same clock that
drives the current sink PWM logic.
This signal has a 10% duty cycle.
Allows software to align LED blink
patterns between SNK1 and SNK2.
0 = Root clock is low.
1 = Root clock is high.
CLK_64_S
1
0
SYSRST
EN_SNK_
MSTR
0 = Current sinks disabled.
1 = Current sinks enabled.
SYSRST
Master Sink Enable Bit
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Typical Application Circuits
Battery Charger using LDO Hardware Enable Key
4.5V
5V DC INPUT
CHGIN
SYS
C 22μF
SYS
C
4.7μF
CHGIN
SYSTEM LOADS
MAX77734
10V (0603)
25V (0402)
INLDO
V
L
C
1μF
nENLDO
LDO
VL
6V (0402)
C
2.2μF
ON-KEY
LDO
GND
6V (0402)
V
(0.8V – 3.975V)
LDO
BATT
THM
V
IO
C
4.7μF
BATT
Li+
10V (0402)
POKLDO
SDA
TBIAS
NTC 3380K
= 10kΩ
10kΩ
R
25
μC
SCL
SYS
nIRQ
SNK1
SNK2
PMLDO
AMUX
ADC
Battery Charger using LDO Software Enable
4.5V
5V DC INPUT
CHGIN
SYS
C
22μF
SYS
C
4.7μF
25V (0402)
CHGIN
MAX77734
SYSTEM LOADS
10V (0603)
INLDO
V
L
nENLDO
LDO
C
1μF
VL
V
(0.8V – 3.975V)
LDO
6V (0402)
C
2.2μF
6V (0402)
LDO
GND
100k
150mA LOAD
POKLDO
BATT
THM
C
4.7μF
BATT
C
0.1μF
VIO
Li+
10V (0402)
6V (0402)
V
IO
TBIAS
NTC 3380K
= 10kΩ
10kΩ
SDA
SCL
IO SUPPLY
R
25
SYS
μC
SNK1
SNK2
nIRQ
PMLDO
AMUX
ADC
Maxim Integrated
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Ordering Information
PART NUMBER
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 WLP
FACTORY OPTIONS
MAX77734ENP+*
Engineering samples with custom options
MAX77734AENP+T**
MAX77734BENP+T
MAX77734CENP+T
MAX77734GENP+T
MAX77734QENP+T
20 WLP
A
B
20 WLP
20 WLP
C
G
Q
20 WLP
20 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*Custom samples only. Not for production or stock. Contact factory for information.
**Future product—contact factory for availability.
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MAX77734
Ultra-Low Power Tiny PMIC with Power Path
Charger for Small Li+ and 150mA LDO
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
6/17
Initial release
—
Updated General Description and Applications sections, replaced Simplified
Application Circuit, Figure 5, Figure 8, Figure 13, and Figure 15, updated Typical
Operating Characteristics, Table 1 changed to Table 3, Table 3 changed to Table 1,
corrected symbology
1, 15, 17, 20,
21, 25−28,
30−33, 38, 39,
45, 47, 73, 74
1
2
9/17
5/18
1, 3, 7, 9, 19,
20, 26, 29, 30,
33, 42, 45-47,
66, 73, 74
Updated Electrical Characteristics tables, updated TOC6, replaced Table 10, updated
Figure 13, added new section called PCB Layout Guidelines, updated
CNFG_CHG_I (0x28) in Register Map, updated Ordering Information table
1, 26,
33, 74, 75
Updated Table 1, added new part number to Table 6, added new part number to
Ordering Information table
3
4
7/18
1, 10, 33,
40, 53, 75
Updated Electrical Characteristics table, updated descriptions in Register Map section,
added MAX77734Q to the Ordering Information table
11/18
1, 29, 36, 38,
59, 69, 71
Updated Benefits and Features, Shutdown (Bias Off) State section, Figure 7, Battery
Temperature Fault State section, and descriptions in Register Map section
5
7/20
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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