MAX78630 [MAXIM]
Energy Measurement Processor for Polyphase Monitoring Systems;
| 型号： | MAX78630 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Energy Measurement Processor for Polyphase Monitoring Systems 监控 |
| 文件： | 总77页 (文件大小：900K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX78630+PPM
Energy Measurement Processor
for Polyphase Monitoring Systems
DATA SHEET
GENERAL DESCRIPTION
BENEFITS AND FEATURES
The MAX78630+PPM is an energy measurement processor
(EMP) for polyphase power monitoring systems. It is
designed for real-time monitoring for a variety of typical
three-phase configurations in industrial applications. It is
available in a 32-pin TQFN package.
• Six Configurable Analog Inputs for Monitoring
a Variety of Delta- and Wye-Connected
Three-phase Topologies
• Supports Current Transformers (CT),
Resistive Shunts, and Rogowski Coils
• Delta-Sigma ADC with Precision Voltage
Reference and On-Chip Temperature Sensor
• Internal or External Oscillator Timing
Reference
• SPI, I2C, or UART Interface Options with
Configurable I/O pins for alarm Signaling,
Address Pins, or User Control
The MAX78630+PPM provides up to six analog inputs for
interfacing to voltage and current sensors. Scaled voltages
from the sensors are fed to the single converter front-end
utilizing a high-resolution delta-sigma converter. Supported
current sensors include current transformers (CT),
Rogowski coils, and resistive shunts.
An embedded 24-bit measurement processor and firmware
perform all necessary computations and data formatting for
accurate reporting to the host. With integrated flash
memory for storing nonvolatile calibration coefficients and
device configuration settings, the MAX78630+PPM is
capable of being a completely autonomous solution.
• 24-Bit Measurement Processor with
Integrated Firmware and Flash Memory for
Nonvolatile Storage of Calibration and
Configuration Parameters
• Supports Extraction of Individual Harmonics
• Small 32-TQFN Package and Reduced Bill of
Materials
The MAX78630+PPM is designed to interface to the host
processor via the UART interface. Alternatively, SPI or I2C
may also be used.
Single Converter
Measurement
Front End
UART
Voltage
Sensors
Processor
Digital
I/O
Host
Controller
MUX
ADC
RAM
SPI
Current
Sensors
FLASH
I2C
MAX78630+PPM
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6679; Rev 3; 8/14
MAX78630+PPM Data Sheet
Table of Contents
ABSOLUTE MAXIMUM RATINGS .......................................................................................................4
Recommended External Components..................................................................................................4
Recommended Operating Conditions...................................................................................................4
Performance Specifications ..................................................................................................................5
Input Logic Levels .......................................................................................................................5
Output Logic Levels ....................................................................................................................5
Supply Current ............................................................................................................................5
Crystal Oscillator .........................................................................................................................5
Internal RC Oscillator ..................................................................................................................5
ADC Converter, V3P3 Referenced................................................................................................6
Timing Specifications............................................................................................................................7
Reset 7
SPI Slave Port.............................................................................................................................7
I2C Slave Port (Note 1)................................................................................................................8
Pin Configuration........................................................................................................................................9
Package Information...........................................................................................................................11
On-Chip Resources Overview .................................................................................................................12
IC Block Diagram ................................................................................................................................12
Clock Management.............................................................................................................................13
Power-On Reset, Watchdog-Timer, and Reset Circuitry....................................................................14
Analog Front-End and Conversion .....................................................................................................15
24-Bit Measurement Processor ..........................................................................................................17
Flash and RAM ...................................................................................................................................17
Digital I/O Pins ....................................................................................................................................17
Communication Interfaces ..................................................................................................................17
Functional Description and Operation....................................................................................................18
Measurement Interface.......................................................................................................................18
AFE Input Multiplexer................................................................................................................18
High Pass Filters and Offset Removal ......................................................................................19
Enabling the software integrators for Rogowski Coil current sensors ......................................19
Gain Correction .........................................................................................................................19
Die Temperature Compensation...............................................................................................20
Phase Compensation................................................................................................................20
Voltage Input Configuration.......................................................................................................21
Current Input Configuration.......................................................................................................23
Current Input Flowchart.............................................................................................................24
Data Refresh Rates ............................................................................................................................25
Scaling Registers and Result Formats ...............................................................................................25
Calibration...........................................................................................................................................26
Voltage and Current Gain Calibration .......................................................................................26
Offset Calibration ......................................................................................................................26
Die Temperature Calibration.....................................................................................................26
Voltage Channel Measurements ........................................................................................................27
RMS Voltage .............................................................................................................................27
Line Frequency..........................................................................................................................27
Current Channel Measurements.........................................................................................................28
Peak Current .............................................................................................................................28
RMS Current .............................................................................................................................28
Current and Voltage Imbalance ..........................................................................................................29
Power Calculations .............................................................................................................................30
Active Power (P) .......................................................................................................................30
Reactive Power (Q)...................................................................................................................31
Apparent Power (S)...................................................................................................................31
Power Factor (PF).....................................................................................................................31
2
Rev 3
MAX78630+PPM Data Sheet
Totals of active power, reactive power, apparent power and power factor ..............................31
Fundamental and Harmonic Calculations...........................................................................................33
Energy Calculations............................................................................................................................34
Bucket Size for Energy Counters..............................................................................................35
Min/Max Tracking................................................................................................................................36
Voltage Sag Detection ........................................................................................................................37
Voltage Sign Outputs..........................................................................................................................38
Alarm Monitoring.................................................................................................................................38
Status Registers..................................................................................................................................39
Digital IO Functionality........................................................................................................................40
DIO Direction.............................................................................................................................41
DIO Polarity...............................................................................................................................41
Alarm Pins.................................................................................................................................41
Command Register .............................................................................................................................42
General Settings .......................................................................................................................42
No Action (0x00xxxx) ................................................................................................................42
Save to Flash Command (0xACC2xx) ......................................................................................43
Clear Flash Storage 0 Command (0xACC0xx).........................................................................43
Clear Flash Storage 1 Command (0xACC1xx).........................................................................43
Calibration Command (0xCAxxxx/0xCBxxxx)...........................................................................44
Configuration Register ........................................................................................................................45
Application Examples...............................................................................................................................46
Wye-connected source, wye-connected load (Y-Y)............................................................................47
Isolated configuration, 3 VT, 3 CT ............................................................................................47
Non-isolated configuration, 3 voltage-dividers, 3 CTs ..............................................................48
Non-isolated, 3 voltage-dividers, 2 CTs, 1 Shunt......................................................................49
Non-isolated, 3 voltage-dividers, 3 shunts................................................................................50
Delta-connected source, delta-connected load (Δ-Δ).........................................................................51
Isolated configuration, 2 VTs, 2 CT, line current measurement................................................52
Non-isolated, 2 voltage-dividers referenced to line, 2 CTs, line current measurements ..........53
Non-isolated, 1 CT, 2 shunts and 2 voltage-dividers, all referenced to phase .........................56
Wye-connected source, delta-connected load (Y-Δ) ..........................................................................57
Register Access ........................................................................................................................................58
Data Types..........................................................................................................................................58
Register Locations ..............................................................................................................................59
Serial Interfaces ........................................................................................................................................64
UART Interface ...................................................................................................................................64
RS-485 Support ........................................................................................................................64
Device Address Configuration...................................................................................................65
SSI Protocol Description ...........................................................................................................65
SPI Interface .......................................................................................................................................69
I2C Interface ........................................................................................................................................72
Device Address Configuration...................................................................................................72
Bus Characteristics ...................................................................................................................73
Device Addressing ....................................................................................................................73
Write Operations .......................................................................................................................74
Read Operations .......................................................................................................................75
Ordering Information ................................................................................................................................76
Contact Information..................................................................................................................................76
Revision History........................................................................................................................................77
Rev 3
3
MAX78630+PPM Data Sheet
Electrical Specifications
ABSOLUTE MAXIMUM RATINGS
(All voltages with respect to ground.)
Supplies and Ground Pins:
V3P3D, V3P3A
-0.5V to 4.6V
GNDD, GNDA
-0.5V to +0.5V
Analog Input Pins:
-10mA to +10mA
-0.5V to (V3P3 + 0.5V)
AV1, AV2, AV3, AI1, AI2, AI3
Oscillator Pins:
-10mA to +10mA
-0.5V to 3.0V
XIN, XOUT
Digital Pins:
-30mA to +30mA,
-0.5 to (V3P3D + 0.5V)
DIO0 through DIO15; Digital Pins configured as outputs
-10mA to +10mA,
-0.5V to +6V
DIO0 through DIO15, RESET; Digital Pins configured as inputs
Temperatures:
Operating Junction Temperature
Peak, 100ms
+140°C
Continuous
+125°C
Storage Temperature Range
Lead Temperature (soldering, 10s)
Soldering Temperature (reflow)
ESD Stress on All Pins
-65°C to +150°C
+260°C
+300°C
±4kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended External Components
NAME
XTAL
CXS
FROM
TO
FUNCTION
VALUE
20.000
UNITS
MHz
pF
XIN
XOUT
GNDD
20.000MHz
Load capacitor for crystal (exact value
depends on crystal specifications and
parasitic capacitance of board)
XIN
18 ±10%
CXL
XOUT
GNDD
pF
18 ±10%
Recommended Operating Conditions
PARAMETER
CONDITIONS
MIN
3.0
TYP
3.3
MAX
3.6
UNITS
V
3.3V Supply Voltage (V3P3
Operating Temperature
)
Normal operation
-40
+85
°C
4
Rev 3
MAX78630+PPM Data Sheet
Performance Specifications
Note that production tests are performed at room temperature.
Input Logic Levels
PARAMETER
CONDITIONS
MIN
TYP
TYP
MAX
UNITS
Digital High-Level Input Voltage (VIH)
Digital Low-Level Input Voltage (VIL)
2
V
V
0.8
Output Logic Levels
PARAMETER
CONDITIONS
MIN
MAX
UNITS
V3P3
0.4
-
ILOAD = 1mA
V
Digital High-Level Output Voltage
(VOH
)
V3P3
0.6
-
ILOAD = 10mA
V
ILOAD = 1mA
0
0.4
0.5
V
V
Digital Low-Level Output Voltage
(VOL)
ILOAD = 10mA
Supply Current
PARAMETER
CONDITIONS
MIN
MIN
TYP
MAX
UNITS
V3P3D and V3P3A Current
(Compounded)
Normal operation, V3P3
3.3V
=
8.1
10.3
mA
Crystal Oscillator
PARAMETER
CONDITIONS
(Note 1)
TYP
MAX
UNITS
XIN to XOUT Capacitance
3
5
5
pF
XIN
pF
Capacitance to GNDD (Note 1)
XOUT
Note 1: Guaranteed by design; not subject to test.
Internal RC Oscillator
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Nominal Frequency
20.000
MHz
V3P3 = 3.0V, 3.6V;
temperature = -40°C to
+85°C
±1.75
%
Accuracy
±1.5
Rev 3
5
MAX78630+PPM Data Sheet
ADC Converter, V3P3 Referenced
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mV
peak
Usable Input Range (VIN - V3P3
)
-250
+250
VIN = 65Hz, 64kpts FFT,
Blackman-Harris window
dB
kΩ
THD (First 10 Harmonics)
Input Impedance
-85
1.7
VIN = 65Hz
30
90
Temperature Coefficient of Input
Impedance
VIN = 65Hz (Note 1)
Ω/°C
ADC Gain Error vs. %Power Supply
Variation
VIN = 200mVpk, 65Hz;
V3P3 = 3.0V, 3.6V
106 ∆NoutPK 357nV /VIN
100∆V3P3A/3.3
50
ppm/%
mV
Input Offset (VIN - V3P3
)
-10
+10
1 Guaranteed by design; not subject to test.
6
Rev 3
MAX78630+PPM Data Sheet
Timing Specifications
Reset
PARAMETER
Reset Pulse Fall Time
Reset Pulse Width
CONDITIONS
(Note 1)
(Note 1)
MIN
TYP
1
MAX
MAX
UNITS
µs
5
µs
SPI Slave Port
PARAMETER
CONDITIONS
MIN
1
TYP
UNITS
µs
SCK Cycle Time (tSPIcyc
Enable Lead Time (tSPILead
Enable Lag Time (tSPILag
)
)
15
ns
)
0
ns
High
Low
250
250
SCK Pulse Width (tSPIW
)
ns
ns
Ignore if SCK is low
when SSB falls (Note 1)
SSB to First SCK Fall (tSPISCK
)
2
0
Disable Time (tSPIDIS
SCK to Data Out (SDO) (tSPIEV
Data Input Setup Time (SDI) (tSPISU
Data Input Hold Time (SDI) (tSPIH
)
(Note 1)
ns
ns
ns
ns
)
25
)
10
5
)
Note 1: Guaranteed by design, not subject to test.
SSB
tSPILead
tSPIcyc
tSPILag
SCK
SDO
SDI
tSPIW
tSPIEV
tSPIW
tSPIDIS
tSPISCK
MSB OUT
LSB OUT
tSPISU
tSPIH
MSB IN
LSB IN
Rev 3
7
MAX78630+PPM Data Sheet
I2C Slave Port (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bus Idle (Free) Time Between
Transmissions (STOP/START) (tBUF
1500
ns
)
I2C Input Fall Time (tICF
I2C Input Rise Time (tICR
I2C START or Repeated START
Condition Hold Time (tSTH
I2C START or Repeated START
Condition Setup Time (tSTS
I2C Clock High Time (tSCH
I2C Clock Low Time (tSCL
I2C Serial Data Setup Time (tSDS
)
(Note 2)
(Note 2)
20
20
300
300
ns
ns
)
500
600
ns
ns
)
)
)
600
1300
100
10
ns
ns
ns
ns
)
)
I2C Serial Data Hold Time (tSDH
)
I2C Valid Data Time (tVDA):
SCL Low to SDA Output Valid
ACK Signal from SCL Low to
SDA (Out) Low
900
ns
Note 1: Guaranteed by design, not subject to test
Note 2: Dependent on bus capacitance.
tVDA
tICR
tSDS
tSDH
tBUF
SDA
tICF
tSCH tSCL
SCL
tSTS
tICR
tICF
tSTH
tSPS
Repeat
Start
Condition
Stop
Condition
Stop
Start
8
Rev 3
MAX78630+PPM Data Sheet
Pin Configuration
26
25
32
31
30
29
28
27
1
GNDA
V3P3A
24
2
3
23
22
RESET
DIO15
IFC0/DIO8
IFC1/DIO9
AL5/DIO10
AL1/DIO0
MAX78630+PPM
(32-Pin)
AL4/DIO7
4
5
21
20
19
DIO14
(Top)
6
7
8
AL3/ADDR1/DIO6
SGNV3/DIO13
SSB/DIR/SCL/DIO5
SGNV1/DIO11
18
17
SCK/ADDR0/DIO1
SDI/RX/SDAI/DIO2
10
11
9
12
13
14
15
16
Rev 3
9
MAX78630+PPM Data Sheet
Pin
Signal
Function
Pin
Signal
Function
SPI DATA IN / UART RX/
I2C Data In / Digital I/O
SDI/RX/SDAI/
DIO2
1
GNDA
GROUND (Analog)
17
SPI CLOCK IN / I2C/Multi-
Point UART Address/ Digital
I/O
SCK/ADDR0/
DIO1
2
3
DIO15
Digital I/O
18
IFC1/SPI (1=IFC1 pin;
0=SPI) (1)
/ Digital I/O
Sign of AV1 Output / Digital
I/O
IFC0/DIO8
19 SGNV1 / DIO11
4
5
AL4/DIO7
DIO14
Alarm Output / Digital I/O
Digital I/O
20
21
AL1/DIO0
Alarm Output / Digital I/O
Alarm Output / Digital I/O
I2C/UART (1=I2C;0=UART) (1)
AL5/DIO10
AL3/ADDR1/ I2C/ UART Address / Alarm
6
7
22
23
IFC1//DIO9
DIO6
Output / Digital I/O
/ Digital I/O
Sign of AV3 Output /
Digital I/O
RESET
SGNV3 / DIO13
Reset Input
Slave Select (SPI) / RS485
TX-RX / I2C Serial Clock/
Digital I/O
SSB/DIR/SCL/
DIO5
8
9
24
V3P3A
3.3VDC Supply (Analog)
AL2/DIO4
Alarm Output / Digital I/O
25
26
27
AV1
AV2
Voltage Input (Phase 1)
Voltage Input (Phase 2)
Voltage Input (Phase 3)
Sign of AV2 Output /
Digital I/O
10 SGNV2 / DIO12
11
12
V3P3D
XIN
3.3VDC Supply (Digital)
AV3
Reserved for future use. Tie
to V3P3A
Crystal Oscillator Driver Input 28
RES1
Crystal Oscillator Driver
Output
13
XOUT
29
AI1
Current Input (Phase 1)
14
15
GNDD
GNDD
GROUND (Digital)
GROUND (Digital)
30
31
AI2
AI3
Current Input (Phase 2)
Current Input (Phase 3)
SPI DATA OUT/ UART TX/
I2C Data Out / Digital I/O
SDO/TX/
SDAO/DIO3
Reserved for future use. Tie
to V3P3A
16
32
RES2
Notes:
1) IFC0 and IFC1 pins are sampled at power-on to select the communication peripheral as follows:
IFC0 = 0 to select SPI; IFC1 = X (Don’t Care)
IFC0 = 1, IFC1 =0 to select UART/RS485; IFC1 = 1 to select I2C
10
Rev 3
MAX78630+PPM Data Sheet
Package Information
For the latest package outline information and land patterns (footprints), go to
www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0140
LAND PATTERN NO.
90-0012
32 TQFN
T3255+4
Rev 3
11
MAX78630+PPM Data Sheet
On-Chip Resources Overview
The MAX78630+PPM device integrates all the hardware blocks required for accurate AC power and
energy measurement. Included on the device are:
•
•
•
•
•
Oscillator and clock management logic
Power-on reset, watchdog timer, and reset circuitry
High-accuracy Analog Front End (AFE) with trimmed voltage reference and temperature sensor
24-bit measurement processor with RAM and flash memory
UART, SPI and I2C serial communication interfaces and multipurpose Digital I/O
IC Block Diagram
The following is a block diagram of the hardware resources available on the MAX78630+PPM.
MUX
V3P3A
IBIAS
GEN
GNDA
VREF
VBIAS
GEN
ADC
2.5v
REG.
RC
OSC
TEMP
SENSE
V3P3
TRIM
BITS
MUX
CONTROL
XIN
2.5v
FIR
XTAL
OSC
CK
SEL
SSB/DIR/SCL
XOUT
TEMP
LOG.
SPCK/
ADDR0
SPI
SDI/RX/
SDAI
MPY
DIV
SDO/TX/
SDAO
CLOCK
GEN
Measurement
Processor
2
IFC0
IFC1
I C
CK20M
SQ
RT
AL3/ADDR1
UART
24b data bus
16
AL1
AL2
AL4
AL5
program bus
RESET
FLASH
4Kx16
CE DATA
RAM
512x24
INFO.
BLOCK
PROGRAM
MEMORY
V3P3D
DIO! !
…
…
GNDD
DIO! %
12
Rev 3
MAX78630+PPM Data Sheet
Clock Management
The device can be clocked by oscillator circuitry that relies on an external crystal or, as a backup source,
by a trimmed internal RC oscillator. The internal RC oscillator provides an accurate clock source for
UART baud rate generation.
The chip hardware automatically handles the clock sources logic and distributes the clock to the rest of
the device. Upon reset or power-on, the device will utilize the internal RC oscillator circuit for the first 1024
clock cycles, allowing the external crystal adequate time to start-up. The device will then automatically
select the external clock, if available. It will also automatically switch back to the internal oscillator in the
event of a failure with the external oscillator. This condition is also monitored by the processor and
available to the user in the STATUS register.
The MAX78630+PPM external clock circuitry requires a 20.000MHz crystal. The circuitry includes two
18pF ceramic capacitors. The figure below shows the typical connection of the external crystal. This
oscillator is self biasing and therefore an external resistor should NOT be connected across the crystal.
18pF
XIN
20.000MHz
XOUT
18pF
MAX78630+PPM
An external 20MHz system clock signal can also be utilized instead of the crystal. In this case, the
external clock should be connected to the XOUT pin while the XIN pin should be connected to GNDD.
Alternatively, if no external crystal or clock is utilized, the XOUT pin should be connected to GNDD and
the XIN pin left unconnected.
Rev 3
13
MAX78630+PPM Data Sheet
Power-On Reset, Watchdog-Timer, and Reset Circuitry
Power-On RESET (POR)
An on-chip Power-On Reset (POR) block monitors the supply voltage (V3P3D) and initializes the internal
digital circuitry at power-on. Once V3P3D is above the minimum operating threshold, the POR circuit
triggers and initiates a reset sequence. It will also issue a reset to the digital circuitry if the supply voltage
falls below the minimum operating level.
Watchdog Timer (WDT)
A Watchdog Timer (WDT) block detects any software processing errors. The embedded software
periodically refreshes the free-running watchdog timer to prevent it from timing out. If the WDT times out,
it is an indication that software is no longer being executed in the intended sequence; thus, a system
reset is initiated.
External Reset Pin (RESET Pin)
In addition to the internal sources, a reset can be forced by applying a low level to the RESETpin. If the
RESETpin is pulled low, all digital activities in the device stop, except the clock management circuitry and
oscillators, which continue to run. The external reset input is filtered to prevent spurious reset events in
noisy environments. The reset does not occur until RESEThas been held low for at least 1 µs.
Once initiated, the reset mode persists until the RESETis set high and the reset timer times out (4096
clock cycles). At the completion of the reset sequence, the internal reset is released and the processor
begins executing from address 0.
If not used, the RESETpin can be connected either directly or through a pull-up resistor to V3P3D supply.
A simple connection diagram is shown below.
V3P3
V3P3
V3P3D
V3P3D
10KΩ
RESET
RESET
Manual
Reset Switch
1nF
GNDD
GNDD
MAX78630+PPM
MAX78630+PPM
GND
GND
b) Unused RESET Connection Example
a) RESET External Connection Example
14
Rev 3
MAX78630+PPM Data Sheet
Analog Front-End and Conversion
The Analog Front-End (AFE) of the MAX78630+PPM includes an input multiplexer, optional pre-amplifier
gain stage, Delta-Sigma A/D Converter, bias current references, voltage references, temperature sensor,
and several voltage fault comparators.
Analog Inputs
Up to six external sensors can be connected to the MAX78630+PPM. The full-scale signal level that can
be applied to any analog input pin with respect to V3P3A is ±250 mVpk. Considering a sinusoidal AC
waveform, the maximum RMS voltage applied to the inputs pins is:
250푚푉푝푘
rmsMAX =
= 176.78mVrms
√2
Voltage Inputs
Three single-ended input pins (AVA, AVB and AVC) can be connected to external voltage sensors.
The figure below shows example signal conditioning circuits for a voltage input in both isolated (via
voltage transformers) and non-isolated (via a resistor divider circuit) cases. Complete system diagrams
for wye- and a delta-connected three-phase system are shown in the Applications Examples section of
this document. Consult application notes for more information on component selection and PCB design
considerations.
Vx
Vx
MAX78630+PPM
MAX78630+PPM
Phase
Or Line
Voltage
Phase
Voltage
AVx
AVx
V
3P3
V3P3A
V3P3A
V
3P3
Vy or NEUTRAL
NEUTRAL
b) Isolated
a) Non-isolated
Current Inputs
Similarly, three single-ended input pins (AIA, AIB and AIC) can be connected to external current sensors.
The figure on the following page shows example signal conditioning circuits for a current input. One
diagram each is shown for measurement via a resistive shunt (a), a current transformer (b) and a
Rogowski coil (c). The latter requires the user to enable the built-in digital integrator and implement a low
pass filter. Complete system diagrams for wye- and a delta-connected three-phase system are shown in
the Applications Examples section of this document. Consult application notes for more information on
component selection and PCB design considerations.
Rev 3
15
MAX78630+PPM Data Sheet
Vx
a) Isolated (CT)
V3P3
V3P3A
Burden
Phase
Load
AIx
MAX78630+PPM
Vy or NEUTRAL
Vx
b) Non-isolated
V3P3A
AIx
Phase
Load
V
3P3
MAX78630+PPM
Shunt
c) Isolated (Rogowski coil)
NEUTRAL
Vx
V
3P3
V3P3A
Digital
Integrator
Phase
Load
AIx
MAX78630+PPM
Vy or NEUTRAL
16
Rev 3
MAX78630+PPM Data Sheet
Delta-Sigma A/D Converter
A second-order Delta-Sigma converter digitizes the analog inputs. The converted data is then processed
through an FIR filter.
Voltage Reference
The device includes an on-chip precision band-gap voltage reference that incorporates auto-zero
techniques as well as production trims to minimize errors caused by component mismatch and drift. The
voltage reference is digitally compensated over temperature.
Die Temperature Measurement
The device includes an on-chip die temperature sensor used for digital compensation of the voltage
reference. It is also used to report temperature information to the user.
24-Bit Measurement Processor
The MAX78630+PPM integrates a fixed-point 24-bit signal processor that performs all the digital signal
processing necessary for energy measurement, alarm generation, calibration, compensation, etc.
Functionality and operation of the device is determined by the firmware and described in the Functional
Description and Operation section.
Flash and RAM
The MAX78630+PPM includes 8KB of on-chip flash memory. The flash memory primarily contains
program code, but also stores coefficients, calibration data, and configuration settings. The
MAX78630+PPM includes 1.5KB of on-chip RAM which contains the values of input and output registers
and is utilized by the FW for its operations.
Digital I/O Pins
There are a total of sixteen digital input/outputs (DIOs) on the MAX78630+PPM device. Some are
dedicated to serial interface communications and configuration. Others are multi-purpose I/O that can be
used as simple push-pull outputs under user control or routed to special purpose internal signals, such as
alarm signaling.
Communication Interfaces
The MAX78630+PPM includes three communication interface options: UART, SPI, and I2C. Since the I/O
pins are shared, only one mode is supported at a time. Interface configuration and address pins are
sampled at power-on or reset to determine which interface will be active and to set device addresses.
Rev 3
17
MAX78630+PPM Data Sheet
Functional Description and Operation
This section describes the MAX78630+PPM functionality. It includes measurements and relevant
calculations, alarms, auxiliary functions such as calibrations, zero-crossing, etc.
A set of input (write), output (read) and read/write registers are provided to allow access to calculated
data and alarms and to configure the device. The input (write) registers values can be saved into flash
memory through a specific command. The values saved into flash memory will be loaded in these
registers at reset or power-on as defaults.
Measurement Interface
The MAX78630+PPM incorporates a flexible measurement interface for simplified integration into any
system. This section describes the configuration and signal conditioning of the analog inputs.
AFE Input Multiplexer
The MAX78630+PPM samples six (6) external sensors with an effective sample rate of 2.7ksps for each
multiplexer slot. Three analog input pins are defined as single ended voltage inputs and three as single
ended current inputs.
Mux Control
Results
ADC
PRECISION
REFERENCE
AIA
S0
S1
S2
S3
S4
S5
SINC3
DECIMATOR
AVA
∆Σ
Measurement
Processor
AIB
MODULATOR
AVB
CROSS-
POINT
AIC
F
ADC
AVC
Sensor Slot
Analog Input Pins
Input Type
S5
S4
S3
S2
S1
S0
AIA
Current
Voltage
Current
Voltage
Current
Voltage
AVA
AIB
AVB
AIC
AVC
18
Rev 3
MAX78630+PPM Data Sheet
High Pass Filters and Offset Removal
Offset registers for each analog input contain values to be subtracted from the raw ADC outputs for the
purpose of removing inherent system DC offsets from any calculated power and RMS values. These
registers are signed fixed-point numbers with a possible range of -1.0 to 1.0-LSB. They default to 0 and
can be either manually changed by the user or by the integrated offset calibration routines.
Register
V1_OFFS
V2_ OFFS
V3_ OFFS
I1_OFFS
I2_ OFFS
I3_ OFFS
Description
Voltage Input AV1 Offset Calibration
Voltage Input AV2 Offset Calibration
Voltage Input AV3 Offset Calibration
Current Input AI1 Offset Calibration
Current Input AI2 Offset Calibration
Current Input AI3 Offset Calibration
Alternatively, the user can enable an integrated High Pass Filter (HPF) to dynamically update the offset
registers every accumulation interval. During each accumulation interval (or low-rate cycle) the HPF
calculates the median or DC average of each input. Adjustable coefficients determine what portion of the
measured offset is combined with the previous offset value.
The HPF_COEF_I and HPF_COEF_V registers contain signed fixed point numbers with a usable range
of 0 to 1.0-LSB (negative values are not supported). By default, they are initialized to 0.5 (0x400000)
meaning the new offset value will come from ½ of the measured offset and ½ will come from the previous
offset value. Setting them to 1.0 (0x7FFFFF) causes the entire measured offset to be applied to the offset
register enabling lump-sum offset removal. Setting them to zero disables any dynamic update of the
offset registers by the HPF. The HPF coefficients apply to all three channels (current or voltage).
Register
Description
HPF_COEF_I
HPF_COEF_V
HPF coefficient for AIA, AIB and AIC current inputs
HPF coefficient for AVA, AVB and AVC voltage inputs
Using the offset calibration routine will automatically set the filter coefficients to zero to disable the HPF.
Enabling the software integrators for Rogowski Coil current sensors
Rogowski Coil current sensors produce an output signal that is proportional to the derivative of current
over time. Therefore, an integration filter is required to reconstruct the original current signal. The
MAX78630+PPM provides such integrators and a configuration bit for each of the three current inputs to
enable this feature.
Register[Bit]
Description
Config[EN_ROGA]
Config[EN_ROGB]
Config[EN_ROGC]
Enables the software integrator for input AIA
Enables the software integrator for input AIB
Enables the software integrator for input AIC
Enabling the software integrator will automatically disable the HPF and offset correction.
Gain Correction
The system (sensors) and the MAX78630+PPM device inherently have gain errors that can be corrected
by using the gain registers. These registers can be directly accessed and modified by an external host
processor or automatically updated by an integrated self calibration routine.
Rev 3
19
MAX78630+PPM Data Sheet
Input gain registers are signed fixed-point numbers with the binary point to the left of bit 21. They are set
to 1.0 by default and have a usable range of 0 to 4.0-LSB (negative values are not supported). The gain
equation for each input X can be described as Y=gain*X.
Register
V1_GAIN
V2_GAIN
V3_GAIN
I1_GAIN
I2_GAIN
I3_GAIN
Description
Voltage Input AV1 Gain Calibration.
Voltage Input AV2 Gain Calibration
Voltage Input AV3 Gain Calibration.
Current Input AI1 Gain Calibration
Current Input AI2 Gain Calibration
Current Input AI3 Gain Calibration
Die Temperature Compensation
The MAX78630+PPM has an on-chip temperature sensor that can be used by the measurement
processor for monitoring the voltage reference error and made available to the user in the TEMPC
register.
Setting the Temperature Compensation (TC) bit in the Command Register allows the firmware to further
adjust the system gain based on measured die temperature. Die temperature offset is typically calibrated
by the user during the calibration stage. Die temperature gain is set to a factory default value for most
applications, but can be adjusted by the user.
Register
T_OFFS
T_GAIN
Description
Die Temperature Offset Calibration.
Die Temperature Slope Calibration. Set by factory.
Voltage Reference Gain Adjustment
The on-chip precision bandgap voltage reference incorporates auto-zero techniques as well as production
trims to maximize measurement accuracy. It can be assumed that the part is trimmed at 22°C to produce
a uniform voltage reference gain at that temperature. The voltage reference is digitally compensated over
changes in measured die temperature using a quadratic equation.
Phase Compensation
Phase compensation registers are used to compensate for phase errors or time delays between the
voltage input source and respective current source that are introduced by the off-chip sensor circuit. The
user configurable registers are signed fixed point numbers with the binary point to the left of bit 21. Values
are in units of high rate (2.7kHz) sample delays so each integer unit of delay is 370µs with a total possible
delay of ±4 samples (approximately ±32° at 60Hz).
Register
Description
PHASECOMP1
PHASECOMP2
PHASECOMP3
Phase (delay) compensation for input current AI1
Phase (delay) compensation for input current AI2
Phase (delay) compensation for input current AI3
20
Rev 3
MAX78630+PPM Data Sheet
Voltage Input Configuration
The MAX78630+PPM supports multiple analog input configurations for determining the voltages in a
three-phase system. The CONFIG register is used to instruct the MAX78630+PPM how to compute them.
CONFIG Bits
Name
Function
22
21
20
5
INV_AV3
INV_AV2
INV_AV1
VDELTA
VPHASE
Invert voltage samples AV3
Invert voltage samples AV2
Invert voltage samples AV1
Compute Line-to-Line voltages
4:3
Missing sensor on voltage input
00: none missing
01: AV1
10: AV2
11: AV3
The VDELTA bit must be set whenever the voltage sensors measure phase voltages (line-to-neutral), but
the load is connected in a Delta configuration. The MAX78630+PPM then computes line-to-line voltages
from the inputs and uses those for all other computations.
The VPHASE setting determines how many voltage sensors are present, and in which phases. If three
sensors are used, these bits should be set to zero. If two sensors are used, settings 01, 10 and 11
indicate the phase with no voltage sensor. This phase will then be computed such that VA+VB+VC
equals to zero. Note that using two voltage sensors is not recommended in Wye-connected systems, as
the above equation may not necessarily be true.
The INV_AVx bits instruct the MAX78630+PPM to invert every sample of the corresponding voltage input,
before performing any other computations based on the VDELTA and VPHASE settings.
VDELTA
VPHASE
Voltage equations
0
0
00
01
VA, VB and VC measured on AV1, AV2 and AV3 inputs
VB and VC measured on AV2 and AV3
VA = VC - VB
0
0
1
10
11
00
VA and VC measured on AV1 and AV3
VB = VA - VC
VA and VB measured on AV1 and AV2
VC = VB - VA
Compute Line-to-Line voltages at high-rate
VA ⇐ VC – VA = VCA
VB ⇐ VA – VB = VAB
VC ⇐ VB – VC = VBC
1
01
10
11
Invalid settings
Note: INV_AVx settings are applied before these computations
The Applications Examples section provides the required settings for the different configurations.
Rev 3
21
MAX78630+PPM Data Sheet
Voltage Input Flowchart
The figure below illustrates the computational flowchart for VA, VB, and VC. The values for the voltage
input configuration register can be saved in flash memory and automatically restored at power-on or
reset.
HPF_COEF_V
CONFIG:
INV_AVx , VDELTA , VPHASE
PHASECOMP1
V1_OFFS
V1_GAIN
V2_GAIN
Delay
Compensation
HPF
HPF
X
X
VA
VB
AV1
AV2
PHASECOMP2
V2_OFFS
Compute Line-to-
Line voltages
Compute “missing”
Voltage
Delay
Compensation
PHASECOMP3
V3_OFFS
V3_GAIN
Delay
Compensation
HPF
X
VC
AV3
22
Rev 3
MAX78630+PPM Data Sheet
Current Input Configuration
The MAX78630+PPM supports multiple analog input configurations for determining the currents in a
three-phase system. The CONFIG register is used to instruct the MAX78630+PPM how to compute them.
CONFIG Bits
Name
Function
2
INEUTRAL Configuration uses a current sensor in the Neutral conductor.
This sensor replaces the missing sensor (see IPHASE setting)
1:0
IPHASE
Missing sensor on current input
00: none missing
01: AI1
10: AI2
11: AI3
The IPHASE setting determines how many line current sensors are present, and for which phases. If
three sensors are used, these bits should be set to zero. If two sensors are used, settings 01, 10 and 11
indicate the phase without a line current sensor. The current for this phase will then be computed
according to the INEUTRAL and VDELTA settings. If VDELTA is cleared and IN can be assumed to be
zero, the current is computed such that IA+IB+IC = 0. If VDELTA is set, the current in this phase is the
difference between the two other currents (INEUTRAL must be cleared in these two cases).
When the INEUTRAL bit is set, a sensor in the neutral conductor replaces one of the three line current
sensors. IN is directly measured from a sensor placed in the neutral conductor and the MAX78630+PPM
calculates the current for the input with no line current sensor, such that IA+IB+IC = IN (IPHASE cannot
be 00).
INEUTRAL
IPHASE
00
Current equations
0
0
IA, IB and IC measured on AI1, AI2 and AI3 inputs
01
IB and IC measured on AI2 and AI3
if VDELTA = 0 ⇨ IA = -(IB + IC)
if VDELTA = 1 ⇨ IA = IB - IC
0
0
10
11
IA and IC measured on AI1 and AI3
if VDELTA = 0 ⇨ IB = -(IC + IA)
if VDELTA = 1 ⇨ IB = IC – IA
IA and IB measured on AI1 and AI2
if VDELTA = 0 ⇨ IC = -(IA + IB)
if VDELTA = 1 ⇨ IC = IA - IB
1
1
00
01
Invalid setting
IB and IC measured on AI2 and AI3
IN measured on AI1
IA = IN - (IB + IC)
1
1
10
11
IA and IC measured on AI1 and AI3
IN measured on AI2
IB = IN - (IC + IA)
IA and IB measured on AI1 and AI2
IN measured on AI3
IC = IN - (IA + IB)
The Applications Examples section provides the required settings for different configurations.
Rev 3
23
MAX78630+PPM Data Sheet
Pre-amp
By default, the full-scale signal that can be applied to the current inputs is V3P3A ±250mVpk
(176.78mVRMS). This setting provides the widest dynamic range and is recommended for most
applications.
For applications requiring a much lower value shunt resistor, an optional pre-amplifier with an 8x gain is
included for the current inputs. The maximum input signal that can be applied to the current inputs in this
case is ±31.25mVpk.
The CONFIG register is used to enable the Pre-amp.
CONFIG Bits
Name
Function
9
EN_PREAMPC Enables the Pre-amp on input AIC
EN_PREAMPB Enables the Pre-amp on input AIB
EN_PREAMPA Enables the Pre-amp on input AIA
11
13
The gain is set by a ratio of internal resistors with one of the resistors in series from the input pad to the
pre-amp itself. As such, the device must only be directly connected to a shunt with minimal resistance
when using the pre-amp.
Current Input Flowchart
The figure below illustrates the computational flowchart for IA, IB and IC. The values for current input
configuration register can be saved in flash memory and automatically restored at power-on or reset.
CONFIG:
EN_ROGx
HPF_COEF_I
I1_OFFS
CONFIG:
INEUTRAL , IPHASE,VDELTA
I1_GAIN
HPF
S/W Integrator
X
X
IA
IB
AI1
AI2
I2_OFFS
I2_GAIN
I3_GAIN
Compute “missing”
Current
Use Sensor in
Neutral Conductor
HPF
S/W Integrator
I3_OFFS
HPF
S/W Integrator
X
IC
AI3
24
Rev 3
MAX78630+PPM Data Sheet
Data Refresh Rates
Instantaneous voltage and current measurement results are updated at the sample rate of 2.7kS/s and
are generally not useful unless accessed with a high speed interface such as SPI. The CYCLE register is
a 24-bit counter that increments every high-rate sample update and resets when low rate results are
updated.
Low rate results, updated at a user configurable rate (also referred to as accumulation interval), are
typically used and more suitable for most applications. The FRAME register is a counter that increments
every accumulation interval. A data ready indicator in the STATUS register indicates when new data is
available. Optionally, this indicator can be made available as a signal on one of the five Alarm output pins.
The high rate samples in one accumulation interval are averaged to produce a low-rate result, increasing
their accuracy and repeatability. Low rate results include RMS voltages and currents, frequency, power,
energy, and power factor. The accumulation interval can be based on a fixed number of ADC samples or
locked to the incoming line voltage cycles.
If Line Lock is disabled, the accumulation interval defaults to a fixed time interval defined by the number
of samples defined in the SAMPLES register (default of 540 samples or 0.2 seconds).
When the Line-Lock bit in the Command Register is set, and a valid AC voltage signal is present, the
actual accumulation interval is stretched to the next positive zero crossing of the reference line voltage
after the defined number of samples has been reached. If there is not a valid AC signal present and line
lock is enabled, there is a 100 sample timeout implemented that would limit the accumulation interval to
SAMPLES+100.
The DIVISOR register records the actual duration (number of high rate samples) of the last low rate
interval whether or not Line-Lock is enabled.
Zero-crossing detection and line frequency for the purpose of determining the accumulation interval are
derived from a composite signal 푉푍퐶 = 푉퐴 − 0.5 ∙ 푉퐵 − 0.25 ∙ 푉ꢀ. For a three-phase system, this signal
oscillates at the line frequency as long as any of the three voltages is present.
Scaling Registers and Result Formats
All voltage, current and power data is reported in binary full-scale units with a value range of -1.0 to 1.0
less one LSB (S.23 format). For voltages and currents, all full-scale register readings correspond to the
max analog input of 250mVpk (or 31.25mVpk with 8x gain from the pre-amp). As an example, if 230V-
peak at the input to the voltage-divider gives 250mV-peak at the chip input, one would get a full-scale
register reading of 1.0-LSB for instantaneous voltage. Similarly, if 30A at the sensor input provides
250mV to the chip input, a full-scale register value of 1.0-1LSB for instantaneous current would
correspond to 30A. Full-scale power corresponds to the result of full-scale current and voltage so in this
example, full-scale watts is 230 x 30 or 6900 watts.
Power Factors are reported as binary fixed-point number, with a range of -2 to +2 less one LSB (format
S.22). Frequency data is reported as binary fixed-point number, with a range of 0 to +256Hz less one LSB
(format S.16). Temperature data has a fixed scaling with a range of -16384°C to +16384°C less one LSB
(format S.10). Energy data scaling is described in a different section of this document.
Nonvolatile registers (IFSCALE and VFSCALE) are provided for storing the real-world current and voltage
levels that apply to the full-scale register readings for any given board design. Any host application can
then format the measurement results to any data format as needed. The usage of these nonvolatile
scratchpad registers is user defined and their content has no effect on the internal operations of the
device.
Rev 3
25
MAX78630+PPM Data Sheet
Calibration
The MAX78630+PPM provides integrated calibration routines to modify gain and offset coefficients. The
user can setup and initiate a calibration routine through the Command Register. On a successful
calibration, the command bits are cleared in the Command Register, leaving only the system setup bits.
In case of a failed calibration, the bit in the Command Register corresponding to the failed calibration is
left set. When in calibration mode, the line-lock bit should be set for best results.
The calibration routines will write the new coefficients to the relevant registers. The user can then save
the new coefficients into flash memory as defaults using the flash access command in the Command
Register.
See the Command Register section for more information on using commands.
Voltage and Current Gain Calibration
In order to calibrate the gain parameters for voltage and current channels, a reference AC signal must be
applied to the channel to be calibrated. The RMS value corresponding to the applied reference signal
must be entered in the relevant target register (V_TARGET, I_TARGET). Considering calibration is done
with low rate RMS results, the value of the target register should never be set to a value above 70.7% of
full-scale.
Initially, the value of the gain is set to unity for the selected channels. RMS values are then calculated on
all inputs and averaged over the number of measurement cycles set by the CALCYCS register. The new
gain is calculated by dividing the appropriate Target register value by the averaged measured value. The
new gain is then written to the select Gain registers unless an error occurred.
Note that there is only one V_TARGET register for voltages. It is possible to calibrate multiple or all
voltage channels simultaneously, if and only if the same RMS voltage value is applied to each
corresponding input. Analogous considerations apply to the current channels, which are calibrated via the
I_TARGET register.
Offset Calibration
To calibrate offset, all signals should be removed from all analog inputs although it is possible to do the
calibration in the presence of AC signals. In the command, the user also specifies which channel(s) to
calibrate. Target registers are not used for Offset calibration.
During the calibration process, each input is accumulated over the entire calibration interval as specified
by the CALCYCS register. The result is divided by the total number of samples and written to the
appropriate offset register, if selected in the calibration command. Using the Offset Calibration command
will set the respective HPF coefficients to zero thereby fixing the offset registers to their calibrated values.
Die Temperature Calibration
To re-calibrate the on-chip temperature sensor offset, the user must first write the known chip
temperature to the T_TARGET register. Next, the user initiates the Temperature Calibration Command in
the Command Register. This will update the T_OFFS offset parameter with a new offset based on the
known temperature supplied by the user. Note that temperature calibration cannot be combined with any
gain or offset calibrations in the same command.
The T_GAIN gain register is set by the factory and not updated with this routine.
26
Rev 3
MAX78630+PPM Data Sheet
Voltage Channel Measurements
Instantaneous voltage measurements are updated every sample, while RMS voltages are updated every
accumulation interval (n samples).
Register
Description
Time Scale
VA
VB
VC
Instantaneous Voltage @ time t
1 sample
VA_RMS
VB_RMS
VC_RMS
RMS Voltage of last interval
1 interval
VT_RMS
Average of VA_RMS, VB_RMS, VC_RMS
Note that the VDELTA and VPHASE settings in the CONFIG register affect how the instantaneous and
averaged values are computed as described in the Voltage Input Configuration section.
Additionally, an AC voltage frequency measurement is also available and is updated every 64 line cycles.
Register
Description
Time Scale
64 voltage
line cycles
FREQ
AC Voltage Frequency
RMS Voltage
The MAX78630+PPM reports true RMS measurements for each input. An RMS value is obtained by
performing the sum of the squares of instantaneous values over a time interval (accumulation interval)
and then performing a square root of the result after dividing by the number of samples in the interval.
Instantaneous
Voltage (Vx)
N-1
Vx2_SUM
Vx2
X
∑
N
Vx_RMS
n=0
Line Frequency
This output is a measurement of the fundamental frequency of the AC voltage source. It is derived from a
composite signal and therefore applies to all three phases (it is a single reading per device).
Rev 3
27
MAX78630+PPM Data Sheet
Current Channel Measurements
Instantaneous current measurements are updated every sample, while peak currents and RMS currents
are updated every accumulation interval (n samples).
Register
Description
Time Scale
IA
IB
IC
Instantaneous Current
1 sample
IA_PEAK
IB_PEAK
IC_PEAK
Peak Current
IA_RMS
IB_RMS
IC_RMS
1 interval
RMS Current
IT_RMS
Average of IA_RMS, IB_RMS, IC_RMS
Note that the INEUTRAL and IPHASE settings in the CONFIG register affect how the instantaneous and
averaged values are computed as described in the Current Input Configuration section.
Peak Current
This output is a capture of the largest magnitude instantaneous current load sample.
Instantaneous
Current (Ix)
ABS
MAX
maximum
Ix_PEAK
RMS Current
The MAX78630+PPM reports true RMS measurements for current inputs. The RMS current is obtained
by performing the sum of the squares of the instantaneous voltage samples over the accumulation
interval and then performing a square root of the result after dividing by the number of samples in the
interval.
An optional “RMS offset” for the current channels can be adjusted to reduce errors due to noise or system
offsets (crosstalk) exhibited at low input amplitudes. Full-scale values in the IxRMS_OFFS registers are
squared and subtracted from the accumulated/divided squares. If the resulting RMS value is negative,
zero is used.
IxRMS_OFF2
Instantaneous
Current
N-1
Ix2_SUM
Ix2
Ix
If |x|< 0
y = 0
X
x
y
Ix_RMS
−
∑
N
n=0
28
Rev 3
MAX78630+PPM Data Sheet
Current and Voltage Imbalance
Imbalance of a three-phase system is typically defined as the percentage of the maximum deviation of
any of the phases from the average of the phases.
Voltage imbalance is obtained from Vx_RMS and VT_RMS as
|
| |
| |
|
max{ 푉퐴푅푀푆 − 푉푇푅푀푆 , 푉퐵푅푀푆 − 푉푇푅푀푆 , 푉ꢀ푅푀푆 − 푉푇푅푀푆 }
푉퐼푀퐵퐴퐿% =
∙ 100
푉푇푅푀푆
Current imbalance is obtained from Ix_RMS and IT_RMS as
|
| |
| |
|
max{ 퐼퐴푅푀푆 − 퐼푇푅푀푆 , 퐼퐵푅푀푆 − 퐼푇푅푀푆 , 퐼ꢀ푅푀푆 − 퐼푇푅푀푆 }
퐼퐼푀퐵퐴퐿% =
∙ 100
퐼푇푅푀푆
The MAX78630+PPM monitors the deviation of any phase from the average value. It generates an alarm
if the deviation exceeds user programmable threshold; V_IMB_MAX for voltages and I_IMB_MAX for
currents.
The thresholds are expressed as binary full-scale units with a value range of 0.0 to 1.0 less one LSB
(S.23 format). 1.0 thus corresponds to 100% imbalance.
Example: generate an alarm if voltage imbalance exceeds 1.5%.
1.5
V
IMB
= int �
∙ 223ꢂ = 125,829 = 0x1EB85
ꢁAX
100
Rev 3
29
MAX78630+PPM Data Sheet
Power Calculations
This section describes the detailed flow of power calculations in the MAX78630+PPM. The table below
lists the available measurement results for AC power.
Register
Description
Time Scale
WATT_A
WATT_B
WATT_C
Average Active Power (P)
VAR_A
VAR_B
VAR_C
Average Reactive Power (Q)
Apparent Power (S)
Power Factor
VA_A
VA_B
VA_C
1 interval
PF_A
PF_B
PF_C
WATT_T
VAR_T
VA_T
Average of WATT_A, WATT_B, WATT_C
Average of VAR_A, VAR_B, VAR_C
Average of VA_A, VA_B, VA_C
PF_T
Total power factor: Equal to WATT_T / VA_T
Note that the voltage and current configuration settings in the CONFIG register affect the physical
meaning of the computed power results. The Applications Examples section provides further details on
these results.
Active Power (P)
The instantaneous power results (PA, PB, PC) are obtained by multiplying aligned instantaneous voltage
and current samples. The sum of these results are then averaged over N samples (accumulation time) to
compute the average active power (WATT_A, WATT_B, WATT_C).
The value in the Px_OFFS register is the “Power Offset” for the power calculations. Full-scale values in
the Px_OFFS register are subtracted from the magnitude of the averaged active power. If the resulting
active power value results in a sign change, zero watts are reported
SIGN
Instantaneous
Values
Px_
SUM
N-1
If |x|< 0
y = 0
Vx
Ix
x
y
X
WATT_x
N
X
−
ABS
Px
∑
n=0
Px_OFFS
.
30
Rev 2
MAX78630+PPM Data Sheet
Reactive Power (Q)
Instantaneous reactive power results are calculated by multiplying the instantaneous samples of current
and the instantaneous quadrature voltage. The sum of these results are then averaged over N samples
(accumulation time) to compute the average reactive power (VAR_A, VAR_B, VAR_C). A reactive power
offset (Qx_OFFS) is also provided for each channel.
SIGN
Instantaneous
Values
Qx_
SUM
N-1
VQx
If |x|< 0
y = 0
Quadrature
Delay
Vx
Ix
x
y
X
VAR_x
N
X
−
Qx
∑
n=0
ABS
Qx_OFFS
Apparent Power (S)
The apparent power, also referred as Volt-Amps, is the product of low rate RMS voltage and current
results. Offsets applied to RMS current will affect apparent power results.
Ix_RMS
VA_x
X
Vx_RMS
Power Factor (PF)
The power factor registers capture the ratio of active power to apparent power for the most recent
accumulation interval. The sign of power factor is determined by the sign of active power.
WATT_x
PF_x =
VA_x
Totals of active power, reactive power, apparent power and power factor
The total power results in a three-phase system depend on how the AC source, the load and the sensors
are configured. As an example, in Wye connected systems, the totals are computed as the sum of all
three per-phase results. In many Delta configurations, the total power is the sum of two “per-phase”
results only, and the third per-phase result must be ignored. The MAX78630+PPM requires a setting to
indicate how the totals are to be computed. The PPHASE bits in the CONFIG register serve this purpose.
CONFIG Bits
Name
Function
7:6
PPHASE
Ignore phase for total power computations
00: none
01: phase A
10: phase B
11: phase C
Rev 3
31
MAX78630+PPM Data Sheet
When PPHASE is not 00, the MAX78630 will compute the totals of two phases only, as is typically done
when only line currents are available in a Delta-connected load. In such cases, the total apparent power
3
√
ꢃ
is correctly scaled by a factor of
. In order to prevent overflows, all totals are computed as averages
2
and must be multiplied by two by the host.
When PPHASE is equal to 00, all totals are computed as averages and must be multiplied by three by the
host.
Total Apparent
Total Active Power
Total Reactive Power
Power
PPHASE
WATT_T =
VAR_T =
VA_T =
(
)
(
)
(
)
WATT_A + WATT_B + WATT_C
VAR_A + VAR_B + VAR_C
VA_A + VA_B + VA_C
00
01
10
11
3
3
3
(
(
)
)
(
(
)
)
WATT_B + WATT_C
VAR_B + VAR_C
(
(
)
)
3
VA_B + VA_C
√
∙
∙
∙
2
2
2
2
WATT_A + WATT_C
2
VAR_A + VAR_C
2
3
√
VA_A + VA_C
2
2
(
)
(
)
WATT_A + WATT_B
VAR_A + VAR_B
(
)
3
VA_A + VA_B
√
2
2
2
2
The total power factor is computed as
WATT_T
VA_T
PF_T =
Specific examples and the required settings are further described in the Applications Examples section.
32
Rev 2
MAX78630+PPM Data Sheet
Fundamental and Harmonic Calculations
The MAX78630+PPM includes the ability to separate low rate voltage, current, active power, and reactive
power measurement results into fundamental and total harmonic components. These outputs can also be
used to track individual harmonics as well as the total value excluding the selected harmonic.
Register
Description
Time Scale
VFUND_A
VFUND_B
VFUND_C
Voltage content at specified harmonic
IFUND_A
IFUND_B
IFUND_C
Current content at specified harmonic
PFUND_A
PFUND_B
PFUND_C
Active Power content at specified harmonic
Reactive Power content at specified harmonic
Voltage content not at specified harmonic
Current content not at specified harmonic
Active Power content not at specified harmonic
Reactive Power content not at specified harmonic
QFUND_A
QFUND_B
QFUND_C
1 interval
VHARM_A
VHARM_B
VHARM_C
IHARM_A
IHARM_B
IHARM_C
PHARM_A
PHARM_B
PHARM_C
QHARM_A
QHARM_B
QHARM_C
The HARM register is used to select the single harmonic to extract. This input register is set by default to
0x000001 selecting the first harmonic (also known as the fundamental frequency). This setting provides
the user with fundamental result and the total harmonic distortion (THD) of the harmonics
By setting the value in the HARM register to a higher harmonic, the fundamental result registers will
contain measurement results of the selected harmonic. The harmonics result registers will report the
measurement of the remaining harmonics. For any given accumulation interval, the magnitude of
measurement result IA_RMS would be the sum of IFUND_A and IHARM_A.
Rev 3
33
MAX78630+PPM Data Sheet
Energy Calculations
Energy calculations are included in the MAX78630+PPM to minimize the traffic on the host interface and
simplify system design. Low rate power measurement results are multiplied by the number of samples
(register DIVISOR) to calculate the energy in the last accumulation interval. Energy results are summed
together until a user defined “bucket size” is reached. For every bucket of energy is reached, the value in
the energy counter register is incremented by one.
All energy counter registers are low rate 24-bit output registers that contain values calculated over
multiple accumulation intervals. Both import (positive) and export (negative) results are provided for active
and reactive energy.
Register
Description
WHA_POS
WHB_POS
Positive Active Energy Counter, per phase
WHC_POS
WHA_NEG
WHB_NEG
Negative Active Energy Counter, per phase
Positive Reactive Energy Counter, per phase
Negative Reactive Energy Counter, per phase
WHC_NEG
VARHA_POS
VARHB_POS
VARHC_POS
VARHA_NEG
VARHB_NEG
VARHC_NEG
Energy results are cleared upon any power down or reset and can be manually cleared by the external
host using the REN bit in the COMMAND register. The CYCLES register can be used to detect device
resets (loss of energy data) or to track time between energy reads.
34
Rev 2
MAX78630+PPM Data Sheet
Bucket Size for Energy Counters
The BUCKET register allows the user to define the unit of measure for the energy counter registers. It is
an unsigned 48-bit fixed-point number with 24 bits for the integer part and 24 bits for the fractional part.
High word
Low word
Bit Position
Value
23
223 222
22
…
…
2
232
1
21
0
20
.
23
2-1
22
2-2
21
2-3
…
…
1
2-23
0
2-24
The units should be set large enough to keep the accumulators and counters from overflowing too
quickly. To increment the energy counters in watt-hours for example, the value in BUCKET should be
equal to the number of seconds in an hour (3600) multiplied by the Sample Rate (2.7kS/s) and divided by
Full-Scale Watts (VSCALE x ISCALE).
Watt-hours (Wh) Bucket = (3600s x 2.7kS/s) / (VSCALE x ISCALE)
Full-Scale Watts is defined by the sensors being used (see the Scaling Registers section). As an
example, if the voltage sources are 400Vpk at full scale (VSCALE) and the currents are 30Apk at full
scale (ISCALE), then full-scale watts would be 12000 (VSCALE x ISCALE). The bucket value can be
saved to flash memory as the register default.
Examples:
For the ISCALE and VSCALE values given above, a:
1. Watt-hour bucket equals to 3600*2700/ (400*30) = 810. The hexadecimal value that must be
written to the BUCKET register is, after shifting 24 bits (multiplying by 223) to the left to align with
the integer part: BUCKET = 0x00032A.000000
2. kilo-Watt-hour bucket equals to 3600*2700/ (400*30/1000) = 810000. The hexadecimal value that
must be written to the BUCKET register is, after shifting 24 bits (multiplying by 224) to the left to
align with the integer part: BUCKET = 0x0C5C10.000000
Rev 3
35
MAX78630+PPM Data Sheet
Min/Max Tracking
The MAX78630+PPM provides a set of output registers for tracking the minimum and/or maximum values
of up to eight (8) different low rate measurement results over multiple accumulation intervals . The user
can select which measurements to track through an address table. The values in MM_ADDR# are word
addresses for all host interfaces and can be saved to flash memory by the user as the register defaults.
Results are stored in RAM and cleared upon any power down or reset and can be cleared by the host
using the RTRK bit in the COMMAND register.
Register
MM_ADDR0
MM_ADDR1
MM_ADDR2
MM_ADDR3
MM_ADDR4
*MM_ADDR5
*MM_ADDR6
*MM_ADDR7
MIN0
Description
Time Scale
Word addresses to track minimum
and maximum values. A value of zero
disables tracking for that address slot.
–
MIN1
MIN2
MIN3
Minimum low rate value at
MM_ADDR#.
multiple
intervals
MIN4
*MIN5
*MIN6
*MIN7
MAX0
MAX1
MAX2
MAX3
Maximum low rate value at
MM_ADDR#.
multiple
intervals
MAX4
*MAX5
*MAX6
*MAX7
*NOTE: When using Rogowski coils, restriction on the use of MIN/MAX functionality apply. For each
current input with a Rogowski coil sensor, one of the MIN/MAX registers 5, 6 and 7 cannot be used to
track minima and maxima. See the Register Locations section for more details.
maximum
MAX#
MAX
RAM[#]
MM_ADDR#
CONTROL
minimum
MIN#
MIN
36
Rev 2
MAX78630+PPM Data Sheet
Voltage Sag Detection
The MAX78630+PPM implements a voltage sag detection function for each of the three phases. When a
phase voltage drops below a programmable threshold, a corresponding alarm is generated.
The firmware computes the following indicator to detect whether the voltage falls below the threshold.
ꢈꢄꢅ퐺_ꢉ푁ꢊꢋ1
2
푉
ꢄꢅ퐺푋
=
ꢆ
(푣푋푛 − 푉푆퐴ꢇ_퐿퐼푀2)
푛= 0
where
•
•
VSAG_LIM is the user-settable RMS value of the voltage threshold
VSAG_INT is the user-settable number of high-rate samples over which the indicators should be
computed. For optimal performance, this should be set so that the resulting interval is an integer
multiple of the line period (at least one half line period)
•
X is the phase (A,B,C)
If VSAGX becomes negative, the firmware sets the VX_SAG bit for the corresponding phase in the
STATUS register. If VX_SAG is enabled in a MASK register, the corresponding AL pin will also be
asserted low. If the VX_SAG bit is set in the STICKY register, then the alarm bit will remain set and any
unmasked AL pin will remain low until the VX_SAG alarm is cleared via the STATUS_CLEAR register or
the MAX78630+PPM is reset. If the VX_SAG bit is cleared in the STICKY register, then the alarm bit will
be automatically cleared and any unmasked AL pin set high as soon as the indicator VSAGX is greater than
the programmable threshold.
The sag detection can be used to monitor or record the quality of the power line or utilize the sag alarm
pin to notify external devices (for example a host microprocessor) of a pending power-down. The external
device can then enter a power-down mode (for example saving data or recording the event) before a
Power outage. The figure below shows a SAG event and how the alarm bit is set by the firmware (in the
case of the STICKY register bit cleared).
VSAG_LIM
VSAG_INT
VX_SAG status/alarm bit
Example:
Set the detection interval to one-half of a line cycle (60Hz line frequency).
푇
푙2푖푛푒
푓
2700
푠푎ꢍꢎ푙푒
푉푆퐴ꢇ_퐼ꢌ푇 =
=
=
= 22
ꢏ
푓
1
2푓
2 ∙ 60
푙푖푛푒
푠푎ꢍꢎ푙푒
Rev 3
37
MAX78630+PPM Data Sheet
Voltage Sign Outputs
The MAX78630+PPM can optionally output the sign of the phase or line voltages VA, VB, VC on
dedicated DIO pins. This functionality is enabled individually for each phase by setting the VSGNA,
VSGNB and VSGNC bits in the CONFIG register. If a VSGNx bit is set, the sign of the voltage Vx drives
the state of the corresponding SGNVx digital output pin. The time delay of the sign output versus the sign
of the actual voltage is approximately 1.20ms. Resetting a VSGNx bit disables this functionality and
makes the corresponding DIO pin available as a general purpose input/output.
Alarm Monitoring
Low rate alarm conditions are determined every accumulation interval. If results for Die Temperature, AC
Frequency, or RMS Voltage exceeds or drops below user configurable thresholds, then a respective
alarm bit in the STATUS register is set. For RMS Current results, a maximum threshold is provided for
detecting over current conditions with the load. For Power Factor results, a minimum threshold is
provided.
Register
T_MAX
Description
Threshold value which Temperature must exceed to trigger alarm.
Threshold value which Temperature must drop below to trigger alarm.
Threshold value which Frequency must exceed to trigger alarm.
Threshold value which Frequency must drop below to trigger alarm.
Threshold value which RMS Voltage must exceed to trigger alarm.
Threshold value which RMS Voltage must drop below to trigger alarm.
Threshold value which RMS current must exceed to trigger alarm.
Threshold value which power factor must drop below to trigger alarm.
T_MIN
F_MAX
F_MIN
VRMS_MAX
VRMS_MIN
IRMS_MAX
PF_MIN
Imbalance of the three voltages and three currents is monitored and reported via dedicated alarm bits if
they exceed respective maximum threshold V_IMB_MAX and I_IMB_MAX. Refer to the Current and
Voltage Imbalance section or details.
Register
Description
Percentage Threshold value which Voltage Imbalance must exceed to
trigger alarm.
V_IMB_MAX
Percentage Threshold value which Current Imbalance must exceed to
trigger alarm.
I_IMB_MAX
The STATUS register also provides Sag voltage alarms. A configurable RMS voltage threshold and
selectable Interval is provided as described below and in the Voltage Sag Detection section.
Register
Description
VSAG_LIM
Threshold value (in RMS) which voltage must go below to trigger a Sag alarm.
Interval (in samples) over which the voltage must be below the threshold. Should
be set in increments of half cycles (i.e. 22 samples per half cycle at 60Hz).
VSAG_INT
38
Rev 2
MAX78630+PPM Data Sheet
Status Registers
The STATUS register is used to monitor the status of the device and user configurable alarms. All other
registers mentioned in this section share the same bit descriptions.
The STICKY register determines which alarm/status bits are sticky and which track the current status of
the condition. Each alarm bit defined as sticky will (once triggered) hold its alarm status until the user
clears it using the STATUS_RESET register. Any sticky bit not set will allow the respective status bit to
clear when the condition clears.
The STATUS_SET and the STATUS_RESET registers allow the user to force status bits on or off
respectively without fear of affecting unintended bits. A bit set in the STATUS_SET register will set the
respective bit in the STATUS register and a bit set in the STATUS_RESET register will clear it.
STATUS_SET and STATUS_RESET are both cleared after the status bit is set or reset.
The following table lists the bit mapping for the all status related registers.
Bit
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Name
Stick-able? Description
New low rate results (data) ready
DRDY
Always
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
OV_FREQ
UN_FREQ
OV_TEMP
UN_TEMP
OV_VRMSC
UN_VRMSC
OV_VRMSB
UN_VRMSB
OV_VRMSA
UN_VRMSA
UN_PFC
Frequency over High Limit
Under Low Frequency Limit
Temperature over High Limit
Under Low Temperature Limit
RMS Voltage C Over Limit
RMS Voltage C Under Limit
RMS Voltage B Over Limit
RMS Voltage B Under Limit
RMS Voltage A Over Limit
RMS Voltage A Under Limit
Power Factor C Under Limit
Power Factor B Under Limit
Power Factor A Under Limit
RMS Current C Over Limit
UN_PFB
UN_PFA
OV_IRMSC
OV_IRMSB
OV_IRMSA
VC_SAG
8
RMS Current B Over Limit
7
RMS Current A Over Limit
6
Voltage C Sag Condition Detected
Voltage B Sag Condition Detected
Voltage A Sag Condition Detected
Voltage Imbalance Detected
Current Imbalance Detected
External Oscillator is clocking source
Set by device after any type of reset
5
VB_SAG
4
VA_SAG
3
V_IMBAL
I_IMBAL
2
1
XSTATE
0
RESET
Always
Rev 3
39
MAX78630+PPM Data Sheet
Digital IO Functionality
The DIO_STATE register contains the current status of the DIOs. The user can use this register to read
the state of a DIO (if configured as an input) or control the state of the DIO (if configured as an output).
NOTE: Some pins are used as serial interface pins and may not be capable of user control. During reset,
all DIOs are configured as inputs.
Pin
Name
DIO
Bit
Alternate
Function
SPI
UART
I2C
MASK Register
AL1/DIO0
SCK/ADDR0/DIO1
SDI/RX/SDAI/DIO2
SDO/TX/SDAO/DIO3
AL2/DIO4
0
1
---
AL1
---
MASK1
---
SCK
SDI
ADDR0
ADDR0
SDAI
2
RXD
---
---
3
SDO
TXD
SDAO
---
---
4
---
AL2
---
MASK2
---
SSB/DIR/SCL//DIO5
AL3/ADDR1/DIO6
AL4/DIO7
5
SSB
---
RS485 DIR
SCL
6
ADDR1
ADDR1
AL3
AL4
---
MASK3
MASK4
---
7
---
IFC0/DIO8
8
IFC0 (at reset)
IFC1/DIO9
9
IFC1 (at reset)
---
---
AL5/DIO10
10
11
12
13
14
15
---
---
---
---
---
---
AL5
SGNV1
SGNV2
SGNV3
---
MASK5
CONFIG
CONFIG
CONFIG
---
SGNV1/DIO11
SGNV2/DIO12
SGNV3/DIO13
DIO14
DIO15
---
---
Interface configuration pins (IFC0, IFC1) and address pins (MP6/ADDR1, SCK/ADDR0) are input pins
sampled at the end of a reset to select the serial host interface and set device addresses (for I2C and
UART modes). If the IFC0 pin is low, the device will operate in the SPI mode. Otherwise, the state of IFC1
and the ADDR# pins determine the operating mode and device address.
These pins MUST remain configured as an input if directly connecting to GND/V3P3D. Otherwise, it
is recommended to use external pull-up or pull-down resistors accordingly.
40
Rev 2
MAX78630+PPM Data Sheet
DIO Direction
The DIO_DIR register sets the direction of the pins, where “1” is input and “0” is output. The same bit
definition as in the DIO_STATE register is used. If a DIO defined as an input is unconnected, internal pull-
ups will assert the respective DIO bit in the DIO_STATE register.
DIO Polarity
DIOs configured as outputs are by default active LOW. The logic “0” state is ON. This can be modified
using the DIO_POL register using the same bit definition as the DIO_STATE register. Any corresponding
bit set in the DIO_POL register will invert the same DIO output so that it becomes active high.
Alarm Pins
The MAX78630+PPM provides five MASK registers for signaling the status of any STATUS bit to one of
five Alarm (ALx) DIO pins. These MASK registers have the same bit mapping as the STATUS register.
The user must first enable the respective ALx pin as an output before the DIO can be driven to its active
state.
Pin Name
AL1
Register
MASK1
MASK2
MASK3
MASK4
MASK5
Description
AL2
A combination of a bit set in both the STATUS
register and a MASK register causes the assigned
ALx pin to be activated (default active-low).
AL3
AL4
AL5
Rev 3
41
MAX78630+PPM Data Sheet
Command Register
This register is used to issue commands to perform specific tasks to the device. Use of any command
not listed in this document can cause unpredictable and possibly dangerous behavior.
General Settings
The general settings allows the user to enable functions such as UART auto reporting, relay operations,
and Line Lock mode etc. These settings are used with all other commands and are stored as non-volatile
settings upon use of the Save to Flash Command (0xACC2xx).
Bit(s)
Value
Description
7
REN
1= reset all energy accumulators. This bit automatically clears to zero when the
reset completes.
6
RTRK
1= reset the minima and maxima registers for all monitored variables. This bit
automatically clears to zero when the reset completes.
5
4
LL
TC
0
Line Lock 1= lock to line cycle; 0= independent.
Temperature Compensation. Should be set to “1” for proper operation.
Reserved
3:0
No Action (0x00xxxx)
Allows the user to disable temperature updates
Bit(s)
23:12
11
Value
0x00
0
Description
No Action
Not Used
10
T
Stop temperature update: 1=stop; 0=update.
This bit prevents the firmware from overwriting the TempC (temperature result)
register. This is necessary when supplying a known temperature for calibration.
9:8
7:0
0
Not Used
See General Settings
42
Rev 2
MAX78630+PPM Data Sheet
Save to Flash Command (0xACC2xx)
Use this command to save to flash the calibration coefficients and system defaults contained in the some
of the input registers. Upon reset or power-on, the values stored in flash will become new system
defaults. The General Settings bits ([7:0] are stored in non-volatile storage while the upper 16 bits
(23:16]) are stored as 0x0000 (No Action Command). When the process completes, bits [23:8] are
cleared. The following table describes the command bits:
Bit(s)
23:12
11:8
7:0
Value
0xACC
0x2
Description
“Access” Command.
Save non-volatile values to flash.
See General Settings (0x00xxxx)
Clear Flash Storage 0 Command (0xACC0xx)
Use this command to clear the flash coefficients (non-volatile system defaults for some of the input
registers). Upon reset or power-on, the values revert to factory system defaults. This command should
always be used in conjunction with Clear Flash Storage 1 Command (0xACC1xx). When the process
completes, bits [23:8] are cleared.
Bit(s)
23:12
11:8
7:0
Value
0xACC
0x0
Description
“Access” Command.
Clear non-volatile values in flash.
See General Settings (0x00xxxx)
Clear Flash Storage 1 Command (0xACC1xx)
Use this command to clear the flash coefficients (non-volatile system defaults for some of the input
registers). Upon reset or power-on, the values revert to factory system defaults. This command should
always be used in conjunction with Clear Flash Storage 0 Command (0xACC0xx). When the process
completes, bits [23:8] are cleared.
Bit(s)
23:12
11:8
7:0
Value
0xACC
0x1
Description
“Access” Command.
Clear non-volatile values in flash.
See General Settings (0x00xxxx)
Rev 3
43
MAX78630+PPM Data Sheet
Calibration Command (0xCAxxxx/0xCBxxxx)
Use this command to start the calibration process for the selected inputs. It is assumed that appropriate
input signals are applied before starting calibration. When the calibration process completes, bits [23:17]
are cleared along with bits associated with channels that calibrated successfully. Any channels that failed
will have their corresponding bit left set.
Bit(s)
23:17
16
Value
Description
0x65
“Calibrate” Command.
1 = Calibrate Voltage for Phase C, 0 = no action
1 = Calibrate Voltage for Phase B, 0 = no action
1 = Calibrate Voltage for Phase A, 0 = no action
1 = Calibrate Current for Phase C, 0 = no action
1 = Calibrate Current for Phase B, 0 = no action
1 = Calibrate Current for Phase A, 0 = no action
1 = Calibrate Temperature, 0 = no action
15
14
13
12
11
10
9
Calibrate Offset versus Gain (0 = calibrate Gain; 1 = calibrate Offset)
Calibrate External Temperature Gain
8
XT
7:0
See General Settings (0x00xxxx)
44
Rev 2
MAX78630+PPM Data Sheet
Configuration Register
A CONFIG register is provided for system settings, such as sensor configuration, current sensor type,
power computations and hardware gains.
Bit(s)
23
Name
----
Description
Reserved for future use, write as zeroes
Invert voltage samples AV3
22
INV_AV3
INV_AV2
INV_AV1
VSGNC
VSGNB
VSGNA
EN_ROGC
21
Invert voltage samples AV2
20
Invert voltage samples AV1
19
Drive SGNV3/DIO13 with sign of voltage C
Drive SGNV2/DIO12 with sign of voltage B
Drive SGNV1/DIO11 with sign of voltage A
18
17
16
Enable Software Integrator on Current input
AI3
15
14
EN_ROGB
EN_ROGA
Enable Software Integrator on Current input
AI2
Enable Software Integrator on Current input
AI1
13 EN_PREAMPA Enable Pre-Amp on Current input AI1
12 ---- Reserved for future use, write as zero
11 EN_PREAMPB Enable Pre-Amp on Current input AI2
10
9
----
Reserved for future use, write as zero
EN_PREAMPC Enable Pre-Amp on Current input AI3
8
----
Reserved for future use, write as zero
7:6
PPHASE
Ignore phase for total power computations
00: none
01: phase A
10: phase B
11: phase C
5
VDELTA
VPHASE
Compute delta voltage between phases
4:3
Missing sensor on voltage input
00: none missing
01: AV1
10: AV2
11: AV3
2
INEUTRAL
IPHASE
Current sensor in neutral leg.
1:0
Missing sensor on current input
00: none missing
01: AI1
10: AI2
11: AI3
Rev 3
45
MAX78630+PPM Data Sheet
Application Examples
The MAX78630+PPM supports various three-phase topologies via appropriate setting of the CONFIG
register. This section describes connection diagrams, firmware settings and output data. In the system
diagrams the following convention is used:
•
A current sensor is shown as
o
o
a shunt resistor, if a non-isolated measurement is taken
a transformer plus a burden resistor, if an isolated measurement is taken. The
transformer depicts either a current transformer (CT) or a Rogowski-coil measurement. In
the latter case, the burden resistor is not required and the EN_ROGx bit in the CONFIG
register must be set accordingly.
•
Voltage sensors are shown as
o
o
Resistor divider networks, if a non-isolated measurement is taken
Transformers, if an isolated measurement is taken.
Configuration diagrams are grouped into three main categories:
1) Wye-connected source, wye-connected load (Y-Y)
2) Delta-connected source, delta-connected load (Δ-Δ)
3) Wye-connected source, delta-connected load (Y-Δ)
Note: this section is intended to show combinations of configurations and sensors and to describe
the settings and operation of the MAX78630+PPM. This list is not exhaustive.
46
Rev 2
MAX78630+PPM Data Sheet
Wye-connected source, wye-connected load (Y-Y)
These configurations require measurement of all three phases (voltage and current) in order to determine
the power. Therefore, six sensors are necessary.
Isolated configuration, 3 VT, 3 CT
A
A
Neutral
Neutral
LOAD C
LOAD B
B
B
C
C
MAX78630+PPM
CONFIG[22:20,7:0]
hex 0XXX00
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
00
0
00
0
00
Phase Phase
Phase
C
Total =
Sum of
Outputs
Comment
A
B
Line-To-
Neutral
Voltages
Voltages
Currents
VA
VB
VC
IC
---
---
Phase
currents
IA
IB
Power (P, Q, S)
computed from:
VA*IA
VB*IB
VC*IC
all three
Rev 3
47
MAX78630+PPM Data Sheet
Non-isolated configuration, 3 voltage-dividers, 3 CTs
A
A
Neutral
Neutral
LOAD C
LOAD B
B
B
C
C
MAX78630+PPM
CONFIG[22:20,7:0]
hex 0XXX00
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
00
0
00
0
00
Phase Phase
Phase
C
Total =
Sum of
Outputs
Comment
A
B
Line-To-
Neutral
Voltages
Voltages
Currents
VA
VB
VC
IC
---
---
Phase
currents
IA
IB
Power (P, Q, S)
computed from:
VA*IA
VB*IB
VC*IC
all three
48
Rev 2
MAX78630+PPM Data Sheet
Non-isolated, 3 voltage-dividers, 2 CTs, 1 Shunt
This configuration eliminates one current transformer (phase C in the diagram) and replaces it with a
shunt resistor in the neutral line.
A
A
Neutral
Neutral
LOAD C
LOAD B
B
B
C
C
MAX78630+PPM
CONFIG[22:20,7:0]
hex 0XXX07
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
00
0
00
1
11
Phase Phase
Phase
C
Total =
Sum of
Outputs
Voltages
Currents
Neutral
Comment
A
B
Line-To-Neutral
Voltages
VA
VB
VC
---
---
---
IN =
measured
from AIC
IC =
IN – IA - IB
IA
IB
Phase currents
Power (P, Q, S)
computed from:
VA*IA
VB*IB
VC*IC
---
all three
Rev 3
49
MAX78630+PPM Data Sheet
Non-isolated, 3 voltage-dividers, 3 shunts
This configuration eliminates all CTs and replaces them with shunt resistors that are referenced to
Neutral.
A
A
LOAD A
Shunt A
Neutral
Neutral
Shunt B
Shunt C
LOAD C
LOAD B
B
B
C
C
MAX78630+PPM
CONFIG[22:20,7:0]
hex 0XXX00
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
00
0
00
0
00
Phase Phase
Phase
Total =
Sum of
Outputs
Voltages
Currents
Comment
A
B
C
Line-To-Neutral
Voltages
VA
VB
VC
---
---
IA
IB
IC
Phase currents
Power (P, Q, S)
computed from:
VA*IA
VB*IB
VC*IC
all three
50
Rev 2
MAX78630+PPM Data Sheet
Delta-connected source, delta-connected load (Δ-Δ)
Delta configurations allow for the option to use 2 voltage sensors and/or 2 current sensors instead of 3.
The firmware supports these configurations, as well as addition of the third sensor in order to detect fault
conditions. Furthermore, the firmware supports placement of the current sensors in either the lines or in
the phases.
Non-isolated, 2 CTs, voltage-dividers referenced to V3P3, line current measurements
This configuration maintains high-impedance as seen from all phases by referencing measurements to a
virtual or floating center point. Note that the Line-to-Line voltages must be computed from the voltages at
the ADC inputs of the device, and therefore VDELTA must be set to “1”.
A
A
V3P3A
B
B
C
C
V3P3A
MAX78630
CONFIG[22:20,7:0]
hex 0XXX61
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
01
1
00
0
01
Phase
A
Phase
B
Phase
C
Total =
Sum of
Outputs
Voltages
Comment
VCA =
VC – VA
VAB =
VA - VB
VBC =
VB - VC
---
---
Line-To-Line Voltages
Line currents
IB =
IA + IC
Currents
IA
-IC
Per-phase powers
cannot be determined,
only total power
Power (P, Q, S)
computed from: (not needed)
---
VAB*IA +
VCB * IC
VAB*IA
-VBC*IC
Rev 3
51
MAX78630+PPM Data Sheet
Isolated configuration, 2 VTs, 2 CT, line current measurement
A
A
B
B
C
C
MAX78630
CONFIG[22:20,7:0]
hex 0XXX92
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
10
0
10
0
10
Phase
A
Phase
Phase
Total =
Sum of
Outputs
Voltages
Currents
Comment
Line-To-Line Voltages
Line currents
B
C
VAC =
VAB– VCB
VAB
IA
VCB
---
---
IB =
- IC – IA
IC
Power (P, Q, S)
computed from:
---
VAB*IA +
VBC * IC
Per-phase powers cannot be
determined, only total power
VAB*IA
VCB * IC
(not needed)
52
Rev 2
MAX78630+PPM Data Sheet
Non-isolated, 2 voltage-dividers referenced to line, 2 CTs, line current measurements
A
A
B
B
C
C
MAX78630
CONFIG[22:20,7:0]
hex 0XXX92
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
10
0
10
0
10
Phase
A
Phase
Phase
C
Total =
Sum of
Outputs
Voltages
Currents
Comment
B
VAC =
– VAB - VCB
VAB
IA
VCB
IC
---
---
Line-To-Line Voltages
Line currents
IB =
– IA - IC
Power (P, Q, S)
computed from:
---
VAB*IA + Per-phase powers cannot be
VCB * IC determined, only total power
VAB*IA
VCB * IC
(not needed)
Rev 3
53
MAX78630+PPM Data Sheet
Fully isolated, 3 VT, 3 CT, line current measurement
A
A
B
B
C
C
MAX78630
CONFIG[22:20,7:0]
hex 4XXX80
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
100
10
0
00
0
00
Phase
A
Phase
B
Phase
Total =
Sum of
Outputs
Voltages
Currents
Comment
C
VAB
IA
VCA
-VBC
---
---
Line-To-Line Voltages
Line currents
IB
---
IC
Power (P, Q, S)
computed from:
VAB*IA +
VCB * IC
Per-phase powers cannot be
determined, only total power
VAB*IA
-VBC * IC
(not needed)
54
Rev 2
MAX78630+PPM Data Sheet
Fully isolated, 3 VTs, 3 CTs, phase current measurement
A
A
LOAD
C
B
-
-
A
LOAD A
LOAD B-C
B
B
C
C
MAX78630
CONFIG[22:20,7:0]
hex 0XXX00
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
00
0
00
0
00
Phase
A
Phase
B
Phase
C
Total =
Sum of
Outputs
Voltages
Currents
Comment
VAB
IAB
VBC
IBC
VCA
ICA
---
---
Line-To-Line Voltages
Phase currents
Power (P, Q, S)
computed from:
VAB*IAB
VBC*IBC
VCA*ICA
all three
Rev 3
55
MAX78630+PPM Data Sheet
Non-isolated, 1 CT, 2 shunts and 2 voltage-dividers, all referenced to phase
This configuration replaces two of the three current transformers with shunts, in this example referenced
to phase B.
A
A
LOAD
C
B
-
-
A
LOAD A
LOAD B-C
B
B
C
C
MAX78630
CONFIG[22:20,7:0]
hex 0XXX10
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
00
0
10
0
00
Phase
A
Phase
B
Phase
C
Total =
Sum of
Outputs
Voltages
Currents
Comment
VAC =
VAB - VCB
VAB
IAB
VCB
ICB
---
---
Line-To-Line Voltages
Phase currents
IAC
Power (P, Q, S)
computed from:
VAB*IAB
VAC*IAC
VCB*ICB
all three
56
Rev 2
MAX78630+PPM Data Sheet
Wye-connected source, delta-connected load (Y-Δ)
Y-Δ configurations can be treated just like the Δ-Δ configurations. The phase voltages can be transformed
to line-to-line voltages via the VDELTA configuration bit. Consequently, load-side configuration as seen in
the previous section can be used in Y-Δ systems as well. As an example, the fully isolated configuration
is shown below.
Fully isolated, 3 VT, 2 CT, line current measurement
A
A
Neutral
B
B
C
C
MAX78630
CONFIG[22:20,7:0]
hex 0XXX61
INV_AV[CBA] PPHASE VDELTA VPHASE INEUTRAL IPHASE
000
01
1
00
0
01
Phase
Phase
B
Phase
C
Total =
Sum of
Outputs
Voltages
Comment
A
VCA =
VC – VA
VAB =
VA - VB
VBC =
VB - VC
---
---
Line-To-Line Voltages
Line currents
IB =
IA + IC
Currents
IA
-IC
Per-phase powers
cannot be determined,
only total power
Power (P, Q, S)
computed from: (not needed)
---
VAB*IA +
VCB * IC
VAB*IA
-VBC*IC
Rev 3
57
MAX78630+PPM Data Sheet
Register Access
All user registers are contained in a 256 word (24-bits each) area of the on-chip RAM and can be
accessed through the UART, SPI, or I2C interfaces. These registers are byte-addressable via the UART
interface and word-addressable via the SPI, and I2C interfaces.
These registers consist of read (output), write (input), and read/write in the case of the Command
Register. Writing to reserved registers or to unspecified memory locations could result in device
malfunction or unexpected results.
Data Types
The input and output registers have different data types, depending on their assignment and functions.
The notation used indicates whether the number is signed, unsigned, or bit-mapped and the location of
the binary point.
INT
Indicates a 24-bit integer with a range of 0 to 16777215 typically used for counters or
Boolean registers with 24 independent bit values.
S
.
Indicates a signed fixed point value.
Indicates a fixed point number.
nn
Indicates the number of bits to the right of the binary point.
Example:
S.21 is a 24-bit signed fixed-point number with 21 fraction bits to the right of the binary
point and a range of -4.0 to 4-2-21
Bit Position
23
22 21
.
20 19 18 17
…
2
1
0
Bit Multiplier
Sign bit
(-22)
21 20
2-1 2-2 2-3 2-4
…
2-19 2-20 2-21
Max Value
Min Value
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
58
Rev 2
MAX78630+PPM Data Sheet
Register Locations
Use Word addresses for I2C and SPI interfaces and Byte addresses for the SSI (UART) protocol.
Nonvolatile (NV) register defaults are indicated with a ‘Y’. All other registers are initialized as described in
the Functional Description.
Word Byte
Addr Addr
Register
Type
NV Description
(hex) (hex)
0
1
2
0
3
6
COMMAND
FW_VERSION
CONFIG
INT
INT
INT
Y
Selects modes, functions, or options
Hardware and firmware version
Selects input configuration
Y
Y
Minimum high-rate samples per accumulation
interval
3
9
SAMPLES
INT
4
5
C
DIVISOR
CYCLE
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
S.23
S.23
S.21
S.21
S.22
INT
Actual samples in previous accumulation interval
High-rate sample counter
F
6
12
15
18
1B
1E
21
24
27
2A
2D
30
33
36
39
3C
3F
42
45
48
4B
FRAME
Low-rate sample counter
7
STATUS
Alarm and device status bits
8
STATUS_CLEAR
STATUS_SET
MASK1
Used to reset alarm/status bits
9
Used to set/force alarm/status bits
A
Y
Y
Y
Y
Y
Y
Alarm/status mask for AL1 output pin
Alarm/status mask for AL2 output pin
Alarm/status mask for AL3 output pin
Alarm/status mask for AL4 output pin
Alarm/status mask for AL5 output pin
Alarm/status bits to hold until cleared by host
State of DIO pins
B
MASK2
C
MASK3
D
MASK4
E
MASK5
F
STICKY
10
11
12
13
14
15
16
17
18
19
DIO_STATE
DIO_DIR
Y
Y
Y
Y
Y
Y
Y
Y
Y
Direction of DIO pins. 1=Input ; 0=Output
Polarity of DIO pins. 1=Active High ; 0=Active Low
Number of calibration cycles to average
Current input HPF coefficient. Positive values only
Voltage input HPF coefficient. Positive values only
Phase compensation (±4 samples) for AV1 input
Phase compensation (±4 samples) for AV2 input
Phase compensation (±4 samples) for AV3 input
Harmonic Selector, default: 1 (fundamental)
DIO_POL
CALCYCS
HPF_COEF_I
HPF_COEF_V
PHASECOMP1
PHASECOMP2
PHASECOMP3
HARM
High order address bits for I2C and UART
interfaces
1A
4E
DEVADDR
INT
Y
1B
1C
1D
1E
1F
20
51
54
57
5A
5D
60
BAUD
INT
Y
Y
Y
Y
Y
Y
Baud rate for UART interface
I1_GAIN
I2_GAIN
I3_GAIN
V1_GAIN
V2_GAIN
S.21
S.21
S.21
S.21
S.21
Current Gain Calibration.Positive values only
Current Gain Calibration.Positive values only
Current Gain Calibration.Positive values only
Voltage Gain Calibration. Positive values only
Voltage Gain Calibration. Positive values only
Rev 3
59
MAX78630+PPM Data Sheet
Word Byte
Addr Addr
Register
Type
NV Description
(hex) (hex)
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
63
66
69
6C
6F
72
75
78
7B
7E
81
84
87
8A
8D
90
93
96
99
9C
9F
A2
A5
A8
AB
V3_GAIN
I1_OFFS
I2_OFFS
I3_OFFS
V1_OFFS
V2_OFFS
V3_OFFS
T_GAIN
S.21
S.23
S.23
S.23
S.23
S.23
S.23
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Voltage Gain Calibration. Positive values only
Current Offset Calibration
Current Offset Calibration
Current Offset Calibration
Voltage Offset Calibration
Voltage Offset Calibration
Voltage Offset Calibration
Temperature Slope Calibration
Temperature Offset Calibration
Voltage sag detect interval (high-rate samples)
Voltage imbalance alarm limit. Positive values only
Current imbalance alarm limit. Positive values only
Instantaneous Voltage
T_OFFS
VSAG_INT
V_IMB_MAX
I_IMB_MAX
VA
INT
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
VB
Instantaneous Voltage
VC
Instantaneous Voltage
VA_RMS
VB_RMS
VC_RMS
VT_RMS
VFUND_A
VFUND_B
VFUND_C
VHARM_A
VHARM_B
VHARM_C
RMS Voltage
RMS Voltage
RMS Voltage
RMS Voltage average (Total / 3)
Fundamental Voltage
Fundamental Voltage
Fundamental Voltage
Harmonic Voltage
Harmonic Voltage
Harmonic Voltage
Calibration Target for Voltages. Positive values
only
3A
AE
V_TARGET
S.23
Y
3B
3C
3D
3E
3F
40
B1
B4
B7
BA
BD
C0
VRMS_MIN
S.23
S.23
S.23
S.23
S.23
S.23
Y
Y
Y
Voltage lower alarm limit. Positive values only
Voltage upper alarm limit. Positive values only
RMS Voltage Sag threshold. Positive values only
Instantaneous Current
VRMS_MAX
VSAG_LIM
IA
IB
IC
Instantaneous Current
Instantaneous Current
RMS Current dynamic offset adjust. Positive
values only
RMS Current dynamic offset adjust. Positive
values only
RMS Current dynamic offset adjust. Positive
values only
41
42
C3
C6
IARMS_OFF
IBRMS_OFF
S.23
S.23
Y
Y
Y
43
44
C9
ICRMS_OFF
IA_PEAK
S.23
S.23
CC
Peak Current
60
Rev 2
MAX78630+PPM Data Sheet
Word Byte
Addr Addr
Register
Type
NV Description
(hex) (hex)
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
CF
D2
D5
D8
DB
DE
E1
E4
E7
EA
ED
F0
F3
IB_PEAK
IC_PEAK
IA_RMS
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
Peak Current
Peak Current
RMS Current
RMS Current
RMS Current
IB_RMS
IC_RMS
IT_RMS
RMS Current average (Total / 3)
IFUND_A
IFUND_B
IFUND_C
IHARM_A
IHARM_B
IHARM_C
IRMS_MAX
Fundamental Current
Fundamental Current
Fundamental Current
Harmonic Current
Harmonic Current
Harmonic Current
Y
Y
Current upper alarm limit. Positive values only
Calibration Target for Currents. Positive values
only
52
F6
I_TARGET
S.23
53
54
55
56
57
58
F9
FC
QFUND_A
QFUND_B
QFUND_C
QHARM_A
QHARM_B
QHARM_C
S.23
S.23
S.23
S.23
S.23
S.23
Fundamental Reactive Power
Fundamental Reactive Power
Fundamental Reactive Power
Harmonic Reactive Power
Harmonic Reactive Power
Harmonic Reactive Power
FF
102
105
108
Reactive Power dynamic offset adjust. Positive
values only
Reactive Power dynamic offset adjust. Positive
values only
Reactive Power dynamic offset adjust. Positive
values only
Active Power dynamic offset adjust. Positive
values only
Active Power dynamic offset adjust. Positive
values only
Active Power dynamic offset adjust. Positive
values only
59
5A
5B
5C
5D
5E
10B
10E
111
114
117
11A
QA_OFFS
QB_OFFS
QC_OFFS
PA_OFFS
PB_OFFS
PC_OFFS
S.23
S.23
S.23
S.23
S.23
S.23
Y
Y
Y
Y
Y
Y
5F
60
61
62
63
64
65
66
67
11D
120
123
126
129
12C
12F
132
135
WATT_A
WATT_B
WATT_C
VAR_A
VAR_B
VAR_C
VA_A
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
S.23
Active Power
Active Power
Active Power
Reactive Power
Reactive Power
Reactive Power
Apparent Power
Apparent Power
Apparent Power
VA_B
VA_C
Rev 3
61
MAX78630+PPM Data Sheet
Word Byte
Addr Addr
(hex) (hex)
Register
Type
NV Description
Active Power average (Total / 3)
68
69
6A
6B
6C
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
138
13B
13E
141
144
14A
14D
150
153
156
159
15C
15F
162
165
168
16B
16E
171
174
177
17A
17D
180
183
186
189
18C
18F
192
195
WATT_T
VAR_T
VA_T
S.23
S.23
S.23
INT
Reactive Power average (Total / 3)
Apparent Power average (Total / 3)
Scratch register (see Scaling Registers section)
Scratch register (see Scaling Registers section)
Fundamental Power
IFSCALE
VSCALE
PFUND_A
PFUND_B
PFUND_C
PHARM_A
PHARM_B
PHARM_C
VAFUNDA
VAFUNDB
VAFUNDC
PFA
Y
Y
INT
S.23
S.23
S.23
S.23
S.23
S.23
Fundamental Power
Fundamental Power
Harmonic Power
Harmonic Power
Harmonic Power
Fundamental Volt Amperes
Fundamental Volt Amperes
Fundamental Volt Amperes
Power Factor
S.22
S.22
S.22
S.22
S.22
S.10
S.10
S.10
S.10
S.16
S.16
S.16
PFB
Power Factor
PFC
Power Factor
PF_T
Total Power Factor
PF_MIN
TEMPC
T_TARGET
T_MIN
Y
Power Factor lower alarm limit
Chip Temperature (Celsius°)
Temperature calibration target
Temperature Alarm Lower Limit
Temperature Alarm Upper Limit
Line Frequency
Y
Y
Y
T_MAX
FREQ
F_MIN
Y
Y
Frequency Alarm Lower Limit
Frequency Alarm Upper Limit
Minimum Recorded Value 1
Minimum Recorded Value 2
Minimum Recorded Value 3
Minimum Recorded Value 4
Minimum Recorded Value 5
F_MAX
MIN0
MIN1
MIN2
MIN3
MIN4
Minimum Recorded Value 6
(reserved when EN_ROGA =1)
Minimum Recorded Value 7
(reserved when EN_ROGB =1)
Minimum Recorded Value 8
(reserved when EN_ROGC =1)
88
89
8A
198
19B
19E
MIN5
MIN6
MIN7
8B
8C
8D
1A1
1A4
1A7
MAX0
MAX1
MAX2
Maximum Recorded Value 1
Maximum Recorded Value 2
Maximum Recorded Value 3
62
Rev 2
MAX78630+PPM Data Sheet
Word Byte
Addr Addr
(hex) (hex)
Register
Type
NV Description
Maximum Recorded Value 4
8E
8F
1AA
1AD
MAX3
MAX4
Maximum Recorded Value 5
Maximum Recorded Value 6
(reserved when EN_ROGA =1)
Maximum Recorded Value 7
(reserved when EN_ROGB =1)
Maximum Recorded Value 8
(reserved when EN_ROGC =1)
90
91
92
1B0
1B3
1B6
MAX5
MAX6
MAX7
93
94
95
96
97
98
99
9A
9B
9C
9F
A2
A5
A8
AB
AE
B1
B4
B7
BA
BD
C0
1B9
1BC
1BF
1C2
1C5
1C8
1CB
1CE
1D1
1D4
1DD
1E6
1EF
1F8
201
20A
213
21C
225
22E
237
240
MMADDR0
MMADDR1
MMADDR2
MMADDR3
MMADDR4
MMADDR5
MMADDR6
MMADDR7
BUCKET
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
INT
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Min/Max Monitor address 1
Min/Max Monitor address 2
Min/Max Monitor address 3
Min/Max Monitor address 4
Min/Max Monitor address 5
Min/Max Monitor address 6
Min/Max Monitor address 7
Min/Max Monitor address 8
Energy Bucket Size – Low word
Energy Bucket Size – High word
Received Active Energy Counter
Delivered Active Energy Counter
Received Active Energy Counter
Delivered Active Energy Counter
Received Active Energy Counter
Delivered Active Energy Counter
Reactive Energy Leading Counter
Reactive Energy Lagging Counter
Reactive Energy Leading Counter
Reactive Energy Lagging Counter
Reactive Energy Leading Counter
Reactive Energy Lagging Counter
BUCKET
WHA_POS
WHA_NEG
WHB_POS
WHB_NEG
WHC_POS
WHC_NEG
VARHA_POS
VARHA_NEG
VARHB_POS
VARHB_NEG
VARHC_POS
VARHC_NEG
Bit 23 is a sticky register with status of any SPI
Errors
C1
243
SYSSTAT
INT
Rev 3
63
MAX78630+PPM Data Sheet
Serial Interfaces
All user registers are contained in a 256 word (24-bits each) area of the on-chip RAM and can be
accessed through the UART, SPI, or I2C interfaces. While access to a single byte is possible with some
interfaces, it is highly recommended that the user access words (or multiple words) of data with each
transaction.
Only one interface can be active at a time. The interface selection pins are sampled at the end of a reset
sequence to determine the operating mode.
Interface Mode
IFC0
IFC1
SPI
0
1
1
X (don’t care)
UART
I2C
0
1
UART Interface
The device implements a simple serial interface (SSI) protocol on the UART interface that features:
•
•
•
•
Support for single and multi-point communications
Transmit (direction) control for an RS-485 transceiver
Efficient use of a low bandwidth serial interface
Data integrity checking
The default configuration is 38400 baud, 8-bit, no-parity, 1 stop-bit, no flow control. The value in the
BAUD register determines the baud rate to be used. Example: To select a 9600 baud rate, the user writes
a decimal 9600 to the BAUD register. The new rate will not take effect immediately. It must be saved to
flash and will take effect at the next reset. The maximum BAUD value is limited to 115200.
RS-485 Support
The SSB/DIR/SCL pin is used to drive an RS-485 transceiver output enable or direction pin. The
implemented protocol supports a full-duplex 4-wire RS-485 bus.
A
ROUT
SDI/RX/SDAI
SSB/DIR/SCL
RS-485 BUS
B
REN
DEN
4.7K
A
B
MAX78630+PPM
DIN
RS-485 BUS
SDO/TX/SDAO
64
Rev 2
MAX78630+PPM Data Sheet
Device Address Configuration
The SSI protocol utilizes 8-bit addressing for multi-point communications. The usable SSI ID range
is 1 to 254. In multi-point systems with more than 4 targets, the user must configure device address bits
in the DEVADDR according to the formula SSI ID = Device Address +1.
A device address of 'FF' is not supported. DEVADDR [23:6] bit are not used and must be set to 1.
Device Address
7
6
5
4
3
2
1
0
SSI ID =
DEVADDR Register bit 5:0
DIO6/ADDR1 Pin
Device Address +1
DIO1/ADDR0 Pin
SSI Protocol Description
The SSI protocol is command response system supporting a single master and one or more targets. The
host (master) sends commands to a selected target that first verifies the integrity of the packet before
sending a reply or executing a command. Failure to decode a host packet will cause the selected target to
send a fail code. If the condition of a received packet is uncertain, no reply is sent.
Each target must have a unique SSI ID. Zero is not a valid SSI ID for a target device as it is used by the
host to de-select all target devices.
With both address pins low on the MAX78630+PPM, the SSI ID defaults to 1 and is the “Selected” device
following a reset. This configuration is intended for single target (point-to-point) systems that do not
require the use of device addressing or selecting targets.
In multi-point systems, the master will typically de-select all target devices by selecting SSI ID #0. The
master must then select the target with a valid SSI ID and get an acknowledgement from the slave before
setting the target’s register address pointer and performing read or write operations. If no target is
selected, no reply is sent. The SSB/DIR/SCL pin is asserted while the device is selected. The sequence
of operation is shown in the following diagram.
Select Target
Device
Set Register
Address Pointer
Read/Write
Commands
De-Select
Target Device
Rev 3
65
MAX78630+PPM Data Sheet
Master Packets
Master packets always start with the 1-byte header (0xAA) for synchronization purposes. The master then
sends the byte count of the entire packet (up to 255 byte packets) followed by the payload (up to 253
bytes) and a 1-byte modulo-256 checksum of all packet bytes for data integrity checking.
The payload can contain either a single command or multiple commands if the target is already selected.
It can also include device addresses, register addresses, and data. All multi-byte payloads are sent and
received least-significant-byte first.
Master Packet Command Summary
Command
0 - 7F
80 - 9F
A0
Parameters
Description
(invalid)
(not used)
Clear address
A1
[byte-L]
[byte-H]
Set Read/Write address bits [7:0]
Set Read/Write address bits [15:8]
A2
A3
[byte-L][byte-H] Set Read/Write address bits [15:0]
(reserved for larger address targets)
(not used)
A4 - AF
B0 - BF
C0
De-select Target (target will Acknowledge)
Select target 1 to 14 (target will Acknowledge)
C1 - CE
CF
[byte]
[data...]
[data...]
[byte]
Select target 0 to 255 (target will Acknowledge)
Write bytes set by remainder of Byte Count
Write 1 to 15 bytes
D0
D1 - DF
E0
Read 0 to 255 bytes
E1 – EF
F0 - FF
Read 1 to 15 bytes
(not used)
Users only need to implement commands they actually need or intend to use. For example, only one
address command is required – either 0xA1 for systems with 8 address bits or less or 0xA3 for systems
with 9 to 16 address bits. Likewise, only one write, read, or select target command needs to be
implemented. Select Target is not needed in systems with only one target.
66
Rev 2
MAX78630+PPM Data Sheet
Command Payload Examples
Device Selection
PAYLOAD
SSI ID
0xCF Command
Register Address Pointer Selection
PAYLOAD
0xA3 Command
Register Address (2 Bytes)
Small Read Command (3 bytes)
PAYLOAD
0xE3 Command
Large Read Command (30 bytes)
PAYLOAD
0xE0 Command
0x1E (30 bytes)
Small Write Command (3 bytes)
PAYLOAD
3 Bytes of Data
0xD3 Command
Large Write Command (30 bytes)
Byte Count
PAYLOAD
30 Bytes of Data
0x21 (34 bytes)
0xD0 Command
After each read or write operation, the internal address pointer is incremented to point to the address that
followed the target of the previous read or write operation.
Rev 3
67
MAX78630+PPM Data Sheet
Slave Packets
The type of slave packet depends upon the type of command from the master device and the successful
execution by the slave device. Standard replies include “Acknowledge” and “Acknowledge with Data”.
ACKNOWLEDGE
without data
ACKNOWLEDGE
with data
BYTE
COUNT
READ
DATA
CHECK
SUM
If no data is expected from the slave or there is a fail code, a single byte reply is sent. If a successfully
decoded command is expected to reply with data, the slave sends a packet format similar to the master
packet where the header is replaced with a Reply Code and the payload contains the read data.
Reply Code
0xAA
Definition
Acknowledge with data
0xAB
Acknowledge with data (half duplex)
Acknowledge without data.
Negative Acknowledge (NACK).
Command not implemented.
Checksum failed.
0xAD
0xB0
0xBC
0xBD
0xBF
Buffer overflow (or packet too long).
- timeout - Any condition too difficult to handle with a reply.
Failure to decode a host packet will cause the selected target to send a fail code (0xB0 – 0xBF)
acknowledgement depending on mode of failure. Masters wishing to simplify could accept any
unimplemented fail code as a Negative Acknowledge.
If no target is selected or the condition of a received packet is uncertain, no reply is sent. Timeouts can
also occur when data is corrupt or no target is selected. The master should implement the appropriate
timeout control logic after approximately 50 byte times at the current baud rate. When a first reply byte is
received, the master should check to see if it is an SSI header or an Acknowledge. If so, the timeout timer
is reset, and each subsequent receive byte will also reset the timer. If no byte is received within the
timeout interval, the master can expect the slave timed out and re-send a new command.
68
Rev 2
MAX78630+PPM Data Sheet
SPI Interface
The Maxim device operates as a SPI slave. The host is expected to instigate and control all transactions.
The signals used for SPI communication are defined as:
•
•
•
•
SSB
SCK
SDI
: (also known as CSB) the device SPI chip/slave select signal (active low)
: the clocking signal that clocks MISO and MOSI (data)
: (also known as MOSI) the data shifted into the measurement device
SDO : (also known as MISO) the data shifted out of the measurement device
In Maxim embedded measurement devices, these signals may have alternate functionality depending
upon the device mode and/or firmware.
SPI Mode
The device operates as a slave in mode 3 (CPOL=1,CPHA==1) and as such the data is captured on the
rising edge and propagated on the falling edge of the serial data clock(SCK). Figure 1 shows a single-
byte transaction on the SPI bus. Bytes are transmitted/received MSB first.
SCK
MSB
MSB
6
6
5
5
4
4
3
3
2
2
1
1
LSB
LSB
SDI
SDO
SSB
Signal Timing on the SPI Bus
Rev 3
69
MAX78630+PPM Data Sheet
Single Word SPI Reads
The device supplies direct read access to the device RAM memory. To read the RAM the master device
must send a read command to the slave device and then clock out the resulting read data. SSB must be
kept active low for the entire read transaction (command and response). SCK may be interrupted as long
as SSB remains low. ADDR[5:0] is filled with the word address of the read transaction. RAM data
contents are transmitted most significant byte first. ADDR[5:0] cannot exceed 0x3F. RAM words, and
therefore the results, are natively 24 bits (3 bytes) long.
Byte#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
2
3
4
0x01
ADDR[5:0]
0x0
0
0
0
Single Word SPI Read Command (SDI)
The slave responds with the data contents of the requested RAM addresses.
Byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Number
0
1
2
3
4
Hi-Z (during Read Command)
Hi-Z (during Read Command)
DATA[23:16] @ ADDR
DATA[15:8] @ ADDR
DATA[7:0]
@ ADDR
Single Word SPI Read Response (SDO)
Read Command[0]
Read Command[1]
SDI
SDO
SCK
0
0
0
HiZ
Data[23:16]
SCK Active
Data[15:8]
Data[7:0]
SSB
Single Word Read Access Timing
70
Rev 2
MAX78630+PPM Data Sheet
Single Word SPI Writes
The device supplies direct write access to the device RAM memory. To write the RAM the master device
must send a write command to the slave device and then clock out the write data. SSB must be kept
active low for the entire write transaction (command and data). SCK may be interrupted as long as SSB
remains low. ADDR[5:0] is filled with the word address of the write transaction. RAM data contents are
transmitted most significant byte first. ADDR[5:0] cannot exceed 0x3F. RAM words are natively 24 bits
(3 bytes) long.
Byte#
Bit 7
Bit 6
Bit 5
Bit 4
0x01
Bit 3
Bit 2
Bit 1
0x02
Bit 0
0
1
2
3
4
ADDR[5:0]
DATA[23:16] @ ADDR
DATA[15:8] @ ADDR
DATA[7:0]
@ ADDR
Single Word SPI Write Command and Data (SDI)
The slave SDO remains Hi-Z during a write access.
Write Command[0]
Write Command[1]
Data[23:16]
HiZ
Data[15:8]
Data[7:0]
SDI
SDO
SCK
SCK Active
SSB
Single Word Write Access Timing
Rev 3
71
MAX78630+PPM Data Sheet
I2C Interface
The MAX78630+PPM has an I2C interface available at the SDAI, SDAO, and SCL pins. The interface
supports I2C slave mode with a 7-bit address and operates at a data rate up to 400 kHz. The figure below
shows two possible configurations. Configuration A is the standard configuration. The double pin for SDA
also allows for isolated configuration B.
V3P3 or 5VDC
5VDC
SDAi
V
3P3 or 5VDC
SDA
SDA
SDAi
V3P3 or 5VDC
I2C_GND
SDAo
SDAo
SCK
5VDC
SCK
SCK
SCK
A) STANDARD CONFIGURATION
B) ISOLATED CONFIGURATION
Device Address Configuration
By default, there are only four possible addresses for the MAX78630+PPM as defined by two external
address pins. To expand the potential address of the device to the entire 7-bit address range for I2C, one
must first set bits [11:5] in the DEVADDR register. Bits 6 through 2 of the device address can then be
defined by the lower 5-bits of the DEVADDR register (bits 4:0).
DEVADDR bits 23 through 12 are not used and should be set to 0.
Device Address
6
5
4
3
2
1
0
DEVADDR Register bit 4:0
MP6/ADDR1 Pin
SCK/ADDR0 Pin
72
Rev 2
MAX78630+PPM Data Sheet
Bus Characteristics
•
•
A data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH will be interpreted as a START or STOP condition.
Bus Conditions:
•
•
Bus not Busy (I): Both data and clock lines are HIGH indicating an Idle Condition.
Start Data Transfer (S): a HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH
determines a START condition. All commands must be preceded by a START condition.
•
•
Stop Data Transfer (P): a LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH
determines a STOP condition. All operations must be ended with a STOP condition.
Data Valid: The state of the data line represents valid data when, after a START condition, the data
line is stable for the duration of the HIGH period of the clock signal. The data on the line must be
changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each
data transfer is initiated with a START condition and terminated with a STOP condition.
•
Acknowledge (A): Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse, which is
associated with this Acknowledge bit. The device that acknowledges has to pull down the SDA line
during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH
period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into
account. During reads, a master must signal an end of data to the slave by not generating an
Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave
(MAX78630+PPM) will leave the data line HIGH to enable the master to generate the STOP
condition.
MSB
SDA
9
ACK
9
ACK
1
7
8
SCL
2
SCL may be held low by
slave to service interrupts
Start Bit
Start or Stop Bits
Device Addressing
A control byte is the first byte received following the START condition from the master device.
The control byte consists of a seven bit address and a bit (LSB) indicating the type of access (0=write;
1=read).
DEVICE ADDRESS
LSB
X
MSB
X
S
X
X
X
X
X
R/W ACK
READ/WRITE
ACKNOWLEDGE
START BIT
Rev 3
73
MAX78630+PPM Data Sheet
Write Operations
Following the START (S) condition from the master, the device address (7-bits) and the R/W bit (logic low
for write) are clocked onto the bus by the master. This indicates to the addressed slave receiver that the
register address will follow after it has generated an acknowledge bit (A) during the ninth clock cycle.
Therefore, the next byte transmitted by the master is the register address and will be written into the
address pointer of the MAX78630+PPM. After receiving another acknowledge (A) signal from the
MAX78630+PPM, the master device will transmit the data byte(s) to be written into the addressed
memory location. The data transfer ends when the master generates a stop (P) condition. This initiates
the internal write cycle. The example below shows a 3-byte data write (24-bit register write).
S
Device Address
0
Register Address
Data
Data
Data
P
0
1
2
3
4
5
6
0
1 2 3 4 5 6 7
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1 2 3 4 5 6 7
0
0
0
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
A
C
K
Upon receiving a STOP (P) condition, the internal register address pointer will be incremented. The write
access can be extended to multiple sequential registers. The figure below shows a single transaction with
multiple registers written sequentially.
REGISTER (n+1)
REGISTER (n)
REGISTER (n+2) REGISTER (n+x)
P
S
Device Address
0
Data
Data
Data
Register Address (n)
0
1 2 3 4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
4
6 7
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1
0
2
3
4
5
6
7
6 7
0
0
A
C
K
A
C
K
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
74
Rev 2
MAX78630+PPM Data Sheet
Read Operations
Read operations are initiated in the same way as write operations with the exception that the R/W bit of
the control byte is set to one. There are two basic types of read operations: current address read and
random read.
Current Address Read: the MAX78630+PPM contains an address counter that maintains the address of
the last register accessed, internally incremented by one when the stop bit is received. Therefore, if the
previous read access was to register address n, the next current address read operation would access
data from address n + 1.
Upon receipt of the control byte with R/W bit set to one, the MAX78630+PPM issues an acknowledge (A)
and transmits the eight bit data byte. The master will not acknowledge the transfer, but generates a STOP
condition to end the transfer and the MAX78630+PPM will discontinue the transmission.
S
Device Address
1
Data
Data
Data
P
0
1
2
3
4
5 6
1
2
3
4
5
6
7
1
2
3
4
5
6
7
1 2 3 4 5 6 7
0
0
0
A
C
K
S
T
A
R
T
S
T
O
P
A
C
K
A
C
K
N
O
A
C
K
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value. If the register address pointer has not been set by previous operations, it is
necessary to set it issuing a command as follows:
S
Device Address
0
S
Register Address (n)
P
0
1
2
3
4
5
6
0 1 2 3 4 5 6 7
A
C
K
A
C
K
S
T
A
R
T
S
T
O
P
Random Read: random read operations allow the master to access any register in a random manner. To
perform this operation, the register address must be set as part of the write operation. After the address is
sent, the master generates a start condition following the acknowledge response. This sequence
completes the write operation. The master should issue the control byte again this time, with the R/W bit
set to 1 to indicate a read operation. The MAX78630+PPM will issue the acknowledge response, and
transmit the data. At the end of the transaction the master will not acknowledge the transfer and generate
a STOP condition.
S
R
S
Device Address
0
S
Register Address (n)
Device Address
1
Data
S
Data
Data
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
1 2 3 4 5 6 7
0
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
O
S
T
A
R
T
A
C
K
This read operation is not limited to 3 bytes but can be extended until the register address pointer
reaches its maximum value.
Rev 3
75
MAX78630+PPM Data Sheet
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFN
TOP MARK
EMP
MAX78630+PPM/D00
MAX78630+PPM/D00T
32 TQFN
EMP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Contact Information
For more information about the MAX78630+PPM or other Maxim Integrated products, go to:
www.maximintegrated.com/support.
76
Rev 2
MAX78630+PPM Data Sheet
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
4/13
Initial release
—
11/13
Updated register map and SPI Slave Select description
58, 62, 68
42–44,
69–71
2
3
5/14
8/14
Updated Command Register and SPI Interface sections
Updated storage temperature parameter in the Electrical
Characteristics table and the SPI Interface section
4, 69–71
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit
patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric
values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are
provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
77
© 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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