MAX796EPE [MAXIM]
Step-Down Controllers with Synchronous Rectifier for CPU Power; 降压型控制器，具有同步整流的CPU电源
| 型号： | MAX796EPE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Step-Down Controllers with Synchronous Rectifier for CPU Power |
| 文件： | 总32页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0221; Rev 3a; 11/97
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6/MAX79
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 96% Efficiency
The MAX796/MAX797/MAX799 high-performance, step-
down DC-DC converters with single or dual outputs
provide main CPU power in battery-powered systems.
These buck controllers achieve 96% efficiency by using
synchronous rectification and Maxim’s proprietary Idle
Mode™ control scheme to extend battery life at full-load
(up to 10A) and no-load outputs. Excellent dynamic
response corrects output transients caused by the latest
dynamic-clock CPUs within five 300kHz clock cycles.
Unique bootstrap circuitry drives inexpensive N-channel
MOSFETs, reducing system cost and eliminating the
crowbar switching currents found in some PMOS/NMOS
switch designs.
♦ 4.5V to 30V Input Range
♦ 2.5V to 6V Adjustable Output
♦ Preset 3.3V and 5V Outputs (at up to 10A)
♦ Multiple Regulated Outputs
♦ +5V Linear-Regulator Output
♦ Precision 2.505V Reference Output
♦ Automatic Bootstrap Circuit
♦ 150kHz/300kHz Fixed-Frequency PWM Operation
♦ Programmable Soft-Start
The MAX796/MAX799 are specially equipped with a sec-
ondary feedback input (SECFB) for transformer-based
dual-output applications. This secondary feedback path
improves cross-regulation of positive (MAX796) or nega-
tive (MAX799) auxiliary outputs.
♦ 375µA Typ Quiescent Current (V = 12V, V
= 5V)
IN
OUT
♦ 1µA Typ Shutdown Current
The MAX797 has a logic-controlled and synchronizable
fixed-frequency pulse-width-modulating (PWM) operating
mode, which reduces noise and RF interference in sensi-
tive mobile-communications and pen-entry applications.
The SKIP override input allows automatic switchover to
idle-mode operation (for high-efficiency pulse skipping) at
light loads, or forces fixed-frequency mode for lowest noise
at all loads.
______________Ord e rin g In fo rm a t io n
†
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
Dice*
MAX796CPE
MAX796CSE
MAX796C/D
MAX796EPE
MAX796ESE
MAX796MJE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 Narrow SO
16 CERDIP
The MAX796/MAX797/MAX799 are all available in 16-
pin DIP and narrow SO packages. See the table below
to compare these three converters.
Ordering Information continued at end of data sheet.
*Contact factory for dice specifications.
PART
MAX796
MAX797
MAX799
MAIN OUTPUT
SPECIAL FEATURE
Regulates positive secondary
voltage (such as +12V)
3.3V/5V or adj.
__________________P in Co n fig u ra t io n
3.3V/5V or adj. Logic-controlled low-noise mode
Regulates negative secondary
3.3V/5V or adj.
TOP VIEW
voltage (such as -5V)
SS
DH
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
________________________Ap p lic a t io n s
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Cellular Phones
LX
(SECFB) SKIP
REF
BST
DL
GND
MAX796
MAX797
MAX799
PGND
VL
SYNC
SHDN
FB
V+
CSH
CSL
Idle Mode is a trademark of Maxim Integrated Products.
DIP/SO
†
( ) ARE FOR MAX796/MAX799.
U.S. and foreign patents pending.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
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ABSOLUTE MAXIMUM RATINGS
V+ to GND.................................................................-0.3V, +36V
GND to PGND........................................................................±2V
VL to GND ...................................................................-0.3V, +7V
BST to GND...............................................................-0.3V, +36V
DH to LX...........................................................-0.3V, BST + 0.3V
LX to BST.....................................................................-7V, +0.3V
SHDN to GND............................................................-0.3V, +36V
SYNC, SS, REF, FB, SECFB, SKIP, DL to GND..-0.3V, VL + 0.3V
CSH, CSL to GND .......................................................-0.3V, +7V
VL Short Circuit to GND..............................................Momentary
REF Short Circuit to GND...........................................Continuous
VL Output Current...............................................................50mA
Continuous Power Dissipation (T = +70°C)
A
SO (derate 8.70mW/°C above +70°C)........................696mW
Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
MAX79_C_ _ ......................................................0°C to +70°C
MAX79_E_ _....................................................-40°C to +85°C
MAX79_MJE .................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 15V, GND = PGND = 0V, I
T
A
= I = 0A, T = 0°C to + 70°C for MAX79_C, T = 0°C to + 85°C for MAX79_E,
A A
REF
VL
= -55°C to +125°C for MAX79_M, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+3.3V AND +5V STEP-DOWN CONTROLLERS
MAX79_C
MAX79_E/M
4.5
5.0
30
30
Input Supply Range
V
V
V
0mV < (CSH-CSL) < 80mV, FB = VL, 6V < V+ < 30V,
includes line and load regulation
5V Output Voltage (CSL)
3.3V Output Voltage (CSL)
4.85
3.20
5.10
3.35
5.25
3.46
6/MAX79
0mV < (CSH-CSL) < 80mV, FB = 0V, 4.5V < V+ < 30V,
includes line and load regulation
Nominal Adjustable Output
Voltage Range
External resistor divider
REF
2.43
6
V
V
Feedback Voltage
Load Regulation
Line Regulation
(CSH-CSL) = 0V
2.505
2.5
2.57
0mV < (CSH-CSL) < 80mV
25mV < (CSH-CSL) < 80mV
6V < V+ < 30V
%
1.5
0.04
100
-100
4.0
0.06
120
-160
6.5
%/V
mV
CSH-CSL, positive
80
-50
2.5
2.0
Current-Limit Voltage
CSH-CSL, negative
SS Source Current
µA
SS Fault Sink Current
mA
FLYBACK/PWM CONTROLLER
Falling edge, hysteresis = 15mV (MAX796)
Falling edge, hysteresis = 20mV (MAX799)
2.45
2.505
0
2.55
0.05
SECFB Regulation Setpoint
V
-0.05
INTERNAL REGULATOR AND REFERENCE
VL Output Voltage
SHDN = 2V, 0mA < I < 25mA, 5.5V < V+ < 30V
4.7
3.8
4.2
5.3
4.1
4.7
V
V
V
VL
VL Fault Lockout Voltage
VL/CSL Switchover Voltage
Rising edge, hysteresis = 15mV
Rising edge, hysteresis = 25mV
2
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6/MAX79
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, GND = PGND = 0V, I
T
A
= I
= 0A, T = 0°C to + 70°C for MAX79_C, T = 0°C to + 85°C for MAX79_E,
A A
REF
VL
= -55°C to +125°C for MAX79_M, unless otherwise noted.)
PARAMETER
Reference Output Voltage
CONDITIONS
MIN
2.46
2.45
1.8
TYP
MAX
2.54
2.55
2.3
50
1
UNITS
MAX79_C
2.505
No external load (Note 1)
V
MAX79_E/M
Reference Fault Lockout Voltage Falling edge
Reference Load Regulation 0µA < I < 100µA
CSL Shutdown Leakage Current SHDN = 0V, CSL = 6V, V+ = 0V or 30V, VL = 0V
V
mV
µA
REF
0.1
1
MAX79_C
3
SHDN = 0V, V+ = 30V,
CSL = 0V or 6V
V+ Shutdown Current
µA
µA
MAX79_E/M
MAX79_C
1
5
1
3
FB = CSH = CSL = 6V,
VL switched over to CSL
V+ Off-State Leakage Current
MAX79_E/M
1
5
Dropout Power Consumption
Quiescent Power Consumption
V+ = 4V, CSL = 0V (Note 2)
CSH = CSL = 6V
4
8
mW
mW
4.8
6.6
OSCILLATOR AND INPUTS/OUTPUTS
SYNC = REF
270
125
200
200
300
150
330
175
Oscillator Frequency
kHz
SYNC = 0V or 5V
SYNC High Pulse Width
SYNC Low Pulse Width
SYNC Rise/Fall Time
Oscillator Sync Range
ns
ns
Guaranteed by design
200
340
ns
190
89
kHz
SYNC = REF
SYNC = 0V or 5V
SYNC
91
96
Maximum Duty Cycle
Input High Voltage
Input Low Voltage
%
V
V
93
VL - 0.5
2.0
SHDN, SKIP
SYNC
0.8
0.5
SHDN, SKIP
SHDN, 0V or 30V
SECFB, 0V or 4V
SYNC, SKIP
2.0
0.1
µA
Input Current
1.0
CSH, CSL, CSH = CSL = 6V, device not shut down
FB, FB = REF
50
±100
nA
A
DL Sink/Source Current
DH Sink/Source Current
DL On-Resistance
DL forced to 2V
1
1
DH forced to 2V, BST-LX = 4.5V
High or low
A
7
7
Ω
DH On-Resistance
High or low, BST-LX = 4.5V
Ω
Note 1: Since the reference uses VL as its supply, V+ line-regulation error is insignificant.
Note 2: At very low input voltages, quiescent supply current may increase due to excess PNP base current in the VL linear
regulator. This occurs only if V+ falls below the preset VL regulation point (5V nominal). See the Quiescent Supply Current
vs. Supply Voltage graph in the Typical Operating Characteristics.
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ELECTRICAL CHARACTERISTICS (continued)
(V+ = 15V, GND = PGND = 0V, I = I
= 0A, T = -40°C to +85°C for MAX79_E, unless otherwise noted.) (Note 3)
A
VL REF
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+3.3V and +5V STEP-DOWN CONTROLLERS
Input Supply Range
5.0
30
V
V
0mV < (CSH - CSL) < 80mV, FB = VL, 6V < V+ < 30V,
includes line and load regulation
5V Output Voltage (CSL)
3.3V Output Voltage (CSL)
4.70
5.10
3.35
5.40
0mV < (CSH - CSL) < 80mV, FB = VL, 4.5V < V+ < 30V,
includes line and load regulation
3.10
3.56
6.0
V
V
Nominal Adjustable Output
Voltage Range
External resistor divider
REF
2.40
Feedback Voltage
Line Regulation
(CSH-CSL) = 0V
6V < V+ < 30V
2.60
0.06
130
V
0.04
-100
%/V
CSH - CSL, positive
CSH - CSL, negative
70
Current-Limit Voltage
mV
V
-40
-160
FLYBACK/PWM CONTROLLER
SECFB Regulation Setpoint
Falling edge, hysteresis = 15mV (MAX796)
Falling edge, hysteresis = 20mV (MAX799)
2.40
2.60
0.08
-0.08
INTERNAL REGULATOR AND REFERENCE
VL Output Voltage
4.7
3.75
4.2
5.3
4.05
4.7
2.57
50
V
V
SHDN = 2V, 0mA < I < 25mA, 5.5V < V+ < 30V
VL
6/MAX79
VL Fault Lockout Voltage
VL/CSL Switchover Voltage
Reference Output Voltage
Reference Load Regulation
V+ Shutdown Current
Rising edge, hysteresis = 15mV
Rising edge, hysteresis = 25mV
No external load (Note 1)
V
2.43
2.505
V
0µA < I
< 100µA
mV
µA
µA
mW
REF
1
1
10
SHDN = 0V, V+ = 30V, CSL = 0V or 6V
V+ Off-State Leakage Current
Quiescent Power Consumption
FB = CSH = CSL = 6V, VL switched over to CSL
10
4.8
8.4
OSCILLATOR AND INPUTS/OUTPUTS
SYNC = REF
250
120
250
250
210
89
300
150
350
180
Oscillator Frequency
kHz
SYNC = 0V or 5V
SYNC High Pulse Width
SYNC Low Pulse Width
Oscillator Sync Range
ns
ns
320
kHz
SYNC = REF
91
96
Maximum Duty Cycle
%
SYNC = 0V or 5V
High or low
93
DL On-Resistance
DH On-Resistance
7
7
Ω
Ω
High or low, BST - LX = 4.5V
Note 3: All -40°C to +85°C specifications above are guaranteed by design.
4
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6/MAX79
__________________________________________________Typ ic a l Op e ra t in g Circ u it s
INPUT
4.5V TO 30V
V+
SHDN
VL
MAX797
DH
+3.3V
OUTPUT
BST
SS
LX
DL
REF
PGND
SYNC
GND
CSH
CSL
SKIP
FB
INPUT
6V TO 30V
V+
SECFB
SHDN
+12V
OUTPUT
FB
VL
MAX796
DH
+5V
OUTPUT
BST
LX
DL
PGND
SS
REF
GND
CSH
CSL
SYNC
_______________________________________________________________________________________
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_____________________________________Typ ic a l Op e ra t in g Circ u it s (c o n t in u e d )
FROM
REF
INPUT 6V TO 30V
V+
SECFB
FB
SHDN
VL
–5V
OUTPUT
MAX799
DH
BST
+5V
OUTPUT
LX
DL
PGND
SS
REF
CSH
CSL
GND
SYNC
6/MAX79
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs.
LOAD CURRENT, 5V/3A CIRCUIT
100
EFFICIENCY vs.
LOAD CURRENT, 3.3V/3A CIRCUIT
EFFICIENCY vs.
LOAD CURRENT, 3.3V/10A CIRCUIT
100
100
90
80
70
60
50
40
V
IN
= 6V
V
IN
= 5V
SKIP = LOW
90
80
70
60
90
80
70
60
V = 12V
IN
V
= 30V
IN
SKIP = HIGH
V
= 30V
IN
STANDARD MAX797 3.3V/10A
CIRCUIT, FIGURE 1
f = 300kHz
STANDARD MAX797 5V/3A
CIRCUIT, FIGURE 1
f = 300kHz
STANDARD MAX797 3.3V/3A
CIRCUIT, FIGURE 1
f = 300kHz
V
IN
= 5V
50
50
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
6
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6/MAX79
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
QUIESCENT SUPPLY CURRENT
vs. SUPPLY VOLTAGE,
QUIESCENT SUPPLY CURRENT
vs. SUPPLY VOLTAGE,
QUIESCENT SUPPLY CURRENT vs.
3.3V/3A CIRCUIT IN IDLE MODE
SUPPLY VOLTAGE, LOW-NOISE MODE
5V/3A CIRCUIT IN IDLE MODE
16m
30
20
10
0
1400
1200
1000
800
15m
14m
SWITCHING
STANDARD MAX797 APPLICATION
CONFIGURED FOR 5V
SKIP = LOW
f = 300kHz
f = 150kHz
800µ
600µ
400µ
SYNC = REF
600
NOT SWITCHING
(FB FORCED TO 3.5V)
400
STANDARD MAX797 3.3V/3A
CIRCUIT, FIGURE 1
SKIP = LOW
STANDARD MAX797 3.3V/3A
CIRCUIT, FIGURE 1
SKIP = HIGH
200
0
200µ
SYNC = REF
0
0
4
8
12 16 20 24 28 32
0
4
8
12 16 20 24 28 32
0
4
8
12 16 20 24 28 32
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DROPOUT VOLTAGE vs.
LOAD CURRENT
REF LOAD-REGULATION ERROR
vs. LOAD CURRENT
1.6
1.4
800
700
600
500
20
15
1.2
1.0
0.8
0.6
0.4
f = 300kHz
400
300
200
100
10
5
DEVICE CURRENT ONLY
SHDN = LOW
f = 150kHz
STANDARD MAX797 APPLICATION
CONFIGURED FOR 5V
0.2
0
V
OUT
> 4.8V
0
0
0.01
0.1
1
10
1
10
100
1000
0
4
8
12 16 20 24 28 32
LOAD CURRENT (A)
REF LOAD CURRENT (µA)
SUPPLY VOLTAGE (V)
MAX796
SWITCHING FREQUENCY vs.
LOAD CURRENT
VL LOAD-REGULATION ERROR
vs. LOAD CURRENT
MAXIMUM SECONDARY CURRENT
vs. SUPPLY VOLTAGE, 5V/15V CIRCUIT
500
1000
450
400
350
300
250
200
150
100
50
I
(MAIN) = 0A
OUT
SYNC = REF (300kHz)
SKIP = LOW
400
300
100
10
1
+5V, V = 7.5V
IN
I
(MAIN) = 3A
OUT
+5V, V = 30V
IN
200
100
0
+3.3V, V = 7.5V
IN
CIRCUIT OF FIGURE 11
TRANSFORMER = TTI5870
V
> 12.75V
SEC
0
0.1
100µ
1m
10m
100m
1
0
4
8 12 16 20 24 28 32
SUPPLY VOLTAGE (V)
0
20
40
60
80
LOAD CURRENT (A)
VL LOAD CURRENT (mA)
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____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(T = +25°C, unless otherwise noted.)
A
MAX796
MAX799
MAXIMUM SECONDARY CURRENT vs.
SUPPLY VOLTAGE, 3.3V/5V CIRCUIT
MAXIMUM SECONDARY CURRENT
vs. SUPPLY VOLTAGE, ±5V CIRCUIT
1050
900
750
600
450
300
800
700
I
(MAIN) = 2A
I
(MAIN) = 0A
OUT
OUT
600
500
400
300
200
I
(MAIN) = 0A
OUT
I
(MAIN) = 1A
OUT
CIRCUIT OF FIGURE 13
TRANSFORMER = TTI5926
CIRCUIT OF FIGURE 12
TRANSFORMER = TDK 1.5:1
V
SEC
≤ -5.1V
150
0
100
0
V
≥ 4.8V
SEC
0
3
6
9
12 15 18 21 24
0
4
8
12 16 20 24 28 32
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
PULSE-WIDTH-MODULATION MODE WAVEFORMS
IDLE-MODE WAVEFORMS
X
+5V OUTPUT
50mV/div
LX VOLTAGE
10V/div
2V/div
+5V OUTPUT
VOLTAGE
50mV/div
500ns/div
200µs/div
I
= 1A, V = 16V,
IN
I
= 100mA, V = 10V,
IN
LOAD
LOAD
CIRCUIT OF FIGURE 1
CIRCUIT OF FIGURE 1
+5V LOAD-TRANSIENT RESPONSE
3A
LOAD CURRENT
0A
+5V OUTPUT
50mV/div
200µs/div
V
IN
= 15V, CIRCUIT OF FIGURE 1
8
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______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1
SS
Soft-Start timing capacitor connection. Ramp time to full current limit is approximately 1ms/nF.
Secondary winding Feedback input. Normally connected to a resistor divider from an auxiliary output.
Don’t leave SECFB unconnected.
SECFB
(MAX796/
MAX799)
•
MAX796: SECFB regulates at VSECFB = 2.505V. Tie to VL if not used.
•
MAX799: SECFB regulates at VSECFB = 0V. Tie to a negative voltage through a high-value current-limit-
2
ing resistor (I
= 100µA) if not used.
MAX
Disables pulse-skipping mode when high. Connect to GND for normal use. Don’t leave SKIP unconnected.
With SKIP grounded, the device will automatically change from pulse-skipping operation to full PWM opera-
tion when the load current exceeds approximately 30% of maximum. (See Table 3.)
SKIP
(MAX797)
3
4
REF
Reference voltage output. Bypass to GND with 0.33µF minimum.
Low-noise analog Ground and feedback reference point.
GND
Oscillator Synchronization and frequency select. Tie to GND or VL for 150kHz operation; tie to REF for
300kHz operation. A high-to-low transition begins a new cycle. Drive SYNC with 0V to 5V logic levels (see the
5
6
SYNC
SHDN
Electrical Characteristics table for V and V specifications). SYNC capture range is 190kHz to 340kHz
IH
IL
guaranteed.
Shutdown control input, active low. Logic threshold is set at approximately 1V (V of an internal N-channel
TH
MOSFET). Tie SHDN to V+ for automatic start-up.
Feedback input. Regulates at FB = REF (approximately 2.505V) in adjustable mode. FB is a Dual-ModeTM
input that also selects the fixed output voltage settings as follows:
•
•
•
Connect to GND for 3.3V operation.
Connect to VL for 5V operation.
Connect FB to a resistor divider for adjustable mode. FB can be driven with +5V rail-to-rail logic in order to
change the output voltage under system control.
7
FB
8
9
CSH
CSL
Current-Sense input, High side. Current-limit level is 100mV referred to CSL.
Current-Sense input, Low side. Also serves as the feedback input in fixed-output modes.
Battery voltage input (4.5V to 30V). Bypass V+ to PGND close to the IC with a 0.1µF capacitor. Connects to a
linear regulator that powers VL.
10
11
V+
VL
5V Internal linear-regulator output. VL is also the supply voltage rail for the chip. VL is switched to the output
voltage via CSL (V
> 4.5V) for automatic bootstrapping. Bypass to GND with 4.7µF. VL can
CSL
supply up to 5mA for external loads.
12
13
14
15
PGND
DL
Power Ground.
Low-side gate-drive output. Normally drives the synchronous-rectifier MOSFET. Swings 0V to VL.
Boost capacitor connection for high-side gate drive (0.1µF).
BST
LX
Switching node (inductor) connection. Can swing 2V below ground without hazard.
High-side gate-drive output. Normally drives the main buck switch. DH is a floating driver output that swings
from LX to BST, riding on the LX switching-node voltage.
16
DH
Dual Mode is a trademark of Maxim Integrated Products.
_______________________________________________________________________________________
9
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If the 3A or 5A circuit must be guaranteed to withstand
______S t a n d a rd Ap p lic a t io n Circ u it
a continuous output short circuit indefinitely, see the
s e c tion MOSFET Switc he s und e r Se le c ting Othe r
Components. Don’t change the frequency of these cir-
cuits without first recalculating component values (par-
ticularly inductance value at maximum battery voltage).
It is easy to adapt the basic MAX797 single-output 3.3V
buc k c onve rte r (Figure 1) to me e t a wide ra nge of
applications with inputs up to 28V (limited by choice of
external MOSFET). Simply substitute the appropriate
components from Table 1. These circuits represent a
good set of tradeoffs between cost, size, and efficiency
while staying within the worst-case specification limits
for stress-related parameters such as capacitor ripple
current. Each of these circuits is rated for a continuous
_______________De t a ile d De s c rip t io n
The MAX796 is a BiCMOS, switch-mode power-supply
controller designed primarily for buck-topology regula-
tors in battery-powered applications where high effi-
ciency and low quiescent supply current are critical.
The MAX796 also works well in other topologies such
as boost, inverting, and CLK due to the flexibility of its
floating high-speed gate driver. Light-load efficiency is
enhanced by automatic idle-mode operation—a vari-
a b le -fre q ue nc y p uls e -s kip p ing mod e tha t re d uc e s
load current at T = +85°C, as shown. The 1A, 2A and
A
10A applications can withstand a continuous output
short-circuit to ground. The 3A and 5A applications can
withstand a short circuit of many seconds duration, but
the synchronous-rectifier MOSFET overheats, exceed-
ing the manufacturer’s ratings for junction temperature
by 50°C or more.
INPUT
C1
C7
6/MAX79
0.1µF
+5V AT
5mA
10
11
VL
D2
CMPSH-3
C4
4.7µF
V+
6
2
16
14
DH
Q1
ON/OFF
CONTROL
SHDN
BST
C3
0.1µF
+3.3V
OUTPUT
15
13
L1
LX
MAX797
LOW-NOISE
CONTROL
SKIP
SS
R1
C2
DL
Q2
D1
GND
OUT
12
8
PGND
1
CSH
CSL
9
C6
0.01µF
(OPTIONAL)
4
3
GND
REF
FB
SYNC
C5
0.33µF
7
5
REF OUTPUT
NOTE: KEEP CURRENT-SENSE
LINES SHORT AND CLOSE
TOGETHER. SEE FIG. 10
+2.505V AT 100µA
J1
150kHz/300kHz
JUMPER
Figure 1. Standard 3.3V Application Circuit
10 ______________________________________________________________________________________
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6/MAX79
Table 1. Component Selection for Standard 3.3V Applications
LOAD CURRENT
COMPONENT
1A
4.75V to 18V
PDA
2A
4.75V to 18V
Sub-Notebook
300kHz
3A
4A
4.75V to 24V
High-End Notebook
300kHz
10A
4.5V to 6V
Input Range
Application
Frequency
4.75V to 28V
Notebook
300kHz
Desktop 5V-to-3V
300kHz
150kHz
Motorola 1/2
MMDF3N03HD or 1/2 MMSF5N03HD or
Si9936
Motorola
Motorola
MTD20N03HDL
DPAK
Motorola
Q1 High-Side
MOSFET
International Rectifier
1/2 IRF7101
MTD75N03HDL
2
Si9410
D PAK
Motorola 1/2
MMDF3N03HD or 1/2 MMSF5N03HD or
Si9936
Motorola
Motorola
MTD20N03HDL
DPAK
Motorola
Q2 Low-Side
MOSFET
International Rectifier
1/2 IRF7101
MTD75N03HDL
2
Si9410
D PAK
2 x 220µF, 10V
Sanyo OS-CON
10SA220M
C1 Input
Capacitor
22µF, 35V AVX TPS 2 x 22µF, 35V AVX
or Sprague 595D
2 x 22µF, 35V AVX
TPS or Sprague 595D TPS or Sprague 595D TPS or Sprague 595D
4 x 22µF, 35V AVX
4 x 220µF, 10V
Sanyo OS-CON
10SA220M
C2 Output
Capacitor
150µF, 10V AVX TPS 150µF, 10V AVX TPS
220µF, 10V AVX TPS 3 x 220µF, 10V AVX
or Sprague 595D
or Sprague 595D
or Sprague 595D
TPS or Sprague 595D
1N5817 NIEC
EC10QS02L or
1N5819 NIEC
EC10QS03 or
1N5821 NIEC
NSQ03A04 or
1N5820 NIEC
NSQ03A02, or
1N5817 Motorola
MBR0502L SOD-89
D1 Rectifier
R1 Resistor
L1 Inductor
Motorola MBRS130T3 Motorola MBRS130T3 Motorola MBRS340T3 Motorola MBRS340T3
3 x 0.02Ω IRC
LR2010-01-R020
(3 in parallel)
0.062Ω IRC
LR2010-01-R062
0.039Ω IRC
LR2010-01-R039
0.025Ω IRC
LR2010-01-R025
0.015Ω IRC
LR2010-01-015
47µH, 1.2A Ferrite or
Kool-Mu
Sumida CD75-470
1.5µH, 11A, 3.5mΩ
Coiltronics
CTX03-12357-1
33µH, 2.2A Ferrite
Dale LPE6562-330MB Sumida CDRH125
10µH, 3A Ferrite
4.7µH, 5.5A Ferrite
Coilcraft DO3316-472
Table 2. Component Suppliers
FACTORY FAX
[Country Code]
FACTORY FAX
[Country Code]
MANUFACTURER
USA PHONE
MANUFACTURER
USA PHONE
AVX
(803) 946-0690 [1] 803-626-3123
(516) 435-1110 [1] 516-435-1824
(847) 639-6400 [1] 847-639-1469
(561) 241-7876 [1] 561-241-9339
(605) 668-4131 [1] 605-665-1627
(310) 322-3331 [1] 310-322-3332
(512) 992-7900 [1] 512-992-3377
(864) 963-6300 [1] 864-963-6521
(714) 969-2491 [1] 714-960-6492
(602) 303-5454 [1] 602-994-6430
(814) 237-1431
(800) 831-9172
Murata-Erie
[1] 814-238-0490
Central Semiconductor
Coilcraft
NIEC
(805) 867-2555* [81] 3-3494-7414
(619) 661-6835 [81] 7-2070-1174
Coiltronics
Dale
Sanyo
(408) 988-8000
[1] 408-970-3950
(800) 554-5565
Siliconix
International Rectifier
IRC
Sprague
Sumida
TDK
(603) 224-1961 [1] 603-224-1430
(847) 956-0666 [81] 3-3607-5144
(847) 390-4461 {1} 847-390-4405
Kemet
Matsuo
Motorola
Transpower Technologies (702) 831-0140 [1] 702-831-3521
* Distributor
losses due to MOSFET gate charge. The step-down
p owe r-s witc hing c irc uit c ons is ts of two N-c ha nne l
MOSFETs, a rectifier, and an LC output filter. The out-
put voltage is the average of the AC voltage at the
switching node, which is adjusted and regulated by
changing the duty cycle of the MOSFET switches. The
gate-drive signal to the N-channel high-side MOSFET
must exceed the battery voltage and is provided by a
flying capacitor boost circuit that uses a 100nF capaci-
tor connected to BST.
The MAX796 contains nine major circuit blocks, which
are shown in Figure 2.
______________________________________________________________________________________ 11
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BATTERY VOLTAGE
TO
V+
CSL
+5V LINEAR
REGULATOR
OUT
VL
+5V AT 5mA
4.5V
AUXILIARY
OUTPUT
SHDN
BST
SECFB
DH
LX
PWM
LOGIC
MAIN
OUTPUT
DL
+2.505V
REF
PGND
PWM
COMPARATOR
CSH
CSL
+2.505V
AT 100µA
6/MAX79
REF
LPF
GND
3.3V FB
5V FB
60kHz
ON/OFF
SHDN
SS
ADJ FB
FB
4V
MAX796
1V
SYNC
Figure 2. MAX796 Block Diagram
12 ______________________________________________________________________________________
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6/MAX79
PWM Controller Blocks:
Table 3. Operating-Mode Truth Table
• Multi-Input PWM Comparator
• Current-Sense Circuit
• PWM Logic Block
• Dual-Mode Internal Feedback Mux
• Gate-Driver Outputs
• Secondary Feedback Comparator
LOAD
CURRENT
MODE
NAME
SHDN SKIP
DESCRIPTION
All circuit blocks
Low
X
X
Shutdown turned off; supply
current = 1µA typ
Pulse-skipping;
supply current =
Bias Generator Blocks:
Low,
<10%
High
Low
Idle
700µA typ at V
=
IN
• +5V Linear Regulator
• Automatic Bootstrap Switchover Circuit
• +2.505V Reference
10V; discontinuous
inductor current
Pulse-skipping;
continuous inductor
current
Medium,
<30%
These internal IC blocks aren’t powered directly from
the battery. Instead, a +5V linear regulator steps down
the battery voltage to supply both the IC internal rail (VL
pin) a s we ll a s the ga te d rive rs. The sync hronous-
switch gate driver is directly powered from +5V VL,
while the high-side-switch gate driver is indirectly pow-
ered from VL via an external diode-capacitor boost cir-
cuit. An automatic bootstrap circuit turns off the +5V
linear regulator and powers the IC from its output volt-
age if the output is above 4.5V.
High
High
Low
Low
Idle
Constant-frequency
PWM; continuous
inductor current
High,
>30%
PWM
Constant-frequency
PWM regardless of
load; continuous
inductor current
even at no load
Low Noise*
(PWM)
High
High
X
P WM Co n t ro lle r Blo c k
The he a rt of the c urre nt-mod e PWM c ontrolle r is a
multi-input open-loop comparator that sums three sig-
nals: output voltage error signal with respect to the ref-
e re nc e volta g e , c urre nt-s e ns e s ig na l, a nd s lop e
compensation ramp (Figure 3). The PWM controller is a
direct summing type, lacking a traditional error amplifi-
er and the phase shift associated with it. This direct-
s umming c onfig ura tion a p p roa c he s the id e a l of
cycle-by-cycle control over the output voltage.
* MAX796/MAX799 have no SKIP pin and therefore can’t go
into low-noise mode.
X = Don’t Care
beginning of each cycle, unless the feedback signal
falls below the reference voltage level.
When in PWM mode, the controller operates as a fixed-
frequency current-mode controller where the duty ratio
is set by the input/output voltage ratio. The current-
mode feedback system regulates the peak inductor
current as a function of the output voltage error signal.
Since the average inductor current is nearly the same
as the peak current, the circuit acts as a switch-mode
transconductance amplifier and pushes the second
output LC filter pole, normally found in a duty-factor-
controlled (voltage-mode) PWM, to a higher frequency.
To preserve inner-loop stability and eliminate regenera-
tive inductor current “staircasing,” a slope-compensa-
tion ramp is summed into the main PWM comparator to
reduce the apparent duty factor to less than 50%.
Under heavy loads, the controller operates in full PWM
mode. Each pulse from the oscillator sets the main
PWM latch that turns on the high-side switch for a peri-
od d e te rmine d b y the d uty fa c tor (a p p roxima te ly
V
/V ). As the high-switch turns off, the synchro-
OUT IN
nous rectifier latch is set. 60ns later the low-side switch
turns on, and stays on until the beginning of the next
clock cycle (in continuous mode) or until the inductor
current crosses zero (in discontinuous mode). Under
fault conditions where the inductor current exceeds the
100mV c urre nt-limit thre s hold , the hig h-s id e la tc h
resets and the high-side switch turns off.
The relative gains of the voltage- and current-sense
inputs are weighted by the values of current sources
that bias three differential input stages in the main PWM
comparator (Figure 4). The relative gain of the voltage
comparator to the current comparator is internally fixed
at K = 2:1. The resulting loop gain (which is relatively
low) determines the 2.5% typical load regulation error.
The low loop -g a in va lue he lp s re d uc e outp ut filte r
c a p a c itor s ize a nd c os t b y s hifting the unity-g a in
crossover to a lower frequency.
At light loads (SKIP = low), the inductor current fails to
exceed the 30mV threshold set by the minimum-current
comparator. When this occurs, the controller goes into
idle mode, skipping most of the oscillator pulses in
order to reduce the switching frequency and cut back
gate-charge losses. The oscillator is effectively gated
off at light loads because the minimum-current com-
parator immediately resets the high-side latch at the
______________________________________________________________________________________ 13
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CSH
CSL
1X
REF
FROM
FEEDBACK
DIVIDER
MAIN PWM
COMPARATOR
BST
DH
LX
R
Q
S
LEVEL
SHIFT
SLOPE COMP
OSC
30mV
SKIP
(MAX797
ONLY)
VL
6/MAX79
4µA
CURRENT
LIMIT
SHOOT-
THROUGH
CONTROL
24R
1R
SS
2.5V
N
SHDN
SYNCHRONOUS
RECTIFIER CONTROL
VL
DL
R
Q
LEVEL
SHIFT
–100mV
S
PGND
REF (MAX796)
GND (MAX799)
1µs
NOTE 1: COMPARATOR INPUT POLARITIES
ARE REVERSED FOR THE MAX799.
SINGLE-SHOT
SECFB
NOTE 1
MAX796, MAX799 ONLY
Figure 3. PWM Controller Detailed Block Diagram
14 ______________________________________________________________________________________
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6/MAX79
VL
R1
R2
TO PWM
LOGIC
UNCOMPENSATED
HIGH-SPEED
FB
LEVEL TRANSLATOR
AND BUFFER
OUTPUT DRIVER
I1
I2
I3
REF
CSH
CSL
SLOPE COMPENSATION
Figure 4. Main PWM Comparator Block Diagram
The output filter capacitor C2 sets a dominant pole in
the feedback loop. This pole must roll off the loop gain
to unity b e fore the ze ro introd uc e d b y the outp ut
capacitor’s parasitic resistance (ESR) is encountered
(see Design Procedure section). A 60kHz pole-zero
cancellation filter provides additional rolloff above the
unity-gain crossover. This internal 60kHz lowpass com-
pensation filter cancels the zero due to the filter capaci-
tor’s ESR. The 60kHz filter is included in the loop in
both fixed- and adjustable-output modes.
In t e rn a l VL a n d REF S u p p lie s
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, logic, reference, and other
blocks within the MAX796. This +5V low-dropout linear
regulator can supply up to 5mA for external loads, with
a reserve of 20mA for gate-drive power. Bypass VL to
GND with 4.7µF. Important: VL must not be allowed to
e xc e e d 6V. Me a s ure VL with the ma in outp ut fully
loaded. If VL is being pumped up above 5.5V, the
probable cause is either excessive boost-diode capaci-
tance or excessive ripple at V+. Use only small-signal
diodes for D2 (1N4148 preferred) and bypass V+ to
PGND with 0.1µF directly at the package pins.
S yn c h ro n o u s -Re c t ifie r Drive r (DL P in )
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky diode with
a low-resistance MOSFET switch. The synchronous rec-
tifier also ensures proper start-up of the boost-gate driv-
e r c irc uit. If you mus t omit the s ync hronous p owe r
MOSFET for cost or other reasons, replace it with a
small-signal MOSFET such as a 2N7002.
The 2.505V reference (REF) is accurate to ±1.6% over
temperature, making REF useful as a precision system
reference. Bypass REF to GND with 0.33µF minimum.
REF can supply up to 1mA for external loads. However,
if tight-accuracy specs for either VOUT or REF are
essential, avoid loading REF with more than 100µA.
Loading REF reduces the main output voltage slightly,
a c c ord ing to the re fe re nc e -volta g e loa d re g ula tion
error. In MAX799 applications, ensure that the SECFB
divider doesn’t load REF heavily.
If the c irc uit is op e ra ting in c ontinuous-c onduc tion
mode, the DL drive waveform is simply the complement
of the DH high-side drive waveform (with controlled
d e a d time to p re ve nt c ros s -c ond uc tion or “s hoot-
through”). In discontinuous (light-load) mode, the syn-
chronous switch is turned off as the inductor current
falls through zero. The synchronous rectifier works
under all operating conditions, including idle mode.
The synchronous-switch timing is further controlled by
the secondary feedback (SECFB) signal in order to
imp rove multip le -outp ut c ros s -re g ula tion (s e e
Secondary Feedback-Regulation Loop section).
When the main output voltage is above 4.5V, an internal P-
channel MOSFET switch connects CSL to VL while simul-
taneously shutting down the VL linear regulator. This
action bootstraps the IC, powering the internal circuitry
from the output voltage, rather than through a linear regu-
lator from the battery. Bootstrapping reduces power dissi-
pation caused by gate-charge and quiescent losses by
providing that power from a 90%-efficient switch-mode
source, rather than from a 50%-efficient linear regulator.
______________________________________________________________________________________ 15
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S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
It’s often possible to achieve a bootstrap-like effect, even
for circuits that are set to V
< 4.5V, by powering VL
OUT
BATTERY
INPUT
+5V
VL SUPPLY
from an external-system +5V supply. To achieve this
pseudo-bootstrap, add a Schottky diode between the
external +5V source and VL, with the cathode to the VL
side. This circuit provides a 1% to 2% efficiency boost
and also extends the minimum battery input to less than
4V. The external source must be in the range of 4.8V to
6V. Another way to achieve a pseudo-bootstrap is to add
an extra flyback winding to the main inductor to generate
the +5V bootstrap source, as shown in the +3.3V/+5V
Dual-Output Application (Figure 12).
VL
MAX796
MAX797
MAX799
VL
BST
DH
LX
LEVEL
TRANSLATOR
Bo o s t Hig h -S id e
Ga t e -Drive r S u p p ly (BS T P in )
PWM
VL
Gate-drive voltage for the high-side N-channel switch is
generated by a flying-capacitor boost circuit as shown
in Figure 5. The capacitor is alternately charged from
the VL supply and placed in parallel with the high-side
MOSFET’s gate-source terminals.
DL
On start-up, the synchronous rectifier (low-side MOS-
FET) forces LX to 0V and charges the BST capacitor to
5V. On the second half-cycle, the PWM turns on the
hig h-s id e MOSFET b y c los ing a n inte rna l s witc h
between BST and DH. This provides the necessary
enhancement voltage to turn on the high-side switch,
an action that “boosts” the 5V gate-drive signal above
the battery voltage.
Figure 5. Boost Supply for Gate Drivers
6/MAX79
Os c illa t o r Fre q u e n c y a n d
S yn c h ro n iza t io n (S YNC P in )
The SYNC inp ut c ontrols the os c illa tor fre q ue nc y.
Connecting SYNC to GND or to VL selects 150kHz
operation; connecting SYNC to REF selects 300kHz.
SYNC can also be used to synchronize with an external
5V CMOS or TTL clock generator. SYNC has a guaran-
teed 190kHz to 340kHz capture range.
Ringing seen at the high-side MOSFET gate (DH) in
discontinuous-conduction mode (light loads) is a natur-
al operating condition, and is caused by the residual
energy in the tank circuit formed by the inductor and
stray capacitance at the switching node LX. The gate-
driver negative rail is referred to LX, so any ringing
there is directly coupled to the gate-drive output.
300kHz operation optimizes the application circuit for
component size and cost. 150kHz operation provides
inc re a s e d e ffic ie nc y a nd imp rove d loa d -tra ns ie nt
response at low input-output voltage differences (see
Low-Voltage Operation section).
Cu rre n t -Lim it in g a n d
Cu rre n t -S e n s e In p u t s (CS H a n d CS L)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor must be sized for
80mV/R1 to guarantee enough load capability, while
components must be designed to withstand continuous
current stresses of 120mV/R1.
Lo w -No is e Mo d e (S KIP P in )
The low-noise mode (SKIP = high) is useful for minimiz-
ing RF and audio interference in noise-sensitive appli-
cations such as Soundblaster™ hi-fi audio-equipped
systems, cellular phones, RF communicating comput-
ers, and electromagnetic pen-entry systems. See the
summary of operating modes in Table 3. SKIP can be
driven from an external logic signal.
The MAX797 can reduce interference due to switching
nois e b y e ns uring a c ons ta nt s witc hing fre q ue nc y
regardless of load and line conditions, thus concentrat-
ing the emissions at a known frequency outside the
system audio or IF bands. Choose an oscillator fre-
For breadboarding purposes or very high-current appli-
cations, it may be useful to wire the current-sense inputs
with a twisted pair rather than PC traces. This twisted
pair needn’t be anything special, perhaps two pieces of
wire-wrap wire twisted together.
Soundblaster is a trademark of Creative Labs.
16 ______________________________________________________________________________________
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6/MAX79
quency where harmonics of the switching frequency
Remote sensing of the output voltage, while not possi-
ble in fixed-output mode due to the combined nature of
the voltage- and current-sense input (CSL), is easy to
achieve in adjustable mode by using the top of the
external resistor divider as the remote sense point.
Fixed-output accuracy is guaranteed to be ±4% over
all conditions. In special circumstances, it may be nec-
essary to improve upon this output accuracy. The High-
Accuracy Adjustable-Output Application (Figure 18)
provides ±2.5% accuracy by adding an integrator-type
error amplifier.
don’t overlap a sensitive frequency band. If necessary,
synchronize the oscillator to a tight-tolerance external
clock generator.
The low-noise mode (SKIP = high) forces two changes
upon the PWM controller. First, it ensures fixed-frequen-
cy operation by disabling the minimum-current com-
parator and ensuring that the PWM latch is set at the
beginning of each cycle, even if the output is in regula-
tion. Second, it ensures continuous inductor current
flow, a nd the re b y s up p re s s e s d is c ontinuous -mod e
inductor ringing by changing the reverse current-limit
detection threshold from zero to -100mV, allowing the
inductor current to reverse at very light loads.
The breakdown voltage rating of the current-sense
inputs (7V absolute maximum) determines the 6V maxi-
mum output adjustment range. To extend this output
range, add two matched resistor dividers and speed-
up capacitors to form a level translator, as shown in
Figure 8. Be sure to set these resistor ratios accurately
(using 0.1% resistors), to avoid adding excessive error
to the 100mV current-limit threshold.
In most applications, SKIP should be tied to GND in
order to minimize quiescent supply current. Supply cur-
rent with SKIP high is typically 10mA to 20mA, depend-
ing on e xte rna l MOSFET g a te c a p a c ita nc e a nd
switching losses.
Forced continuous conduction via SKIP can improve
cross regulation of transformer-coupled multiple-output
supplies. This second function of the SKIP pin pro-
duces a result that is similar to the method of adding
secondary regulation via the SECFB feedback pin, but
with muc h hig he r q uie s c e nt s up p ly c urre nt. Still,
improving cross regulation by enabling SKIP instead of
building in SECFB feedback can be useful in noise-
s e ns itive a p p lic a tions , s inc e SECFB a nd SKIP a re
mutually exclusive pins/functions in the MAX796 family.
S e c o n d a ry Fe e d b a c k -Re g u la t io n Lo o p
(S ECFB P in )
A flyback winding control loop regulates a secondary
wind ing outp ut (MAX796/MAX799 only), imp roving
cross-regulation when the primary is lightly loaded or
when there is a low input-output differential voltage. If
SECFB crosses its regulation threshold (VREF for the
Ad ju s t a b le -Ou t p u t Fe e d b a c k
(Du a l-Mo d e FB P in )
V+
REMOTE
SENSE
Adjusting the main output voltage with external resis-
tors is easy for any of the devices in the MAX796 family,
via the circuit of Figure 6. The nominal output voltage
(given by the formula in Figure 6) should be set approx-
imately 2% high in order to make up for the MAX796’s
-2.5% typ ic a l loa d -re gula tion e rror. For e xa mple , if
designing for a 3.0V output, use a resistor ratio that
results in a nominal output voltage of 3.06V. This slight
offs e tting g ive s the b e s t p os s ib le a c c ura c y.
Recommended normal values for R5 range from 5kΩ to
100kΩ. To achieve a 2.505V nominal output, simply
connect FB to CSL directly. To achieve output voltages
lowe r tha n 2.5V, use a n e xte rna l re fe re nc e -volta g e
DH
MAIN
OUTPUT
LINES
MAX796
MAX797
MAX799
DL
R4
CSH
CSL
FB
GND
R5
source higher than V , as shown in Figure 7. For best
accuracy, this second reference voltage should be
REF
R4
V
OUT
= V (1 + –––)
REF
R5
much higher than V
. Alternatively, an external op
REF
WHERE V (NOMINAL) = 2.505V
REF
amp could be used to gain-up REF in order to create
the second reference source. This scheme requires a
minimum load on the output in order to sink the R3/R4
divider current.
Figure 6. Adjusting the Main Output Voltage
______________________________________________________________________________________ 17
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
V+
VREF2 >>VREF
V+
(4.096V)
OUTPUT
(8V AS
SHOWN)
DH
MAX874
R5
R
SENSE
MAX796
MAX797
MAX799
R1
2.43k
R3
2.43k
DH
R4
MAIN
OUTPUT
DL
0.01µF
MAX796
MAX797
MAX799
0.01µF
CSH
CSL
FB
DL
CSH
R2
1.1k
R4
1.1k
GND
CSL
FB
R3
V
= V (1 + –––)
OUT
REF
R4
GND
DIVIDER IMPEDANCE ≤ 5kΩ
R4
- V )
V
OUT
= V - (V
REF2 REF (–––)
REF
(EACH LEG)
R5
Figure 8. Adjusting the Output Voltage to Greater than 6V
Figure 7. Output Voltage Less than 2.5V
MAX796), a 1µs one-shot is triggered that extends the
low-side switch’s on-time beyond the point where the
inductor current crosses zero (in discontinuous mode).
This causes the inductor (primary) current to reverse,
which in turn pulls current out of the output filter capacitor
and causes the flyback transformer to operate in the for-
ward mode. The low impedance presented by the trans-
former secondary in the forward mode dumps current into
the secondary output, charging up the secondary capac-
itor and bringing SECFB back into regulation. The SECFB
feedback loop does not improve secondary output accu-
racy in normal flyback mode, where the main (primary)
output is heavily loaded. In this mode, secondary output
accuracy is determined, as usual, by the secondary recti-
fier drop, turns ratio, and accuracy of the main output
voltage. So, a linear post-regulator may still be needed in
order to meet tight output accuracy specifications.
noise. In negative-output (MAX799) applications, the
resistor divider acts as a load on the internal reference,
which in turn can cause errors at the main output. Avoid
overloading REF (see the Reference Load-Regulation
Error vs. Load Current graph in the Typical Operating
Characteristics). 100kΩ is a good value for R3 in MAX799
circuits.
6/MAX79
S o ft -S t a rt Circ u it (S S )
Soft-start allows a gradual increase of the internal cur-
rent-limit level at start-up for the purpose of reducing
input surge currents, and perhaps for power-supply
sequencing. In shutdown mode, the soft-start circuit
holds the SS capacitor discharged to ground. When
SHDN goes high, a 4µA current source charges the SS
capacitor up to 3.2V. The resulting linear ramp wave-
form causes the internal current-limit level to increase
proportionally from 20mV to 100mV. The main output
capacitor thus charges up relatively slowly, depending
on the SS capacitor value. The exact time of the output
rise depends on output capacitance and load current
and is typically 1ms per nanofarad of soft-start capaci-
tance. With no SS capacitor connected, maximum cur-
rent limit is reached within 10µs.
The secondary output voltage-regulation point is deter-
mined by an external resistor divider at SECFB. For nega-
tive output voltages, the SECFB comparator is referenced
to GND (MAX799); for positive output voltages, SECFB
regulates at the 2.505V reference (MAX796). As a result,
output resistor divider connections and design equations
for the two d e vic e typ e s d iffe r s lig htly (Fig ure 9).
Ordinarily, the secondary regulation point is set 5% to
10% below the voltage normally produced by the flyback
effect. For example, if the output voltage as determined
by the turns ratio is +15V, the feedback resistor ratio
should be set to produce about +13.5V; otherwise, the
SECFB one-shot might be triggered unintentionally, caus-
ing an unnecessary increase in supply current and output
S h u t d o w n
Shutdown mode (SHDN = 0V) reduces the V+ supply
current to typically 1µA. In this mode, the reference and
VL are inactive. SHDN is a logic-level input, but it can
be safely driven to the full V+ range. Connect SHDN to
V+ for automatic start-up. Do not allow slow transitions
(slower than 0.02V/µs) on SHDN.
18 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
In d u c t o r Va lu e
_________________De s ig n P ro c e d u re
The e xa c t ind uc tor va lue is n’t c ritic a l a nd c a n b e
adjusted freely in order to make tradeoffs among size,
cost, and efficiency. Although lower inductor values will
minimize size and cost, they will also reduce efficiency
due to higher peak currents. To permit use of the physi-
cally smallest inductor, lower the inductance until the
circuit is operating at the border between continuous
and discontinuous modes. Reducing the inductor value
even further, below this crossover point, results in dis-
continuous-conduction operation even at full load. This
helps reduce output filter capacitance requirements but
c a us e s the c ore e ne rg y s tora g e re q uire me nts to
increase again. On the other hand, higher inductor val-
ues will increase efficiency, but at some point resistive
losses due to extra turns of wire will exceed the benefit
gained from lower AC current levels. Also, high induc-
tor values can affect load-transient response; see the
The five pre-designed standard application circuits
(Figure 1 and Table 1) contain ready-to-use solutions
for common applications. Use the following design pro-
cedure to optimize the basic schematic for different
voltage or current requirements. Before beginning a
design, firmly establish the following:
V
, the maximum input (battery) voltage. This
IN(MAX)
value should include the worst-case conditions, such
as no-load operation when a battery charger or AC
a d a p te r is c onne c te d b ut no b a tte ry is ins ta lle d .
V
must not exceed 30V. This 30V upper limit is
IN(MAX)
determined by the breakdown voltage of the BST float-
ing gate driver to GND (36V absolute maximum).
V
, the minimum input (battery) voltage. This
IN(MIN)
should be taken at full-load under the lowest battery
conditions. If V is less than 4.5V, a special circuit
IN(MIN)
V
SAG
equation in the Low-Voltage Operation section.
must be used to externally hold up VL above 4.8V. If
the minimum input-output difference is less than 1.5V,
the filter capacitance required to maintain good AC
load regulation increases.
The following equations are given for continuous-con-
duction operation since the MAX796 is mainly intended
for high-efficiency battery-powered applications. See
Appendix A in Maxim’s Battery Management and DC-
DC Converter Circuit Collection for crossover point and
discontinuous-mode equations. Discontinuous conduc-
tion doesn’t affect normal idle-mode operation.
0.33µF
REF
R3
R3
SECFB
SECFB
1-SHOT
1-SHOT
TRIG
TRIG
R2
R2
POSITIVE
NEGATIVE
SECONDARY
OUTPUT
V+
V+
2.505V REF
DH
SECONDARY
OUTPUT
DH
DL
MAIN
OUTPUT
MAIN
OUTPUT
MAX796
MAX799
DL
R2
+V = V (1 + –––)
R2
-V = -V (–––)
WHERE V (NOMINAL) = 2.505V
R3 = 100kΩ (RECOMMENDED)
TRIP
REF
REF
TRIP
REF
R3
R3
Figure 9. Secondary-Output Feedback Dividers, MAX796 vs. MAX799
______________________________________________________________________________________ 19
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
Thre e ke y ind uc tor p a ra me te rs mus t b e s p e c ifie d :
inductance value (L), peak current (I ), and DC
may be used in place of I
if the inductor value has
PEAK
been set for LIR = 0.3 or less (high inductor values)
and 300kHz operation is selected. Low-inductance
resistors, such as surface-mount metal-film resistors,
are preferred.
PEAK
resistance (R ). The following equation includes a
DC
constant LIR, which is the ratio of inductor peak-to-
peak AC current to DC load current. A higher value of
LIR allows smaller inductance, but results in higher
losses and ripple. A good compromise between size
and losses is found at a 30% ripple current to load cur-
rent ratio (LIR = 0.3), which corresponds to a peak
inductor current 1.15 times higher than the DC load
current.
80mV
R
= ————
SENSE
I
PEAK
In p u t Ca p a c it o r Va lu e
Place a small ceramic capacitor (0.1µF) between V+
and GND, close to the device. Also, connect a low-ESR
bulk capacitor directly to the drain of the high-side
MOSFET. Select the bulk input filter capacitor accord-
ing to input ripple-current requirements and voltage rat-
ing, rather than capacitor value. Electrolytic capacitors
that have low enough ESR to meet the ripple-current
re q uire me nt inva ria b ly ha ve more tha n a d e q ua te
capacitance values. Aluminum-electrolytic capacitors
such as Sanyo OS-CON or Nichicon PL are preferred
ove r ta nta lum typ e s , whic h c ould c a us e p owe r-up
surge-current failure, especially when connecting to
robust AC adapters or low-impedance batteries. RMS
input ripple current is determined by the input voltage
and load current, with the worst possible case occur-
V
(V
- V
)
OUT IN(MAX)
OUT
L = ———————————
x f x I x LIR
V
OUT
IN(MAX)
where: f = switching frequency, normally 150kHz or
300kHz
I
= maximum DC load current
OUT
LIR = ratio of AC to DC inductor current,
typically 0.3
The peak inductor current at full load is 1.15 x I
if
OUT
the above equation is used; otherwise, the peak current
can be calculated by:
V
(V
- V
)
OUT IN(MAX)
OUT
6/MAX79
I
= I
+ ———————————
PEAK
LOAD
ring at V = 2 x V
:
IN
OUT
2 x f x L x V
IN(MAX)
————————
√V (V - V
The inductor’s DC resistance is a key parameter for effi-
ciency performance and must be ruthlessly minimized,
)
OUT
OUT IN
I
= I
x ——————————
RMS
LOAD
V
IN
preferably to less than 25mΩ at I
= 3A. If a stan-
OUT
dard off-the-shelf inductor is not available, choose a
I
= I
/ 2 when V is 2 x V
RMS
LOAD IN OUT
2
2
core with an LI rating greater than L x I
and wind
PEAK
Ou t p u t Filt e r Ca p a c it o r Va lu e
it with the largest diameter wire that fits the winding
area. For 300kHz applications, ferrite core material is
strongly preferred; for 150kHz applications, Kool-mu
(a luminum a lloy) a nd e ve n p owd e re d iron c a n b e
acceptable. If light-load efficiency is unimportant (in
desktop 5V-to-3V applications, for example) then low-
p e rme a b ility iron-p owd e r c ore s , s uc h a s the
Micrometals type found in Pulse Engineering’s 2.1µH
PE-53680, may be acceptable even at 300kHz. For
high-current applications, shielded core geometries
(such as toroidal or pot core) help keep noise, EMI, and
switching-waveform jitter low.
The output filter capacitor values are generally deter-
mined by the ESR (effective series resistance) and volt-
age rating requirements rather than actual capacitance
requirements for loop stability. In other words, the low-
ESR electrolytic capacitor that meets the ESR require-
me nt us ua lly ha s more outp ut c a p a c ita nc e tha n is
required for AC stability. Use only specialized low-ESR
capacitors intended for switching-regulator applications,
such as AVX TPS, Sprague 595D, Sanyo OS-CON, or
Nichicon PL series. To ensure stability, the capacitor
must meet both minimum capacitance and maximum
ESR values as given in the following equations:
Cu rre n t -S e n s e Re s is t o r Va lu e
The current-sense resistor value is calculated accord-
ing to the worst-case-low current-limit threshold voltage
(from the Electrical Characteristics table) and the peak
inductor current. The continuous-mode peak inductor-
current calculations that follow are also useful for sizing
the switches and specifying the inductor-current satu-
V
(1 + V
/ V
)
REF
OUT
IN(MIN)
C > ––––––––––––––––———–––
F
V
OUT
x R
x f
SENSE
x V
R
SENSE
OUT
R
< ————————
ESR
V
REF
ration ratings. In order to simplify the calculation, I
(can be multiplied by 1.5, see note below)
LOAD
20 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
These equations are “worst-case” with 45 degrees of
Tra n s fo rm e r De s ig n
(MAX7 9 6 /MAX7 9 9 On ly)
phase margin to ensure jitter-free fixed-frequency opera-
tion and provide a nicely damped output response for
zero to full-load step changes. Some cost-conscious
designers may wish to bend these rules by using less
expensive (lower quality) capacitors, particularly if the
load lacks large step changes. This practice is tolerable,
provided that some bench testing over temperature is
done to verify acceptable noise and transient response.
Buck-plus-flyback applications, sometimes called “cou-
pled-inductor” topologies, need a transformer in order to
generate multiple output voltages. The basic electrical
design is a simple task of calculating turns ratios and
adding the power delivered to the secondary in order to
calculate the current-sense resistor and primary induc-
tance. However, extremes of low input-output differen-
tials, widely different output loading levels, and high turns
ratios can complicate the design due to parasitic trans-
former parameters such as inter-winding capacitance,
secondary resistance, and leakage inductance. For
examples of what is possible with real-world transformers,
see the graphs of Maximum Secondary Current vs. Input
Voltage in the Typical Operating Characteristics.
There is no well-defined boundary between stable and
unstable operation. As phase margin is reduced, the
first symptom is a bit of timing jitter, which shows up as
blurred edges in the switching waveforms where the
scope won’t quite sync up. Technically speaking, this
(usually) harmless jitter is unstable operation, since the
s witc hing fre q ue nc y is now non-c ons ta nt. As the
capacitor quality is reduced, the jitter becomes more
p ronounc e d a nd the loa d -tra ns ie nt outp ut volta g e
wa ve form s ta rts looking ra g g e d a t the e d g e s .
Eventually, the load-transient waveform has enough
ringing on it that the peak noise levels exceed the
allowable output voltage tolerance. Note that even with
zero phase margin and gross instability present, the
Power from the main and secondary outputs is lumped
together to obtain an equivalent current referred to the
main output voltage (see Inductor L1 for definitions of
parameters). Set the value of the current-sense resistor
at 80mV / I
.
TOTAL
P
= the sum of the output power from all outputs
TOTAL
I
=
P
/ V
= the equivalent output cur-
TOTAL
TOTAL
OUT
output voltage noise never gets much worse than I
PEAK
rent referred to V
OUT
x R
(under constant loads, at least).
ESR
V
(V
- V
)
Designers of RF communicators or other noise-sensi-
tive analog equipment should be conservative and
stick to the guidelines. Designers of notebook comput-
ers and similar commercial-temperature-range digital
OUT IN(MAX)
OUT
L(primary) = —————————————
x f x I x LIR
V
IN(MAX)
TOTAL
V
SEC
+ V
FWD
systems can multiply the R
value by a factor of 1.5
ESR
Turns Ratio N = ——————————————
+ V + V
V
OUT(MIN)
RECT
SENSE
without hurting stability or transient response.
The output voltage ripple is usually dominated by the
ESR of the filter capacitor and can be approximated as
where: V
is the minimum required rectified sec-
SEC
ondary-output voltage
is the forward drop across the secondary
I
x R
. There is also a capacitive term, so the
ESR
RIPPLE
V
FWD
full e q ua tion for rip p le in the c ontinuous mod e is
= I x (R + 1 / (2 x pi x f x C )). In
rectifier
V
NOISE(p-p)
RIPPLE
ESR
F
V
is the minimum value of the main
OUT(MIN)
idle mode, the inductor current becomes discontinuous
with hig h p e a ks a nd wid e ly s p a c e d p uls e s , s o the
noise can actually be higher at light load compared to
full load. In idle mode, the output ripple can be calcu-
lated as:
output voltage (from the Electrical
Characteristics)
V
RECT
is the on-state voltage drop across the
synchronous-rectifier MOSFET
is the voltage drop across the sense
V
SENSE
resistor
0.02 x R
ESR
V
= —————— +
NOISE(p-p)
In positive-output (MAX796) applications, the trans-
former secondary return is often referred to the main
output voltage rather than to ground in order to reduce
the needed turns ratio. In this case, the main output
voltage must first be subtracted from the secondary
R
SENSE
0.0003 x L x [1 / V
+ 1 / (V - V
)]
OUT
IN
OUT
———————————————————
2
(R
) x C
F
SENSE
voltage to obtain V
.
SEC
______________________________________________________________________________________ 21
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
During short circuit, Q2’s duty factor can increase to
greater than 0.9 according to:
Q2 DUTY (short circuit) = 1 - [V / (V
______S e le c t in g Ot h e r Co m p o n e n t s
MOS FET S w it c h e s
The two high-current N-channel MOSFETs must be
logic-level types with guaranteed on-resistance specifi-
- V )]
Q2
IN(MAX)
Q1
where the on-state voltage drop V = (120mV / R
)
Q
SENSE
x R
DS(ON).
cations at V = 4.5V. Lower gate threshold specs are
GS
better (i.e., 2V max rather than 3V max). Drain-source
breakdown voltage ratings must at least equal the max-
imum input voltage, preferably with a 20% derating fac-
tor. The b e s t MOSFETs will ha ve the lowe s t
on-re s is ta nc e p e r na noc oulomb of g a te c ha rg e .
Re c t ifie r Dio d e D1
Rectifier D1 is a clamp that catches the negative induc-
tor swing during the 110ns dead time between turning
off the high-side MOSFET and turning on the low-side.
D1 must be a Schottky type in order to prevent the
lossy parasitic MOSFET body diode from conducting. It
is acceptable to omit D1 and let the body diode clamp
the negative inductor swing, but efficiency will drop one
or two percent as a result. Use an MBR0530 (500mA
rated) type for loads up to 1.5A, a 1N5819 type for
loads up to 3A, or a 1N5822 type for loads up to 10A.
D1’s rated reverse breakdown voltage must be at least
equal to the maximum input voltage, preferably with a
20% derating factor.
Multiplying R
x Q provides a meaningful figure
DS(ON)
G
by which to compare various MOSFETs. Newer MOS-
FET process technologies with dense cell structures
generally give the best performance. The internal gate
drivers can tolerate >100nC total gate charge, but
70nC is a more practical upper limit to maintain best
switching times.
In high-current applications, MOSFET package power
dissipation often becomes a dominant design factor.
2
I R power losses are the greatest heat contributor for
2
Bo o s t -S u p p ly Dio d e D2
A signal diode such as a 1N4148 works well for D2 in
most applications. If the input voltage can go below 6V,
use a small (20mA) Schottky diode for slightly improved
efficiency and dropout characteristics. Don’t use large
power diodes such as 1N5817 or 1N4001, since high
junction capacitance can cause VL to be pumped up to
excessive voltages.
both high- and low-side MOSFETs. I R losses are dis-
tributed between Q1 and Q2 according to duty factor
(see the equations below). Switching losses affect the
upper MOSFET only, since the Schottky rectifier clamps
the switching node before the synchronous rectifier
turns on. Gate-charge losses are dissipated by the dri-
ver- er and don’t heat the MOSFET. Ensure that both
MOSFETs are within their maximum junction tempera-
ture at high ambient temperature by calculating the
temperature rise according to package thermal-resis -
tance specifications. The worst-case dissipation for the
high-side MOSFET occurs at the minimum battery volt-
a g e , a nd the wors t-c a s e for the low-s id e MOSFET
occurs at the maximum battery voltage.
6/MAX79
Re c t ifie r Dio d e D3
(Tra n s fo rm e r S e c o n d a ry Dio d e )
The secondary diode in coupled-inductor applications
must withstand high flyback voltages greater than 60V,
whic h us ua lly rule s out mos t Sc hottky re c tifie rs .
Common silicon rectifiers such as the 1N4001 are also
prohibited, as they are far too slow. This often makes
fast silicon rectifiers such as the MURS120 the only
choice. The flyback voltage across the rectifier is relat-
2
PD (upper FET) = I
x R
x DUTY
LOAD
DS(ON)
V
x C
RSS
IN
+ V x I
x f x
(
––––––––––– +20ns
)
IN
LOAD
I
GATE
ed to the V -V
former turns ratio:
difference according to the trans-
IN OUT
2
PD (lower FET) = I
x R
x (1 - DUTY)
LOAD
DS(ON)
V
= V
+ (V - V
) x N
OUT
FLYBACK
SEC
IN
DUTY = (V
+ V ) / (V - V
)
OUT
Q2
IN
Q1
where: N is the transformer turns ratio SEC/PRI
where: On-state voltage drop V = I
x R
DS(ON)
Q_
LOAD
V
V
OUT
is the maximum secondary DC output voltage
is the primary (main) output voltage
SEC
C
= MOSFET reverse transfer capacitance
= DH driver peak output current capability
(1A typically)
RSS
I
GATE
Subtract the main output voltage (V ) from V
OUT FLYBACK
in this equation if the secondary winding is returned to
and not to ground. The diode reverse breakdown
rating must also accommodate any ringing due to leak-
age inductance. D3’s current rating should be at least
twice the DC load current on the secondary output.
20ns = DH driver inherent rise/fall time
V
OUT
Under output short circuit, the synchronous-rectifier
MOSFET suffers extra stress and may need to be over-
sized if a continuous DC short circuit must be tolerated.
22 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
____________Lo w -Vo lt a g e Op e ra t io n
__________Ap p lic a t io n s In fo rm a t io n
Low input voltages and low input-output differential volt-
ages each require some extra care in the design. Low
absolute input voltages can cause the VL linear regulator
to enter dropout, and eventually shut itself off. Low input
He a vy-Lo a d Effic ie n c y Co n s id e ra t io n s
The major efficiency loss mechanisms under loads are,
in the usual order of importance:
2
2
• P(I R), I R losses
voltages relative to the output (low V -V
differential)
IN OUT
can cause bad load regulation in multi-output flyback
applications. See the design equations in the Transformer
• P(gate), gate-charge losses
• P(diode), diode-conduction losses
• P(tran), transition losses
• P(cap), capacitor ESR losses
Design section. Finally, low V -V
differentials can also
IN OUT
cause the output voltage to sag when the load current
changes abruptly. The amplitude of the sag is a function
of inductor value and maximum duty factor (an Electrical
Characteristics parameter, 93% guaranteed over temper-
ature at f = 150kHz) as follows:
• P(IC), losses due to the operating supply current
of the IC
Ind uc tor-c ore los s e s a re fa irly low a t he a vy loa d s
because the inductor’s AC current component is small.
Therefore, they aren’t accounted for in this analysis.
Ferrite cores are preferred, especially at 300kHz, but
powdered cores such as Kool-mu can work well.
2
(I
) x L
STEP
V
SAG
= ———————————————
2 x C x (V
x D
- V
)
F
IN(MIN)
MAX
OUT
The cure for low-voltage sag is to increase the value of
the output capacitor. For example, at V = 5.5V, V
IN
OUT
Efficiency = P
/ P x 100%
IN
OUT
OUT
= 5V, L = 10µH, f = 150kHz, a total capacitance of
660µF will prevent excessive sag. Note that only the
capacitance requirement is increased and the ESR
re q uire me nts d on’t c ha ng e . The re fore , the a d d e d
c a p a c ita nc e c a n b e s up p lie d b y a low-c os t b ulk
capacitor in parallel with the normal low-ESR capacitor.
= P
/ (P
+ P
) x 100%
OUT
TOTAL
2
P
= P(I R) + P(gate) + P(diode) + P(tran) +
TOTAL
2
P(cap) + P(IC)
2
P(I R) = (I
) x (R
+ R
+ R
)
LOAD
DC
DS(ON)
SENSE
where R
is the DC resistance of the coil, R
is
DC
DS(ON)
the MOSFET on-resistance, and R
is the current-
SENSE
Table 4. Low-Voltage Troubleshooting
SOLUTION
SYMPTOM
CONDITION
ROOT CAUSE
Increase bulk output capacitance per
formula above. Reduce inductor value.
Sag or droop in V
under step load change
Low V -V
<1.5V
differential, Limited inductor-current slew
rate per cycle.
OUT
IN OUT
Dropout voltage is too
Reduce f to 150kHz. Reduce MOSFET
on-resistance and coil DCR.
Low V -V
<1V
differential, Maximum duty-cycle limits
exceeded.
IN OUT
high (V
follows V as
IN
OUT
V
IN
decreases)
Reduce L value. Tolerate the remaining
jitter (extra output capacitance helps
somewhat).
Inherent limitation of fixed-fre-
differential,
Unstable—jitters between Low V -V
IN OUT
quency current-mode SMPS
two distinct duty factors
<1V
slope compensation.
Not enough duty cycle left to
differential,
Reduce f to 150kHz. Reduce secondary
impedances—use Schottky if possible.
Stack secondary winding on main output.
Low V -V
IN OUT
Secondary output won’t
support a load
initiate forward-mode operation.
V
< 1.3 x V
(main)
OUT
IN
Small AC current in primary can’t
store energy for flyback operation.
(MAX796/MAX799 only)
Use a small 20mA Schottky diode for
boost diode D2. Supply VL from an
external source.
VL linear regulator is going into
dropout and isn’t providing
good gate-drive levels.
High supply current,
poor efficiency
Low input voltage, <5V
Won’t start under load or
quits before battery is
completely dead
Supply VL from an external source other
VL output is so low that it hits the
VL UVLO threshold at 4.2V max.
Low input voltage, <4.5V
than V
, such as the system 5V supply.
BATT
______________________________________________________________________________________ 23
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
sense resistor value. The R
term assumes identi-
ground plane is essential for optimum performance. In
most applications, the circuit will be located on a multi-
layer board and full use of the four or more copper lay-
ers is recommended. Use the top layer for high-current
connections, the bottom layer for quiet connections
(REF, SS, GND), and the inner layers for an uninterrupt-
ed ground plane. Use the following step-by-step guide.
DS(ON)
c a l MOSFETs for the hig h- a nd low-s id e s witc he s
because they time-share the inductor current. If the
MOSFETs aren’t identical, their losses can be estimat-
ed by averaging the losses according to duty factor.
P(gate) = gate-driver loss = qG x f x VL
where VL is the MAX796 internal logic supply voltage
(5V), and qG is the sum of the gate-charge values for
low- and high-side switches. For matched MOSFETs,
qG is twice the data sheet value of an individual MOS-
1) Place the high-power components (C1, C2, Q1, Q2,
D1, L1, and R1) first, with their grounds adjacent.
Priority 1: Minimize current-sense resistor trace
lengths (see Figure 10).
FET. If V
is set to less than 4.5V, replace VL in this
OUT
equation with V
improved by connecting VL to an efficient 5V source,
such as the system +5V supply.
. In this case, efficiency can be
BATT
Priority 2: Minimize ground trace lengths in the
high-current paths (discussed below).
Priority 3: Minimize other trace lengths in the high-
current paths. Use >5mm wide traces.
C1 to Q1: 10mm ma x le ng th.
D1 c a thod e to Q2: 5mm ma x le ng th
LX node (Q1 source, Q2 drain, D1 cath-
ode, inductor): 15mm max length
P(diode) = diode conduction losses
= I
x V
x t x f
LOAD
FWD D
where t is the diode conduction time (110ns typ) and
D
V
FWD
is the forward voltage of the Schottky.
PD(tran) = transition loss =
Id e a lly, s urfa c e -mount p owe r c omp one nts a re
butted up to one another with their ground terminals
almost touching. These high-current grounds (C1-,
C2-, source of Q2, anode of D1, and PGND) are
then connected to each other with a wide filled zone
of top-layer copper, so that they don’t go through
vias. The resulting top-layer “sub-ground-plane” is
connected to the normal inner-layer ground plane at
the output ground terminals. This ensures that the
analog GND of the IC is sensing at the output termi-
na ls of the s up p ly, without inte rfe re nc e from IR
drops and ground noise. Other high-current paths
should also be minimized, but focusing ruthlessly
on short ground and current-sense connections
eliminates about 90% of all PC layout
headaches. See the evaluation kit PC board layouts
for examples.
VBATT x CRSS
x f x (——————— + 20ns)
V
x I
BATT LOAD
I
GATE
where C
is the reverse transfer capacitance of the
RSS
6/MAX79
high-side MOSFET (a data sheet parameter), I
is
GATE
the DH gate-driver peak output current (1A typ), and
20ns is the rise/fall time of the DH driver (20ns typ).
2
P(cap) = input capacitor ESR loss = (I
) x R
ESR
RMS
where I
is the input ripple current as calculated in the
Input Capacitor Value section of the Design Procedure.
RMS
Lig h t -Lo a d Effic ie n c y Co n s id e ra t io n s
Under light loads, the PWM operates in discontinuous
mode, where the inductor current discharges to zero at
some point during the switching cycle. This causes the
AC component of the inductor current to be high com-
pared to the load current, which increases core losses
2) Place the IC and signal components. Keep the main
switching node (LX node) away from sensitive ana-
log components (current-sense traces and REF and
SS capacitors). Placing the IC and analog compo-
nents on the opposite side of the board from the
power-switching node is desirable. Important: the
IC must be no farther than 10mm from the current-
sense resistor. Keep the gate-drive traces (DH, DL,
and BST) shorter than 20mm and route them away
from CSH, CSL, REF, and SS.
2
and I R losses in the output filter capacitors. Obtain best
light-load efficiency by using MOSFETs with moderate
gate-charge levels and by using ferrite, MPP, or other
low-loss core material. Avoid powdered iron cores; even
Kool-mu (aluminum alloy) is not as good as ferrite.
__P C Bo a rd La yo u t Co n s id e ra t io n s
Good PC board layout is required to achieve specified
noise, efficiency, and stability performance. The PC
b oa rd la yout a rtis t mus t b e p rovid e d with e xp lic it
instructions, preferably a pencil sketch of the place-
ment of power switching components and high-current
routing. See the evaluation kit PC board layouts in the
MAX796 and MAX797 EV kit manuals for examples. A
3) Employ a single-point star ground where the input
ground trace, power ground (sub-ground-plane),
and normal ground plane all meet at the output
ground terminal of the supply.
24 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
FAT, HIGH-CURRENT TRACES
MAIN CURRENT PATH
SENSE RESISTOR
MAX796
MAX797
MAX799
Figure 10. Kelvin Connections for the Current-Sense Resistor
_________________________________________________________Ap p lic a t io n Circ u it s
V (6.5V TO 18V)
IN
+15V
AT
22µF, 35V
250mA
C2
4.7µF
D1
210k, 1%
2
7
11
VL
CMPSH
-3A
49.9k, 1%
C2
4.7µF
C3
15µF
2.5V
SECFB
FB
10
V+
DH
Si9410
16
14
0.01µF
18V
1/4 W
D2
EC11FS1
6
ON/OFF
SHDN
BST
+5V
AT 3A
0.1µF
15
T1
LX
MAX796
20mΩ
15µH
2.2:1
220µF
6.3V
Si9410
13
12
1
4
DL
1N5819
SS
PGND
0.01µF
(OPTIONAL)
8
9
GND
CSH
CSL
22Ω*
4700pF*
SYNC
REF
T1 = TRANSPOWER TTI5870
* = OPTIONAL, MAY NOT BE NEEDED
5
3
0.33µF
Figure 11. +5V/+15V Dual-Output Application (MAX796)
______________________________________________________________________________________ 25
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
____________________________________________Ap p lic a t io n Circ u it s (c o n t in u e d )
33µF, 35V
V
IN
(8V TO 18V AS SHOWN)
102k, 1%
100k, 1%
10
2
11
+5V
AT
1N4148
4.7µF
MBR0502L
V+
SECFB
VL
14
500mA
BST
DH
T1
1:1.5
6
16
15
ON/OFF
SHDN
Q1
Q2
47µF
+3.3V
AT 2A
0.1µF
10µH
LX
25mΩ
1N5819
13
12
MAX796
Q3
DL
330µF
PGND
1N5817
102k
1%
1
8
9
SS
CSH
CSL
33.2k
1%
7
0.01µF
(OPTIONAL)
FB
SYNC
5
GND
4
REF
3
Q1-Q2 = Si9410 or EQUIVALENT
T1 = TDK 1:1.5 TRANSFORMER
49.9k
1%
Q3 = Si9955 or EQUIVALENT (50V) PC40EEM 12.7/13.7 - A160 CORE
BEM 12.7/13.7 BOBBIN
0.33µF
PRIMARY = 8 TURNS 24 AWG
SECONDARY = 12 TURNS 24 AWG
DESIGN FOR TIGHT MAGNETIC COUPLING
6/MAX79
Figure 12. +3.3V/+5V Dual-Output Application (MAX796)
V
IN
(9V TO 18V)
22µF, 35V
107k, 1%
1000pF
221k, 1%
1µF
-5.5V OUT
(-5.5V AT 200mA)
3
11
2
1N4148
22µF
10V
EQ11FS1
REF
VL
SECFB
10
V+
DH
4.7µF
5
16
14
SYNC
1/2
Si9936
BST
0.1µF
+5V OUT
15
T1
15µH
1:1.3
(+5V AT 1A)
LX
50mΩ
220µF
10V
1N5819
13
12
8
1/2 Si9936
MAX799
DL
6
ON/OFF
PGND
CSH
SHDN
9
7
CSL
FB
GND
SS
T1 = TRANSPOWER TTI5926
4
1
0.01µF
(OPTIONAL)
Figure 13. ±5V Dual-Output Application (MAX799)
26 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
____________________________________________Ap p lic a t io n Circ u it s (c o n t in u e d )
MAX797
INPUT
4.5V
TO 30V
STANDARD 3.3V
CIRCUIT
+3.3V
MAIN OUTPUT
V+
MAIN
3.3V
OUTPUT
(CSL)
REF
(2.505V)
VL (5V)
82pF
1k
Q1
Si9433DY
OR MMSF4P01
MAX473
1.5k
+2.9V OUTPUT
AT 2A
20pF
100k, 1%
16k, 1%
10µF
10µF
SANYO OS-CON
Figure 14. 2.9V Low-Dropout Linear Regulator with Fast Transient Response
0.033Ω
V
IN
2.5V TO 5.25V
L1
5µH
CSH
CSL
C1
100µF
+5V AT 1A
DL
REF
D1
Q1
DH
LX
0.33µF
GND
SKIP
MAX797
SYNC
PGND
C2
C3
100µF 100µF
V+
SHDN
FB
BST
VL
0.1µF
100k
4.7µF
100k
L1 = SUMIDA CDRH125, 5µH
D1 = MOTOROLA MBR130
C1 - C3 = AVX TPS 100µF, 10V
33k
1N4148
2N7002
Q1 = SILICONIX Si9936 (BOTH SECTIONS)
OR MOTOROLA MMDF3N03L
0.01µF
1N4148
+3.3V
(EXTERNAL)
OPTIONAL SYNC AND LOW-VOLTAGE
START-UP CIRCUIT
190kHz - 340kHz
Figure 15. Low-Noise Boost Converter for Cellular Phones
______________________________________________________________________________________ 27
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
____________________________________________Ap p lic a t io n Circ u it s (c o n t in u e d )
0.01Ω
VIN
4.75V TO 6V
L1
5µH
CSH
SYNC
CSL
C1
220µF
+12V AT 2A
D1
Q1
REF
DH
LX
MAX797
0.33µF
4.7µF
GND
SKIP
PGND
C2
C3
150µF 150µF
V+
SHDN
FB
191k
BST
VL
SS
49.9k
L1 = 2x SUMIDA CDRH125-100 IN PARALLEL
D1 = MOTOROLA MBR640
0.01µF
Q1 = MOTOROLA MTD20N03HDL
C1 = SANYO OS-CON 220µF, 10V
C2, C3 = SANYO OS-CON 150µF, 16V
6/MAX79
Figure 16. 5V-to-12V PWM Boost Converter
INPUT
OUTPUT
+5V AT 500mA
33mΩ
CMPSH-3A
3V TO 6.5V
T1
CSH
CSL
100µF
BST
VL
220µF 220µF
Q1
DH
LX
4.7µF
MAX797
DL
Q2
PGND
HI EFF
LOW IQ
SKIP
V+
SHDN
200k
FB
GND
SYNC
REF
200k
Q1, Q2 = Si9410DY
T1 = COILTRONIX CTX 10-4
10µH PRIMARY, 1:1
0.33µF
START-UP SUPPLY VOLTAGE = 3.5V TYP
Figure 17. 90% Efficient, Low-Voltage PWM Flyback Converter (4 Cells to 5V)
28 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
____________________________________________Ap p lic a t io n Circ u it s (c o n t in u e d )
INPUT
V+
VL
SHDN
4.7µF
BST
DH
Q1
Q2
OUTPUT
3.3V ±1.8%
L1
LX
SKIP
SS
R
SENSE
MAX797
REMOTE
SENSE
POINT
DL
PGND
CSH
CSL
FB
0.01µF
R1
51k
5%
63.4k
0.1%
GND
SYNC
REF
51k
5%
R1
V
OUT
= V (1 + –––)
REF
TO
VL
R2
ADJUST RANGE = 2.5V TO 4V AS SHOWN.
R2
200k
0.1%
200k
5%
0.33µF
1000pF
10k
OMIT R2 FOR V = 2.5V.
OUT
USE EXTERNAL REFERENCE
(MAX872) FOR BETTER ACCURACY.
MAX495
Figure 18. High-Accuracy Adjustable-Output Application
INPUT
4.5V TO 25V
1N4148
V+
FB
VL
BST
DH
LX
0.1µF
4.7µF
Si9410
22µF
22µF
SHDN
1N5819
-5V AT 1.5A
L1
MAX797
Si9410
CSH
CSL
150µF
150µF
0.025Ω
DL
GND
PGND
SKIP
SYNC
REF
0.33µF
L1 = DALE LPE6562-A093
Figure 19. Negative-Output (Inverting Topology) Power Supply
______________________________________________________________________________________ 29
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
____________________________________________Ap p lic a t io n Circ u it s (c o n t in u e d )
INPUT
0.1µF
C1
2x 22µF
1N4148
4.7µF
V+
VL
BST
DH
Q1
SHDN
T1
0.1µF
10µH
LX
MAX797
+5V OUTPUT
AT 3A
Q2
DL
C2
220µF
100k
1%
D1
1N5819
PGND
SS
FB
0.01µF
CSH
100k
1%
1.91Ω, 1%
1N4148
SKIP
CSL
SYNC
REF
T1 = 1:70 5mm SURFACE-MOUNT TRANSFORMER
DALE LPE-3325-A087
GND
0.33µF
Q1, Q2 = MMSF5N03 OR Si9410DY
6/MAX79
Figure 20. Buck Converter with Low-Loss SMT Current-Sense Transformer
N1 = N2 = MTD20N03HDL
L1 = COILCRAFT DO3316-332
C1
220µF
OS-CON
INPUT
4.75V
TO 5.5V
0.1µF
D1
4.7µF
V+
VL
BST
DH
L1
3.3µH
R1
12mΩ
N1
N2
C3
0.1µF
1.5V OUTPUT
AT 5A
LX
C2
2 x 220µF
OS-CON
D2
ON/OFF
C6
DL
SHDN
SS
1N5820
PGND
MAX797
CSH
CSL
0.01µF
R6
49.9k
FB
C7
330pF
R5
150k
R7
124k
SYNC
REF
R3
66.5k
1%
TO
VL
SKIP
GND
C5
0.33µF
R4
100k
1%
MAX495
REMOTE SENSE LINE
Figure 21. 1.5V GTL Bus Termination Supply
30 ______________________________________________________________________________________
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
6/MAX79
____________________________________________Ap p lic a t io n Circ u it s (c o n t in u e d )
10
V+
6
11
14
2
VL
BST
SKIP
V
SHDN
IN
10.5V to
28V
2X
D1
22µF
35V
0.01µF
4.7µF
16
Q1
DH
15
8
LX
MAX797
D3
CSH
T1
L1
10µH
1.7Ω
3
REF
CSL
DL
1
5
9
SS
3X
100µF
16V
0.01µF
I
Q2
13
OUT
D2
2.5A
12
SYNC
PGND
FB
GND
0.025Ω
0.33µF
7
4
1.0k
3
2
7
0.1µF
6
MAX495
4
D1, D3 CENTRAL SEMI. CMPSH-3
D2 NIEC EC10QS02L, SCHOTTKY RECT.
L1 DALE IHSM-4825 10µH 15%
T1 DALE LPE-3325-A087, CURRENT TRANSFORMER, 1:70
Q1, Q2 MOTOROLA MMSF5N03HD
39k
0.33µF
Figure 22. Battery-Charger Current Source
______________________________________________________________________________________ 31
S t e p -Do w n Co n t ro lle rs w it h
S yn c h ro n o u s Re c t ifie r fo r CP U P o w e r
_Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip To p o g ra p h y
PART
MAX797CPE
MAX797CSE
MAX797C/D
MAX797EPE
MAX797ESE
MAX797MJE
MAX799CPE
MAX799CSE
MAX799C/D
MAX799EPE
MAX799ESE
MAX799MJE
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
Dice*
SS
DH
0°C to +70°C
LX
SKIP
(SECFB)
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
16 Plastic DIP
16 Narrow SO
16 CERDIP
BST
16 Plastic DIP
16 Narrow SO
Dice*
0°C to +70°C
REF
DL
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 Narrow SO
16 CERDIP
PGND
GND
0. 16O"
(4. 064mm)
*Contact factory for dice specifications
SYNC
SHDN
VL
6/MAX79
V+
CSL
FB CSH
0. 085"
(2. 159mm)
(
) ARE FOR MAX796/MAX799 ONLY.
TRANSISTOR COUNT: 913
SUBSTRATE CONNECTED TO GND
32 ______________________________________________________________________________________
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