MAX807MCWE [MAXIM]
Full-Featured uP Supervisory Circuit with +/-1.5% Reset Accuracy; 全功能UP监控电路具有+/- 1.5 ％复位精度
| 型号： | MAX807MCWE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Full-Featured uP Supervisory Circuit with +/-1.5% Reset Accuracy |
| 文件： | 总16页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0433; Rev 3; 4/03
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
General Description
____________________________Features
The MAX807 microprocessor (µP) supervisory circuit
reduces the complexity and number of components
needed to monitor power-supply and battery-control func-
tions in µP systems. A 70µA supply current makes the
MAX807 ideal for use in portable equipment, while a 2ns
chip-enable propagation delay and 250mA output current
capability (20mA in battery-backup mode) make it suit-
able for larger, higher-performance equipment.
ꢀ Precision 4.675V (MAX807L), 4.425V (MAX807M),
or 4.575V (MAX807N) Voltage Monitoring
ꢀ 200ms Power-OK/Reset Time Delay
ꢀ RESET and RESET Outputs
ꢀ Independent Watchdog Timer
ꢀ 1µA Standby Current
The MAX807 comes in 16-pin DIP, SO, and TSSOP pack-
ages, and provides the following functions:
ꢀ Power Switching
250mA in V Mode
CC
• µP reset. The active-low RESET output is asserted dur-
ing power-up, power-down, and brownout conditions,
and is guaranteed to be in the correct state for VCC
down to 1V.
20mA in Battery-Backup Mode
ꢀ On-Board Gating of Chip-Enable Signals;
2ns CE Gate Propagation Delay
• Active-high RESET output.
• Manual-reset input.
®
®
ꢀ MaxCap and SuperCap Compatible
ꢀ Voltage Monitor for Power Fail
ꢀ Backup-Battery Monitor
• Two-stage power-fail warning. A separate low-line
comparator compares VCC to a threshold 52mV above
the reset threshold. This low-line comparator is more
accurate than those in previous µP supervisors.
ꢀ Guaranteed RESET Valid to VCC = 1V
ꢀ
1.5% Low-Line Threshold Accuracy 52mV above
Reset Threshold
• Backup-battery switchover for CMOS RAM, real-time
clocks, µPs, or other low-power logic.
• Write protection of CMOS RAM or EEPROM.
• 2.275V threshold detector provides for power-fail
warning and low-battery detection, or monitors a
power supply other than +5V.
Pin Configuration
• BATT OK status flag indicates that the backup-battery
voltage is above +2.275V.
• Watchdog-fault output—asserted if the watchdog input
has not been toggled within a preset timeout period.
TOP VIEW
PFI
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
Applications
BATT OK
BATT
PFO
V
CC
Computers
Controllers
WDI
GND
MAX807
BATT ON
CE IN
Intelligent Instruments
Critical µP Power Monitoring
Portable/Battery-Powered Equipment
MR
CE OUT
LOW LINE
RESET
10 WDO
RESET
9
DIP/SO/TSSOP
Ordering Information and Typical Operating Circuit appear at end of data sheet.
SuperCap is a registered trademark of Baknor Industries. MaxCap is a registered trademark of Cesiwid, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
ABSOLUTE MAXIMUM RATINGS
Input Voltages (with respect to GND)
Continuous Power Dissipation (T = +70°C)
A
V
V
..........................................................................-0.3V to 6V
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Wide SO (derate 9.52mW/°C above +70°C)................762mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
TSSOP (derate 6.70 mW/°C above +70°C) .................533mW
Operating Temperature Ranges
MAX807_C_E......................................................0°C to +70°C
MAX807_E_E ...................................................-40°C to +85°C
MAX807_MJE ................................................-55°C to +125°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
.......................................................................-0.3V to 6V
BATT
All Other Inputs......................................-0.3V to (V
Input Current
+ 0.3V)
OUT
V
V
Peak ...........................................................................1.0A
Continuous .............................................................500mA
Peak......................................................................250mA
Continuous .............................................................50mA
CC
CC
I
I
BATT
BATT
GND .................................................................................50mA
All Other Inputs ................................................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 4.60V to 5.5V for the MAX807L, V
= 4.50V to 5.5V for the MAX807N, V
= 4.35V to 5.5V for the MAX807M,
CC
CC
CC
V
BATT
= 2.8V, V
= 0V, T = T
to T
. Typical values are tested with V
MAX
= 5V and T = +25°C, unless otherwise noted.)
PFI
A
MIN
CC A
PARAMETER
Operating Voltage Range
, V (Note 1)
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
0
5.5
V
V
V
BATT CC
I
I
= 25mA
V
- 0.02
- 0.22
OUT
CC
= 250mA,
OUT
V
- 0.35 V
CC
CC
MAX807C/E
V
= 4.5V
V
OUT
in Normal Operating
CC
Mode
I
= 250mA,
OUT
V
V
- 0.45
CC
MAX807M
V
V
= 3V, V
= 4.5V,
= 2.8V, I
= 100mA
= 100mA
- 0.25 V
- 0.12
1.0
CC
BATT
OUT
CC
CC
MAX807C/E
MAX807M
1.4
1.8
2.5
CC
I
= 250mA
V
V
to OUT On-Resistance
OUT
Ω
CC
V
V
V
V
V
V
V
= 3V, I
OUT
1.2
CC
= 4.5V, I
= 2.8V, I
= 2.0V, I
= 4.5V, I
= 2.8V, I
= 2.0V, I
= 20mA, V
= 10mA, V
= 5mA, V
= 20mA
= 10mA
= 5mA
= 0V
= 0V
= 0V
V
- 0.17
- 0.12
- 0.08
BATT
BATT
BATT
BATT
BATT
BATT
OUT
OUT
OUT
OUT
OUT
OUT
CC
CC
BATT
BATT
BATT
8.5
in Battery-Backup Mode
V
V
- 0.25 V
- 0.20 V
V
OUT
BATT
CC
BATT
BATT to OUT On-Resistance
Supply Current in Normal
12
16
25
40
Ω
70
110
µA
µA
Operating Mode (excludes I
)
OUT
T
= +25°C
0.4
1
5
A
Supply Current in Battery-
Backup Mode (excludes I
(Note 2)
)
V
CC
= 0V, V = 2.8V
BATT
MAX807C/E
MAX807M
OUT
50
T
= +25°C
-0.1
-1.0
0.1
1.0
A
BATT Standby Current (Note 3)
V
V
= 2.8V, V = 3.0V
CC
µA
V
BATT
T
T
= T
to
A
MAX
MIN
Power up
Power down
V
+ 0.05
BATT
Battery-Switchover Threshold
= 2.8V
BATT
V
BATT
Battery-Switchover Hysteresis
BATT ON Output, Low Voltage
BATT ON Output, High Voltage
50
0.1
2.7
mV
V
V
V
V
, I
= 3.2mA
= 0.1mA, V = 2.8V
BATT
0.4
RST (max) SINK
= 0V, I
2
CC
SOURCE
2
_______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
ELECTRICAL CHARACTERISTICS (continued)
(V
= 4.60V to 5.5V for the MAX807L, V
= 4.50V to 5.5V for the MAX807N, V
= 4.35V to 5.5V for the MAX807M,
CC
CC
CC
V
BATT
= 2.8V, V
= 0V, T = T
to T
. Typical values are tested with V
MAX
= 5V and T = +25°C, unless otherwise noted.)
PFI
A
MIN
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
70
5
MAX
UNITS
Sink current
Source current, V
BATT ON Output
Short-Circuit Current
mA
= 0V, V
= 2.8V
CC
BATT
RESET, LOW LINE, AND WATCHDOG TIMER
MAX807L
MAX807N
MAX807M
4.600
4.500
4.350
4.675
4.575
4.425
13
4.750
4.650
4.500
Reset Threshold
V
V
rising and falling
V
RST
CC
Reset Threshold Hysteresis
mV
mV
LOW LINE to RESET
Threshold Voltage
V
V
CC
falling
30
52
70
LR
MAX807L
MAX807N
MAX807M
4.73
4.63
4.48
26
4.81
4.71
4.56
LOW LINE Threshold,
V
V
LL
V
CC
Rising
V
V
to RESET Delay
V
CC
V
CC
V
CC
falling at 1mV/µs
falling at 1mV/µs
rising
µs
µs
ms
s
CC
to LOW LINE Delay
24
200
1.6
CC
RESET Active-Timeout Period
Watchdog-Timeout Period
t
RP
140
280
t
1.12
2.24
WD
Minimum Watchdog Input
Pulse Width
V
IL
= 0.8V, V = 0.75 x V
CC
100
ns
IH
V
= 1V,
CC
0.3
MAX807_C
I
= 50µA,
SINK
V
= 0V, V
falling
CC
BATT
V
= 1.2V,
CC
RESET Output Voltage
0.3
0.4
V
MAX807_E/M
I
I
= 3.2mA, V
= 4.25V
0.1
SINK
CC
= 0.1mA
V
V
V
V
- 1.5
V
- 0.1
CC
SOURCE
CC
CC
CC
CC
Output sink current, V
Output source current
= 4.25V
60
1.6
RESET Output
Short-Circuit Current
CC
I
mA
V
SC
SC
SC
SC
I
I
= 3.2mA
0.4
0.4
0.4
SINK
RESET Output Voltage
= 5mA
- 1.5
- 1.5
- 1.5
SOURCE
Output sink current
Output source current, V
60
15
RESET Output
Short-Circuit Current
I
mA
V
= 4.25V
CC
I
I
= 3.2mA, V
= 4.25V
SINK
CC
LOW LINE Output Voltage
= 5mA
SOURCE
Output sink current, V
Output source current
= 4.25V
28
20
LOW LINE Output
Short-Circuit Current
CC
I
I
mA
V
I
I
= 3.2mA
SINK
WDO Output Voltage
= 5mA
SOURCE
Output sink current
Output source current
35
20
WDO Output
Short-Circuit Current
mA
V
V
V
0.75 x V
-50
WDI Threshold Voltage
(Note 4)
IH
CC
0.8
50
IL
Reset deasserted, WDI = 0V
Reset deasserted, WDI = V
-10
16
WDI Input Current
µA
CC
_______________________________________________________________________________________
3
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
ELECTRICAL CHARACTERISTICS (continued)
(V
= 4.60V to 5.5V for the MAX807L, V
= 4.50V to 5.5V for the MAX807N, V
= 4.35V to 5.5V for the MAX807M,
CC
CC
CC
V
BATT
= 2.8V, V
= 0V, T = T
to T
. Typical values are tested with V
MAX
= 5V and T = +25°C, unless otherwise noted.)
PFI
A
MIN
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.20
2.22
TYP
2.265
2.285
20
0.005
14
MAX
2.33
2.35
UNITS
V
V
falling
rising
PFI
PFI Input Threshold
V
PFT
V
PFI
PFI Hysteresis
PFI Leakage Current
PFI to PFO Delay (Note 5)
mV
nA
µs
40
V
OD
= 30mV, V
falling
PFI
CHIP-ENABLE GATING
CE IN Leakage Current
Disabled mode, MR = 0V
Enabled mode, V = V
0.00002
75
1
µA
CE IN to CE OUT Resistance
(Note 6)
(max)
RST
150
Ω
CC
CE OUT Short-Circuit Current
(RESET Active)
V
= 5V, disabled mode,
CC
17
2
mA
ns
CE OUT = 0, MR = 0V
CE IN to CE OUT
Propagation Delay (Note 7)
V
CC
= 5V, C = 50pF,
LOAD
8
50Ω source impedance driver
V
= 5V,
= 2mA
CC
3.5
I
OUT
CE OUT Output Voltage High
(RESET Active)
Disabled mode, MR = 0V
V
V
= 0V,
= 10µA
CC
V
- 0.1
V
BATT
BATT
28
I
OUT
RESET to CE OUT Delay
MANUAL RESET INPUT
MR Minimum Pulse Input
V
CC
falling
µs
1
µs
ns
MR-to-RESET Propagation
Delay
170
100
V
V
2.4
50
IH
MR Threshold
V
0.8
IL
MR Pullup Current
MR = 0V
200
µA
BATT OK COMPARATOR
BATT OK Threshold
BATT OK Hysteresis
LOGIC OUTPUTS
V
2.200
2.265
20
2.350
0.4
V
mV
BOK
V
V
I
= 3.2mA
SINK
Output Voltage
(PFO, BATT OK)
OL
V
I
= 5mA
V
- 1.5
OH
SOURCE
CC
Output sink current
Output source current
35
20
Output Short-Circuit Current
I
mA
SC
Note 1: Either V
or V
can go to 0 if the other is greater than 2.0V.
CC
BATT
Note 2: The supply current drawn by the MAX807 from the battery (excluding I
) typically goes to 15µA when (V
- 0.1V)
OUT
BATT
< V < V
. In most applications, this is a brief period as V falls through this region (see Typical Operating Characteristics).
CC
BATT
CC
Note 3: “+”= battery discharging current, “-”= battery charging current.
Note 4: WDI is internally connected to a voltage-divider between V and GND. If unconnected, WDI is driven to 1.8V (typical),
CC
disabling the watchdog function.
Note 5: Overdrive (V ) is measured from center of hysteresis band.
OD
Note 6: The chip-enable resistance is tested with V
= V /2, and I
= 1mA.
CE IN
CE IN
CC
Note 7: The chip-enable propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
_______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
__________________________________________Typical Operating Characteristics
(V
= 5V, V = 2.8V, PFI = 0, no load, T = +25°C, unless otherwise noted.)
BATT A
CC
CHIP-ENABLE PROPAGATION DELAY
vs. TEMPERATURE
BATTERY SUPPLY CURRENT vs.
TEMPERATURE (BATTERY-BACKUP MODE)
V
SUPPLY CURRENT vs. TEMPERATURE
(NORMAL OPERATING MODE)
CC
6
5
4
3
2
1
0
3.0
2.5
2.0
1.5
1.0
0.5
0
80
78
76
74
72
70
68
66
64
62
60
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
BATT-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
V
-TO-OUT ON-RESISTANCE
vs. TEMPERATURE
PFI THRESHOLD
CC
vs. TEMPERATURE (V FALLING)
PFI
30
1.6
1.5
1.4
1.3
1.2
2.340
2.320
V
I
= 0V
CC
I
= 250mA
OUT
= 10mA
OUT
25
20
15
10
5
2.300
2.280
2.260
2.240
2.220
2.200
V
BATT
= 2.0V
1.1
1.0
V
V
= 2.8V
= 4.5V
BATT
0.9
0.8
0.7
BATT
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET THRESHOLD
vs. TEMPERATURE
RESET TIMEOUT PERIOD
vs. TEMPERATURE (V RISING)
LOW LINE -TO-RESET THRESHOLD
vs. TEMPERATURE (V FALLING)
CC
CC
4.70
4.65
4.60
4.55
4.50
4.45
4.40
280
260
80
70
60
50
MAX807L
240
220
200
180
160
140
MAX807N
40
30
20
10
0
MAX807M
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
Typical Operating Characteristics (contiued)
(V
= 5V, V
= 2.8V, PFI = 0, no load, T = +25°C, unless otherwise noted.)
CC
BATT A
LOW LINE THRESHOLD
LOW LINE COMPARATOR PROPAGATION
DELAY vs. TEMPERATURE (V FALLING)
RESET COMPARATOR PROPAGATION
DELAY vs. TEMPERATURE (V FALLING)
vs. TEMPERATURE (V RISING)
CC
CC
CC
4.80
40
40
L VERSION
N VERSION
4.75
4.70
35
30
25
35
30
25
V
CC
FALLING AT 1mV/µs
V
CC
FALLING AT 1mV/µs
4.65
4.60
20
15
20
15
4.55
4.50
M VERSION
10
10
5
0
5
0
4.45
4.40
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
BATTERY CURRENT
vs. INPUT SUPPLY VOLTAGE
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
BATT-TO-OUT vs.
OUTPUT CURRENT
16
1000
100
10
8
6
4
V
= 0V
CC
SLOPE = 12Ω
14
12
10
8
6
4
2
0
2
0
50Ω DRIVER
2.5
2.6
2.7
2.8
2.9
3.0
0
50
100
1
10
(mA)
100
V
CC
(V)
C
LOAD
(pF)
I
OUT
MAXIMUM TRANSIENT DURATION vs.
RESET COMPARATOR OVERDRIVE
V
-TO-OUT vs.
CC
OUTPUT CURRENT
1000
100
10
1000
100
10
SLOPE = 1.0Ω
RESET OCCURS
1
1
1
10
100
1000
1
10
100
1000
RESET COMPARATOR OVERDRIVE (mV)
I
(mA)
OUT
6
_______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
Pin Description
PIN
NAME
FUNCTION
1
PFI
Power-Fail Input. When PFI is less than V
(2.265V), PFO goes low. Connect to ground when unused.
PFT
Power-Fail Output. This CMOS-logic output goes low when PFI is less than V
(2.265V). Valid for
PFT
2
3
4
5
PFO
V
CC
≥ 4V. PFO swings between V
and GND.
CC
V
CC
Input Supply Voltage, nominally +5V. Bypass with a 0.1µF capacitor to GND.
Watchdog Input. If WDI remains high or low longer than the watchdog-timeout period (1.6s, typ), WDO
goes low. Leave unconnected to disable the watchdog function.
WDI
GND
Ground
Manual-Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as MR remains low
and for 200ms after MR returns high. MR is an active-low input with an internal pullup to V . It can be
CC
6
MR
driven using TTL or CMOS logic, or shorted to ground with a switch. Connect to V , or leave uncon-
CC
nected if not used.
Low-Line Comparator Output. This CMOS-logic output goes low when V
falls to 52mV above the reset
CC
7
8
LOW LINE
RESET
threshold. Use this output to generate an NMI to initiate an orderly shutdown routine when V
is falling.
CC
LOW LINE swings between V
and GND.
CC
Active-High Reset Output. RESET is the inverse of RESET. It is a CMOS output that sources and sinks
current. RESET swings between V and GND.
CC
Active-Low Reset Output. RESET is triggered and stays low when V
is below the reset threshold or
CC
when MR is low. It remains low 200ms after V
rises above the reset threshold or MR returns high.
CC
9
RESET
WDO
RESET has a strong pulldown but a relatively weak pullup, and can be wire-OR connected to logic gates.
Valid for V ≥ 1V. RESET swings between V and GND.
CC
CC
Watchdog Output. This CMOS-logic output goes low if WDI remains high or low longer than the watch-
dog-timeout period (t ), and remains low until the next transition of WDI. WDO remains high if WDI is
WD
10
unconnected. WDO is high during reset. WDO swings between V
generate resets during watchdog faults.
and GND. Connect WDO to MR to
CC
Chip-Enable Output. Output to the chip-enable gating circuit. CE OUT is pulled up to the higher of V
CC
11
12
CE OUT
CE IN
or V
, when the chip-enable gate is disabled.
BATT
Chip-Enable Input
Battery-On Output. CMOS-logic output/external bypass switch driver. High when OUT is connected to
BATT and low when OUT is connected to V . Connect the base of a PNP transistor or gate of a PMOS
CC
13
14
BATT ON
BATT
transistor to BATT ON for I
requirements exceeding 250mA. BATT ON swings between the higher of
OUT
V
CC
and V
and GND.
BATT
Backup-Battery Input. When V
falls below the reset threshold and V
, OUT switches from V
to
CC
BATT
CC
BATT. V
may exceed V . The battery can be removed while the MAX807 is powered-up, provided
BATT
CC
BATT is bypassed with a 0.1µF capacitor to GND. If no battery is used, connect BATT to ground, and
connect V and OUT together.
CC
Battery-OK Signal Output. High in normal operating mode when V
exceeds V
(2.265V). Valid for
BATT
BOK
15
16
BATT OK
OUT
V
CC
≥ 4V.
Output Supply Voltage to CMOS RAM. When V
exceeds the reset threshold or V
> V
, OUT is
CC
CC
BATT
connected to V . When V
falls below the reset threshold and V
, OUT connects to BATT. Bypass
CC
CC
BATT
OUT with a 0.1µF capacitor to GND.
_______________________________________________________________________________________
7
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
ꢀESET and ꢀESET Outputs
Detailed Description
The MAX807’s RESET output ensures that the µP pow-
ers up in a known state, and prevents code execution
errors during power-down and brownout conditions. It
accomplishes this by resetting the µP, terminating pro-
The MAX807 µP supervisory circuit provides power-
supply monitoring, backup-battery switchover, and pro-
gram execution watchdog functions in µP systems
(Figure 1). Use of BiCMOS technology results in an
improved 1.5% reset-threshold precision, while keeping
supply currents typically below 70µA. The MAX807 is
intended for battery-powered applications that require
high reset-threshold precision, allowing a wide power-
supply operating range while preventing the system
from operating below its specified voltage range.
gram execution when V
dips below the reset thresh-
CC
old or MR is pulled low. Each time RESET is asserted it
stays low for the 200ms reset timeout period, which is
set by an internal timer to ensure the µP has adequate
time to return to an initial state. Any time V
goes
CC
below the reset threshold before the reset-timeout peri-
od is completed, the internal timer restarts. The watch-
dog timer can also initiate a reset if WDO is connected
to MR (see the Watchdog Input section).
V
CC
OUT
BATT
BATTERY-BACKUP
COMPARATOR
P
BATT ON
N
RESET
COMPARATOR
LOW LINE
BATT OK
LOW-LINE
COMPARATOR
PFO
WATCHDOG
TRANSITION
DETECTOR
WDI
BATTERY-OK
COMPARATOR
V
CC
50kΩ
GND
PFI
POWER-FAIL
COMPARATOR
MR
RESET
STATE
MACHINE
RESET
WDO
OSCILLATOR
2.275V
THE HIGHER
OF V OR V
CC
BATT
P
MAX807
P
CE IN
CE OUT
N
Figure 1. Block Diagram
8
_______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
V
RST
+ V
V
V
RST
V
LL
LR RST
V
CC
V
CC
V
V
LOW LINE
LOW LINE
t
t
V
V
RP
RESET
RESET
V
RESET
(MAX801)
RP
V
RESET
(MAX808)
CE OUT
V
BATT
V
V
CE OUT
V
BATT
SHOWN FOR V = 5V to 0, V
= 2.8V, CE IN = GND
SHOWN FOR V = 0 to 5V, V
= 2.8V, CE IN = GND
CC
BATT
CC
BATT
Figure 2a. Timing Diagram, V
Rising
Figure 2b. Timing Diagram, V
Falling
CC
CC
The RESET output is active low and implemented with a
strong pulldown/relatively weak pullup structure. It is
MANUAL RESET
guaranteed to be a logic low for 0 < V
< V
, pro-
CC
RST
vided V
is greater than 2V. Without a backup bat-
BATT
MR
tery, RESET is guaranteed valid for V
≥ 1. It typically
CC
sinks 3.2mA at 0.1V saturation voltage in its active state.
*
The RESET output is the inverse of the RESET output; it
both sources and sinks current and cannot be wire-OR
MAX807
OTHER
RESET
SOURCES
connected. Figure 2a shows a timing diagram with V
CC
*
rising and Figure 2b shows V
falling.
CC
Manual ꢀeset Input
*DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS.
Many µP-based products require manual-reset capabil-
ity to allow an operator or test technician to initiate a
reset. The Manual Reset (MR) input permits the genera-
tion of a reset in response to a logic low from a switch,
WDO, or external circuitry. Reset remains asserted
while MR is low, and for 200ms after MR returns high.
Figure 3. Diode “OR” Connections Allow Multiple Reset
Sources to Connect to MR
Watchdog Timer
Watchdog Input
The watchdog circuit monitors the µP’s activity. If the
µP does not toggle the watchdog input (WDI) within
1.6s, WDO goes low. The internal 1.6s timer is cleared
and WDO returns high when reset is asserted or when
a transition (low-to-high or high-to-low) occurs at WDI
while RESET is high. As long as reset is asserted, the
timer remains cleared and does not count. As soon as
reset is released, the timer starts counting (Figure 5).
Supply current is typically reduced by 10µA when WDI
is at a valid logic level.
MR has an internal 50µA to 200µA pullup current, so it
can be left open if it is not used. MR can be driven with
TTL or CMOS-logic levels, or with open-drain/collector
outputs. Connect a normally open momentary switch
from MR to GND to create a manual-reset function;
external debounce circuitry is not required. If MR is dri-
ven from long cables or if the device is used in a noisy
environment, connect a 0.1µF capacitor from MR to
ground to provide additional noise immunity. As shown
in Figure 3, diode-ORed connections can be used to
allow manual resets from multiple sources. Figure 4
shows the reset timing.
_______________________________________________________________________________________
9
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
Chip-Enable Signal Gating
1µs MIN
The MAX807 provides internal gating of chip-enable
(CE) signals to prevent erroneous data from corrupting
the CMOS RAM in the event of a power failure. During
normal operation, the CE gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The MAX807 uses a series
transmission gate from the Chip-Enable Input (CE IN) to
the Chip-Enable Output (CE OUT) (Figure 1).
MR
170ns
RESET
CE IN
0V
CE OUT
28µs TYP
The 8ns (max) chip-enable propagation from CE IN to
CE OUT enables the MAX807 to be used with most µPs.
Figure 4. Manual-Reset Timing Diagram
Chip-Enable Input
CE IN is high impedance (disabled mode) while RESET
Watchdog Output
is asserted. During a power-down sequence when V
CC
WDO remains high if there is a transition or pulse at
WDI during the watchdog-timeout period. WDO goes
low if no transition occurs at WDI during the watchdog-
timeout period. The watchdog function is disabled and
passes the reset threshold, the CE transmission gate
disables and CE IN becomes high impedance 28µs
after reset is asserted (Figure 7). During a power-up
sequence, CE IN remains high impedance (regardless
of CE IN activity) until reset is deasserted following the
reset-timeout period.
WDO is a logic high when V
is below the reset
CC
threshold or WDI is an open circuit. To generate a sys-
tem reset on every watchdog fault, diode-OR connect
WDO to MR (Figure 6). When a watchdog fault occurs
in this mode, WDO goes low, which pulls MR low, caus-
ing a reset pulse to be issued. As soon as reset is
asserted, the watchdog timer clears and WDO returns
high. With WDO connected to MR, a continuous high or
low on WDI will cause 200ms reset pulses to be issued
every 1.6s.
In the high-impedance mode, the leakage currents into
this input are 1µA (max) over temperature. In the low-
impedance mode, the impedance of CE IN appears as
a 75Ω resistor in series with the load at CE OUT.
The propagation delay through the CE transmission
gate depends on both the source impedance of the
drive to CE IN and the capacitive loading on CE OUT
V
RST
V
CC
4.7kΩ
V
CC
MAX807
WDO
MR
TO µP
RESET
t
RP
RESET
WDO
V
CC
∼50µs
t
WD
WDO
WDI
t
RP
t
t
RP
WD
RESET
WDI
WDO CONNECTED TO µP INTERRUPT.
Figure 5. Watchdog Timing Relationship
Figure 6. Generating a Reset on Each Watchdog Fault
10 ______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
V
RST
MAX
V
CC
RESET
THRESHOLD
V
CC
CE IN
MAX807
CE OUT
CE IN
CE OUT
28µs
26µs
26µs
50pF
50Ω DRIVER
C
LOAD
RESET
RESET
GND
Figure 7. Reset and Chip-Enable Timing
Figure 8. CE Propagation Delay Test Circuit
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 8). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low output-impedance driver.
4.5V to 5.5V
REGULATOR
TO µP NMI
LOW LINE
V
CC
C
HOLD
MAX807
Chip-Enable Output
In the enabled mode, the impedance of CE OUT is equiv-
alent to 75Ω in series with the source driving CE IN. In the
disabled mode, the 75Ω transmission gate is off and CE
C
> I
x t
HOLD LOAD SHDN
OUT is actively pulled to the higher of V
or V . This
BATT
CC
V
LR
source turns off when the transmission gate is enabled.
GND
Low-Line Comparator
The low-line comparator monitors V
with a threshold
CC
voltage typically 52mV above the reset threshold, with
13mV of hysteresis. Use LOW LINE to provide a non-
maskable interrupt (NMI) to the µP when power begins
to fall to initiate an orderly software shutdown routine.
Figure 9. Using LOW LINE to Provide a Power-Fail Warning to
the µP
In most battery-operated portable systems, reserve
energy in the battery provides ample time to complete
the shutdown routine once the low-line warning is
encountered, and before reset asserts. If the system must
worst-case shutdown time, the worst-case load current,
and the minimum low-line to reset threshold (V
),
LR(min)
calculate the amount of capacitance required to allow the
shutdown routine to complete before reset is asserted:
contend with a more rapid V
fall time—such as when
CC
C
HOLD
= (I
x t
) / V (min)
SHDN LR
LOAD
the main battery is disconnected, a DC-DC converter
where t
is the time required for the system to com-
SHDN
shuts down, or a high-side switch is opened during
plete the shutdown routine, and includes the V
to
CC
normal operation—use capacitance on the V
line to
CC
low-line propagation delay; and where I
is the cur-
LOAD
provide time to execute the shutdown routine (Figure 9).
First calculate the worst-case time required for the
system to perform its shutdown routine. Then, with the
rent being drained from the capacitor, V is the low-
LR
line to reset threshold.
______________________________________________________________________________________ 11
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
V
IN
V
V
CC
CC
R1
R2
R1
R2
MAX807
MAX807
PFI
PFO
PFI
PFO
MR
GND
GND
V
IN
V
CC
V
CC
PFO
PFO
V
IN
V
IN
V
L
V
TRIP
V
TRIP
V
H
0V
1
1
V
CC
R1
R1 + R2
R2
+
–
V
= R2 (V + V
PFT
)
TRIP
PFH
V
V
= V
PFT
(
)
CC
R1
TRIP
(
)
R1 R2
WHERE V
V
= 2.265V
= 20mV
PFT
PFH
1
1
V
R1 + R2
R2
+
–
V = R2 (V
PFT
)
L
= (V + V
)
(
)
H
PFT PFH
(
)
R1 R2
NOTE: V
V ARE NEGATIVE.
L
TRIP,
a)
b)
Figure 10. Using the Power-Fail Comparator to Monitor an Additional Power Supply: a) V is Negative, b) V is Positive
IN
IN
Power-Fail Comparator
PFI is the noninverting input to an uncommitted com-
parator. If PFI is less than V (2.265V), PFO goes low.
The power-fail comparator is intended to monitor the
preregulated input of the power supply, providing an
early power-fail warning so software can conduct an
orderly shutdown. It can also be used to monitor sup-
plies other than 5V. Set the power-fail threshold with a
resistor-divider, as shown in Figure 10.
FROM
REGULATED
SUPPLY
µP POWER
POWER TO
CMOS RAM
V
OUT
PFT
CC
0.1µF
0.1µF
MAX807
BATT
µP
2.8V
RESET
LOW LINE
WDI
RESET
NMI
I/O LINE
Power-Fail Input
PFI is the input to the power-fail comparator. The typical
comparator delay is 14µs from V to V (power failing),
GND
a)
IL
OL
and 32µs from V to V
(power being restored). If
unused, connect this input to ground.
IH
OH
µP POWER
POWER TO
CMOS RAM
Power-Fail Output
The Power-Fail Output (PFO) goes low when PFI goes
below V . It typically sinks 3.2mA with a saturation
V
OUT
CC
0.1µF
0.1µF
VOLTAGE
REGULATOR
PFT
MAX807
voltage of 0.1V. With PFI above V
, PFO is actively
PFT
BATT
µP
pulled to V . Connecting PFI through a voltage-
CC
2.8V
divider to a preregulated supply allows PFO to gener-
ate an NMI as the preregulated power begins to fall
(Figure 11b). If the preregulated supply is inaccessible,
use LOW LINE to generate the NMI (Figure 11a). The
LOW LINE threshold is typically 52mV above the reset
threshold (see the Low-Line Comparator section).
RESET
PFO
WDI
RESET
NMI
I/O LINE
PFI
GND
b)
Figure 11. a) If the preregulated supply is inaccessible, LOW
LINE generates the NMI for the µP. b) Use PFO to generate the
µP NMI if the preregulated supply is accessible.
12 ______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
Table 1. Input and Output Status in Battery-Backup Mode
PIN
1
NAME
PFI
FUNCTION
The power-fail comparator remains active in battery-backup mode for V
≥ 4V.
CC
2
PFO
The power-fail comparator remains active in battery-backup mode for V ≥ 4V. Below 4V, PFO is forced low.
CC
3
V
CC
Battery switchover comparator monitors V for active switchover.
CC
4
WDI
WDI is ignored and goes high impedance
5
6
GND
MR
Ground—0V reference for all signals
MR is ignored
7
LOW LINE
RESET
RESET
WDO
Logic low
8
Logic high; the open-circuit output voltage is equal to V
.
CC
9
Logic low
10
11
12
13
14
15
16
Logic high. The open-circuit output voltage is equal to V
Logic high. The open-circuit output voltage is equal to V
High impedance
.
CC
CE OUT
CE IN
.
.
BATT
BATT ON
BATT
Logic high. The open-circuit output voltage is equal to V
BATT
Supply current is 1µA maximum for V
≤ 2.8V.
exceeds 2.285V. Valid for V
BATT
BATT OK
OUT
Logic high when V
≥ 4V. Below 4V, BATT OK is forced low.
BATT
CC
OUT is connected to BATT through two internal PMOS switches in series.
Backup-Battery Input
The BATT input is similar to V , except the PMOS
CC
switch is much smaller. This input is designed to con-
duct up to 20mA to OUT during battery backup. The
on-resistance of the PMOS switch is approximately
13Ω. Figure 12 shows the two series pass elements
between the BATT input and OUT that facilitate UL
MAX807
P
V
CC
approval. V
can exceed V
during normal opera-
BATT
CC
tion without causing a reset.
CONTROL
CIRCUITRY
OUT
Output Supply Voltage
The output supply (OUT) transfers power from V or
0.1µF
CC
BATT to the µP, RAM, and other external circuitry. At
BATT
the maximum source current of 250mA, V
will typi-
P
P
OUT
cally be 260mV below V . Decouple this terminal with
CC
a 0.1µF capacitor.
BATT ON Output
The battery on (BATT ON) output indicates the status of
the internal battery switchover comparator, which con-
Figure 12. V
and BATT-to-OUT Switch
CC
Battery-Backup Mode
trols the internal V
and BATT switches. For V
CC
CC
Battery backup preserves the contents of RAM in the
event of a brownout or power failure. With a backup
battery installed at BATT, the MAX807 automatically
switches RAM to backup power when V
conditions are required for switchover to battery-back-
up mode: 1) V must be below the reset threshold; 2)
greater than V
(ignoring the small hysteresis
BATT
effect), BATT ON typically sinks 3.2mA at 0.4V. In bat-
tery-backup mode, this output sources approximately
5mA. Use BATT ON to indicate battery switchover sta-
tus, or to supply gate or base drive for an external pass
transistor for higher current applications (see the
Typical Operating Circuit).
falls. Two
CC
CC
V
must be below V
. Table 1 lists the status of
BATT
CC
inputs and outputs during battery-backup mode.
______________________________________________________________________________________ 13
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
SuperCap (e.g., order of 0.47F) and a simple charging
circuit as a backup source (Figure 13). Since V can
BATT OK Output
The BATT OK comparator monitors the backup battery
BATT
exceed V
while V
is above the reset threshold,
voltage, comparing it with a 2.265V reference (V
≥
CC
CC
CC
there are no special precautions when using these µP
supervisors with a SuperCap.
4V). BATT OK remains high as long as the backup bat-
tery voltage remains above 2.265V, signaling that the
backup battery has sufficient voltage to maintain the
memory of static RAM. When the battery voltage drops
below 2.265V, the BATT OK output drops low, signaling
that the backup battery needs to be changed.
Alternative Chip-Enable Gating
Using memory devices with CE and CE inputs allows
the MAX807 CE loop to be bypassed. To do this, con-
nect CE IN to ground, pull up CE OUT to OUT, and
connect CE OUT to the CE input of each memory
device (Figure 14). The CE input of each part then con-
nects directly to the chip-select logic, which does not
have to be gated by the MAX807.
Applications Information
The MAX807 is not short-circuit protected. Shorting
OUT to ground, other than power-up transients such as
charging a decoupling capacitor, may destroy the
device. If long leads connect to the IC’s inputs, ensure
that these lines are free from ringing and other condi-
tions that would forward bias the IC’s protection diodes.
Adding Hysteresis to the
Power-Fail Comparator
The power-fail comparator has a typical input hystere-
sis of 20mV. This is sufficient for most applications
where a power-supply line is being monitored through
an external voltage-divider (Figure 10).
There are two distinct modes of operation:
1) Normal Operating Mode, with all circuitry powered
up. Typical supply current from V
is 70µA, while
CC
only leakage currents flow from the battery.
Figure 15 shows how to add hysteresis to the power-fail
comparator. Select the ratio of R1 and R2 such that PFI
2) Battery-Backup Mode, where V is below V
CC
BATT
sees 2.265V when V falls to the desired trip point
IN
and V
. The supply current from the battery is typ-
RST
(V
TRIP
). Resistor R3 adds hysteresis. It will typically be
ically less than 1µA.
an order of magnitude greater than R1 or R2. The cur-
rent through R1 and R2 should be at least 1µA to
ensure that the 25nA (max) PFI input current does not
shift the trip point. R3 should be larger than 10kΩ to
prevent it from loading down the PFO pin. Capacitor C1
adds additional noise rejection.
Using SuperCaps or
MaxCaps with the MAX807
BATT has the same operating voltage range as V , and
CC
the battery-switchover threshold voltage is typically
V
V
when V
is decreasing or V
+ 0.06V when
BATT
CC
CC
BATT
is increasing. This hysteresis allows use of a
Rp*
CE
+5V
RAM 1
CE
OUT
CE IN
CE OUT
V
CC
1N4148
0.47F
CE
CE
RAM 2
RAM 3
RAM 4
BATT
OUT
CE
CE
MAX807
MAX807
GND
CE
CE
GND
*MAXIMUM Rp VALUE DEPENDS ON
THE NUMBER OF RAMs.
MINIMUM Rp VALUE IS 1kΩ.
ACTIVE-HIGH CE
LINES FROM LOGIC
Figure 14. Alternate CE Gating
Figure 13. SuperCap or MaxCap on BATT
14 ______________________________________________________________________________________
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
Backup-Battery ꢀeplacement
The backup battery may be disconnected while V
is
CC
START
above the reset threshold, provided BATT is bypassed
with a 0.1µF capacitor to ground. No precautions are
necessary to avoid spurious reset pulses.
SET
WDI
LOW
Negative-Going V
Transients
CC
While issuing resets to the µP during power-up, power-
down, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going V
CC
SUBROUTINE
OR PROGRAM LOOP,
SET WDI
transients (glitches). It is usually undesirable to reset
the µP when V experiences only small glitches.
CC
HIGH
The Typical Operating Characteristics show Maximum
Transient Duration vs. Reset Comparator Overdrive, for
which reset pulses are not generated. The graph was
RETURN
END
produced using negative-going V
pulses, starting at
CC
5V and ending below the reset threshold by the magni-
tude indicated (reset comparator overdrive). The graph
shows the maximum pulse width that a negative-going
V
transient may typically have without causing a
CC
reset pulse to be issued. As the amplitude of the tran-
sient increases (i.e., goes farther below the reset
threshold), the maximum allowable pulse width
decreases.
Figure 16. Watchdog Flow Diagram
A 0.1µF bypass capacitor mounted close to the V
pin provides additional transient immunity.
CC
Typically, a V
reset threshold and lasts for 3µs or less will not cause a
reset pulse to be issued.
transient that goes 40mV below the
CC
Watchdog Software Considerations
To help the watchdog timer keep a closer watch on soft-
ware execution, you can use the method of setting and
resetting the watchdog input at different points in the
program, rather than “pulsing” the watchdog input high-
low-high or low-high-low. This technique avoids a “stuck”
loop where the watchdog timer continues to be reset
within the loop, keeping the watchdog from timing out.
V
IN
+5V
R1
R2
V
CC
Figure 16 shows an example flow diagram where the
I/O driving the watchdog input is set high at the begin-
ning of the program, set low at the beginning of every
subroutine or loop, then set high again when the pro-
gram returns to the beginning. If the program should
“hang” in any subroutine, the I/O is continually set low
and the watchdog timer is allowed to time out, causing
a reset or interrupt to be issued.
PFI
C1*
R3
MAX807
PFO
GND
TO µP
*OPTIONAL
Maximum V
Fall Time
CC
+5V
PFO
0V
The V
fall time is limited by the propagation delay of
CC
the battery switchover comparator and should not
exceed 0.03V/µs. A standard rule for filter capacitance
on most regulators is on the order of 100µF per amp of
current. When the power supply is shut off or the main
0V
V
V
V
L
TRIP H
IN
V
R1 + R2
R2
V
V
= 2.265
TRIP
battery is disconnected, the associated initial V
fall
CC
rate is just the inverse or 1A / 100µF = 0.01V/µs. The
R2 || R3
V - 2.265 5 - 2.265 2.265
L
= 2.265 /
+
=
H
R1 + R2 R3
R1
R3
R2
V
CC
fall rate decreases with time as V falls exponen-
||
CC
tially, which more than satisfies the maximum fall-time
requirement.
Figure 15. Adding Hysteresis to the Power-Fail Comparator
______________________________________________________________________________________ 15
Full-Featured µP Supervisory Circuit with
±±1.5 ꢀeset Accuracy
Typical Operating Circuit
Ordering Information
PART†
TEMP RANGE
PIN-PACKAGE
16 Plastic DIP
16 TSSOP
MAX807_CPE
MAX807_CUE
MAX807_CWE
MAX807_EPE
MAX807_EUE
MAX807_EWE
MAX807_MJE
0°C to +70°C
+5V
0.1µF
0.1µF
0°C to +70°C
0°C to +70°C
16 Wide SO
16 Plastic DIP
16 TSSOP
REAL-
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
TIME
CLOCK
V
BATT
BATT ON
OUT
CC
CMOS
RAM
0.47F*
16 Wide SO
16 CERDIP
CE OUT
CE IN
OTHER
MR
SYSTEM
RESET
† This part offers a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
ADDRESS
DECODE
SOURCES
PUSH-
BUTTON
SWITCH
A0–A15
MAX807
WDI
I/O
RESET THRESHOLD (V)
SUFFIX
µP
NMI
LOW LINE
RESET
MIN
TYP
MAX
RESET
L
N
M
4.60
4.50
4.35
4.675
4.575
4.425
4.75
4.65
4.50
RESET
RESET
BATT OK
+12V
SUPPLY
INTERRUPT
PFO
+12V SUPPLY FAILURE
WATCHDOG FAILURE
WDO
PFI
GND
*
MaxCap.
___________________Chip Information
TRANSISTOR COUNT: 984
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