MAX8632 [MAXIM]
Integrated DDR Power-Supply Solution for Desktops,Notebooks, and Graphic Cards; 集成DDR电源方案，适用于台式机，笔记本电脑和图形卡
| 型号： | MAX8632 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Integrated DDR Power-Supply Solution for Desktops,Notebooks, and Graphic Cards |
| 文件： | 总29页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3623; Rev 0; 3/05
Integrated DDR Power-Supply Solution
for Desktops, Notebooks, and Graphic Cards
General Description
Features
The MAX8632 integrates a synchronous-buck PWM con-
Buck Controller
troller to generate V
, a sourcing and sinking LDO lin-
DDQ
♦ Quick-PWM with 100ns Load-Step Response
♦ Up to 95% Efficiency
ear regulator to generate V , and a 10mA reference
TT
output buffer to generate V . The buck controller drives
TTR
♦ 2V to 28V Input Voltage Range
two external n-channel MOSFETs to generate output volt-
ages down to 0.7V from a 2V to 28V input with output cur-
rents up to 15A. The LDO can sink or source up to 1.5A
continuous and 3A peak current. Both the LDO output
and the 10mA reference buffer output can be made to
track the REFIN voltage. These features make the
MAX8632 ideally suited for DDR memory applications in
desktops, notebooks, and graphic cards.
♦ 1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output
♦ Up to 600kHz Selectable Switching Frequency
♦ Programmable Current Limit with Foldback
Capability
♦ 1.7ms Digital Soft-Start
♦ Independent Shutdown and Standby Controls
♦ Overvoltage-/Undervoltage-Protection Option
The PWM controller in the MAX8632 utilizes Maxim’s
proprietary Quick-PWM™ architecture with programma-
ble switching frequencies of up to 600kHz. This control
scheme handles wide input/output voltage ratios with
ease and provides 100ns response to load transients
while maintaining high efficiency and a relatively con-
stant switching frequency. The MAX8632 offers fully pro-
grammable UVP/OVP and skip-mode options ideal in
portable applications. Skip mode allows for improved
efficiency at lighter loads.
♦ Power-Good Window Comparator
LDO Section
♦ Fully Integrated VTT and VTTR Capability
♦ VTT Has ±±A Sourcing/Sinking Capability
♦ Only 20µF Ceramic Capacitance Required for VTT
♦ VTT and VTTR Outputs Track V
/ 2
REFIN
♦ All-Ceramic Output-Capacitor Designs
♦ 1.0V to 2.8V Input Voltage Range
♦ Power-Good Window Comparator
The VTT and VTTR outputs track to within 1% of V
/ 2.
REFIN
The high bandwidth of this LDO regulator allows excel-
lent transient response without the need for bulk capac-
itors, thus reducing cost and size.
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
-40°C to +85°C 28 Thin QFN 5mm × 5mm
+Denotes lead-free packaging.
The buck controller and LDO regulators are provided with
independent current limits. Adjustable lossless foldback
current limit for the buck regulator is achieved by monitor-
ing the drain-to-source voltage drop of the low-side
MOSFET. Additionally, overvoltage and undervoltage pro-
tection mechanisms are built in. Once the overcurrent
condition is removed, the regulator is allowed to enter
soft-start again. This helps minimize power dissipation
during a short-circuit condition. The MAX8632 allows flex-
ible sequencing and standby power management using
the SHDN and STBY inputs, which support all DDR
operating states.
MAX8632ETI+
Pin Configuration
TOP VIEW
21 20 19 18 17 16 15
V
22
23
DD
14
13 VTTI
REFIN
PGND1
12
11
10
9
GND 24
VTT
The MAX8632 is available in a small 5mm × 5mm, 28-
pin thin QFN package.
25
26
27
28
SKIP
AV
PGND2
VTTR
VTTS
SS
MAX8632
DD
Applications
DDR I and DDR II Memory Power Supplies
Desktop Computers
Notebooks and Desknotes
Graphic Cards
SHDN
TPO
8
1
2
3
4
5
6
7
Game Consoles
RAID
5mm x 5mm THIN QFN
Networking
Typical Operating Circuit appears at end of data sheet.
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
to GND .............................................................-0.3V to +30V
VTTS to GND............................................-0.3V to (AV
PGND1, PGND2, TP0 to GND...............................-0.3V to +0.3V
REF Short Circuit to GND...........................................Continuous
+ 0.3V)
DD
SS, POK1, POK2, SKIP, ILIM, FB to GND ................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
28-Pin 5mm x 5mm Thin QFN (derate 35.7mW/°C
above +70°C).................................................................2.86W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
A
STBY, TON, REF, UVP/OVP to GND ........-0.3V to (AV
OUT, VTTR to GND ..................................-0.3V to (AV
DL to PGND1..............................................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
DH to LX....................................................-0.3V to (V
BST
LX to BST..................................................................-6V to +0.3V
LX to GND .................................................................-2V to +30V
VTT to GND...............................................-0.3V to (V
+ 0.3V)
VTTI
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +15V, V
= AV
= V
= STBY = V
= V
= 5V, V
= V
= V
= 2.5V, UVP/OVP = TP0 = FB = SKIP
VTTI
IN
DD
DD
SHDN
BST
ILIM
OUT
REFIN
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, V
= V , T = -40°C to +85°C, unless otherwise noted. Typical values
VTTS
VTT A
are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN PWM CONTROLLER
V
2
28
5.5
IN
Input Voltage Range
Output Adjust Range
V
V
V
, AV
DD
V
4.5
DD
0.7
5.5
OUT
FB = OUT
FB = GND
FB = V
0.693
2.47
1.78
0.7
2.5
1.8
1.7
194
243
352
516
300
25
0.707
2.53
1.82
Output Voltage Accuracy
(Note 2)
V
DD
Soft-Start Ramp Time
t
Rising edge of SHDN to full current limit
ms
SS
TON = GND (600kHz)
170
213
316
461
200
219
273
389
571
450
40
V
V
= 15V,
= 1.5V
IN
OUT
TON = REF (450kHz)
TON = open (300kHz)
On-Time
t
ns
ON
(Note 3)
TON = AV
(200kHz)
DD
Minimum Off-Time
t
(Note 3)
ns
µA
µA
OFF_MIN
V
V
Quiescent Supply Current
Shutdown Supply Current
I
IN
IN
IN
SHDN = GND
1
5
All on (PWM, VTT, and VTTR on)
2.5
1
5
AV
Quiescent Supply Current
I
mA
µA
DD
AVDD
STBY = GND (only VTTR and PWM on)
2
AV
+ V
Shutdown Supply
DD
DD
SHDN = GND
20
Current
Rising edge of V
Hysteresis
4.05
4.25
50
1
4.40
V
IN
AV Undervoltage-Lockout
Threshold
DD
mV
µA
V
Quiescent Supply Current
I
Set V = 0.8V
5
DD
VDD
FB
2
_______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(V = +15V, V
= AV
= V
= STBY = V
= V
= 5V, V
= V
= V
= 2.5V, UVP/OVP = TP0 = FB = SKIP
VTTI
IN
DD
DD
SHDN
BST
ILIM
OUT
REFIN
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, V
= V , T = -40°C to +85°C, unless otherwise noted. Typical values
VTTS
VTT A
are at T = +25°C.) (Note 1)
A
PARAMETER
REFERENCE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Reference Voltage
V
AV
= 4.5V to 5.5V; I = 0
REF
1.98
2
2.02
0.01
V
V
REF
DD
Reference Load Regulation
I
= 0 to 50µA
rising
REF
V
1.93
300
V
REF
REF Undervoltage Lockout
Hysteresis
mV
FAULT DETECTION
OVP Trip Threshold
(Referred to Nominal V
UVP/OVP = AV
112
65
116
70
120
75
%
%
%
DD
)
)
)
OUT
OUT
OUT
UVP Trip Threshold
(Referred to Nominal V
Lower level, falling edge, 1% hysteresis
Upper level, rising edge, 1% hysteresis
87
90
93
POK1 Trip Threshold
(Referred to Nominal V
107
110
113
POK2 Trip Threshold
(Referred to Nominal V
Lower level, falling edge, 1% hysteresis
Upper level, rising edge, 1% hysteresis
87.5
90
92.5
%
VTTS
107.5
110
112.5
and V
)
VTTR
POK2 Disable Threshold
(Measured at REFIN)
V
rising (hysteresis = 75mV typ)
0.7
10
0.9
40
V
REFIN
UVP Blanking Time
From rising edge of SHDN
20
10
ms
µs
OVP, UVP, POK_ Propagation
Delay
POK_ Output Low Voltage
POK_ Leakage Current
ILIM Adjustment Range
ILIM Input Leakage Current
I
= 4mA
0.3
1
V
SINK
V
= 5.5V, V = 0.8V, V = 1.3V
VTTS
µA
V
POK_
FB
V
0.25
2.00
0.1
ILIM
µA
Current-Limit Threshold (Fixed)
PGND1 to LX
45
170
-75
50
200
-60
55
235
-45
mV
mV
mV
Current-Limit Threshold
(Adjustable) PGND1 to LX
V
= 2V
ILIM
Current-Limit Threshold (Fixed,
Negative Direction) PGND1 to LX
SKIP = AV
DD
Current-Limit Threshold
(Adjustable, Negative Direction)
PGND1 to LX
SKIP = AV , V
= 2V
-250
3
mV
mV
DD ILIM
Zero-Crossing Detection
Threshold PGND1 to LX
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
+160
15
°C
°C
_______________________________________________________________________________________
±
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(V = +15V, V
= AV
= V
= STBY = V
= V
= 5V, V
= V
= V
= 2.5V, UVP/OVP = TP0 = FB = SKIP
VTTI
IN
DD
DD
SHDN
BST
ILIM
OUT
REFIN
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, V
= V , T = -40°C to +85°C, unless otherwise noted. Typical values
VTTS
VTT A
are at T = +25°C.) (Note 1)
A
PARAMETER
MOSFET DRIVERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DH Gate-Driver On-Resistance
V
- V = 5V
1
1
4
4
Ω
Ω
BST
LX
DL Gate-Driver On-Resistance in
High State
DL Gate-Driver On-Resistance in
Low State
0.5
3
Ω
DH falling to DL rising
DL falling to DH rising
30
50
Dead Time (Additional to
Adaptive Delay)
ns
INPUTS AND OUTPUTS
Rising edge
Hysteresis
1.20
-1
1.7
2.20
V
Logic Input Threshold
(SHDN, STBY, SKIP)
225
mV
Logic Input Current
(SHDN, STBY, SKIP)
+1
µA
Low (2.5V output)
High (1.8V output)
0.05
Dual-Mode™ Input Logic
Levels (FB)
V
2.1
Input Bias Current (FB)
-0.1
+0.1
µA
AV
0.4
-
DD
High
Four-Level Input Logic Levels
(TON, OVP/UVP)
Floating
REF
3.15
1.65
3.85
2.35
0.5
V
Low
Logic Input Current
(TON, OVP/UVP)
-3
+3
µA
kΩ
Ω
FB = GND
90
70
175
135
800
350
270
OUT Input Resistance
FB = AV
DD
FB adjustable mode
400
1600
OUT Discharge-Mode
On-Resistance
10
25
DL Turn-On Level During
Discharge Mode
0.01
0.1
0.20
V
(Measured at OUT)
Dual Mode is a trademark of Maxim Integrated Products, Inc.
4
_______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
ELECTRICAL CHARACTERISTICS (continued)
(V = +15V, V
= AV
= V
= STBY = V
= V
= 5V, V
= V
= V
= 2.5V, UVP/OVP = TP0 = FB = SKIP
VTTI
IN
DD
DD
SHDN
BST
ILIM
OUT
REFIN
= GND, PGND1 = PGND2 = LX = GND, TON = OPEN, V
= V , T = -40°C to +85°C, unless otherwise noted. Typical values
VTTS
VTT A
are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LINEAR REGULATORS (VTTR AND VTT)
VTTI Input Voltage Range
VTTI Supply Current
VTTI Shutdown Current
REFIN Input Impedance
REFIN Range
V
1
2.8
1
V
mA
µA
kΩ
V
VTTI
VTTI
I
I
= I
= 0
<0.1
20
VTT
VTTR
SHDN = GND
10
30
2.8
V
= 2.5V
12
1
REFIN
V
REFIN
VTT, VTTR UVLO Threshold
(Measured at OUT)
0.01
0.1
4
0.20
V
µA
Ω
Soft-Start Charge Current
I
V
= 0
SS
SS
VTT Internal MOSFET High-Side
On-Resistance
I
= -100mA, V
= 1.5V,
= 4.5V
VTT
VTTI
0.3
0.3
+1
AV
= 4.5V
DD
VTT Internal MOSFET Low-Side
On-Resistance
I
= 100mA, AV
Ω
%
%
VTT
DD
VTT Output Accuracy
V
= 1.5V or 2.5V, I
= 1mA
-1
3
REFIN
VTT
(Referred to V
/ 2)
REFIN
V
V
= 2.5V, I
= 1.5V, I
= 0 to 1.5A
= 0 to 1A
1.3
1.3
5
REFIN
REFIN
VTT
VTT Load Regulation
VTT
VTT Current Limit
VTTS Input Current
VTTR Output Error
VTT = 0 or VTTI
6.5
1
A
I
V
= 1.5V, VTT open
0.1
µA
VTTS
VTTS
V
= 1.5V or 2.5V, I
= 0
-1
+1
%
REFIN
VTTR
(Referred to V
/ 2)
REFIN
VTTR Current Limit
VTTR Bias Current
V
V
= 0 or V
18
32
50
4
mA
µA
VTTR
VTTI
= V
= 0
VTTI
0.6
REFIN
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-compara-
tor threshold by 50% of the ripple. In discontinuous conduction, the output voltage has a DC regulation level higher than the
trip level by approximately 1.5% due to slope compensation.
Note ±: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, V
= 5V,
BST
and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching speeds.
_______________________________________________________________________________________
5
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Typical Operating Characteristics
(V
VIN
= 12V, V
= 2.5V, TON = GND, SKIP = AV , circuit of Figure 8, T = +25°C, unless otherwise noted.)
OUT
DD
A
SWITCHING FREQUENCY vs. LOAD CURRENT
(TON = GND)
700
EFFICIENCY vs. LOAD CURRENT
(TON = GND)
EFFICIENCY vs. LOAD CURRENT
(TON = OPEN)
100
f
100
= 600kHz
f
= 300kHz
SW
SW
650
600
550
500
450
400
350
300
250
200
150
100
50
90
80
70
90
80
70
60
50
40
30
20
10
0
V
= 2.5V
OUT
V
= 2.5V
OUT
V
= 1.8V
60
50
40
V
= 1.8V
OUT
OUT
V
OUT
= 1.5V
V
OUT
= 1.5V
30
20
10
0
SKIP = GND
SKIP = AV
SKIP = GND
SKIP = AV
SKIP = GND
DD
DD
SKIP = AV
DD
0
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0
1
2
3
4
5
6
7
8
9 10 11 12
I
(A)
I
(A)
I
(A)
LOAD
LOAD
LOAD
SWITCHING FREQUENCY vs. INPUT VOLTAGE
(TON = GND)
SWITCHING FREQUENCY vs. TEMPERATURE
(TON = GND)
OUTPUT VOLTAGE
vs. LOAD CURRENT
700
700
2.540
2.535
2.530
2.525
2.520
2.515
2.510
2.505
2.500
2.495
2.490
680
660
640
620
600
580
560
540
520
500
480
460
440
420
400
V
IN
= 15V,
690
680
670
TON = GND
I
= 12A
LOAD
I
= 12A
LOAD
660
650
640
630
SKIP = GND
SKIP = AV
I
= 0A
LOAD
DD
620
610
600
4
6
8
10 12 14 16 18 20 22 24 26 28
(V)
-40 -25 -10
5
20 35 50 65 80
0
2
4
6
8
10
12
14
V
TEMPERATURE (°C)
I
(A)
IN
LOAD
VTTR VOLTAGE
vs. VTTR CURRENT
LINE REGULATION
(V vs. V )
VTT VOLTAGE
vs. VTT CURRENT
OUT
IN
MAX8632 toc07
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
1.18
0.93
0.92
0.91
0.90
0.89
0.88
0.87
0.86
0.85
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
V
= 0.9V
VTT
I
= 0A
LOAD
I
= 12A
LOAD
V
= 1.25V
VTT
0
-3
-2
-1
1
2
3
-15
-10
-5
0
5
10
15
4
6
8
10 12 14 16 18 20 22 24 26 28
(V)
I
(A)
I
(mA)
V
IN
VTT
VTTR
6
_______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Typical Operating Characteristics (continued)
(V
VIN
= 12V, V
= 2.5V, TON = GND, SKIP = AV , circuit of Figure 8, T = +25°C, unless otherwise noted.)
OUT DD A
LOAD TRANSIENT (BUCK)
LOAD TRANSIENT VTT (-1.5A TO +1.5A)
LOAD TRANSIENT VTT (-3A TO +3A)
MAX8632 toc12
MAX8632 toc11
MAX8632 toc10
I
= 1.5A, I
= 15mA
V
V
OUT
50mV/div
VTT
VTTR
OUT
V
OUT
50mV/div
100mV/div
I
= 12A, I
= 15mA
I
= 12A, I = 15mA
VTTR
LOAD
VTTR
LOAD
VTT
VTT
50mV/div
VTT
50mV/div
50mV/div
VTTR
50mV/div
VTTR
50mV/div
VTTR
50mV/div
0A
0A
I
LOAD
I
5A/div
VTT
I
VTT
0A
1A/div
2A/div
10µs/div
10µs/div
10µs/div
STARTUP AND SHUTDOWN INTO
HEAVY LOAD, DISCHARGE DISABLED
POWER-UP WAVEFORMS
POWER-DOWN WAVEFORMS
MAX8632 toc14
MAX8632 toc15
MAX8632 toc13
V
DD
= 5V, I
= 12A, I = 1.5A, I
= 15mA
VTTR
V
= 5V, I
= 12A, I = 1.5A, I
= 15mA
VTTR
LOAD
VTT
I
I
= 12A,
= 1.5A
DD
LOAD
VTT
LOAD
VTT
OUT
2V/div
OUT
2V/div
V
OUT
1V/div
0V
0V
VTT
0V
VTT
1V/div
1V/div
VTT
1V/div
0V
0V
0V
0V
0V
0V
VTTR
1V/div
VTTR
1V/div
SHDN
5V/div
0V
0V
V
IN
V
IN
POK1
5V/div
10V/div
10V/div
0V
1ms/div
200µs/div
200µs/div
STANDBY RESPONSE
VTT LOADED AT 10Ω TO GND
STARTUP AND SHUTDOWN INTO
LIGHT LOAD, DISCHARGE ENABLED
SHUTDOWN BY LOSS OF V
DD
MAX8632 toc16b
MAX8632 toc16a
MAX8632 toc17a
10V/div
SHDN
V
DD
4V
1.8V
2V/div
500mV/div
5V/div
STBY
1.8V
1.8V
0.9V
500mV/div
V
OUT
V
OUT
V
OUT
500mV/div
0.9V
0.9V
500mV/div
500mV/div
VTT
500mV/div
500mV/div
VTT
V
0.9V
DL
VTTR
0V
0A
VTTR
5V/div
I
OUT
5A/div
2ms/div
2ms/div
200µs/div
_______________________________________________________________________________________
7
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Typical Operating Characteristics (continued)
(V
VIN
= 12V, V
= 2.5V, TON = GND, SKIP = AV , circuit of Figure 8, T = +25°C, unless otherwise noted.)
OUT DD A
OVERVOLTAGE AND TURN-OFF
OF BUCK OUTPUT
STANDBY RESPONSE, VTT AT NO LOAD
MAX8632 toc18
MAX8632 toc17b
5V/div
STBY
V
OUT
1.8V
0.9V
1V/div
500mV/div
500mV/div
V
OUT
0V
0V
0V
VTT
V
LX
10V/div
0.9V
V
DL
500mV/div
VTTR
5V/div
40µs/div
2ms/div
SHORT CIRCUIT AND
SHORT CIRCUIT AND
RECOVERY OF V
RECOVERY OF V
SHORT CIRCUIT OF VTT
DDQ
DDQ
MAX8632 toc20
MAX8632 toc19
MAX8632 toc21
UVP ENABLED
UVP DISABLED, FOLDBACK CURRENT LIMIT
V
OUT
V
OUT
2V/div
2V/div
0V
VTT
1V/div
0V
I
LOAD
I
LOAD
10A/div
0V
0A
10A/div
0A
0A
V
V
IN
IN
10V/div
10V/div
0V
0A
0V
0A
I
VTT
I
5A/div
IN
I
IN
2A/div
2A/div
400µs/div
400µs/div
400µs/div
8
_______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Pin Description
PIN
NAME
FUNCTION
On-Time Selection-Control Input. This four-level logic input sets the nominal DH on-time. Connect to
GND, REF, AV , or leave TON unconnected to select the following nominal switching frequencies:
DD
TON = AV
(200kHz)
DD
1
TON
TON = open (300kHz)
TON = REF (450kHz)
TON = GND (600kHz)
Overvoltage-/Undervoltage-Protection Control Input. This four-level logic input enables or disables the
overvoltage and/or undervoltage protection. The overvoltage limit is 116% of the nominal output
voltage. The undervoltage limit is 70% of the nominal output voltage. Discharge mode is enabled when
OVP is also enabled. Connect the OVP/UVP pin to the following pins for the desired function:
OVP/
UVP
2
OVP/UVP = AV
(Enable OVP and discharge mode, enable UVP.)
DD
OVP/UVP = open (Enable OVP and discharge mode, disable UVP.)
OVP/UVP = REF (Disable OVP and discharge mode, enable UVP.)
OVP/UVP = GND (Disable OVP and discharge mode, disable UVP.)
+2.0V Reference Voltage Output. Bypass to GND with a 0.1µF (min) capacitor. REF can supply 50µA
for external loads. Can be used for setting voltage for ILIM. REF turns off when SHDN is low and
OUT < 0.1V.
3
4
REF
ILIM
Valley Current-Limit Threshold Adjustment for Buck Regulator. The current-limit threshold across PGND
and LX is 0.1 times the voltage at ILIM. Connect ILIM to a resistive divider, typically from REF to GND,
to set the current-limit threshold between 25mV and 200mV. This corresponds to a 0.25V to 2V range at
ILIM. Connect ILIM to AV to select the 50mV default current-limit threshold. See the Setting the
DD
Current Limit (Buck) section.
Buck Power-Good Open-Drain Output. POK1 is low when the buck output voltage is more than 10%
above or below the normal regulation point or during soft-start. POK1 is high impedance when the
output is in regulation and the soft-start circuit has terminated. POK1 is low in shutdown.
5
6
7
8
POK1
POK2
STBY
SS
LDO Power-Good Open-Drain Output. In normal mode, POK2 is low when either VTTR or VTTS is more
than 10% above or below the normal regulation point, which is typically REFIN / 2. In standby mode,
POK2 responds only to the VTTR input. POK2 is low in shutdown, and when V
is less than 0.8V.
REFIN
Standby. Connect to GND for low-quiescent mode where the VTT output is open circuit. POK2 takes
input from only VTTR in this mode. PWM output can be on or off, depending on the state of SHDN.
Soft-Start Control for VTT. Connect a capacitor (C9 in the Typical Applications Circuit of Figure 8) from
SS to ground. Leave SS open to disable soft-start. SS discharges to ground when VTT is off. See the
POR, UVLO, and Soft-Start section.
Sensing Pin for Termination Supply Output. Normally connected to VTT pin to allow accurate regulation
to half the REFIN voltage. Connected to a resistive divider from VTT to GND to regulate VTT to higher
than half the REFIN voltage.
9
VTTS
VTTR
10
Termination Reference Voltage. VTTR tracks V
/ 2.
REFIN
_______________________________________________________________________________________
9
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Pin Description (continued)
PIN
11
NAME
PGND2
VTT
FUNCTION
Power Ground for VTT and VTTR. Connect PGND2 externally to the underside of the exposed pad.
Termination Power-Supply Output. Connect VTT to VTTS to regulate to V / 2.
12
REFIN
Power-Supply Input Voltage for VTT and VTTR. Normally connected to the output of the buck regulator
for DDR application.
13
14
VTTI
REFIN
External Reference Input. This is used to regulate the VTT and VTTR outputs to V
/ 2.
REFIN
Feedback Input for Buck Output. Connect to AV
for a +1.8V fixed output or to GND for a +2.5V fixed
DD
15
FB
output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output
voltage. FB regulates to +0.7V.
Output-Voltage Sense Connection. Connect to the positive terminal of the buck output filter capacitor.
OUT senses the output voltage to determine the on-time for the high-side switching MOSFET (Q1 in the
Typical Applications Circuit of Figure 8). OUT also serves as the buck output’s feedback input in fixed-
output modes. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged
through an internal 10Ω resistor connected between OUT and GND. OUT also acts as the input to the
VTT and VTTR UVLO detector.
16
OUT
Input-Voltage Sense Connection. Connect to input power source. V is used only to set the PWM’s on-
IN
time one-shot timer. IN voltage range is from 2V to 28V.
17
18
19
V
IN
DH
LX
High-Side Gate-Driver Output. Swings from LX to BST. DH is low when in shutdown or UVLO.
External Inductor Connection. Connect LX to the input side of the inductor. LX is used for both current
limit and the return supply of the DH driver.
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode according to the
Typical Applications Circuit (Figure 8). See the Boost-Supply Diode and Capacitor Selection section.
20
21
22
BST
DL
Synchronous-Rectifier Gate-Driver Output. Swings from PGND to V
.
DD
Supply Input for the DL Gate Drive. Connect to the +4.5V to +5.5V system supply voltage. Bypass to
PGND1 with a 1µF (min) ceramic capacitor.
V
DD
23
24
PGND1
GND
Power Ground for Buck Controller. Connect PGND1 externally to the underside of the exposed pad.
Analog Ground for Both Buck and LDO. Connect GND externally to the underside of the exposed pad.
Pulse-Skipping Control Input. Connect to AV
enable pulse-skipping operation.
for low-noise, forced-PWM mode. Connect to GND to
DD
25
26
SKIP
Analog Supply Input for Both Buck and LDO. Connect to the +4.5V to +5.5V system supply voltage
with a series 10Ω resistor. Bypass to GND with a 1µF or greater ceramic capacitor.
AV
DD
Shutdown Control Input. Use to control buck output. A rising edge on SHDN clears the overvoltage-
27
28
—
SHDN
TP0
and undervoltage-protection fault latches (see Tables 2 and 3). Connect to AV
for normal operation.
DD
This is a test pin. Must connect to GND externally.
Exposed pad. The exposed pad must be star-connected to GND and PGND2. See Special Layout
Considerations for LDO Section for more details.
EP
10 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
IN
t
OFF
TRIG
MAX8632
Q
ONE-SHOT
ON-TIME
COMPUTE
OUT
TON
BST
DH
LX
t
ON
S
R
TRIG
Q
ONE-SHOT
Q
V
DD
DL
S
R
INTREF
Q
PGND
1.16 x INTREF
QUAD LEVEL
DECODE
ILIM
OVP/UVP
OVP/UVP
LATCH
BUCK ON/OFF
SHDN
TP0
V
- 1V
DD
1.0V
LX
SKIP
OUT
BIAS ON/OFF
SHUTDOWN
DECODER
20ms
TIMER
ZERO CROSSING
LX
STBY
0.7 x INTREF
VTT ON/OFF
VTTR ON/OFF
DISCHARGE
LOGIC
N
V
= 1.8V
OUT
INTREF + 10%
INTREF - 10%
V
= 2.5V
OUT
POK1
AV
DD
2V
GND
REF
REFERENCE
N
FB
DECODE
INTREF
FB
VTTS
10kΩ
10kΩ
REFIN
0.1V
OUT
REFIN / 2 + 10%
REFIN / 2 - 10%
REFIN/2
VTTI
VTT
V
DD
N
N
POK2
V
DD
POWER-DOWN
N
VTTI
CURRENT
LIMITS
VTT ILIM
PGND2
VTTR
PGND2
REFIN / 2 + 10%
REFIN / 2 - 10%
SS
Figure 1. Functional Diagram
______________________________________________________________________________________ 11
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
the IC. The current from the AV
and V
power
DD
DD
Detailed Description
supply must supply the current for the IC and the gate
drive for the MOSFETs. This maximum current can be
estimated as:
The MAX8632 combines a synchronous-buck PWM con-
troller, an LDO linear regulator, and a 10mA reference out-
put buffer. The buck controller drives two external
n-channel MOSFETs to deliver load currents up to 12A
and generate voltages down to 0.7V from a +2V to +28V
input. The LDO linear regulator can sink and source up to
1.5A continuous and 3A peak current with relatively fast
response. These features make the MAX8632 ideally
suited for DDR memory applications.
I
= I
+ I
+ f
× Q + Q
(
)
BIAS
VDD
AVDD
G1
G2
SW
where I
+ I
are the quiescent supply currents
VDD
and AV , Q
AVDD
DD
into V
and Q
are the total gate
G2
DD
G1
charges of MOSFETs Q1 and Q2 (at V
= 5V) in the
GS
Typical Applications Circuit of Figure 8, and f
switching frequency.
is the
SW
The MAX8632 buck regulator is equipped with a fixed
switching frequency of up to 600kHz using Maxim’s
proprietary constant on-time Quick-PWM architecture.
This control scheme handles wide input/output voltage
ratios with ease, and provides 100ns “instant-on”
response to load transients, while maintaining high effi-
ciency with relatively constant switching frequency.
Free-Running Constant-On-Time PWM
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant on-time, current-mode regulator
with voltage feed-forward (Figure 1). This architecture
relies on the output filter capacitor’s ESR to act as a
current-sense resistor, so the output ripple voltage pro-
vides the PWM ramp signal. The control algorithm is
simple: the high-side switch on-time is determined
solely by a one-shot whose pulse width is inversely pro-
portional to input voltage and directly proportional to
the output voltage. Another one-shot sets a minimum
off-time of 300ns (typ). The on-time one-shot is trig-
gered if the error comparator is low, the low-side switch
current is below the valley current-limit threshold, and
the minimum off-time one-shot has timed out.
The buck controller, LDO, and a reference output
buffer are provided with independent current limits.
Lossless foldback current limit in the buck regulator is
achieved by monitoring the drain-to-source voltage
drop of the low-side FET. The ILIM input is used to
adjust this current limit. Overvoltage protection, if
selected, is achieved by latching the low-side synchro-
nous FET on and the high-side FET off when the output
voltage is over 116% of its set output. It also features
an optional undervoltage protection by latching the
MOSFET drivers to the OFF state during an overcurrent
condition, when the output voltage is lower than 70% of
the regulated output. This helps minimize power dissi-
pation during a short-circuit condition.
On-Time One-Shot (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to input and output voltages. The high-side
switch on-time is inversely proportional to the input volt-
The current limit in the LDO and buffered reference out-
put buffer is 5A and 32mA, respectively, and neither
have the over- or undervoltage protection. When the
current limit in either output is reached, the output no
longer regulates the voltage, but regulates the current
to the value of the current limit.
age (V ) and is proportional to the output voltage:
IN
V
+ I
× R
(
)
OUT
LOAD DS(ON)Q2
t
= K ×
ON
V
IN
+5V Bias Supply (V
and AV
)
DD
DD
where K (the switching period) is set by the TON input
connection (Table 1) and R is the on-resis-
tance of the synchronous rectifier (Q2) in the Typical
Applications Circuit (Figure 8). This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. The benefits of a
constant switching frequency are twofold:
The MAX8632 requires an external +5V bias supply in
DS(ON)Q2
addition to the input voltage (V ). Keeping the bias sup-
IN
ply external to the IC improves the efficiency and elimi-
nates the cost associated with the +5V linear regulator
that would otherwise be needed to supply the PWM cir-
cuit and the gate drivers. If stand-alone capability is
needed, then the +5V supply can be generated with an
1) The frequency can be selected to avoid noise-sensi-
tive regions such as the 455kHz IF band.
external linear regulator such as the MAX1615. V
,
DD
AV , and IN can be connected together if the input
DD
source is a fixed +4.5V to +5.5V supply.
2) The inductor ripple-current operating point remains
relatively constant, resulting in an easy design
methodology and predictable output voltage ripple.
V
DD
is the supply input for the buck regulator’s MOSFET
drivers, and AV
supplies the power for the rest of
DD
12 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
The on-time one-shot has good accuracy at the operat-
for the default 50mV current-limit threshold), the com-
parator forces DL low (Figure 1). This mechanism caus-
es the threshold between pulse-skipping PFM and
nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation (also known as the critical
conduction point). The load-current level at which
ing points specified in the Electrical Characteristics
table (approximately 12.5% at 600kHz and 450kHz,
and 10% at 200kHz and 300kHz). On-times at operat-
ing points far removed from the conditions specified in
the Electrical Characteristics table can vary over a
wider range. For example, the 600kHz setting typically
runs approximately 10% slower with inputs much
greater than 5V due to the very short on-times required.
PFM/PWM crossover occurs, I
, is equal to
LOAD(SKIP)
half the peak-to-peak ripple current, which is a function
of the inductor value (Figure 2). This threshold is rela-
tively constant, with only a minor dependence on the
The constant on-time translates only roughly to a con-
stant switching frequency. The on-times guaranteed in
the Electrical Characteristics table are influenced by
resistive losses and by switching delays in the high-
side MOSFET. Resistive losses, which include the
inductor, both MOSFETs, the output capacitor’s ESR,
and any PC board copper losses in the output and
ground, tend to raise the switching frequency as the
load increases. The dead-time effect increases the
effective on-time, reducing the switching frequency as
one or both dead times are added to the effective on-
time. The dead time occurs only in PWM mode (SKIP =
input voltage (V ):
IN
⎛
⎞
V
× K
V
- V
V
IN
⎛
⎞
OUT
IN OUT
I
=
⎜
⎝
⎟
⎠
LOAD(SKIP)
⎜
⎟
2L
⎝
⎠
where K is the on-time scale factor (see Table 1). For
example, in the Typical Applications Circuit of Figure 8
(K = 1.7µs, V
= 2.5V, V = 12V, and L = 1µH), the
IN
OUT
pulse-skipping switchover occurs at:
⎛
⎞
⎛
V
) and during dynamic output-voltage transitions
2.5V × 1.7µs 12V - 2.5V
⎞
DD
=1.68A
⎜
⎟
⎟
⎠
⎜
when the inductor current reverses at light or negative
load currents. With reversed inductor current, the induc-
tor’s EMF causes LX to go high earlier than normal,
extending the on-time by a period equal to the DH-rising
dead time. For loads above the critical conduction point,
where the dead-time effect is no longer a factor, the
actual switching frequency is:
⎝
2 × 1µH
12V
⎝
⎠
The crossover point occurs at an even lower value if a
swinging (soft-saturation) inductor is used. The switching
waveforms can appear noisy and asynchronous when
light loading causes pulse-skipping operation, but this is
a normal operating condition that results in high light-
load efficiency. Trade-offs in PFM noise vs. light-load
efficiency are made by varying the inductor value.
Generally, low inductor values produce a broader effi-
ciency vs. load curve, while higher values result in higher
full-load efficiency (assuming that the coil resistance
V
+ V
DROP1
+ V
OUT
f
=
SW
t
V
(
)
ON IN DROP2
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including the synchro-
nous rectifier, the inductor, and any PC board resis-
Table 1. Approximate K-Factor Errors
tances; V
is the sum of the resistances in the
DROP2
MINIMUM V AT
IN
charging path, including the high-side switch (Q1 in the
Typical Applications Circuit of Figure 8), the inductor,
V
= 2.5V
OUT
TYPICAL K-FACTOR
(h = 1.5; SEE THE
DROPOUT
PERFORMANCE
(BUCK) SECTION)
and any PC board resistances, and t
is the one-shot
ON
TON SETTING
K-FACTOR
(µs)
ERROR
(%)
on-time (see the On-Time One-Shot (TON) section.
Automatic Pulse-Skipping Mode
(SKIP = GND)
200
(TON = AV
5.0
3.3
2.2
1.7
10
10
3.15
3.47
4.13
5.61
In skip mode (SKIP = GND), an inherent automatic
switchover to PFM takes place at light loads (Figure 2).
This switchover is affected by a comparator that trun-
cates the low-side switch on-time at the inductor cur-
rent’s zero crossing. The zero-crossing comparator
differentially senses the inductor current across the
synchronous-rectifier MOSFET (Q2 in the Typical
)
DD
300
(TON = open)
450
(TON = REF)
12.5
12.5
600
(TON = GND)
Applications Circuit of Figure 8). Once V
- V
LX
PGND
drops below 5% of the current-limit threshold (2.5mV
______________________________________________________________________________________ 1±
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
remains fixed) and less output voltage ripple. Penalties
for using higher inductor values include larger physical
size and degraded load-transient response, especially
at low input-voltage levels.
protection circuit, this current-limit method is effective in
almost every circumstance.
In forced-PWM mode, the MAX8632 also implements a
negative current limit to prevent excessive reverse induc-
tor currents when the buck regulator output is sinking
current. The negative current-limit threshold is set to
approximately 120% of the positive current limit and
DC output accuracy specifications refer to the threshold
of the error comparator. When the inductor is in continu-
ous conduction, the MAX8632 regulates the valley of the
output ripple, so the actual DC output voltage is higher
than the trip level by 50% of the output ripple voltage. In
tracks the positive current limit when V
is adjusted.
ILIM
The current-limit threshold is adjusted with an external
resistor-divider at ILIM. A 2µA to 20µA divider current is
recommended for accuracy and noise immunity.
discontinuous conduction (SKIP = GND and I
LOAD(SKIP)
<
LOAD
I
), the output voltage has a DC regulation
level higher than the error-comparator threshold by
approximately 1.5% due to slope compensation.
The current-limit threshold adjustment range is from
25mV to 200mV. In the adjustable mode, the current-
limit threshold voltage (from PGND1 to LX) is precisely
1/10th the voltage seen at ILIM. The threshold defaults
Forced-PWM Mode (SKIP = AV
)
DD
The low-noise forced-PWM mode (SKIP = AV ) dis-
DD
to 50mV when ILIM is connected to AV . The logic
DD
ables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gate-
drive waveform to constantly be the complement of the
high-side gate-drive waveform, so the inductor current
reverses at light loads while DH maintains a duty factor
threshold for switchover to the 50mV default value is
approximately AV
- 1V.
DD
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the differ-
ential current-sense signals seen between LX and GND.
of V
/ V . Forced-PWM mode keeps the switching
IN
OUT
frequency fairly constant. However, forced-PWM opera-
tion comes at a cost where the no-load V bias cur-
POR, UVLO, and Soft-Start
DD
Internal power-on reset (POR) occurs when AV
rises
DD
rent remains between 2mA and 20mA due to the
external MOSFET’s gate charge and switching frequen-
cy. Forced-PWM mode is most useful for reducing
audio frequency noise, improving load-transient
response, and providing sink-current capability for
dynamic output-voltage adjustment.
above approximately 2V, resetting the fault latch and
the soft-start counter, powering up the reference, and
preparing the buck regulator for operation. Until AV
DD
reaches 4.25V (typ), AV
undervoltage-lockout
DD
V
- V
L
∆I
∆t
Current-Limit Buck Regulator (ILIM)
IN
OUT
=
Valley Current Limit
The current-limit circuit for the buck regulator portion of
the MAX8632 employs a unique “valley” current-sensing
algorithm that senses the voltage drop across LX and
PGND1 and uses the on-resistance of the rectifying
MOSFET (Q2 in the Typical Applications Circuit of
Figure 8) as the current-sensing element. If the magni-
tude of the current-sense signal is above the valley cur-
rent-limit threshold, the PWM controller is not allowed to
initiate a new cycle (Figure 4). With valley current-limit
sensing, the actual peak current is greater than the val-
ley current-limit threshold by an amount equal to the
inductor current ripple. Therefore, the exact current-limit
characteristic and maximum load capability are a func-
tion of the current-sense resistance, inductor value, and
input voltage. When combined with the undervoltage-
I
PEAK
I
= I
/ 2
LOAD PEAK
0
ON-TIME
TIME
Figure 2. Pulse-Skipping/Discontinuous Crossover Point
14 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
MAX8632
TO PWM
CONTROLLER
(SEE FIGURE 1)
C
REF
REF
R
R
A
C
ILIM
ILIM
B
1.0V
V
DD
- 1V
LX
Figure 3. Adjustable Current-Limit Threshold
The buck regulator’s internal soft-start allows a gradual
increase of the current-limit level during startup to
reduce the input surge currents. The MAX8632 divides
the soft-start period into five phases. During the first
phase, the controller limits the current limit to only 20%
of the full current limit. If the output does not reach reg-
ulation within 425µs, soft-start enters the second phase,
and the current limit is increased by another 20%. This
process repeats until the maximum current limit is
reached, after 1.7ms, or when the output reaches the
nominal regulation voltage, whichever occurs first.
Adding a capacitor in parallel with the external ILIM
resistors creates a continuously adjustable analog soft-
start function for the buck regulator’s output.
I
I
I
PEAK
LOAD
LIMIT
I
LOAD(MAX)
LIR
2
I
LIM(VAL) =
1 -
x I
LOAD
( )
Soft-start in the LDO section can be realized by con-
necting a capacitor between the SS pin and ground.
When VTT is turned off or placed in standby mode, or
during thermal shutdown of the LDOs, the SS capacitor
is discharged. When VTT is turned on or when the ther-
mal limit is removed, an internal 4µA (typ) current
charges the SS capacitor. The resulting ramp voltage
on SS linearly increases the current-limit comparator
threshold to the VTT output, until full current limit is
attained when SS reaches approximately 1.6V. This
lowering of the current limit during startup limits the ini-
tial inrush current peaks, particularly when driving
capacitors. Choose the value of the SS capacitor
appropriately to set the soft-start time window. Leave
SS floating to disable the soft-start feature.
0
TIME
Figure 4. Valley Current-Limit Threshold
(UVLO) circuitry inhibits switching. The controller
inhibits switching by pulling DH low and holding DL low
when OVP and shutdown discharge are disabled
(OVP/UVP = REF or GND) or forcing DL high when OVP
and shutdown discharge are enabled (OVP/UVP =
or OPEN). See Table 3 for a detailed truth table
for OVP/UVP and shutdown settings. When AV
AV
DD
rises
DD
above 4.25V, the controller activates the buck regulator
and initializes the internal soft-start.
______________________________________________________________________________________ 15
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
by the load current and its output capacitance. The buck
regulator detects and latches the discharge-mode state
set by the OVP/UVP setting on startup.
Power-OK (POK1)
POK1 is an open-drain output for a window comparator
that continuously monitors V
. POK1 is actively held
OUT
low when SHDN is low and during the buck regulator
output’s soft-start. After the digital soft-start terminates,
POK1 becomes high impedance as long as the output
voltage is within 10% of the nominal regulation voltage
When OUT is discharging, both VTT and VTTR outputs
remain alive and continue to track REFIN until OUT
drops to 0.1V.
set by FB. When V
drops 10% below or rises 10%
STBY
The STBY input is an active-low input that is used to
shut down only the VTT output. When STBY is low, VTT
is high impedance.
OUT
above the nominal regulation voltage, the MAX8632
pulls POK1 low. Any fault condition forces POK1 low
until the fault latch is cleared by toggling SHDN or
cycling AV
power below 1V. For logic-level output
DD
Power-OK (POK2)
POK2 is the open-drain output for a window compara-
tor that continuously monitors the VTTS input and VTTR
output. POK2 is pulled low when REFIN is less than
0.8V. POK2 is high impedance as long as the output
voltage is within 10% of the nominal regulation voltage
voltages, connect an external pullup resistor between
POK1 and AV . A 100kΩ resistor works well in most
DD
applications. Note that the POK1 window detector is
completely independent of the overvoltage- and under-
voltage-protection fault detectors and the state of VTTS
and VTTR.
as set by REFIN. When V
or V
rises 10%
VTTR
VTTS
SHDN and Output Discharge
The SHDN input corresponds to the buck regulator and
places the buck regulator’s portion of the IC in a low-
power mode (see the Electrical Characteristics table).
SHDN is also used to reset a fault signal such as an
overvoltage or undervoltage fault.
above or 10% below its nominal regulation voltage, the
MAX8632 pulls POK2 low. For logic-level output volt-
ages, connect an external pullup resistor between
POK2 and AV . A 100kΩ resistor works well in most
DD
applications.
Current Limit (LDO for VTT
and VTTR Buffer)
When output discharge is enabled, (OVP/UVP = AV
DD
or open) and SHDN is pulled low, or if UVP is enabled
(OVP/UVP = AV ) and V falls to 70% of its regula-
The VTT output is a linear regulator that regulates the
DD
OUT
input (VTTI) to half the V
voltage. The feedback
REFIN
tion set point, the MAX8632 discharges the buck regu-
lator output (through the OUT input) through an internal
10Ω switch to ground. While the output is discharging,
DL is forced low and the PWM controller is disabled but
the reference remains active to provide an accurate
threshold. Once the output voltage drops below 0.1V,
the MAX8632 shuts down the reference and DL
remains low.
point for VTT is at the VTTS input (Figure 1). VTT is
capable of sinking and sourcing at least 1.5A of continu-
ous current and 3A peak current. The current limit for
VTT and VTTR is typically 5A and 32mA, respective-
ly. When the current limit for either output is reached,
the outputs regulate the current, not the voltage.
Fault Protection
The MAX8632 provides overvoltage/undervoltage fault
protection in the buck controller. Select OVP/UVP to
enable and disable fault protection as shown in Table 3.
Once activated, the controller continuously monitors the
output for undervoltage and overvoltage fault conditions.
When output discharge is disabled (OVP/UVP = REF or
GND), the controller does not actively discharge the
buck output and the DL driver remains low. Under these
conditions, the buck output discharge rate is determined
Table 2. Shutdown and Standby Control Logic
SHDN
AV
STBY
AV
BUCK OUTPUT (V
)
VTT
VTTR
DDQ
*
*
DD
ON
ON
ON
ON
ON
DD
AV **
DD
GND**
X
OFF (high impedance)
OFF (tracking 0.5 REFIN)
GND***
OFF
OFF (tracking 0.5 REFIN)
*For DDR application, this is referred as S0 state, where all outputs are on.
**For DDR application, this is referred as S3 state, where V and VTTR are kept on, but VTT is turned off (high impedance).
DDQ
***For DDR application, this is referred as S4/S5 states, where all outputs are off. Discharge mode should be selected (OVP/UVP =
AV or OPEN, see Table 3) to discharge the outputs.
DD
16 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Overvoltage Protection (OVP)
When the output voltage rises above 116% of the nomi-
nal regulation voltage and OVP is enabled (OVP/UVP =
Thermal Fault Protection
The MAX8632 features two thermal-fault-protection cir-
cuits. One monitors the buck-regulator portion of the IC
and the other monitors the linear regulator (VTT) and
the reference buffer output (VTTR). When the junction
temperature of the buck-regulator portion of the
MAX8632 rises above +160°C, a thermal sensor acti-
vates the fault latch, pulls POK1 low, and shuts down
the buck-controller output using discharge mode
regardless of the OVP/UVP setting. Toggle SHDN or
AV
or open), the OVP circuit sets the fault latch,
DD
shuts down the PWM controller, and immediately pulls
DH low and forces DL high. This turns on the synchro-
nous-rectifier MOSFET (Q2 in the Typical Applications
Circuit of Figure 8) with a 100% duty cycle, rapidly dis-
charging the output capacitor and clamping the output
to ground. Once the output reaches 0.1V, DL is
switched off, preventing the possibility of a negative
cycle AV
below 1V to reactivate the controller after
DD
voltage on the output. Toggle SHDN or cycle AV
the junction temperature cools by 15°C. If the VTT and
VTTR regulator portion of the IC has its die temperature
rise above +160°C, then VTT and VTTR shut off, go
high impedance, and restart after the die portion of the
IC cools by 15°C. Both thermal faults are independent.
For example, if the VTT output is overloaded to the
point that it triggers its thermal fault, the buck regulator
continues to function.
DD
below 1V to clear the fault latch and restart the con-
troller. OVP is disabled when OVP/UVP is connected to
REF or GND (see Table 3). OVP only applies to the
buck output. The VTT and VTTR outputs do not have
overvoltage protection.
Undervoltage Protection (UVP)
When the output voltage drops below 70% of its regula-
tion voltage while UVP is enabled, the controller sets
the fault latch and begins the discharge mode (see the
SHDN and Output Discharge section). When the output
voltage drops to 0.1V, the synchronous rectifier (Q2 in
the Typical Applications Circuit) turns on and clamps
the buck output to GND. UVP is ignored for at least
10ms (min) after startup or after a rising edge on
Design Procedure
Firmly establish the input voltage range (V ) and maxi-
IN
mum load current (I
) in the buck regulator before
LOAD
choosing a switching frequency and inductor operating
point (ripple current ratio or LIR). The primary design
trade-off lies in choosing a good switching frequency
and inductor operating point, and the following four fac-
tors dictate the rest of the design:
SHDN. Toggle SHDN or cycle AV
power below 1V to
DD
clear the fault latch and restart the controller. UVP is
disabled when OVP/UVP is left open or connected to
GND (see Table 3). UVP only applies to the buck out-
put. The VTT and VTTR outputs do not have undervolt-
age protection.
• Input Voltage Range. The maximum value (V
)
IN(MAX)
must accommodate the worst-case voltage. The mini-
mum value (V ) must account for the lowest
IN(MIN)
voltage after drops due to connectors and fuses. If
there is a choice, lower input voltages result in better
efficiency.
Table ±. OVP/UVP Fault Protection
OVP/UVP
DISCHARGE
UVP PROTECTION
OVP PROTECTION
Yes.
AV
Output is discharged through an
internal 10Ω resistance.
Enabled
Disabled
Enabled
DD
Yes.
Output is discharged through an
internal 10Ω resistance.
OPEN
Enabled
No.
REF
Enabled
Disabled
Disabled
Disabled
DL forced low when SHDN is low.
No.
GND
DL forced low when SHDN is low.
______________________________________________________________________________________ 17
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
• Maximum Load Current. There are two values to con-
sider. The peak load current (I ) determines the
where V is 0.7V, R and R are shown in Figure 6,
FB
C
D
and V
is:
PEAK
RIPPLE
instantaneous component stresses and filtering
requirements and thus drives output capacitor selec-
tion, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current
V
= LIR × I
× R
RIPPLE
LOAD(MAX) ESR
Setting the VTT and VTTR Voltages (LDO)
The termination power-supply output (VTT) can be set by
two different methods. First, the VTT output can be con-
nected directly to the VTTS input to force VTT to regulate
REFIN
higher than V
from VTT to VTTS. The maximum value for VTT is V
DROPOUT
= +85°C.
(I
) determines the thermal stresses and thus
LOAD
drives the selection of input capacitors, MOSFETs,
and other critical heat-contributing components.
• Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses proportion-
to V
/ 2. Secondly, VTT can be forced to regulate
/ 2 by connecting a resistive divider
REFIN
-
A
VTTI
V
where V
= I
× 0.3Ω (max) at T
DROPOUT
VTT
al to frequency and V 2. The optimum frequency is
IN
also a moving target due to rapid improvements in
MOSFET technology that are making higher frequen-
cies more practical.
The termination reference voltage (VTTR) tracks 0.5
REFIN
V
.
Inductor Selection (Buck)
• Inductor Operating Point. This choice provides trade-
offs: size vs. efficiency and transient response vs. out-
put ripple. Low inductor values provide better
transient response and smaller physical size but also
result in lower efficiency and higher output ripple due
to increased ripple currents. The minimum practical
inductor value is one that causes the circuit to operate
at the edge of critical conduction (where the inductor
current just touches zero with every cycle at maximum
load). Inductor values lower than this grant no further
size-reduction benefit. The optimum operating point is
usually found between 20% and 50% ripple current.
When pulse skipping (SKIP = low at light loads), the
inductor value also determines the load-current value
at which PFM/PWM switchover occurs.
The switching frequency and inductor operating point
determine the inductor value as follows:
V
V
- V
(
)
OUT
IN OUT
L =
V
× f
× I
× LIR
IN
SW
LOAD(MAX)
For example: I
= 12A, V = 12V, V
=
OUT
LOAD(MAX)
IN
2.5V, f
= 600kHz, 30% ripple current or LIR = 0.3:
SW
2.5V (12V - 2.5V)
12V × 600kHz × 12A × 0.3
L =
≈1µH
Setting the Output Voltage (Buck)
OUT
MAX8632
TO
ERROR
AMPLIFIER
Preset Output Voltages
The MAX8632 dual-mode operation allows the selection
of common voltages without requiring external compo-
nents (Figure 5). Connect FB to GND for a fixed 2.5V
1.8V
(FIXED)
FB
output, to AV
for a fixed 1.8V output, or connect FB
DD
directly to OUT for a fixed 0.7V output.
2.5V
(FIXED)
REF (2.0V)
Setting the Buck Regulator Output (V
) with a
OUT
Resistive Voltage-Divider at FB
The buck-regulator output voltage can be adjusted from
0.7V to 5.5V using a resistive voltage-divider (Figure 6).
The MAX8632 regulates FB to a fixed reference voltage
(0.7V). The adjusted output voltage is:
⎛
⎞
R
R
V
RIPPLE
C
V
= V
1 +
+
OUT
FB
0.1V
⎜
⎟
2
⎝
⎠
D
Figure 5. Dual-Mode Feedback Decoder
18 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
second stage of a two-stage power conversion system,
tantalum input capacitors are acceptable. In either con-
figuration, choose a capacitor that has less than 10°C
temperature rise at the RMS input current for optimal
reliability and lifetime.
V
L
OUT
LX
C
OUT
MAX8632
DL
PGND1
GND
Q2
Output Capacitor Selection (Buck)
The output filter capacitor must have low enough equiv-
alent series resistance (R
) to meet output ripple and
ESR
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
OUT
For processor core voltage converters and other appli-
cations in which the output is subject to violent load
transients, the output capacitor’s size depends on how
R
C
D
much R
is needed to prevent the output from dip-
ESR
FB
ping too low under a load transient. Ignoring the sag
due to finite capacitance:
R
V
STEP
LOAD(MAX)
R
≤
ESR
∆I
Figure 6. Setting V
with a Resistive Voltage-Divider
OUT
In applications without large and fast load transients,
the output capacitor’s size often depends on how much
ESR
put voltage ripple. The output ripple voltage of a step-
down controller is approximately equal to the total
inductor ripple current multiplied by the output capaci-
Find a low-loss inductor with the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at frequencies up
to 200kHz. The core must be large enough not to satu-
R
is needed to maintain an acceptable level of out-
rate at the peak inductor current (I
):
tor’s R
. Therefore, the maximum R
required to
ESR
PEAK
ESR
meet ripple specifications is:
LIR
2
⎛
⎝
⎞
I
= I
1 +
⎜
⎟
⎠
PEAK
LOAD(MAX)
V
RIPPLE
R
≤
ESR
I
× LIR
LOAD(MAX)
Most inductor manufacturers provide inductors in stan-
dard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc.
Also look for nonstandard values, which can provide a
better compromise in LIR across the input voltage range.
If using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values.
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OSCONs, polymers, and other electrolytics).
Input Capacitor Selection (Buck)
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
The input capacitor must meet the ripple current
requirement (I
) imposed by the switching currents:
capacity needed to prevent V
and V
from
SOAR
RMS
SAG
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
V
V
- V
(
)
OUT IN
OUT
I
= I
LOAD
RMS
V
IN
is no longer a problem (see the V
and V
equa-
SOAR
SAG
tions in the Transient Response (Buck) section).
However, low-capacity filter capacitors typically have
high-ESR zeros that can affect the overall stability (see
the Stability Requirements section).
I
has a maximum value of I
OUT
/ 2 when V = 2 ×
RMS
V
LOAD IN
. For most applications, nontantalum capacitors
(ceramic, aluminum, POS, or OSCON) are preferred
due to their resistance to power-up surge currents typi-
cal of systems with a mechanical switch or connector in
series with the input. If the MAX8632 is operated as the
______________________________________________________________________________________ 19
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Stability Requirements
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching fre-
quency. The boundary of instability is given by the fol-
lowing equation:
VTT Output Capacitor Selection (LDO)
A minimum value of 20µF is needed to stabilize the VTT
output. This value of capacitance limits the regulator’s
unity-gain bandwidth frequency to approximately 1.8MHz
(typ) to allow adequate phase margin for stability. To
keep the capacitor acting as a capacitor within the regu-
lator’s bandwidth, it is important that ceramic caps with
low ESR and ESL be used.
f
SW
π
f
≤
ESR
Since the gain bandwidth is also determined by the
transconductance of the output FETs, which increases
with load current, the output capacitor may need to be
greater than 20µF if the load current exceeds 1.5A, but
can be smaller than 20µF if the maximum load current
is less than 1.5A. As a guideline, choose the minimum
capacitance and maximum ESR for the output capaci-
tor using the following:
where:
1
f
=
ESR
2π × R
× C
OUT
ESR
If C
OUT
consists of multiple same-value capacitors, as
in the Typical Applications Circuit of Figure 8, the f
remains the same as that of a single capacitor.
ESR
For a typical 600kHz application, the ESR zero frequen-
cy must be well below 190kHz, preferably below
100kHz. Two 150µF/4V Sanyo POS capacitors are used
I
LOAD
C
= 20µF ×
= 5mΩ ×
OUT_MIN
1.5A
to provide 12mΩ (max) of R
. This results in a zero at
ESR
1.5A
42kHz, well within the bounds of stability.
R
ESR_MAX
I
LOAD
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
R
value is measured at the unity-gain-bandwidth
ESR
frequency given by approximately:
36
I
LOAD
1.5A
f
=
×
GBW
C
OUT
Once these conditions for stability are met, additional
capacitors, including those of electrolytic and tantalum
types, can be connected in parallel to the ceramic
capacitor (if desired) to further suppress noise or volt-
age ripple at the output.
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and fast-feed-
back loop instability. Double pulsing occurs due to
noise on the output or because the ESR is so low that
there is not enough voltage ramp in the output voltage
signal. This “fools” the error comparator into triggering
a new cycle immediately after the 400ns minimum off-
time period has expired.
VTTR Output Capacitor Selection (LDO)
The VTTR buffer is a scaled-down version of the VTT
regulator, with much smaller output transconductance.
Its compensation cap can therefore be smaller, and its
ESR larger, than what is required for its larger counter-
part. For typical applications requiring load current up
to 15mA, a ceramic cap with a minimum value of 1µF
Double pulsing is more annoying than harmful, result-
ing in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped but can
cause the output voltage to rise above or fall below the
tolerance limits. The easiest method for checking stabil-
ity is to apply a very fast zero-to-max load transient and
carefully observe the output-voltage-ripple envelope for
overshoot and ringing. It can help to simultaneously
monitor the inductor current with an AC current probe.
Do not allow more than one cycle of ringing after the
initial step-response under/overshoot.
is recommended (R
< 0.3Ω). Connect this cap
between VTTR and the analog ground plane.
ESR
VTTI Input Capacitor Selection (LDO)
Both the VTT and VTTR output stages are powered
from the same VTTI input. Their output voltages are ref-
erenced to the same REFIN input. The value of the VTTI
bypass capacitor is chosen to limit the amount of rip-
ple/noise at VTTI, or the amount of voltage dip during a
load transient. Typically VTTI is connected to the output
of the buck regulator, which already has a large bulk
20 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
capacitor. Nevertheless, a ceramic capacitor of at least
10µF must be used and must be added and placed as
close as possible to the VTTI pin. This value must be
increased with larger load current, or if the trace from
the VTTI pin to the power source is long and has signifi-
cant impedance. Furthermore, to prevent undesirable
VTTI bounce from coupling back to the REFIN input
and possibly causing instability in the loop, the REFIN
pin should ideally tap its signal from a separate low-
impedance DC source rather than directly from the
VTTI input. If the latter is unavoidable, increase the
amount of bypass capacitance at the VTTI input and
add additional bypass at the REFIN pin.
Use R
at T
:
DS(ON)
J(MAX)
P
= 2I
× V × t
× f
DT SW
LSDC
LOAD
F
where V is the body-diode forward-voltage drop, t is
F
DT
the dead time (≈30ns), and f
is the switching fre-
SW
quency. Because of the zero-voltage switch operation,
the low-side MOSFET gate-drive loss occurs as a result
of charging and discharging the input capacitance,
(C ). This loss is distributed among the average DL
ISS
gate-driver’s pullup and pulldown resistance, R
DL
) of the
(≈1Ω), and the internal gate resistance (R
GATE
MOSFET (≈2Ω). The drive power dissipated is given by:
MOSFET Selection (Buck)
The MAX8632 drives external, logic-level, n-channel
MOSFETs as the circuit-switch elements. The key
selection parameters:
R
2
GATE
P
= C
× V
× f
×
LSDR
ISS
GS
SW
R
+ R
GATE
DL
On-resistance (R
): the lower, the better.
DS(ON)
The high-side MOSFET operates as a duty-cycle control
switch and has the following major losses:
Maximum drain-to-source voltage (V
at least 20% higher than input supply rail at the high-
side MOSFET’s drain.
): should be
DSS
• The channel-conduction loss (P
)
HSCC
• The VI overlapping switching loss (P
)
HSSW
Gate charges (Q , Q , Q ): the lower the better.
G
GD
GS
• The drive loss (P
)
HSDR
Choose MOSFETs with rated R
at V
= 4.5V.
GS
DS(ON)
(The high-side MOSFET does not have body-diode
conduction loss because the diode never conducts
current):
For a good compromise between efficiency and cost,
choose the high-side MOSFET that has a conduction
loss equal to its switching loss at nominal input voltage
and maximum output current (see below). For the low-
side MOSFET, make sure that it does not spuriously
turn on because of dV/dt caused by the high-side
MOSFET turning on, as this results in shoot-through
current degrading efficiency. MOSFETs with a lower
V
V
2
OUT
P
=
× I
× R
DS(ON)
HSCC
LOAD
IN
Use R
at T
:
DS(ON)
J(MAX)
Q
to Q ratio have higher immunity to dV/dt.
GS
GD
For proper thermal-management design, calculate the
power dissipation at the desired maximum operating
junction temperature, maximum output current, and
worst-case input voltage. For the low-side MOSFET, the
Q
+ Q
GD
GS
I
P
= V × I
× f
×
HSSW
IN
LOAD
SW
GATE
where I
determined by:
is the average DH-driver output current
GATE
worst case is at V
. For the high-side MOSFET,
IN(MAX)
the worst case could be at either V
or V
.
IN(MIN)
IN(MAX)
The high-side MOSFET and low-side MOSFET have dif-
ferent loss components due to the circuit operation.
The low-side MOSFET operates as a zero-voltage
switch; therefore, major losses are:
2.5V
+ R
I
=
GATE(ON)
R
DH
GATE
where R
is the high-side MOSFET driver’s on-resis-
DH
• The channel-conduction loss (P
)
LSCC
tance (1Ω typ) and R
is the internal gate resis-
GATE
tance of the MOSFET (≈2Ω):
= Q × V × f ×
SW
• The body-diode conduction loss (P
)
LSDC
• The gate-drive loss (P ):
LSDR
R
GATE
P
HSDR
G
GS
⎛
⎞
R
+ R
V
V
GATE
DH
2
OUT
P
=
1 -
× I
× R
DS(ON)
LSCC
LOAD
⎜
⎟
⎝
⎠
IN
______________________________________________________________________________________ 21
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
where V
= V
= 5V. In addition to the losses above,
The power loss of the snubber circuit (P
) is dissi-
GS
DD
RSNUB
allow about 20% more for additional losses because of
MOSFET output capacitances and low-side MOSFET
body-diode reverse-recovery charge dissipated in the
high-side MOSFET that is not well defined in the
MOSFET data sheet. Refer to the MOSFET data sheet
for thermal-resistance specifications to calculate the PC
board area needed to maintain the desired maximum
operating junction temperature with the above-calculat-
ed power dissipations. To reduce EMI caused by
switching noise, add a 0.1µF ceramic capacitor from the
high-side switch drain to the low-side switch source, or
add resistors in series with DH and DL to slow down the
switching transitions. Adding series resistors increases
the power dissipation of the MOSFET, so ensure that
this does not overheat the MOSFET.
pated in the resistor and can be calculated as:
2
P
= C
× V
× f
SW
RSNUB
SNUB
IN
where V is the input voltage and f
is the switching
IN
SW
frequency. Choose an R
power rating that meets
SNUB
the specific application’s derating rule for the power
dissipation calculated.
Setting the Current Limit (Buck)
The current-sense method used in the MAX8632 makes
use of the on-resistance (R
) of the low-side
DS(ON)
MOSFET (Q2 in the Typical Applications Circuit of Figure
8). When calculating the current limit, use the worst-case
maximum value for R
from the MOSFET data
DS(ON)
sheet, and add some margin for the rise in R
with
DS(ON)
MOSFET Snubber Circuit (Buck)
Fast switching transitions cause ringing because of a
resonating circuit formed by the parasitic inductance
and capacitance at the switching nodes. This high-fre-
quency ringing occurs at LX’s rising and falling transi-
tions and can interfere with circuit performance and
generate EMI. To dampen this ringing, an optional
series RC snubber circuit is added across each switch.
Below is a simple procedure for selecting the value of
the series RC of the snubber circuit:
temperature. A good general rule is to allow 0.5% addi-
tional resistance for each 1°C of temperature rise.
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
half the ripple current; therefore:
minus
LOAD(MAX)
I
× LIR
⎛
⎞
LOAD(MAX)
I
> I
-
LIM(VAL)
LOAD(MAX)
⎜
⎟
2
⎝
⎠
1) Connect a scope probe to measure V to PGND1,
LX
and observe the ringing frequency, f .
R
where I
equals the minimum valley current-limit
LIM(VAL)
2) Estimate the circuit parasitic capacitance (C
) at
PAR
threshold voltage divided by the on-resistance of Q2
LX by first finding a capacitor value, which, when
connected from LX to PGND1, reduces the ringing
(R
). For the 50mV default setting, connect ILIM
DS(ON)Q2
to AV . In adjustable mode, the valley current-limit
DD
frequency by half. C
can then be calculated as
PAR
threshold is precisely 1/10th* the voltage seen at ILIM.
For an adjustable threshold, connect a resistive divider
from REF to GND with ILIM connected to the center tap.
The external 250mV to 2V adjustment range corresponds
to a 25mV to 200mV valley current-limit threshold. When
adjusting the current limit, use 1% tolerance resistors and
a divider current of approximately 10µA to prevent signifi-
cant inaccuracy in the valley current-limit tolerance.
1/3rd the value of the capacitor value found.
3) Estimate the circuit parasitic inductance (LPAR) from
the equation:
1
2
L
=
PAR
2π × f
(
× C
PAR
)
R
4) Calculate the resistor for critical dampening (R
)
SNUB
. Adjust
Foldback Current Limit
Alternately, foldback current limit can be implemented
if the UVP latch option is not available. Foldback cur-
rent limit reduces the power dissipation of external
components so they can withstand indefinite overload
and short circuit, with automatic recovery after the over-
load or short circuit is removed. To implement foldback
from the equation: R
= 2π × f x L
SNUB
R
PAR
the resistor value up or down to tailor the desired
damping and the peak voltage excursion.
5) The capacitor (C
) should be at least 2 to 4
to be effective.
SNUB
times the value of C
PAR
current limit, connect a resistor from V
to ILIM (R6
OUT
in Figure 7 and in the Typical Applications Circuit of
Figure 8), in addition to the resistor-divider network (R4
*In the negative direction, the adjustable current limit is typically
-1/8th the voltage seen at ILIM.
22 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
and R5) used for setting the adjustable current limit as
6) Then R6 can be calculated as:
shown in Figure 7.
V
× R4 × R56
OUT
The following is a procedure for calculating the value of
R4, R5, and R6:
R6 =
⎡
⎤
⎥
⎥
V
- V
-V
× R4-
(
)
(
OUT
ILIM(NOM) ILIM(0V)
)
⎢
⎢
1) Calculate the voltage, V
, required at ILIM
ILIM(NOM)
when the output voltage is at nominal:
V
− V
× R56
⎢
(
)
⎥
⎦
(
ILIM(NOM)
ILIM(0V)
)
⎣
LIR
2
⎛
⎝
⎞
7) Then R5 is calculated as:
V
= 10 × I
× 1-
⎜
⎟
⎠
ILIM(NOM)
LOAD(MAX)
R6 × R56
R6 - R56
× R
DS(ON)Q2
R5 =
2) Pick a percentage of foldback, PFB, from 15%
to 40%.
Boost-Supply Diode and
3) Calculate the voltage, V
, when the output is
= P × V
FB ILIM(NOM)
ILIM(0V)
Capacitor Selection (Buck)
A low-current Schottky diode, such as the CMDSH-3
from Central Semiconductor, works well for most appli-
cations. Do not use large-power diodes, because high-
er junction capacitance can charge up the voltage at
BST to the LX voltage and this exceeds the absolute
maximum rating of 6V. The boost capacitor should be
0.1µF to 4.7µF, depending on the input and output volt-
ages, external components, and PC board layout. The
boost capacitance should be as large as possible to
prevent it from charging to excessive voltage, but small
enough to adequately charge during the minimum low-
side MOSFET conduction time, which happens at maxi-
mum operating duty cycle (this occurs at minimum
input voltage). In addition, ensure that the boost capac-
itor does not discharge to below the minimum gate-to-
source voltage required to keep the high-side MOSFET
fully enhanced for lowest on-resistance. This minimum
shorted (0V):
V
ILIM(0V)
4) The value for R4 can be calculated as:
2V - V
ILIM(0V)
R4 =
10µA
5) The parallel combination of R5 and R6, denoted
R56, is calculated as:
⎛
⎞
2V
10µA
R56 =
- R4
⎜
⎝
⎟
⎠
gate-to-source voltage (V ) is determined by:
GS(MIN)
V
OUT
REF
Q
G
V
= V
x
GS(MIN)
DD
C
REF
C
BOOST
R5
R4
R6
MAX8632
where V
is 5V, Q is the total gate charge of the
G
DD
high-side MOSFET, and C
value where C
Circuit (Figure 8).
is the boost-capacitor
is C7 in the Typical Applications
BOOST
ILIM
GND
BOOST
Figure 7. Foldback Current Limit
______________________________________________________________________________________ 2±
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
R6
C1
20Ω
0.1µF
REFIN
C3
1µF
VTTI
VTT
C2
10µF
VTT
AV
V
DD
1.25V/ 1.5A
R1
10Ω
C4
MAX8632
VTTS
20µF
5V
DD
BIAS
SUPPLY
PGND2
C5
4.7µF
D1
CMDSH-3
VTTR
1.25V/10mA
VTTR
C6
1µF
V
IN
(4.5V TO 28V)
V
IN
C14
470µF
(OPTIONAL)
OVP/UVP
BST
LX
R2
100kΩ
R3
100kΩ
C8
2 x 10µF
C7
0.22µF
POK1
POK1
Q1
POK2
POK2
SKIP
IRF7821
n-CHANNEL
30V, 9mΩ
DH
L1
TON
GND
TOKO FDA1254-1R0M
1.0µH, 21A, 1.6mΩ
C9
3.9nF
2.5V/12A
Q2
IRF7832
n-CHANNEL
30V,5mΩ
SS
C12
150µF
DL
C10
0.22µF
C11
150µF
C13
1µF
REF
PGND1
SHDN
R4
100kΩ
R5
47.5kΩ
C11, C12 (150µF, 4V,
25mΩ, LOW-ESR POS
CAPACITOR (D2E)
ILIM
ON
SANYO 4TPE150M
STBY
TP0
FB
OFF
OUT
Figure 8. Typical Applications Circuit
Transient Response (Buck)
⎡
⎢
⎣
⎤
V
× K
2
OUT
L × ∆I
+ t
OFF(MIN)
The inductor ripple current also affects transient-
⎥
⎦
LOAD(MAX)
V
IN
response performance, especially at low V - V
dif-
OUT
IN
V
=
SAG
⎡
⎤
⎥
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The output sag is also a function of the maximum duty
factor, which can be calculated from the on-time and
minimum off-time:
V
- V
× K
(
)
IN OUT
2C
× V
+ t
OFF(MIN)
⎢
OUT
OUT
V
⎢
⎣
⎥
⎦
IN
where t
is the minimum off-time (see the
Electrical Characteristics) and K is from Table 1.
OFF(MIN)
24 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
The overshoot during a full-load to no-load transient
due to stored inductor energy can be calculated as:
If the calculated V
minimum input voltage, then the operating frequency
must be reduced or output capacitance added to
obtain an acceptable V
anticipated, calculate V
transient response.
is greater than the required
IN(MIN)
2
∆I
× L
. If operation near dropout is
LOAD(MAX)
SAG
V
=
SOAR
to be sure of adequate
SAG
2 × C
× V
OUT
OUT
A dropout design example follows:
= 2.5V
Applications Information
V
OUT
Dropout Performance (Buck)
f
= 600kHz
SW
The output-voltage adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout perfor-
mance, use the slower (200kHz) on-time setting. When
working with low input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propa-
gation delays introduce an error to the TON K-factor.
This error is greater at higher frequencies (see Table
1). Also, keep in mind that transient-response perfor-
mance of buck regulators operated too close to
dropout is poor, and bulk output capacitance must
K = 1.7µs
t
= 450ns
OFF(MIN)
V
= V
= 100mV
DROP1
DROP2
h = 1.5
⎡
⎢
⎤
⎥
⎥
⎥
⎥
2.5V + 0.1V
⎢
⎢
⎢
V
=
+ 0.1V - 0.1V = 4.3V
IN(MIN)
⎛
⎞
1.5 × 450ns
1.7µs
1 -
⎜
⎝
⎟
⎠
⎢
⎥
⎣
⎦
often be added (see the V
equation in the Design
SAG
Procedure section).
Voltage Positioning (Buck)
In applications where fast-load transients occur, the
output voltage changes instantly by R × C
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
×
OUT
)
ESR
DOWN
∆I
. Voltage positioning allows the use of fewer out-
as much as it ramps up during the on-time (∆I ). The
LOAD
UP
put capacitors for such applications, and maximizes
the output-voltage AC and DC tolerance window in
tight-tolerance applications.
ratio h = ∆I / ∆I
indicates the controller’s ability
UP
DOWN
to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
Figure 9 shows the connection of OUT and FB in a volt-
age-positioned circuit. In nonvoltage-positioned cir-
cuits, the MAX8632 regulates at the output capacitor. In
voltage-positioned circuits, the MAX8632 regulates on
the inductor side of the voltage-positioning resistor.
each switching cycle, and V
greatly increases,
SAG
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
V
OUT
is reduced to:
this up or down allows trade-offs between V
, output
SAG
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
V
= V
- R
× I
POS LOAD
OUT(VPS)
OUT(NO_LOAD)
PC Board Layout Guidelines
⎡
⎢
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎥
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
V
+ V
h × t
OUT
DROP1
OFF(MIN)
K
V
=
+ V
- V
IN(MIN)
DROP2 DROP1
⎛
⎞
1 -
⎜
⎟
⎢
⎣
⎥
⎦
⎝
⎠
where V
and V
are the parasitic voltage
DROP2
DROP1
drops in the discharge and charge paths (see the On-
Time One-Shot (TON) section), t is from the
Electrical Characteristics, and K is taken from Table 1.
The absolute minimum input voltage is calculated with
h = 1.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
OFF(MIN)
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
______________________________________________________________________________________ 25
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
+5V BIAS
SUPPLY
AV
V
DD
DD
IN
V
IN
BST
DH
VOLTAGE-
POSITIONED
OUTPUT
MAX8632
R
POS
LX
DL
PGND1
GND
OUT
FB
Figure 9. Voltage-Positioned Output
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance caus-
es a measurable efficiency penalty.
Special Layout Considerations for LDO Section
The capacitor (or capacitors) at VTT should be placed
as close to VTT and PGND2 (pins 12 and 11) as possi-
ble to minimize the series resistance/inductance of the
trace. The PGND2 side of the capacitor must be short
with a low-impedance path to the exposed pad under-
neath the IC. The exposed pad must be star-connected
to GND (pin 24) and PGND2 (pin 11). Connect PGND1
(pin 23) separately to the nearby PGND plane at the
source of the low-side MOSFET. Do not connect this
pin directly to the exposed pad as this can inject unde-
sirable switching noise into the clean analog GND.
Instead, PGND1 (pin 23) is connected to PGND2 (pin
11) by the large PGND plane. A narrower trace can be
used to connect the output voltage on the VTT side of
the capacitor back to VTTS (pin 9). For best perfor-
mance, the VTTI bypass capacitor must be placed as
close to VTTI (pin 13) as possible. REFIN (pin 14)
should be separately routed with a clean trace and
adequately bypassed to GND. Refer to the MAX8632
evaluation kit data sheet for PC board guidelines.
• The LX and PGND1 connections to the low-side
MOSFET for current sensing must be made using
Kelvin-sense connections.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor-charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes (BST, LX, DH,
and DL) away from sensitive analog areas (REF, FB,
and ILIM).
• Input ceramic capacitors must be placed as close
as possible to the high-side MOSFET drain and the
low-side MOSFET source. Position the MOSFETs so
the impedance between the input capacitor termi-
nals and the MOSFETs is as low as possible.
26 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Typical Operating Circuit
R8
C1
REFIN
VTTI
C2
C3
VTT
AV
V
DD
VTT
0.9V - 1.25V / 1.5A
R1
D1
C4
VTTS
5V
BIAS
SUPPLY
DD
PGND2
VTTR
C5
C8
VTTR
0.9V - 1.25V / 10mA
MAX8632
V
IN
(4.5V TO 28V)
C6
V
IN
OVP/UVP
BST
LX
R2
R3
C7
POK1
POK2
POK1
Q1
Q2
POK2
SKIP
DH
TON
GND
L1
C9
1.8V - 2.5V / 12A
SS
DL
C10
C11
REF
PGND1
SHDN
R4
R5
R7
ILIM
ON
STBY
TP0
FB
OFF
R6
OUT
Chip Information
TRANSISTOR COUNT: 5100
PROCESS: BiCMOS
______________________________________________________________________________________ 27
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
XXXXX
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
C
L
L1
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
21-0140
H
-DRAWING NOT TO SCALE-
2
28 ______________________________________________________________________________________
Integrated DDR Power-Supply Solution for
Desktops, Notebooks, and Graphic Cards
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
DOWN
BONDS
ALLOWED
L
PKG.
CODES
MIN. NOM. MAX. MIN. NOM. MAX. ±0.15
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-1
T1655-2
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
**
**
**
**
A1
A3
b
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-2
T2055-3
T2055-4
T2055-5
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
D
E
**
**
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-1
T2855-2
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
L
**
**
**
**
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
40
T2855-3
T2855-4
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
N
ND
NE
16
20
28
32
4
4
5
5
7
7
8
8
10
10
T2855-5
T2855-6
T2855-7
T2855-8
**
**
**
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
NO
YES
2.80
3.35
3.35
3.20
2.60 2.70
3.15 3.25
2.60 2.70 2.80
3.15 3.25 3.35
3.15 3.25 3.35
3.00 3.10 3.20
0.40
YES
NO
NO
NOTES:
T2855N-1 3.15 3.25
**
**
**
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255-2
T3255-3
T3255-4
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
**
**
**
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
NO
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3, AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
H
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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