MAX8756ETI+T [MAXIM]
Dual Switching Controller;
| 型号： | MAX8756ETI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller 开关 |
| 文件： | 总30页 (文件大小：705K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3569; Rev 2; 4/07
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
General Description
Features
The MAX8716/MAX8717/MAX8756/MAX8757 are dual,
step-down, interleaved, fixed-frequency, switch-mode
power-supply (SMPS) controllers with synchronous rec-
tification. The MAX8716/MAX8717/MAX8756/MAX8757
are intended for main (5V/3.3V) power generation, while
the MAX8756 is optimized for I/O power rails in battery-
powered systems.
o Fixed Switching Frequency
200kHz, 300kHz, or 500kHz
250kHz, 300kHz, or 400kHz (MAX8756 Only)
o No Current-Sense Resistor Required
o 40/60 Optimal Interleaving
o Reduced Input-Capacitor Requirement
o Output Voltage Fixed or Adjustable Outputs
(Dual Mode™)
Fixed-frequency operation with optimal interleaving min-
imizes input ripple current from the lowest input voltages
up to the 26V maximum input. Optimal 40/60 interleav-
ing allows the input voltage to go down to 8.3V before
duty-cycle overlap occurs in 5V/3.3V applications, com-
pared to 180° out-of-phase regulators where the duty-
cycle overlap occurs when the input drops below 10V.
Accurate output current limit is achieved using a sense
resistor. Alternatively, power dissipation can be
reduced using lossless inductor current sensing.
Independent ON/OFF controls and power-good signals
allow flexible power sequencing. Soft-start reduces
inrush current, while soft-stop gradually ramps the out-
put voltage down preventing negative voltage dips.
3.3V/5V Fixed or 1V to 5.5V Adjustable
1.5V/1.8V Fixed or 1V to 2.3V Adjustable
(MAX8756 Only)
o 4V to 26V Input Range
o Independently Selectable PWM, Skip, and Low-
Noise Mode Operation
o Soft-Start and Soft-Stop
o 2V Precision Reference with 0.75% Accuracy
o Independent Power-Good Outputs
Ordering Information
A low-noise mode maintains high light-load efficiency
while keeping the switching frequency out of the audi-
ble range.
The MAX8716 is available in a 24-pin thin QFN pack-
age, and the MAX8717/MAX8756/MAX8757 are avail-
able in a 28-pin thin QFN package.
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
24 Thin QFN
4mm x 4mm
MAX8716ETG
-40°C to +85°C
T2444-4
T2444-4
T2855-6
24 Thin QFN
4mm x 4mm
MAX8716ETG+ -40°C to +85°C
MAX8717ETI -40°C to +85°C
Applications
28 Thin QFN
5mm x 5mm
2 to 4 Li+ Cell Battery-Powered Devices
Notebook and Subnotebook Computers
PDAs and Mobile Communicators
Main or I/O Power Supplies
+Denotes a lead-free package.
Ordering Information continued at end of data sheet.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
Pin Configurations
TOP VIEW
TOP VIEW
21 20 19 18 17 16 15
18 17 16 15 14 13
DH1
22
23
14 DH2
DH1 19
BST1 20
12 DH2
11 BST2
BST1
BST2
CSH2
13
12
CSH1 24
CSL1 25
CSH1 21
CSL1 22
10 CSH2
MAX8716ETG
11 CSL2
10 FB2
9
8
7
CSL2
MAX8717ETI
MAX8756ETI+
MAX8757ETI+
FB1 23
FB2
FB1
26
27
PGOOD1 24
PGOOD2
PGOOD1
9
8
PGOOD2
ILIM2
+
ILIM1 28
1
2
3
4
5
6
+
1
2
3
4
5
6
7
TQFN
+
TQFN
A " " SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
ABSOLUTE MAXIMUM RATINGS (Note 1)
DD CC
ON1, ON2, SKIP1, SKIP2, PGOOD1,
V
, V , CSL1, CSH1, CSL2, CSH2 to AGND ......-0.3V to +6V
REF Short Circuit to AGND.........................................Continuous
REF Current ......................................................................+10mA
PGOOD2 to AGND...............................................-0.3V to +6V
FB1, FB2, ILIM1, ILIM2, FSEL to AGND...................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
24-Pin Thin QFN 4mm x 4mm (derate 20.8mW/°C
A
REF to AGND..............................................-0.3V to (V
+ 0.3V)
above +70°C)..........................................................1666.7mW
28-Pin Thin QFN 5mm x 5mm (derate 21.3mW/°C
above +70°C)..........................................................1702.1mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
BST1, BST2 to AGND.............................................-0.3V to +36V
LX1 to BST1..............................................................-6V to +0.3V
LX2 to BST2..............................................................-6V to +0.3V
DH1 to LX1 ..............................................-0.3V to (V
DH2 to LX2 ..............................................-0.3V to (V
DL1, DL2 to PGND .....................................-0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
BST1
BST2
DD
AGND to PGND.....................................................-0.3V to +0.3V
Note 1: For the 24-pin TQFN version, AGND and PGND refer to a single pin designated GND.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, FSEL = REF, SKIP_ = 0, V
= V
= V
= V = 5V T = 0°C to +85°C, unless otherwise noted.
CC DD , A
IN
ON_
ILIM_
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLIES
V
26
5.5
4.4
4.2
IN
Input Voltage Range
V
V
V
V
, V
CC DD
4.5
3.9
3.7
BIAS
V
V
rising
falling
4.15
3.95
CC
CC
V
Undervoltage-Lockout
200mV typical
hysteresis
CC
V
UVLO
Threshold
MAX8716, MAX8717,
MAX8757
CSL_ and FB_ forced
above their regulation
points
0.8
1
1.3
1.8
5
Quiescent Supply Current (V
)
I
I
mA
µA
CC
CC
MAX8756
CSL_ and FB_ forced above their regulation
points
Quiescent Supply Current (V
)
DD
< 1
DD
Shutdown Supply Current (V
Shutdown Supply Current (V
)
ON1 = ON2 = GND
ON1 = ON2 = GND
< 1
< 1
5
5
µA
µA
CC
)
DD
MAIN SMPS CONTROLLERS
16/MAX857
MAX8716, MAX8717,
MAX8757
V
= 6V to 26V,
IN
3.265
1.484
4.94
3.30
1.50
3.365
1.530
5.09
PWM1 Output Voltage in
Fixed Mode
V
V
SKIP1 = V
zero to full load
,
CC
V
V
OUT1
OUT2
MAX8756
MAX8716, MAX8717,
MAX8757
V
= 6V to 26V,
IN
5.00
PWM2 Output Voltage in
Fixed Mode
SKIP2 = V
zero to full load
,
CC
MAX8756
1.778
0.990
1.800
1.005
1.832
1.020
V
= 6V to 26V, FB1 or FB2,
duty factor = 20% to 80%
IN
Feedback Voltage in Adjustable
Mode (Note 2)
V
V
V
FB_
V
= 6V to 26V, FB1 or FB2,
IN
0.995
1.005
1.015
duty factor = 50%
MAX8716, MAX8717,
MAX8757
1.0
1.0
5.5
2.3
Output-Voltage-Adjust Range
Either SMPS
MAX8756
2
_______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, FSEL = REF, SKIP_ = 0, V
= V
= V
= V = 5V T = 0°C to +85°C, unless otherwise noted.
CC DD , A
IN
ON_
ILIM_
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
1.9
TYP
MAX
2.1
UNITS
FB1, FB2 Fixed-Mode Threshold
Voltage
Dual Mode comparator
FB1 = 1.1V, FB2 = 1.1V
V
Feedback Input Leakage Current
DC Load Regulation
-0.1
+0.1
µA
%
Either SMPS, SKIP_ = V , zero to full load
-0.1
CC
Line-Regulation Error
Either SMPS, 4V < V < 26V
0.03
%/V
µA
IN
FB_ Input Bias Current
I
V
= 0 to 5.5V
FB_
-0.1
170
+0.1
230
FB_
MAX8716, MAX8717,
MAX8757
200
FSEL = GND
MAX8756
215
270
250
300
285
330
Operating Frequency
Maximum Duty Factor
f
FSEL = REF (Note 3)
kHz
%
OSC
MAX8716, MAX8717,
MAX8757
425
500
575
460
FSEL = V
CC
MAX8756
340
97.5
97.5
97.5
400
99
FSEL = GND
D
FSEL = REF (Note 3)
99
MAX
FSEL = V
(Note 4)
99
CC
Minimum On-Time
t
200
ns
%
ON(MIN)
40
SMPS1 to SMPS2 Phase Shift
SMPS2 starts after SMPS1
144
Degrees
Measured from the rising edge of ON_ to full
scale, REF = 2V
Soft-Start Ramp Time
Soft-Stop Ramp Time
t
2
4
ms
ms
SSTART
Measured from the falling edge of ON_ to full
scale
t
SSTOP
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Limit Threshold (Fixed)
0.5
45
V
V
REF
V
_
V
V
V
_ - V
_ - V
_ - V
_, ILIM_ = V
(Note 3)
50
55
mV
LIMIT
LIMIT
CSH
CSL
CSL
CC
V
_ = 2.00V
_ = 1.00V
190
94
200
100
210
106
ILIM
ILIM
Current-Limit Threshold
(Adjustable)
V
_
_
mV
mV
%
CSH
V
_, SKIP_ = ILIM_ = V
CC
CSH
CSL
-67
-60
-53
14
(Note 3)
Current-Limit Threshold
(Negative)
V
NEG
V
_ - V
CSH
_, SKIP_ = V , adjustable
CC
CSL
-120
mode, percent of current limit
Current-Limit Threshold
(Zero Crossing)
V
V
_ - V
CSH
_, SKIP_ = GND or REF
3
mV
mV
ZX
CSL
ILIM_ = V
(Note 3)
6
10
CC
V
_ - V
_,
CSH
CSL
With respect to
current-limit
threshold
Idle Mode™ Threshold
V
IDLE
SKIP_ = GND
20
%
Idle Mode is a trademark of Maxim Integrated Products, Inc.
_______________________________________________________________________________________
3
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, FSEL = REF, SKIP_ = 0, V
= V
= V
= V = 5V T = 0°C to +85°C, unless otherwise noted.
CC DD , A
IN
ON_
ILIM_
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.5
1
TYP
5
MAX
7.5
4
UNITS
MAX8716, MAX8717,
MAX8757
V
_ - V
_
CSL
CSH
SKIP_ = REF
ILIM_ = V (Note 3)
mV
MAX8756
2.5
10
CC
Low-Noise-Mode Threshold
V
IDLE
V
_ - V
CSH
_
CSL
MAX8716, MAX8717,
MAX8757
SKIP_ = REF with
respect to current-
limit threshold
%
MAX8756
5
ILIM_ Leakage Current
Reference Load Regulation
Reference Sink Current
REF Lockout Voltage
0.1
10
µA
mV
µA
V
ΔV
I
= 0µA to 50µA
REF
REF
10
V
Rising edge, hysteresis = 50mV
1.8
REF(UVLO)
FAULT DETECTION
Output Overvoltage Trip
Threshold
Output Overvoltage
Fault-Propagation Delay
Output Undervoltage-Protection
Trip Threshold
Output Undervoltage
Fault-Propagation Delay
Output Undervoltage-Protection
Blanking Time
MAX8716/MAX8717/MAX8756 only
11
65
15
10
19
75
%
µs
%
50mV overdrive,
MAX8716/MAX8717/MAX8756 only
t
OVP
With respect to error-comparator threshold
50mV overdrive
70
t
10
µs
UVP
t
From rising edge of ON_
6144
1/f
OSC
BLANK
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD_ Lower Trip Threshold
-12.5
-10
10
-8.0
%
PGOOD_ Propagation Delay
PGOOD_ Output Low Voltage
PGOOD_ Leakage Current
Thermal-Shutdown Threshold
GATE DRIVERS
t
_
_
Falling edge, 50mV overdrive
µs
V
PGOOD
I
= 4mA
0.4
1
SINK
I
High state, PGOOD_ forced to 5.5V
Hysteresis = 15°C
µA
°C
PGOOD
T
+160
SHDN
16/MAX857
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V (Note 5)
DL_, high state
1.5
1.7
0.6
5
5
3
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
(Note 5)
R
DL
DL_, low state
DH_ Gate-Driver Source/Sink
Current
DH_ forced to 2.5V, BST_ - LX_ forced to
5V
I
2
A
DH
I
DL
(SOURCE)
DL_ Gate-Driver Source Current
DL_ Gate-Driver Sink Current
DL_ forced to 2.5V
1.7
A
A
I
DL_ forced to 2.5V
DL_ rising
3.3
35
DL (SINK)
Dead Time
t
ns
DEAD
DH_ rising
26
LX_, BST_ Leakage Current
V
_ = V _ = 26V
< 2
20
µA
BST
LX
4
_______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, FSEL = REF, SKIP_ = 0, V
= V
= V
= V = 5V T = 0°C to +85°C, unless otherwise noted.
CC DD , A
IN
ON_
ILIM_
Typical values are at T = +25°C.)
A
PARAMETER
INPUTS AND OUTPUTS
Logic Input Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ON1, ON2
-1
+1
µA
V
ON_ Input Voltage
Rising edge, hysteresis = 225mV
1.2
1.7
2.2
V
0.2
-
CC
Tri-Level Input Logic
SKIP1, SKIP2, FSEL, high
V
Input Leakage Current
Input Leakage Current
Input Leakage Current
Input Bias Current
SKIP1, SKIP2, FSEL, 0V, or V
-3
+3
+0.1
+0.1
50
µA
µA
µA
µA
CC
ILIM1, ILIM2, 0V, or V
-0.1
-0.1
CC
CSH_, 0V, or V
DD
DD
CSL_, 0V, or V
25
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, FSEL = REF, SKIP_ = 0, V
= V
= V
= V
= 5V, T = -40°C to +85°C, unless otherwise
DD A
IN
ON_
ILIM_
CC
noted.) (Note 6)
PARAMETER
INPUT SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
26
IN
Input Voltage Range
V
V
V
, V
CC DD
4.5
5.5
BIAS
MAX8716, MAX8717,
MAX8757
CSL_ and FB_
forced above their
regulation points
1.3
1.8
5
Quiescent Supply Current (V
Quiescent Supply Current (V
)
I
mA
µA
CC
CC
MAX8756
CSL_ and FB_ forced above their regulation
points
)
DD
I
DD
Shutdown Supply Current (V
Shutdown Supply Current (V
)
ON1 = ON2 = GND
ON1 = ON2 = GND
5
5
µA
µA
CC
)
DD
MAIN SMPS CONTROLLERS
MAX8716, MAX8717,
MAX8757
V
= 6V to 26V,
IN
3.255
1.480
4.925
1.773
0.987
3.375
1.534
5.105
1.838
1.023
PWM1 Output Voltage in
Fixed Mode
V
V
SKIP1 = V
zero to full load
,
CC
V
OUT1
OUT2
MAX8756
MAX8716, MAX8717,
MAX8757
V
= 6V to 26V,
IN
PWM2 Output Voltage in
Fixed Mode
SKIP2 = V
zero to full load
,
V
V
V
CC
MAX8756
Feedback Voltage in
Adjustable Mode
V
= 6V to 26V, FB1 or FB2,
IN
duty factor = 20% to 80% (Note 1)
V
FB_
MAX8716, MAX8717,
MAX8757
MAX8756
1.0
1.0
5.5
2.3
Output Voltage Adjust Range
Either SMPS
FB1, FB2 Fixed-Mode
Threshold Voltage
Dual Mode comparator
1.9
2.1
V
_______________________________________________________________________________________
5
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, FSEL = REF, SKIP_ = 0, V
= V
= V
= V
= 5V, T = -40°C to +85°C, unless otherwise
DD A
IN
ON_
ILIM_
CC
noted.) (Note 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX8716, MAX8717,
MAX8757
170
230
FSEL = GND
FSEL = REF (Note 3)
FSEL = V
MAX8756
215
270
285
330
Operating Frequency
f
kHz
OSC
MAX8716, MAX8717,
MAX8757
425
575
460
CC
MAX8756
340
97.5
97.5
97.5
FSEL = GND
Maximum Duty Factor
D
FSEL = REF (Note 3)
%
MAX
FSEL = V
(Note 4)
CC
Minimum On-Time
t
200
ns
ON(MIN)
CURRENT LIMIT
ILIM_ Adjustment Range
Current-Limit Threshold (Fixed)
0.5
44
V
V
REF
V
_
_
V
V
_ - V
_, ILIM_ = V (Note 3)
CC
56
mV
LIMIT
LIMIT
CSH
CSL
CSL
V
V
_ = 2.00V
_ = 1.00V
188
93
212
107
ILIM
ILIM
Current-Limit Threshold
(Adjustable)
V
_ - V
CSH
_
mV
V
REFERENCE (REF)
Reference Voltage
V
V
= 4.5V to 5.5V, I
= 0
1.98
2.02
REF
CC
REF
FAULT DETECTION
Output Overvoltage Trip Threshold
MAX8716/MAX8717/MAX8756 only
11
65
19
75
%
%
Output Undervoltage-Protection
Trip Threshold
With respect to error-comparator threshold
With respect to error-comparator threshold,
hysteresis = 1%
PGOOD_ Lower Trip Threshold
-12.5
-8.0
0.4
%
V
PGOOD_ Output Low Voltage
GATE DRIVERS
I
= 4mA
SINK
DH_ Gate-Driver On-Resistance
R
BST_ - LX_ forced to 5V (Note 5)
DL_, high state
5
5
3
Ω
Ω
DH
DL_ Gate-Driver On-Resistance
(Note 5)
16/MAX857
R
DL
DL_, low state
INPUTS AND OUTPUTS
ON_ Input Voltage
Rising edge, hysteresis = 225mV
High
1.2
2.2
V
V
V
-
CC
0.2
Tri-Level Input Logic
SKIP1, SKIP2, FSEL
REF
1.7
2.3
0.5
GND
Note 2: When the inductor is in continuous conduction, the output voltage will have a DC regulation level lower than the error-com-
parator threshold by 50% of the ripple. In discontinuous conduction, the output voltage will have a DC regulation level higher
than the error-comparator threshold by 50% of the ripple.
Note 3: Default setting for the MAX8716.
Note 4: Specifications are guaranteed by design, not production tested.
Note 5: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin QFN
package.
Note 6: Specifications from 0°C to -40°C are guaranteed by design, not production tested.
6
_______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
Typical Operating Characteristics
(Circuit of Figure 1, MAX8717, V = 12V, V
IN
= V
= 5V, SKIP_ = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
CC A
DD
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
3.3V OUTPUT EFFICIENCY
vs. LOAD CURRENT
100
100
100
SKIP
MODE
SKIP
MODE
SKIP
MODE
90
80
90
80
70
60
90
80
70
60
LOW-
PWM
NOISE
MODE
MODE
70
PWM
MODE
PWM
MODE
LOW-
NOISE
MODE
LOW-
NOISE
MODE
60
V
= 12V
V = 20V
IN
V
= 6V
IN
IN
50
50
50
0.001
0.01
0.1
1
10
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
10
10
LOAD CURRENT (A)
3.3V OUTPUT VOLTAGE
vs. LOAD CURRENT
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
3.40
100
100
LOW-
NOISE
MODE
SKIP
MODE
90
80
70
60
90
80
70
60
LOW-
NOISE
MODE
3.35
3.30
3.25
PWM
MODE
LOW-
PWM
SKIP
MODE
SKIP
MODE
NOISE
MODE
MODE
PWM
MODE
V
= 12V
V
= 6V
V = 12V
IN
IN
IN
50
50
0
1
2
3
4
5
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
2.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
5V OUTPUT VOLTAGE
vs. LOAD CURRENT
100
5.15
5.10
5.05
5.00
4.95
100
90
80
70
60
50
V
= 12V
IN
L = 4.3μH
SKIP
MODE
90
80
70
60
LOW-
NOISE
MODE
SKIP
MODE
SKIP
MODE
PWM
MODE
PWM
MODE
LOW-
NOISE
MODE
LOW-NOISE
MODE
PWM
MODE
V
= 20V
V = 12V
IN
IN
50
0.001
0.01
0.1
1
10
0
1
2
3
4
5
0.001
0.01
0.1
LOAD CURRENT (A)
1
LOAD CURRENT (A)
LOAD CURRENT (A)
_______________________________________________________________________________________
7
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, MAX8717, V = 12V, V
IN
= V
= 5V, SKIP_ = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
CC A
DD
1.8V OUTPUT EFFICIENCY
NO-LOAD SUPPLY CURRENT vs. INPUT
VOLTAGE (FORCED-PWM MODE)
NO-LOAD SUPPLY CURRENT vs. INPUT
VOLTAGE (IDLE MODE)
vs. LOAD CURRENT
100
28
10
1
V
= 12V
L = 3.2μH
IN
SKIP1 = SKIP2 = GND OR REF
24
20
16
12
8
ON1 = ON2 = V
CC
90
80
70
60
50
I
BIAS
SKIP
MODE
I
BIAS
PWM
MODE
I
IN
I
IN
0.1
0.01
LOW-NOISE
MODE
SKIP1 = SKIP2 = V
CC
4
ON1 = ON2 = V
CC
0
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
0
4
8
12
16
20
24
0
4
8
12
16
20
24
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUT2 IDLE-MODE CURRENT
vs. INPUT VOLTAGE
OUT2 SWITCHING FREQUENCY
vs. LOAD CURRENT
5V OUTPUT VOLTAGE
vs. INPUT VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1000
100
10
5.05
5.00
4.95
4.90
MAXIMUM DUTY-
CYCLE LIMITED
SKIP2 = V
CC
SKIP2 = GND
SKIP2 = REF
SKIP2 = REF
SKIP2 = GND
SKIP2 = V
CC
1
0
4
8
12
16
20
24
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
0
4
8
12
16
20
24
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
3.3V OUTPUT VOLTAGE
vs. INPUT VOLTAGE
OUT2 DROPOUT VOLTAGE
vs. LOAD CURRENT
16/MAX857
3.40
3.35
3.30
3.25
0.4
0.3
0.2
0.1
0
V
= 4.8V
OUT2
SKIP1 = V
CC
0
4
8
12
16
20
24
0
1
2
3
4
5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
8
_______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
Typical Operating Characteristics (continued)
(Circuit of Figure 1, MAX8717, V = 12V, V
IN
= V
= 5V, SKIP_ = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
CC A
DD
STARTUP WAVEFORMS
SHUTDOWN WAVEFORMS
STARTUP WAVEFORMS
MAX8716/17/57 toc20
MAX8716/17/57 toc18
MAX8716/17/57 toc19
3.3V
0
5V
0
5V
A
A
A
B
12V
B
C
0
B
0
0
2V
5V
C
0
C
2V
5V
D
E
5V
D
0
0
F
E
F
0
0
0
0
0
0
D
E
400μs/div
1ms/div
1ms/div
A. ON1/ON2, 5V/div
B. PGOOD1, 10V/div
C. PGOOD2, 10V/div
A. LX2, 20V/div
B. ON2, 10V/div
D. REF, 2V/div
E. OUT2, 2V/div
F. I , 2.5AV/div
LX2
A. DL2, 10V/div
B. ON2, 10V/div
D. REF, 2V/div
E. OUT2, 2V/div
F. I , 2.5AV/div
LX2
D. OUT2, 2V/div
E. OUT1, 2V/div
C. PGOOD2, 10V/div
C. PGOOD2, 10V/div
1.0Ω LOAD ON OUT2
1.0kΩ LOAD ON OUT2
SKIP2 = GND
V
CC
UVLO WAVEFORMS
STEADY-STATE WAVEFORMS
DROPOUT WAVEFORMS
MAX8716/17/57 toc23
MAX8716/17/57 toc21
MAX8716/17/57 toc22
5V
5V
4.9V
5V
A
A
B
5V
12V
A
0
0
B
5V
B
C
C
5V
C
5V
0
3.3V
12V
D
E
D
E
3.3V
5V
0
D
E
0
0
4ms/div
2μs/div
2μs/div
A. V , 2V/div
CC
B. OUT2, 2V/div
D. DL2, 5V/div
E. I , 2.5AV/div
A. OUT2, 50mV/div
B. LX2, 10V/div
D. OUT1, 50mV/div
E. LX1, 10V/div
A. OUT2, 50mV/div
B. LX2, 10V/div
D. OUT1, 50mV/div
E. LX1, 10V/div
LX2
C. PGOOD2, 5V/div
C. V , 50mV/div
C. V , 50mV/div
IN
IN
1.0A LOAD ON OUT1, 1.0A LOAD ON OUT2
SKIP1 = V , SKIP2 = V
100Ω LOAD ON OUT2
SKIP2 = V
CC
1.0A LOAD ON OUT1, 1.0A LOAD ON OUT2
SKIP1 = V , SKIP2 = V
CC
CC
CC
CC
_______________________________________________________________________________________
9
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, MAX8717, V = 12V, V
IN
= V
= 5V, SKIP_ = GND, FSEL = REF, T = +25°C, unless otherwise noted.)
CC A
DD
SKIP1 TRANSITION
SKIP1 TRANSITION
MAX8716/17/57 toc26
OUT1 LOAD TRANSIENT
MAX8716/17/57 toc25
MAX8716/17/57 toc24
0
0
0
A
B
A
B
A
12V
12V
3.3V
B
0
0
3A
0
3.3V
3.3V
C
D
C
D
C
D
2.5A
0
2.5A
0
12V
0
20μs/div
20μs/div
20μs/div
A. CONTROL, 5V/div
B. OUT1, 50mV/div
A. SKIP1, 5V/div
B. LX1, 10V/div
C. OUT1, 50mV/div
D. I , 2.5A/div
LX1
A. SKIP1, 5V/div
B. LX1, 10V/div
C. OUT1, 50mV/div
D. I , 2.5A/div
C. I , 3A/div
LX1
D. LX1, 10V/div
LX1
30mA LOAD ON OUT1
30mA LOAD ON OUT1
SKIP1 = V
CC
MAX8756 NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (FORCED-PWM MODE)
MAX8756 NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (IDLE MODE)
SKIP1 TRANSITION
MAX8716/17/57 toc27
28
10
1
ON1 = ON2 = V
CC
A
B
0
24
20
16
12V
0
I
BIAS
I
BIAS
0.1
12
8
3.3V
C
D
I
IN
I
IN
SKIP_ = GND
0.01
0.001
2.5A
0
I
IN
4
SKIP1 = SKIP2 = V
ON1 = ON2 = V
CC
SKIP_ = REF
CC
0
0
4
8
12
16
20
24
0
4
8
12
16
20 24
20μs/div
A. SKIP1, 5V/div
B. LX1, 10V/div
C. OUT1, 50mV/div
D. I , 2.5A/div
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LX1
16/MAX857
30mA LOAD ON OUT1
MAX8756 OUT2 IDLE MODE CURRENT
vs. INPUT VOLTAGE
2.0
1.8
1.6
1.4
SKIP2 = GND
SKIP2 = REF
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
4
8
12
16
20
24
INPUT VOLTAGE (V)
10 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
Pin Description
PIN
MAX8717/
MAX8756/
MAX8757
NAME
FUNCTION
MAX8716
Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a
series 20 resistor. Bypass V to AGND with a 1μF or greater ceramic capacitor.
CC
1
2
1
2
V
CC
Low-Noise Mode Control for SMPS1. Connect SKIP1 to GND for normal Idle Mode
(pulse-skipping) operation or to V for PWM mode (fixed frequency). Connect to REF
CC
for low-noise mode.
SKIP1
REF
2.0V Reference Voltage Output. Bypass REF to AGND with a 0.1μF or greater ceramic
capacitor. The reference can source up to 50μA. Loading REF degrades output voltage
accuracy according to the REF load-regulation error (see the Typical Operating
Characteristics). The reference shuts down when both ON1 and ON2 are low.
3
4
3
4
Low-Noise Mode Control for SMPS2. Connect SKIP2 to GND for normal Idle Mode
(pulse-skipping) operation or to V for PWM mode (fixed frequency). Connect to REF
CC
SKIP2
for low-noise mode.
Frequency Select Input. This four-level logic input sets the controller’s switching
frequency.
MAX8717/MAX8757 (kHz)
MAX8756 (kHz)
FSEL
5
FSEL
—
500
300
200
400
300
250
V
CC
REF
GND
SMPS1 Enable Input. Drive ON1 high to enable SMPS1. Drive ON1 low to shut down
SMPS1.
5
6
6
7
ON1
ON2
SMPS2 Enable Input. Drive ON2 high to enable SMPS2. Drive ON2 low to shut down
SMPS2.
SMPS2 Peak Current-Limit Threshold Adjustment. Connect ILIM2 to V to enable the
CC
default 50mV current-limit threshold. In adjustable mode, the current-limit threshold across
CSH2 and CSL2 is precisely 1/10 the voltage seen at ILIM2 over a 500mV to 2.0V range.
—
8
ILIM2
The logic threshold for switchover to the 50mV default value is approximately V
- 1V.
CC
SMPS2 Open-Drain Power-Good Output. PGOOD2 is low when SMPS2 is more than 10%
below its regulation threshold, during soft-start, and in shutdown.
7
8
9
PGOOD2
FB2
Feedback Input for SMPS2. Connect FB2 to V for fixed 5V output for the
CC
MAX8716/MAX8717/MAX8757, or a fixed 1.8V for the MAX8756. In adjustable mode,
FB2 regulates to 1V.
10
Negative Current-Sense Input for SMPS2. Connect to the negative terminal of the
current-sense element. Figure 8 describes two different current-sensing options.
9
11
12
CSL2
CSH2
Positive Current-Sense Input for SMPS2. Connect to the positive terminal of the current-
sense element. Figure 8 describes two different current-sensing options.
10
Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor and
diode as shown in Figure 1. An optional resistor in series with BST2 allows the DH2
turn-on current to be adjusted.
11
13
BST2
12
13
14
15
DH2
LX2
High-Side Gate-Driver Output for SMPS2. DH2 swings from LX2 to BST2.
Inductor Connection for SMPS2. Connect LX2 to the switched side of the inductor. LX2
is the lower supply rail for the DH2 high-side gate driver.
______________________________________________________________________________________ 11
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Pin Description (continued)
PIN
MAX8717/
MAX8756/
MAX8757
NAME
FUNCTION
MAX8716
14
15
16
—
—
17
16
17
—
18
19
20
DL2
Low-Side Gate-Driver Output for SMPS2. DL2 swings from PGND to V
DD.
V
Supply Voltage Input for the DL_ Gate Drivers. Connect to a 5V supply.
Power and Analog Ground. Connect backside pad to GND.
Power Ground
DD
GND
PGND
AGND
DL1
Analog Ground. Connect backside pad to AGND.
Low-Side Gate-Driver Output for SMPS1. DL1 swings from PGND to V
DD.
Inductor Connection for SMPS1. Connect LX1 to the switched side of the inductor. LX1
is the lower supply rail for the DH1 high-side gate driver.
18
19
21
22
LX1
DH1
High-Side Gate-Driver Output for SMPS1. DH1 swings from LX1 to BST1.
Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor and
diode as shown in Figure 1. An optional resistor in series with BST1 allows the DH1 turn-
on current to be adjusted.
20
23
BST1
Positive Current-Sense Input for SMPS1. Connect to the positive terminal of the current-
sense element. Figure 8 describes two different current-sensing options.
21
22
24
25
CSH1
CSL1
Negative Current-Sense Input for SMPS1. Connect to the negative terminal of the
current-sense element. Figure 8 describes two different current-sensing options.
Feedback Input for SMPS1. Connect FB1 to V
for fixed 3.3V output for the
CC
23
24
26
27
FB1
MAX8716/MAX8717/MAX8757, or a fixed 1.5V for the MAX8756. In adjustable mode,
FB1 regulates to 1V.
SMPS1 Open-Drain Power-Good Output. PGOOD1 is low when SMPS1 is more than
10% below its regulation threshold, during soft-start, and in shutdown.
PGOOD1
SMPS1 Peak Current-Limit Threshold Adjustment. Connect ILIM1 to V to enable the
CC
default 50mV current-limit threshold. In adjustable mode, the current-limit threshold
across CSH1 and CSL1 is precisely 1/10 the voltage seen at ILIM1 over a 500mV to
2.0V range. The logic threshold for switchover to the 50mV default value is
—
28
EP
ILIM1
EP
approximately V
- 1V.
CC
EP
Exposed Pad. Connect exposed backside pad to analog ground.
16/MAX857
SMPS 5V Bias Supply (V
and V
)
CC
DD
Detailed Description
The MAX8716/MAX8717/MAX8756/MAX8757 switch-
mode power supplies (SMPS) require a 5V bias supply
in addition to the high-power input supply (battery or
The MAX8716/MAX8717/MAX8756/MAX8757 Standard
Application Circuit (Figure 1) generates the 5V/5A and
3.3V/5A typical of the main supplies in notebook com-
puters. The input supply range is 6V to 24V. See Table 1
for component selections, while Table 2 lists the compo-
nent manufacturers.
AC adapter). V
is the power rail for the MOSFET gate
DD
drive, and V
is the power rail for the IC. Connect the
CC
external 4.5V to 5.5V supply directly to V
and con-
DD
nect V
to V
through an RC filter, as shown in
DD
CC
The MAX8716/MAX8717/MAX8756/MAX8757 contain
two interleaved fixed-frequency, step-down controllers
designed for low-voltage power supplies. The optimal
interleaved architecture guarantees out-of-phase oper-
ation, which reduces the input capacitor ripple.
Figure 1. The maximum supply current required is:
= I + f (Q + Q +Q +
G2(NL2)
I
BIAS
CC
SW
G(NL1)
G1(NH1)
Q
) = 1.3mA to 40mA
G2(NH2)
where I
is 1.3mA, f
is the switching frequency,
SW
CC
and Q
are the MOSFET data sheet’s total gate-
G_
charge specification limits at V = 5V.
GS
12 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
INPUT (V )
IN
+5V BIAS
C
IN
C1
(2) 10μF
1μF
V
DD
D
BST1
D
BST2
N
H1
N
H2
DH1
DH2
MAX8716
MAX8717
MAX8756
MAX8757
BST2
BST1
C
0.1μF
C
0.1μF
BST1
BST2
LX1
DL1
LX2
DL2
D
L2
D
L1
L1
L2
5.7μH
N
L2
5.7μH
N
L1
*PGND
*AGND
R
CS1
7mΩ
R
7mΩ
CS2
CSH2
CSL2
CSH1
CSL1
5V PWM
OUTPUT
3.3V PWM
OUTPUT
C
OUT2
150μF
C
OUT1
(1.8V FOR MAX8756)
(1.5V FOR MAX8756)
220μF
FB1
FB2
V
CC
V
CC
R1
20Ω
V
CC
+5V BIAS
C2
1μF
R2
100kΩ
R3
100kΩ
PULSE-
SKIPPING
CONTROL
SKIP1
SKIP2
PGOOD1
POWER-GOOD 1
POWER-GOOD 2
ON1
ON2
PGOOD2
REF
C
ON OFF
REF
0.22μF
*FOR THE MAX8716 AGND AND PGND,
REFER TO A SINGLE
PIN DESIGNATED GND.
V
ILIM1
ILIM2
DEFAULT
CURRENT
LIMIT
CC
REF (300kHz)
FSEL
V
CC
MAX8717/MAX8756/MAX8757 ONLY
POWER GROUND
ANALOG GROUND
SEE TABLE 1 FOR COMPONENT SPECIFICATIONS.
Figure 1. Standard Application Circuit
______________________________________________________________________________________ 13
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Table 1. Component Selection for Standard Applications
MAX8716/MAX8717/MAX8757
5V/5A, 3.3V/5A, 300kHz
MAX8716/MAX8717/MAX8757
5V/5A, 3.3V/5A, 500kHz
MAX8756
1.8V/5A, 1.5V/5A, 300kHz
COMPONENT
Input Voltage
V
= 7V to 24V
V
= 7V to 24V
V
= 7V to 24V
IN
IN
IN
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
C
, Input Capacitor
IN
220µF, 4V, 25mΩ
low-ESR capacitor,
SANYO 4TPE220M
150µF, 4V, 25mΩ
low-ESR capacitor,
SANYO 4TPE150M
220µF, 4V, 18mΩ
low-ESR capacitor,
SANYO 4TPE220MIC2
C
C
, Output Capacitor
OUT1
150µF, 6.3V, 25mΩ
low-ESR capacitor,
SANYO 6TPE150M
100µF, 6.3V, 25mΩ
low-ESR capacitor,
SANYO 6TPE100M
220µF, 4V, 18mΩ
low-ESR capacitor,
SANYO 4TPE220MIC2
, Output Capacitor
OUT2
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
Fairchild Semiconductor
FDS6612A
International Rectifier
IRF7807V
N
High-Side MOSFET
Low-Side MOSFET
H_
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
Fairchild Semiconductor
FDS6670S
International Rectifier
IRF7807VD1
N
L_
D
Schottky Rectifier
(if needed)
Nihon EC21QS03L
Nihon EC21QS03L
Nihon EC21QS03L
L_
2A, 30V, 0.45V
2A, 30V, 0.45V
2A, 30V, 0.45V
f
f
f
5.7µH
3.9µH
3.1µH
L_ Inductor
Sumida CDEP105-5R7NC
Sumida CDRH124-3R9NC
Sumida CDRH125-3R1NC
7mΩ 1% 0.5W resistor
IRC LR2010-01-R007F or
Dale WSL-2010-R007F
7mΩ 1% 0.5W resistor
IRC LR2010-01-R007F or
Dale WSL-2010-R007F
7mΩ 1% 0.5W resistor
IRC LR2010-01-R007F or
Dale WSL-2010-R007F
R
SENSE_
Reference (REF)
Table 2. Component Suppliers
The 2V reference is accurate to 1.5% over tempera-
ture and load, making REF useful as a precision system
reference. Bypass REF to GND with a 0.1µF or greater
ceramic capacitor. The reference sources up to 50µA
and sinks 10µA to support external loads.
SUPPLIER
WEBSITE
AVX
www.avx.com
Central Semiconductor
Coilcraft
www.centralsemi.com
www.coilcraft.com
www.coiltronics.com
16/MAX857
SMPS Detailed Description
Coiltronics
Power-on reset (POR) occurs when V
rises above
CC
Fairchild Semiconductor www.fairchildsemi.com
approximately 2V, resetting the undervoltage, overvolt-
age, and thermal-shutdown fault latches. The POR cir-
cuit also ensures that the low-side drivers are driven
International Rectifier
KEMET
www.irf.com
www.kemet.com
Panasonic
SANYO
www.panasonic.com/industrial
www.secc.co.jp
high until the SMPS controllers are activated. The V
CC
input undervoltage-lockout (UVLO) circuitry inhibits
switching if V is below the V UVLO threshold.
CC
CC
Sumida
www.sumida.com
www.t-yuden.com
www.component.tdk.com
www.tokoam.com
www.vishay.com
An internal soft-start gradually increases the regulation
voltage during startup to reduce the input surge cur-
rents (see the Startup Waveforms in the Typical
Operating Characteristics).
Taiyo Yuden
TDK
TOKO
Vishay (Dale, Siliconix)
14 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
REF
R
V
CC
MAX8717/MAX8756/MAX8757
2.0V
REF
GND
OSC
FSEL
R
SKIP1
ON1
SKIP2
ON2
ILIM1
CSH1
ILIM2
CSH2
CSL1
BST1
CSL2
BST2
PWM1
CONTROLLER
(FIGURE 3)
PWM2
CONTROLLER
(FIGURE 3)
DH1
LX1
DH2
LX2
V
V
DD
DD
DL1
DL2
FB2
PGND
FB
FB
DECODE
(FIGURE 5)
DECODE
(FIGURE 5)
FB1
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
POWER-GOOD AND
FAULT PROTECTION
(FIGURE 7)
PGOOD1
PGOOD2
Figure 2. Functional Diagram
from 0V to the final set voltage in 2ms. This reduces
inrush current and provides a predictable ramp-up time
for power sequencing.
SMPS Enable Controls (ON1, ON2)
ON1 and ON2 provide independent control of output
soft-start and soft-shutdown. This allows flexible control
of startup and shutdown sequencing. The outputs can
be started simultaneously, sequentially, or indepen-
dently. To provide sequential startup, connect ON_ of
one regulator to PGOOD_ of the other. For example,
with ON1 connected to PGOOD2, OUT1 soft-starts after
OUT2 is in regulation. Drive ON_ low to clear the over-
voltage, undervoltage, and thermal fault latches.
Soft-shutdown begins after ON_ goes low, an output
undervoltage fault occurs, or a thermal fault occurs.
The two outputs are independent. A fault at one output
does not trigger shutdown of the other. During soft-
shutdown the output is ramped down to 0V in 4ms,
reducing negative inductor currents that can cause
negative voltages on the output. At the end of soft-shut-
down, DL_ is driven high until startup is again triggered
by a rising edge of ON_. The reference is turned off
when both outputs have been shut down.
Soft-Start and Soft-Shutdown
Soft-start begins when ON_ is driven high and REF is in
regulation. During soft-start, the output is ramped up
______________________________________________________________________________________ 15
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Frequency Selection (FSEL)
The FSEL input selects the PWM mode switching fre-
quency. Table 3 shows the switching frequency based
on the FSEL connection. High-frequency operation opti-
mizes the application for the smallest component size,
trading off efficiency due to higher switching losses.
This may be acceptable in ultra-portable devices where
the load currents are lower. Low-frequency operation
offers the best overall efficiency at the expense of com-
ponent size and board space.
Fixed-Frequency,
Current-Mode PWM Controller
The heart of each current-mode PWM controller is a
multi-input, open-loop comparator that sums two sig-
nals: the output-voltage error signal with respect to the
reference voltage and the slope-compensation
ramp (Figure 3). The MAX8716/MAX8717/MAX8756/
MAX8757 use a direct-summing configuration,
approaching ideal cycle-to-cycle control over the out-
put voltage without a traditional error amplifier and the
phase shift associated with it. The MAX8716/MAX8717/
MAX8756/MAX8757 use a relatively low loop gain,
allowing the use of low-cost output capacitors. The low
loop gain results in the 0.1% typical load-regulation
error and helps reduce the output capacitor size and
cost by shifting the unity-gain crossover frequency to a
lower level.
Forced-PWM Mode
To maintain low ripple fixed-frequency operation, drive
SKIP_ high to put the output into forced-PWM mode.
This disables the zero-crossing comparator and allows
negative inductor current. During forced-PWM mode,
FB
CSH
CSL
(0.05 x V
FOR MAX8756)
LIMIT
REF / 2
SLOPE COMP
SOFT-START
SOFT-STOP
0.1 x V
0.2 x V
LIMIT
LIMIT
ON
AGND
R
S
Q
SKIP
DECODE
DH DRIVER
SKIP
OSC
16/MAX857
V
LIMIT
-1.2 x V
LIMIT
3mV
DL DRIVER
S
Q
R
Figure 3. PWM-Controller Functional Diagram
16 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
the switching frequency remains constant and the
no-load supply current is typically between 8mA and
20mA per phase, depending on external MOSFETs and
switching frequency.
Light-Load Operation Control (SKIP_)
The MAX8716/MAX8717/MAX8756/MAX8757 include
SKIP_ inputs that enable the corresponding outputs to
V
OUT
t
=
ON(SKIP)
operate in discontinuous mode. Connect SKIP_ to GND
or REF as shown in Table 4 to enable or disable the
zero-crossing comparators of either controller. When
the zero-crossing comparator is enabled, the controller
forces DL_ low when the current-sense inputs detect
zero inductor current. This keeps the inductor from dis-
charging the output capacitors and forces the con-
troller to skip pulses under light-load conditions to
avoid overcharging the output. During skip mode, the
V
x f
IN OSC
I
LOAD(SKIP)
I
LOAD(SKIP)
2
I
=
LOAD
0
TIME
V
DD
current consumption is reduced and efficiency is
ON-TIME
improved. During low-noise skip mode, the no-load rip-
ple amplitude is two times smaller and the no-load
switching frequency is four times higher, although the
light-load efficiency is somewhat lower.
Figure 4. Pulse-Skipping/Discontinuous Crossover Point
Automatic Pulse-Skipping Crossover
In skip mode, an inherent automatic switchover to PFM
takes place at light loads (Figure 4). This switchover is
affected by a comparator that truncates the low-side
switch on-time at the inductor current’s zero crossing.
The zero-crossing comparator senses the inductor cur-
Table 3. FSEL Configuration Table
MAX8717/
MAX8757 (kHz)
FSEL
MAX8756 (kHz)
V
500
300
200
400
300
250
CC
rent across CSH_ and CSL_. Once V
- V
_ drops
CSH
CSL
REF
below the 3mV zero-crossing, current-sense threshold,
the comparator forces DL_ low (Figure 3). This mecha-
nism causes the threshold between pulse-skipping PFM
and nonskipping PWM operation to coincide with the
boundary between continuous and discontinuous induc-
tor-current operation (also known as the “critical conduc-
tion” point). The load-current level at which PFM/PWM
GND
Idle Mode Current-Sense Threshold
When pulse-skipping mode is enabled, the on-time of
the step-down controller terminates when the output
voltage exceeds the feedback threshold and when the
current-sense voltage exceeds the Idle Mode current-
sense threshold. Under light-load conditions, the on-
time duration depends solely on the Idle Mode
current-sense threshold (SKIP_ = GND), which is 20%
of the full-load current-limit threshold set by ILIM_, or
the low-noise current-sense threshold (SKIP_ = REF),
which is 10% for the MAX8716/MAX8717/MAX8757 and
5% for the MAX8756 of the full-load current-limit thresh-
old set by ILIM_. This forces the controller to source a
minimum amount of power with each cycle. To avoid
overcharging the output, another on-time cannot begin
until output voltage drops below the feedback thresh-
old. Since the zero-crossing comparator prevents the
switching regulator from sinking current, the controller
must skip pulses. Therefore, the controller regulates the
valley of the output ripple under light-load conditions.
crossover occurs, I , is determined by:
LOAD(SKIP)
(V − V
)V
IN
OUT OUT
I
=
LOAD(SKIP)
2LV ƒ
IN OSC
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency are made by varying the
inductance. Generally, low inductance produces a
broader efficiency vs. load curve, while higher values
result in higher full-load efficiency (assuming that the
coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values
include larger physical size and degraded load-tran-
sient response (especially at low input-voltage levels).
______________________________________________________________________________________ 17
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Output Voltage
⎛
⎞
A
(V − V
)
V
RIPPLE
⎛
⎞
DC output accuracy specifications in the Electrical
Characteristics refer to the error comparator’s thresh-
old. When the inductor continuously conducts, the
MAX8716/MAX8717/MAX8756/MAX8757 regulate the
peak of the output ripple, so the actual DC output volt-
age is lower than the slope-compensated trip level by
50% of the output ripple voltage. For PWM operation
(continuous conduction), the output voltage is accu-
rately defined by the following equation:
SLOPE IN
NOM
V
= V
1−
−
⎜
⎝
⎟
⎠
OUT(PWM)
NOM
⎜
⎟
V
2
⎝
⎠
IN
where V
is the nominal output voltage, A
SLOPE
NOM
equals 1%, and V
is the output ripple voltage
x ΔI as described in the
INDUCTOR
RIPPLE
(V
= R
RIPPLE
ESR
Output Capacitor Selection section).
In discontinuous conduction (I
< I
), the
LOAD(SKIP)
OUT
MAX8716/MAX8717/MAX8756/MAX8757 regulate the
valley of the output ripple, so the output voltage has a DC
regulation level higher than the error-comparator thresh-
old. For PFM operation (discontinuous conduction), the
output voltage is approximately defined by the following
equation:
Table 4. SKIP_ Configuration Table
SKIP_
MODE
COMMENTS
Fixed-frequency operation.
Constant output ripple voltage.
Able to source and sink current.
High efficiency at light loads.
Source-only applications.
Forced-PWM
mode
V
CC
⎛
⎜
⎞
1
ƒ
SW
V
= V
+
I R
IDLE ESR
OUT(PFM)
NOM
⎟
GND
REF
Skip mode
2 ƒ
⎝
⎠
OSC
Good efficiency at light loads.
where V
is the nominal output voltage, f
is the
NOM
OSC
(V
/ V ) times smaller no-load
LN
IDLE
Low-noise
skip mode
maximum switching frequency set by the internal oscil-
ripple and (V
/ V )2 times higher
IDLE
LN
lator, f
is the actual switching frequency, and I
is
SW
IDLE
frequency compared with skip mode.
Source-only applications.
the Idle Mode inductor current when pulse skipping.
Table 5. Operating Modes Truth Table
MODE
Power-Up
Run
CONDITION
COMMENT
DL_ tracks V
as V
rises from 0V to +5V.
CC
CC
When ON_ is low, DL_ tracks V
as V
falls.
falls below the
CC
CC
CC
V
UVLO
When ON_ is high, DL_ is forced low as V
3.95V (typ) falling UVLO threshold. DL_ is forced high when
falls below 1V (typ).
CC
V
CC
ON1 or ON2 enabled
Normal operation.
When the overvoltage (OV) comparator trips, the faulted side
sets the OV latch, forcing PGOOD_ low and DL_ high. The
Output Overvoltage
Protection (OVP)
MAX8716/MAX8717/
MAX8756 Only
Either output > 115% of nominal level other controller is not affected.
The OV latch is cleared by cycling V
16/MAX857
below 1V or cycling
CC
the respective ON_ pin.
When the undervoltage (UV) comparator trips, the faulted
side sets the UV latch, forcing PGOOD_ low and initiating the
soft-shutdown sequence by pulsing only DL_. DL_ goes high
after soft-shutdown. The other controller is not affected.
Either output < 70% of nominal level,
UVP is enabled 6144 clock cycles
Output Undervoltage
Protection (UVP)
(1/f
) after the output is enabled
(ON_ going high)
OSC
The UV latch is cleared by cycling V
the respective ON_ pin.
below 1V or cycling
CC
DL_ stays high after soft-shutdown is completed.
All circuitry is shut down.
Shutdown
ON1 and ON2 are driven low
Exited by POR or cycling ON1 and ON2.
DL1 and DL2 remain high.
Thermal Shutdown
T > +160°C
J
18 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
inductor ripple current. Therefore, the maximum load
TO ERROR
AMPLIFIER
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
ADJUSTABLE
(V
/ V ).
IN
OUT
OUTPUT
FB
In forced-PWM mode, the MAX8716/MAX8717/
MAX8756/MAX8757 also implement a negative current
limit to prevent excessive reverse inductor currents
when V
is sinking current. The negative current-limit
OUT
threshold is set to approximately -120% of the positive
current limit and tracks the positive current limit when
ILIM is adjusted.
2V
Connect ILIM_ to V
for the 50mV default threshold, or
CC
adjust the current-limit threshold with an external resis-
tor-divider at ILIM_. Use a 2µA to 20µA divider current
for accuracy and noise immunity. The current-limit
threshold adjustment range is from 50mV to 200mV. In
the adjustable mode, the current-limit threshold voltage
equals precisely 1/10 the voltage seen at ILIM_. The
logic threshold for switchover to the 50mV default value
FIXED OUTPUT
FB = V
CC
CSL
is approximately V
- 1V.
CC
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the differential
current-sense signals seen by CSH_ and CSL_. Place
the IC close to the sense resistor with short, direct
traces, making a Kelvin-sense connection to the cur-
rent-sense resistor.
Figure 5. Dual Mode Feedback Decoder
Adjustable/Fixed Output Voltages
(Dual-Mode Feedback)
to enable the fixed SMPS
Connect FB1 and FB2 to V
CC
output voltages (3.3V and 5V, respectively, for the
MAX8716/MAX8717/MAX8757, and 1.5V and 1.8V for
the MAX8756, respectively), set by a preset, internal
resistive voltage-divider connected between CSL_ and
analog ground. See Figure 5. Connect a resistive volt-
age-divider at FB_ between CSL_ and GND to adjust
the respective output voltage between 1V and 5.5V.
Choose R2 (resistance from FB to AGND) to be approx-
imately 10kΩ and solve for R1 (resistance from OUT to
FB) using the equation:
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V
OUT
-
IN
V
differential exists. The high-side gate drivers
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
diode-capacitor charge pumps at BST_ (Figure 6) while
the DL_ synchronous-rectifier drivers are powered
⎛
⎞
V
OUT_
R1 = R2
−1
⎟
⎜
V
⎝
⎠
FB_
directly by the external 5V supply (V ).
DD
where V
= 1V nominal.
FB_
Adaptive dead-time circuits monitor the DL_ and DH_ dri-
vers and prevent either FET from turning on until the other
is fully off. The adaptive driver dead-time allows operation
without shoot-through with a wide range of MOSFETs,
minimizing delays and maintaining efficiency. There must
be a low-resistance, low-inductance path from the DL_
and DH_ drivers to the MOSFET gates for the adaptive
dead-time circuits to work properly; otherwise, the sense
circuitry in the MAX8716/MAX8717/MAX8756/MAX8757
interprets the MOSFET gates as “off” while charge actually
remains. Use very short, wide traces (50 mils to 100 mils
wide if the MOSFET is 1in from the driver).
Current-Limit Protection (ILIM_)
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
rent. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the current-limit threshold. The
actual maximum load current is less than the peak cur-
rent-limit threshold by an amount equal to half of the
______________________________________________________________________________________ 19
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps pre-
vent DL_ from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side MOSFETs
when the inductor node (LX_) quickly switches from
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output of a comparator that
continuously monitors each SMPS output voltage for
overvoltage and undervoltage conditions. PGOOD_ is
actively held low in shutdown (ON_ = GND), soft-start,
and soft-shutdown. Once the analog soft-start termi-
nates, PGOOD_ becomes high impedance as long as
the output is above 90% of the nominal regulation volt-
age set by FB_. PGOOD_ goes low once the output
drops 10% below its nominal regulation point, an output
overvoltage fault occurs, or ON_ is pulled low. For a
logic-level PGOOD_ output voltage, connect an exter-
nal pullup resistor between PGOOD_ and +5V or +3.3V.
A 100kΩ pullup resistor works well in most applications.
ground to V . Applications with high input voltages and
IN
long inductive driver traces may require additional gate-
to-source capacitance to ensure fast-rising LX_ edges
do not pull up the low-side MOSFETs gate, causing
shoot-through currents. The capacitive coupling
between LX_ and DL_ created by the MOSFET’s gate-to-
drain capacitance (C
), gate-to-source capacitance
RSS
(C
- C
), and additional board parasitics should not
ISS
RSS
exceed the following minimum threshold:
Fault Protection
Output Overvoltage Protection
(MAX8716/MAX8717/MAX8756 Only)
⎛
⎞
C
C
RSS
V
> V
IN
GS(TH)
⎜
⎟
⎝
⎠
ISS
If the output voltage of either SMPS rises above 115%
of its nominal regulation voltage, the corresponding
controller sets its overvoltage fault latch, pulls PGOOD_
low, and forces DL_ high for the corresponding SMPS
controller. The other controller is not affected. If the
condition that caused the overvoltage persists (such as
a shorted high-side MOSFET), the battery fuse will
Variation of the threshold voltage may cause problems
in marginal designs. Alternatively, adding a resistor
less than 10Ω in series with BST_ may remedy the
problem by increasing the turn-on time of the high-side
MOSFET without degrading the turn-off time (Figure 6).
blow. Cycle V
below 1V or toggle ON_ to clear the
CC
C
BYP
overvoltage fault latch and restart the SMPS controller.
V
DD
MAX8716
MAX8717
MAX8756
MAX8757
D
BST
FAULT
PROTECTION
(R )*
BST
POWER-GOOD
BST
0.9 x
1.15 x
0.7 x
INT REF_
INT REF_
INT REF_
INPUT (V
)
IN
INTERNAL FB
C
BST
DH
LX
N
H
L
POR
16/MAX857
V
DD
TIMER
DL
N
L
(C )*
NL
FAULT
FAULT
LATCH
PGND
POWER-
GOOD
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
BST
THE SWITCHING-NODE RISE TIME.
(C )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
NL
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 7. Power-Good and Fault Protection
Figure 6. Optional Gate-Driver Circuitry
20 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
Output Undervoltage Protection
If the output voltage of either SMPS falls below 70% of
its regulation voltage, the corresponding controller sets
its undervoltage fault latch, pulls PGOOD_ low, and
begins soft-shutdown for the corresponding SMPS con-
troller by pulsing DL_. DH_ remains off during the soft-
shutdown sequence initiated by an unvervoltage fault.
The other controller is not affected. After soft-shutdown
has completed, the MAX8716/MAX8717/MAX8756/
•
Maximum Load Current. There are two values to
consider. The peak load current (I ) deter-
LOAD(MAX)
mines the instantaneous component stresses and fil-
tering requirements and thus drives output capacitor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I ) determines the thermal stresses and thus
LOAD
drives the selection of input capacitors, MOSFETs,
and other critical heat-contributing components.
MAX8757 force DL_ high and DH_ low. Cycle V
CC
•
•
Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage, due to MOSFET switching losses that
below 1V or toggle ON_ to clear the undervoltage fault
latch and restart the SMPS controller.
V
POR and UVLO
CC
CC
are proportional to frequency and V 2. The opti-
IN
Power-on reset (POR) occurs when V
rises above
mum frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
approximately 2V, resetting the fault latch and prepar-
ing the PWM for operation. V undervoltage-lockout
CC
(UVLO) circuitry inhibits switching, forces PGOOD_
low, and forces the DL_ gate drivers low.
Inductor Operating Point. This choice provides
trade-offs between size vs. efficiency and transient
response vs. output ripple. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output ripple due to increased ripple currents. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 20% and 50% ripple current. When pulse-
skipping (SKIP low and light loads), the inductor
value also determines the load-current value at
which PFM/PWM switchover occurs.
If V
drops low enough to trip the UVLO comparator
CC
while ON_ is high, the MAX8716/MAX8717/MAX8756/
MAX8757 immediately force DH_ and DL_ low on both
controllers. The output discharges to 0V at a rate
dependent on the load and the total output capaci-
tance. This prevents negative output voltages, eliminat-
ing the need for a Schottky diode to GND at the output.
Thermal Fault Protection
The MAX8716/MAX8717/MAX8756/MAX8757 feature a
thermal fault-protection circuit. When the junction tem-
perature rises above +160°C, a thermal sensor sets the
fault latches, pulls PGOOD low, and shuts down both
SMPS controllers using the soft-shutdown sequence
(see the Sort-Start and Soft-Shutdown section). Cycle
V
CC
below 1V or toggle ON1 and ON2 to clear the fault
Inductor Selection
latches and restart the controllers after the junction
temperature cools by 15°C.
The switching frequency and inductor operating point
determine the inductor value as follows:
Design Procedure
V
(V − V
I
)
OUT IN
OUT
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
L =
V ƒ
LIR
IN OSC LOAD(MAX)
For example: I
= 5A, V = 12V, V
= 5V,
OUT
LOAD(MAX)
= 300kHz, 30% ripple current or LIR = 0.3:
IN
f
OSC
5V ×(12V − 5V)
12V × 300kHz× 5A × 0.3
•
Input Voltage Range. The maximum value (V
)
IN(MAX)
L =
= 6.50μH
must accommodate the worst-case, high AC-adapter
voltage. The minimum value (V ) must account
IN(MIN)
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also
for the lowest battery voltage after drops due to con-
nectors, fuses, and battery selector switches. If there
is a choice at all, lower input voltages result in better
efficiency.
______________________________________________________________________________________ 21
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
look for nonstandard values, which can provide a better
ΔI
⎛
⎞
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values. For
the selected inductance value, the actual peak-to-peak
INDUCTOR
I
>I
+
⎜
⎝
⎟
⎠
LIMIT LOAD(MAX)
2
where I
equals the minimum current-limit thresh-
old voltage divided by the current-sense resistance
(R ). For the 50mV default setting, the minimum
LIMIT_
inductor ripple current (ΔI ) is defined by:
INDUCTOR
SENSE
current-limit threshold is 50mV.
V
(V − V
)
Connect ILIM_ to V for a default 50mV current-limit
OUT IN
OUT
L
CC
ΔI
=
INDUCTOR
threshold. In adjustable mode, the current-limit thresh-
old is precisely 1/10 the voltage seen at ILIM_. For an
adjustable threshold, connect a resistive divider from
REF to analog ground (GND) with ILIM_ connected to
the center tap. The external 500mV to 2V adjustment
range corresponds to a 50mV to 200mV current-limit
threshold. When adjusting the current limit, use 1% tol-
erance resistors and a divider current of approximately
10µA to prevent significant inaccuracy in the current-
limit tolerance.
V ƒ
IN OSC
Ferrite cores are often the best choice, although pow-
dered iron is inexpensive and can work well at 200kHz.
The core must be large enough not to saturate at the
peak inductor current (I
):
PEAK
ΔI
INDUCTOR
I
=I
+
PEAK LOAD(MAX)
2
The current-sense method (Figure 8) and magnitude
determines the achievable current-limit accuracy and
power loss. Typically, higher current-sense limits pro-
vide tighter accuracy, but also dissipate more power.
Most applications employ a current-limit threshold
Transient Response
The inductor ripple current also impacts transient-
response performance, especially at low V - V dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The total output voltage sag is the sum of the voltage
sag while the inductor is ramping up and the voltage
sag before the next pulse can occur:
IN
OUT
(V ) of 50mV to 100mV, so the sense resistor can be
LIM
determined by:
R
= V
/ I
SENSE_
LIM_ LIM_
For the best current-sense accuracy and overcurrent
protection, use a 1% tolerance current-sense resistor
between the inductor and output as shown in Figure 8a.
This configuration constantly monitors the inductor cur-
rent, allowing accurate current-limit protection.
2
L(ΔI
)
ΔI
(T − ΔT)
LOAD(MAX)
LOAD(MAX)
V
=
+
SAG
2C
(V ×D
− V
)
C
OUT
OUT IN
MAX
OUT
where D
is maximum duty factor (see the Electrical
MAX
Alternatively, high-power applications that do not
require highly accurate current-limit protection may
reduce the overall power dissipation by connecting a
series RC circuit across the inductor (Figure 8b) with an
equivalent time constant:
Characteristics), T is the switching period (1 / f
), and
OSC
ΔT equals V
/ V x T when in PWM mode, or L x 0.2
OUT
OUT
IN
x I
/ (V - V
) when in skip mode. The amount of
MAX
IN
overshoot during a full-load to no-load transient due to
stored inductor energy can be calculated as:
16/MAX857
L
2
= C ×R
(ΔI
) L
EQ
EQ
LOAD(MAX)
R
V
≈
L
SOAR
2C
V
OUT OUT
where R is the inductor’s series DC resistance. In this
L
configuration, the current-sense resistance equals the
Setting the Current Limit
inductor’s DC resistance (R
= R ). Use the worst-
L
The minimum current-limit threshold must be great
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The
SENSE
case inductance and R values provided by the induc-
L
tor manufacturer, adding some margin for the
inductance drop over temperature and load.
peak inductor current occurs at I
the ripple current; therefore:
plus half
LOAD(MAX)
22 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
INPUT (V )
IN
C
IN
N
H
DH_
LX_
R
SENSE
L
C
OUT
D
L
DL_
MAX8716
MAX8717
MAX8756
MAX8757
N
L
PGND
CSH_
CSL_
a) OUTPUT SERIES RESISTOR SENSING
INPUT (V )
IN
C
IN
N
H
INDUCTOR
DH_
LX_
C
OUT
DL_
MAX8716
MAX8717
MAX8756
MAX8757
D
L
N
L
R
EQ
C
EQ
PGND
CSH_
CSL_
R
R
BIAS = EQ
b) LOSSLESS INDUCTOR SENSING
Figure 8. Current-Sense Configurations
Output Capacitor Selection
The output filter capacitor must have low enough equiv-
alent series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements. The output capaci-
tance must be high enough to absorb the inductor
energy while transitioning from full-load to no-load con-
ditions without tripping the overvoltage fault protection.
When using high-capacitance, low-ESR capacitors (see
the Output-Capacitor Stability Considerations section),
the filter capacitor’s ESR dominates the output voltage
ripple. So the output capacitor’s size depends on the
maximum ESR required to meet the output-voltage-rip-
V
R
R
IDLE ESR
V
=
RIPPLE(P−P)
SENSE
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tanta-
lums, OS-CONs, polymers, and other electrolytics).
When using low-capacity filter capacitors, such as
ceramic capacitors, size is usually determined by the
capacity needed to prevent V
and V
from
SOAR
SAG
causing problems during load transients. Generally,
once enough capacitance is added to meet the over-
shoot requirement, undershoot at the rising load edge
ple (V
) specifications:
RIPPLE(P-P)
V
= R
I
LIR
RIPPLE(P-P)
ESR LOAD(MAX)
In Idle Mode, the inductor current becomes discontinu-
ous, with peak currents set by the idle-mode current-
is no longer a problem (see the V
and V
equa-
SOAR
SAG
tions in the Transient Response section). However, low-
capacity filter capacitors typically have high-ESR zeros
that may effect the overall stability (see the Output-
Capacitor Stability Considerations section).
sense threshold (V
= 0.2V
). In Idle Mode, the
LIMIT
IDLE
no-load output ripple can be determined as follows:
______________________________________________________________________________________ 23
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Output-Capacitor Stability Considerations
Stability is determined by the value of the ESR zero rel-
ative to the switching frequency. The boundary of insta-
bility is given by the following equation:
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output-voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
ƒ
SW
π
ƒ
≤
ESR
where:
1
ƒ
=
ESR
2πR
C
ESR OUT
Input Capacitor Selection
For a typical 300kHz application, the ESR zero frequen-
cy must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use
at the time of publication have typical ESR zero fre-
quencies of 25kHz. In the design example used for
The input capacitor must meet the ripple-current
requirement (I
) imposed by the switching currents.
RMS
For an out-of-phase regulator, the total RMS current in
the input capacitor is a function of the load currents,
the input currents, the duty cycles, and the amount of
overlap as defined in Figure 9.
inductor selection, the ESR needed to support 25mV
P-P
ripple is 25mV/1.5A = 16.7mΩ. One 220µF/4V SANYO
polymer (TPE) capacitor provides 15mΩ (max) ESR.
This results in a zero at 48kHz, well within the bounds
of stability.
The 40/60 optimal interleaved architecture of the
MAX8716/MAX8717/MAX8756/MAX8757 allows the
input voltage to go as low as 8.3V before the duty
cycles begin to overlap. This offers improved efficiency
over a regular 180° out-of-phase architecture where the
duty cycles begin to overlap below 10V. Figure 9
For low input-voltage applications where the duty cycle
exceeds 50% (V
voltage should not be greater than twice the internal
slope-compensation voltage:
/ V ≥ 50%), the output ripple
IN
OUT
V
≤ 0.02 x V
RIPPLE
OUT
INPUT CAPACITOR RMS CURRENT
vs. INPUT VOLTAGE
where V
equals ΔI
x R
. The worst-
ESR
RIPPLE
INDUCTOR
5.0
case ESR limit occurs when V = 2 x V
, so the
OUT
IN
4.5
above equation can be simplified to provide the follow-
ing boundary condition:
4.0
IN PHASE
3.5
R
ESR
≤ 0.04 x L x ƒ
OSC
3.0
2.5
2.0
1.5
1.0
0.5
0
50/50 INTERLEAVING
Do not put high-value ceramic capacitors directly
across the feedback sense point without taking precau-
tions to ensure stability. Large ceramic capacitors can
have a high-ESR zero frequency and cause erratic,
unstable operation. However, it is easy to add enough
series resistance by placing the capacitors a couple of
inches downstream from the feedback sense point,
which should be as close as possible to the inductor.
40/60 OPTIMAL
INTERLEAVING
5V/5A AND 3.3V/5A
16/MAX857
6
8
10
12
V
14
(V)
16
18
20
IN
Unstable operation manifests itself in two related but
distinctly different ways: short/long pulses or cycle
skipping resulting in a lower switching frequency.
Instability occurs due to noise on the output or because
the ESR is so low that there is not enough voltage ramp
in the output voltage signal. This “fools” the error com-
parator into triggering too early or skipping a cycle.
Cycle skipping is more annoying than harmful, resulting
in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
INPUT RMS CURRENT FOR INTERLEAVED OPERATION
I
=
RMS
2
2
(I
(I
- I
OUT1 IN
)
(D - D ) + (I
LX1 OL
- I
)
(D - D ) +
LX2 OL
OUT2 IN
2
2
+ I
- I
)
D
+ I (1 - D - D + D
)
OL
OUT1 OUT2 IN
OL IN
LX1
LX2
V
V
V
V
OUT1
OUT2
D
OL
= DUTY-CYCLE OVERLAP FRACTION
D
=
D
=
LX2
LX1
IN
IN
V
I
+ V
I
OUT1 OUT1
OUT2 OUT2
I
=
IN
V
IN
INPUT RMS CURRENT FOR SINGLE-PHASE OPERATION
I
= I
RMS LOAD
V
(V - V
OUT IN
)
OUT
(
)
V
IN
Figure 9. Input RMS Current
24 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
shows the input-capacitor RMS current vs. input volt-
age for an application that requires 5V/5A and 3.3V/5A.
This shows the improvement of the 40/60 optimal inter-
leaving over 50/50 interleaving and in-phase operation.
The optimum occurs when the switching losses equal
the conduction (R ) losses. High-side switching
losses do not become an issue until the input is greater
than approximately 15V.
DS(ON)
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to power-up surge currents typical of systems
with a mechanical switch or connector in series with the
input. Choose a capacitor that has less than 10°C tem-
perature rise at the RMS input current for optimal relia-
bility and lifetime.
Calculating the power dissipation in high-side
MOSFETs (N ) due to switching losses is difficult, since
H
it must allow for difficult-to-quantify factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substi-
tute for breadboard evaluation, preferably including
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
verification using a thermocouple mounted on N :
H
PD (N SWITCHING)=
H
2
V
I
f
Q
I
⎛
⎞⎛
⎞
C
V
f
IN(MAX) LOAD SW
G(SW)
OSS IN SW
2
+
⎜
⎟⎜
⎟
η
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
⎝
⎠⎝
⎠
GATE
TOTAL
V
and V
. Ideally, the losses at V
where C
is the N , MOSFET's output capacitance,
H
IN(MIN)
IN(MAX)
IN(MIN)
, with
OSS
2
should be roughly equal to the losses at V
lower losses in between. If the losses at V
Q
, is the change needed to turn on the
IN(MAX)
IN(MIN)
G(SW)
are
N
MOSFET, and I
is the peak gate-drive
GATE
H
significantly higher, consider increasing the size of N .
source/sink current (1A typ).
H
Conversely, if the losses at V
are significantly
IN(MAX)
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied, due to the squared term in the switching-
loss equation (C x V 2 x f ). If the high-side MOSFET
higher, consider reducing the size of N . If V does
H
IN
not vary over a wide range, optimum efficiency is
achieved by selecting a high-side MOSFET (N ) that
H
IN
SW
DS(ON)
has conduction losses equal to the switching losses.
chosen for adequate R
at low battery voltages
Choose a low-side MOSFET (N ) that has the lowest
L
becomes extraordinarily hot when subjected to
possible on-resistance (R
), comes in a moder-
V
, consider choosing another MOSFET with
DS(ON)
IN(MAX)
ate-sized package (i.e., 8-pin SO, DPAK, or D2PAK),
and is reasonably priced. Ensure that the
MAX8716/MAX8717/MAX8756/MAX8757 DL_ gate dri-
ver can supply sufficient current to support the gate
charge and the current injected into the parasitic drain-
to-gate capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur. Switching losses are not an issue for the low-
side MOSFET since it is a zero-voltage switched device
when used in the step-down topology.
lower parasitic capacitance.
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum battery voltage:
⎡
⎤
⎥
⎛
⎞
V
OUT
2
⎢
PD (N RESISTIVE)= 1−
(I
) R
⎜
⎟
L
LOAD DS(ON)
V
⎢
⎣
⎥
⎦
IN(MAX)
⎝
⎠
The absolute worst case for MOSFET power dissipation
occurs under heavy-overload conditions that are
greater than I
but are not high enough to
LOAD(MAX)
Power MOSFET Dissipation
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
Worst-case conduction losses occur at the duty-factor
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at
minimum input voltage:
ΔI
⎛
⎞
INDUCTOR
I
=I
−
⎜
⎝
⎟
⎠
LOAD LIMIT
2
V
2
OUT
PD (N RESISTIVE) =
(I
) R
H
LOAD DS(ON)
V
IN
where I
is the peak current allowed by the current-
LIMIT
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
DS(ON)
limit circuit, including threshold tolerance and sense-
resistance variation. The MOSFETs must have a
relatively large heatsink to handle the overload power
dissipation.
R
required to stay within package power-dissi-
pation limits often limits how small the MOSFET can be.
______________________________________________________________________________________ 25
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Choose a Schottky diode (D ) with a forward-voltage
L
(ΔI ). This results in a minimum operating voltage
UP
drop low enough to prevent the low-side MOSFET’s
body diode from turning on during the dead time. As a
general rule, select a diode with a DC current rating
equal to 1/3 the load current. This diode is optional and
can be removed if efficiency is not critical.
defined by the following equation:
⎛
⎞
1
V
= V
+ V
+h
−1 (V
+ V
)
IN(MIN)
OUT
CHG
OUT
DIS
⎜
⎟
D
⎝
⎠
MAX
where V
and V
are the parasitic voltage drops in
DIS
CHG
Boost Capacitors
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
minimum input voltage is calculated with h = 1.
The boost capacitors (C
) must be selected large
BST
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
Maximum Input Voltage
The MAX8716/MAX8717/MAX8756/MAX8757 controller
includes a minimum on-time specification, which deter-
mines the maximum input operating voltage that main-
tains the selected switching frequency (see the
Electrical Characteristics table). Operation above this
maximum input voltage results in pulse-skipping opera-
tion, regardless of the operating mode selected by
SKIP. At the beginning of each cycle, if the output volt-
age is still above the feedback threshold voltage, the
controller does not trigger an on-time pulse, effectively
skipping a cycle. This allows the controller to maintain
regulation above the maximum input voltage, but forces
the controller to effectively operate with a lower switch-
ing frequency. This results in an input threshold voltage
Q
GATE
200mV
C
=
BST
where Q
is the total gate charge specified in the
GATE
high-side MOSFET’s data sheet. For example, assume
the FDS6612A n-channel MOSFET is used on the high
side. According to the manufacturer’s data sheet, a sin-
gle FDS6612A has a maximum gate charge of 13nC
at which the controller begins to skip pulses (V
):
IN(SKIP)
(V
= 5V). Using the above equation, the required
GS
⎛
⎞
⎟
boost capacitance would be:
1
V
= V
IN(SKIP)
OUT ⎜
ƒ
t
⎝
OSC ON(MIN) ⎠
13nC
100mV
C
=
= 0.065μF
BST
where f
is the switching frequency selected by FSEL.
OSC
PCB Layout Guidelines
Selecting the closest standard value, this example
requires a 0.1µF ceramic capacitor.
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching
power stage requires particular attention (Figure 10). If
possible, mount all the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PCB layout:
Applications Information
16/MAX857
Duty-Cycle Limits
Minimum Input Voltage
The minimum input operating voltage (dropout voltage)
is restricted by the maximum duty-cycle specification
(see the Electrical Characteristics table). For the best
dropout performance, use the slowest switching-fre-
quency setting (FSEL = GND). However, keep in mind
that the transient performance gets worse as the step-
down regulators approach the dropout voltage, so bulk
output capacitance must be added (see the voltage
sag and soar equations in the Design Procedure sec-
tion). The absolute point of dropout occurs when the
inductor current ramps down during the off-time
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PCBs (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single mΩ
of excess trace resistance causes a measurable effi-
ciency penalty.
(ΔI
) as much as it ramps up during the on-time
DOWN
26 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
• Minimize current-sensing errors by connecting
CSH_ and CSL_ directly across the current-sense
3) Group the gate-drive components (BST_ diode and
capacitor and LDO5 bypass capacitor) together
near the controller IC.
resistor (R
).
SENSE_
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
4) Make the DC-DC controller ground connections as
shown in Figures 1 and 10. This diagram can be
viewed as having two separate ground planes:
power ground, where all the high-power compo-
nents go; and an analog ground plane for sensitive
analog components. The analog ground plane and
power ground plane must meet only at a single point
directly at the IC.
• Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF,
FB_, CSH_, CSL_).
5) Connect the output power planes directly to the out-
put filter capacitor positive and negative terminals
with multiple vias. Place the entire DC-DC converter
circuit as close to the load as is practical.
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (N _ source, C , C
_, and D _
L
L
IN
OUT
Chip Information
TRANSISTOR COUNT: 5879
anode). If possible, make all these connections on
the top layer with wide, copper-filled areas.
PROCESS: BiCMOS
2) Mount the controller IC adjacent to the low-side
MOSFET, preferably on the back side opposite N
L_
and N to keep LX_, GND, DH_, and the DL_ gate-
H_
drive lines short and wide. The DL_ and DH_ gate
traces must be short and wide (50 mils to 100 mils
wide if the MOSFET is 1in from the controller IC) to
keep the driver impedance low and for proper adap-
tive dead-time sensing.
______________________________________________________________________________________ 27
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
CONNECT GND AND PGND TO THE
CONTROLLER AT ONE POINT
ONLY AS SHOWN
VIA TO POWER
GROUND
CONNECT THE
EXPOSED PAD TO
ANALOG GND
VIA TO V PIN
CC
VIA TO V
CC
BYPASS CAPACITOR
VIA TO REF
BYPASS CAPACITOR
VIA TO REF PIN
MAX8717/MAX8756/MAX8757
BOTTOM LAYER
MAX8717/MAX8756/MAX8757
TOP LAYER
KELVIN-SENSE VIAS
UNDER THE SENSE
RESISTOR
(REFER TO THE EVALUATION KIT)
DUAL
n-CHANNEL
MOSFET
INDUCTOR
SINGLE
n-CHANNEL
MOSFETS
INDUCTOR
DH
LX
DL
C
C
OUT
INPUT
OUT
OUTPUT
C
OUT
OUTPUT
GROUND
INPUT
GROUND
HIGH-POWER LAYOUT
Figure 10. PCB Layout Example
LOW-POWER LAYOUT
16/MAX857
Ordering Information (continued)
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28 Thin QFN
5mm x 5mm
MAX8717ETI+
MAX8756ETI+
MAX8757ETI+
T2855-6
T2855-6
T2855-6
28 Thin QFN
4mm x 4mm
28 Thin QFN
5mm x 5mm
+Denotes a lead-free package.
28 ______________________________________________________________________________________
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
16/MAX857
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
21-0139
F
2
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
21-0139
F
2
______________________________________________________________________________________ 29
Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
16/MAX857
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
30 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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