MAX8770_技术文档

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

19-3913; Rev 0; 10/05

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

General Description

Features

The MAX8770/MAX8771/MAX8772 are 2/1-phase inter-

leaved Quick-PWM™ step-down VID power-supply con-

trollers for notebook CPUs. True out-of-phase operation

reduces input ripple current requirements and output volt-

age ripple while easing component selection and layout

difficulties. The Quick-PWM control provides instanta-

neous response to fast load current steps. Active voltage

positioning reduces power dissipation and bulk output

capacitance requirements and allows ideal positioning

compensation for tantalum, polymer, or ceramic bulk out-

put capacitors.

♦ Single/Dual-Phase, Quick-PWM Controller

0.4% V_OUTAccuracy Over Line, Load, and

Temperature

♦

♦ 7-Bit On-Board DAC: 0 to +1.5000V Output Adjust

Range

♦ Dynamic Phase Selection Optimizes Active/Sleep

Efficiency

♦ Transient Phase Overlap Reduces Output

Capacitance

The MAX8770/MAX8771/MAX8772 are intended for two

different notebook CPU core applications: either bucking

down the battery directly to create the core voltage, or

else bucking down the +5V system supply. The single-

stage conversion method allows this device to directly

step down high-voltage batteries for the highest possible

efficiency. Alternatively, 2-stage conversion (stepping

down the +5V system supply instead of the battery) at

higher switching frequency provides the minimum possi-

ble physical size.

♦ Integrated Boost Switches

♦ Active Voltage Positioning with Adjustable Gain

♦ Programmable 200kHz to 600kHz Switching

Frequency

♦ Accurate Current Balance and Current Limit

♦ Adjustable Slew-Rate Control

♦ Power-Good (PWRGD), Clock Enable (CLKEN),

Power Monitor (POUT) and Thermal Fault

(VRHOT) Outputs

A slew-rate controller allows controlled transitions

between VID codes, controlled soft-start and shutdown,

and controlled exit from suspend. A thermistor-based

temperature sensor provides a programmable thermal-

fault output (VRHOT). A power-monitor output (POUT)

provides an analog voltage output proportional to the

power consumed by the CPU. The MAX8770/MAX8771/

MAX8772 include output undervoltage protection (UVP)

and thermal protection, and the MAX8770/MAX8771 also

include overvoltage protection (OVP). When any of these

protection features detect a fault, the controller shuts

down. A voltage-regulator power-OK (PWRGD) output

indicates the output is in regulation. A clock enable

(CLKEN) output provides proper system startup sequenc-

ing. Additionally, the MAX8771 has a phase-good

(PHASEGD) output, and the MAX8770/MAX8772 includes

true differential current sense.

♦ Phase Fault (PHASEGD) Output (MAX8771)

♦ Drives Large Synchronous Rectifier MOSFETs

♦ 4V to 26V Battery-Input-Voltage Range

♦ Output OV Protection (MAX8770/MAX8771)

♦ UV and Thermal-Fault Protection

♦ Power Sequencing and Timing

♦ Soft-Startup and Soft-Shutdown

Ordering Information

PART

TEMP

PIN-PACKAGE

MAX8770GTL+ -40°C to +105°C 40 Thin QFN 6mm x 6mm

MAX8771GTL+ -40°C to +105°C 40 Thin QFN 6mm x 6mm

MAX8772GTL+ -40°C to +105°C 40 Thin QFN 6mm x 6mm

+Denotes lead-free package.

The MAX8770/MAX8771/MAX8772 implement the Intel

IMVP-6+ code set and the required IMVP-6+ control sig-

nals. The MAX8770/MAX8771/MAX8772 are available in a

40-pin TQFN package.

Applications

IMVP-6+ Core Supply

Multiphase CPU Core Supply

Voltage-Positioned, Step-Down Converters

Notebook/Desktop Computers

Blade Servers

Pin Configuration appears at end of data sheet.

Intel is a registered trademark of Intel, Corp.

Quick-PWM is a trademark of Maxim Integrated Products, Inc.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ABSOLUTE MAXIMUM RATINGS

CC DD

D0–D6, CSP_ to GND...............................................-0.3V to +6V

CSN12 (MAX8771) to GND ......................................-0.3V to +6V

CSN_ (MAX8770/MAX8772) to GND........................-0.3V to +6V

PHASEGD (MAX8771) to GND.................................-0.3V to +6V

THRM, VRHOT, CLKEN to GND...............................-0.3V to +6V

V

, V

to GND .....................................................-0.3V to +6V

BST_ to GND ..........................................................-0.3V to +36V

LX_ to BST_ ..............................................................-6V to +0.3V

BST_ to VDD...........................................................-0.3V to +30V

DH_ to LX_ ..................................................-0.3V to V

+0.3V

BST_

REF Short Circuit to GND...........................................Continuous

Continuous Power Dissipation

TIME, PWRGD, POUT to GND......................-0.3V to V

REF, FB, CCV, CCI to GND ..........................-0.3V to V

SHDN to GND (Note 1)...........................................-0.3V to +14V

TON to GND ...........................................................-0.3V to +30V

DPRSLPVR, DPRSTP, PSI to GND ...........................-0.3V to +6V

GNDS, PGND_ to GND .........................................-0.3V to +0.3V

+ 0.3V

40-Pin 6mm x 6mm Thin QFN

CC

(derate 23.2mW/°C above +70°C).............................2051mW

Operating Temperature Range .........................-40°C to +105°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +165°C

Lead Temperature (soldering, 10s) .................................+300°C

DL_ to PGND_...............................................-0.3V to V

+ 0.3V

DD

Note 1: SHDN may be forced to 12V for the purpose of debugging prototype boards using the no-fault test mode, which disables

fault protection and disables overlapping operation.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1. V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)

A

PARAMETER

PWM CONTROLLER

Input Voltage Range

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

, V

CC DD

4.5

5.5

V

DAC codes from

0.8375V to 1.500V

-0.4

+0.4

%

Includes load-

regulation error

(Note 2)

DAC codes from

0.500V to 0.825V

DC Output-Voltage Accuracy

V

-4

+4

OUT

mV

DAC codes below

0.4875V

-10

+10

Boot Voltage

V

A

1.19

-200

0.95

-25

1.20

1.21

+200

1.05

+2

V

BOOT

GNDS

GNDS Input Range

GNDS Gain

mV

V/V

µA

∆V

/∆V

, -200mV ≤ V ≤ +200mV

GNDS

1.00

-15

OUT

GNDS

GNDS Input Bias Current

FB Input Bias Current

I

CSP_ = CSN_ for both enabled phases

-2

+2

FB

R

= 96.75kΩ

= 200kΩ

142

300

425

167

333

500

0.01

192

366

575

0.1

TON

V

= 12V

IN

On-Time Accuracy (Note 3)

t

ns

µA

V

ON

= V

= 1.2V

CCI

FB

= 303.25kΩ

TON Shutdown Input Current

SHDN = 0, V = 26V, V

= V

= 0 or 5V

DD

IN

CC

Minimum FB and CCI Voltages

for Pseudo-Fixed-Frequency

Operation

Switching frequency is reduced if FB and/or

CCI are less than this value

0.2

0.25

375

Minimum Off-Time

t

(Note 3)

300

ns

OFF(MIN)

2

_______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

R

= 71.5kΩ (12.5mV/µs nominal)

-10

+10

TIME

= 35.7kΩ (25mV/µs nominal) to 178kΩ

TIME

-15

+15

(5mV/µs nominal)

DPRSTP = high, DPRSLPVR = high,

TIME Slew-Rate Accuracy

R

TIME

= 35.7kΩ to 178kΩ, SR = 6.25mV/µs

-20

+20

%

nominal to 1.25mV/µs nominal

Startup and shutdown, R = 35.7kΩ

TIME

(3.125mV/µs nominal) to 178kΩ

-20

+20

(0.625mV/µs nominal)

BIAS AND REFERENCE

Measured at V , FB forced above the

CC

Quiescent Supply Current (V

)

I

5

10

1

mA

µA

CC

DD

regulation point, DPRSLPVR = V

CC

Measured at V , FB forced above the

DD

Quiescent Supply Current (V

)

DD

0.01

regulation point, DPRSLPVR = V

CC

Shutdown Supply Current (V

Reference Voltage

)

I

Measured at V , SHDN = GND

0.01

2.000

-0.2

1

µA

V

CC

CC(SHDN)

CC

)

DD

Measured at V , SHDN = GND

DD

DD(SHDN)

V

= 4.5V to 5.5V, I

= 0 to 500µA

= -100µA to 0

= 0

1.986

-2

2.014

REF

CC

REF

I

Reference Load Regulation

∆V

mV

REF

0.21

6.2

350

1.85

FAULT PROTECTION

Measured at FB with respect to unloaded

output voltage; rising edge;

PWM mode or skip mode after output reaches

the regulation voltage

250

300

mV

Output Overvoltage Protection

Threshold

(MAX8770/MAX8771 Only)

V

OVP

Skip mode and output

have not reached the

regulation voltage

1.75

1.80

0.8

10

Measured at FB;

rising edge

V

Minimum OVP threshold

Output Overvoltage-

Propagation Delay

t

FB forced 25mV above trip threshold

µs

OVP

(MAX8770/MAX8771 Only)

Output Undervoltage

Protection Threshold

Measured at FB with respect to unloaded

output voltage

V

-450

20

-400

10

-350

100

mV

µs

UVP

Output Undervoltage

Propagation Delay

t

FB forced 25mV below trip threshold

UVP

Measured from the time when FB reaches the

boot target voltage based on the slew rate set

CLKEN Startup Delay

(Boot Time Period)

t

60

µs

BOOT

by R

TIME

_______________________________________________________________________________________

3

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PWRGD, PHASEGD Startup

Delay

Measured at startup from the time when

CLKEN goes low

t

3

5

8

ms

PWRGD

Measured at FB with

respect to unloaded

output voltage

Lower threshold, falling

edge (undervoltage)

-350

-300

-250

+250

CLKEN, PWRGD Threshold

mV

Upper threshold, rising

edge (overvoltage)

15mV hysteresis (typ)

+150

+200

10

CLKEN, PWRGD, PHASEGD

Delay

FB forced 25mV outside the PWRGD trip

thresholds

µs

Measured from the time when FB reaches the

target voltage based on the slew rate set by

CLKEN, PWRGD, PHASEGD

Transition Blanking Time

t

20

32

BLANK

R

TIME

PHASEGD Transition Blanking

Time

Number of DH2 pulses from when phase 2 is

enabled

t

Cycles

PHASEGD

V(CCI, FB),

0.4V ≤ V(FB) ≤ 1.5V

Lower threshold,

0.6V nominal

FB

-20

+20

0.4

1

PHASEGD Window

Comparator Thresholds

mV

Upper threshold,

15mV hysteresis (typ)

1.4V nominal

FB

CLKEN, PWRGD, PHASEGD

Output Low Voltage

I

= 3mA

V

SINK

CLKEN, PWRGD, PHASEGD

Leakage Current

High state, CLKEN, PWRGD, PHASEGD forced

to 5V

µA

%

Measured at THRM, with respect to V ; falling

CC

edge, 115mV hysteresis (typ)

VRHOT Trip Threshold

VRHOT Delay

29.5

30

30.5

THRM forced 25mV below the VRHOT trip

threshold; falling edge

t

10

µs

VRHOT

VRHOT Output On-Resistance

VRHOT Leakage Current

THRM Input Leakage

R

Low state

3.5

11

1

Ω

VRHOT

High state. VRHOT forced to 5V

µA

nA

-100

4.1

+100

V

Undervoltage Lockout

Rising edge, 50mV hysteresis, DL_ pulled low

below this level

CC

V

4.25

4.45

V

UVLO(VCC)

Threshold

Falling edge, typical hysteresis = 1.1V, faults

V

Power-On Reset

CC

cleared and DL_ forced high when V

below this level

falls

1.8

V

CC

Threshold

Thermal Shutdown Threshold

T

Hysteresis = 15°C

160

°C

SHDN

4

_______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)

A

PARAMETER

DROOP AND BALANCE

DC Droop Amplifier Offset

SYMBOL

CONDITIONS

MIN

-1.0

590

TYP

MAX

UNITS

mV

+1.0

610

∆I /(Σ∆V ),

FB

CS

DC Droop Amplifier

Transconductance

G

V

= V _ = 1.2V,

600

µS

m(FB)

FB

CSN

V

_ - V

_ = 0 to +60mV

CSN

CSP

Current-Balance

Preamplifier Offset

[V(CSP1, CSN_) - V(CSP2, CSN_)] at I

= 0

-1.0

+1.0

mV

µS

CCI

∆ I /∆ [V(CSP1, CSN_), V(CSP2, CSN_)]

CCI

Current-Balance Amplifier

Transconductance

CCI = FB = CSN_ = 0.45V to 1.5V, and

V(CSP_, CSN_) = -10mV to +10mV

G

200

m(CCI)

CURRENT LIMIT

Valley Current-Limit Threshold

(Positive)

V

CSP_ - CSN_

CSP_, CSN_

19.5

-35

22.5

25.5

-25

mV

LIMIT

Valley Current-Limit Threshold

(Negative)

-30

2.5

mV

Zero Crossing Threshold

V

PGND1 - LX1, DPRSLPVR = high (skip mode)

ZX

CSP_

-0.2

-0.4

+0.2

+0.4

Current-Sense Input Current

CSN_

µA

CSN12 (MAX8771)

Common-Sense Common-Mode

Input Range

CSP_ -CSN_

CSP2

0

2

V

Phase 2 Disable Threshold

Gate Drivers

3

V

- 1 V - 0.4

CC CC

GATE DRIVERS

High state (pullup)

0.9

0.7

2.5

2.0

0.5

DH_ Gate Driver

On-Resistance

BST_ -LX_ forced

to 5V

R

Ω

A

ON(DH_)

Low state (pulldown)

High state (pullup)

0.7

DL_ Gate Driver

On-Resistance

R

ON(DL_)

Low state (pulldown)

0.25

DH_ Gate Driver Source/Sink

Current

I

DH_ forced to 2.5V, BST_ - LX_ forced to 5V

2.2

DH

DL_ Gate Driver Source Current

DL_ Gate Driver Sink Current

I

DL_ forced to 2.5V

DH_ low to DL_ high

DL_ low to DH_ high

2.7

8

A

DL(SOURCE)

I

DL(SINK)

18

9

25

20

Driver Propagation Delay

DL_ Transition Time

DH_ Transition Time

ns

DL_ falling, C

= 3nF

DL_

DL_ rising, C

DH_ falling, C

= 3nF

DH_

DH_ rising, C

_______________________________________________________________________________________

5

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

= 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). T = 0°C to +85°C, unless otherwise specified. Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Internal Boost Charging Switch

On-Resistance

V

to BST_

10

20

Ω

DD

FB

POWER MONITOR

Power-Monitor Output Voltage

for Typical HFM Conditions

- V

= 1.200V, Σ∆V = 30mV

2.08

1.72

2.16

1.80

72

2.24

1.88

73.5

V

GNDS

CS

Power-Monitor Gain Referred

to Feedback Voltage

Σ∆V = 30mV

V/V

CS

Power-Monitor Gain Referred

to ΣV (CSP_, CSN)

V

- V

= 1.200V, T = +25°C to +85°C

70.5

-6

FB

GNDS

A

Sourcing: I

= 0 to 500µA

µV/µA

mV

POUT

Power-Monitor Load

Regulation

Sinking: I

= 0 to 100µA

50

POUT

LOGIC AND I/O

SHDN, DPRSLPVR, rising edge,

hysteresis = 200mV

Logic Input High Voltage

V

1.2

11

1.7

2.3

13

V

IH

SHDN No-Fault Level

To enable no-fault mode

Low-Voltage Logic Input High

Voltage

V

D0–D6, PSI, DRPSTP

0.67

IHLV

Low-Voltage Logic Input Low

Voltage

V

D0–D6, PSI, DRPSTP

0.33

+1

V

ILLV

Logic Input Current

SHDN, PSI, DPRSLPVR, D0–D6 = 0 to 5V

-1

µA

6

_______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1. V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

= 1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). T = -40°C to +105°C, unless otherwise specified. Typical values are at T

=

A

+25°C.) (Note 4)

PARAMETER

PWM CONTROLLER

Input Voltage Range

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

V

, V

CC DD

4.5

5.5

V

DAC codes from

0.8375V to 1.500V

-0.6

+0.6

%

Includes load-

regulation error

(Note 2)

DAC codes from

0.500V to 0.825V

DC Output Voltage Accuracy

V

-6

+6

OUT

mV

DAC codes below

0.4875V

-15

+15

Boot Voltage

V

1.182

-200

1.218

+200

V

BOOT

GNDS

GNDS Input Range

mV

∆V

+200mV

/∆V

-200mV ≤ V

≤

GNDS

OUT

GNDS,

GNDS Gain

A

0.95

1.05

V/V

ns

GNDS

R

TON

R

TON

R

TON

= 96.75kΩ

= 200kΩ

142

300

425

192

366

575

V

= 12V

IN

On-Time Accuracy (Note 3)

t

ON

= V

= 1.2V

CCI

FB

= 303.25kΩ

Minimum FB and CCI Voltages

for Pseudo-Fixed-Frequency

Operation

Switching frequency is reduced if FB and/or

CCI are less than this value

0.25

V

Minimum Off-Time

t

(Note 3)

375

+10

ns

OFF(MIN)

R

TIME

= 71.5kΩ (12.5mV/µs nominal)

-10

-15

R

TIME

= 35.7kΩ (25mV/µs nominal) to

+15

178kΩ (5mV/µs nominal)

DPRSTP = high, DPRSLPVR = high, R

= 35.7kΩ to 178kΩ, SR = 6.25mV/µs

nominal to 1.25mV/µs nominal

TIME

TIME Slew-Rate Accuracy

BIAS AND REFERENCE

%

-20

+20

Startup and shutdown,

R

TIME

= 35.7kΩ (3.125mV/µs nominal) to

+20

178kΩ (0.625mV/µs nominal)

Measured at V , FB forced above the

CC

Quiescent Supply Current (V

)

I

10

1

mA

µA

CC

regulation point, DPRSLPVR = V

CC

Measured at V , FB forced above the

DD

Quiescent Supply Current (V

DD

regulation point, DPRSLPVR = V

CC

Shutdown Supply Current (V

Reference Voltage

)

I

Measured at V , SHDN = GND

1

µA

V

CC

CC(SHDN)

CC

)

DD

Measured at V , SHDN = GND

DD

DD(SHDN)

V

= 4.5V to 5.5V, I

= 0 to 500µA

= -100µA to 0

= 0

1.98

-2

2.02

REF

CC

REF

I

Reference Load Regulation

∆V

mV

REF

6.2

_______________________________________________________________________________________

7

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. V = V = V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _ =

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). T = -40°C to +105°C, unless otherwise specified. Typical values are at T = +25°C.)

A

(Note 4)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

FAULT PROTECTION

Measured at FB with respect to unloaded

output voltage, rising edge,

PWM mode, or skip mode after output

reaches the regulation voltage

250

350

mV

Output Overvoltage Protection

Threshold

(MAX8770/MAX8771 Only)

V

OVP

UVP

Skip mode and

output have not

reached the

Measured at FB,

rising edge

1.75

1.85

V

regulation voltage

Output Undervoltage Protection

Threshold

Measured at FB with respect to unloaded

output voltage

-450

20

3

-350

100

8

mV

µs

Measured from the time when FB reaches

the boot target voltage based on the slew

CLKEN Startup Delay (Boot Time

Period)

t

BOOT

rate set by R

TIME

PWRGD, PHASEGD Startup

Delay

Measured at startup from the time when

CLKEN goes low

t

ms

PWRGD

Measured at FB

Lower threshold,

with respect to

falling edge

-350

-250

unloaded output

(undervoltage)

voltage

CLKEN, PWRGD Threshold

mV

Upper threshold,

15mV hysteresis

rising edge

(typ)

+150

+250

(overvoltage)

V(CCI,FB),

0.4V ≤ V(FB) ≤ 1.5V 0.6V nominal

Lower threshold,

-20

+20

0.4

FB

PHASEGD Window Comparator

Thresholds

mV

V

15mV hysteresis

(typ)

Upper threshold,

1.4V nominal

FB

CLKEN, PWRGD, PHASEGD

Output Low Voltage

I

= 3mA

SINK

Measured at THRM, with respect to V

falling edge, 115mV hysteresis (typ)

,

CC

VRHOT Trip Threshold

V

29.5

4.1

30.5

11

%

Ω

V

HOT

VRHOT Output On-Resistance

R

Low state

VRHOT

V

Undervoltage Lockout

Rising edge, 50mV hysteresis, DL_ pulled

low below this level

CC

V

4.45

UVLO(VCC)

Threshold

DROOP AND BALANCE

DC Droop Amplifier Offset

-1.5

580

+1.5

620

mV

µs

∆I /(Σ∆V ),

FB

CS

DC Droop Amplifier

Transconductance

G

V

= V

_ = 1.2V,

CSN

m(FB)

FB

V

_ - V

_ = 0 to +60mV

CSN

CSP

Current-Balance

Preamplifier Offsets

[V(CSPI, CSN_) - V(CPS2, CSN_)]

at I = 0

-1.5

+1.5

mV

CCI

8

_______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. V = V = V

= V

= 5V, DPRSLPVR = GNDS = PGND_ = GND, V = V

= V _ = V _ =

CSP CSN

DD

CC

SHDN

PSI

DPRSTP

FB

CCI

1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). T = -40°C to +105°C, unless otherwise specified. Typical values are at T = +25°C.)

A

(Note 4)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CURRENT LIMIT

Valley Current-Limit Threshold

(Positive)

V

CSP_ - CSN_

18.5

-36

26.5

-24

2

mV

LIMIT

Valley Current-Limit Threshold

(Negative)

Current-Sense Common-Mode

Input Range

CSP_, CSN_

CSP2

0

3

V

Phase 2 Disable Threshold

V

- 0.4

CC

GATE DRIVERS

High state (pullup)

2.5

2.0

0.5

BST_ – LX_ forced

to 5V

DH_ Gate Driver On-Resistance

DL_ Gate Driver On-Resistance

Driver Propagation Delay

R

Ω

ON(DH_)

Low state (pulldown)

High state (pullup)

R

Ω

ON(DL_)

Low state (pulldown)

DH_ Low to DL_ High

DL_ Low to DH_ High

15

9

ns

Internal Boost Charging Switch

On-Resistance

V

to BST_

20

Ω

DD

POWER MONITOR

Power-Monitor Output Voltage for

Typical HFM Conditions

V

- V

= 1.200V, Σ∆V = 30mV

2.04

1.70

2.28

1.90

74

V

FB

GNDS

CS

Power-Monitor Gain Referred to

Feedback Voltage

Σ∆V = 30mV

V/V

CS

Power-Monitor Gain Referred to

ΣV(CSP_,CSN)

V

- V

= 1.200V

70

-6

V/V

FB

GNDS

Power-Monitor Load Regulation

Sourcing: I

= 0 to 500µA

µV/µA

POUT

LOGIC AND I/O

SHDN, DPRSLPVR, rising edge,

hysteresis = 200mV

Logic-Input High Voltage

V

1.2

2.3

V

IH

Low-Voltage Logic-Input High

Low-Voltage Logic-Input Low

V

D0–D6, PSI, DRPSTP

0.67

V

IHLV

V

0.33

ILLV

Note 2: DC output accuracy specifications refer to the trip level of the error amplifier. The output voltage has a DC regulation higher

than the trip level by 50% of the output ripple. When pulse skipping, the output rises by approximately 1.5% when transition-

ing from continuous conduction to no load.

Note 3: On-time and minimum off-time specifications are measured from 50% to 50% at the DH_ and DH_ pins, with LX_ forced to

GND, BST_ forced to 5V, and a 500pF capacitor from DH_ to LX_ to simulate external MOSFET gate capacitance. Actual in-

circuit times may be different due to MOSFET switching speeds.

Note 4: Specifications to T = -40°C and +105°C are guaranteed by design and are not production tested.

A

_______________________________________________________________________________________

9

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Typical Operating Characteristics

(Circuit of Figure 1. V = 12V, V

IN

wise specified.)

= V , SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, T = 25°C, unless other-

CC

DD

A

OUTPUT VOLTAGE vs. LOAD CURRENT

EFFICIENCY vs. LOAD CURRENT

(V = 0.9500V)

OUT(LFM)

(V

= 1.2875V)

(V

= 1.2875V)

OUT(HFM)

0.98

0.96

0.94

0.92

0.90

0.88

1.4

1.3

1.2

1.1

100

90

80

70

60

50

12V

SKIP MODE

PWM MODE

7V

20V

PSI = GND

16

0

4

8

12

20

0

10

20

30

40

50

0.1

1

10

100

LOAD CURRENT (A)

EFFICIENCY vs. LOAD CURRENT

OUTPUT VOLTAGE

EFFICIENCY vs. LOAD CURRENT

(V

= 0.9500V)

vs. LOAD CURRENT (V

= 0.6500V)

OUT(C4)

(V

= 0.6500V)

OUT(LFM)

OUT(C4)

100

90

80

70

60

50

0.68

0.66

0.64

0.62

0.60

0.58

100

90

80

70

60

50

12V

7V

20V

PSI - GND

DPRSLPVR = GND

DPRSLPVR = V

CC

DPRSLPVR = V

CC

0.1

1

10

100

0

4

8

12

16

20

0.1

1

10

100

LOAD CURRENT (A)

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE (V = 1.2875V)

SWITCHING FREQUENCY

vs. LOAD CURRENT

OUT(HFM)

400

150

V

= 0.9500V

OUT(LFM)

125

100

75

50

25

0

300

200

100

0

I

IN

V

= 1.2875V

OUT(HFM)

I + I

CC DD

DPRSLPVR = GND

DPRSLPVR = V

CC

0

10

20

30

40

50

0

5

10

15

20

25

LOAD CURRENT (A)

INPUT VOLTAGE (V)

10 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Typical Operating Characteristics (continued)

(Circuit of Figure 1. V = 12V, V

IN

wise specified.)

= V , SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, T = 25°C, unless other-

CC

DD

A

NO-LOAD SUPPLY CURRENT

vs. INPUT VOLTAGE AT SKIP MODE

OUTPUT OFFSET VOLTAGE DISTRIBUTION

REFERENCE VOLTAGE DISTRIBUTION

100

80

60

40

20

0

100

80

60

40

20

0

10

1

SAMPLE SIZE = 200

1.2000V

0.8125V

SAMPLE SIZE = 200

I

+ I

CC DD

0.1

0.01

I

IN

DPRSLPVR = V

CC

0

5

10

15

20

25

-3

-2

-1

1

2

3

1.990

2.000

2.010

INPUT VOLTAGE (V)

OUTPUT OFFSET VOLTAGE (mV)

REFERENCE VOLTAGE (V)

G

m(FB)

TRANSCONDUCTANCE

DISTRIBUTION

INDUCTOR CURRENT DIFFERENCE

vs. LOAD CURRENT

100

80

60

40

20

0

0.3

0.2

0.1

0

SAMPLE SIZE = 200

R

= 1mΩ

SENSE

595

597

599

601

603

605

0

5

10

15

20

25

TRANSCONDUCTANCE (µS)

INPUT VOLTAGE (V)

SOFT-START (UP TO CLKEN)

SOFT-START (UP TO PWRGD)

MAX8770 toc15

MAX8770 toc14

A

0

B

C

D

0

B

C

D

0

E

F

0

E

F

G

0

R

= 65mΩ

LOAD

R

= 65mΩ

LOAD

200µs/div

D. V , 1V/div

1ms/div

E. V , 1V/div

A. SHDN, 5V/div

B. CLKEN, 10V/div

C. LX1, 10V/div

OUT

A. SHDN, 5V/div

OUT

E. I , 10A/div

LXI

B. CLKEN, 10V/div

C. PWRGD, 10V/div

D. PHASEGD, 10V/div

F. I , 10A/div

G. I , 10V/div

LX2

LXI

F. I , 10V/div

LX2

______________________________________________________________________________________ 11

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Typical Operating Characteristics (continued)

(Circuit of Figure 1. V = 12V, V

IN

wise specified.)

= V , SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, T = 25°C, unless other-

CC

DD

A

LFM LOAD TRANSIENT

HFM LOAD TRANSIENT

(V = 1.2875V

SHUTDOWN WAVEFORMS

(V

OUT(LFM)

= 0.9500V

OUT(HFM)

MAX8770 toc16

MAX8770 toc17

MAX8770 toc18

A

0

A

B

A

B

0

1.28V

C

0

1V

1.22V

20A

0.94V

0.92V

D

E

F

C

D

0

10A

0

C

G

R

= 65mΩ

LOAD

PSI = 0

200µs/div

E. V , 1V/div

40µs/div

= 5A TO 36A, 10A/div

40µs/div

= 5A TO 15A, 10A/div

A. SHDN, 5V/div

B. CLKEN, 10V/div

C. DL1, 10V/div

OUT

C. I , 10A/div

LXI

D. I ,10A/div

LX2

C. I , 10A/div

LXI

D. I ,10A/div

LX2

A. I

OUT

F. I , 10A/div

LXI

B. V , 50mV/div

OUT

B. V , 50mV/div

OUT

G. I , 10V/div

LX2

D. PWRGD, 10V/div

ENTERING DEEPER SLEEP

EXITING TO LFM

ENTERING DEEPER SLEEP

EXITING TO NEAREST VID

ENTERING DEEPER SLEEP

EXITING TO LFM

MAX8770 toc19

MAX8770 toc20

MAX8770 toc21

A

B

A

B

0

B

0

1.28V

C

0

D

E

0

D

E

D

E

100µs/div

D. I , 10A/div

E. I , 10A/div

LX2

A. DPRSTP, 5V/div

B. DPRSLPVR, 5V/div

LXI

D. I , 10A/div

E. I , 10A/div

LX2

D. I , 10A/div

LXI

E. I , 10A/div

LX2

A. DPRSTP, 5V/div

B. DPRSLPVR, 5V/div

A. DPRSTP, 5V/div

B. DPRSLPVR, 5V/div

C. V , 500mV/div

LXI

C. V , 500mV/div

OUT

C. V , 500mV/div

OUT

I

= 2A

OUT

I

= 2A

I

= 2A

OUT

12 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Typical Operating Characteristics (continued)

(Circuit of Figure 1. V = 12V, V

IN

wise specified.)

= V , SHDN = PSI = 5V, DPRSLPVR = GND, D0–D6 set for 1.1500V, T = 25°C, unless other-

CC

DD

A

D0 DYNAMIC VID CODE CHANGE

PSI + 1-LSB TRANSITION

D3 DYNAMIC VID CODE CHANGE

MAX8770 toc23

MAX8770 toc24

MAX8770 toc22

A

B

A

B

0

A

B

0

0.93V

C

D

E

C

D

C

D

0

20µs/div

40µs/div

C. I , 10A/div

D. I , 10A/div

A. D0, 5V/div

C. I , 10A/div

D. I , 10A/div

LXI

LX2

A. D3, 5V/div

LXI

LX2

B. V , 20mV/div

D. I , 10A/div

LXI

E. I , 10A/div

A. PSI, 5V/div

B. D0, 5V/div

B. V , 200mV/div

OUT

I

= 10A

I

= 10A

OUT

LX2

C. V , 20mV/div

OUT

I

= 10A

OUT

POWER MONITOR -

VID TRANSITION RESPONSE

POWER MONITOR vs. LOAD CURRENT

POWER MONITOR vs. OUTPUT VOLTAGE

MAX8770 TOC28

4

3

2

1

0

1.0

0.8

0.6

0.4

0.2

0

R

V

= 1mΩ

= 1.2875V

SENSE

R

= 1mΩ

= 10A

SENSE

0

A

OUT

I

OUT

B

C

D

1.185

0.72V

0

E

F

0

40µs/div

0

10

20

LOAD CURRENT (A)

30

40

0

0.3

0.6

0.9

1.2

1.5

OUTPUT VOLTAGE (V)

A. D3, 5V/div

B. V , 200mV/div

D. POUT, 2V/div

E. I , 10A/div

OUT

LX1

C. POUT WITH RC FILTER

F. I , 10A/div

LX2

(10kΩ, 0.1µF), 200mV/div

I

= 10A

OUT

______________________________________________________________________________________ 13

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Pin Description

NAME

FUNCTION

Clock-Enable Logic Output. This inverted logic output indicates when the output voltage sensed at FB is in

regulation. CLKEN is forced low during VID transitions. Except during startup, CLKEN is the inverse of

PWRGD. See the Startup Timing Diagram (Figure 9). When in pulse-skipping mode (DPRSLPVR high), the

upper CLKEN threshold is disabled.

1

CLKEN

Open-Drain, Power-Good Output. After output-voltage transitions, except during power-up and power-

down, if FB is in regulation then PWRGD is high impedance. During startup, PWRGD is held low and

continues to be low while the part is in boot mode and until 5ms (typ) after CLKEN goes low.

PWRGD is forced low in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is

active (output-voltage transitions).

2

PWRGD

When in pulse-skipping mode (DPRSLPVR high), the upper PWRGD threshold comparator is blanked.

A pullup resistor on PWRGD causes additional finite shutdown current.

Logic Input to Indicate Power Usage. PSI and DPRSLPVR together determine the operating mode as

shown in the truth table below. Blank the PWRGD upper threshold when the part is in skip mode. The part

is forced into full-phase PWM mode during startup, while in boot mode, during the transition from

boot mode to VID mode and during shutdown:

3

4

PSI

DPRSLPVR PSI

Mode

1

0

1

0

1

Very low current (1-phase skip)

Low current (approximately 3A) (1-phase skip)

Intermediate power potential (1-phase PWM)

Max power potential (2- or 1-phase PWM as configured at CSP2)

Power-Monitor Output: V

monitor scale factor:

CSNpm = CSN12 for MAX8771.

= K

x V(CSNpm, GNDS) x ΣV(CSP_, CSN_), where K

is the power

POUT

PWR

POUT

CSNpm = CSN2 for MAX8770/MAX8772.

POUT is zero in shutdown.

Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below

5

6

VRHOT

1.5V (30% of V ). VRHOT is high impedance in shutdown.

CC

Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V

and

CC

THRM

GND) to THRM. Select the components such that the voltage at THRM falls below 1.5V (30% of V ) at the

CC

desired high temperature.

Slew-Rate Adjustment Pin. Connect a resistor R

from TIME to GND to set the internal slew rate:

TIME

Slew rate = (12.5mV/µs) x (71.5kΩ_/ R

)

TIME

where R

is between 35.7kΩ and 178kΩ.

TIME

7

TIME

This slew rate applies to transitions into and out of the low-power pulse-skipping modes (and to the

transition from boot mode to VID mode. The slew rate for startup and shutdown is 1/8 this value. If the VID

DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are

clocked, up to a maximum slew rate equal to the one set by R

as defined above.

TIME

Switching-Frequency Setting Input. An external resistor between the input power source and TON sets the

switching period (T = 1/f ) per phase according to the following equation:

SW

8

9

TON

CCV

T

= C

(R

+ 6.5kΩ)

SW

TON TON

where C

= 16.26pF.

TON

TON is high impedance in shutdown.

Integrator Capacitor Connection. Connect a 470pF x (2/η

to set the integration time constant. The integrator is internally disabled when the part is in skip mode and

the output is above regulation.

) x 300kHz/f

TOTAL

capacitor from CCV to GND

SW

14 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Pin Description (continued)

NAME

FUNCTION

Current-Balance Compensation. Connect a 470pF capacitor between CCI and the positive side of the

feedback remote sense (or between CCI and GND). CCI is internally forced low in shutdown.

10

CCI

2.0V Reference Output. Bypass to GND with a 1µF maximum low-ESR (ceramic) capacitor. Can source

500µA for external loads. Loading REF degrades OUT accuracy, according to the REF load-regulation error.

11

12

REF

FB

Output of the DC-Voltage Positioning Transconductance Amplifier. Connect a resistor R between FB and

FB

the positive side of the feedback remote sense to set the DC steady-state droop based on the voltage-

positioning gain requirement:

R

= R

/ (R

x G

)

FB

DROOP

SENSE

m(FB)

where R

is the desired voltage-positioning slope and G

= 600µS (typ). R

is the value of

DROOP

m(FB)

SENSE

the current-sense resistors that are used to provide the (CSP_, CSN_) current-sense voltages. If lossless

sensing is used, R = R . In this case, consider making R a resistor network that includes an NTC

SENSE

L

FB

thermistor to minimize the temperature dependence of the voltage-positioning slope. DC droop can be

disabled by shorting FB to the positive remote-sense point. FB is high impedance in shutdown.

Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the load. GNDS

internally connects to a transconductance amplifier that fine tunes the output voltage— compensating for

voltage drops from the regulator ground to the load ground.

13

14

GNDS

CSP2

Positive Input of the Output Current Sense of Phase 2. This pin should be connected to the positive side of

the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is

utilized for current sensing. Tie this pin to V

for 1-phase operation.

CC

Combined Negative Current-Sense Input for Phases 1 and 2. The negative current-sense signals of the

two phases (taken from the negative sides of the output current-sensing resistors or the filtering capacitors

if the DC resistances of the output inductors are utilized for current sensing) are resistively averaged, and

the resulting signal is connected to this pin. Pay special attention to board layout to maximize current-

sensing accuracy; either place the sense elements (inductors for lossless sensing or sense resistors)

close to each other, or equalize the layout paths and PC board trace resistances between the sense

elements and the remote load. CSN12 is also used as the voltage input to the power monitor.

CSN12

(MAX8771)

15

CSN2

Negative Input of the Output Current Sense of Phase 2. This pin should be connected to the negative side

(MAX8770 of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is

/MAX8772) utilized for current sensing. CSN2 is also used as the voltage input to the power monitor.

Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of

the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is

utilized for current sensing.

CSP1

(MAX8771)

16

CSN1

Negative Input of the Output Current Sense of Phase 1. This pin should be connected to the negative side

(MAX8770/ of the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is

MAX8772) utilized for current sensing.

______________________________________________________________________________________ 15

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Pin Description (continued)

NAME

FUNCTION

Open-Drain, Phase-Good Output. Used to signal the system that one of the two phases either has a fault

condition or is not matched with the other. Detection is done by identifying the need for a large on-time

difference between phases in order to achieve or move towards current balance. PHASEGD is low in

shutdown.

PHASEGD is forced high impedance whenever the slew-rate controller is active (output-voltage

transitions).

PHASEGD

(MAX8771)

17

PHASEGD is forced high impedance while in 1-phase operation (DPRSLPVR = high or PSI = low).

CSP1

Positive Input of the Output Current Sense of Phase 1. This pin should be connected to the positive side of

(MAX8770 the output current-sensing resistor or the filtering capacitor if the DC resistance of the output inductor is

MAX8772) utilized for current sensing.

18

19

GND

Analog Ground. Connect to the exposed backside pad and low-current analog ground terminations.

Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.

V

CC

Boost Flying-Capacitor Connection for the DH2 high-side gate driver. An internal switch between V

BST2 charges the flying capacitor during the time the low-side FET is on.

and

DD

20

21

22

BST2

DH2

LX2

Phase-2, High-Side Gate-Driver Output. DH2 swings from LX2 to BST2. Low in shutdown.

Phase-2 Inductor Connection. LX2 is the internal lower supply rail for the DH2 high-side gate driver. Also

used as an input to the phase 2’s zero-crossing comparator.

Power Ground for Phase 2. Ground connection for the DL2 driver. Also used as an input to phase 2’s zero

crossing comparator.

23

24

PGND2

DL2

Phase-2, Low-Side Gate-Driver Output. DL2 swings from PGND2 to V . DL2 is forced high in shutdown.

DD

DL2 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit

condition that may be present. DL2 is forced low in skip mode (DPRSLPVR high) after an inductor current

zero crossing (PGND2 - LX2) is detected. DL2 is forced low in 1-phase mode (TWO - PH = low).

Supply Voltage Input for the DL1 and DL2 Drivers. V

is also the supply voltage used to internally

DD

recharge the BST1, BST2 flying capacitors during the off-times of the respective phases. Connect V

to

DD

25

V

DD

the 4.5V to 5.5V system supply voltage. Bypass V

ceramic capacitors.

to PGND1 and PGND2 with a 1µF each or greater

DD

Phase 1, Low-Side Gate-Driver Output. DL1 swings from PGND1 to V . DL1 is forced high in shutdown.

DD

DL1 is also forced high when an output overvoltage fault is detected, overriding any negative current-limit

condition that may be present. DL1 is forced low in skip mode (DPRSLPVR high) whenever an inductor

current zero crossing (PGND1 - LX1) is detected.

26

27

DL1

Power Ground for Phase 1. Ground connection for the DL1 driver. Also used as an input to the phase 1’s

zero crossing comparator.

PGND1

Phase 1 Inductor Connection. LX1 is the internal lower supply rail for the DH1 high-side gate driver. Also

used as an input to the phase-1’s zero-crossing comparator.

28

29

30

LX1

DH1

BST1

Phase 1 High-Side Gate-Driver Output. DH1 swings from LX1 to BST1. Low in shutdown.

Boost Flying Capacitor Connection for the DH1 High-Side Gate Driver. An internal switch between V

and BST1 charges the flying capacitor during the time the low-side FET is on.

DD

16 ______________________________________________________________________________________

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Pin Description (continued)

NAME

FUNCTION

Low-Voltage VID DAC Code Input. The D0–D6 inputs do not have internal pullups. These 1.0V logic inputs

are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the

logic-level voltages on D0–D6 (see Table 4).

31–37

D0–D6

Shutdown Control Input. This input cannot withstand the battery voltage. Connect to V for normal

CC

operation. Connect to ground to put the IC into its 1µA max shutdown state. During startup, the output

voltage is ramped up to the boot voltage slowly at a slew rate that is 1/8 the slew rate set by the TIME

resistor. During the transition from normal operation to shutdown, the output voltage is ramped down at the

same slow slew rate. Forcing SHDN to 11V~13V disables both OVP and UVP protection circuits, clears the

fault latch, disables transient phase overlap, and disables the BST_ charging switches. Do not connect

SHDN to > 13V.

38

SHDN

Logic Input to Indicate Power Usage. PSI and DPRSLPVR together determine the operating mode as

shown in the truth table below. The PWRGD upper threshold is blanked when the part is in skip mode. The

part is forced into full-phase PWM mode during startup, while in boot mode, during the transition

from boot mode to VID mode, and during shutdown.

39

DPRSLPVR

PSI

0

1

0

1

Mode

1

0

Very low current (1-phase skip)

Low current (approximately 3A) (1-phase skip)

Intermediate power potential (1-phase PWM)

Max power potential (full-phase PWM: number of phases by CSP2)

1.0V Logic-Input Signal. This signal from the system is usually the logical complement of the DPRSLPVR

signal. However, there is a special condition during C4 exit when both DPRSTP and DPRSLPVR could

temporarily be simultaneously high. If this happens, the slew rate reduces to 1/4 of the normal (R

-

TIME

based) slew rate for the duration of this condition. The slew rate returns to normal when this condition is

exited. Note that only DPRSLPVR and PSI (but not DPRSTP) determine the mode of operation (PWM vs.

skip) and the number of active phases:

40

EP

DPRSTP

DPRSLPVR

0

DPRSTP

Functionality

0

Normal slew rate, number of phases set by PSI and CSP2

(DPRSLPVR low

Normal slew rate, number of phases set by PSI and CSP2

(DPRSLPVR low

Normal slew rate, 1-phase skip mode

Slew rate reduced to 1/4 of normal,1-phase skip mode

→

DPRSTP is ignored)

0

1

→

DPRSTP is ignored)

1

0

1

EP

Exposed Backside Pad. Connect the exposed backside pad to AGND.

______________________________________________________________________________________ 17

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Table 1. Component Selection for Standard Applications

1.2875V/36A COMPONENTS

(FIGURE 1)

1.1500V/44A COMPONENTS

(FIGURE 1)

0.9000V/9A COMPONENTS

(FIGURE 12)

DESIGNATION

Input Voltage Range

7V to 24V

VID Output Voltage

(D6–D0)

1.2875V

(D6–D0 = 0010001)

1.1500V

(D6–D0 = 0011100)

0.9000V

(D6–D0 = 0110000)

Load Line

-2.1mV/A

36A

-2.1mV/A

44A

-5.1mV/A

9A

Maximum Load Current

0.36µH, 0.8mΩ

NEC/Tokin MPC1055LR36

0.33µH, 0.82mΩ

Panasonic ETQP5LR33XFC

0.56µH, 1.3mΩ

NEC/Tokin MPC1040LR56

Inductor (per Phase)

Switching Frequency

High-Side MOSFET

(N , per Phase)

H

300kHz (R

= 200kΩ)

300kHz (R

= 200kΩ)

300kHz (R

= 200kΩ)

TON

Siliconix (1) Si7892ADP

Siliconix (1) Si7336ADP

Low-Side MOSFET

(N , per Phase)

L

Siliconix (2) Si7336ADP

(4) 10µF, 25V

Siliconix (2) Si7336ADP

(4) 10µF, 25V

(2) 10µF, 25V

Taiyo Yuden TMK432BJ106KM

or

Total Input Capacitance

Taiyo Yuden TMK432BJ106KM Taiyo Yuden TMK432BJ106KM

(C

)

IN

or

TDK C4532X5R1E106M

Total Output Capacitance

(C

(4) 330µF, 2.5V, 6mΩ

Panasonic EEFSX0D0D331XR

(4) 330µF, 2.5V, 6mΩ

Panasonic EEFSX0D0D331XR

(2) 330µF, 2.5V, 6mΩ

Panasonic EEFSX0D0D331XR

)

OUT

Current-Sense Resistor

(R , per Phase)

1.0mΩ

2.0mΩ

Panasonic ERJM1WTJ1M0U

Panasonic ERJM1WTJ2M0U

CS

Table 2. Component Suppliers

MANUFACTURER

AVX

BI Technologies

WEBSITE

MANUFACTURER

Pulse

WEBSITE

www.pulseeng.com

www.renesas.com

www.secc.co.jp

www.avxcorp.com

www.bitechnologies.com

Renesas

Central Semiconductor www.centralsemi.com

Sanyo

Fairchild

www.fairchildsemi.com

Semiconductor

Siliconix (Vishay)

www.vishay.com

International Rectifier

Kemet

www.irf.com

Sumida

Taiyo Yuden

TDK

www.sumida.com

www.kemet.com

www.nec-tokin.com

www.panasonic.com

www.t-yuden.com

www.component.tdk.com

www.tokoam.com

NEC/Tokin

Panasonic

TOKO

18 ______________________________________________________________________________________

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

5V BIAS

SUPPLY

3.3V BIAS

SUPPLY

C1

2.2µF

R1

10Ω

R4

10kΩ

R3

1.9kΩ

R2

1.9kΩ

V

DD

CC

C2

R18

200kΩ

2.2µF

INPUT V

8V TO 24V

IN

RTON

BST1

PHASEGD

CLKEN

R22

0Ω

CLK_ENABLE#

IMVPOK

C

PWRGD

IN

C3

0.22µF

D0

D1

D2

D3

D4

D5

D6

DH1

LX1

DL1

RCS1

1mΩ

N

L1

H1

DAC INPUTS

(1V LOGIC)

N

L1

R12

100Ω

PGND1

GND

C11

2.2nF

PSI#

DPRSTP#

DPRLSPVR

VR_ON

PSI

CSP1

DPRSTP

DPRSLPVR

SHDN

*CSN1

C13

OPEN

R18

0Ω

R9

R10

3.40kΩ

100Ω

CPU V

CC

FB

C5

470pF

SENSE

CCV

C8

4700pF

R11**

10Ω

C7

470pF

R18

0Ω

MAX8770

MAX8771

MAX8772

OUTPUT

C6

0.1µF

REF

CCI

C

OUT

R5

71.5kΩ

R23

0Ω

TIME

R16**

10Ω

BST2

CPU GND

SENSE

DH2

LX2

RCS1

1mΩ

N

L1

H2

R6

13kΩ

V

THRM

CC

DL2

NTC4

100kΩ

N

L2

R12

100Ω

PGND2

1.2V BIAS

SUPPLY

C11

2.2nF

R7

56Ω

CSP2

*CSN2

VRHOT

POUT

R8

10kΩ

R17

100

GNDS

C10

0.1µF

C9

4700pF

*

CSN1 and CSN2 are bonded together on the

MAX8771 and called CSN12

** Optional -- Resistor allow remote sensing for system

verification when the CPU is not present

+ PHASEGD is only on the MAX8771

Figure 1. Standard 2-Phase IMVP-6 44A Application Circuit

______________________________________________________________________________________ 19

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

vides the PWM ramp signal. The control algorithm is sim-

MAX8770/MAX8771/MAX8772

ple: the high-side switch on-time is determined solely by

Detailed Description

a one-shot whose period is inversely proportional to

input voltage, and directly proportional to output voltage

Free-Running, Constant On-Time PWM

or the difference between the main and secondary

Controller with Input Feed-Forward

inductor currents (see the On-Time One-Shot section).

The Quick-PWM control architecture is a pseudo-fixed-

Another one-shot sets a minimum off-time. The on-time

frequency, constant-on-time, current-mode regulator

one-shot triggers when the error comparator goes low,

with voltage feed-forward (Figure 2). This architecture

the inductor current of the selected phase is below the

relies on the output filter capacitor’s ESR to act as the

valley current-limit threshold, and the minimum off-time

current-sense resistor, so the output ripple voltage pro-

one-shot times out. The controller maintains 180° out-of-

BST2

DH2

THRM

MAX8770

MAX8771

MAX8772

VRHOT

LX2

SECONDARY

PHASE DRIVERS

DL2

PGND2

0.3 x V

CC

BLANK

CSP2

CSN2

PHASEGD

CCI

TRIG

5ms

STARTUP

DELAY

CURRENT-

BALANCE-

FAULT

Q

22.5mV

CSP1

CSN1

ONE-SHOT

PHASE 2

ON-TIME

MINIMUM

OFF-TIME

CSN2

VCC

REF

TRIG

Q

22.5mV

CSP2

REF

(2.0V)

G

(CCI)

m

ONE-SHOT

GND

TIME

CSP1

CSN1

PHASE 1

ON-TIME

DPRSLPVR

FB

ONE-SHOT

TRIG

(CCI)

TON

R-TO-I

CONVERTER

Q

DPRSTP

BST1

DH1

LX1

D0–D6

SHDN

MAIN PHASE

DRIVERS

R

S

DAC

Q

S

R

Q

FAULT

Q

CSP1

CSN1

2.5mV

T

REF

V

DD

CCV

DL1

G

(CCV)

m

PGND1

TARGET

+ 200mV

TARGET

- 300mV

PWRGD

5ms

STARTUP

DELAY

FB

CLKEN

x2

CSP_

CSN_

60µs

STARTUP

DELAY

G

(FB)

m

BLANK

GNDS

PHASE CONTROL

CSP1 - CSN1

POUT

POWER

MONITOR

CSN1 - GNDS

CSP2 - CSN2

Figure 2. Functional Block Diagram

20 ______________________________________________________________________________________

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

phase operation by alternately triggering the main and

secondary phases after the error comparator drops

below the output voltage set point.

where I

is provided in the Electrical Characteristics

CC

Table, f

is the switching frequency, and Q

SW

G(LOW)

and Q

are the MOSFET data sheet’s total gate-

G(HIGH)

charge specification limits at V

= 5V.

GS

Dual 180° Out-of-Phase Operation

The two phases in the MAX8770/MAX8771/MAX8772

operate 180° out-of-phase to minimize input and output

filtering requirements, reduce electromagnetic interfer-

ence (EMI), and improve efficiency. This effectively low-

ers component count—reducing cost, board space,

and component power requirements— making the

MAX8770/MAX8771/MAX8772 ideal for high-power,

cost-sensitive applications.

V

and V

can be tied together if the input power

DD

IN

source is a fixed +4.5V to +5.5V supply. If the +5V

bias supply is powered up prior to the battery supply,

the enable signal (SHDN going from low to high) must

be delayed until the battery voltage is present to

ensure startup.

Switching Frequency (TON)

Connect a resistor (R

the switching period T

) between TON and V to set

IN

SW SW

TON

Typically, switching regulators provide power using

only 1 phase instead of dividing the power among sev-

eral phases. In these applications, the input capacitors

must support high instantaneous current requirements.

The high RMS ripple current can lower efficiency due to

I²R® power loss associated with the input capacitor’s

effective series resistance (ESR). Therefore, the system

typically requires several low-ESR input capacitors in

parallel to minimize input voltage ripple, to reduce ESR-

related power losses, and to meet the necessary RMS

ripple current rating.

= 1/f , per phase:

T

SW

= C

(R

+ 6.5kΩ)

TON TON

where C

= 16.26pF.

TON

A 96.75kΩ to 303.25kΩ corresponds to switching peri-

ods of 167ns (600kHz) to 500ns (200kHz), respectively.

High-frequency (600kHz) operation optimizes the appli-

cation for the smallest component size, trading off effi-

ciency due to higher switching losses. This may be

acceptable in ultra-portable devices where the load

currents are lower and the controller is powered from a

lower voltage supply. Low-frequency (200kHz) opera-

tion offers the best overall efficiency at the expense of

component size and board space.

With the MAX8770/MAX8771/MAX8772, the controller

shares the current between two phases that operate

180° out-of-phase, so the high-side MOSFETs never

turn on simultaneously during normal operation. The

instantaneous input current of either phase is effectively

halved, resulting in reduced input voltage ripple, ESR

power loss, and RMS ripple current (see the Input

Capacitor Selection section). Therefore, the same per-

formance may be achieved with fewer or less-expen-

sive input capacitors.

On-Time One-Shot

The core of each phase contains a fast, low-jitter,

adjustable one-shot that sets the high-side MOSFETs

on-time. The one-shot for the main phase varies the on-

time in response to the input and feedback voltages.

The main high-side switch on-time is inversely propor-

tional to the input voltage (V ), and proportional to the

feedback voltage (V ):

IN

FB

+5V Bias Supply (V

and V )

DD

CC

The Quick-PWM controller requires an external +5V

bias supply in addition to the battery. Typically, this

+5V bias supply is the notebook’s 95% efficient +5V

system supply. Keeping the bias supply external to the

IC improves efficiency and eliminates the cost associat-

ed with the +5V linear regulator that would otherwise be

needed to supply the PWM circuit and gate drivers. If

stand-alone capability is needed, the +5V bias supply

can be generated with an external linear regulator.

T

V

+ 0.075V

(

)

SW FB

t

=

ON(MAIN)

V

IN

where the switching period (T

= 1/f ) is set by the

SW

resistor at the TON pin, and 0.075V is an approximation

to accommodate the expected drop across the low-

side MOSFET switch.

The one-shot for the secondary phase varies the on-

time in response to the input voltage and the difference

between the main and secondary inductor currents.

Two identical transconductance amplifiers integrate the

difference between the master and slave current-sense

signals. The summed output is internally connected to

The +5V bias supply must provide V

(PWM con-

CC

troller) and V

(gate-drive power), so the maximum

DD

current drawn is:

I

= I

- f

(Q

+ Q

)

BIAS

CC SW

G(LOW)

G(HIGH)

2

I R is a registered trademark of instruments for Research and

Industry, Inc.

______________________________________________________________________________________ 21

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

CCI, allowing adjustment of the integration time con-

stant with a compensation network connected between

CCI and FB. The resulting compensation current and

voltage are determined by the following equations:

tor current reverses at light or negative load currents.

With reversed inductor current, the inductor’s EMF

causes LX to go high earlier than normal, extending the

on-time by a period equal to the DH-rising dead time.

For loads above the critical conduction point, where the

dead-time effect is no longer a factor, the actual switch-

ing frequency (per phase) is:

I

= G (V

M

- V

) - G (V

- V

)

CSN

CCI

CMP

CMN

M

CSP

V

CCI

= V + I

Z

FB

CCI CCI

where Z

is the impedance at the CCI output. The

CCI

V

+ V

DIS

secondary on-time one-shot uses this integrated signal

(V ) to set the secondary high-side MOSFETs on-

(

OUT

)

f

=

SW

CCI

t

V

+ V

− V

ON

(

IN

DIS

CHG

)

time. When the main and secondary current-sense sig-

nals (V = V - V and V = V -V

)

CSM

CM

CMP

CMN

CS

CSP

where V

is the sum of the parasitic voltage drops in

DIS

become unbalanced, the transconductance amplifiers

adjust the secondary on-time, which increases or

decreases the secondary inductor current until the cur-

rent-sense signals are properly balanced:

the inductor discharge path, including synchronous

rectifier, inductor, and PC board resistances; V is

CHG

the sum of the parasitic voltage drops in the inductor

charge path, including high-side switch, inductor, and

PC board resistances; and t

mined above.

is the on-time as deter-

ON

⎛

⎞

V

+ 0.075V

CCI

t

= T

SW

ON(SEC)

⎜

⎟

V

⎝

⎠

IN

Current Sense

⎛

⎞

⎛

⎞

V

+ 0.075V

I

Z

FB

CCI CCI

The output current of each phase is sensed. Low-offset

amplifiers are used for current balance, voltage-posi-

tioning gain, and current limit. Sensing the current at

the output of each phase offers advantages, including

less noise sensitivity, more accurate current sharing

between phases, and the flexibility of using either a

current-sense resistor or the DC resistance of the out-

put inductor.

= T

+ T

SW

⎜

⎟

⎜

⎟

V

⎝

⎠

⎝

⎠

IN

= (Main On-Time)

+ (Secondary Current Balance Correction)

This algorithm results in a nearly constant switching fre-

quency and balanced inductor currents, despite the lack

of a fixed-frequency clock generator. The benefits of a

constant switching frequency are twofold: first, the fre-

quency can be selected to avoid noise-sensitive regions

such as the 455kHz IF band; second, the inductor ripple-

current operating point remains relatively constant,

resulting in easy design methodology and predictable

output voltage ripple. The on-time one-shots have good

accuracy at the operating points specified in the

Electrical Characteristics table. On-times at operating

points far removed from the conditions specified in the

Electrical Characteristics table can vary over a wider

range. For example, the 600kHz setting typically runs

about 5% slower, with inputs much greater than +12V

due to the very short on-times required.

Using the DC resistance (R

) of the output inductor

DCR

allows higher efficiency. In this configuration, the initial

tolerance and temperature coefficient of the inductor’s

DCR must be accounted for in the output-voltage

droop-error budget and power monitor. This current-

sense method uses an RC filtering network to extract

the current information from the output inductor (see

Figure 3). The resistive divider used should provide a

current-sense resistance (R ) low enough to meet the

CS

current-limit requirements, and the time constant of the

RC network should match the inductor’s time constant

(L/R ):

CS

R2

R1+R2

⎛

⎞

On-times translate only roughly to switching frequen-

cies. The on-times guaranteed in the Electrical

Characteristics table are influenced by switching

delays in the external high-side MOSFET. Resistive

losses, including the inductor, both MOSFETs, output

capacitor ESR, and PC board copper losses in the out-

put and ground tend to raise the switching frequency at

higher output currents. Also, the dead-time effect

increases the effective on-time, reducing the switching

frequency. It occurs only during forced-PWM operation

and dynamic output-voltage transitions when the induc-

R

=

R

and

⎜

⎝

⎟

⎠

CS

DCR

L

1

⎡

⎤

+

CS

⎢

⎣

⎥

⎦

C

R1 R2

EQ

where R

is the required current-sense resistance,

is the inductor’s series DC resistance. Use

CS

and R

DCR

the worst-case inductance and R

values provided

DCR

by the inductor manufacturer, adding some margin for

the inductance drop over temperature and load. To

22 ______________________________________________________________________________________

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

minimize the current-sense error due to the current-

sense inputs’ bias current (I _ and I _), choose

but results in a significant peak current-sense voltage

error that results in unwanted offsets in the regulation

voltage and results in early current-limit detection.

Similar to the inductor DCR sensing method above, the

RC filter’s time constant should match the L/R time con-

stant formed by the current-sense resistor’s parasitic

inductance:

CSP

CSN

R1||R2 to be less than 2kΩ and use the above equation

to determine the sense capacitance (C ). Choose

EQ

capacitors with 5% tolerance and resistors with 1% tol-

erance specifications. Temperature compensation is

recommended for this current-sense method. See the

Voltage Positioning and the Loop Compensation sec-

tion for detailed information.

L

ESL

= C R1

EQ

When using a current-sense resistor for accurate out-

put-voltage positioning, the circuit requires a differential

RC filter to eliminate the AC voltage step cause by the

R

SENSE

where L

is the equivalent series inductance of the

ESL

equivalent series inductance (L

) of the current-

current-sense resistor, R

is current-sense resis-

are the time-constant

ESL

SENSE

and R

EQ EQ

sense resistor (see Figure 3). The ESL-induced voltage

step does not affect the average current-sense voltage,

tance value, and C

matching components.

INPUT (V

)

IN

C

IN

SENSE RESISTOR

N

H

DH_

L

R

SENSE

L

ESL

R1

LX_

L

C

DL_

SENSE

D

OUT

L

C

R1 =

N

EQ

L

R

SENSE

PGND

C

EQ

CSP_

CSN_

A) OUTPUT SERIES RESISTOR SENSING

INPUT (V

)

IN

C

IN

INDUCTOR

N

H

DH_

LX_

DL_

DCR

L

R2

R

=

R

DCR

CS

( _{R1 + R2})

C

OUT

D

L

N

R1

R2

L

1

+

R

DCR

PGND

C

R1 R2

[ ]

EQ

C

EQ

CSP_

CSN_

FOR THERMAL COMPENSATION:

R2 SHOULD CONSIST OF AN NTC RESISTOR IN

SERIES WITH A STANDARD THIN-FILM RESISTOR

B) LOSSLESS INDUCTOR SENSING

Figure 3. Current-Sense Methods

______________________________________________________________________________________ 23

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Current Balance

Without active current-balance circuitry, the current

matching between phases depends on the MOSFETs’

Since only the valley current is actively limited, the actu-

al peak current is greater than the current-limit threshold

by an amount equal to the inductor ripple current.

Therefore, the exact current-limit characteristic and

maximum load capability are a function of the current-

sense resistance, inductor value, and battery voltage.

When combined with the UVP circuit, this current-limit

method is effective in almost every circumstance.

on-resistance (R

), thermal ballasting, on/off-time

DS(ON)

matching, and inductance matching. For example, vari-

ation in the low-side MOSFET on-resistance (ignoring

thermal effects) results in a current mismatch that is

proportional to the on-resistance difference:

The positive current-limit threshold is fixed internally at

22.5mV. There is also a negative current limit that pre-

⎡

⎤

⎥

⎛

⎞

R

MAIN

I

−I

=I

1−

⎢

MAIN SEC MAIN

⎜

⎟

⎝

⎠

vents excessive reverse inductor currents when V

OUT

⎢

⎣

SEC

⎥

⎦

is sinking current. The negative current-limit threshold

is set at -30mV. When a phase drops below the nega-

tive current limit, the controller immediately activates an

on-time pulse—DL turns off, and DH turns on—allowing

the inductor current to remain above the negative cur-

rent threshold.

However, mismatches between on-times, off-times, and

inductor values increase the worst-case current imbal-

ance, making it impossible to passively guarantee

accurate current balancing.

The MAX8770/MAX8771/MAX8772 integrate the differ-

ence between the current-sense voltages and adjust the

on-time of the secondary phase to maintain current bal-

ance. The current balance now relies on the accuracy of

the current-sense resistors instead of the inaccurate, ther-

mally sensitive on-resistance of the low-side MOSFETs.

With active current balancing, the current mismatch is

determined by the current-sense resistor values and the

offset voltage of the transconductance amplifiers:

Carefully observe the PC board layout guidelines to

ensure that noise and DC errors do not corrupt the cur-

rent-sense signals seen by the current-sense inputs

(CSP_, CSN_). For the MAX8771, where the negative

current-sense returns are to a common pin, it is recom-

mended that the current-sense elements (sense resis-

tor or inductor DCR) be placed close to each other to

minimize any voltage differences that might arise due

to trace impedance between the two common nodes.

V

OS(IBAL)

I

=I

−I

=

OS(IBAL) LMAIN LSEC

Feedback Adjustment Amplifiers

R

SENSE

Voltage-Positioning Amplifier

(Steady-State Droop)

where R

= R

and V

is the cur-

OS(IBAL)

SENSE

CM

CS

The MAX8770/MAX8771/MAX8772 include a transcon-

ductance amplifier for adding gain to the voltage-posi-

tioning sense path. The amplifier’s input is generated

by summing the current-sense inputs, which differen-

tially sense the voltage across either current-sense

resistors or the inductor’s DCR. The amplifier’s output

connects directly to the regulator’s voltage-positioned

feedback input (FB), so the resistance between FB and

the output-voltage sense point determines the voltage-

positioning gain:

rent-balance offset specification in the Electrical

Characteristics table .

The worst-case current mismatch occurs immediately

after a load transient due to inductor value mismatches

resulting in different di/dt for the two phases. The time it

takes the current-balance loop to correct the transient

imbalance depends on the mismatch between the

inductor values and switching frequency.

Current Limit

The current-limit circuit employs a unique “valley” cur-

rent-sensing algorithm that uses current-sense resistors

between the current-sense inputs (CSP_ to CSN12 for

MAX8771, CSP_ to CSN_ for MAX8770/MAX8772) as

the current-sensing elements. If the current-sense sig-

nal of the selected phase is above the current-limit

threshold, the PWM controller does not initiate a new

cycle until the inductor current of the selected phase

drops below the valley current-limit threshold. When

either phase trips the current limit, both phases are

effectively current limited since the interleaved con-

troller does not initiate a cycle with either phase.

V

OUT

= V

- R I

FB FB

TARGET

where the target voltage (V

) is defined in the

TARGET

Nominal Output Voltage Selection section, and the FB

amplifier’s output current (I ) is determined by the

FB

sum of the current-sense voltages:

η

PH

∑

I

= G

V

CSX

FB

m(FB)

X=1

where V

= V

- V

CSP

is the differential current-

CS

CSN

sense voltage, and G

is typically 600µS as defined

m(FB)

in the Electrical Characteristics table.

24 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Differential Remote Sense

The MAX8770/MAX8771/MAX8772 include differential,

remote-sense inputs to eliminate the effects of voltage

drops along the PC board traces and through the

processor’s power pins. The feedback-sense node

heavy load transients are detected, effectively reducing

the response time. After either high-side MOSFET turns

off, if the output voltage does not exceed the regulation

voltage when the minimum off-time expires, the controller

simultaneously turns on both high-side MOSFETs during

the next on-time cycle. This maximizes the total inductor

current slew rate. The phases remain overlapped until

the output voltage exceeds the regulation voltage after

the minimum off-time expires.

connects to the voltage-positioning resistor (R ). The

FB

ground-sense (GNDS) input connects to an amplifier

that adds an offset directly to the target voltage, effec-

tively adjusting the output voltage to counteract the

voltage drop in the ground path. Connect the voltage-

positioning resistor (R ), and ground sense (GNDS)

FB

input directly to the processor’s remote-sense outputs

as shown in Figure 1.

After the phase-overlap mode ends, the controller

automatically begins with the opposite phase. For

example, if the secondary phase provided the last on-

time pulse before overlap operation began, the con-

troller starts switching with the main phase when

overlap operation ends.

Integrator Amplifier

An integrator amplifier forces the DC average of the FB

voltage to equal the target voltage. This transconduc-

tance amplifier integrates the feedback voltage and pro-

vides a fine adjustment to the regulation voltage (Figure

2), allowing accurate DC output-voltage regulation

regardless of the output ripple voltage. The integrator

amplifier has the ability to shift the output voltage by

60mV (typ), including DC offset and AC ripple. The inte-

gration time constant can be set easily with an external

compensation capacitor at the CCV pin. Use a 470pF x

Nominal Output-Voltage Selection

The nominal no-load output voltage (V

) is

TARGET

defined by the selected voltage reference (VID DAC)

plus the remote ground-sense adjustment (V

defined in the following equation:

), as

GNDS

V

= V = V

+ V

TARGET

FB

DAC GNDS

where V

is the selected VID voltage. On startup, the

DAC

(2/η

) x 300kHz/f

or greater ceramic capacitor.

TOTAL

SW

MAX8770/MAX8771/MAX8772 slew the target voltage

from ground to the preset boot voltage.

The MAX8770/MAX8771/MAX8772 disable the integra-

tor by connecting the amplifier inputs together at the

beginning of all VID transitions done in pulse-skipping

mode (DPRSLPVR = high). The integrator remains dis-

abled until 20µs after the transition is completed (the

internal target settles) and the output is in regulation

(edge detected on the error comparator).

DAC Inputs (D0–D6)

The digital-to-analog converter (DAC) programs the out-

put voltage using the D0–D6 inputs. D0–D6 are low-volt-

age (1.0V) logic inputs, designed to interface directly

with the CPU. Do not leave D0–D6 unconnected.

Changing D0–D6 initiates a transition to a new output-

voltage level. Change D0–D6 together, avoiding greater

than 20ns skew between bits. Otherwise, incorrect DAC

readings may cause a partial transition to the wrong volt-

age level followed by the intended transition to the cor-

rect voltage level, lengthening the overall transition time.

The available DAC codes and resulting output voltages

are compatible with the IMVP-6 (Table 4) specifications.

Transient-Overlap Operation

When a transient occurs, the response time of the con-

troller depends on how quickly it can slew the inductor

current. Multiphase controllers that remain 180° out-of-

phase when a transient occurs actually respond slower

than an equivalent single-phase controller. In order to

provide fast transient response, the MAX8770/

MAX8771/MAX8772 support a phase-overlap mode that

allows the dual regulators to operate in-phase when

______________________________________________________________________________________ 25

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Table 3. Operating Mode Truth Table

INPUTS

PHASE

OPERATION*

OPERATING MODE

SHDN

DPRSTP DPRSLPVR

PSI

Low-Power Shutdown Mode. DL1 and DL2 forced high,

and the controller is disabled. The supply current drops to

1µA (max).

Low

X

DISABLED

Startup/Boot. When SHDN is pulled high, the

MAX8770/MAX8771/MAX8772 begin the startup sequence.

Once the REF is above 1.84V, the controller enables the PWM

controller and ramps the output voltage up to the boot

voltage. See Figure 9.

Multiphase

forced PWM

Rising

X

1/8R

slew

TIME

rate

Multiphase

Full Power. The no-load output voltage is determined by the

selected VID DAC code (D0–D6, Table 4).

forced PWM;

High

X

Low

High

Low

normal R

TIME

slew rate

1-phase forced Intermediate Power. The no-load output voltage is determined

PWM;

normal R

by the selected VID DAC code (D0–D6, Table 4). When PSI is

pulled low, the MAX8770/MAX8771/MAX8772 immediately

disable phase 2—DH2, and DL2 pulled low.

TIME

slew rate

Deeper Sleep Mode. The no-load output voltage is

determined by the selected VID DAC code (D0–D6, Table 4).

When DPRSLPVR is pulled high, the MAX8770/MAX8771/

MAX8772 immediately enter 1-phase pulse-skipping

operation allowing automatic PWM/PFM switchover under

light loads. The PWRGD and CLKEN upper thresholds are

blanked. DH2 and DL2 are pulled low.

1-phase pulse

skipping,

High

Low

High

X

normal R

TIME

slew rate

Deeper Sleep Slow-Exit Mode. The no-load output voltage is

determined by the selected VID DAC code (D0–D6, Table 4).

When DPRSTP is pulled high while DPRSLPVR is already

high, the MAX8770/MAX8771/MAX8772 remain in 1-phase

pulse-skipping operation, allowing automatic PWM/PFM

switchover under light loads. The PWRGD and CLKEN upper

thresholds are blanked. DH2 and DL2 are pulled low.

1-phase pulse

skipping,

High

1/4 R

slew

TIME

rate

Shutdown. When SHDN is pulled low, the

Multiphase

forced-PWM,

MAX8770/MAX8771/MAX8772 immediately pull PWRGD and

PHASEGD low, CLKEN becomes high impedance, all

Falling

High

X

1/8 R

rate

slew enabled phases are activated, and the output voltage is

ramped down to ground. Once the output reaches zero, the

controller enters the low-power shutdown state. See Figure 9.

TIME

Fault Mode. The fault latch has been set by the MAX8770/

MAX8771/MAX8772 UVP or thermal shutdown protection, or

DISABLED

by the MAX8771 OVP protection. The controller remains in

FAULT mode until V power is cycled or SHDN toggled.

CC

*Multiphase operation = All enabled phases active.

26 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Table 4. IMVP-6 Output Voltage VID DAC Codes

OUTPUT

VOLTAGE (V)

OUTPUT

VOLTAGE (V)

D6

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

______________________________________________________________________________________ 27

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Table 4. IMVP-6 Output Voltage VID DAC Codes (continued)

OUTPUT

VOLTAGE (V)

OUTPUT

VOLTAGE (V)

D6

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.3000

0.2875

0.2750

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

0.0625

0.0500

0.0375

0.0250

0.0125

0

28 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Suspend Mode

When the processor enters low-power deeper sleep

mode, the IMVP-6 CPU sets the VID DAC code to a

lower output voltage and drives DPRSLPVR high. The

MAX8770/MAX8771/MAX8772 respond by slewing the

internal target voltage to the new DAC code, switching

to single-phase operation, and letting the output volt-

age gradually drift down to the deeper sleep voltage.

During the transition, the MAX8770/MAX8771/MAX8772

blank both the upper and lower PWRGD and CLKEN

thresholds until 20µs after the internal target reaches

the deeper sleep voltage. Once the 20µs timer expires,

the MAX8770/MAX8771/MAX8772 reenable the lower

PWRGD and CLKEN threshold, but keep the upper

threshold blanked. PHASEGD remains blanked high

impedance while DPRSLPVR is high.

transitions, the transition time (t

) is given by:

TRAN

V

− V

OLD

NEW

t

=

TRAN

dV

/dt

(

)

TARGET

where dV

/dt = 12.5mV/µs × 71.5kΩ / R

is

TIME

TARGET

the slew rate, V

is the original output voltage, and

OLD

V

is the new target voltage. See TIME Slew Rate

NEW

Accuracy in Electrical Characteristics for slew-rate lim-

its. For soft-start and shutdown, the controller automati-

cally reduces the slew rate to 1/8.

The output voltage tracks the slewed target voltage,

making the transitions relatively smooth. The average

inductor current per phase required to make an output

voltage transition is:

C

Output-Voltage Transition Timing

The MAX8770/MAX8771/MAX8772 perform mode tran-

sitions in a controlled manner, automatically minimizing

input surge currents. This feature allows the circuit

designer to achieve nearly ideal transitions, guarantee-

ing just-in-time arrival at the new output-voltage level

with the lowest possible peak currents for a given out-

put capacitance.

OUT

I ≅

× dV

(

/dt

)

L

TARGET

η

TOTAL

where dV

/dt is the required slew rate, C

the total output capacitance, and η

is

OUT

TARGET

is the number

TOTAL

of active phases.

Deeper Sleep Transitions

When DPRSLPVR goes high, the MAX8770/MAX8771/

MAX8772 immediately disable phase 2 (DH2 and DL2

forced low), blank PHASEGD high impedance

(MAX8771 only), and enter pulse-skipping operation

(see Figures 4 and 5). If the VIDs are set to a lower volt-

age setting, the output drops at a rate determined by

the load and the output capacitance. The internal target

still ramps as before, and CLKEN and PWRGD upper

and lower thresholds remain blanked until 20µs after

the internal target reaches the programmed VID code.

Once this time expires, PWRGD monitors only the lower

threshold:

At the beginning of an output-voltage transition, the

MAX8770/MAX8771/MAX8772 blank PHASEGD,

CLKEN, and PWRGD upper and lower thresholds, pre-

venting the open-drain outputs from changing states

during the transition. The controller enables the lower

CLKEN and PWRGD threshold approximately 20µs

after the slew-rate controller reaches the target output

voltage, but the upper CLKEN and PWRGD threshold is

enabled only if the controller remains in forced-PWM

operation. If the controller enters pulse-skipping opera-

tion, the upper CLKEN and PWRGD threshold remains

blanked. The slew rate (set by resistor R ) must be

TIME

set fast enough to ensure that the transition may be

completed within the maximum allotted time.

• Fast C4E Deeper Sleep Exit: When exiting deeper

sleep (DPRSLPVR pulled low) while the output volt-

age still exceeds the deeper sleep voltage, the

MAX8770/MAX8771/MAX8772 quickly slew (50mV/µs

The MAX8770/MAX8771/MAX8772 automatically con-

trol the current to the minimum level required to com-

plete the transition in the calculated time. The slew-rate

controller uses an internal capacitor and current source

min regardless of R

setting) the internal target

TIME

voltage to the DAC code provided by the processor

as long as the output voltage is above the new tar-

get. The controller remains in skip mode until the out-

put voltage equals the internal target. Once the

internal target reaches the output voltage, phase 2 is

enabled. The controller blanks PWRGD, PHASEGD,

and CLKEN (forced high impedance) until 20µs after

the transition is completed. See Figure 4.

programmed by R

to transition the output voltage.

TIME

The total transition time depends on R

, the voltage

TIME

difference, and the accuracy of the slew-rate controller

(C accuracy). The slew rate is not dependent on

SLEW

the total output capacitance, as long as the surge cur-

rent is less than the current limit. For all dynamic VID

______________________________________________________________________________________ 29

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

• Standard C4 Deeper Sleep Exit: When exiting

deeper sleep (DPRSLPVR pulled low) while the out-

put voltage is regulating to the deeper sleep voltage,

the MAX8770/MAX8771/MAX8772 immediately acti-

vate all enabled phases and ramp the output voltage

to the LFM DAC code provided by the processor at

• Slow C4 Deeper Sleep Exit: When exiting deeper

sleep (DPRSLPVR high, DPRSTP pulled high) while

the output voltage is regulating to the deeper sleep

voltage, the MAX8770/MAX8771/MAX8772 remain in

1-phase skip mode and ramp the output voltage to the

LFM DAC code provided by the processor at 1/4 the

the slew rate set by R

. The controller blanks

slew-rate set by R

. The controller blanks PWRGD,

TIME

PWRGD, PHASEGD, and CLKEN (forced high

impedance) until 20µs after the transition is complet-

ed. See Figure 5.

PHASEGD, and CLKEN (forced high impedance) until

20µs after the transition is completed. See Figure 6.

ACTUAL V

OUT

CPU CORE

VOLTAGE

INTERNAL TARGET

DEEPER SLEEP VID

VID (D0–D6)

DPRSLPVR

PSI

DO NOT CARE (DPRSLPVR DOMINATES STATE)

INTERNAL

PWM CONTROL

FORCED PWM

1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 = FORCED LOW)

NO PULSES: V

> V

TARGET

DH1

PWM2

DH2

OUT

BLANK HIGH-Z

BLANK LO

BLANK HIGH THRESHOLD ONLY

BLANK HIGH-Z

BLANK LO

PWRGD

CLKEN

PHASEGD

OVP

SET TO 1.75V MIN

TRACKS INTERNAL TARGET

t

BLANK

t

BLANK

20µs TYP

Figure 4. C4E (C4 Early Exit) Transition

30 ______________________________________________________________________________________

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ACTIVE VID

CPU CORE

VOLTAGE

ACTUAL V

OUT

LFM VID

INTERNAL

TARGET

DPRSLP VID

VID (D0–D6)

DPRSLPVR

LFM VID

DEEPER SLEEP VID

DPRSTP

PSI

DO NOT CARE (DPRSLPVR DOMINATES STATE)

1-PHASE SKIP (DH1 ACTIVE, DL2 FORCED LOW)

INTERNAL

PWM CONTROL

1-PHASE FORCED PWM

NO PULSES: V

> V

TARGET

DH1

DH2

OUT

PWRGD

CLKEN

BLANK HIGH-Z

BLANK HIGH THRESHOLD ONLY

BLANK HIGH-Z

BLANK LOW

BLANK HIGH THRESHOLD ONLY

BLANK LOW

BLANK HIGH-Z (1-PHASE OPERATION)

PHASEGD

OVP

SET TO 1.75V MIN

TRACKS INTERNAL TARGET

t

BLANK

20µs TYP

Figure 5. Standard C4 Transition

______________________________________________________________________________________ 31

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ACTIVE VID

CPU CORE

VOLTAGE

ACTUAL V

OUT

LFM VID

INTERNAL

TARGET

DPRSLP VID

VID (D0–D6)

DPRSLPVR

LFM VID

DEEPER SLEEP VID

DPRSTP

PSI

DO NOT CARE (DPRSLPVR DOMINATES STATE)

1-PHASE SKIP (DH1 ACTIVE, DL2 FORCED LOW)

INTERNAL

PWM CONTROL

1-PHASE FORCED PWM

NO PULSES: V

> V

TARGET

DH1

DH2

OUT

PWRGD

CLKEN

BLANK HIGH-Z

BLANK HIGH THRESHOLD ONLY

BLANK HIGH-Z

BLANK LOW

BLANK HIGH THRESHOLD ONLY

BLANK LOW

BLANK HIGH-Z (1-PHASE OPERATION)

PHASEGD

OVP

SET TO 1.75V MIN

TRACKS INTERNAL TARGET

t

BLANK

20µs TYP

Figure 6. Slow C4 Transition

32 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

phase 2. PHASEGD is blanked high impedance for 32

switching cycles on DH2, allowing sufficient time/cycles

for phase 1 and 2 to achieve current balance. In a typical

IMVP-6 application, the VID is reduced by 1 LSB

(12.5mV) when PSI is pulled low, and increased by 1

LSB when PSI is pulled high.

PSI Transitions

When PSI is pulled low, the MAX8770/MAX8771/

MAX8772 immediately disable phase 2 (DH2 and DL2

forced low), blank PHASEGD high impedance, and enter

single-phase PWM operation (see Figure 7). When PSI is

pulled high, the MAX8770/MAX8771/MAX8772 enable

ACTIVE VID

CPU CORE

VOLTAGE

SLOW SLEW RATE

ACTUAL V

OUT

LFM VID

DPRSLP VID

INTERNAL

TARGET

VID (D0–D6)

DPRSLPVR

LFM VID

DEEPER SLEEP VID

SLOW SLEW RATE

DPRSTP

PSI

DO NOT CARE (DPRSLPVR DOMINATES STATE)

INTERNAL

PWM CONTROL

1-PHASE FORCED PWM

1-PHASE SKIP (DH1 ACTIVE, DH2 = DL2 - FORCED LOW)

NO PULSES: V

> V

TARGET

DH1

DH2

OUT

PWRGD

CLKEN

BLANK HIGH THRESHOLD ONLY

BLANK HIGH-Z

BLANK HIGH THRESHOLD ONLY

BLANK LOW

BLANK HIGH-Z (1-PHASE OPERATION)

PHASEGD

OVP

SET TO 1.75V MIN

TRACKS INTERNAL TARGET

t

BLANK

20µs TYP

Figure 7. PSI# Transition

______________________________________________________________________________________ 33

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PWM Controller for IMVP-6+ CPU Core Power Supplies

Automatic Pulse-Skipping Switchover

In skip mode (DPRSLPVR = high), an inherent automat-

ic switchover to PFM takes place at light loads (Figure

8). This switchover is affected by a comparator that

truncates the low-side switch on-time at the inductor

current’s zero crossing. The zero-crossing comparator

senses the inductor current across the low-side

Forced-PWM Operation (Normal Mode)

During soft-start, soft-shutdown, and normal opera-

tion—when the CPU is actively running (DPRSLPVR =

low, Table 5)—the MAX8770/MAX8771/MAX8772 oper-

ate with the low-noise, forced-PWM control scheme.

Forced-PWM operation disables the zero-crossing

comparators of all active phases, forcing the low-side

gate-drive waveforms to be constantly the complement

of the high-side gate-drive waveforms. This keeps the

switching frequency constant and allows the inductor

current to reverse under light loads, providing fast,

accurate negative-output-voltage transitions by quickly

discharging the output capacitors.

MOSFETs. Once V drops below the zero crossing

LX

comparator threshold (see the Electrical Characteristics

table), the comparator forces DL low (Figure 2). This

mechanism causes the threshold between pulse-skip-

ping PFM and nonskipping PWM operation to coincide

with the boundary between continuous and discontinu-

ous inductor-current operation. The PFM/PWM

crossover occurs when the load current of each phase

is equal to 1/2 the peak-to-peak ripple current, which is

a function of the inductor value (Figure 8). For a bat-

tery-input 7V to 20V range, this threshold is relatively

constant, with only a minor dependence on the input

voltage due to the typically low duty cycles. The total

load current at the PFM/PWM crossover threshold

Forced-PWM operation comes at a cost; the no-load

+5V bias supply current remains between 10mA to

50mA per phase, depending on the external MOSFETs

and switching frequency. To maintain high efficiency

under light-load conditions, the processor may switch

the controller to a low-power, pulse-skipping control

scheme after entering suspend mode.

PSI determines how many phases are active when

operating in forced-PWM mode (DPRSLPVR = low).

When PSI is pulled low, the main phase remains active

but the secondary phase is disabled (DH2 and DL2

forced low).

(I ) is approximately:

LOAD(SKIP)

⎛

⎞

T

V

V − V

IN OUT

⎛

⎞

SW OUT

L

I

= η

⎜

⎝

⎟

⎠

LOAD(SKIP)

TOTAL

⎜

⎟

V

⎝

⎠

IN

where η

is the number of active phases.

Light-Load Pulse-Skipping Operation

(Deeper Sleep)

TOTAL

The switching waveforms may appear noisy and asyn-

chronous when light loading activates pulse-skipping

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs between

PFM noise and light-load efficiency are made by vary-

When DPRSLPVR is pulled high, the MAX8770/

MAX8771/MAX8772 operate with a single-phase,

pulse-skipping mode. The pulse-skipping mode

enables the driver’s zero-crossing comparator, so the

controller pulls DL1 low when its current-sense inputs

detect “zero” inductor current. This keeps the inductor

from discharging the output capacitors and forces the

controller to skip pulses under light-load conditions to

avoid overcharging the output.

When pulse skipping, the controller blanks the upper

PWRGD and CLKEN thresholds, and also blanks

PHASEGD high impedance for the MAX8771. Upon

entering pulse-skipping operation, the controller tem-

porarily sets the OVP threshold to 1.80V, preventing

false OVP faults when the transition to pulse-skipping

operation coincides with a downward VID code

change. Once the error amplifier detects that the output

voltage is in regulation, the OVP threshold tracks the

selected VID DAC code. The MAX8770/MAX8771/

MAX8772 automatically use forced-PWM operation dur-

ing soft-start and soft-shutdown, regardless of the

DPRSLPVR and PSI configuration.

V_BATT– V_OUT

L

∆i

∆t

I

PEAK

I

= I

/2

LOAD PEAK

0

TIME

ON-TIME

Figure 8. Pulse-Skipping/Discontinuous Crossover Point

34 ______________________________________________________________________________________

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ing the inductor value. Generally, low inductor values

produce a broader efficiency vs. load curve, while

higher values result in higher full-load efficiency

(assuming that the coil resistance remains fixed) and

less output-voltage ripple. Penalties for using higher

inductor values include larger physical size and

degraded load-transient response, especially at low

input-voltage levels.

Power-Up Sequence (POR, UVLO)

The MAX8770/MAX8771/MAX8772 are enabled when

SHDN is driven high (Figure 9). The reference powers

up first. Once the reference exceeds its UVLO thresh-

old, the internal analog blocks are turned on and

masked by a 150µs one-shot delay. The PWM con-

troller then begins switching.

Power-on reset (POR) occurs when V

rises above

CC

approximately 2V, resetting the fault latch and prepar-

ing the controller for operation. The V

UVLO circuitry

CC

V

CC

SHDN

INVALID

CODE

INVALID

CODE

VID (D0–D6)

SOFT-START =

1/8th SLEW RATE SET

BY R

SOFT-SHUTDOWN =

1/8th SLEW RATE SET

BY R

TIME

V

CORE

INTERNAL

PWM CONTROL

FORCED PWM

PHASEGD

CLKEN

PWRGD

t

BLANK

5ms TYP

BLANK

t

BLANK

60µs TYP

20µs TYP

t

BLANK

20µs TYP

Figure 9. Power-Up and Shutdown Sequence Timing Diagram

______________________________________________________________________________________ 35

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

inhibits switching until V

troller powers up the reference once the system

enables the controller, V above 4.25V and SHDN dri-

ven high. With the reference in regulation, the controller

ramps the output voltage to the 1.20V boot voltage at

1/8 the slew rate set by R

rises above 4.25V. The con-

eliminates the need for the Schottky diode normally

connected between the output and ground to clamp

the negative output-voltage excursion. After the con-

troller reaches the zero target, the MAX8770/

MAX8771/MAX8772 shut down completely—the drivers

are disabled (DL1 and DL2 driven high)—the reference

turns off, and the supply currents drop to about 1µA

(max) 20µs.

CC

:

TIME

8V

BOOT

t

=

TRAN(START)

dV

(

/dt

When a fault condition—output UVLO or thermal shut-

down—activates the shutdown sequence, the protection

circuitry sets the fault latch to prevent the controller from

restarting. To clear the fault latch and reactivate the con-

)

TARGET

where dV /dt = 12.5mV/µs x 71.5kΩ / R

TARGET

is the

TIME

slew rate. The soft-start circuitry does not use a variable

current limit, so full output current is available immediate-

ly. CLKEN is pulled low approximately 60µs after the

MAX8770/MAX8771/MAX8772 reach the boot voltage. At

the same time, the MAX8770/MAX8771/MAX8772 slew

the output to the voltage set at the VID inputs at the pro-

grammed slew rate. PWRGD and PHASEGD become

high impedance approximately 5ms after CLKEN is

pulled low. The MAX8770/MAX8771/MAX8772 automati-

cally use forced-PWM operation during soft-start and

soft-shutdown, regardless of the DPRSLPVR and PSI

configuration.

troller, toggle SHDN or cycle V power below 0.5V.

CC

Power Monitor (POUT)

The MAX8770/MAX8771/MAX8772 include a single-

quadrant multiplier used to determine the actual output

power based on the inductor current (sum of the differ-

ential CS inputs) and output voltage (CSNpm to GNDS,

when CSNpm = CSN12 for MAX8771, CSNpm = CSN2

for MAX8770/MAX8772). The buffered output of this

multiplier is connected to POUT and provides a voltage

relative to the output power dissipation:

For automatic startup, the battery voltage should be

V

pm− V

I R

(

=

)(

)

CSN

GNDS LOAD SENSE

V

PWR

present before V . If the controller attempts to bring

CC

K

PWR

the output into regulation without the battery-voltage

present, the fault latch trips. The controller remains shut

down until the fault latch is cleared by toggling SHDN

where the power-monitor scale factor (K

) is typical-

PWR

ly 16.67mV. The power monitor allows the system to

accurately monitor the CPU’s power dissipation and

quickly predict if the system is about to overheat before

the significantly slower temperature sensor signals an

overtemperature alert.

or cycling the V

power supply below 0.5V.

CC

If the V

voltage drops below 4.25V, the controller

CC

assumes that there is not enough supply voltage to

make valid decisions. To protect the output from over-

voltage faults, the controller shuts down immediately

and forces a high-impedance output.

Phase Fault (PHASEGD, MAX8771 Only)

The MAX8771 includes a phase-fault output that sig-

nals the system that one of the two phases either has a

fault condition or is not matched with the other.

Detection is done by identifying the need for a large on-

time difference between phases in order to achieve or

move towards current balance. PHASEGD is forced low

Shutdown

When SHDN goes low, the MAX8770/MAX8771/MAX8772

enter low-power shutdown mode. CLKEN is pulled high

and PWRGD is pulled low immediately, and the output

voltage ramps down at 1/8 the slew rate set by R

:

TIME

when V

is below 0.6xV or above 1.4xV

.

CCI

FB

8V

OUT

t

=

PHASEGD is high impedance when the MAX8771 is set

to run in 1-phase operation (DPRSLPVR high, or PSI

low and DPRSLPVR low). On exit to the 2-phase mode,

PHASEGD is forced high impedance for 32 switching

cycles on DH2.

TRAN(SHDN)

dV

(

/dt

)

TARGET

where dV

/dt = 12.5mV/µs x 71.5kΩ / R

is

TIME

TARGET

the slew rate. Slowly discharging the output capacitors

by slewing the output over a long period of time keeps

the average negative inductor current low (damped

response), thereby eliminating the negative output-volt-

age excursion that occurs when the controller dis-

charges the output quickly by permanently turning on

the low-side MOSFET (underdamped response). This

PHASEGD is low in shutdown. PHASEGD is forced high

impedance whenever the slew rate controller is active

(output voltage transitions).

36 ______________________________________________________________________________________

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

forces the DL1 and DL2 high and pulls DH1 and DH2

low. Toggle SHDN or cycle the V power supply

below 0.5V to clear the fault latch and reactivate the

controller.

Temperature Comparator (VRHOT)

The MAX8770/MAX8771/MAX8772 also feature an

independent comparator with an accurate threshold

CC

(V

) that tracks the analog supply voltage (V

=

HOT

0.3V ). This makes the thermal trip threshold indepen-

CC

UVP can be disabled through the no-fault test mode

(see the No-Fault Test Mode section).

dent of the V

tor- and thermistor-divider between V

supply voltage tolerance. Use a resis-

CC

and GND to

CC

Thermal-Fault Protection

The MAX8770/MAX8771/MAX8772 feature a thermal-

fault-protection circuit. When the junction temperature

rises above +160°C, a thermal sensor sets the fault

latch and activates the soft-shutdown sequence. Once

the controller ramps down to zero, it forces the DL1 and

DL2 high and pulls DH1 and DH2 low. Toggle SHDN or

generate a voltage-regulator overtemperature monitor.

Place the thermistor as close to the MOSFETs and

inductors as possible.

Fault Protection (Latched)

Output Overvoltage Protection (MAX8770/

MAX8771 Only)

cycle the V

power supply below 0.5V to clear the

CC

The OVP circuit is designed to protect the CPU against

a shorted high-side MOSFET by drawing high current

and blowing the battery fuse. The MAX8770/MAX8771

continuously monitor the output for an overvoltage fault.

The controller detects an OVP fault if the output voltage

exceeds the set VID DAC voltage by more than 300mV,

regardless of the operating state. During pulse-skip-

ping operation (DPRSLPVR = high), the OVP threshold

is set at 1.8V once a downward VID transition occurs,

and reverts to track the VID DAC voltage when the out-

put reaches the set VID code.

fault latch and reactivate the controller after the junction

temperature cools by 15°C.

Thermal shutdown can be disabled through the no-fault

test mode (see the No-Fault Test Mode section).

No-Fault Test Mode

The latched fault-protection features can complicate

the process of debugging prototype breadboards

since there are (at most) a few milliseconds in which to

determine what went wrong. Therefore, a “no-fault” test

mode is provided to disable the fault protection—over-

voltage protection, undervoltage protection, and ther-

mal shutdown. Additionally, the test mode clears the

fault latch if it has been set. The no-fault test mode is

entered by forcing 11V to 13V on SHDN.

When the OVP circuit detects an overvoltage fault while

in multiphase mode (DPRSLPVR = low, PSI = high), the

MAX8770/MAX8771 immediately force DL1 and DL2

high and pull DH1 and DH2 low. This action turns on

the synchronous-rectifier MOSFETs with 100% duty

and, in turn, rapidly discharges the output filter capaci-

tor and forces the output low. If the condition that

caused the overvoltage (such as a shorted high-side

MOSFET) persists, the battery fuse blows. Toggle

MOSFET Gate Drivers

The DH and DL drivers are optimized for driving mod-

erate-sized high-side and larger low-side power

MOSFETs. This is consistent with the low duty factor

SHDN or cycle the V

power supply below 0.5V to

CC

seen in notebook applications where a large V - V

IN

OUT

clear the fault latch and reactivate the controller.

differential exists. The high-side gate drivers (DH)

source and sink 2.2A, and the low-side gate drivers

(DL) source 2.7A and sink 8A. This ensures robust gate

drive for high-current applications. The DH_ floating

high-side MOSFET drivers are powered by internal

boost switch charge pumps at BST_, while the DL_ syn-

chronous-rectifier drivers are powered directly by the

When an overvoltage fault occurs while in 1-phase

operation (DPRSLPVR = high, or PSI = low), the

MAX8770/MAX8771 immediately force DL1 high and

pull DH1 low. DL2 and DH2 remain low as phase 2 was

disabled. DL2 is forced high only when the output falls

below the UV threshold. Overvoltage protection can be

disabled through the no-fault test mode (see the No-

Fault Test Mode section).

5V bias supply (V ).

DD

Adaptive dead-time circuits monitor the DL and DH dri-

vers and prevent either FET from turning on until the

other is fully off. The adaptive driver dead time allows

operation without shoot-through with a wide range of

MOSFETs, minimizing delays and maintaining efficiency.

Output Undervoltage Protection

The output UVP function is similar to foldback current

limiting, but employs a timer rather than a variable cur-

rent limit. If the MAX8770/MAX8771/MAX8772 output

voltage is 400mV below the target voltage, the con-

troller activates the shutdown sequence and sets the

fault latch. Once the controller ramps down to zero, it

There must be a low-resistance, low-inductance path

from the DL and DH drivers to the MOSFET gates for

the adaptive dead-time circuits to work properly; other-

wise, the sense circuitry in the MAX8770/

______________________________________________________________________________________ 37

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

MOSFETs, greatly reduces coupling. Do not exceed

22nF of total gate capacitance to prevent excessive

turn-off delays.

(R )*

BST

INPUT (V )

IN

Alternatively, shoot-through currents may be caused by

a combination of fast high-side MOSFETs and slow low-

side MOSFETs. If the turn-off delay time of the low-side

MOSFET is too long, the high-side MOSFETs can turn

on before the low-side MOSFETs have actually turned

off. Adding a resistor less than 5Ω in series with BST

slows down the high-side MOSFET turn-on time, elimi-

nating the shoot-through currents without degrading

C

BST

DH

LX

N

H

L

C

BYP

V

DD

the turn-off time (R

in Figure 10). Slowing down the

BST

high-side MOSFET also reduces the LX node rise time,

thereby reducing EMI and high-frequency coupling

responsible for switching noise.

DL

N

L

(C )*

NL

Multiphase Quick-PWM

Design Procedure

PGND

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency

and inductor operating point (ripple-current ratio). The

primary design trade-off lies in choosing a good switch-

ing frequency and inductor operating point, and the fol-

lowing four factors dictate the rest of the design:

(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE

BST

SWITCHING NODE RISE TIME.

(C )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE

NL

COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS

• Input voltage range: The maximum value (V

)

IN(MAX)

must accommodate the worst-case high-AC adapter

voltage. The minimum value (V ) must account

Figure 10. Gate Drive Circuit

IN(MIN)

for the lowest input voltage after drops due to con-

nectors, fuses, and battery selector switches. If there

is a choice at all, lower input voltages result in better

efficiency.

MAX8771/MAX8772 interprets the MOSFET gates as

“off” while charge actually remains. Use very short,

wide traces (50 mils to 100 mils wide if the MOSFET is

1in from the driver).

• Maximum load current: There are two values to

The internal pulldown transistor that drives DL low is

robust, with a 0.25Ω (typ) on-resistance. This helps pre-

vent DL from being pulled up due to capacitive cou-

pling from the drain to the gate of the low-side

MOSFETs when the inductor node (LX) quickly switch-

consider. The peak load current (I

) deter-

LOAD(MAX)

mines the instantaneous component stresses and fil-

tering requirements, and thus drives output capacitor

selection, inductor saturation rating, and the design

of the current-limit circuit. The continuous load cur-

es from ground to V . Applications with high-input volt-

IN

rent (I

) determines the thermal stresses and

LOAD

ages and long inductive driver traces may require

rising LX edges that do not pull up the low-side

MOSFETs’ gate, causing shoot-through currents. The

capacitive coupling between LX and DL created by the

thus drives the selection of input capacitors,

MOSFETs, and other critical heat-contributing com-

ponents. Modern notebook CPUs generally exhibit

I

= I

x 80%.

LOAD

LOAD(MAX)

MOSFET’s gate-to-drain capacitance (C

), gate-to-

RSS

For multiphase systems, each phase supports a frac-

tion of the load, depending on the current balancing.

When properly balanced, the load current is evenly dis-

tributed among each phase:

source capacitance (C

- C

), and additional

ISS

RSS

board parasitics should not exceed the following mini-

mum threshold:

⎛

⎞

C

RSS

V

> V

IN

I

GS(TH)

⎜

⎟

LOAD

I

=

⎝

⎠

ISS

LOAD(PHASE)

η

TOTAL

Typically, adding a 4700pF between DL and power

ground (C in Figure 10), close to the low-side

where η

is the total number of active phases.

TOTAL

NL

38 ______________________________________________________________________________________

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

• Switching frequency: This choice determines the

basic trade-off between size and efficiency. The opti-

mal frequency is largely a function of maximum input

voltage due to MOSFET switching losses that are

Transient Response

The inductor ripple current impacts transient-response

performance, especially at low V - V

differentials.

OUT

IN

Low inductor values allow the inductor current to slew

faster, replenishing charge removed from the output fil-

ter capacitors by a sudden load step. The amount of

output sag is also a function of the maximum duty fac-

tor, which can be calculated from the on-time and mini-

mum off-time. For a dual-phase controller, the

worst-case output sag voltage may be determined by:

proportional to frequency and V ². The optimum fre-

IN

quency is also a moving target, due to rapid

improvements in MOSFET technology that are mak-

ing higher frequencies more practical.

• Inductor operating point: This choice provides

trade-offs between size vs. efficiency and transient

response vs. output noise. Low inductor values pro-

vide better transient response and smaller physical

size, but also result in lower efficiency and higher

output noise due to increased ripple current. The

minimum practical inductor value is one that causes

the circuit to operate at the edge of critical conduc-

tion (where the inductor current just touches zero

with every cycle at maximum load). Inductor values

lower than this grant no further size-reduction benefit.

The optimum operating point is usually found

between 20% and 50% ripple current.

⎡

⎢

⎤

⎥

2

⎛

⎞

V

T

OUT SW

V

L ∆I

+ t

OFF(MIN)

(

)

LOAD(MAX)

⎜

⎟

⎝

⎢

⎣

⎠

IN

⎥

⎦

V

=

SAG

⎡

⎢

⎤

⎥

⎛

⎞

V

− 2V

T

(

)

IN

OUT SW

2C

V

− 2t

OFF(MIN)

OUT OUT

⎜

⎟

V

⎢

⎣

⎥

⎦

⎝

IN

⎠

∆I

⎡

⎢

⎤

⎛

⎞

V

T

LOAD(MAX)

OUT SW

+

+ t

OFF(MIN)

⎥

⎜

⎟

2C

V

⎝

⎢

⎣

⎠

OUT

IN

⎥

⎦

where t

is the minimum off-time (see the

Electrical Characteristics table).

OFF(MIN)

Inductor Selection

The switching frequency and operating point (% ripple

current or LIR) determine the inductor value as follows:

The amount of overshoot due to stored inductor energy

can be calculated as:

2

⎛

⎞

⎛

⎞

V

I

− V

V

OUT

IN

OUT

∆I

L

L = η

(

)

LOAD(MAX)

TOTAL⎜

⎟

⎜

⎟

f

LIR

V

≈

⎝

⎠

⎝ SW LOAD(MAX)

⎠

IN

SOAR

2η

C

V

TOTAL OUT OUT

where η

is the total number of phases.

TOTAL

where η

is the total number of active phases.

TOTAL

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite

cores are often the best choice, although powdered

iron is inexpensive and can work well at 200kHz. The

core must be large enough not to saturate at the peak

Setting the Current Limit

The minimum current-limit threshold must be high

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

ley of the inductor current occurs at I

half the ripple current; therefore:

minus

LOAD(MAX)

inductor current (I

):

PEAK

I

⎛

⎞

LIR

2

LOAD(MAX)

⎛

⎞

I

⎛

⎞

I

=

1 +

⎜

⎝

⎟

⎠

⎛

LIR

2

⎞

LOAD(MAX)

PEAK

⎜

⎟

η

I

>

1 −

⎝

⎠

⎜

⎝

⎟

⎠

TOTAL

LIMIT(LOW)

⎜

⎟

η

⎝

⎠

TOTAL

where η

is the total number of active phases,

LIMIT(LOW)

TOTAL

and I

equals the minimum current-limit

threshold voltage divided by the current-sense resistor

(R ). For the 22.5mV default setting, the minimum

SENSE

current-limit threshold is 19.5mV.

______________________________________________________________________________________ 39

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PWM Controller for IMVP-6+ CPU Core Power Supplies

Output Capacitor Selection

The output filter capacitor must have low enough ESR to

meet output ripple and load-transient requirements, yet

have high enough ESR to satisfy stability requirements.

Output Capacitor Stability Considerations

For Quick-PWM controllers, stability is determined by

the value of the ESR zero relative to the switching

frequency. The boundary of instability is given by the

following equation:

In CPU V

converters and other applications where

CORE

the output is subject to large load transients, the output

capacitor’s size typically depends on how much ESR is

needed to prevent the output from dipping too low

under a load transient. Ignoring the sag due to finite

capacitance:

f

SW

π

f

≤

ESR

where:

1

f

=

and

ESR

2πR

C

V

EFF OUT

STEP

R

(

+ R

≤

)

ESR

PCB

R

= R

+ R

PCB

∆I

EFF

ESR

DROOP

LOAD(MAX)

where C

is the total output capacitance, R

is the

OUT

total ESR, R

ESR

In non-CPU applications, the output capacitor’s size

often depends on how much ESR is needed to maintain

an acceptable level of output ripple voltage. The output

ripple voltage of a step-down controller equals the total

inductor ripple current multiplied by the output capaci-

tor’s ESR. When operating multiphase systems out-of-

phase, the peak inductor currents of each phase are

staggered, resulting in lower output ripple voltage by

reducing the total inductor ripple current. For multi-

phase operation, the maximum ESR to meet ripple

requirements is:

is the current-sense resistance (R

CM

SENSE

DROOP

= R ), R

is the voltage-positioning gain, and

CS

R

is the parasitic board resistance between the out-

PCB

put capacitors and sense resistors.

For a standard 300kHz application, the ESR zero fre-

quency must be well below 95kHz, preferably below

50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP

capacitors in widespread use at the time of publication

have typical ESR zero frequencies below 50kHz. In the

standard application circuit, the ESR needed to support

a 30mV

ripple is 30mV/(40A x 0.3) = 2.5mΩ. Four

P-P

330µF/2.5V Panasonic SP (type SX) capacitors in paral-

lel provide 1.5mΩ (max) ESR. With a 2mΩ droop and

0.5mΩ PC board resistance, the typical combined ESR

results in a zero at 30kHz.

⎡

⎢

⎤

⎥

V f

L

IN SW

R

≤

V

RIPPLE

ESR

V

− η

V V

(

)

⎢

⎣

⎥

⎦

IN

TOTAL OUT OUT

where η

is the total number of active phases and

TOTAL

Ceramic capacitors have a high ESR zero frequency,

but applications with significant voltage positioning can

take advantage of their size and low ESR. Do not put

high-value ceramic capacitors directly across the output

without verifying that the circuit contains enough voltage

positioning and series PC board resistance to ensure

stability. When only using ceramic output capacitors,

f

is the switching frequency per phase. The actual

SW

capacitance value required relates to the physical size

needed to achieve low ESR, as well as to the chemistry

of the capacitor technology. Thus, the capacitor is usu-

ally selected by ESR and voltage rating rather than by

capacitance value (this is true of polymer types).

When using low-capacity ceramic filter capacitors,

capacitor size is usually determined by the capacity

output overshoot (V

) typically determines the mini-

SOAR

mum output capacitance requirement. Their relatively

low capacitance value can cause output overshoot

when stepping from full-load to no-load conditions,

unless a small inductor value is used (high switching

frequency) to minimize the energy transferred from

inductor to capacitor during load-step recovery. The

efficiency penalty for operating at 600kHz is approxi-

mately 5% when compared to the 300kHz circuit, pri-

marily due to the high-side MOSFET switching losses.

needed to prevent V

and V

from causing

SOAR

SAG

problems during load transients. Generally, once

enough capacitance is added to meet the overshoot

requirement, undershoot at the rising load edge is no

longer a problem (see the V

and V

equations

SOAR

SAG

in the Transient Response section).

40 ______________________________________________________________________________________

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Unstable operation manifests itself in two related but

distinctly different ways: double-pulsing and feed-back

loop instability. Double pulsing occurs due to noise on

the output or because the ESR is so low that there is

not enough voltage ramp in the output voltage signal.

This “fools” the error comparator into triggering a new

cycle immediately after the minimum off-time period

has expired. Double pulsing is more annoying than

harmful, resulting in nothing worse than increased out-

put ripple. However, it can indicate the possible pres-

ence of loop instability due to insufficient ESR. Loop

instability can result in oscillations at the output after

line or load steps. Such perturbations are usually

damped, but can cause the output voltage to rise

above or fall below the tolerance limits.

Power MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability

when using high-voltage (>20V) AC adapters. Low-cur-

rent applications usually require less attention.

The high-side MOSFET (N ) must be able to dissipate

H

the resistive losses plus the switching losses at both

V

and V

. Calculate both of these sums.

IN(MAX)

IN(MIN)

Ideally, the losses at V

should be roughly equal

IN(MIN)

to losses at V

the losses at V

losses at V

(reducing R

if the losses at V

losses at V

(increasing R

, with lower losses in between. If

IN(MAX)

are significantly higher than the

IN(MIN)

, consider increasing the size of N

IN(MAX)

DS(ON)

H

but with higher C

IN(MAX)

). Conversely,

are significantly higher than the

GATE

, consider reducing the size of N

IN(MIN)

DS(ON)

H

The easiest method for checking stability is to apply a

very fast zero-to-max load transient and carefully

observe the output voltage ripple envelope for over-

shoot and ringing. It can help to simultaneously monitor

the inductor current with an AC current probe. Do not

allow more than one cycle of ringing after the initial

step-response under/overshoot.

to lower C

). If V does not

GATE IN

vary over a wide range, the minimum power dissipation

occurs where the resistive losses equal the switching

losses.

Choose a low-side MOSFET that has the lowest possi-

ble on-resistance (R

), comes in a moderate-

DS(ON)

sized package (i.e., one or two 8-pin SOs, DPAK, or

D²PAK), and is reasonably priced. Make sure that the

DL gate driver can supply sufficient current to support

the gate charge and the current injected into the para-

sitic gate-to-drain capacitor caused by the high-side

MOSFET turning on; otherwise, cross-conduction prob-

lems may occur (see the MOSFET Gate Driver section).

Input Capacitor Selection

The input capacitor must meet the ripple current

requirement (I

) imposed by the switching currents.

RMS

The multiphase Quick-PWM controllers operate out-of-

phase while the Quick-PWM slave controllers provide

selectable out-of-phase or in-phase on-time triggering.

Out-of-phase operation reduces the RMS input current

by dividing the input current between several stag-

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor

gered stages. For duty cycles less than 100%/η

OUTPH

extremes. For the high-side MOSFET (N ), the worst-

H

per phase, the I

requirements may be determined

RMS

case power dissipation due to resistance occurs at the

minimum input voltage:

by the following equation:

2

⎛

⎞

I

⎛

⎞ ⎛

⎞

V

I

LOAD

η

TOTAL

LOAD

OUT

I

=

η

V

− η

V

(

)

PD (N Resistive) =

R

DS(ON)

RMS

TOTAL OUT IN

TOTAL OUT

⎜

⎟

⎜

⎟ ⎜

⎟

H

η

V

⎝

⎠

TOTAL IN

⎝

⎠ ⎝

⎠

IN

where η

is the total number of phases.

where η

is the total number of out-of-phase

TOTAL

switching regulators. The worst-case RMS current

requirement occurs when operating with V

Generally, a small high-side MOSFET is desired to

reduce switching losses at high input voltages.

However, the R

power dissipation often limits how small the MOSFET

can be. Again, the optimum occurs when the switching

losses equal the conduction (R

=

IN

2η

V

RMS

. At this point, the above equation simpli-

TOTAL OUT

fies to I

required to stay within package

DS(ON)

= 0.5 x I

/η

.

LOAD TOTAL

For most applications, nontantalum chemistries (ceram-

ic, aluminum, or OS-CON) are preferred due to their

resistance to inrush surge currents typical of systems

with a mechanical switch or connector in series with the

input. If the Quick-PWM controller is operated as the

second stage of a two-stage power-conversion system,

tantalum input capacitors are acceptable. In either con-

figuration, choose an input capacitor that exhibits less

than +10°C temperature rise at the RMS input current

for optimal circuit longevity.

) losses. High-

DS(ON)

side switching losses do not usually become an issue

until the input is greater than approximately 15V.

Calculating the power dissipation the in high-side MOS-

FET (N ) due to switching losses is difficult since it

H

must allow for difficult quantifying factors that influence

the turn-on and turn-off times. These factors include the

internal gate resistance, gate charge, threshold volt-

______________________________________________________________________________________ 41

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

age, source inductance, and PC board layout charac-

teristics. The following switching-loss calculation pro-

vides only a very rough estimate and is no substitute for

breadboard evaluation, preferably including verification

Choose a Schottky diode (D ) with a forward voltage

L

low enough to prevent the low-side MOSFET body

diode from turning on during the dead time. Select a

diode that can handle the load current per phase dur-

ing the dead times. This diode is optional and can be

removed if efficiency is not critical.

using a thermocouple mounted on N :

H

PD (N SWITCHING) =

Boost Capacitors

H

The boost capacitors (C

) must be selected large

BST

2

V

I

f

Q

I

⎛

⎞ ⎛

⎞

C

V

f

IN(MAX) LOAD SW

G(SW)

OSS IN SW

2

enough to handle the gate-charging requirements of

the high-side MOSFETs. Typically, 0.1µF ceramic

capacitors work well for low-power applications driving

medium-sized MOSFETs. However, high-current appli-

cations driving large, high-side MOSFETs require boost

capacitors larger than 0.1µF. For these applications,

select the boost capacitors to avoid discharging the

capacitor more than 200mV while charging the high

side MOSFETs’ gates:

+

⎜

⎟ ⎜

⎟

η

⎝

⎠ ⎝

⎠

TOTAL

GATE

where C

G(SW)

FET, and I

rent (2.2A typ).

is the N MOSFET’s output capacitance,

H

OSS

Q

is the charge needed to turn on the N MOS-

H

is the peak gate-drive source/sink cur-

GATE

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum AC adapter

voltages are applied due to the squared term in the C x

N × Q

GATE

2

V

x ƒ

switching-loss equation. If the high-side

SW

C

=

IN

BST

200mV

MOSFET chosen for adequate R

at low battery

DS(ON)

voltages becomes extraordinarily hot when biased from

, consider choosing another MOSFET with

where N is the number of high side MOSFETs used for

one regulator, and Q is the gate charge specified

in the MOSFET’s data sheet. For example, assume (2)

IRF7811W n-channel MOSFETs are used on the high

side. According to the manufacturer’s data sheet, a sin-

gle IRF7811W has a maximum gate charge of 24nC

V

IN(MAX)

lower parasitic capacitance.

GATE

For the low-side MOSFET (N ), the worst-case power

L

dissipation always occurs at maximum input voltage:

(V

= 5V). Using the above equation, the required

PD (N RESISTIVE) =

GS

L

boost capacitance would be:

2

⎡

⎤

⎥

⎛

⎞

⎛

⎞

V

I

LOAD

η

TOTAL

OUT

⎢

1 −

R

DS(ON)

⎜

⎟

⎜

⎟

2 × 24nC

200mV

V

⎢

⎥

⎦

⎝

⎠

IN(MAX)

⎝

⎠

C

=

= 0.24µF

⎣

BST

The worst case for MOSFET power dissipation occurs

under heavy overloads that are greater than

LOAD(MAX)

Selecting the closest standard value, this example

requires a 0.22µF ceramic capacitor.

I

, but are not quite high enough to exceed

the current limit and cause the fault latch to trip. To pro-

tect against this possibility, you can “overdesign” the

circuit to tolerate:

Current-Balance Compensation (CCI)

The current-balance compensation capacitor (C

)

CCI

integrates the difference between the main and sec-

ondary current-sense voltages. The internal compensa-

∆I

⎛

⎝

⎞

INDUCTOR

tion resistor (R

= 200kΩ) improves transient

CCI

I

= η

I

+

⎜

⎟

⎠

LOAD

TOTAL VALLEY(MAX)

2

response by increasing the phase margin. This allows

the dynamics of the current-balance loop to be opti-

mized. Excessively large capacitor values increase the

integration time constant, resulting in larger current dif-

ferences between the phases during transients.

Excessively small capacitor values allow the current

loop to respond cycle-by-cycle, but can result in small

DC current variations between the phases. Likewise,

excessively large resistor values can also cause DC

current variations between the phases. Small resistor

values reduce the phase margin, resulting in marginal

I

LIR

⎛

⎞

LOAD(MAX)

2

= η

I

+

TOTAL VALLEY(MAX)

⎜

⎟

⎝

⎠

where I

is the maximum valley current

VALLEY(MAX)

allowed by the current-limit circuit, including threshold

tolerance and on-resistance variation. The MOSFETs

must have a good size heatsink to handle the overload

power dissipation.

42 ______________________________________________________________________________________

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

CPU

C

OUT

C

OUT

OUTPUT

INDUCTOR

INPUT

PLACE CONTROLLER ON BACKSIDE WHEN POSSIBLE, USING THE

GROUND PLANE TO SHIELD THE IC FROM EMI.

SEE THE EVALUATION KIT FOR ANALOG/POWER GROUND AND

CONTROLLER LAYOUT EXAMPLE.

Figure 11. PC Board Layout Example

stability in the current-balance loop. For most applica-

tions, a 470pF capacitor from CCI to the switching reg-

ulator’s output works well.

rent-sense resistance to be used, reducing the overall

power dissipated.

Steady-State Voltage Positioning

Connecting the compensation network to the output

Connect a resistor (R ) between FB and V

to set

FB

OUT

(V

) allows the controller to feed-forward the output-

OUT

the DC steady-state droop (load line) based on the

required voltage-positioning slope (R ):

voltage signal, especially during transients. To reduce

noise pickup in applications that have a widely distrib-

uted layout, it is sometimes helpful to connect the com-

pensation network to the quiet analog ground rather

DROOP

R

DROOP

R

=

FB

R

G

SENSE m(FB)

than V

.

OUT

Voltage Positioning and Loop

Compensation

where the effective current-sense resistance (R

)

SENSE

depends on the current-sense method (see the Current

Sense section), and the voltage-positioning amplifier’s

Voltage positioning dynamically lowers the output volt-

age in response to the load current, reducing the out-

put capacitance and processor’s power-dissipation

requirements. The controller uses a transconductance

amplifier to set the transient and DC output voltage

droop (Figure 2) as a function of the load. This adjusta-

bility allows flexibility in the selected current-sense

resistor value or inductor DCR, and allows smaller cur-

transconductance (G

) is typically 600µS, as

m(FB)

defined in the Electrical Characteristics table. The con-

troller sums together the input signals of the current-

sense inputs (CSP_, CSN_).

When the inductors’ DCR is used as the current-sense

element (R

= R

), each current-sense input

DCR

SENSE

should include an NTC thermistor to minimize the tem-

perature dependence of the voltage-positioning slope.

______________________________________________________________________________________ 43

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CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

3.3V BIAS

SUPPLY

5V BIAS

SUPPLY

C1

2.2µF

R1

10Ω

R3

1.9kΩ

R2

1.9kΩ

V

DD

CC

C2

R18

200kΩ

2.2µF

INPUT V

8V TO 24V

IN

RTON

BST1

R22

0Ω

CLK_ENABLE#

IMVPOK

CLKEN

C3

0.22µF

PWRGD

PHASEGD

C

IN

+

D0

D1

D2

D3

D4

D5

D6

DH1

LX1

DL1

RCS1

2mΩ

N

H1

OUTPUT

L1

DAC INPUTS

(1V LOGIC)

C

OUT

N

L1

R12

100Ω

PGND1

GND

C11

2.2nF

R16*

10Ω

PSI#

DPRSTP#

PSI

CSP1

DPRSTP

*CSN1

CPU GND

SENSE

DPRLSPVR

VR_ON

DPRSLPVR

SHDN

R11*

10Ω

R9

4.12kΩ

R10

100Ω

C5

1000pF

MAX8770

MAX8771

MAX8772

CCV

REF

FB

CPU V

SENSE

CC

C8

4700pF

C6

0.1µF

POWER GROUND

ANALOG GROUND

CCI

BST2

DH2

LX2

R5

71.5kΩ

TIME

R6

13kΩ

DL2

V

THRM

CC

NTC4

100kΩ

PGND2

1.2V BIAS

SUPPLY

CSP2

R7

56Ω

*CSN2

R17

100Ω

VRHOT

POUT

GNDS

C9

* CSN1 AND CSN2 ARE BONDED TOGETHER ON THE

MAX8771 AND CALLED CSN12.

C10

0.1µF

R8

10kΩ

4700pF

**

OPTIONAL -- RESISTOR ALLOW REMOTE SENSING FOR SYSTEM

VERIFICATION WHEN THE CPU IS NOT PRESENT;

PHASEGD IS ONLY ON THE MAX8771.

Figure 12. Single-Phase ULV Design

44 ______________________________________________________________________________________

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Dropout design example:

= 1.15V

Minimum Input-Voltage Requirements and

Dropout Performance

V

VID

The output voltage-adjustable range for continuous-

conduction operation is restricted by the nonadjustable

minimum off-time one-shot and the number of phases.

For best dropout performance, use the slower (200kHz)

on-time settings. When working with low input voltages,

the duty-factor limit must be calculated using worst-

case values for on- and off-times.

f

t

= 300kHz

SW

OFF(MIN)

= 375ns

V

= 2.1mV/A x 44A = 92.4mV

DROOP

= 150mV (44A Load)

CHG

h = 1.5

Manufacturing tolerances and internal propagation

delays introduce an error to the on-times. This error is

greater at higher frequencies. Also, keep in mind that

transient response performance of buck regulators

operated too close to dropout is poor, and bulk output

⎡

⎢

⎣

⎤

⎥

⎦

1.15V − 92.4mV + 150mV

1 − (0.375µs × 1.5 × 300kHz)

V

=

=1.45V

IN(MIN)

Calculating again with h = 1 gives the absolute limit of

dropout:

capacitance must often be added (see the V

equa-

SAG

tion in the Design Procedure section).

⎡

⎢

⎣

⎤

⎥

⎦

1.15V − 92.4mV + 150mV

1 − (0.375µs × 1.0 × 300kHz)

The absolute point of dropout is when the inductor cur-

rent ramps down during the minimum off-time (∆I

V

=

=1.36V

IN(MIN)

)

DOWN

as much as it ramps up during the on-time (∆I ). The

UP

Therefore, V must be greater than 4.1V, even with

IN

ratio h = ∆I /∆I

is an indicator of the ability to

UP DOWN

very large output capacitance, and a practical input

voltage with reasonable output capacitance would be

5.0V.

slew the inductor current higher in response to

increased load, and must always be greater than 1. As

h approaches 1, the absolute minimum dropout point,

the inductor current cannot increase as much during

Applications Information

each switching cycle and V

greatly increases

SAG

unless additional output capacitance is used.

PC Board Layout Guidelines

Careful PC board layout is critical to achieve low switching

losses and clean, stable operation. The switching power

stage requires particular attention (Figure 11). If possible,

mount all the power components on the top side of the

board with their ground terminals flush against one anoth-

er. Follow these guidelines for good PC board layout:

A reasonable minimum value for h is 1.5, but adjusting

this up or down allows tradeoffs between V

, output

SAG

capacitance, and minimum operating voltage. For a

given value of h, the minimum operating voltage can be

calculated as:

⎡

⎢

⎤

⎥

V

− V

1 − h × t

+ V

CHG

1) Keep the high-current paths short, especially at the

ground terminals. This is essential for stable, jitter-free

operation.

VID

DROOP

V

=

IN(MIN)

f

⎢

⎣

⎥

⎦

OFF(MIN) SW

where V

is the voltage-positioning droop, V

CHG

DROOP

2) Connect all analog grounds to a separate solid cop-

per plane, which connects to the GND pin of the

is the parasitic voltage drops in the charge path (see

the On-Time One-Shot section) and t

is from

OFF(MIN)

Quick-PWM controller. This includes the V

bypass

CC

the Electrical Characteristics table. The absolute mini-

capacitor, REF and GNDS bypass capacitors, and

compensation (CCV) components.

mum input voltage is calculated with h = 1.

If the calculated V

imum input voltage, then reduce the operating frequency

or add output capacitance to obtain an acceptable V

If operation near dropout is anticipated, calculate V

be sure of adequate transient response.

is greater than the required min-

IN(MIN)

3) Keep the power traces and load connections short.

This is essential for high efficiency. The use of thick

copper PC boards (2oz vs. 1oz) can enhance full-

load efficiency by 1% or more. Correctly routing PC

board traces is a difficult task that must be

approached in terms of fractions of centimeters,

where a single mΩ of excess trace resistance causes

a measurable efficiency penalty.

.

SAG

to

SAG

4) Keep the high-current, gate-driver traces (DL, DH,

LX, and BST) short and wide to minimize trace resis-

tance and inductance. This is essential for high-

______________________________________________________________________________________ 45

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MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

power MOSFETs that require low-impedance gate

drivers to avoid shoot-through currents.

Make the DC-DC controller ground connections as shown

in the Standard Application Circuits. This diagram can be

viewed as having four separate ground planes: input/out-

put ground, where all the high-power components go; the

5) CSP_ and CSN_ connections for current limiting and

voltage positioning must be made using Kelvin-sense

connections to guarantee the current-sense accuracy.

power ground plane, where the PGND pin and V

DD

bypass capacitor go; the master’s analog ground plane

where sensitive analog components, the master’s GND

6) When trade-offs in trace lengths must be made, it is

preferable to allow the inductor charging path to be

made longer than the discharge path. For example, it

is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-side

MOSFET or between the inductor and the output filter

capacitor.

pin, and V bypass capacitor go; and the slave’s analog

CC

ground plane where the slave’s GND pin and V bypass

CC

capacitor go. The master’s GND plane must meet the

PGND plane only at a single point directly beneath the IC.

Similarly, the slave’s GND plane must meet the PGND

plane only at a single point directly beneath the IC. The

respective master and slave ground planes should con-

nect to the high-power output ground with a short metal

trace from PGND to the source of the low-side MOSFET

(the middle of the star ground). This point must also be

very close to the output capacitor ground terminal.

7) Route high-speed switching nodes away from sensi-

tive analog areas (REF, CCV, CCI, FB, CSP_, CSN_,

etc.).

Layout Procedure

Connect the output power planes (V

and system

CORE

Place the power components first, with ground terminals

ground planes) directly to the output filter capacitor

positive and negative terminals with multiple vias. Place

the entire DC-DC converter circuit as close to the CPU

as is practical.

adjacent (low-side MOSFET source, C , C

, and D1

OUT

IN

anode). If possible, make all these connections on the top

layer with wide, copper-filled areas:

Mount the controller IC adjacent to the low-side MOSFET.

The DL gate traces must be short and wide (50 mils to 100

mils wide if the MOSFET is 1in from the controller IC).Group

Chip Information

TRANSISTOR COUNT: 8990

the gate-drive components (BST capacitors, V

capacitor) together near the controller IC.

bypass

DD

PROCESS: BiCMOS

Pin Configurations

TOP VIEW

30 29 28 27 26 25 24 23 22 21

20 BST2

31

32

33

34

35

36

37

38

39

40

31

32

33

34

35

36

37

38

39

40

D0

D1

D2

D0

D1

D2

19

18

19

18

V

CC

GND

17 CSP1

17 PHASEGD

D3

D4

D3

D4

16

15

14

16

15

14

CSN1

CSN2

CSP2

CSP1

CSN12

CSP2

MAX8770

MAX8772

MAX8771

D5

D6

D5

D6

13 GNDS

SHDN

12

FB

12

FB

DPRSLPVR

DPRSTP

DPRSLPVR

DPRSTP

11

REF

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

THIN QFN

6mm x 6mm

THIN QFN

6mm x 6mm

A "+" SIGN REPLACES THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES.

46 ______________________________________________________________________________________

®

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

(NE-1) X

e

E

E/2

k

D/2

C

(ND-1) X

e

D

D2

L

D2/2

e

b

E2/2

L

C

L

k

E2

e

L

C

L

L1

L

e

A

A1

A2

PACKAGE OUTLINE

36, 40, 48L THIN QFN, 6x6x0.8mm

1

F

21-0141

2

NOTES:

1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.

2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.

3. N IS THE TOTAL NUMBER OF TERMINALS.

4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1

SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE

ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.

5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm

FROM TERMINAL TIP.

6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.

7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.

8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.

9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1.

10. WARPAGE SHALL NOT EXCEED 0.10 mm.

11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.

12. NUMBER OF LEADS SHOWN FOR REFERENCE ONLY.

PACKAGE OUTLINE

36, 40, 48L THIN QFN, 6x6x0.8mm

2

F

21-0141

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 47

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX8770
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	MAX8770/MAX8771/MAX8772 Dual-Phase, Quick- PWM Controller for IMVP-6 CPU Core Power Supplies
文件：	总47页 (文件大小：1023K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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