MAX8792ETDT [MAXIM]
Single Quick-PWM Step-Down Controller with Dynamic REFIN; 单一的Quick-PWM降压型控制器，具有动态REFIN
| 型号： | MAX8792ETDT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single Quick-PWM Step-Down Controller with Dynamic REFIN |
| 文件： | 总29页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0739; Rev 0; 1/07
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
General Description
Features
o Quick-PWM with Fast Transient Response
The MAX8792 pulse-width modulation (PWM) controller
provides high efficiency, excellent transient response,
and high DC-output accuracy needed for stepping
down high-voltage batteries to generate low-voltage
core or chipset/RAM bias supplies in notebook comput-
ers. The output voltage can be dynamically controlled
using the dynamic REFIN, which supports input volt-
ages between 0 to 2V. The REFIN adjustability com-
bined with a resistive voltage-divider on the feedback
input allows the MAX8792 to be configured for any out-
o Supports Any Output Capacitor
No Compensation Required with
Polymers/Tantalum
Stable with Ceramic Output Capacitors Using
External Compensation
o Precision 2V ±±1mV Reꢀerence
o Dynamically Adjustable Output Voltage
(1 to 1.9 V Range)
IN
Feedback Input Regulates to 1 to 2V REFIN
Voltage
put voltage between 0 to 0.9 V .
IN
1.5% V
Accuracy Over Line and Load
OUT
Maxim’s proprietary Quick-PWM™ quick-response, con-
stant-on-time PWM control scheme handles wide
input/output voltage ratios (low-duty-cycle applications)
with ease and provides 100ns “instant-on” response to
load transients while maintaining a relatively constant
switching frequency. Strong drivers allow the MAX8792
to efficiently drive large synchronous-rectifier MOSFETs.
o 26V Maximum Input Voltage Rating
o Adjustable Valley Current-Limit Protection
Thermal Compensation with NTC
Supports Foldback Current Limit
o Resistively Programmable Switching Frequency
o Overvoltage Protection
The controller senses the current across the synchro-
nous rectifier to achieve a low-cost and highly efficient
valley current-limit protection. The adjustable current-
limit threshold provides a high degree of flexibility,
allowing thermally compensated protection using an
NTC or foldback current-limit protection using a volt-
age-divider derived from the output.
o Undervoltage/Thermal Protection
o Voltage Soꢀt-Start and Soꢀt-Shutdown
o Monotonic Power-Up with Precharged Output
o Power-Good Window Comparator
Ordering Information
The MAX8792 includes a voltage-controlled soft-start
and soft-shutdown in order to limit the input surge cur-
rent, provide a monotonic power-up (even into a
precharged output), and provide a predictable power-
up time. The controller also includes output fault protec-
tion—undervoltage and overvoltage protection—as well
as thermal-fault protection.
PKG
CODE MARK
TOP
PART
PIN-PACKAGE
MAX8792ETD+T 14 TDFN-EP* 3mm x 3mm T1433-1 ADC
Note: This device is specified over the -40°C to +80°C operating
temperature range.
+Denotes a lead-free package.
The MAX8792 is available in a tiny 14-pin, 3mm x 3mm
TDFN package. For space-constrained applications,
refer to the MAX17016 single step-down with 10A, 26V
internal MOSFETs available in a small 40-pin, 6mm x
6mm TQFN package.
Pin Configuration
TOP VIEW
14 13 12 11 10
9
8
.
Applications
Notebook Computers
I/O and Chipset Supplies
GPU Core Supply
MAX8792
DDR Memory—VDDQ or VTT
Point-of-Load Applications
Step-Down Power Supply
GND
6
1
2
3
4
5
7
TDFN
(3mm x 3mm)
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering inꢀormation, please contact Maxim/Dallas Direct! at
±-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
ABSOLUTE MAXIMUM RATINGS
TON to GND ...........................................................-0.3V to +28V
DH to LX....................................................-0.3V to (V
+ 0.3V)
BST
V
V
to GND..............................................................-0.3V to +6V
REF Short Circuit to GND...........................................Continuous
DD
CC
to GND................................................-0.3V to (V
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
DD
A
EN, SKIP, PGOOD to GND.......................................-0.3V to +6V
REF, REFIN to GND....................................-0.3V to (V + 0.3V)
ILIM, FB to GND .........................................-0.3V to (V
DL to GND..................................................-0.3V to (V
BST to GND.................................................(V
BST to LX..................................................................-0.3V to +6V
BST to V .............................................................-0.3V to +28V
14-Pin 3mm x 3mm TDFN
(derated 24.4mW/°C above +70°C)....................1951mW
Operating Temperature Range (extended).........-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
CC
DD
+ 0.3V)
+ 0.3V)
- 0.3V) to +34V
DD
MAX8792
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, V
= V
= V = 5V, REFIN = ILIM = REF, SKIP = GND. T = 1°C to +85°C, unless otherwise spec-
CC EN A
IN
DD
ified. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
PWM CONTROLLER
Input Voltage Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
2
26
1.2
2
V
IN
Quiescent Supply Current (V
)
I
+ I
FB forced above REFIN
EN = GND, T = +25°C
0.7
0.1
mA
µA
Ω
DD
DD
CC
I
SHDN
Shutdown Supply Current (V
)
DD
A
V
-to-V
Resistance
R
20
DD
CC
CC
R
TON
R
TON
R
TON
= 97.5kΩ (600kHz)
118
250
354
139
278
417
200
160
306
480
300
V
V
= 12V,
= 1.0V
IN
On-Time
t
= 200kΩ (300kHz)
ns
ON
FB
(Note 3)
= 302.5kΩ (200kHz)
Minimum Off-Time
t
(Note 3)
ns
OFF(MIN)
EN = GND, V
= 26V,
TON
TON Shutdown Supply Current
0.01
1
µA
V
= 0V or 5V, T = +25°C
A
CC
REFIN Voltage Range
FB Voltage Range
V
(Note 2)
(Note 2)
0
0
V
V
V
V
REFIN
REF
REF
V
FB
T
T
= +25°C
0.495
0.5
0.505
V
= 0.5V,
A
REFIN
measured at FB,
= 2V to 26V,
V
IN
= 0°C to +85°C
0.493
0.507
A
SKIP = V
DD
FB Voltage Accuracy
V
V
FB
T
T
T
= +25°C
0.995
0.993
1.990
-0.1
1.0
2.0
1.005
1.007
2.010
+0.1
A
A
A
V
= 1.0V
= 2.0V
REFIN
= 0°C to +85°C
= 0°C to +85°C
V
V
REFIN
FB Input Bias Current
Load-Regulation Error
Line-Regulation Error
Soft-Start/-Stop Slew Rate
Dynamic REFIN Slew Rate
REFERENCE
I
t
= 0.5V to 2.0V, T = +25°C
µA
%
FB
SS
FB
A
I
= 0 to 3A, SKIP = V
0.1
0.25
1
LOAD
DD
V
= 4.5V to 5.5V, V = 4.5V to 26V
%
CC
IN
Rising/falling edge on EN
Rising edge on REFIN
mV/µs
mV/µs
t
8
DYN
No load
= -10µA to +50µA
1.990
1.98
2.00
2.010
2.02
V
= 4.5V
CC
Reference Voltage
V
V
REF
to 5.5V
I
REF
2
_______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V
= V
= V = 5V, REFIN = ILIM = REF, SKIP = GND. T = 1°C to +85°C, unless otherwise spec-
CC EN A
IN
DD
ified. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mV
FAULT DETECTION
With respect to the internal target voltage
(error comparator threshold); rising edge;
hysteresis = 50mV
250
300
350
Output Overvoltage-Protection
Trip Threshold
OVP
V
+
REF
Dynamic transition
0.30
V
Minimum OVP threshold
FB forced 25mV above trip threshold
0.7
Output Overvoltage
Fault-Propagation Delay
t
5
µs
mV
µs
OVP
With respect to the internal target voltage
(error comparator threshold) falling edge;
hysteresis = 50mV
Output Undervoltage-Protection
Trip Threshold
UVP
-240
100
-200
200
-160
350
Output Undervoltage
Fault-Propagation Delay
t
FB forced 25mV below trip threshold
UVP
UVP falling edge, 25mV overdrive
OVP rising edge, 25mV overdrive
Startup delay
5
5
PGOOD Propagation Delay
t
I
µs
PGOOD
PGOOD
100
200
350
0.4
PGOOD Output-Low Voltage
PGOOD Leakage Current
I
= 3mA
V
SINK
FB = REFIN (PGOOD high impedance),
PGOOD forced to 5V, T = +25°C
A
1
µA
Fault blanking initiated; REFIN deviation
from the internal target voltage (error
comparator threshold); hysteresis = 10mV
Dynamic REFIN Transition Fault
Blanking Threshold
50
mV
Thermal-Shutdown Threshold
T
Hysteresis = 15°C
160
4.2
°C
V
SHDN
V
Undervoltage Lockout
Rising edge, PWM disabled below this
level; hysteresis = 100mV
CC
V
3.95
4.45
UVLO(VCC)
Threshold
CURRENT LIMIT
ILIM Input Range
0.4
18
92
V
V
REF
V
= 0.4V
20
22
ILIM
Current-Limit Threshold
V
mV
ILIMIT
ILIM = REF (2.0V)
100
108
Current-Limit Threshold
(Negative)
V
V
= 0.4V
-24
1
mV
mV
INEG
ILIM
Current-Limit Threshold
(Zero Crossing)
V
V
= 0.4V,
ILIM
V
ZX
- V , SKIP = GND or open
GND
LX
Ultrasonic Frequency
SKIP = open (3.3V); V = V
+ 50mV
+ 50mV
18
30
35
kHz
mV
FB
REFIN
REFIN
Ultrasonic Current-Limit Threshold
SKIP = open (3.3V); V = V
FB
_______________________________________________________________________________________
3
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V
= V
= V = 5V, REFIN = ILIM = REF, SKIP = GND. T = 1°C to +85°C, unless otherwise spec-
CC EN A
IN
DD
ified. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
GATE DRIVERS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Low state (pulldown)
High state (pullup)
1.2
1.2
1.7
0.9
3.5
3.5
4
DH Gate Driver On-Resistance
DL Gate Driver On-Resistance
R
BST - LX forced to 5V
Ω
ON(DH)
MAX8792
High state (pullup)
R
Ω
ON(DL)
Low state (pulldown)
2
DH Gate Driver Source/
Sink Current
I
DH forced to 2.5V, BST - LX forced to 5V
1.5
A
DH
DL Gate Driver Source Current
DL Gate Driver Sink Current
I
DL forced to 2.5V
DL forced to 2.5V
DH low to DL high
DL low to DH high
1
2.4
25
35
20
20
20
20
4
A
A
DL(SOURCE)
I
DL(SINK)
10
15
Driver Propagation Delay
DL Transition Time
ns
ns
DL falling, C = 3nF
DL
DL rising, C = 3nF
DL
DH falling, C
= 3nF
= 3nF
DH
DH
DH Transition Time
ns
DH rising, C
Internal BST Switch On-Resistance
INPUTS AND OUTPUTS
EN Logic-Input Threshold
EN Logic-Input Current
R
I
I
= 10mA, V = 5V
DD
7
Ω
BST
BST
V
EN rising edge, hysteresis = 450mV (typ)
EN forced to GND or V , T = +25°C
1.20
-0.5
1.7
2.20
+0.5
V
EN
µA
EN
DD
A
V
0.4
-
CC
High (5V V )
DD
SKIP Quad-Level Input Logic
Levels
Mid (3.3V)
Ref (2.0V)
3.0
1.7
3.6
2.3
0.4
+2
V
V
SKIP
Low (GND)
SKIP forced to GND to V
SKIP Logic-Input Current
I
-2
µA
SKIP
DD
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V = 12V, V
= V
= V = 5V, REFIN = ILIM = REF, SKIP = GND. T = -41°C to +85°C, unless otherwise
CC EN A
IN
DD
specified.) (Note 1)
PARAMETER
PWM CONTROLLER
Input Voltage Range
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
2
26
V
IN
Quiescent Supply Current (V
)
DD
I
+ I
FB forced above REFIN
1.2
mA
DD
CC
R
TON
R
TON
R
TON
= 97.5kΩ (600kHz)
= 200kΩ (300kHz)
= 302.5kΩ (200kHz)
115
250
348
163
306
486
V
V
= 12V
= 1.0V
IN
On-Time
t
ns
ON
FB
(Note 3)
4
_______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V
= V
= V = 5V, REFIN = ILIM = REF, SKIP = GND. T = -41°C to +85°C, unless otherwise
CC EN A
IN
DD
specified.) (Note 1)
PARAMETER
Minimum Off-Time
SYMBOL
CONDITIONS
MIN
MAX
UNITS
t
(Note 3)
350
ns
V
OFF(MIN)
REFIN Voltage Range
FB Voltage Range
V
(Note 2)
(Note 2)
0
0
V
V
REFIN
REF
REF
V
V
V
FB
FB
V
V
V
= 0.5V
= 1.0V
= 2.0V
0.49
0.51
1.01
REFIN
REFIN
REFIN
Measured at FB,
FB Voltage Accuracy
V
V
= 2V to 26V,
0.99
IN
SKIP = V
DD
1.985
2.015
REFERENCE
Reference Voltage
FAULT DETECTION
V
V
= 4.5V to 5.5V
DD
1.985
250
2.015
350
V
REF
With respect to the internal target voltage
(error comparator threshold) rising edge;
hysteresis = 50mV
Output Overvoltage-Protection
Trip Threshold
OVP
UVP
mV
mV
With respect to the internal target voltage
(error comparator threshold);
falling edge; hysteresis = 50mV
Output Undervoltage-Protection
Trip Threshold
-240
80
-160
Output Undervoltage
Fault-Propagation Delay
t
FB forced 25mV below trip threshold
400
0.4
µs
V
UVP
PGOOD Output Low Voltage
I
= 3mA
SINK
V
Undervoltage Lockout
Rising edge, PWM disabled below this level,
hysteresis = 100mV
CC
V
3.95
4.45
V
UVLO(VCC)
Threshold
CURRENT LIMIT
ILIM Input Range
0.4
17
90
17
V
V
REF
V
= 0.4V
23
ILIM
Current-Limit Threshold
V
mV
kHz
ILIMIT
ILIM = REF (2.0V)
SKIP = open (3.3V), V = V
110
Ultrasonic Frequency
+ 50mV
REFIN
FB
GATE DRIVERS
Low state (pulldown)
High state (pullup)
3.5
3.5
4
BST - LX forced
to 5V
DH Gate Driver On-Resistance
DL Gate Driver On-Resistance
R
Ω
ON(DH)
High state (pullup)
R
Ω
Ω
ON(DL)
Low state (pulldown)
= 10mA, V = 5V
2
Internal BST Switch On-Resistance
R
I
7
BST
BST
DD
_______________________________________________________________________________________
5
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V = 12V, V
= V
= V = 5V, REFIN = ILIM = REF, SKIP = GND. T = -41°C to +85°C, unless otherwise
CC EN A
IN
DD
specified.) (Note 1)
PARAMETER
INPUTS AND OUTPUTS
EN Logic-Input Threshold
SYMBOL
CONDITIONS
MIN
MAX
UNITS
V
EN rising edge hysteresis = 450mV (typ)
1.20
2.20
V
EN
V
0.4
-
CC
High (5V V )
DD
MAX8792
SKIP Quad-Level Input Logic
Levels
V
Mid (3.3V)
Ref (2.0V)
3.0
1.7
3.6
2.3
0.4
V
SKIP
Low (GND)
Note ±: Limits are 100% production tested at T = +25°C. Maximum and minimum limits over temperature are guaranteed by
A
design and characterization.
Note 2: The 0 to 0.5V range is guaranteed by design, not production tested.
Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, V
= 5V,
BST
and a 250pF capacitor connected from DH to LX. Actual in-circuit times can differ due to MOSFET switching speeds.
Typical Operating Characteristics
(MAX8792 Circuit of Figure 1, V = 12V, V
IN
= 5V, SKIP = GND, R
= 200kΩ, T = +25°C, unless otherwise noted.)
TON
A
DD
1.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
1.5V OUTPUT EFFICIENCY
vs. LOAD CURRENT
1.5V OUTPUT VOLTAGE
vs. LOAD CURRENT
100
100
90
80
70
60
50
40
30
20
1.54
1.52
1.50
1.48
7V
SKIP MODE
90
12V
80
LOW-NOISE
MODE
70
20V
60
50
40
SKIP MODE
PWM MODE
LOW-NOISE
MODE
PWM MODE
30
20
SKIP MODE
PWM MODE
0.01
0.1
1
10
0.01
0.1
1
10
0
2
4
6
8
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
6
_______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Typical Operating Characteristics (continued)
(MAX8792 Circuit of Figure 1, V = 12V, V
IN
= 5V, SKIP = GND, R
= 200kΩ, T = +25°C, unless otherwise noted.)
TON
A
DD
1.05V OUTPUT EFFICIENCY
1.05V OUTPUT EFFICIENCY
vs. LOAD CURRENT
1.05V OUTPUT VOLTAGE
vs. LOAD CURRENT
vs. LOAD CURRENT
100
100
90
80
70
60
50
40
30
20
1.07
1.06
1.05
1.04
1.03
SKIP MODE
7V
90
80
LOW-NOISE
MODE
70
20V
12V
60
SKIP MODE
PWM MODE
50
40
LOW-NOISE
MODE
PWM MODE
30
20
SKIP MODE
PWM MODE
0.01
0.01
6
0.1
1
10
10
24
0.01
0.1
1
10
0
2
4
6
8
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
SWITCHING FREQUENCY
vs. LOAD CURRENT
PWM MODE SWITCHING FREQUENCY
vs. INPUT VOLTAGE
SWITCHING FREQUENCY
vs. TEMPERATURE
350
300
250
200
150
100
50
330
320
300
I
= 5A
LOAD
PWM MODE
I
= 10A
310
LOAD
300
290
280
270
260
250
240
290
280
270
NO LOAD
I
= 5A
LOAD
LOW-NOISE
MODE
SKIP MODE
1
0
0.1
6
10
14
18
22
-40 -20
0
20 40 60 80 100
LOAD CURRENT (A)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
MAXIMUM OUTPUT CURRENT
vs. INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs. TEMPERATURE
NO-LOAD SUPPLY CURRENT I
vs. INPUT VOLTAGE
BIAS
13.6
13.5
13.4
13.3
20
19
18
17
16
14
12
10
8
WITHOUT TEMPERATURE
COMPENSATION
R4 = R5 = 49.9kΩ
PWM MODE
16
15
14
13
WITH
TEMPERATURE
COMPENSATION
(FIGURE 1)
13.2
13.1
13.0
12.9
6
LOW-NOISE MODE
SKIP MODE
4
12
11
10
2
0
9
12
15
18
21
-40 -20
0
20
40
60 80 100
6
9
12
15
18
21
24
INPUT VOLTAGE (V)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Typical Operating Characteristics (continued)
(MAX8792 Circuit of Figure 1, V = 12V, V
= 5V, SKIP = GND, R
= 200kΩ, T = +25°C, unless otherwise noted.)
TON
A
IN
DD
NO-LOAD SUPPLY CURRENT I
vs. INPUT VOLTAGE
REF OUTPUT VOLTAGE
vs. LOAD CURRENT
IN
REFIN-TO-FB OFFSET
VOLTAGE DISTRIBUTION
100
10
1
2.02
2.01
2.00
1.99
50
SAMPLE SIZE = 100
+85°C
+25°C
40
30
PWM MODE
MAX8792
LOW-NOISE MODE
20
10
0
0.1
SKIP MODE
0.01
1.98
6
9
12
15
18
21
24
-10
0
10 20 30 40 50 60 70 80 90 100 110
INPUT VOLTAGE (V)
LOAD CURRENT (μA)
OFFSET VOLTAGE (mV)
20V ILIM THRESHOLD
VOLTAGE DISTRIBUTION
SOFT-START WAVEFORM
SOFT-START WAVEFORM
(LIGHT LOAD)
(HEAVY LOAD)
MAX17016 toc17
MAX17016 toc18
50
40
30
20
10
0
SAMPLE SIZE = 100
+85°C
+25°C
5V
A
5V
A
B
0
5V
0
5V
B
0
0
1.5V
1.5V
C
D
C
D
0
8A
0
0
0
200μs/div
200μs/div
A. SHDN, 5V/div
B. PWRGD, 5V/div
C. V , 1V/div
B. INDUCTOR CURRENT,
A. SHDN, 5V/div
B. PWRGD, 5V/div
C. V , 1V/div
OUT
B. INDUCTOR CURRENT,
OUT
ILIM THRESHOLD VOLTAGE (mV)
10A/div
10A/div
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
SHUTDOWN WAVEFORM
(PWM MODE)
(SKIP MODE)
MAX17016 toc20
MAX17016 toc21
MAX17016 toc19
5V
A
B
8A
1A
8A
1A
0
A
B
C
A
B
C
5V
0
5V
1.55V
1.55V
C
D
E
0
1.5V
1.45V
8A
1.45V
10A
0A
0
0
1A
20μs/div
20μs/div
200μs/div
D. V , 1V/div
A. I
= 1A TO 8A, 10A/div C. INDUCTOR CURRENT,
A. I
= 1A TO 8A, 10A/div C. INDUCTOR CURRENT,
OUT
A. SHDN, 5V/div
B. PWRGD, 5V/div
C. DL, 5V/div
OUT
OUT
OUT
B. V , 50mV/div
10A/div
B. V , 50mV/div
10A/div
E. INDUCTOR CURRENT,
5A/div
OUT
8
_______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Typical Operating Characteristics (continued)
(MAX8792 Circuit of Figure 1, V = 12V, V
= 5V, SKIP = GND, R
= 200kΩ, T = +25°C, unless otherwise noted.)
TON
IN
DD
A
OUTPUT OVERLOAD WAVEFORM
(UVP ENABLED)
OUTPUT OVERVOLTAGE WAVEFORM
MAX17016 toc23
MAX17016 toc22
14A
1.5V
A
A
B
0
0
1.5V
5V
B
0
5V
0
C
D
5V
0
5V
C
0
0
100μs/div
200μs/div
A. INDUCTOR CURRENT,
10A/div
B. V , 1V/div
A. V , 1V/div
OUT
B. DL, 5V/div
C. PWRGD, 5V/div
C. DL, 5V/div
D. PWRGD, 5V/div
OUT
DYNAMIC OUTPUT-VOLTAGE TRANSITION
DYNAMIC OUTPUT-VOLTAGE TRANSITION
(PWM MODE)
(SKIP MODE)
MAX17016 toc24
MAX17016 toc25
1.5V
1.5V
1.05V
1.5V
A
B
A
B
1.05V
1.5V
1.05V
0
1.05V
10A
C
D
C
D
0
-10A
12V
12V
0
0
20μs/div
100μs/div
A. REFIN, 500mV/div
B. V , 200mV/div
C. INDUCTOR CURRENT,
10A/div
A. REFIN, 500mV/div
B. V , 200mV/div
C. INDUCTOR CURRENT,
10A/div
OUT
OUT
D. LX, 10V/div
D. LX, 10V/div
_______________________________________________________________________________________
9
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Pin Description
PIN
NAME
FUNCTION
Shutdown Control Input. Connect to V
for normal operation. Pull EN low to place the controller into
DD
its 2µA shutdown state. When disabled, the MAX8792 slowly ramps down the target/output voltage to
ground and after the target voltage reaches 0.1V, the controller forces both DH and DL low and
enters the low-power shutdown state. Toggle EN to clear the fault-protection latch.
1
EN
Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V).
2
3
V
DD
MAX8792
Bypass V
to power ground with a 1µF or greater ceramic capacitor.
DD
Low-Side Gate Driver. DL swings from GND to V . The controller pulls DL high when an output
DD
overvoltage fault is detected, overriding any negative current-limit condition that may be present. The
DL
MAX8792 forces DL low during V
UVLO and REFOK lockout conditions.
CC
4
5
LX
Inductor Connection. Connect LX to the switched side of the inductor as shown in Figure 1.
High-Side Gate Driver. DH swings from LX to BST. The MAX8792 pulls DH low whenever the
controller is disabled.
DH
Boost Flying-Capacitor Connection. Connect to an external 0.1µF 6V capacitor as shown in Figure 1.
The MAX8792 contains an internal boost switch/diode (see Figure 2).
6
BST
Switching Frequency-Setting Input. An external resistor between the input power source and TON
sets the switching period (T
= 1 / f ) according to the following equation:
SW
SW
⎛ V
⎞
FB
T
SW
= C
R
+ 6.5kΩ
TON TON
⎜
(
)
⎝
V
⎟
⎠
7
TON
OUT
where C
= 16.26pF and V = V
under normal operating conditions. If the TON current
REFIN
TON
FB
drops below 10µA, the MAX8792 shuts down, and enters a high-impedance state.
TON is high impedance in shutdown.
Feedback Voltage-Sense Connection. Connect directly to the positive terminal of the output capacitors
for output voltages less than 2V as shown in Figure 1. For fixed-output voltages greater than 2V,
connect REFIN to REF and use a resistive divider to set the output voltage (Figure 4). FB senses the
output voltage to determine the on-time for the high-side switching MOSFET.
8
9
FB
Current-Limit Threshold Adjustment. The current-limit threshold is 0.05 times (1/20) the voltage at
ILIM. Connect ILIM to a resistive divider (from REF) to set the current-limit threshold between 20mV
and 100mV (with 0.4V to 2V at ILIM).
ILIM
External Reference Input. REFIN sets the feedback regulation voltage (V = V
) of the MAX8792
REFIN
FB
using the resistor-divider connected between REF and GND. The MAX8792 includes an internal
window comparator to detect REFIN voltage transitions, allowing the controller to blank PGOOD and
the fault protection.
10
11
REFIN
REF
2V Reference Voltage. Bypass to analog ground using a 470pF to 10nF ceramic capacitor. The
reference can source up to 50µA for external loads.
Pulse-Skipping Control Input. This four-level input determines the mode of operation under normal
steady-state conditions and dynamic output-voltage transitions.
V
(5V) = forced-PWM operation.
DD
12
13
SKIP
REF (2V) = pulse-skipping mode with forced-PWM during transitions.
Open (3.3V)= ultrasonic mode (without forced-PWM during transitions).
GND = pulse-skipping mode (without forced-PWM during transitions).
5V Analog Supply Voltage. Internally connected to V
to analog ground using a 1µF ceramic capacitor.
through an internal 20Ω resistor. Bypass V
CC
DD
V
CC
±1 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Pin Description (continued)
PIN
NAME
FUNCTION
Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 200mV (typ)
below or 300mV (typ) above the target voltage (V
soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation.
PGOOD is blanked—forced high-impedance state—when a dynamic REFIN transition is detected.
), during soft-start and soft-shutdown. After the
REFIN
14
PGOOD
EP
(15)
Ground/Exposed Pad. Internally connected to the controller’s ground plane and substrate.
Connect directly to ground.
GND
R
TON
200kΩ
2
7
6
INPUT
7V TO 24V
5V BIAS
SUPPLY
V
V
TON
BST
DD
C1
1μF
C
IN
PWR
C
BST
PWR
C2
1μF
0.1μF
5
4
3
DH
LX
DL
13
14
L1
OUTPUT
1.05V/1.50V
10A (MAX)
CC
AGND
R10
100kΩ
C
OUT
PGOOD
PWR
PWR
1
MAX8792
ON OFF
GND/OPEN/REF/V
EN
8
12
FB
SKIP
CC
C3
NTC
100kΩ
B = 4250
1000pF
11
10
REF
AGND
R1
49.9kΩ
R4
68kΩ
9
REFIN
REF
ILIM
R2
54.9kΩ
R3
97.6kΩ
AGND
LO
R5
82kΩ
GND
(EP)
HI
AGND
PWR
AGND
AGND
SEE TABLE 1 FOR COMPONENT SELECTION.
Figure 1. MAX8792 Standard Application Circuit
in a notebook computer. See Table 1 for component
selections. Table 2 lists the component manufacturers.
Standard Application Circuits
The MAX8792 standard application circuit (Figure 1) gen-
erates a 1.5V or 1.05V output rail for general-purpose use
______________________________________________________________________________________ ±±
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Table ±. Component Selection ꢀor Standard Applications
V
OUT
= ±.5V/±.15V AT ±1A
(Figure ±)
V
OUT
= 3.3V AT 6A
(Figure 4)
V
OUT
= ±.5V/±.15V AT ±1A
(Figure 7)
COMPONENT
V
= 7V to 20V
V
= 7V to 20V
V
= 4V to 12V
IN
IN
IN
TON = 200kΩ (300kHz)
TON = 332kΩ (300kHz)
TON = 100kΩ (600kHz)
(2x) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2x) 10µF, 25V
Taiyo Yuden TMK432BJ106KM
(2x) 10µF 25V
Taiyo Yuden TMK432BJ106KM
Input Capacitor
Output Capacitor
Inductor
(2x) 330µF, 6mΩ
Panasonic EEFSX0D331XR
(1x) 330µF, 18mΩ
Sanyo 4TPE330MI
(2x) 330µF, 7mΩ
Nec-Tokin PSGD0E337M7
MAX8792
1.0µH, 3.25mΩ
Wurth 744 3552 100
3.3µH, 14mΩ
NEC-Tokin MPLC1040L3R3
0.68µH, 4.6mΩ
Coiltronics FP3-R68
Fairchild (1x) FDS8690
8.6mΩ/11.4mΩ (typ/max)
Fairchild (1x) FDS8690
8.6mΩ/11.4mΩ (typ/max)
High-Side MOSFET
Low-Side MOSFET
Siliconix (1x) Si4916DY
N
= 18mΩ/22mΩ (typ/max)
H
Fairchild (1x) FDS8670
4.2mΩ/5.0mΩ (typ/max)
Fairchild (1x) FDS8670
4.2mΩ/5.0mΩ (typ/max)
N = 15mΩ/18mΩ (typ/max)
L
Table 2. Component Suppliers
MANUFACTURER
Panasonic
Pulse
WEBSITE
MANUFACTURER
WEBSITE
www.panasonic.com
AVX
www.avxcorp.com
www.pulseeng.com
www.renesas.com
www.secc.co.jp
BI Technologies
www.bitechnologies.com
Renesas
Sanyo
Central
Semiconductor
www.centralsemi.com
www.cooperet.com
Siliconix (Vishay)
Sumida
www.vishay.com
Coiltronics
www.sumida.com
www.t-yuden.com
www.component.tdk.com
www.tokoam.com
www.we-online.com
Fairchild
Semiconductor
www.fairchildsemi.com
Taiyo Yuden
TDK
International Rectifier
Kemet
www.irf.com
TOKO
www.kemet.com
www.nec-tokin.com
Wurth
NEC Tokin
+5V Bias Supply (V /V
)
CC DD
Detailed Description
The MAX8792 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s main 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator such as the MAX1615.
The MAX8792 step-down controller is ideal for the low-
duty-cycle (high-input voltage to low-output voltage)
applications required by notebook computers. Maxim’s
proprietary Quick-PWM pulse-width modulator in the
MAX8792 is specifically designed for handling fast load
steps while maintaining a relatively constant operating
frequency and inductor operating point over a wide
range of input voltages. The Quick-PWM architecture
circumvents the poor load-transient timing problems of
fixed-frequency, current-mode PWMs while also avoid-
ing the problems caused by widely varying switching
frequencies in conventional constant-on-time (regard-
less of input voltage) PFM control schemes.
The 5V bias supply powers both the PWM controller
and internal gate-drive power, so the maximum current
drawn is determined by:
I
= I + f
Q = 2mA to 20mA (typ)
SW G
BIAS
Q
±2 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
relies on the output filter capacitor’s ESR to act as a cur-
rent-sense resistor, so the output ripple voltage provides
the PWM ramp signal. The control algorithm is simple:
the high-side switch on-time is determined solely by a
one-shot whose pulse width is inversely proportional to
Free-Running Constant-On-Time PWM
Controller with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant on-time, current-mode regulator
with voltage feed-forward (Figure 2). This architecture
TON
IN
t
OFF(MIN)
BST
ON-TIME
COMPUTE
TRIG
Q
FB
ONE-SHOT
DH
LX
S
R
Q
t
ON
TRIG
Q
ONE-SHOT
INTEGRATOR
(CCV)
ERROR
AMPLIFIER
V
DD
DL
S
R
Q
GND
SKIP
FB
QUAD-
LEVEL
DECODE
BLANK
EA + 0.3V
ZERO CROSSING
PGOOD
VALLEY CURRENT LIMIT
AND FAULT
PROTECTION
ILIM
REF
EA - 0.2V
V
CC
2V
REF
EN
SOFT-
START/STOP
PGOOD
EA
REFIN
BLANK
DYNAMIC OUTPUT
TRANSITION DETECTION
MAX8792
Figure 2. MAX8792 Functional Block Diagram
______________________________________________________________________________________ ±3
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
input voltage and directly proportional to output volt-
age. Another one-shot sets a minimum off-time (200ns
typ). The on-time one-shot is triggered if the error com-
parator is low, the low-side switch current is below the
valley current-limit threshold, and the minimum off-time
one-shot has timed out.
Power-Up Sequence (POR, UVLO)
The MAX8792 is enabled when EN is driven high and
the 5V bias supply (V ) is present. The reference
DD
powers up first. Once the reference exceeds its UVLO
threshold, the internal analog blocks are turned on and
masked by a 50µs one-shot delay in order to allow the
bias circuitry and analog blocks enough time to settle
to their proper states. With the control circuitry reliably
powered up, the PWM controller may begin switching.
On-Time One-Shot
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to input and output voltage. The high-side
switch on-time is inversely proportional to the input volt-
age as sensed by the TON input, and proportional to
the feedback voltage as sensed by the FB input:
MAX8792
Power-on reset (POR) occurs when V
rises above
CC
approximately 3V, resetting the fault latch and prepar-
ing the controller for operation. The V UVLO circuitry
CC
inhibits switching until V
rises above 4.25V. The con-
CC
troller powers up the reference once the system
enables the controller, V exceeds 4.25V, and EN is
CC
On-Time (t ) = T
(V / V )
SW FB IN
ON
driven high. With the reference in regulation, the con-
troller ramps the output voltage to the target REFIN volt-
age with a 1mV/µs slew rate:
where T
TON
(switching period) is set by the resistance
SW
(R
) between TON and V . This algorithm results in
IN
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. Connect a resis-
V
V
FB
FB
t
=
=
START
1mV/μs 1V/ms
tor (R
) between TON and V to set the switching
IN
TON
period T
= 1 / f
:
SW
SW
The soft-start circuitry does not use a variable current
limit, so full output current is available immediately.
PGOOD becomes high impedance approximately
200µs after the target REFIN voltage has been reached.
The MAX8792 automatically uses pulse-skipping mode
during soft-start and uses forced-PWM mode during
soft-shutdown, regardless of the SKIP configuration.
⎛ V
⎞
FB
T
= C
R
+ 6.5kΩ
TON TON
⎜
(
)
⎝
V
SW
⎟
⎠
OUT
where C
= 16.26pF. When used with unity-gain feed-
= V ), a 96.75kΩ to 303.25kΩ corresponds
FB
TON
OUT
back (V
to switching periods of 167ns (600kHz) to 500ns
(200kHz), respectively. High-frequency (600kHz) opera-
tion optimizes the application for the smallest compo-
nent size, trading off efficiency due to higher switching
losses. This may be acceptable in ultra-portable devices
where the load currents are lower and the controller is
powered from a lower voltage supply. Low-frequency
(200kHz) operation offers the best overall efficiency at
the expense of component size and board space.
For automatic startup, the battery voltage should be
present before V . If the controller attempts to bring
CC
the output into regulation without the battery voltage
present, the fault latch trips. The controller remains shut
down until the fault latch is cleared by toggling EN or
cycling the V
power supply below 0.5V.
CC
If the V
voltage drops below 4.25V, the controller
CC
assumes that there is not enough supply voltage to
make valid decisions. To protect the output from over-
voltage faults, the controller shuts down immediately
and forces a high-impedance output (DL and DH
pulled low).
For continuous conduction operation, the actual switching
frequency can be estimated by:
V
+ V
DROP1
FB
f
=
SW
t
(V + V
)
ON IN
DROP2
Shutdown
When the system pulls EN low, the MAX8792 enters
low-power shutdown mode. PGOOD is pulled low
immediately, and the output voltage ramps down with a
1mV/µs slew rate:
where V
is the sum of the parasitic voltage drops
DROP1
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board (PCB) resistances;
V
is the sum of the resistances in the charging
DROP2
path, including the high-side switch, inductor, and PCB
resistances; and t
MAX8792.
is the on-time calculated by the
V
V
FB
ON
FB
t
=
=
SHDN
1mV/μs 1V/ms
±4 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Slowly discharging the output capacitors by slewing
is higher than the trip level by 50% of the output ripple
the output over a long period of time (typically 0.5ms to
2ms) keeps the average negative inductor current low
(damped response), thereby preventing the negative
output-voltage excursion that occurs when the con-
troller discharges the output quickly by permanently
turning on the low-side MOSFET (underdamped
response). This eliminates the need for the Schottky
diode normally connected between the output and
ground to clamp the negative output-voltage excursion.
After the controller reaches the zero target, the
MAX8792 shuts down completely—the drivers are dis-
abled (DL and DH pulled low)—the reference turns off,
and the supply currents drop to about 0.1µA (typ).
voltage. In discontinuous conduction (SKIP = GND and
I
< I ), the output voltage has a DC regu-
LOAD(SKIP)
OUT
lation level higher than the error-comparator threshold
by approximately 1.5% due to slope compensation.
When SKIP is pulled to GND, the MAX8792 remains in
pulse-skipping mode. Since the output is not able to
sink current, the timing for negative dynamic output-volt-
age transitions depends on the load current and output
capacitance. Letting the output voltage drift down is typ-
ically recommended in order to reduce the potential for
audible noise since this eliminates the input current
surge during negative output-voltage transitions.
Ultrasonic Mode (SKIP = Open = 3.3V)
Leaving SKIP unconnected activates a unique pulse-
skipping mode with a minimum switching frequency of
18kHz. This ultrasonic pulse-skipping mode eliminates
audio-frequency modulation that would otherwise be
present when a lightly loaded controller automatically
skips pulses. In ultrasonic mode, the controller automati-
cally transitions to fixed-frequency PWM operation when
the load reaches the same critical conduction point
When a fault condition—output UVP or thermal shut-
down—activates the shutdown sequence, the protection
circuitry sets the fault latch to prevent the controller from
restarting. To clear the fault latch and reactivate the
controller, toggle EN or cycle V
power below 0.5V.
CC
The MAX8792 automatically uses pulse-skipping mode
during soft-start and uses forced-PWM mode during
soft-shutdown, regardless of the SKIP configuration.
(I
) that occurs when normally pulse skipping.
LOAD(SKIP)
Modes of Operation
An ultrasonic pulse occurs when the controller detects
that no switching has occurred within the last 33µs.
Once triggered, the ultrasonic controller pulls DL high,
turning on the low-side MOSFET to induce a negative
inductor current (Figure 3). After the inductor current
reaches the negative ultrasonic current threshold, the
controller turns off the low-side MOSFET (DL pulled low)
Forced-PWM Mode (SKIP = V
)
DD
The low-noise, forced-PWM mode (SKIP = V ) dis-
DD
ables the zero-crossing comparator, which controls the
low-side switch on-time. This forces the low-side gate-
drive waveform to constantly be the complement of the
high-side gate-drive waveform, so the inductor current
reverses at light loads while DH maintains a duty factor
of V
/V . The benefit of forced-PWM mode is to
OUT IN
keep the switching frequency fairly constant. However,
forced-PWM operation comes at a cost: the no-load 5V
bias current remains between 10mA to 50mA, depend-
ing on the switching frequency.
33μs (typ)
INDUCTOR
CURRENT
The MAX8792 automatically always uses forced-PWM
operation during shutdown, regardless of the SKIP
configuration.
Automatic Pulse-Skipping Mode
(SKIP = GND or 3.3V)
ZERO-CROSSING
DETECTION
In skip mode (SKIP = GND or 3.3V), an inherent auto-
matic switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. The zero-crossing comparator threshold
is set by the differential across LX to GND.
0
I
SONIC
ON-TIME (t
)
ON
DC output-accuracy specifications refer to the thresh-
old of the error comparator. When the inductor is in
continuous conduction, the MAX8792 regulates the val-
ley of the output ripple, so the actual DC output voltage
Figure 3. Ultrasonic Waveform
______________________________________________________________________________________ ±5
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
and triggers a constant on-time (DH driven high). When
Integrated Output Voltage
The MAX8792 regulates the valley of the output ripple,
so the actual DC output voltage is higher than the
slope-compensated target by 50% of the output ripple
voltage. Under steady-state conditions, the MAX8792’s
internal integrator corrects for this 50% output ripple-
voltage error, resulting in an output voltage that is
accurately defined by the following equation:
the on-time has expired, the controller reenables the
low-side MOSFET until the controller detects that the
inductor current dropped below the zero-crossing
threshold. Starting with a DL pulse greatly reduces the
peak output voltage when compared to starting with a
DH pulse.
The output voltage at the beginning of the ultrasonic
pulse determines the negative ultrasonic current
threshold, resulting in the following equation:
⎛ V
⎞
MAX8792
RIPPLE
V
FB
= V
+
REFIN
⎜
⎟
⎠
⎝
A
CCV
V
=I R = V
− V
× 0.7
(
)
ISONIC L CS
REFIN
FB
where V
is the nominal feedback voltage, A
is
REFIN
CCV
the integrator’s gain, and V
is the feedback rip-
RIPPLE
where V > V
and R is the current-sense resis-
CS
FB
REFIN
ple voltage (V
= ESR x ΔI
as described
RIPPLE
INDUCTOR
tance seen across GND to LX.
in the Output Capacitor Selection section). Therefore,
the feedback-voltage accuracy specification provided
in the Electrical Characteristics table actually refers to
the integrated feedback threshold and primarily reflects
the offset voltage of the integrator amplifier.
Valley Current-Limit Protection
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that senses the inductor current
through the low-side MOSFET. If the current through the
low-side MOSFET exceeds the valley current-limit thresh-
old, the PWM controller is not allowed to initiate a new
cycle. The actual peak current is greater than the valley
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore, the exact current-limit char-
acteristic and maximum load capability are a function of
the inductor value and input voltage. When combined
with the undervoltage protection circuit, this current-limit
method is effective in almost every circumstance.
Dynamic Output Voltages
The MAX8792 regulates OUT to the voltage set at
REFIN. By changing the voltage at REFIN (Figure 1),
the MAX8792 can be used in applications that require
dynamic output-voltage changes between two set
points. For a step-voltage change at REFIN, the rate of
change of the output voltage is limited either by the
internal 8mV/µs slew-rate circuit or by the component
selection—inductor current ramp, the total output
capacitance, the current limit, and the load during the
transition—whichever is slower. The total output capac-
itance determines how much current is needed to
change the output voltage, while the inductor limits the
current ramp rate. Additional load current slows down
the output voltage change during a positive REFIN volt-
age change, and speeds up the output voltage change
during a negative REFIN voltage change.
In forced-PWM mode, the MAX8792 also implements a
negative current limit to prevent excessive reverse
inductor currents when V
negative current-limit threshold is set to approximately
120% of the positive current limit.
is sinking current. The
OUT
±6 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
R
TON
332kΩ
2
7
6
INPUT
7V TO 24V
5V BIAS
SUPPLY
V
TON
BST
DD
C1
1μF
C
IN
PWR
C
BST
C2
1μF
PWR
0.1μF
5
4
3
DH
LX
DL
13
V
CC
L1
OUTPUT
3.3V
5A (MAX)
AGND
R10
100kΩ
C
OUT
R6
14
1
PGOOD
EN
13.0kΩ
PWR
PWR
ON OFF
GND/OPEN/REF/V
8
FB
12
SKIP
CC
R7
20.0kΩ
C3
1000pF
MAX8792
11
10
REF
AGND
R4
0Ω
AGND
9
REFIN
ILIM
REF
R5
OPEN
GND
(EP)
AGND
PWR
AGND
SEE TABLE 1 FOR COMPONENT SELECTION.
Figure 4. High Output-Voltage Application Using a Feedback Divider
Output Voltages Greater than 2V
Although REFIN is limited to a 0 to 2V range, the out-
put-voltage range is unlimited since the MAX8792 uti-
lizes a high-impedance feedback input (FB). By adding
a resistive voltage-divider from the output to FB to ana-
log ground (Figure 4), the MAX8792 supports output
voltages above 2V. However, the controller also uses
FB to determine the on-time, so the voltage-divider
influences the actual switching frequency, as detailed
in the On-Time One-Shot section.
The MAX8792 disables the integrator by connecting the
amplifier inputs together at the beginning of all downward
REFIN transitions done in pulse-skipping mode. The inte-
grator remains disabled until 20µs after the transition is
completed (the internal target settles) and the output is in
regulation (edge detected on the error comparator).
Power-Good Outputs (PGOOD)
and Fault Protection
PGOOD is the open-drain output that continuously
monitors the output voltage for undervoltage and over-
voltage conditions. PGOOD is actively held low in shut-
down (EN = GND), during soft-start, and soft-shutdown.
Approximately 200µs (typ) after the soft-start termi-
nates, PGOOD becomes high impedance as long as
the feedback voltage is above the UVP threshold
(REFIN - 200mV) and below the OVP threshold (REFIN
+ 300mV). PGOOD goes low if the feedback voltage
drops 200mV below the target voltage (REFIN) or rises
300mV above the target voltage (REFIN), or the SMPS
controller is shut down. For a logic-level PGOOD output
Internal Integration
An integrator amplifier forces the DC average of the FB
voltage to equal the target voltage. This internal amplifi-
er integrates the feedback voltage and provides a fine
adjustment to the regulation voltage (Figure 2), allowing
accurate DC output-voltage regulation regardless of the
compensated feedback ripple voltage and internal
slope-compensation variation. The integrator amplifier
has the ability to shift the output voltage by 55mV (typ).
______________________________________________________________________________________ ±7
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
TARGET
+ 300mV
TARGET
- 200mV
POWER-GOOD AND FAULT PROTECTION
FB
EN
OVP
SOFT-START
COMPLETE
MAX8792
UVP
OVP ENABLED
FAULT
ONE-
SHOT
200μs
FAULT
LATCH
POWER-GOOD
IN
CLK
OUT
Figure 5. Power-Good and Fault Protection
voltage, connect an external pullup resistor between
Thermal-Fault Protection (TSHDN)
PGOOD and V . A 100kΩ pullup resistor works well in
The MAX8792 features a thermal fault-protection circuit.
When the junction temperature rises above +160°C, a
thermal sensor activates the fault latch, pulls PGOOD
low, and shuts down the controller. Both DL and DH are
DD
most applications. Figure 5 shows the power-good and
fault-protection circuitry.
Overvoltage Protection (OVP)
When the internal feedback voltage rises 300mV above
the target voltage and OVP is enabled, the OVP compara-
tor immediately pulls DH low and forces DL high, pulls
PGOOD low, sets the fault latch, and disables the SMPS
pulled low. Toggle EN or cycle V
power below V
CC
CC
POR to reactivate the controller after the junction tem-
perature cools by 15°C.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving mode-
rate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
controller. Toggle EN or cycle V
power below the V
CC
CC
POR to clear the fault latch and restart the controller.
Undervoltage Protection (UVP)
When the feedback voltage drops 200mV below the
target voltage (REFIN), the controller immediately pulls
PGOOD low and triggers a 200µs one-shot timer. If the
feedback voltage remains below the undervoltage fault
threshold for the entire 200µs, then the undervoltage
fault latch is set and the SMPS begins the shutdown
sequence. When the internal target voltage drops
below 0.1V, the MAX8792 forces DL low. Toggle EN or
seen in notebook applications, where a large V
-
IN
V
differential exists. The high-side gate driver (DH)
OUT
sources and sinks 1.5A, and the low-side gate driver
(DL) sources 1.0A and sinks 2.4A. This ensures robust
gate drive for high-current applications. The DH floating
high-side MOSFET driver is powered by internal boost
switch charge pumps at BST, while the DL synchro-
nous-rectifier driver is powered directly by the 5V bias
supply (V ).
DD
cycle V
power below V
POR to clear the fault latch
CC
CC
and restart the controller.
±8 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Adaptive dead-time circuits monitor the DL and DH dri-
vers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
(R )*
BST
BST
INPUT (V )
IN
C
BST
DH
LX
N
H
There must be a low-resistance, low-inductance path
from the DL and DH drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; other-
wise, the sense circuitry in the MAX8792 interprets the
MOSFET gates as “off” while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
L
C
BYP
V
DD
The internal pulldown transistor that drives DL low is
robust, with a 0.9Ω (typ) on-resistance. This helps pre-
vent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs
when the inductor node (LX) quickly switches from
DL
N
L
(C )*
NL
PGND
ground to V . Applications with high-input voltages and
IN
long inductive driver traces may require rising LX edges
do not pull up the low-side MOSFETs’ gate, causing
shoot-through currents. The capacitive coupling
between LX and DL created by the MOSFET’s gate-to-
(R )* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
BST
THE SWITCHING NODE RISE TIME.
(C )* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
NL
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
drain capacitance (C
), gate-to-source capacitance
RSS
(C
- C
), and additional board parasitics should
ISS
RSS
not exceed the following minimum threshold:
Figure 6. Gate Drive Circuit
⎛ C
⎞
RSS
V
> V
IN
⎜
GS(TH)
⎟
⎠
Quick-PWM Design Procedure
⎝
C
ISS
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple-current ratio). The prima-
ry design trade-off lies in choosing a good switching fre-
quency and inductor operating point, and the following
four factors dictate the rest of the design:
Typically, adding a 4700pF between DL and power
ground (C in Figure 6), close to the low-side
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
NL
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow low-
side MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, elimi-
nating the shoot-through currents without degrading
•
Input voltage range: The maximum value
(V ) must accommodate the worst-case input
IN(MAX)
supply voltage allowed by the notebook’s AC
adapter voltage. The minimum value (V
)
IN(MIN)
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selec-
tor switches. If there is a choice at all, lower input
voltages result in better efficiency.
the turn-off time (R
in Figure 6). Slowing down the
BST
•
Maximum load current: There are two values to
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
consider. The peak load current (I
)
LOAD(MAX)
determines the instantaneous component stresses
and filtering requirements, and thus drives output
______________________________________________________________________________________ ±9
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
which can be calculated from the on-time and minimum
off-time. The worst-case output sag voltage can be
determined by:
ous load current (I
) determines the thermal
LOAD
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components. Most notebook loads gener-
⎡
⎢
⎣
⎤
⎥
⎦
2
⎛ V
⎝
T
⎞
OUT SW
V
L ΔI
+ t
OFF(MIN)
(
)
LOAD(MAX)
⎜
⎟
⎠
IN
V
=
SAG
ally exhibit I
= I
x 80%.
LOAD
LOAD(MAX)
⎡
⎢
⎤
⎛
⎞
V
IN
− V
T
)
(
OUT SW
⎥
2C
V
− t
OFF(MIN)
⎟
OUT OUT
•
•
Switching ꢀrequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
⎜
V
⎢
IN
⎥
⎝
⎠
⎣
⎦
MAX8792
where t
is the minimum off-time (see the Electrical
OFF(MIN)
Characteristics table).
are proportional to frequency and V 2. The opti-
IN
mum frequency is also a moving target, due to
rapid improvements in MOSFET technology that are
making higher frequencies more practical.
The amount of overshoot due to stored inductor energy
when the load is removed can be calculated as:
2
ΔI
L
(
≈
)
LOAD(MAX)
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values pro-
vide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction bene-
fit. The optimum operating point is usually found
between 20% and 50% ripple current.
V
SOAR
2C
V
OUT OUT
Setting the Valley Current Limit
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The val-
ley of the inductor current occurs at I
minus
LOAD(MAX)
half the inductor ripple current (ΔIL); therefore:
ΔI
2
L
I
>I
−
LIMIT(LOW) LOAD(MAX)
where I
equals the minimum current-limit
LIMIT(LOW)
threshold voltage divided by the low-side MOSFETs on-
reistance (R ).
Inductor Selection
DS(ON)
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
The valley current-limit threshold is precisely 1/20 the
voltage seen at ILIM. Connect a resistive divider from
REF to ILIM to analog ground (GND) in order to set a
fixed valley current-limit threshold. The external 400mV to
2V adjustment range corresponds to a 20mV to 100mV
valley current-limit threshold. When adjusting the current-
limit threshold, use 1% tolerance resistors and a divider
current of approximately 5µA to 10µA to prevent signifi-
cant inaccuracy in the valley current-limit tolerance.
⎛
⎜
⎞
V
− V
⎛ V
OUT
⎝
V
IN
⎞
IN
OUT
L =
⎜
⎟
⎠
⎟
f
I
LIR
⎝ SW LOAD(MAX)
⎠
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
The MAX8792 uses the low-side MOSFET’s on-resis-
inductor current (I
):
PEAK
tance as the current-sense element (R
DS(ON)
=
SENSE
ΔI
2
R
). Therefore, special attention must be made to
L
I
=I
+
PEAK LOAD(MAX)
the tolerance and thermal variation of the on-resistance.
Use the worst-case maximum value for R from
DS(ON)
the MOSFET data sheet, and add some margin for the
rise in R with temperature. A good general rule is
to allow 0.5% additional resistance for each °C of tem-
perature rise, which must be included in the design
margin unless the design includes an NTC thermistor in
the ILIM resistive voltage-divider to thermally compen-
sate the current-limit threshold.
Transient Response
DS(ON)
The inductor ripple current impacts transient-response
performance, especially at low V - V
differentials.
IN
OUT
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output fil-
ter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty factor,
21 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Foldback Current Limit
In core and chipset converters and other applications
where the output is subject to large load transients, the
output capacitor’s size typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
Including an additional resistor between ILIM and the
output automatically creates a current-limit threshold that
folds back as the output voltage drops (see Figure 7).
The foldback current limit helps limit the inductor cur-
rent under fault conditions, but must be carefully
designed in order to provide reliable performance
under normal conditions. The current-limit threshold
must not be set too low, or the controller will not reliably
power up. To ensure the controller powers up properly,
V
STEP
R
+R
≤
(
)
ESR
PCB
ΔI
LOAD(MAX)
In low-power applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capaci-
tor’s ESR. The maximum ESR to meet ripple require-
ments is:
the minimum current-limit threshold (when V
= 0V)
OUT
must always be greater than the maximum load during
startup (which at least consists of leakage currents),
plus the maximum current required to charge the out-
put capacitors:
I
= C
x 1mV/µs + I
OUT LOAD(START)
START
Output Capacitor Selection
⎡
⎢
⎣
⎤
⎥
⎦
V
− V
f
L
IN SW
R
ESR
≤
V
RIPPLE
The output filter capacitor must have low enough effec-
tive series resistance (ESR) to meet output ripple and
load-transient requirements. Additionally, the ESR
impacts stability requirements. Capacitors with a high
ESR value (polymers/tantalums) will not need additional
external compensation components.
V
IN
V
)
(
OUT OUT
⎢
⎥
where f
is the switching frequency.
SW
R
TON
100kΩ
2
7
6
INPUT
4V TO 12V
5V BIAS
SUPPLY
V
TON
BST
DD
C1
1μF
C
IN
PWR
CBST
0.1μF
PWR
C2
1μF
5
4
3
DH
LX
DL
13
14
L1
OUTPUT
1.50V 10A
1.05V 7A
V
CC
AGND
R10
100kΩ
C
OUT
PGOOD
PWR
PWR
1
MAX8792
ON OFF
GND/OPEN/REF/V
EN
8
12
FB
SKIP
CC
C3
1000pF
11
10
REF
R8
R5
100kΩ
AGND
R1
49.9kΩ
R4
100kΩ
9
REFIN
REF
ILIM
R2
54.9kΩ
R3
97.6kΩ
AGND
LO
GND
(EP)
100kΩ
HI
AGND
PWR
AGND
AGND
SEE TABLE 1 FOR COMPONENT SELECTION.
Figure 7. Standard Application with Foldback Current-Limit Protection
______________________________________________________________________________________ 2±
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
With most chemistries (polymer, tantalum, aluminum
electrolytic), the actual capacitance value required
relates to the physical size needed to achieve low ESR
and the chemistry limits of the selected capacitor tech-
nology. Ceramic capacitors provide low ESR, but the
capacitance and voltage rating (after derating) are
For a standard 300kHz application, the effective zero
frequency must be well below 95kHz, preferably below
50kHz. With these frequency requirements, standard
tantalum and polymer capacitors already commonly
used have typical ESR zero frequencies below 50kHz,
allowing the stability requirements to be achieved with-
out any additional current-sense compensation. In the
standard application circuit (Figure 1), the ESR needed
determined by the capacity needed to prevent V
SAG
and V
from causing problems during load tran-
SOAR
sients. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the
to support a 15mV
ripple is 15mV / (10A x 0.3) =
P-P
MAX8792
5mΩ. Two 330µF, 9mΩ polymer capacitors in parallel
provide 4.5mΩ (max) ESR and 1 / (2π x 330µF x 9mΩ)
= 53kHz ESR zero frequency.
rising load edge is no longer a problem (see the V
SAG
and V
equations in the Transient Response sec-
SOAR
tion). Thus, the output capacitor selection requires
carefully balancing capacitor chemistry limitations
(capacitance vs. ESR vs. voltage rating) and cost.
TON
BST
INPUT
C
IN
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the in-phase feedback ripple relative to the switching
frequency, which is typically dominated by the output
ESR. The boundary of instability is given by the following
equation:
PWR
DH
LX
DL
L1
OUTPUT
C
OUT
f
1
SW
π
≥
PWR
2πR
C
EFF OUT
MAX8792
PWR
R
EFF
=R
+R
+R
ESR
PCB COMP
FB
STABILITY REQUIREMENT
where C
is the total output capacitance, R
is the
OUT
ESR
GND
1
≥
R
C
total equivalent-series resistance of the output capaci-
tors, R is the parasitic board resistance between
ESR OUT
2f
SW
AGND
PCB
PWR
the output capacitors and feedback sense point, and
Figure 8. Standard Application with Output Polymer or Tantalum
R
is the effective resistance of the DC- or AC-cou-
COMP
pled current-sense compensation (see Figure 10).
TON
INPUT
PCB PARASITIC RESISTANCE
SENSE RESISTANCE FOR EVALUATION
C
IN
BST
PWR
DH
LX
L1
OUTPUT
C
LOAD
C
OUT
DL
PWR
PWR
R
COMP
PWR
MAX8792
OUTPUT VOLTAGE REMOTELY
SENSED NEAR POINT OF LOAD
100Ω
FB
GND
AGND
PWR
STABILITY REQUIREMENT
1
1
f
SW
≥
≥
C
COMP COMP
R
C
AND
R
ESR OUT
2f
SW
FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT
Figure 9. Remote-Sense Compensation for Stability and Noise Immunity
22 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Ceramic capacitors have a high ESR zero frequency,
The DC-coupling requires fewer external compensation
capacitors, but this also creates an output load line that
depends on the inductor’s DCR (parasitic resistance).
Alternatively, the current-sense information may be AC-
coupled, allowing stability to be dependent only on the
inductance value and compensation components and
eliminating the DC load line.
but applications with sufficient current-sense compen-
sation may still take advantage of the small size, low
ESR, and high reliability of the ceramic chemistry. Using
the inductor DCR, applications using ceramic output
capacitors may be compensated using either a DC
compensation or AC compensation method (Figure 10).
OPTION A: DC-COUPLED CURRENT-SENSE COMPENSATION
DC COMPENSATION
TON
<> FEWER COMPENSATION COMPONENTS
<> CREATES OUTPUT LOAD LINE
<> LESS OUTPUT CAPACITANCE REQUIRED
FOR TRANSIENT RESPONSE
INPUT
C
IN
BST
DH
LX
PWR
L
OUTPUT
C
OUT
R
SENA
DL
R
SENB
PWR
MAX8792
PWR
C
SEN
FB
GND
STABILITY REQUIREMENT
AGND
PWR
⎛
⎞
L
1
2f
SW
R
R
SENB DCR
C
OUT
⎟
≥
AND LOAD LINE =
⎜
R
||R
C
R
+R
SENB
(
)
SENA
SENB SEN
SENA
⎝
⎠
FEEDBACK RIPPLE IN-PHASE WITH INDUCTOR CURRENT
OPTION B: AC-COUPLED CURRENT-SENSE COMPENSATION
AC COMPENSATION
<> NOT DEPENDENT ON ACTUAL DCR VALUE
<> NO OUTPUT LOAD LINE
TON
INPUT
C
IN
BST
DH
LX
PWR
L
OUTPUT
C
OUT
R
SEN
DL
C
SEN
PWR
MAX8792
PWR
C
COMP
FB
R
COMP
GND
STABILITY REQUIREMENT
AGND
PWR
⎛
L
⎞
1
2f
SW
1
f
SW
C
≥
AND R ≥
C
OUT
COMP COMP
⎜
⎝
⎟
⎠
R
C
SEN SEN
FEEDBACK RIPPLE IN PHASE WITH INDUCTOR CURRENT
Figure 10. Feedback Compensation for Ceramic Output Capacitors
______________________________________________________________________________________ 23
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
When only using ceramic output capacitors, output
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
overshoot (V
) typically determines the minimum
SOAR
output capacitance requirement. Their relatively low
capacitance value may allow significant output over-
shoot when stepping from full-load to no-load condi-
tions, unless designed with a small inductance value
and high switching frequency to minimize the energy
transferred from the inductor to the capacitor during
load-step recovery.
The high-side MOSFET (N ) must be able to dissipate
H
the resistive losses plus the switching losses at both
V
and V
. Calculate both of these sums.
IN(MAX)
IN(MIN)
Ideally, the losses at V
should be roughly equal to
IN(MIN)
MAX8792
Unstable operation manifests itself in two related but
distinctly different ways: double pulsing and feedback-
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double pulsing is more annoying than
harmful, resulting in nothing worse than increased out-
put ripple. However, it can indicate the possible pres-
ence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
losses at V
, with lower losses in between. If the
are significantly higher than the losses
IN(MAX)
IN(MIN)
losses at V
at V
, consider increasing the size of N (reducing
IN(MAX)
H
R
but with higher C
). Conversely, if the losses
GATE
DS(ON)
at V
are significantly higher than the losses at
IN(MAX)
V
, consider reducing the size of N (increasing
IN(MIN)
R
H
to lower C
). If V does not vary over a
GATE IN
DS(ON)
wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible
on-resistance (R
), comes in a moderate-sized
DS(ON)
package (i.e., one or two 8-pin SOs, DPAK, or D2PAK),
and is reasonably priced. Make sure that the DL gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems may
occur (see the MOSFET Gate Drivers section).
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage-ripple envelope for over-
shoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N ), the worst-
H
case power dissipation due to resistance occurs at the
minimum input voltage:
Input Capacitor Selection
The input capacitor must meet the ripple current
⎛ V
⎞
OUT
2
requirement (I
RMS
lowing equation:
) imposed by the switching currents.
RMS
PD (N Resistive) =
(I
) R
H
LOAD DS(ON)
⎜
⎟
⎠
⎝
V
IN
The I
requirements may be determined by the fol-
Generally, a small high-side MOSFET is desired to
reduce switching losses at high-input voltages.
⎛ I
⎝
⎞
LOAD
V
IN
I
=
V
V − V
(
)
RMS
OUT IN OUT
⎜
⎟
⎠
However, the R
required to stay within package-
DS(ON)
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
The worst-case RMS current requirement occurs when
operating with V = 2V . At this point, the above
IN
OUT
= 0.5 x I
losses equal the conduction (R
) losses. High-
DS(ON)
equation simplifies to I
.
RMS
LOAD
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resis-
tance to inrush surge currents typical of systems with a
mechanical switch or connector in series with the input.
If the Quick-PWM controller is operated as the second
stage of a two-stage power-conversion system, tanta-
lum input capacitors are acceptable. In either configu-
ration, choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit longevity.
Calculating the power dissipation in the high-side MOS-
FET (N ) due to switching losses is difficult since it must
H
allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching-loss calculation provides only a very
24 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
rough estimate and is no substitute for breadboard
Boost Capacitors
evaluation, preferably including verification using a
The boost capacitors (C
) must be selected large
BST
thermocouple mounted on N :
H
enough to handle the gate charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low- power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side, MOSFETs require
boost capacitors larger than 0.1µF. For these applica-
tions, select the boost capacitors to avoid discharging
the capacitor more than 200mV while charging the
high-side MOSFETs’ gates:
Q
⎛
⎜
⎞
G(SW)
PD (N Switching) = V
I
f
+
H
IN(MAX)LOAD SW
⎟
⎝ I
⎠
GATE
2
C
V
f
OSS IN SW
2
where C
G(SW)
FET, and I
rent (2.2A typ).
is the N MOSFET’s output capacitance,
H
OSS
Q
is the charge needed to turn on the N MOS-
H
is the peak gate-drive source/sink cur-
GATE
N×Q
GATE
C
BST
=
200mV
where N is the number of high-side MOSFETs used for
one regulator, and Q is the gate charge specified
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
GATE
2
x V
x f
switching-loss equation. If the high-side
SW
IN
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
MOSFET chosen for adequate R
at low battery
DS(ON)
voltages becomes extraordinarily hot when biased from
, consider choosing another MOSFET with
V
IN(MAX)
lower parasitic capacitance.
(V
= 5V). Using the above equation, the required
GS
boost capacitance would be:
For the low-side MOSFET (N ), the worst-case power
L
dissipation always occurs at maximum input voltage:
2×24nC
200mV
C
BST
=
= 0.24μF
⎡
⎤
⎥
⎥
⎦
⎛
⎜
⎞
⎟
V
2
OUT
PD (N Resistive) = 1−
I
R
DS(ON)
⎢
(
)
L
LOAD
V
⎝ IN(MAX) ⎠
⎢
⎣
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
Minimum Input-Voltage Requirements
and Dropout Performance
I
, but are not quite high enough to exceed
LOAD(MAX)
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “overdesign” the
circuit to tolerate:
The output voltage-adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout perfor-
mance, use the slower (200kHz) on-time settings. When
working with low-input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propa-
gation delays introduce an error to the on-times. This
error is greater at higher frequencies. Also, keep in
mind that transient response performance of buck reg-
ulators operated too close to dropout is poor, and bulk
ΔI
L
I
=I
+
+
LOAD VALLEY(MAX)
2
I
LIR
⎛
⎞
LOAD(MAX)
=I
VALLEY(MAX)
⎜
⎟
⎝
2
⎠
where I
is the maximum valley current
VALLEY(MAX)
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
output capacitance must often be added (see the V
SAG
equation in the Quick-PWM Design Procedure section).
The absolute point of dropout is when the inductor cur-
Choose a Schottky diode (D ) with a forward voltage
L
rent ramps down during the minimum off-time (ΔI
)
DOWN
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if effi-
ciency is not critical.
as much as it ramps up during the on-time (ΔI ). The
UP
ratio h = ΔI / ΔI
is an indicator of the ability to
UP
DOWN
slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V
greatly increases
SAG
unless additional output capacitance is used.
______________________________________________________________________________________ 25
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows trade-offs between V , output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the Quick-PWM controller. This includes the V
SAG
CC
bypass capacitor, REF bypass capacitors, REFIN
components, and feedback compensation/dividers.
⎛
⎞
3) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance full-
load efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes
a measurable efficiency penalty.
V
− V
+ V
FB
DROOP DROPCHG
V
=
IN(MIN)
⎜
⎟
1− h× t
f
(
)
OFF(MIN) SW
⎝
⎠
7
where V is the voltage-positioning droop, V
FB DROPCHG
is the parasitic voltage drop in the charge path, and
is from the Electrical Characteristics table. The
t
OFF(MIN)
absolute minimum input voltage is calculated with h = 1.
If the calculated V is greater than the required
IN(MIN)
4) Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
. If operation near dropout is anticipated,
SAG
calculate V
response.
to be sure of adequate transient
SAG
5) When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
Dropout Design Example:
V
FB
= 1.5V
f
t
= 300kHz
SW
= 350ns
OFF(MIN)
No droop/load line (V
= 0)
DROOP
V
= 150mV (10A load)
DROPCHG
h = 1.5:
6) Route high-speed switching nodes away from sen-
sitive analog areas (REF, REFIN, FB, ILIM).
⎡
⎤
1.5V − 0V +150mV
1−(1.5× 350ns × 300kHz)
V
=
=1.96V
IN(MIN)
⎢
⎥
Layout Procedure
1) Place the power components first, with ground ter-
⎣
⎦
Calculating again with h = 1 gives the absolute limit of
dropout:
minals adjacent (low-side MOSFET source, C
OUT
,
IN
C
, and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
⎡
⎤
1.5V − 0V +150mV
1−(1.0× 350ns × 300kHz)
V
=
=1.84V
IN(MIN)
⎢
⎥
⎣
⎦
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
Therefore, V must be greater than 1.84V, even with
IN
very large output capacitance, and a practical input volt-
age with reasonable output capacitance would be 2.0V.
3) Group the gate-drive components (BST capacitors,
Applications Information
V
bypass capacitor) together near the controller IC.
DD
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow these guidelines for good PCB layout:
4) Make the DC-DC controller ground connections as
shown in the Standard Application Circuits. This
diagram can be viewed as having four separate
ground planes: input/output ground, where all the
high-power components go; the power ground
plane, where the PGND pin and V
bypass
DD
capacitor go; the master’s analog ground plane
where sensitive analog components, the master’s
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
GND pin, and V
bypass capacitor go; and the
CC
slave’s analog ground plane where the slave’s GND
26 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
pin and V
bypass capacitor go. The master’s
5) Connect the output power planes (V
and sys-
CORE
CC
GND plane must meet the PGND plane only at a
single point directly beneath the IC. Similarly, the
slave’s GND plane must meet the PGND plane only
at a single point directly beneath the IC. The
respective master and slave ground planes should
connect to the high-power output ground with a
short metal trace from PGND to the source of the
low-side MOSFET (the middle of the star ground).
This point must also be very close to the output
capacitor ground terminal.
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit
as close to the load as is practical.
Chip Information
TRANSISTOR COUNT: 7169
PROCESS: BiCMOS
______________________________________________________________________________________ 27
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
MAX8792
28 ______________________________________________________________________________________
Single Quick-PWM Step-Down
Controller with Dynamic REFIN
MAX8792
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE VARIATIONS
COMMON DIMENSIONS
SYMBOL
A
MIN.
0.70
MAX.
0.80
PKG. CODE
T633-2
N
6
D2
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEED-3
MO229 / WEED-3
- - - -
b
[(N/2)-1] x e
1.90 REF
1.95 REF
1.95 REF
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.50±0.10
1.70±0.10
1.70±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
2.30±0.10
0.95 BSC
0.65 BSC
0.65 BSC
0.50 BSC
0.50 BSC
0.40 BSC
0.40 BSC
0.40±0.05
0.30±0.05
0.30±0.05
0.25±0.05
0.25±0.05
0.20±0.05
0.20±0.05
T833-2
8
D
E
2.90
2.90
3.10
3.10
T833-3
8
A1
0.00
0.20
0.05
0.40
T1033-1
T1033-2
T1433-1
T1433-2
10
10
14
14
2.00 REF
2.00 REF
2.40 REF
2.40 REF
L
k
0.25 MIN.
0.20 REF.
- - - -
A2
Note: MAX8792ETD+ Package Code = T1433-1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
29 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products. Inc.
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