MAX8967EWV+T [MAXIM]
Dual 2A Step-Down Converters with 6 LDOs for Baseband and Applications Processor; 双路2A降压型转换器，带有6的LDO用于基带和应用处理器
| 型号： | MAX8967EWV+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual 2A Step-Down Converters with 6 LDOs for Baseband and Applications Processor |
| 文件： | 总59页 (文件大小：3136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
General Description
Benefits and Features
The MAX8967 is an FPMIC with two DC-to-DC step-
down switching converters and six remote capaci-
tor-capable LDOs. The step-down converters deliv-
er up to 2A of output current independently. Two
of the LDOs deliver a load current up to 300mA,
while the remaining four deliver up to 150mA. Both
step-down converters have remote sense, allowing loads
to be placed away from the IC. The IC operates over a
2.6V to 5.5V input supply range.
S Multi-Output PMIC in a Compact Package
Two 2A Step-Down Converters with Remote
Output Voltage Sensing
Two 300mA LDOs
Four 150mA LDOs
< 1µA Shutdown Current
2.32mm x 2.44mm Package
S Versatile Step-Down Converters
Programmable Output Voltage (0.6V to 3.3875V)
Through I2C Bus
Fixed-frequency 4.4MHz PWM operation and clocks that
are 180N out of phase permit the use of small external
components. Under light load conditions, the step-down
converters automatically switch to skip mode operation.
In skip mode operation, switching occurs only as need-
ed, allowing efficient operation. Placing either of the step-
down converters into green mode reduces the quiescent
current consumption of that converter to 5FA (typ).
Programmable Output Voltage Slew Rate
(12.5mV/µs to 50mV/µs)
Dynamic Switching Between Two Output
Voltages Through V
Pins
ID_
S Efficient Step-Down Converters
Over 95% Efficiency with Internal Synchronous
Rectifier
The IC supports dynamic adjustment of the output
voltage through its I2C interface. Each step-down
converter has two register settings for output voltage and
a setting for ramp rate. Also, each step-down converter
Automatic Skip Mode at Light Loads
Low 61µA (typ) Quiescent Current
5µA (typ) Green Mode per Step-Down Converter
has a dedicated enable pin and a dedicated V pin to
ID
S Programmable LDOs
toggle between the two programmed output voltages.
Additionally, an interrupt output is provided, allowing the
IC to signal its master.
Programmable Output Voltage (0.8V to 3.95V in
50mV Steps)
Programmable Soft-Start Slew Rate
(5mV/µs–100mV/µs)
Typical Operating Circuit
S Reduces Component Size and Board Area Solution
4.4MHz Step-Down Switching Allows for 1µH
Inductors
INPUT
2.6V TO 5.5V
OUT1
C
= 1µF for All LDOs
IN1
IN2
AV
OUT1
LX1
OUT
1µH
0.6V TO
3.3875V,
2A
Reduced Board Space with Remote Capacitor
LDOs
PGND1
Internal Feedback for Step-Down Converters
1.7V TO 5.5V
and LDOs
INA
OUT2
LX2
OUT2
0.6V TO
3.3875V,
2A
1µH
INB
AGND
Applications
MAX8967
1.65V TO 5.5V
V
PGND2
IO
Cellular Handsets and Smartphones
Tablets
SCL
SDA
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
0.8V TO 3.95V, 150mA
2
I C
0.8V TO 3.95V, 300mA
0.8V TO 3.95V, 150mA
0.8V TO 3.95V, 150mA
0.8V TO 3.95V, 300mA
0.8V TO 3.95V, 150mA
Portable Devices
EN1
EN2
V
V
ID1
ID2
Ordering Information appears at end of data sheet.
IRQB
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6534; Rev 0; 12/12
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ABSOLUTE MAXIMUM RATINGS
IN1, IN2, INA, INB, AV, OUT1, OUT2, ,SCL, SDA, SNSP1,
SNSN1, SNSP2, SNSN2 to AGND....................-0.3V to +6.0V
Continuous Power Dissipation (T = +70NC)
30-Bump, 2.32mm x 2.44mm WLP
A
EN1, EN2, V , V , IRQB to AGND...... -0.3V to (V
LDO1, LDO2, LDO3 to AGND.................-0.3V to (V
LDO4, LDO5, LDO6 to AGND.................-0.3V to (V
PGND1, PGND2 to AGND ...................................-0.3V to +0.3V
LX1, LX2 Current..........................................................2.0A
+ 0.3V)
+ 0.3V)
+ 0.3V)
(derate 20.4mW/NC above +70NC)............................1632mW
Operating Temperature...................................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
ID_ IO
AV
INA
INB
RMS
CAUTION! ESD SENSITIVE DEVICE
PACKAGE THERMAL CHARACTERISTICS (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (B )..........49NC/W
Junction-to-Case Thermal Resistance (B ) ....................9NC/W
JC
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
_
IN
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
AV IO A A
PARAMETER
SYMBOL
CONDITIONS
= V
MIN
TYP
MAX
5.5
UNITS
Operating Input Voltage Range
Overvoltage Lockout
V
V
V
V
= V
2.6
V
V
INPUT
IN1
AV
AV
IN2
AV
OVP
rising, 100mV hysteresis
rising, 55mV hysteresis
5.70
5.85
2.4
6.00
2.5
AV Undervoltage Lockout (UVLO)
UVLO
2.3
1.65
1.4
V
V
V
V
V
V
Operating Range
V
5.5
IO
IO
IO
IO
IO
Enable Threshold High
Enable Threshold Low
Enable Hysteresis
V
0.4
V
100
+0.1
0.1
mV
T
T
= +25NC
= +85NC
-5
+0.5
V
> 2.6V, V < 0.4V,
IO
EN1 = EN2 = 0
A
AV
V
Shutdown Current
FA
A
A
V
V
Standby Current
Supply Current
V
> 2.6V, V > 1.4V, EN1 = EN2 = 0
28
FA
FA
A
AV
IO
All logic in high or low state
0.1
IO
Quiescent Current
(Green Mode)
No switching, V = 1.2V, step-down
converter in green mode, all LDOs off
OUT_
5
FA
FA
Quiescent Current
(Step-Down Converters On)
No switching, V
sense off
= 1.2V remote
OUT_
61
85
No switching, V
off, both step-down converters in normal
mode, all LDOs on
= 1.2V, remote sense
OUT_
Quiescent Current
(All On Normal Mode)
176
75
FA
FA
Quiescent Current (Step-Down
Converters On, Normal Mode
Remote sense ON)
No switching, V
on, both step-down converters on
= 1.2V, remote sense
OUT_
120
Maxim Integrated
2
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
_
IN
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
AV IO A A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
No switching, V
step-down converters in green mode,
all LDOs on
= 1.2V, both
OUT_
Quiescent Current
(All On Green Mode)
40
FA
Forced PWM, one step-down converter on
FPWM Current
only, I
= 0A, C
= C = 22FF,
9
mA
OUT
OUT1
OUT2
L1 = L2 = 1FH, V
= 1.2V
OUT
Thermal Shutdown
T
rising, 20NC hysteresis
+160
NC
A
STEP-DOWN CONVERTER 1
Output Current
L = 1FH
2
A
V
Adjustable Output Voltage
Range
12.5mV steps
0.6000
3.3875
FPWM, I
= 0.2A C
= 22FF,
OUT1
OUT1
Settling Time
L = 1FH, measure from V
= 1V to
20
Fs
OUT1
V
= 1.2V
OUT1
Output Voltage Accuracy
(FPWM)
V
= 1.2V, FPWM, V
< 0.95 x V ,
OUT1
OUT1 IN
1.176
1.152
1.20
1.200
0.04
1.224
1.248
V
V
remote sense disabled (Note 3)
Output Voltage Accuracy
(Green Mode)
Green mode, I P 5mA (Note 3)
OUT1
V
= 1.2V, I
= 0.2A,
OUT1
OUT1
Line Regulation
%/V
C
= 22FF, L = 1FH
OUT1
Load Regulation
V
= 1.2V, 0 P I
P 2A
+0.125
4.40
3000
1800
1
%/A
MHz
mA
mA
A
OUT1
OUT1
Switching Frequency
Peak Current Limit
Valley Current Limit
Negative Current limit
3.96
4.84
FPWM mode
FPWM mode
FPWM mode
2500
3600
Zero-Crossing Current
Threshold
Used in skip mode and green mode
20
mA
PMOS On-Resistance
NMOS On-Resistance
V
V
= 3.6V, I
= 3.6V, I
= 190mA
= 190mA
60
50
0.1
1
mI
mI
IN_
IN_
OUT1
OUT1
T
T
= +25NC
= +85NC
-1
+1
A
LX Leakage
V
= V
0V
FA
LX1
IN ,
A
Output Discharge Resistor in
Shutdown
Feature must be active, see the Register
Definitions section
100
I
Maxim Integrated
3
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
_
IN
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
AV IO A A
PARAMETER
SYMBOL
CONDITIONS
Slew_ _[7:6] = 00, see Table 15
Slew_ _[7:6] = 01, see Table 15
Slew_ _[7:6] = 10, see Table 15
MIN
TYP
12.5
25
MAX
UNITS
Output Step Ramp Rate
Load Transient FPWM
mV/Fs
50
FPWM mode, V
= 1.2V, load steps
OUT1
between 0.2 to 1.2A in 30ns,
40
mV
C
= 22FF, L = 1FH
OUT1
Skip mode, V
= 1.2V, load steps
OUT
Load Transient (Skip Mode)
Line Transient
between 0.2 to 1.2A in 30ns,
40
0.25
40
mV
%/V
mV
Fs
C
= 22FF, L = 1FH
OUT1
V
= 1.2V, I
= 1.2A,
OUT
OUT1
C
= 22FF, L = 1FH.
OUT1
Transitions between output voltage states
1.0 and 1.4V, I = 400mA,
Overshoot
OUT1
C
= 22FF, L = 1FH
OUT1
From chip standby state until first output
voltage ramp starts
Chip Enable Time
250
From enabling until voltage ramp starts,
the IC is in normal operating state with
Enable Time
25
Fs
previous state shut down, I
P 100mA,
OUT1
L = 1FH, C
= 22FF
OUT1
Output POK Threshold
V
falling, 1.2V nominal setting
86
90
3
94
%V
OUT1
OUT1
Output POK Threshold
Hysteresis
%
Minimum Output Capacitance
Minimum Inductance
12
1
FF
1FH inductor with 30% duration
FH
STEP-DOWN CONVERTER 2
Output Current
L = 1FH
2
A
V
Adjustable Output Voltage
Range
12.5mV steps
0.6000
3.3875
FPWM, I
= 0.2A, C
= 22FF,
OUT2
OUT2
Settling Time
L = 1FH, measure from V
= 1V to
20
Fs
OUT2
V
= 1.2V
OUT2
Output Voltage Accuracy
(FPWM)
V
= 1.2V, FPWM, V
< 0.95 x V ,
OUT2
OUT2 IN
1.176
1.152
1.20
1.200
0.04
1.224
1.248
V
V
remote sense disabled (Note 3)
Output Voltage Accuracy
(Green Mode)
Green mode, I P 5mA (Note 3)
OUT2
V
= 1.2V, I
= 0.2A,
OUT2
OUT2
Line Regulation
%/V
C
= 22FF, L = 1FH
OUT2
Maxim Integrated
4
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
_
IN
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
AV IO A A
PARAMETER
SYMBOL
CONDITIONS
= 1.2V, 0 P I P 2A
MIN
TYP
+0.125
4.40
3000
1800
1
MAX
UNITS
%/A
MHz
mA
Load Regulation
V
OUT2
OUT2
Switching Frequency
Peak Current Limit
Valley Current Limit
Negative Current Limit
3.96
4.84
FPWM mode
FPWM mode
FPWM mode
2500
3600
mA
A
Zero-Crossing Current Threshold
Used in skip mode and green mode
20
mA
PMOS On-Resistance
NMOS On-Resistance
V
V
= 3.6V, I
= 3.6V, I
= 190mA
= 190mA
60
50
0.1
1
mI
mI
IN_
OUT2
IN_
OUT2
T
T
= +25NC
= +85NC
-1
+1
A
A
LX Leakage
V
= V ,0V
FA
LX2
IN
Output Discharge Resistor in
Shutdown
Feature must be active, see the Register
Definitions section
100
I
Slew_ _[7:6] = 00, see Table 15
Slew_ _[7:6] = 01, see Table 15
Slew_ _[7:6] = 10, see Table 15
12.5
25
Output Step Ramp Rate
Load Transient FPWM
mV/Fs
50
FPWM mode, V
= 1.2V, load steps
OUT2
between 0.2 to 1.2A in 30ns,
40
mV
C
= 22FF, L = 1FH
OUT2
Skip mode, V
= 1.2V, load steps
OUT2
Load Transient (Skip Mode)
Line Transient
between 0.2 to 1.2A in 30ns,
40
0.25
40
mV
%/V
mV
Fs
C
= 22FF, L = 1FH
OUT2
V
= 1.2V, I
= 1.2A,
OUT2
OUT2
C
= 22FF, L = 1FH
OUT2
Transitions between output voltage states
1.0V and 1.4V, I = 400mA,
Overshoot
OUT21
C
= 22FF, L = 1FH
OUT2
From chip standby state until first output
voltage ramp starts
Chip Enable Time
250
From enabling until voltage ramp starts;
the IC is in normal operating state with
Enable Time
25
Fs
previous state shut down, I
P 100mA,
OUT2
L = 1FH, C
= 22FF
OUT2
Output POK Threshold
V
falling, 1.2V nominal setting
86
90
3
94
%V
OUT2
OUT2
Output POK Threshold
Hysteresis
%
Minimum Output Capacitance
Minimum Inductance
12
1
FF
1FH inductor with 30% duration
FH
Maxim Integrated
5
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO1
V
Input Voltage Range
Undervoltage Lockout
IN,LDO1
1.7
5.5
1.7
V
V
V
UVLO,LDO1
V
rising, 100mV hysteresis
is the maximum of 3.7V or
1.6
IN,LDO1
V
V
INLDO1
V
Output Voltage Range
OUT,LDO1
0.8
3.95
V
+ 0.3V
OUT,LDO1
Normal mode
Green mode
150
5
I
Maximum Output Current
Minimum Output Capacitance
MAX,LDO1
mA
FF
Normal mode
Green mode
0.7
0.7
C
OUT,LDO1 (Note 4)
Time to enable LDO bias only, central bias
is already enabled
t
Bias Enable Time
LBIAS1
90
10
0
Fs
I
Bias Enable Currents
QBIAS1
LDO bias enabled, LDOBIASEN = 1
FA
Shutdown, T = +25NC
A
(Note 5)
I
AV Supply Current
AV,LDO1
No load
No load
FA
FA
Normal regulation
Green mode
3
6
3
0.5
Shutdown, T = +25NC
(Note 6)
A
0
I
INA Input Supply Current
IN,LDO1
Normal regulation
Green mode
15
1
30
3
V
= V
+
IN,LDO1
NOM
0.3V to 5.5V with 1.7V
minimum, I
=
OUT,LDO1
Normal mode
Green mode
-3
-5
+3
+5
0.1mA to I
,
MAX,LDO1
V
set to any
NOM,LDO1
voltage
Output Voltage Accuracy
%
V
= V
NOM,LDO1
IN,LDO1
+ 0.3V to 5.5V with 2.4V
minimum, I
OUT,LDO1
= 0.1mA to 5mA,
V
set to any
NOM,LDO1
voltage
Maxim Integrated
6
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
= 0.1mA to
OUT,LDO1
, V
MAX,LDO1 IN,LDO1
= V
+ 0.3V
NOM,LDO1
Normal mode
Green mode
0.1
with 1.7V minimum,
V
set to any
NOM,LDO1
voltage
Load Regulation
(Note 7)
%
I
= 0.1mA
OUT,LDO1
to 5mA, V
=
IN,LDO1
V
+ 0.3V
NOM,LDO1
0.2
0.03
0.1
with 2.4V minimum,
V
set to any
NOM,LDO1
voltage
V
= V
NOM,LDO1
IN,LDO1
+ 0.3V to 5.5V with 1.7V
Normal mode minimum, I
=
OUT,LDO1
0.1mA, V
any voltage
set to
NOM,LDO1
Line Regulation
(Note 7)
%/V
V
= V
NOM,LDO1
IN,LDO1
+ 0.3V to 5.5V with 2.4V
minimum, I
Green mode
=
OUT,LDO1
0.1mA, V
set to
NOM,LDO1
any voltage
V
IN,LDO1
60
120
300
= 3.7V
I
I
=
OUT,LDO1
MAX,LDO1
Normal mode
Green mode
mV
mA
V
IN,LDO1
V
Dropout Voltage
DO,LDO1
150
= 1.7V
I
V
= 5mA,
= 3.7V
OUT,LDO1
50
100
375
IN,LDO1
I
Output Current Limit
LIM,LDO1
V
= 0V
150
225
OUT,LDO1
Normal mode, V
= V
+
IN,LDO1
NOM,LDO1
0.3V to 5.5V with 1.7V absolute minimum,
I
I
t
= 1% to 100% to 1% of
66
25
OUT,LDO1
, V
set to any voltage,
MAX,LDO1 NOM,LDO1
Output Load Transient
(LDO1OVCLMP_EN = 1)
(Notes 4, 7)
= t = 1Fs, LDO1COMP[5:4] = 01
R1
F1
mV
Green mode, V
= V
+
IN,LDO1
NOM,LDO1
0.3V to 5.5V with 2.4V absolute minimum,
= 0.05mA to 5mA to 0.05mA,
I
OUT,LDO1
V
set to any voltage,
NOM,LDO1
t
= t = 1Fs
R1
F1
Maxim Integrated
7
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
Normal mode, V = V
MIN
TYP
MAX
UNITS
+
IN,LDO1
NOM,LDO1
0.3V to V
+ 0.8V to V
+
NOM,LDO1
NOM,LDO1
0.3V with 1.7V absolute minimum, t = t
5
R1
F1
= 1Fs, I
= I
, V
OUT,LDO1
MAX,LDO1 NOM,LDO1
set to any voltage
Output Line Transient
(Notes 3, 6)
mV
Green mode, V
= V
+
IN,LDO1
NOM,LDO1
0.3V to V
+ 0.8V to V
+
NOM,LDO1
NOM,LDO1
0.3V with 2.4V absolute minimum, t = t
5
R1
F1
= 1Fs, I
= 5mA, V
set to
OUT,LDO1
NOM,LDO1
any voltage
f = 1kHz
63
51
44
57
33
50
Rejection
from
V
f = 10kHz
INLDO1DC
V
= V
IN,LDO1
NOM,
to
+
LDO1
0.3V
f = 100kHz
f = 1000kHz
f = 4450kHz
V
OUT,LDO1
Power-Supply Rejection
PSRR
dB
LDO1
I
V
OUT,LDO1
INLDO1AC
= 50mV
= 10% of
I
MAX,LDO1
Green mode, I
= 1mA, f = 1kHz,
OUT,LDO1
rejection from V
to V
IN,LDO1
OUT,LDO1
OUT,LDO1
OUT,LDO1
OUT,LDO1
V
V
V
= 0.8V
= 1.8V
= 3.7V
45
45
f = 10Hz to 100kHz,
Output Noise
I
I
= 10% of
FV
RMS
OUT,LDO1
MAX,LDO1
60
100
5
LDO1SS = 0
LD01SS = 1
Startup Ramp Rate
t
After enabling
mV/Fs
kI
SS,LDO1
Active discharge
enabled,
LDO1ADE = 1
0.16
0.3
V
= 1V,
OUT,LDO1
Active-Discharge Resistance
output disabled
Active discharge
disabled,
1000
LDO1ADE = 0
Maxim Integrated
8
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Clamp Active Regulation
Voltage
Clamp active (LDO1OVCLMP_EN = 1), LDO
output sinking 0.1mA
V
NOM,
LDO1
V
Clamp Disabled Overvoltage
Sink Current
V
= V
x 110%
2.2
10
60
FA
Fs
OUT,LDO1
NOM,LDO1
Ramp rate =
100mV/Fs
Time from LDO
enable command
received to the
Enable Delay (Note 4)
Disable Delay (Note 4)
t
LON,LDO1
Ramp rate = 5mV/
output starting to slew
Fs
After LDO is disabled; the LDO output
voltage discharges based on load and
C
0.1
10
Fs
; to ensure fast discharge times,
OUT
enable the active discharge resistor
Transition Time from Green
Mode to Normal Mode
Fs
NC
T rising
165
150
92
Output disabled or
enabled
J
Thermal Shutdown
T falling
J
V
rising
falling
95
V
when V
POK
OUT,LDO1
OUT,LDO1
Power-OK Threshold
V
%
POKTHL1
switches
V
84
87
OUT,LDO1
V
pulsed from 100% to 80% of
OUT,LDO1
Power-OK Noise Pulse Immunity
V
25
Fs
POKNF1
regulation
LDO2
Input Voltage Range
V
1.7
0.8
5.5
1.7
V
V
IN,LDO2
V
UVLO,
LDO2
Undervoltage Lockout
V
rising, 100mV hysteresis
is the maximum of 3.7V or
1.6
IN,LDO2
V
V
V
OUT,
IN,LDO2
Output Voltage Range
3.95
V
+ 0.3V
LDO2
OUT,LDO2
Normal mode
Green mode
300
5
Maximum Output Current
Minimum Output Capacitance
I
mA
FF
MAX,LDO2
Normal mode
Green mode
0.7
0.7
C
OUT,
(Note 3)
LDO2
Time to enable LDO bias only, central bias
is already enabled
Bias Enable Time
t
I
90
10
Fs
LBIAS2
LBIAS2
Bias Enable Current
LDO bias enabled
FA
Maxim Integrated
9
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Shutdown, T = +25NC
(Note 5)
A
0
AV Supply Current
INA Supply Current
I
No load
No load
FA
AV,LDO2
Normal regulation
Green mode
3
6
3
0.5
Shutdown, T = +25NC
A
0
(Note 5)
I
FA
IN,LDO2
Normal regulation
Green mode
17
1
30
3
V
= V
NOM,LDO2
IN,LDO2
+ 0.3V to 5.5V with 1.7V
minimum, I
=
OUT,LDO2
Normal mode
-3
-5
+3
+5
0.1mA to I
,
MAX,LDO2
V
set to
NOM,LDO2
any voltage
Output Voltage Accuracy
%
V
= V
IN,LDO2
NOM,LDO2
+ 0.3V to 5.5V with 2.4V
Green mode minimum, I
=
OUT,LDO2
0.1mA to 5mA, V
NOM,LDO2
set to any voltage
I
I
= 0.1mA to
OUT,LDO2
, V
=
MAX,LDO2 IN,LDO2
Normal mode
V
+ 0.3V with 1.7V
0.1
0.2
NOM,LDO2
minimum, V
any voltage
set to
NOM,LDO2
Load Regulation
(Note 6)
%
I
= 0.1mA to 5mA,
OUT,LDO2
V
= V
+
IN,LDO2
NOM,LDO2
Green mode 0.3V with 2.4V minimum,
V
set to any
NOM,LDO2
voltage
V
= V
NOM,LDO2
IN,LDO2
+ 0.3V to 5.5V with 1.7V
Normal mode minimum; I
=
set to
0.03
0.1
OUT,LDO2
0.1mA, V
NOM,LDO2
any voltage
Line Regulation
(Note 6)
%/V
V
= V
IN,LDO2
NOM,LDO2
+ 0.3V to 5.5V with 2.4V
Green mode minimum; I
=
OUT,LDO2
0.1mA, V
set to
NOM,LDO2
any voltage
Maxim Integrated
10
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
3.7V
=
=
IN,LDO2
50
100
I
I
=
OUT,LDO2
MAX,LDO2
Normal mode
Green mode
mV
V
IN,LDO2
Dropout Voltage
V
150
450
DO,LDO2
1.7V
I
= 5mA, V
OUT,LDO2
IN,LDO2
150
450
300
750
= 3.7V
Output Current Limit
I
V
= 0V
300
mA
mV
LIM,LDO2
OUT,LDO2
Normal mode, V
= V
+
IN,LDO2
NOM,LDO2
0.3V to 5.5V with 1.7V absolute minimum;
I
I
t
= 1% to 100% to 1% of
66
25
5
OUT,LDO2
, V
set to any voltage,
MAX,LDO2 NOM,LDO2
Output Load Transient
(LDO2OVCLMP_EN = 1)
(Notes 3, 6 )
= t = 1Fs, LDO2COMP[5:4] = 01
R2
F2
Green mode, V
,
= V
+
IN LDO2
NOM,LDO2
0.3V to 5.5V with 2.4V absolute minimum;
I
= 0.05mA to 5mA to 0.05mA,
set to any voltage,
OUT,LDO2
V
NOM,LDO2
t
= t = 1Fs
R2
F2
Normal mode, V
= V
+
IN,LDO2
NOM,LDO2
0.3V to V
+ 0.8V to V
+
+
NOM,LDO2
0.3V with 1.7V absolute minimum;
= t = 1Fs, I = I ,
MAX,LDO2
NOM,LDO2
t
R2
F2
OUT,LDO2
V
set to any voltage
NOM,LDO2
Output Line Transient
(Notes 3, 6)
mV
Green mode, V
0.3V to V
= V +
NOM,LDO2
IN,LDO2
+ 0.8V to V
NOM,LDO2
NOM,LDO2
0.3V with 2.4V absolute minimum;
= t = 1Fs, I = 5mA,
5
t
R2
F2
OUT,LDO2
V
set to any voltage
NOM,LDO2
Maxim Integrated
11
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
f = 1kHz
63
Rejection from
f = 10kHz
51
44
57
33
50
V
V
to
V
V
=
=
IN,LDO2
INLDO2DC
OUT,LDO2
NOM,LDO2
I
+0.3V
f = 100kHz
f = 1000kHz
f = 4450kHz
OUT,LDO2
= 10% of
V
Power-Supply Rejection
PSRR
INLDO2AC
dB
LDO2
I
50mV
MAX,LDO2
Green mode, I
rejection from V
= 1mA, f = 1kHz,
OUT,LDO2
to V
IN,LDO2
OUT,LDO2
V
V
V
= 0.8V
45
45
OUT,LDO2
OUT,LDO2
OUT,LDO2
f = 10Hz to 100kHz,
Output Noise
I
I
= 10% of
= 1.8V
= 3.7V
FV
RMS
OUT,LDO2
MAX,LDO2
60
100
5
LDO2SS = 0
LDO2SS = 1
Startup Ramp Rate
t
After enabling
mV/Fs
kI
SS22
Active discharge
enabled,
LDO2ADE = 1
0.16
0.3
V
= 1V,
OUT,LDO2
Active-Discharge Resistance
output disabled
Active discharge
disabled, LDO2ADE 1000
= 0
Clamp active (LDO2OVCLMP_EN = 1), LDO
output sinking 0.1mA
V
NOM,
LDO2
Clamp Active Regulation Voltage
V
Clamp Disabled Overvoltage
Sink Current
V
= V
x 110%
2.2
10
60
FA
OUT,LDO2
NOM,LDO2
Ramp rate =
100mV/Fs
Time from LDO enable
command received to
the output starting to
slew
Enable Delay (Note 3)
Disable Delay (Note 3)
t
Fs
Fs
LON2
Ramp rate = 5mV/
Fs
After LDO is disabled; the LDO output
voltage discharges based on load and
C
0.1
; to ensure fast discharge times, enable
OUT
the active discharge resistor
Maxim Integrated
12
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Transition Time from Green
Mode to Normal Mode
10
Fs
T rising
165
150
92
Output disabled or
enabled
J
Thermal Shutdown
NC
T falling
J
V
rising
falling
95
%
V
when V
POK
OUT,LDO2
OUT,LDO2
Power-OK Threshold
V
POKTHL2
switches
V
84
87
OUT,LDO2
V
pulsed from 100% to 80% of
OUT,LDO2
Power-OK Noise Pulse Immunity
V
25
Fs
POKNF2
regulation
LDO3
Input Voltage Range
V
1.7
0.8
5.5
1.7
V
V
IN,LDO3
V
UVLO,
LDO3
Undervoltage Lockout
V
rising, 100mV hysteresis
is the maximum of 3.7V or
1.6
IN,LDO3
V
V
V
OUT,
IN,LDO3
Output Voltage Range
3.95
V
+ 0.3V
LDO3
OUT,LDO3
Normal mode
Green mode
150
5
Maximum Output Current
Minimum Output Capacitance
I
mA
FF
MAX,LDO3
Normal mode
Green mode
0.7
0.7
C
OUT,
(Note 3)
LDO3
Time to enable LDO bias only, central bias is
already enabled
Bias Enable Time
t
90
10
0
Fs
LBIAS3
Bias Enable Currents
I
LDO bias enabled
FA
QBIAS3
Shutdown, T
=
A
+25NC (Note 4)
Normal regulation
Green mode
AV Supply Current
INA Supply Current
I
No load
No load
FA
FA
AV,LDO3
3
6
3
0.5
Shutdown, T
=
A
0
+25NC (Note 5)
Normal regulation
Green mode
I
IN,LDO3
15
1
30
3
Maxim Integrated
13
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
= V
MIN
TYP
MAX
UNITS
V
IN,LDO3
NOM,LDO3
+ 0.3V to 5.5V with 1.7V
minimum, I
=
OUT,LDO3
Normal mode
Green mode
-3
-5
+3
0.1mA to I
,
MAX,LDO3
V
NOM,LDO3
set to any voltage
= V
Output Voltage Accuracy
%
V
IN,LDO3
NOM,LDO3
+ 0.3V to 5.5V with 2.4V
minimum, I
=
OUT,LDO3
+5
0.1mA to 5mA,
V
set to
NOM,LDO3
any voltage
I
I
= 0.1mA to
OUT,LDO3
, V
=
MAX,LDO3 IN,LDO3
Normal mode
Green mode
Normal mode
Green mode
V
+ 0.3V with
0.1
0.2
NOM,LDO3
1.7V minimum, V
set to any voltage
NOM,LDO3
Load Regulation
(Note 6)
%
I
= 0.1mA
OUT,LDO3
to 5mA, V
=
IN,LDO3
V
+ 0.3V with
NOM,LDO3
2.4V minimum, V
set to any voltage
NOM,LDO3
V
= V
IN,LDO3
NOM,LDO3
+ 0.3V to 5.5V with 1.7V
minimum, I
0.1mA, V
any voltage
=
0.03
0.1
OUT,LDO3
set to
NOM,LDO3
Line Regulation
(Note 6)
%/V
V
= V
IN,LDO3
NOM,LDO3
+ 0.3V to 5.5V with 2.4V
minimum, I
=
OUT,LDO3
0.1mA, V
set to
NOM,LDO3
any voltage
V
3.7V
=
=
IN,LDO3
60
120
300
I
I
=
OUT,LDO3
MAX,LDO3
Normal Mode
Green Mode
mV
mA
V
IN,LDO3
Dropout Voltage
V
150
DO,LDO3
1.7V
I
= 5mA,
= 3.7V
OUT,LDO3
50
100
375
V
IN,LDO3
Output Current Limit
I
V
= 0V
150
225
LIM,LDO3
OUT
Maxim Integrated
14
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
Normal mode, V = V
MIN
TYP
MAX
UNITS
+
NOM,LDO3
IN,LDO3
0.3V to 5.5V with 1.7V absolute minimum,
I
I
t
= 1% to 100% to 1% of
66
OUT,LDO3
, V
set to any voltage,
MAX,LDO3 NOM,LDO3
Output Load Transient
(LDO3OVCLMP_EN = 1)
(Notes 3, 6)
= t = 1Fs, LDO3COMP[5:4] = 01
R3
F3
mV
Green mode, V
= V
+
IN,LDO3
NOM,LDO3
0.3V to 5.5V with 2.4V absolute minimum,
= 0.05mA to 5mA to 0.05mA,
I
25
5
OUT,LDO3
V
set to any voltage,
NOM,LDO3
t
= t = 1Fs
R3
F3
Normal mode, V
= V
+
IN,LDO3
NOM,LOD3
0.3V to V
+ 0.8V to V
+
NOM,LDO3
NOM,LDO3
0.3V with 1.7V absolute minimum,
= t = 1Fs, I = I ,
MAX,LDO3
t
R3
F3
OUT,LOD3
V
set to any voltage
NOM,LOD3
Output Line Transient
(Notes 3, 6)
mV
Green mode, V
to V
= V
+ 0.3V
+ 0.3V
IN,LDO3
NOM,LOD3
+ 0.8V to V
NOM,LDO3
NOM,LDO3
with 2.4V absolute minimum, t = t =1Fs,
5
R3
F3
I
= 5mA, V
set
OUT,LOD3
NOM,LOD3
to any voltage
f = 1kHz
63
51
44
57
33
50
Rejection from
V
=
f = 10kHz
INLDO3DC
V
V
to
IN,LDO3
OUT,lDO3
V
NOM,LDO3
I
f = 100kHz
f = 1000kHz
f = 4450kHz
OUT,LDO3
+ 0.3V
= 10% of
Power-Supply Rejection
PSRR
dB
LDO3
V
INLDO3AC
I
MAX,LDO3
= 50mV
Green mode, I
rejection from V
= 1mA, f = 1kHz,
OUT,LDO3
to V
IN,LDO3
OUT,LDO3
Maxim Integrated
15
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f = 10Hz to
V
V
V
= 0.8V
= 1.8V
= 3.7V
45
OUT,LDO3
OUT,LDO3
OUT,LDO3
100kHz, I
= 10% of
OUT
Output Noise
45
60
FV
RMS
I
MAX,LDO3
LDO3SS = 0
LDO3SS = 1
100
5
Startup Ramp Rate
Active-Discharge Resistance
t
After enabling
mV/Fs
kI
SS3
Active discharge enabled,
LDO3ADE = 1
0.16
0.3
V
OUT,LDO3
= 1V, output
disabled
Active discharge disabled,
LDO3ADE = 0
1000
Clamp Active Regulation
Voltage
Clamp active (LDO3OVCLMP_EN = 1),
LDO output sinking 0.1mA
V
NOM,
LDO3
V
Clamp Disabled Overvoltage
Sink Current
V
= V
x110%
2.2
10
60
FA
OUT,LDO3
NOM,LDO3
Ramp rate =
100mV/Fs
Time from LDO
enable command
received to the
Enable Delay (Note 3)
Disable Delay (Note 3)
t
Fs
Fs
LON3
Ramp rate = 5mV/
output starting to slew
Fs
After LDO is disabled; the LDO output
voltage discharges based on Load and
C
0.1
10
; to ensure fast discharge times
OUT,LDO3
enable the active discharge resistor
Transition Time from Green
Mode to Normal Mode
Fs
NC
Output
disabled or
enabled
T rising
165
150
92
J
Thermal Shutdown
T falling
J
V
OUT,LDO3
V
V
rising
falling
95
OUT,LDO3
OUT,LDO3
Power-OK Threshold
V
when V
switches
%
POKTHL3
POK
84
87
V
pulsed from 100% to 80% of
OUT,LDO3
Power-OK Noise Pulse Immunity
V
25
Fs
POKNF3
regulation
LDO4
Input Voltage Range
V
1.7
0.8
5.5
1.7
V
V
IN,LDO4
V
UVLO,
LDO4
Undervoltage Lockout
Output Voltage Range
Maximum Output Current
V
rising, 100mV hysteresis
is the maximum of 3.7V or
1.6
IN,LDO4
V
V
V
OUT,
IN,LDO4
3.95
V
+ 0.3V
LDO4
OUT,LDO4
Normal mode
Green mode
150
5
I
mA
FF
MAX,LDO4
Normal mode
Green mode
0.7
0.7
C
OUT,
LDO4
Minimum Output Capacitance
(Note 3)
Maxim Integrated
16
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
90
10
0
MAX
UNITS
Fs
Time to enable LDO bias only, central bias is
already enabled
Bias Enable Time
t
LBIAS4
Bias Enable Currents
I
LDO bias enabled
FA
QBIAS4
Shutdown, T = +25NC
(Note 4)
A
AV Supply Current
INB Supply Current
I
No load
No load
FA
FA
AV,LDO4
Normal regulation
Green mode
3
6
3
0.5
Shutdown, T = +25NC
(Note 5)
A
0
I
IN,LDO4
Normal regulation
Green mode
15
1
30
3
V
= V
NOM,LDO4
IN,LDO4
+ 0.3V to 5.5V with 1.7V
minimum, I
= 0.1mA to I
OUT,LDO4
Normal mode
Green mode
Normal mode
Green mode
-3
-5
+3
+5
,
MAX,LD04
V
NOM,LDO4
set to any voltage
Output Voltage Accuracy
%
V
= V
NOM,LDO4
IN,LDO4
+ 0.3V to 5.5V with 2.4V
minimum, I
=
OUT,LDO4
0.1mA to 5mA, V
set to any voltage
NOM,LDO4
I
I
= 0.1mA to
OUT,LDO4
,
MAX,LD04
V
= V
+
IN
NOM,LDO4
0.1
0.2
0.3V with 1.7V minimum,
V
set to any
NOM,LDO4
Load Regulation
(Note 6)
voltage
%
I
= 0.1mA to
OUT,LDO4
5mA, V = V
+
IN
NOM,LDO4
0.3V with 2.4V minimum,
set to any
V
NOM,LDO4
voltage
Maxim Integrated
17
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
= V
MIN
TYP
MAX
UNITS
V
IN,LDO4
NOM,LDO4
+ 0.3V to 5.5V with 1.7V
Normal mode
Green mode
minimum, I
=
set to
0.03
OUT,LDO4
0.1mA, V
NOM,LDO4
any voltage
Line Regulation
(Note 6)
%/V
V
= V
IN,LDO4
NOM,LDO4
+ 0.3V to 5.5V with 2.4V
minimum, I
=
0.1
OUT,LDO4
0.1mA, V
set to
NOM,LDO4
any voltage
V
3.7V
=
IN,LDO4
60
120
300
I
I
=
OUT,LDO4
MAX,LD04
Normal mode
Green mode
V
=
IN,LDO4
Dropout Voltage
V
150
mV
mA
DO,LDO4
1.7V
I
= 5mA,
= 3.7V
OUT,LDO4
50
100
375
V
IN,LDO4
Output Current Limit
I
V
= 0V
150
225
LIM,LDO4
OUT,LDO4
Normal mode, V
= V
+
IN,LDO4
NOM,LDO4
0.3V to 5.5V with 1.7V absolute minimum.
I
I
t
= 1% to 100% to 1% of
66
25
5
OUT,LDO4
, V
set to any voltage,
MAX,LDO4 NOM,LD04
Output Load Transient
(LDO4OVCLMP_EN = 1)
(Notes 3, 6)
= t = 1Fs, LDO4COMP[5:4] = 01
R4
F4
mV
Green mode, V
= V
+
IN,LDO4
NOM,LDO4
0.3V to 5.5V with 2.4V absolute minimum,
= 0.05mA to 5mA to 0.05mA,
I
V
t
OUT,LDO4
set to any voltage,
NOM,LDO4
= t = 1Fs
R4
F4
Normal mode, V
0.3V to V
= V
+
IN,LDO4
NOM,LDO4
+ 0.8V to V
+
NOM,LDO4
NOM,LDO4
0.3V with 1.7V absolute minimum,
= t = 1Fs, I = I ,
MAX,LDO4
t
R4
F4
OUT,LDO4
V
set to any voltage
NOM,LDO4
Output Line Transient
(Notes 3, 6)
mV
Green mode, V
to V
= V
+ 0.3V
+ 0.3V
IN,LDO4
NOM,LDO4
+ 0.8V to V
NOM,LDO4
NOM,LDO4
with 2.4V absolute minimum, t = t = 1Fs,
5
R4
= 5mA, V
NOM,LDO4
F4
I
OUT,LDO4
set to any voltage
Maxim Integrated
18
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f = 1kHz
63
Rejection from
f = 10kHz
51
44
57
33
50
V
V
I
to
V
=
+
IN,LDo4
INLDO4DC
V
OUT,LDO4
OUT,LDO4
NOM,LDO4
0.3V,
f = 100kHz
f = 1000kHz
f = 4450kHz
= 10% of
V
=
Power-Supply Rejection
PSRR
INLDO4AC
dB
LDO4
I
50mV
MAX,LDO4
Green mode, I
rejection from V
= 1mA, f = 1kHz,
OUT,LDO4
to V
IN,LDO4
OUT,LDO4
V
V
V
= 0.8V
= 1.8V
= 3.7V
45
45
OUT
OUT
OUT
f = 10Hz to
Output Noise
100kHz, I
=
FV
RMS
OUT
10% of I
MAX
60
100
5
LDO4SS = 0
LDO4SS = 1
Startup Ramp Rate
t
After enabling
mV/Fs
kI
SS4
Active discharge enabled,
LDO4ADE = 1
0.16
0.3
V
OUT,LDO4
Active-Discharge Resistance
= 1V, output
disabled
Active discharge disabled,
LDO4ADE = 0
1000
Clamp Active Regulation
Voltage
Clamp active (LDO4OVCLMP_EN = 1),
LDO output sinking 0.1mA
V
NOM,
LDO4
V
Clamp Disabled Overvoltage
Sink Current
V
= V
x 110%
2.2
10
60
FA
OUT,LDO4
NOM,LDO4
Ramp rate = 100mv/
Time from LDO
enable command
received to the
Fs
Enable Delay (Note 3)
Disable Delay (Note 3)
t
Fs
Fs
LON4
Ramp rate = 5mv/Fs
output starting to slew
After LDO is disabled; the LDO output
voltage discharges based on load and
C
0.1
10
; to ensure fast discharge times
OUT,LDO4
enable the active discharge resistor
Transition time from Green
Mode to Normal Mode
Fs
NC
Output
disabled or
enabled
T rising
165
150
J
Thermal Shutdown
T falling
J
Maxim Integrated
19
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OUT,LDO4
V
V
rising
falling
92
95
OUT,LDO4
OUT,LDO4
Power-OK Threshold
V
when V
switches
%
POKTHL4
POK
84
87
25
V
pulsed from 100% to 80% of
OUT,LDO4
Power-OK Noise Pulse Immunity
V
Fs
POKNF4
regulation
LDO5
Input Voltage Range
V
1.7
0.8
5.5
1.7
V
V
IN,LDO5
V
UVLO,
LDO5
Undervoltage Lockout
V
rising, 100mV hysteresis
is the maximum of 3.7V or
1.6
IN,LDO5
V
V
V
OUT,
IN,LDO5
Output Voltage Range
3.95
V
+ 0.3V
LDO5
OUT,LDO5
Normal mode
Green mode
300
5
Maximum Output Current
Minimum Output Capacitance
I
mA
FF
MAX,LDO5
Normal mode
Green mode
0.7
0.7
C
(Note 3)
OUT,LDO5
Time to enable LDO bias only,
central bias is already enabled
Bias Enable Time
t
90
10
0
Fs
LBIAS5
Bias Enable Currents
I
LDO bias enabled
FA
QBIAS5
Shutdown, T = +25NC
A
(Note 4)
AV Supply Current
INB Supply Current
I
No load
No load
FA
FA
AV,LDO5
Normal regulation
Green mode
3
6
3
0.5
Shutdown, T = +25NC
(Note 5)
A
0
I
IN,LDO5
Normal regulation
Green mode
17
1
30
3
V
= V
NOM,LDO5
IN,LDO5
+ 0.3V to 5.5V with 1.7V
minimum, I
=
OUT,LDO5
Normal mode
Green mode
-3
-5
+3
+5
0.1mA to I
,
MAX,LDO5
V
set to any
NOM,LDO5
voltage
Output Voltage Accuracy
%
V
= V
NOM,LDO5
IN,LDO5
+ 0.3V to 5.5V with 2.4V
minimum, I
=
OUT,LDO5
0.1mA to 5mA, V
NOM,LDO5
set to any voltage
Maxim Integrated
20
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
= 0.1mA to
OUT,LDO5
, V
=
MAX,LDO5 IN,LDO5
Normal mode
Green mode
Normal mode
Green mode
V
+ 0.3V with
0.1
NOM,LDO5
1.7V minimum, V
set to any voltage
NOM,LDO5
Load Regulation
(Note 6)
%
I
= 0.1mA to
OUT,LDO5
5mA, V
=
IN,LDO5
V
+ 0.3V with
0.2
0.03
0.1
NOM,LDO5
2.4V minimum, V
set to any voltage
NOM,LDO5
V
= V
IN,LDO5
NOM,LDO5
+ 0.3V to 5.5V with 1.7V
minimum. I
0.1mA, V
any voltage
=
OUT,LDO5
set to
NOM,LDO5
Line Regulation
(Note 6)
%/V
V
= V
IN,LDO5
NOM,LDO5
+ 0.3V to 5.5V with 2.4V
minimum. I
=
OUT,LDO5
0.1mA, V
set to
NOM,LDO5
any voltage
V
3.7V
=
IN,LDO5
50
100
450
I
I
=
OUT,LDO5
MAX,LDO5
Normal mode
Green mode
V
=
IN,LDO5
Dropout Voltage
V
150
mV
mA
DO,LDO5
1.7V
I
= 5mA,
= 3.7V
OUT,LDO5
150
450
300
750
V
IN,LDO5
Output Current Limit
I
V
= 0V
300
LIM,LDO5
OUT,LDO5
Normal mode, V
= V
+
IN,LDO5
NOM,LDO5
0.3V to 5.5V with 1.7V absolute minimum,
I
I
t
= 1% to 100% to 1% of
66
25
OUT,LDO5
, V
set to any voltage,
MAX,LDO5 NOM,LDO5
Output Load Transient
(LDO5OVCLMP_EN = 1)
(Notes 3, 6)
= t = 1Fs, LDO5COMP[5:4] = 01
R5
F5
mV
Green mode, V
= V
+
IN,LDO5
NOM,LDO5
0.3V to 5.5V with 2.4V absolute minimum,
= 0.05mA to 5mA to 0.05mA,
I
OUT,LDO5
V
set to any voltage,
NOM,LDO5
t
= t = 1Fs
R5
F5
Maxim Integrated
21
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
Normal mode, V = V
MIN
TYP
MAX
UNITS
+
IN,LOD5
NOM,LDO5
0.3V to V
+ 0.8V to V
+
NOM,LDO5
NOM,LDO5
0.3V with 1.7V absolute minimum,
= t = 1Fs, I = I ,
MAX,LDO5
5
t
R5
F5
OUT,LDO5
V
set to any voltage
NOM,LDO5
Output Line Transient
(Notes 3, 6)
mV
Green mode, V
to V
= V
+ 0.3V
+ 0.3V
IN,LDO5
NOM,LDO5
+ 0.8V to V
NOM,LDO5
NOM,LDO5
with 2.4V absolute minimum,
5
t
= t = 1Fs, I = 5mA,
R5
F5
OUT,LDO5
V
set to any voltage
NOM,LDO5
f = 1kHz
63
51
44
57
33
50
Rejection from
f = 10kHz
V
V
to
V
V
0.3V
=
+
IN,LDO5
INLDO5DC
OUT,LDO5
NOM,LDO5
I
f = 100kHz
f = 1000kHz
f = 4450kHz
OUT,LDO5
= 10% of
V
=
Power-Supply Rejection
PSRR
INLDO5AC
dB
LDO5
I
50mV
MAX,LDO5
Green mode, I
rejection from V
= 1mA, f = 1kHz,
OUT
to V
IN,LDO5
OUT,LDO5
V
V
V
= 0.8V
= 1.8V
= 3.7V
45
45
60
OUT,LDO5
f = 10Hz to
100kHz,
Output Noise
FV
RMS
OUT,LDO5
I
I
= 10% of
OUT
MAX,LDO5
OUT,LDO5
LDO5SS = 0
LDO5SS = 1
100
5
Startup Ramp Rate
t
After enabling
mV/Fs
kI
SS5
Active discharge enabled,
LDO5ADE = 1
0.16
0.3
V
OUT,LDO5
Active-Discharge Resistance
= 1V, output
disabled
Active discharge disabled,
LDO5ADE = 0
1000
Clamp Active Regulation
Voltage
Clamp active (LDO5OVCLMP_EN = 1),
LDO output sinking 0.1mA
V
NOM,
LD05
V
Maxim Integrated
22
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
x 110%
NOM,LDO5
MIN
TYP
MAX
UNITS
Clamp Disabled Overvoltage
Sink Current
V
= V
2.2
FA
OUT,LDO5
Ramp rate =100mV/
Fs
Time from LDO
enable command
received to the
10
60
Enable Delay (Note 3)
Disable Delay (Note 3)
t
Fs
Fs
LON5
Ramp rate = 5mV/
Fs
output starting to slew
After LDO is disabled; the LDO output
voltage discharges based on load and
0.1
10
C
; to ensure fast discharge times, enable
OUT
the active discharge resistor
Transition Time from Green
Mode to Normal Mode
Fs
NC
Output
disabled or
enabled
T rising
165
150
92
J
Thermal Shutdown
T falling
J
V
OUT,LDO5
V
V
rising
falling
95
OUT,LDO5
OUT,LDO5
Power-Ok Threshold
V
V
when V
switches
%
POKTHL
POK
84
87
V
pulsed from 100% to 80% of
OUT,LDO5
Power-Ok Noise Pulse Immunity
V
25
Fs
POKNF
regulation
LDO6
Input Voltage Range
Undervoltage Lockout
1.7
0.8
5.5
1.7
V
V
IN,LDO6
V
Rising, 100mV hysteresis
1.6
UVLO,LDO6
V
V
is the maximum of 3.7V or
IN,LDO6
Output Voltage Range
V
3.95
V
OUT,LDO6
+ 0.3V
OUT,LDO6
Normal mode
Green mode
150
5
Maximum Output Current
Minimum Output Capacitance
I
mA
FF
MAX,LDO6
Normal mode
Green mode
0.7
0.7
C
(Note 3)
OUT,LDO6
Time to enable LDO bias only, central
bias is already enabled
Bias Enable Time
t
90
10
0
Fs
LBIAS6
Bias Enable Currents
I
LDO bias enabled
FA
QBIAS6
Shutdown, T = +25NC
A
(Note 4)
AV Supply Current
I
No load
No load
FA
FA
AV,LDO6
Normal regulation
Green mode
3
6
3
0.5
Shutdown, T = +25NC
(Note 5)
A
0
INB Supply Current
I
IN,LDO6
Normal regulation
Green mode
15
1
30
3
Maxim Integrated
23
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
= V
MIN
TYP
MAX
UNITS
V
IN,LDO6
NOM,LDO6
+ 0.3V to 5.5V with 1.7V
minimum, I
=
OUT,LDO6
Normal mode
-3
-5
+3
0.1mA to I
,
MAX,LDO6
V
set to any
NOM,LDO6
voltage
Output Voltage Accuracy
%
V
= V
NOM,LDO6
IN,LDO6
+ 0.3V to 5.5V with 2.4V
Green mode
Normal mode
Green mode
Normal mode
Green mode
minimum, I
=
+5
OUT,LDO6
0.1mA to 5mA, V
set to any voltage
NOM,LDO6
I
I
= 0.1mA to
OUT,LDO6
, V
=
MAX,LDO6 IN,LDO6
V
+ 0.3V with
0.1
0.2
NOM,LDO6
1.7V minimum, V
NOM,LDO6
set to any voltage
Load Regulation
(Note 6)
%
I
= 0.1mA to 5mA,
OUT,LDO6
V
= V
+
IN,LDO6
NOM,LDO6
0.3V with 2.4V minimum,
V
set to any
NOM,LDO6
voltage
V
= V
NOM,LDO6
IN,LDO6
+ 0.3V to 5.5V with 1.7V
minimum, I
=
set to
0.03
0.1
OUT,LDO6
0.1mA, V
NOM,LDO6
any voltage
Line Regulation
(Note 6)
%/V
V
= V
IN,LDO6
NOM,LDO6
+ 0.3V to 5.5V with 2.4V
minimum, I
=
OUT,LDO6
0.1mA, V
set to
NOM,LDO6
any voltage
V
3.7V
=
IN,LDO6
60
120
300
I
I
=
OUT,LDO6
MAX,LDO6
Normal mode
Green mode
mV
mA
V
1.7V
=
IN,LDO6
Dropout Voltage
V
150
DO,LDO6
I
V
= 5mA,
= 3.7V
OUT,LDO6
50
100
375
IN,LDO6
Output Current Limit
I
V
= 0V
150
225
LIM,LDO6
OUT,LDO6
Maxim Integrated
24
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
Normal mode, V = V
MIN
TYP
MAX
UNITS
+
NOM,LDO6
IN,LDO6
0.3V to 5.5V with 1.7V absolute minimum,
I
I
t
= 1% to 100% to 1% of
66
OUT,LDO6
, V
set to any voltage,
MAX,LDO6 NOM,LDO6
Output Load Transient
(LDO6OVCLMP_EN = 1)
(Notes 3, 6)
= t = 1Fs, LDO6COMP[5:4] = 01
R6
F6
mV
Green mode, V
= V
NOM,LDO6
IN,LDO6
+0.3V to 5.5V with 2.4V absolute minimum,
I
V
= 0.05mA to 5mA to 0.05mA,
25
5
OUT,LDO6
set to any voltage,
NOM,LDO6
t
= t = 1Fs
R6
F6
Normal mode, V
0.3V to V
= V
+
IN,LDO6
NOM,LDO6
+ 0.8V to V
+
+
NOM,DLo6
NOM,LDO6
0.3V with 1.7V absolute minimum,
= t = 1Fs, I = I
MAX,LDO6
t
V
,
R6
F6
OUT,LDO6
set to any voltage
NOM,LDO6
Output Line Transient
(Notes 3, 6)
mV
Normal mode, V
0.3V to V
= V +
NOM,LDO6
IN,LDO6
+ 0.8V to V
NOM,DLo6
NOM,LDO6
0.3V with 2.4V absolute minimum,
5
t
= t = 1Fs, I = 5mA,
R6
F6
OUT,LDO6
V
set to any voltage
NOM,LDO6
f = 1kHz
63
51
44
57
33
50
Rejection from
f = 10kHz
V
V
0.3V,
=
+
INLOD6DC
V
V
to
IN,LDO6
NOM,LDO6
OUT,LDO06
f = 100kHz
f = 1000kHz
f = 4450kHz
I
OUT,LDO6
V
=
Power-Supply Rejection
PSRR
INLDO6AC
dB
LDO6
= 10% of
50mV
I
MAX,LDO6
Green mode, I
rejection from V
= 1mA, f = 1kHz,
OUT,LDO6
to V
IN,LDO6
OUT,LDO6
Maxim Integrated
25
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f = 10Hz
to 100kHz,
V
= 0.8V
45
OUT,LDO06
Output Noise
I
FV
RMS
OUT,LDO6
V
V
= 1.8V
= 3.7V
45
60
OUT,LDO06
= 10% of
I
OUT,LDO06
MAX,LDO6
LDO6SS = 0
LDO6SS = 1
100
5
Startup Ramp Rate
t
After enabling
mV/Fs
kI
SS,LDO6
Active discharge enabled,
LDO6ADE = 1
0.16
0.3
V
OUT,LDO6
Active-Discharge Resistance
= 1V, output
disabled
Active discharge disabled,
LDO6ADE = 0
1000
Clamp Active Regulation
Voltage
Clamp active (LDO6OVCLMP_EN = 1),
LDO output sinking 0.1mA
V
NOM,
LDO6
V
Clamp Disabled Overvoltage
Sink Current
V
= V
x 110%
2.2
10
60
FA
OUT,LDO6
NOM,LDO6
Ramp rate =
100mV/Fs
Time from LDO
enable command
received to the
Enable Delay (Note 3)
Disable Delay (Note 3)
t
Fs
Fs
LON6
Ramp rate = 5mV/
output starting to slew
Fs
After LDO is disabled, the LDO output
voltage discharges based on load and
C
0.1
10
; to ensure fast discharge times,
OUT,LDO6
enable the active discharge resistor
Transition Time from Green
mode to Normal Mode
Fs
NC
Output
disabled or
enabled
T rising
165
150
92
J
Thermal Shutdown
T falling
J
V
OUT,LDO6
V
V
LDO6 rising
95
OUT,
Power-OK Threshold
V
when V
switches
%
POKTHL6
POK
falling
84
87
OUT,LDO6
Power-OK Noise Pulse
Immunity
V
pulsed from 100% to 80% of
OUT,LDO6
V
25
Fs
POKNF6
regulation
DIGITAL I/O
V
V
V
, EN_, SDA, SCL,
ID_
Logic Input High Voltage
Threshold
V
= V
= V = 2.6V to 5.5V
1.4
V
V
IH
IN1
IN2
AV
= 1.65V to 3.6V
IO
V
V
V
, EN_, SDA, SCL,
ID_
Logic Input Low Voltage
Threshold
V
= V
= V = 2.6V to 5.5V
0.4
IL
IN1
IN2
AV
= 1.65V to 3.6V
IO
Maxim Integrated
26
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(V
= V = 3.6V, V = 1.8V, T = -40NC to +85NC, unless otherwise noted. Typical values are T = +25NC.) (Note 2)
_
IN
AV
IO
A
A
PARAMETER
Logic Input Current (SDA, SCL)
SYMBOL
CONDITIONS
MIN
-1
TYP
MAX
UNITS
V
V
= 0V or
= 3.6V,
IL
T
T
= +25NC
= +85NC
+1
A
FA
IH
0.1
0.1
EN_ = AGND
A
T
T
= +25NC
= +85NC
-1
+1
V
= 0V,
A
IL
Logic Input Current (V , EN_)
FA
kI
ID_
EN_ = AGND
A
V
, EN_ Logic Input
ID_
400
Pulldown Resistor
I2C INTERFACE
SDA Output Low Voltage
I2C Clock Frequency
I
= 3mA
0.1
V
SDA
400
kHz
Bus-Free Time Between START
and STOP
t
See Figure 7 in the Digital I/O section
See Figure 7 in the Digital I/O section
1.3
0.6
Fs
Fs
BUF
Hold Time Repeated START
Condition
t
t
0.1
HD_STA
SCL Low Period
SCL High Period
t
See Figure 7 in the Digital I/O section
See Figure 7 in the Digital I/O section
1.3
0.6
0.2
0.1
Fs
Fs
LOW
t
HIGH
Setup Time Repeated START
Condition
See Figure 7 in the Digital I/O section
0.6
0.1
Fs
SU_STA
HD_DAT
SDA Hold Time
SDA Setup Time
t
See Figure 7 in the Digital I/O section
See Figure 7 in the Digital I/O section
0
-0.01
0.05
Fs
Fs
t
0.1
SU_DAT
Maximum pulse width of spikes that must
be suppressed by the input filter of both the
DATA and CLK pins
Glitch Filter
50
ns
Setup Time for STOP Condition
t
See Figure 7 in the Digital I/O section
0.6
0.1
Fs
SU_STO
Note 2: Specifications are 100% production tested at T = +25NC. Limits over the operating temperature range are guaranteed by
A
design and characterization. LDO_COMP = 01 (default).
Note 3: V
is limited to approximately: V - (inductor DCR + output trace resistance + 100mI) x I
.
OUT
IN
OUT
Note 4: Values are based on simulations and bench testing; they are not production tested.
Note 5: System shutdown current is guaranteed by testing the combined current part in shutdown in the main bias section.
Note 6: IN shutdown current is guaranteed by testing the combined current of all IN_ and LDO_ pins in shutdown to a 5FA (max).
Note 7: Does not include ESR of the capacitance or trace resistance of the module/PCB.
Maxim Integrated
27
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics
(V
IN_
= V
AV
= 3.6V, V = 1.8V, Typical Application Circuit, T = +25NC, unless otherwise noted.)
IO
A
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
60
60
55
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
55
50
45
40
35
30
25
20
15
10
5
STEP-DOWN 1 IN GREEN MODE,
PFM LDOs DISABLED
STEP-DOWN 1 WITH REMOTE
SENSE OFF, PFM LDOs DISABLED
STEP-DOWN 1 WITH REMOTE
SENSE ON, PFM LDOs DISABLED
0
0
0
2.5
2.5
2.5
3.5
4.5
5.5
5.5
5.5
2.5
3.5
4.5
5.5
2.5
3.5
4.5
5.5
5.5
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
60
55
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
60
55
50
45
40
35
30
25
20
15
10
5
STEP-DOWNs DISABLED
, LDO1 = 1V IN GREEN MODE
STEP-DOWNs DISABLED
, LDO1 = 1V IN NORMAL MODE
STEP-DOWNs IN GREEN MODE
LDOs1 = 1V IN GREEN MODE
V
V
OUT
OUT
0
0
0
3.5
4.5
2.5
3.5
4.5
5.5
2.5
3.5
4.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
STANDBY CURRENT
vs. INPUT VOLTAGE
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
60
55
50
45
40
35
30
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
V
V
V
V
= 4.2V
= 3.6V
= 3.0V
= 2.6V
BATT
BATT
BATT
BATT
V
= 4.2V
BATT
V
V
V
= 3.6V
BATT
= 3.0V
= 2.6V
BATT
BATT
V
= 1.2V, FPWM, REMOTE
OUT
SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
STEP-DOWNs DISABLED
LDOs1 = DISABLED
V
= 1.2V, PFM, REMOTE SENSE DISABLED,
OUT
L = 1µH (TOKO DFE252010R-1R0N)
0
3.5
4.5
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
INPUT VOLTAGE (V)
LOAD CURRENT (A)
LOAD CURRENT (A)
Maxim Integrated
28
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(V
IN_
= V
AV
= 3.6V, V = 1.8V, Typical Application Circuit, T = +25NC, unless otherwise noted.)
IO
A
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
V
= 4.2V
= 3.6V
= 3.0V
= 2.6V
V
V
V
= 4.2V
= 3.6V
= 3.2V
BATT
BATT
BATT
BATT
BATT
BATT
BATT
V
V
V
V
= 1.8V, PFM, REMOTE SENSE DISABLED,
OUT
L = 1µH (TOKO DFE252010R-1R0N)
V
= 2.8V, PFM, REMOTE SENSE DISABLED,
OUT
L = 1µH (TOKO DFE252010R-1R0N)
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
STEP-DOWN LOAD REGULATION
100
95
90
85
80
75
70
65
60
55
50
1.220
1.215
1.210
1.205
1.200
1.195
1.190
1.185
1.180
V
V
V
V
= 4.2V
= 3.6V
= 3.0V
= 2.6V
BATT
BATT
BATT
BATT
V
V
V
V
= 5.5V
= 4.2V
= 3.6V
= 3.0V
BATT
BATT
BATT
BATT
V
= 0.6V, PFM, REMOTE SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
OUT
FPWM, REMOTE SENSE ENABLED
0.001
0.01
0.1
1
10
0
0.5
1.0
1.5
2.0
LOAD CURRENT (A)
LOAD CURRENT (mA)
V
TRANSTION
V TRANSTION
ID
(12.5mV/µs SLEW)
ID
(12.5mV/µs SLEW)
MAX8967 toc14
MAX8967 toc15
3.38V
3.38V
V
OUT1
0.6V
V
OUT1
0.6V
V = 4.2V
IN
V
= 4.2V
IN
40µs/div
40µs/div
Maxim Integrated
29
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(V
IN_
= V
AV
= 3.6V, V = 1.8V, Typical Application Circuit, T = +25NC, unless otherwise noted.)
IO
A
STEP-DOWN LOAD TRANSIENT
STEP-DOWN LOAD TRANSIENT
MAX8967 toc17
MAX8967 toc16
V
= 3.6V
IN
SKIP MODE
V
= 1.2V
1.2A
OUT
200mA
5mA
I
OUT
OUT
I
OUT
200mA
V
V
50mV/div
OUT
50mV/div
AC-COUPLED
AC-COUPLED
V
V
= 3.6V
IN
= 1.2V
OUT
20µs/div
20µs/div
LDO1 OUTPUT VOLTAGE
vs. LOAD CURERNT
LDO2 OUTPUT VOLTAGE
vs. LOAD CURERNT
1.796
1.794
1.792
1.790
1.788
1.786
1.784
1.782
1.780
1.778
1.798
1.796
1.794
1.792
1.790
1.788
1.786
1.784
1.782
1.780
1.778
1.776
V = 4.2V
BATT
V
BATT
= 4.2V
0
50
100
150
0
100
200
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO4 OUTPUT VOLTAGE
vs. LOAD CURERNT
LDO3 OUTPUT VOLTAGE
vs. LOAD CURERNT
1.796
1.795
1.794
1.793
1.792
1.791
1.790
1.789
1.788
1.787
1.786
1.795
1.794
1.793
1.792
1.791
1.790
1.789
1.788
1.787
V
BATT
= 4.2V
V
BATT
= 4.2V
0
50
100
150
0
50
100
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Maxim Integrated
30
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(V
IN_
= V
AV
= 3.6V, V = 1.8V, Typical Application Circuit, T = +25NC, unless otherwise noted.)
IO
A
LDO5 OUTPUT VOLTAGE
vs. LOAD CURERNT
LDO6 OUTPUT VOLTAGE
vs. LOAD CURERNT
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.794
1.793
1.792
1.791
1.790
1.789
1.788
1.787
1.786
1.785
V
= 4.2V
BATT
V
= 4.2V
BATT
0
100
200
300
0
50
100
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO1 LINE REGULATION
MAX8967 toc24
1.7810
1.7805
1.7800
1.7795
1.7790
1.7785
1.7780
V
= 1.8V, NORMAL MODE, I = 150mA
OUT
OUT
100mA
1mA
I
, LDO1
, LDO1
OUT
V
OUT
50mV/div
AC-COUPLED
2.5
3.5
4.5
5.5
20µs/div
INPUT VOLTAGE (V)
LDO2 LINE REGULATION
LDO SLEW CONTROL (5mV/µs)
MAX8967 toc27
1.7795
1.7790
1.7785
1.7780
1.7775
1.7770
V
= 1.8V, NORMAL MODE, I = 300mA
OUT
OUT
3.95V
0.8V
V
= 4.2V
IN
NO LOAD
V
, LDO1
OUT
2.5
3.5
4.5
5.5
200µs/div
INPUT VOLTAGE (V)
Maxim Integrated
31
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(V
IN_
= V
AV
= 3.6V, V = 1.8V, Typical Application Circuit, T = +25NC, unless otherwise noted.)
IO
A
LDO OUTPUT VOLTAGE ACCURACY
vs. TEMPERATURE
LDO SLEW CONTROL (100mV/µs)
MAX8967 toc28
0.25
0.20
0.15
0.10
0.05
0
3.95V
0.8V
-0.05
-0.10
-0.15
-0.20
-0.25
V
= 4.2V
IN
NO LOAD
V
, LDO1
OUT
V
= 1V, NORMAL MODE
50 100
OUT,LDO1
-50
0
10µs/div
TEMPERATURE (°C)
STEP-DOWN SWITCHING FREQUENCY
vs. LOAD CURRENT
LIGHT LOAD WAVEFORMS
MAX8967 toc31
4.60
4.55
4.50
4.45
4.40
4.35
4.30
4.25
4.20
V
= 1V, FPWM
OUT1
AC-COUPLED
50mV/div
V
OUT1
2V/div
V
LX1
LX1
I
V
V
= 50mA
= 1.2V
OUT
OUT
0
500mA/div
= 3.6V
IN
0
I
0
500
1000
1500
2000
2µs/div
LOAD CURRENT (mA)
MODERATE LOAD WAVEFORMS
HEAVY LOAD WAVEFORMS
MAX8967 toc33
MAX8967 toc32
AC-COUPLED
50mV/div
AC-COUPLED
50mV/div
V
OUT1
V
OUT1
2V/div
2V/div
V
I
V
I
LX1
LX1
LX1
I
= 500mA
OUT
V
V
0
0
= 1.2V
OUT
= 3.6V
500mA/div
500mA/div
IN
I
V
V
= 1A
OUT
LX1
0
= 1.2V
0
OUT
= 3.6V
IN
100µs/div
100ns/div
Maxim Integrated
32
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Applications Circuit
INPUT
2.6V TO 5.5V
IN1
IN2
AV
SNSP1
OUT1
C
IN1,2
10µF
OUT1
0.6V TO 3.3875V,
2A
1µH
LX1
C
1µF
AV
C
22µF
OUT1
SNSN1
PGND1
1.7V TO 5.5V
INA
C
INA,B
2.2µF
INB
SNSP2
OUT2
AGND
OUT2
0.6V TO 3.3875V,
2A
1µH
LX2
V
IO
C
22µF
OUT2
MAX8967
SNSN2
PGND2
1.65V TO 5.5V
V
IO
0.8V TO 3.95V, 150mA
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
SCL
SDA
EN1
EN2
C
LDO1
1µF
0.8V TO 3.95V, 300mA
C
LDO2
1µF
0.8V TO 3.95V, 150mA
C
LDO3
1µF
0.8V TO 3.95V, 150mA
V
IO
C
LDO4
1µF
V
V
ID1
ID2
0.8V TO 3.95V, 300mA
C
LDO5
1µF
0.8V TO 3.95V, 150mA
IRQB
C
LDO6
1µF
PGND AGND
Maxim Integrated
33
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX8967
1
2
3
4
5
6
+
PGND2
LX2
OUT2
AGND
EN2
EN1
A
B
C
D
E
IN2
SNSP2
SNSN2
V
LDO1
LDO4
ID2
SCL
IN1
SDA
V
IRQB
INA
INB
IO
SNSP1
SNSN1
OUT1
V
ID1
LDO2
LDO5
PGND1
LX1
AV
LDO3
LDO6
WLP
Pin Description
PIN
NAME
FUNCTION
Step-Down Converter 2 Power Ground. Bypass IN2 to PGND2 with a 10FF ceramic capacitor as close as
possible to the IC.
A1
PGND2
Step-Down Converter 2 Inductor Switching Node. Connect a 1FH inductor from LX2 to OUT2. LX2 is high
impedance when disabled.
A2
A3
LX2
Step-Down Converter 2 Output Sense and Discharge Connection. Bypass OUT2 to PGND2 with a 22FF
ceramic capacitor. OUT2 can also be connected to ground through an internal 100I resistor using an I2C
command when disabled.
OUT2
A4
A5
AGND
EN2
Analog Ground. Connect AGND to PGND_.
Enable Logic Input for Step-Down Converter 2. Step-down converter 2 can also be enabled through I2C.
EN2 has an internal 800kI pulldown resistor.
Enable Logic Input for Step-Down Converter 1. Step-down converter 1 can also be enabled through I2C.
EN1 has an internal 800kI pulldown resistor.
A6
B1
B2
EN1
IN2
Step-Down Converter 2 Input Supply. Bypass IN2 to PGND2 with a 10FF ceramic capacitor as close as
possible to the IC. Connect IN2 to both IN1 and AV.
Step-Down Converter 2 Positive Remote Voltage Sense. Connect SNSP2 to the positive terminal of the
OUT2 bypass capacitor.
SNSP2
Maxim Integrated
34
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Pin Description (continued)
PIN
B3
NAME
SNSN2
FUNCTION
Step-Down Converter 2 Negative Remote Voltage Sense. Connect SNSN2 to the negative terminal of the
OUT2 bypass capacitor.
Voltage Identification Digital 2. To toggle between two step-down converter 2 output voltages, toggle V
ID2
B4
V
ID2
logic-high and logic-low. V
has an internal 800kI pulldown resistor.
ID2
B5
B6
C1
C2
C3
LDO1
LDO4
SCL
LDO1 Output. Bypass LDO1 to AGND with a 1FF ceramic capacitor.
LDO4 Output. Bypass LDO4 to AGND with a 1FF ceramic capacitor.
I2C Clock Signal. Connect SCL to V with a 2.2kI pullup resistor.
IO
SDA
I2C Data Signal. Connect SCA to V with a 2.2kI pullup resistor.
IO
V
I/O Input Supply. Connect V to the I2C bus master’s power supply.
IO
IO
Interrupt Open-Drain Active-Low Output. IRQB signals if there is a fault. Connect IRQB to V with a
IO
100kI pullup resistor.
C4
C5
C6
D1
D2
D3
D4
IRQB
INA
Input Supply for LDOs 1, 2, and 3. Bypass INA to AGND with a 2.2FF ceramic capacitor as close as
possible to the IC.
Input Supply for LDOs 4, 5, and 6. Bypass INB to AGND with a 2.2FF ceramic capacitor as close as
possible to the IC.
INB
Power input for Step-Down Converter 1. Bypass IN1 to PGND1 as close as possible to the IC. Connect
IN1 to both IN2 and AV.
IN1
Step-Down Converter 1 Positive Remote Voltage Sense. Connect SNSP1 to the positive terminal of the
OUT1 bypass capacitor.
SNSP1
SNSN1
Step-Down Converter 1 Negative Remote Voltage Sense. Connect SNSN1 to the negative terminal of the
OUT1 bypass capacitor.
Voltage Identification Digital 1. To toggle between two different step-down converter 1 output voltages
V
ID1
toggle V
logic-high and logic-low. V
has an internal 800kI pulldown resistor.
ID1
ID1
D5
D6
LDO2
LDO5
LDO2 Output. Bypass LDO2 to AGND with a 1FF ceramic capacitor.
LDO5 Output. Bypass LDO5 to AGND with a 1FF ceramic capacitor.
Step-Down Converter 1 Power Ground. Bypass IN1 to PGND1 with a 10FF ceramic capacitor as close as
possible to the IC.
E1
E2
PGND1
LX1
Inductor Connection for Buck 1. LX is high impedance when disabled.
Step-Down Converter 1 Output Sense and Discharge Connection. Bypass OUT1 to PGND1 with a 22FF
ceramic capacitor.
E3
OUT1
OUT1 can also be connected to ground through an internal 100I resistor using an I2C command when
disabled.
Analog Input Supply. Connect AV to IN1 and IN2. Bypass AV to AGND with 1FF ceramic capacitor as
close as possible to the IC.
E4
AV
E5
E6
LDO3
LDO6
LDO3 Output. Bypass LDO3 to AGND with a 1FF ceramic capacitor.
LDO6 Output. Bypass LDO6 to AGND with a 1FF ceramic capacitor.
Maxim Integrated
35
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
core voltages are restored, providing the optimal operat-
ing condition for best system performance.
General Description
The MAX8967’s two ultra-low I step-down converters
Q
Remote Output Voltage Sensing
Each step-down converter’s output features remote out-
put voltage sensing for improved output voltage accu-
racy. The remote sense accommodates a distance that
incures up to a 200mV correction in the output voltage.
The SNSP_ and SNSN_ inputs connect directly across
the load, with the SNSN_ connected to a quiet analog
ground near the load, and SNSP_ connected directly to
the output bypass capacitor.
are ideal for powering modems, applications processor
cores, memory, system I/O, and portable devices. In
normal operation, these step-down converters consume
only 16FA (typ) of quiescent current. In green mode, the
quiescent current is reduced to 5FA (typ) per converter
with reduced load capability. Each step-down converter
can be independently put into green mode by writing a
bit in its control register.
Step-Down Converters
Each step-down converter provides internal feed-
back, minimizing external component count. Both
step-down converter output voltages are programmed
through the IC’s serial interface. A 4.4MHz switching
frequency minimizes external component size.
Dynamic voltage scaling is available to reduce power
consumption. Both step-down converters feature auto-
matic transition from skip mode to FPWM operation.
Forced PWM operation can be enabled by writing a bit
in a control register.
The remote sense feature requires a 1V or greater differ-
ence between AV and OUT_ for best performance. The
remote sense feature can be disabled through registers
to reduce quiescent current consumption. In addition,
this feature is disabled during green mode operation.
Output Voltage Slew Rate
Both step-down converters feature an adjustable slew
rate when increasing or decreasing output voltage. The
nominal slew rate is 12.5mV/Fs. Two additional slew rates
are provided (25mV/Fs and 50mV/Fs), so that faster and
slower slew rates can be programmed. An option for
fastest possible ramp rate is also provided to allow the
converter to operate at current limit for the fastest pos-
sible slew rate.
Interleaved Switching
The step-down converter’s high-side switches turn on
during opposite clock edges of the oscillator. This helps
minimize input current ripple, thus reducing the input
capacitance required to reduce input voltage ripple.
When decreasing the output voltage, two settings are
provided with a single register bit. When this control bit is
set, the converter operates in forced PWM (FPWM) mode
with negative inductor current so that the output voltage
can be decreased in finite steps at the selected slew
rate. When this control bit is reset, the converter operates
in skip mode, and the actual slew rate of the output is
dependent on the external load, and might not necessar-
ily track the slew rate set for falling output voltages.
Skip Mode/FPWM Operation
In the normal operating state, both step-down converters
automatically transition from skip mode to fixed-frequency
operation as load current increases. For operating
modes where lowest output ripple is required, forced
PWM switching behavior can be enabled by writing a
bit in the appropriate FPWM_ register. See Table 3 and
Table 15.
Output Ripple
Voltage Control Using V
For normal operation (not in green mode), output ripple
ID
Both step-down converters feature V control to reduce
should be < 20mV
for an output current < 50mA.
ID
P-P
power consumption in the loads such as modem and
Ripple can be further reduced by increasing output
capacitance above the minimum for stable operation.
Transition from skip to PWM operation should occur at
current levels below 50mA. In green mode, the output
applications processor cores. Each V control allows
ID
the converter to transition between two states setup in
advance using I2C. Essentially two voltage states are
accessible without the overhead associated with I2C con-
ripple can increase to 40mV
(max) for V
= 0.7V.
P-P
OUT_
trol. V control allows the core voltages to be reduced
when the processor clock is throttled back. When exiting
This value can be decreased by adding additional output
capacitance.
ID
sleep mode (by changing the state of V ), the normal
ID
Maxim Integrated
36
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Green Mode Operation
In green mode, the quiescent current of each of the
step-down converters are reduced from 16FA (typ) to
5FA (typ). If the output voltages are adjusted during
green mode slew rate is very slow. Also, output current
is limited to 5mA. Green mode is enabled by setting bits
PWR_[5:4] = 10 in the appropriate converter’s control
register. See Table 3. Each converter can be individually
selected to enter green mode.
Discharge Resistance
The IC provides an internal 100I discharge resistor for
each disabled step-down converter. The discharge resis-
tor connection can be enabled and disabled through the
nADEN_ register bit for maximum flexibility. See Table 3.
LDO Detailed Description
The IC provides six LDOs with adjustable outputs as
shown in Table 1.
Shutdown, Standby, and Reset
SHUTDOWN
= EN1 = EN2 = 0V
V
IO
I
= 0µA
Q
NO VALID SUPPLY FOR
VALID SUPPLY FOR
V /IN1/IN2/AV
IO
AND EN1 = EN2 = 0 AND
TEMPERATURE IN RANGE
V
IO
/IN1/IN2/AV OR
TEMPERATURE
NOT IN RANGE
NO VALID SUPPLY FOR
/IN1/IN2/AV
VALID SUPPLY FOR
V /IN1/IN2/AV
IO
AND TEMPERATURE
IN RANGE EN_ = 1
STANDBY
REFERENCE ON
V
IO
AND EN1 = EN2 = 0
I
= 20µA
Q
PWR1 _[5:4] = 00 AND
PWR2 _[5:4] = 00 AND
EN1 = EN2 = 0V AND
A VALID VIO SUPPLY
PWR1 _[5:4] ≠ 00 OR
PWR2 _[5:4] ≠ 00
STEPDOWN
CONVERTER
1 OR 2 IS ON
Figure 1. Power Mode State Diagram
Table 1. LDO Description
MAXIMUM OUTPUT
CURRENT (mA)
LDO
V
_ RANGE (V)
INPUT SUPPLY
V
RANGE (V)
C
(FF)
IN
OUT
OUT
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
INA
INA
INA
INB
INB
INB
0.8 to 3.95
0.8 to 3.95
0.8 to 3.95
0.8 to 3.95
0.8 to 3.95
0.8 to 3.95
150
300
150
150
300
150
1
1
1
1
1
1
Maxim Integrated
37
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
LDO Power Modes
All LDO regulators have independent enable and
disable control through their LDO_PWR[7:6] bits. In
addition, each LDO has a special green mode that
reduces the quiescent current to 1.5FA (typ). In green
mode, each regulator supports a load of up to 10mA. The
load regulation performance degrades proportionally
with the reduced load current.
Active Discharge
Each linear regulator has an active-discharge resistor
feature that can be enabled/disabled with the LDO_ADE
bit. See Table 3 and Table 20. Enabling the active
discharge feature helps ensure a complete and time-
ly power-down of all system peripherals. The default
condition of the active-discharge resistor feature is
enabled so that whenever VUVLO,LDO_ is below its
UVLO threshold, all regulators are disabled with their
active discharge resistors turned on. When VUVLO,LDO_
is less than 1.0V, the NMOS transistors that control
the active discharge resistors lose their gate drive and
become open.
Several usage options are available for green mode.
To force individual regulators to green mode set LDO_
PWR[7:6] = 10.
Soft-Start and Dynamic Voltage Change
The LDO regulators have a programmable soft-start rate.
When an LDO is enabled, the output voltage ramps to its
final voltage at a slew rate of either 5mV/Fs or 100mV/Fs,
depending on the state of the LDO_SS bit. See Table 3
and Table 20.
When the regulator is disabled while the active discharge
is disabled, the internal active-discharge resistor is not
connected to its output and the output voltage decays at
a rate that is determined by the output capacitance and
the external load.
The 5mV/Fs ramp rate limits the input inrush current to
around 5mA on a 300mA regulator with a 1FF output
capacitor and no load. The 100mV/Fs ramp rate results in
a 100mA inrush current with a 1FF output capacitor and
no load, but achieves regulation within 50Fs. The soft-
start ramp rate is also the rate of change at the output
when switching dynamically between two output voltages
without disabling.
When the regulator is enabled, the internal active-
discharge resistor is not connected to its output. When
the regulator is disabled while the active discharge is
enabled, an internal active-discharge resistor is con-
nected to its output which discharges the energy stored
in the output capacitance.
Adjustable Compensation
All six LDOs have adjustable compensation to facilitate
remote capacitor capability. This feature can be used to
adjust the compensation of the LDO based on the resis-
tance and inductance to the remote capacitor. This abil-
ity allows each LDO to be programmed for optimal load
transient performance based on the location of its remote
capacitor. See Table 20 for more details. The LDO com-
pensation should be switched only when that LDO is off.
If the compensation switches when the LDO is enabled,
it causes unknown output glitches, due to switching in
uncharged capacitors as compensation changes.
The soft-start circuitry of the LDOs supports starting into
a prebiased output.
Power-OK Comparator
Each regulator includes a power-OK (POK) compara-
tor. The POK comparator signals (LDO_POK) indicate
when each output has lost regulation (i.e., the output
voltage is below V ). The POK signal has a 25Fs
POKTHL
noise immunity filter (V ). The POK comparator
POKNF_
is disabled in green mode to save power. When any of
the POK signals (LDO_POK) go low, then an interrupt is
generated.
Overvoltage Clamp
Each LDO has an overvoltage clamp that allows it to sink
current when the output voltage is above its target volt-
age. This overvoltage clamp is default enabled but can
be disabled with LDO_OVCLMP_EN. See Table 3 and
Table 15. The following list briefly describes three typi-
cal applications scenarios that pertain to the overvoltage
clamp.
Note that the LDOs implement a proprietary POK scheme
that allows the POK comparator to operate correctly even
while the LDO is in its soft-start period. If the LDO is over-
loaded when it is in its soft-start period, POK is low. If it
is not overloaded during its soft-start period, POK is high.
Maxim Integrated
38
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
•ꢀ LDO’s Load Leaking Current into the LDO’s
heat dissipated can exceed the maximum junction tem-
perature of the part. If the junction temperature reaches
approximately +165NC, the thermal overload protection
is activated.
Output: Some LDO loads leak current into an
LDO output during certain operating modes.
This is typically seen with microprocessor loads.
For example, a microprocessor with 3.3V, 2.5V,
1.8V, and 1.0V supply rails is running in standby
mode. In this mode, the higher voltage rails can
leak currents of several mA into the lower voltage
rails. If the 1.0V rail is supplied by an LDO, the
LDO output voltage rises based on the amount of
leakage current. With the LDO overvoltage clamp
enable, when the output voltage rises above its
target regulation voltage, the overvoltage clamp
sinks current from the output capacitor to bring
the output voltage back within regulation.
The IC maximum power dissipation depends on the
thermal resistance of the IC package and circuit board.
The power dissipated in the device is:
PD = P
×(1/η1 - 1) + P
× (1/η2 - 1)
OUT1
OUT2
where E1 and E2 are the efficiencies of each converter
while P and P are the output power of each
OUT1
OUT2
converter.
The maximum allowed power dissipation is:
P
= (T - T )/θ
JA
MAX
JMAX
A
•ꢀ Negative Load Transient to 0A: When the LDO
load current quickly ramps to 0A (i.e., 300mA to
0A load transient with 1Fs transition time), the
output voltage can overshoot (i.e., soar). Since
the LDO cannot turn off its pass device immedi-
ately, the LDO output voltage overshoots. In this
instance, when the output voltage sores above
target regulation voltage, the overvoltage clamp
sinks current from the output capacitor to bring
the output voltage back within regulation.
T
- T is the temperature difference between
A
the IC’s maximum rated junction temperature and the
surrounding air, B is the thermal resistance of the
junction through the PCB, copper traces, and other
materials to the surrounding air.
JMAX
JA
Digital Interface
The IC has four types of digital interface:
•ꢀ Twoꢀ enableꢀpinsꢀ (EN_),ꢀ oneꢀforꢀ eachꢀstep-downꢀ
•ꢀ Negative Dynamic Voltage Transition: When
the LDO output target voltage is decreased (i.e.,
1.2V to 0.8V) when the system loading is light,
the energy in the output capacitor tends to hold
the output voltage up. When the output voltage is
above its target regulation voltage, the overvolt-
age clamp sinks current from the output capacitor
to bring the output voltage back within regulation.
converter
•ꢀ Two V pins (V ), one for each step-down converter
ID ID_
•ꢀ Anꢀinterruptꢀpin,ꢀIRQB
•ꢀ Aꢀtwo-wireꢀI2C interface
The I2C interface is use to set the state of the IC while the
two enable and two V pins, one set for each step-down
converter, are used to rapidly transition between on/off
and two voltage and mode states previously defined
using I2C communication.
ID
LDO Interrupt
The power-OK comparators outputs drive a set of inter-
rupts. Each regulator is capable of generating an inter-
rupt, when the output goes out of regulation in normal
operation. In green mode, the POK comparators are
disabled and the regulators do not generate interrupts.
Enable (EN_)
Two enable logic input pins are provided to allow rapid
transitions between on and off for each step-down
converter. The enable pins work in conjunction with the
I2C step-down converter PWR MD (mode) bits to control
on/off, normal or green mode, and enabling/disabling of
remote sense per step-down converter. Each converter
can be enabled through the dedicated enable pin or
through the I2C with a logical OR function.
Thermal Considerations
In most applications, the IC does not dissipate much heat
due to its high efficiency. But in applications where the IC
runs at high ambient temperature with heavy loads, the
Maxim Integrated
39
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Voltage Identification Digital (V
)
I2C Interface
ID_
pins are provided to allow rapid transitions
2
Two V
An I C-compatible, 2-wire serial interface controls the
step-down converter output voltage, ramp rate, operat-
ing mode, and synchronization. The serial bus consists
of a bidirectional serial-data line (SDA) and a serial-clock
input (SCL). The master initiates data transfer on the bus
and generates SCL to permit data transfer.
ID_
between two previously configured states for each step-
down converter. There are multiple registers for output
voltage and mode of operation for each converter as well.
IRQB
The IRQB is an active-low, open-drain output that signals
a fault on any one or more of the step-down converters or
LDOs. Each converter and LDO is individually monitored
for its POK status, and thermal shutdown for the entire
MAX8967 is monitored.
2
I C is an active-low open-drain bus. SDA and SCL
require pullup resistors (500Ior greater). Optional resis-
tors (24I) in series with SDA and SCL can protect the
device inputs from high-voltage spikes on bus lines.
Series resistors also minimize crosstalk and undershoot
on bus signals.
Table 2. Step-Down Converter Modes
Bit Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. See Figure 2. Changes in
SDA while SCL is high are control signals. See the START
and STOP Conditions section for more information.
EN_
0
I2C MD BITS
MODE
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Off
0
On, green
0
On, normal, remote sense on
On, normal, remote sense off
On, normal, remote sense on
On, green
0
Each transmit sequence is framed by a START (S) condi-
tion and a STOP (P) condition. Each data packet is 9 bits
long, 8 bits of data followed by the acknowledge bit. The
IC supports data transfer rates with SCL frequencies up
to 400kHz.
1
1
1
On, normal, remote sense on
On, normal, remote sense off
1
SDA
SCL
CHANGE OF DATA
ALLOWED
DATA LINE STABLE DATA VALID
2
Figure 2. I C Bit Transfer
Maxim Integrated
40
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is
a low-to-high transition on SDA, while SCL is high. See
Figure 3.
Acknowledge
The number of data bytes between the START and STOP
conditions for the transmitter and receiver are unlimited.
Each 8-bit byte is followed by an acknowledge bit. The
acknowledge bit is a high-level signal put on SDA by the
transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
that is addressed must generate an acknowledge after
each byte it receives. Also, a master receiver must
generate an acknowledge after each byte it receives that
has been clocked out of the slave transmitter.
A START condition from the master signals the beginning
of a transmission to the IC. The master terminates trans-
mission by issuing a not-acknowledge (nACK) followed
by a STOP condition. See the Acknowledge section for
more information. The STOP condition frees the bus.
To issue a series of commands to the slave, the master
can issue REPEATED START (Sr) commands instead
of a STOP command to maintain control of the bus. In
general, a REPEATED START command is functionally
equivalent to a regular START command.
The device that acknowledges must pull down the DATA
line during the acknowledge clock pulse, so that the
DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave SDA high to enable
the master to generate a STOP condition.
When a STOP condition or incorrect address is detected,
the IC internally disconnects SCL from the serial interface
until the next START condition, minimizing digital noise
and feedthrough.
Update of Output Operation Mode
If updating the output voltage or operation mode register
for the mode that the is currently operating in, the output
voltage/operation mode is updated at the same time the
IC sends the acknowledge for the I2C data byte.
System Configuration
A device on the I2C bus that generates a message is
called a transmitter and a device that receives the mes-
sage is a receiver. The device that controls the message
is the master and the devices that are controlled by the
master are called slaves.
SDA BY MASTER
D0
D7
D6
SDA
SCL
NOT ACKNOWLEDGE
SDA BY SLAVE
ACKNOWLEDGE
8
SCL
1
2
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
STOP
CONDITION
START CONDITION
2
2
Figure 3. I C START and STOP Conditions
Figure 4. I C Acknowledge
Maxim Integrated
41
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Slave Address
A bus master initiates communication IC by issuing a
START condition followed by the slave address. The
slave address byte consists of 7 address bits (1100011x)
and a read/write bit (R/W). After receiving the proper
address, the IC issues an acknowledge by pulling SDA
low during the ninth clock cycle.
The IC uses a default I2C slave address of C6h. There
are two other slave addresses (C8h and CAh) that can
be assigned. Contact the factory for details. See the
Selector Guide.
any register pointer even though only a subset of those
registers actually exists in the device. The write byte pro-
tocol is as follows:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
Write Operations
The IC recognizes the write byte protocol as defined in
the SMBus specification. The write byte protocol allows
the I2C master device to send 1 byte of data to the slave
device. The write byte protocol requires a register pointer
address for the subsequent write. The IC acknowledges
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
9) The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
NUMBER
OF BITS
1
7
1
0
1
8
1
8
1
1
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A
P
R/W
b) WRITING TO MULTIPLE REGISTERS
NUMBER
OF BITS
1
7
1
1
8
1
8
1
8
1
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
DATA X + 1
A
R/W
NUMBER OF BITS
8
1
8
1
DATA X + n - 1
A
DATA X + n
A
P
2
Figure 5. I C Write Operation
Maxim Integrated
42
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Read Operations
The method for reading a single register (byte) is shown
below. To read a single register:
In addition to the write-byte protocol, the IC can write
to multiple registers as shown in Figure 5. This protocol
allows the I2C master device to address the slave only
once and then send data to a sequential block of regis-
ters starting at the specified register pointer.
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
Use the following procedure to write to a sequential block
of registers:
3) The addressed slave asserts an acknowledge by
pulling SDA low.
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START condition.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
7) The master sends the 7-bit slave address followed
by a read bit.
4) The master sends the 8-bit register pointer of the
first register to write.
8) The slave assets an acknowledge by pulling
SDA low.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
9) The slave sends the 8-bit data (contents of
the register).
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
10) The master assets a not acknowledge by keeping
SDA high.
9) Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
11) The master sends a STOP condition.
10) The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
1
7
1
0
1
8
1
1
7
1
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
A
REGISTER POINTER
A
Sr
SLAVE ADDRESS
1
A
DATA
A
P
R/W
R/W
b) READING MULTIPLE REGISTERS
NUMBER OF BITS
1
7
1
1
8
1
1
7
1
8
1
1
1
...
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
Sr
SLAVE ADDRESS
A
DATA X
A
R/W
...
R/W
1
8
1
8
8
1
1
NUMBER OF BITS
...
A
DATA X+1
DATA X+n-1
A
DATA X+n
A
P
2
Figure 6. I C Read Operation
Maxim Integrated
43
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
In addition, the IC can read a block of multiple sequential
8) The slave assets an acknowledge by pulling
registers as shown in section B of Figure 6. Use the fol-
lowing procedure to read a sequential block of registers:
SDA low.
9) The slave sends the 8-bit data (contents of
the register).
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
10) The master assets an acknowledge by pulling
SDA low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
4) The master sends an 8-bit register pointer of the first
register in the block.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START condition.
12) The master sends a STOP condition.
7) The master sends the 7-bit slave address followed
by a read bit.
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
HIGH
t
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 7. I C Timing Diagram
Maxim Integrated
44
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
I2C Commands
Register Reset
All resisters associated with the IC’s I2C interface are reset to their default values when the voltage applied to V drops
IO
below the 0.4V threshold. See the Electrical Characteristics table. The slave address of the IC is 0xC6.
I2C High Level Register Map
2
Table 3. I C High Level Register Map
BIT
REGISTER
DESCRIPTION
7
MSB
0
LSB
6
5
4
3
2
1
0x00
0x01
ID
ID[7:0]
Chip Configuration
FREQ[2:0]
RSVD
RSVD
RSVD
RSVD
RSVD
Step-Down 1
Voltage V High
ID
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0B
VOUT_B1_VIDH[7:0]
VOUT_B1_VIDL[7:0]
Step-Down 1
Voltage V Low
ID
Step-Down 1
FALL
SLEW1H
SLEW1H[7:6]
PWR1H[5:4]
PWR1L[5:4]
nADEN1H FPWM1H
nADEN1L FPWM1L
RSVD
RSVD
Configuration V High
ID
Step-Down 1
FALL
SLEW1L
SLEW1L[7:6]
Configuration V Low
ID
Step-Down 2
VOUT_B2_VIDH[7:0]
VOUT_B2_VIDL[7:0]
Voltage V High
ID
Step-Down 2
Voltage V Low
ID
Step-Down 2
FALL
SLEW2H
SLEW2H[7:6]
SLEW2L[7:6]
PWR2H[5:4]
PWR2L[5:4]
nADEN2H FPWM2H
nADEN2L FPWM2L
RSVD
RSVD
RSVD
Configuration V High
ID
Step-Down 2
FALL
SLEW2L
Configuration V Low
ID
LDO_
PNOK
Status
PNOK1
PNOK2
TH
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
LDO_
PNOK_
INT
PNOK1_
INT
PNOK2_
INT
0x0C
Interrupt
TH_INT
THM
RSVD
RSVD
LDO_
PNOKM
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
Interrupt Mask
PNOK1M PNOK2M
LDO1PWR[7:6]
LDO 1 Configuration 1
LDO 1 Configuration 2
LDO 2 Configuration 1
LDO 2 Configuration 2
LDO 3 Configuration 1
LDO 3 Configuration 2
LDO1TV[5:0]
LDO1OV
RSVD
LDO1
ADE
LDO1COMP[5:4]
LDO2COMP[5:4]
LDO3COMP[5:4]
LDO1POK
RSVD
LDO1SS
LDO2SS
LDO3SS
CLMP_EN
LDO2PWR[7:6]
LDO2TV[5:0]
LDO2OV
RSVD
LDO2
ADE
LDO2POK
RSVD
CLMP_EN
LDO3PWR[7:6]
LDO3TV[5:0]
LDO3OV
RSVD
LDO3
ADE
LDO3POK
RSVD
CLMP_EN
Maxim Integrated
45
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
2
Table 3. I C High Level Register Map (continued)
BIT
REGISTER
DESCRIPTION
7
MSB
0
LSB
6
5
4
3
2
1
0x14
0x15
0x16
0x17
0x18
0x19
LDO 4 Configuration 1
LDO 4 Configuration 2
LDO 5 Configuration 1
LDO 5 Configuration 2
LDO 6 Configuration 1
LDO 6 Configuration 2
LDO4PWR[7:6]
LDO4OV
CLMP_EN
LDO5PWR[7:6]
LDO5OV
CLMP_EN
LDO6PWR[7:6]
LDO6OV
CLMP_EN
RSVD
RSVD
LDO4TV[5:0]
LDO4POK RSVD
LDO5TV[5:0]
LDO5POK RSVD
LDO6TV[5:0]
LDO4
ADE
RSVD
LDO4COMP[5:4]
LDO5COMP[5:4]
LDO6COMP[5:4]
LDO4SS
LDO5SS
LDO5
ADE
RSVD
LDO6
ADE
RSVD
LDO6POK
RSVD
LDO6SS
L01_INT
0x1B
0x1C
LDO INT
L06_INT
L05_INT
L04_INT
L03_INT
L02_INT
LDO INTM
L06_INTM L05_INTM L04_INTM L03_INTM L02_INTM L01_INTM
Table 4. ID Register
COMMAND NAME
ID
MAX8967 I2C address
0x00
I2C address
Command code
Access type
Read only
Reset condition
Hard wired, not reset
BIT
NAME
DESCRIPTION
Code is a unique chip version identifier
DEFAULT
7–0
ID[7:0]
0x66
Table 5. Chip Configuration Register
COMMAND NAME
I2C address
CHIP CONFIGURATION
MAX8967 I2C address
0x01
Command code
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
7, 6, 5
4–0
NAME
DESCRIPTION
DEFAULT
0b000
0b0
Switching frequency selection bits
000 = 4.4MHz
001 = 4.8MHz
010 = 4.0MHz
011 = RSVD
100 = 4.2MHz
101 = RSVD
110 = 4.6MHz
111 = RSVD
FREQ[2:0]
Reserved
—
Maxim Integrated
46
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 6. Step-Down 1 Output Voltage VID High
COMMAND NAME
STEP-DOWN CONVERTER 1 VOLTAGE VID HIGH
I2C address
MAX8967 I2C address
Command code
Access type
0x02
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
0x00
7:0
VOUT_ B1_VIDH [7:0]
See Table 14
Table 7. Step-Down 1 Output Voltage VID Low
COMMAND NAME
STEP-DOWN CONVERTER 1 VOLTAGE VID LOW
MAX8967 I2C address
0x03
I2C address
Command code
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
VOUT_B1_VIDL [7:0]
See Table 14
0x30
Table 8. Step-Down 1 Configuration Register VID High
COMMAND NAME
STEP-DOWN CONVERTER 1 CONFIGURATION VID HIGH
I2C address
MAX8967 I2C address
Command code
Access type
0x04
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
See Table 15
See Table 15
0x00
Table 9. Step-Down 1 Configuration Register VID Low
COMMAND NAME
STEP-DOWN CONVERTER 1 CONFIGURATION VID LOW
I2C address
MAX8967 I2C address
Command code
Access type
0x05
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
See Table 15
See Table 15
0x00
Maxim Integrated
47
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 10. Step-Down 2 Voltage Register VID High
COMMAND NAME
STEP-DOWN 2 VOLTAGE VID HIGH
I2C address
MAX8967 I2C address
Command code
Access type
0x06
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
VOUT_B2_VIDH[7:0]
See Table 14
0x00
Table 11. Step-Down 2 Output Voltage VID Low
COMMAND NAME
STEP-DOWN 2 VOLTAGE VID LOW
I2C address
MAX8967 I2C address
Command code
Access type
0x07
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
VOUT_B2_VIDL[7:0]
See Table 14
0x30
Table 12. Step-Down 2 Configuration Register VID High
COMMAND NAME
STEP-DOWN 2 CONFIGURATION VID HIGH
I2C address
MAX8967 I2C address
Command code
Access type
0x08
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
See Table 15
See Table 15
0x00
Table 13. Step-Down 2 Configuration Register VID Low
COMMAND NAME
STEP-DOWN 2 CONFIGURATION VID LOW
I2C address
MAX8967 I2C address
Command code
Access type
0x09
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
7–0
See Table 15
See Table 15
0x00
Maxim Integrated
48
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 14. Step-Down Output Voltage Table
BIT
DESCRIPTION
DEFAULT
0x00 =
0x20 =
0x40 =
0x60 =
0x80 =
0xA0 =
0xC0 =
0.6000V
1.0000V
1.4000V
1.8000V
2.2000V
2.6000V
3.0000V
0x01 =
0x21 =
0x41 =
0x61 =
0x81 =
0xA1 =
0xC1 =
0.6125V
1.0125V
1.4125V
1.8125V
2.2125V
2.6125V
3.0125V
0x02 =
0x22 =
0x42 =
0x62 =
0x82 =
0xA2 =
0xC2 =
0.6250V
1.0250V
1.4250V
1.8250V
2.2250V
2.6250V
3.0250V
0x03 =
0x23 =
0x43 =
0x63 =
0x83 =
0xA3 =
0xC3 =
0.6375V
1.0375V
1.4375V
1.8375V
2.2375V
2.6375V
3.0375V
0x04 =
0x24 =
0x44 =
0x64 =
0x84 =
0xA4 =
0xC4 =
0.6500V
1.0500V
1.4500V
1.8500V
2.2500V
2.6500V
3.0500V
0x05 =
0x25 =
0x45 =
0x65 =
0x85 =
0xA5 =
0xC5 =
0.6625V
1.0625V
1.4625V
1.8625V
2.2625V
2.6625V
3.0625V
0x06 =
0x26 =
0x46 =
0x66 =
0x86 =
0xA6 =
0xC6 =
0.6750V
1.0750V
1.4750V
1.8750V
2.2750V
2.6750V
3.0750V
0x07 =
0x27 =
0x47 =
0x67 =
0x87 =
0xA7 =
0xC7 =
0.6875V
1.0875V
1.4875V
1.8875V
2.2875V
2.6875V
3.0875V
0x08 =
0x28 =
0x48 =
0x68 =
0x88 =
0xA8 =
0xC8 =
0.7000V
1.1000V
1.5000V
1.9000V
2.3000V
2.7000V
3.1000V
0x09 =
0.7125V
0x29 =
1.1125V
0x49 =
1.5125V
0x69 =
1.9125V
0x89 =
2.3125V
0xA9 =
2.7125V
0xC9 =
3.1125V
See the
Electrical
VOUT_B_
VID_[7:0]
Characteristics
table.
0x0A =
0.7250V
0x2A =
1.1250V
0x4A =
1.5250V
0x6A =
1.9250V
0x8A =
2.3250V
0xAA =
2.7250V
0xCA =
3.1250V
0x0B =
0.7375V
0x2B =
1.1375V
0x4B =
1.5375V
0x6B =
1.9375V
0x8B =
2.3375V
0xAB =
2.7375V
0xCB =
3.1375V
0x0C =
0.7500V
0x2C =
1.1500V
0x4C =
1.5500V
0x6C =
1.9500V
0x8C =
2.3500V
0xAC =
2.7500V
0xCC =
3.1500V
0x0D =
0.7625V
0x2D =
1.1625V
0x4D =
1.5625V
0x6D =
1.9625V
0x8D =
2.3625V
0xAD =
2.7625V
0xCD =
3.1625V
0x0E =
0.7750V
0x2E =
1.1750V
0x4E =
1.5750V
0x6E =
1.9750V
0x8E =
2.3750V
0xAE =
2.7750V
0xCE =
3.1750V
0x0F =
0x2F =
0x4F =
0x6F =
0x8F =
0xAF =
0xCF =
0.7875V
1.1875V
1.5875V
1.9875V
2.3875V
2.7875V
3.1875V
0x10 =
0x30 =
0x50 =
0x70 =
0x90 =
0xB0 =
0xD0 =
0.8000V
1.2000V
1.6000V
2.0000V
2.4000V
2.8000V
3.2000V
0x11 =
0x31 =
0x51 =
0x71 =
0x91 =
0xB1 =
0xD1 =
0.8125V
1.2125V
1.6125V
2.0125V
2.4125V
2.8125V
3.2125V
0x12 =
0x32 =
0x52 =
0x72 =
0x92 =
0xB2 =
0xD2 =
0.8250V
1.2250V
1.6250V
2.0250V
2.4250V
2.8250V
3.2250V
0x13 =
0x33 =
0x53 =
0x73 =
0x93 =
0xB3 =
0xD3 =
0.8375V
1.2375V
1.6375V
2.0375V
2.4375V
2.8375V
3.2375V
Maxim Integrated
49
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 14. Step-Down Output Voltage Table (continued)
BIT
DESCRIPTION
DEFAULT
0x14 =
0x34 =
0x54 =
0x74 =
0x94 =
0xB4 =
0xD4 =
0.8500V
1.2500V
1.6500V
2.0500V
2.4500V
2.8500V
3.2500V
0x15 =
0x35 =
0x55 =
0x75 =
0x95 =
0xB5 =
0xD5 =
0.8625V
1.2625V
1.6625V
2.0625V
2.4625V
2.8625V
3.2625V
0x16 =
0x36 =
0x56 =
0x76 =
0x96 =
0xB6 =
0xD6 =
0.8750V
1.2750V
1.6750V
2.0750V
2.4750V
2.8750V
3.2750V
0x17 =
0x37 =
0x57 =
0x77=
0x97 =
0xB7 =
0xD7 =
0.8875V
1.2875V
1.6875V
2.0875V
2.4875V
2.8875V
3.2875V
0x18 =
0x38 =
0x58 =
0x78 =
0x98 =
0xB8 =
0xD8 =
0.9000V
1.3000V
1.7000V
2.1000V
2.5000V
2.9000V
3.3000V
0x19 =
0.9125V
0x39 =
1.3125V
0x59 =
1.7125V
0x79 =
2.1125V
0x99 =
2.5125V
0xB9 =
2.9125V
0xD9 =
3.3125V
See the
Electrical
VOUT_ B_
VID_[7:0]
Characteristics
table.
0x1A =
0.9250V
0x3A =
1.3250V
0x5A =
1.7250V
0x7A =
2.1250V
0x9A =
2.5250V
0xBA =
2.9250V
0xDA =
3.3250V
0x1B =
0.9375V
0x3B =
1.3375V
0x5B =
1.7375V
0x7B =
2.1375V
0x9B =
2.5375V
0xBB =
2.9375V
0xDB =
3.3375V
0x1C =
0.9500V
0x3C =
1.3500V
0x5C =
1.7500V
0x7C =
2.1500V
0x9C =
2.5500V
0xBC =
2.9500V
0xDC =
3.3500V
0x1D =
0.9625V
0x3D =
1.3625V
0x5D =
1.7625V
0x7D =
2.1625V
0x9D =
2.5625V
0xBD =
2.9625V
0xDD =
3.3625V
0x1E =
0.9750V
0x3E =
1.3750V
0x5E =
1.7750V
0x7E =
2.1750V
0x9E =
2.5750V
0xBE =
2.9750V
0xDE =
3.3750V
0x1F =
0x3F =
0x5F =
0x7F =
0x9F =
0xBF =
0xDF =
0.9875V
1.3875V
1.7875V
2.1875V
2.5875V
2.9875V
3.3875V
Maxim Integrated
50
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 15. Step-Down Configuration Table
BIT
NAME
DESCRIPTION
DEFAULT
Active-Low Step-Down Converter Falling Slew Rate Enable
0 = The slew rate control circuit is active when the output voltage is decreased. The
desired regulation voltage is decreased in 12.5mV steps, and forced PWM mode is
enabled so that negative inductor current can be used to pull energy out of the output
capacitor.
0
FALLSLEW_
0b0
1 = The slew rate control circuit is disabled when the output voltage is decreased.
The desired regulation voltage is decreased in 12.5mV steps, but it is up to the external
load to drain energy from the output capacitor in order to pull down on the output voltage.
1
2
RSVD
Reserved
0b0
0b0
Step-Down Forced PWM Mode Enable
0 = Step-Down Converter automatically skips pulses under light load conditions, and
transfers to fixed frequency operation as the load current increases.
1 = Step-Down Converter operates with fixed frequency under all load conditions.
FPWM_
Active-Low Buck Converter Active Discharge Enable
0 = The active discharge function is enabled. When the buck converter is disabled, an
internal 100I discharge resistor is connected to the output to discharge the energy
stored in the output capacitor. When the buck converter is enabled, the discharge
resistor is disconnected from the output.
3
nADEN_
0b0
1 = The active discharge function is disabled. When the buck converter is disabled, the
internal 100I discharge resistor is not connected to the output, and the discharge rate is
dependent on the output capacitance and the load present. When the buck converter is
enabled, the discharge resistor is disconnected from the output.
Step-Down Power Mode Configuration. These bits determine the mode of operation for
this converter.
00 = Disabled
5:4
7:6
PWR_[5:4]
0b00
0b00
01 = Normal operation mode with remote sense disabled
10 = Green mode
11 = Normal operation mode with remote sense enabled
Step-Down Rising Slew Rate
00 = 12.5mV/Fs ramp rate
01 = 25mV/Fs ramp rate
SLEW_[7:6]
10 = 50mV/Fs ramp rate
11 = No slew rate control. Output voltage increases as fast as the current limit allows.
Maxim Integrated
51
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 16. Status
COMMAND NAME
STATUS
I2C address
MAX8967 I2C address
Command code
0x0B
Read only. Status is masked by the interrupt mask register and
is cleared by reading related interrupt register bits.
Access type
Reset condition
Power-up/chip reset/0b1 written to bit
BIT
NAME
DESCRIPTION
0 = Step-down converter 1 is on.
1 = Step-down converter 1 is off or faulted.
DEFAULT
7
PNOK1
0b1
0 = Step-down converter 2 is on.
1 = Step-down converter 2 is off or faulted.
6
5
4
PNOK2
TH
0b1
0b0
0b0
0 = Temperature is below the thermal shutdown threshold.
1 = Temperature exceeds the thermal shutdown threshold.
0 = One or more LDOs are off or above the POK threshold.
0 = One or more LDOs are on and below the POK threshold.
LDO_PNOK
3
2
1
0
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
0b1
0b1
0b1
0b1
Table 17. Interrupt
COMMAND NAME
I2C address
INTERRUPT
MAX8967 I2C address
Command code
Access type
0x0C
Read—clear on read
Power-up/chip reset/0b1 written to bit
Reset condition
BIT
NAME
DESCRIPTION
DEFAULT
Step-Down 1 Interrupt Bit
7
PNOK1_INT
PNOK2_INT
TH_INT
0 = Output is normal
1 = Output has fallen below the power-OK threshold.
0b0
Step-Down 2 Interrupt Bit
0 = Output is normal
1 = Output has fallen below the power-OK threshold.
6
5
0b0
0b0
Thermal Interrupt Bit
0 = Die temperature is normal
1 = Die temperature has exceeded thermal shutdown threshold
4
3
2
1
0
LDO_PNOK_INT
RSVD
One or more LDO power-OK levels have not been maintained.
0b0
0b0
0b0
0b0
0b0
Reserved
Reserved
Reserved
Reserved
RSVD
RSVD
RSVD
Maxim Integrated
52
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 18. Interrupt Mask
COMMAND NAME
I2C address
INTERRUPT MASK
MAX8967 I2C address
0x0D
Command code
Access type
Read–clear on read
Power-up/chip reset/0b1 written to bit
Reset condition
BIT
NAME
DESCRIPTION
DEFAULT
Step-Down 1 Interrupt Mask Bit
7
PNOK1M
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
Step-Down 2 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
6
5
4
PNOK2M
THM
0b1
0b1
0b1
Thermal Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
LDO Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
LDO_PNOKM
3
2
1
0
RSVD
RSVD
RSVD
RSVD
Reserved
Reserved
Reserved
Reserved
0b1
0b0
0b0
0b0
Maxim Integrated
53
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 19. LDO_ Configuration 1 Register
REGISTER NAME
Register address
Access type
LDO_ CONFIGURATION 1
See Table 3
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
LDO Power Mode Configuration
00 = Output disabled
01 = Output disabled
10 = Green mode
7, 6
LDO_PWR [7:6]
0b00
11 = Normal mode
Sets the Target Voltage of the LDO.
Programmed in 0.05V steps.
0x00 =
0.80V
0x0A =
1.30V
0x14 =
1.80V
0x1E =
2.30V
0x28 =
2.80V
0x32 =
3.30V
0x3C =
3.80V
0x01 =
0.85V
0x0B =
1.35V
0x15 =
1.85V
0x1F =
2.35V
0x29 =
2.85V
0x33 =
3.35V
0x3D =
3.85V
0x02 =
0.90V
0x0C =
1.40V
0x16 =
1.90V
0x20 =
2.40V
0x2A =
2.90V
0x34 =
3.40V
0x3E =
3.90V
0x03 =
0.95V
0x0D =
1.45V
0x17 =
1.95V
0x21 =
2.45V
0x2B =
2.95V
0x35 =
3.45V
0x3F =
3.95V
0x04 =
1.00V
0x0E =
1.50V
0x18 =
2.00V
0x22 =
2.50V
0x2C =
3.00V
0x36 =
3.50V
5–0
LDO_TV[5:0]
0b00
0x05 =
1.05V
0x0F =
1.55V
0x19 =
2.05V
0x23 =
2.55V
0x2D =
3.05V
0x37 =
3.55V
0x06 =
1.10V
0x10 =
1.60V
0x1A =
2.10V
0x24 =
2.60V
0x2E =
3.10V
0x38 =
3.60V
0x07 =
1.15V
0x11 =
1.65V
0x1B =
2.15V
0x25 =
2.65V
0x2F =
3.15V
0x39 =
3.65V
0x08 =
1.20V
0x12 =
1.70V
0x1C =
2.20V
0x26 =
2.70V
0x30 =
3.20V
0x3A =
3.70V
0x09 =
1.25V
0x13 =
1.75V
0x1D =
2.25V
0x27 =
2.75V
0x31 =
3.25V
0x3B =
3.75V
Maxim Integrated
54
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 20. LDO_ Configuration 2 Register
REGISTER NAME
Register address
Access type
LDO_ CONFIGURATION 2
See Table 3.
Read only for bit 3, and read/write for the rest
Power-up/chip reset
Reset condition
BIT
7
NAME
LDO_OVCLMP_EN
RSVD
DESCRIPTION
DEFAULT
0b1
Overvoltage Clamp Enable
0 = Overvoltage clamp disabled.
1 = Overvoltage clamp enabled.
6
Reserved
0b0
LDO Compensation
00 = Assume 50mI/5nH trace impedance to remote capacitor.
01 = Assume 100mI/10nH trace impedance to remote capacitor.
10 = Assume 50mI to 200mI /5nH to 20nH trace impedance to
remote capacitor.
11 = Assume 100mI to 400mI /10nH to 40nH trace impedance to
remote capacitor.
5, 4
LDO_COMP
0b01
Note: The LDO_COMP bits should only be changed with the LDO
is disabled. If the compensation bits are changed when the LDO is
enabled, the output voltage glitches as the compensation changes.
Voltage OK Status Bit
0 = The voltage is less than the POK threshold and the device is in
normal mode.
3
LDO_POK
0b0
1 = The voltage is above the POK threshold or the LDO is operating
in its green mode or the LDO is disabled.
2
1
RSVD
Reserved
—
Active Discharge Enable
0 = The active discharge function is disabled.
1 = The active discharge function is enabled.
LDO_ADE
0b1
Sets the LDO Soft-Start Slew Rate
(Applies to both startup and output voltage setting changes)
0 = Fast Startup and Dynamic Voltage Change—100mV/Fs.
1 = Slow Startup and Dynamic Voltage Change—5mV/Fs.
0
LDO_SS
0b1
Maxim Integrated
55
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 21. LDO_INT Register
REGISTER NAME
LDO_INT
Register address
Access type
0x1B
Read—clear on read
Power-up/chip reset
Reset condition
BIT
NAME
DESCRIPTION
DEFAULT
7, 6
RSVD
Reserved
LDO6 Interrupt Bit
5
4
3
2
1
0
L06_INT
L05_INT
L04_INT
L03_INT
L02_INT
L01_INT
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
0b0
0b0
0b0
0b0
0b0
LDO5 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
LDO4 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
LDO3 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
LDO2 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
LDO1 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
Maxim Integrated
56
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 22. LDO_INTM Register
REGISTER NAME
LDO_INTM
Register address
Access type
0x1C
Read—clear on read
Power-up/chip reset
Reset condition
BIT
NAME
DESCRIPTION
DEFAULT
7, 6
RSVD
Reserved
0b11
LDO6 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
5
4
3
2
1
0
L06_INTM
L05_INTM
L04_INTM
L03_INTM
L02_INTM
L01_INTM
0b1
0b1
0b1
0b1
0b1
0b1
LDO5 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
LDO4 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
LDO3 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
LDO2 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
LDO1 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
Input Capacitor Selection
Applications Information
Inductor Selection
Each step-down converter operates with a 1FH nominal
inductance. It is recommended to use an inductor with a
DCR less than 50mI to reduce I2R losses.
Since ripple cancelation is used, the worst case condition
is if one supply is operating at near its 2A maximum while
the other supply is providing very little current. Since the
IC can normally be connected to a node with significant
capacitance, only 4.7FF need be applied locally. A 10FF
ceramic capacitor with X5R rating is recommended.
Output Capacitor Selection
The IC is designed to operate with at least a 22µF
ceramic capacitor (X5R rated) connected to each step-
down converter output. Note that a significant share of
each output’s capacitance can be placed as bypassing
at the load.
PCB Layout
Nearly all noise generated by the IC is found across IN1,
IN2, and PGND_ pins. The bypass capacitors for these
pins should be placed closest to the IC. PGND_ and AGND
should be connected only after the PGND_ pins connect
to its corresponding step-down converter’s input capaci-
tor. Both step-down converters have remote sensing which
accommodates a distance that incurs up to a 200mV cor-
rection in the output voltage. Refer to the MAX8967 EV kit
for more details.
A 1µF (X5R rated ceramic capacitor is required for each
LDO output. The capacitor can be remotely placed away
from the IC and the appropriate compensation can be
2
selected through an I C command. See Table 20.
Maxim Integrated
57
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Ordering Information
PART
PIN-PACKAGE
30 WLP
TEMP RANGE
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
-40NC to +85NC
BUCK OUT1 (V)
BUCK OUT2 (V)
MAX8967EWV+T
MAX8967AEWV+T
MAX8967BEWV+T
MAX8967CEWV+T
1.20
1.20
1.20
1.20
1.20
1.80
2.80
3.20
30 WLP
30 WLP
30 WLP
+Denotes a lead (Pb)-free/RoHS-compliant package.
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE PACKAGE OUTLINE
LAND
TYPE
CODE
NO.
PATTERN NO.
Refer to
Application Note 1891
30 WLP
W302B2+2
21-0548
Maxim Integrated
58
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
12/12
Initial release
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
59
©
2012 Maxim Integrated
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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