MAX8982PEWO+T [MAXIM]
Power-Management ICs for ICERA E400 Platform;
| 型号： | MAX8982PEWO+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Power-Management ICs for ICERA E400 Platform |
| 文件： | 总73页 (文件大小：4026K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
General Description
Features
The MAX8982A/MAX8982P/MAX8982X are complete
power-management ICs for the latest LTE/WCDMA/GSM/
GPRS/EDGE data card based on the new ICERA platform
(E400). The MAX8982A operates from a 4.1V to 5.5V
supply and contains four efficient step-down converters,
nine low dropout linear regulators (LDOs) to power all
RF and baseband circuitry, three current regulators with
programmable current up to 24mA and embedded flash
timers, and an I2C serial interface to program individual
regulator output voltages as well as on/off control for flex-
ibility. The linear regulators provide greater than 60dB
PSRR, less than 45FV of output noise, and minimal cross
coupling noise between LDOs.
S 4 High-Efficiency Buck Converters
0.9V at 1.2A (1.3 for MAX8982P) for CORE with
DVS Function (0.6V
to 1.2V in 25mV Steps) and Slew Rate Control
1.8V at 600mA for System IO
3.2V at 600mA for All LDO Inputs (2.9V to 3.65V
in 50mV Steps) (MAX8982A/MAX8982P Only)
3.4V at 1.8A for GSM/WCDMA PA (3.0V to 3.75V
in 50mV Steps) (MAX8982A/MAX8982P Only)
S 9 LDO Linear Regulators
2.7V at 300mA on LDO1 for RF Transceiver
1.8V at 150mA on LDO2 for RF Transceiver
2.8V at 150mA on LDO3 for Analogue BB
0.9V at 50mA on LDO4 for BB PLL with the
Separate Input for a Higher Efficiency
3.0V at 150mA on LDO5 for SD Card
2.7V at 150mA on LDO6 for TCXO
1.8V or 3.0V at 150mA on LDO7 for SIM
3.0V at 150mA on LDO8 for USB with the
Separate Input (MAX8982A/MAX8982P Only)
0.9V at 50mA on LDO9 for BB with the Separate
Input for a Higher Efficiency
The MAX8982X/MAX8982P operates from a 2.9V to 5.5V
supply. The MAX8982X has the same features as the
MAX8982A, except it does not have BUCK3, BUCK4,
and LDO8. The MAX8982P has the same features as the
MAX8982A.
All buck converters and LDOs are enabled/disabled by
either I2C or PWR_REQ control signal after power-up.
This feature provides more flexibility in system design.
Applications
GSM, GPRS, EDGE, WCDMA, and LTE
S 32 Programmable Voltage Options and External
Input on BUCK1 (0.9V Default) for DVS
Data Card with New ICERA Platform (E400)
S 16 Programmable Voltage Options for BUCK3
(MAX8982A/MAX8982P Only)
Ordering Information
S 16 Programmable Voltage Options on BUCK4
(MAX8982A/MAX8982P Only)
PART
TEMP RANGE PIN-PACKAGE
S Programmable Voltage Options for All LDOs
MAX8982AEWO+T
MAX8982PEWO+T
MAX8982XEWO+T
42 WLP
42 WLP
42 WLP
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
(LDO8 for MAX8982A/MAX8982P Only)
S BUCK2, BUCK3 (MAX8982A/MAX8982P Only),
LDO3, and Internal 32kHz Clock Default On at
Initial Startup
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel. These devices have a minimum order inc-
rement of 1k pieces.
S All Buck Converters and LDOs are Enabled by
Either I2C or Power Request Control (PWR_REQ)
After Power-Up
S 3 Current Regulators with 8 Dimming Current
Options Up to 24mA with Embedded Flash Timer
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5472; Rev 2; 4/11
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Buck1 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Buck2 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Buck3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Buck4 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OUT1 (LDO1) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OUT2 (LDO2) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OUT3 (LDO3) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OUT4 (LDO4) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT5 (LDO5) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT6 (LDO6) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VSIM (LDO7) Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUT8 (LDO8) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
OUT9 (LDO9) Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RESET Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
IRQ Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current Regulator Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Flash Timer Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
N32kHz Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-On/Off Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PWR_REQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Active Discharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
BUCK1, BUCK2, and BUCK3
Step-Down Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Setting the Output Voltage on BUCK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Dynamic Voltage Scaling (DVS)
Function on Buck 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
TABLE OF CONTENTS (CONTINUED)
Ramp-Up/Down Slope Control on BUCK1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Setting the Output Voltage on BUCK2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Setting the Output Voltage on BUCK3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
BUCK4 Step-Down Converter
for PA (Power Amplifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Setting the Output Voltage on BUCK4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Linear Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Reference Bypass (REFBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Thermal Overload Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Overvoltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Current Regulators (DR1, DR2, DR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Embedded Flash Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
IRQ Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
RESET SIGNAL to B/B Chipset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Write Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Maxim Integrated
3
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
LIST OF FIGURES
Figure 1. MAX8982A/MAX8982P Typical Application Circuit and Functional Block Diagram . . . . . . . . . . . . . . . . . . 31
Figure 2. MAX8982X Typical Application Circuit and Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 3. Power-On/Off State Diagram with IN3 Connected to BUCK2 Output and IN4 Connected to IN1_.
Default PWR_REQ Regulators Are Shown.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4. MAX8982_ Power-On Timing Diagram at Initial Startup with EN Connected to IN1_.
BUCK3 and OUT8 Are for the MAX8982A/MAX8982P Only.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 5. MAX8982_ Power-On Timing Diagram in PWR_REQ ON Mode After Power-Up . . . . . . . . . . . . . . . . . . . . 37
Figure 6. Frequency Variation vs. Load Current with a 5V Input Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 7. DVS1 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 8. BUCK1 Ramp-Up/Down Slope Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 9. POR State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Adding Series Resistors to Adjust LED Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Flash Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 12. I2C Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 13. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 14. Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 15. I2C Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 16. I2C Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 17. Writing to the ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 18. Reading from the ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LIST OF TABLES
Table 1. Summary of Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 2. External Component List for Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3. External Component List for Figure 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4. BUCK1 Ramp-Up/Down Slope Control Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6. CHIPID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 7. IRQM Register (Interrupt Mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 8. IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 9. STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 10. LED1FT1 Register (LED1 (DR1) Flash Timer On/Off and TON Adjust) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 11. LED1FT2 Register (LED1 (DR1) Flash Timer t Setting). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
1
Table 12. LED1FT3 Register (LED1 (DR1) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2
4
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
LIST OF TABLES (CONTINUED)
Table 13. LED1FT4 Register (LED1 (DR1) Flash Timer t Setting). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3
Table 14. LED1FT5 Register (LED1 (DR1) Flash Timer t Setting). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4
Table 15. LED1FT6 Register (LED1 (DR1) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
P
Table 16. LED2FT1 Register (LED2 (DR2) Flash Timer On/Off and t
Adjust) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ON
Table 17. LED2FT2 Register (LED2 (DR2) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1
Table 18. LED2FT3 Register (LED2 (DR2) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2
Table 19. LED2FT4 Register (LED2 (DR2) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3
Table 20. LED2FT5 Register (LED2 (DR2) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4
Table 21. LED2FT6 Register (LED2 (DR2) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
P
Table 22. LED3FT1 Register (LED3 (DR3) Flash Timer On/Off and t
Adjust) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ON
Table 23. LED3FT2 Register (LED3 (DR3) Flash Timer t Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1
Table 24. LED3FT3 Register (LED3 (DR3) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2
Table 25. LED3FT4 Register (LED3 (DR3) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3
Table 26. LED3FT5 Register (LED3 (DR3) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4
Table 27. LED3FT6 Register (LED3 (DR3) Flash Timer t Setting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
P
Table 28. BUCK1 Register (On/Off Control for BUCK1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 29. BUCK1DVS1 Register (Output Voltage Setting for BUCK1 (DVS1 = Low)) . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 30. BUCK1DVS2 Register (Output Voltage Setting for BUCK1 (DVS1 = High)). . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 31. BUCK2 Register (On/Off Control for BUCK2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 32. LDO1 Register (On/Off Control for LDO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 33. LDO1V Register (Output Voltage Setting for OUT1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 34. LDO2 Register (ON/OFF Control for LDO2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 35. LDO2V Register (Output Voltage Setting for OUT2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 36. LDO3 Register (On/Off Control for LDO3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 37. LDO3V Register (Output Voltage Setting for OUT3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 38. LDO4 Register (On/Off Control for LDO4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 39. LDO4V Register (Output Voltage Setting for OUT4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 40. LDO5 Register (On/Off Control for LDO5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 41. LDO5V Register (Output Voltage Setting for OUT5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 42. LDO6 Register (On/Off Control for LDO6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 43. LDO6V Register (Output Voltage Setting for OUT6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 44. VSIM Register (On/Off Control for VSIM (LDO7)). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 45. VSIMV Register (Output Voltage Setting for VSIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 46. LDO8 Register (On/Off Control for LDO8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 47. LDO8V Register (Output Voltage Setting for OUT8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 48. LDO9 Register (On/Off Control for LDO9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Maxim Integrated
5
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
LIST OF TABLES (CONTINUED)
Table 49. LDO9V Register (Output Voltage Setting for OUT9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 50. LED_EN Register (On/Off Control for 3 Current Regulators) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 51. On/Off Register (On/Off Control for BUCK3, BUCK4, and the Internal 32kHz Clock) . . . . . . . . . . . . . . . . . 64
Table 52. BUCK3 Register (Output Voltage Setting for BUCK3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 53. BUCK4 Register (Output Voltage Setting for BUCK4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 54. CURRENTREG1 Register (Current Setting for Current Regulators DR1 and DR2) . . . . . . . . . . . . . . . . . . . 66
Table 55. CURRENTREG2 Register (Current Setting for Current Regulator DR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 56. RAMP Register (Slope Setting for BUCK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 57. BUCK1-4ADIS Register (Active Discharge Settings for BUCK1–BUCK4) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 58. LDO1-8ADIS Register (Active Discharge Settings for LDO1–LDO8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 59. LDO9ADIS Register (Active Discharge Setting for LDO9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 60. Recommended Inductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
ABSOLUTE MAXIMUM RATINGS
DDA DDB
REFBP, BUCK1, BUCK2, BUCK3, BUCK4,
V
, V
, IN4, IN1A, IN1B to GND....................-0.3V to +6V
LX1 Continuous Current (Note 1)...................................1200mA
LX2, LX3 Continuous Current (Note 1) ............................600mA
LX4 Continuous Current (Note 1)...................................1800mA
EN to GND...............................-0.3V to (V
V
+ 0.3V)
IN1A, IN1B
SDA, SCL, PWR_REQ, DVS1, IRQ, RESET, IN3,
Continuous Power Dissipation (T = +70NC)
A
7 x 6 42-Bump WLP, 0.5mm Pitch, 3.75mm x 3.20mm
(derate 27.8mW/NC above +70NC)................................2.22W
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
N32kHz to GND.............................. -0.3V to (V
OUT1, OUT2 to GND ............................. -0.3V to (V
OUT3, OUT5, OUT6, VSIM to GND ....... -0.3V to (V
OUT8 to GND........................................... -0.3V to (V
OUT4, OUT9 to GND ............................... -0.3V to (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
BUCK2
DDA
DDB
IN4
IN3
PGND1, PGND2, PGND3, PGND4 to GND .........-0.3V to +0.3V
DR1, DR2, DR3 to GND ..........................-0.3V to (V + 0.3V)
IN1_
Note 1: LX1–LX4 have internal clamp diodes to PGND_, IN1A, and IN1B. Applications that forward bias this diode should take
care not to exceed the power dissipation limits of the device.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 2)
WLP
Junction-to-Ambient Thermal Resistance (q ) ..........36°C/W
JA
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
GENERAL ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
= V
= +5.0V and C
= 1000FF, MAX8982X: V
= V
= +3.3V and
IN1A
IN1B
OUT1,2,3+CIN_
IN1A
IN1B
C
= 20FF, C = 0.1FF, T = -40NC to +85NC. Typical values are at T = +25NC, unless otherwise noted.) (Note 3)
REFBP A A
OUT1,2,3+CIN_
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
kV
Module level ESD protection, in-circuit tested with 0.1FF
IN1A, IN1B, IN4 ESD Protection
Q10
ceramic capacitor
Shutdown Supply Current (Note 4) EN = GND
10
FA
MAX8982A/MAX8982P, V = V
on (default output), all other regulators off
, BUCK3 and OUT3
IN1_
EN
300
300
MAX8982X, V = V
EN
, OUT3 on (default output), all
IN1_
other regulators off
MAX8982A/MAX8982P, V = V
output), BUCK2 on (default output), BUCK3 on (default
output), all LDOs (except LDO8) default output on
, BUCK1 on (default
EN
IN1_
No Load Supply Current
FA
600
600
MAX8982X, V = V
, BUCK1 on (default output),
EN
IN1_
BUCK2 on (default output), all LDOs (except LDO8)
default output on
MAX8982A/MAX8982P, V = V
, 32kHz clock on,
EN
IN1_
BUCK2 on (default output) with 200FA load, BUCK3
on (default output), OUT3 on (default output) with 20FA
1000
1000
load, OUT2 on (default output) with 100FA load, V
VSIM
= 3.0V with 50FA load, OUT8 on (default output) with
100FA load
Loaded Supply Current
FA
MAX8982X, V = V
, 32kHz clock on, BUCK2 on
EN
IN1_
(default output) with 200FA load, OUT3 on (default
output) with 20FA load, OUT2 on (default output) with
100FA load, V
= 3.0V with 50FA load
VSIM
Maxim Integrated
7
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
GENERAL ELECTRICAL CHARACTERISTICS (continued)
(MAX8982A/MAX8982P: V
= V
= +5.0V and C
= 1000FF, MAX8982X: V
= V
= +3.3V and
IN1A
IN1B
OUT1,2,3+CIN_
IN1A
IN1B
C
= 20FF, C
= 0.1FF, T = -40NC to +85NC. Typical values are at T = +25NC, unless otherwise noted.) (Note 3)
OUT1,2,3+CIN_
PARAMETER
OPERATING VOLTAGE
REFBP
A
A
CONDITIONS
MIN
TYP
MAX
UNITS
MAX8982A
4.1
2.9
3.5
5.5
5.5
4.1
IN1A, IN1B Operating Voltage
V
MAX8982X/MAX8982P
MAX8982A, V
MAX8982A, V
rising
falling
3.8
3.5
2.7
2.4
IN1_
IN1_
Undervoltage Lockout
V
MAX8982X/MAX8982P, V
MAX8982X/MAX8982P, V
rising
falling
2.5
2.9
IN1_
IN1_
OVERVOLTAGE LOCKOUT (OVP)
Overvoltage Lockout
(Shutdown All Outputs Including
LDO7)
V
rising
5.75
250
5.93
V
IN1_
IN1A, IN1B Overvoltage
Hysteresis
mV
THERMAL SHUTDOWN
Threshold
T rising
160
10
NC
NC
J
Hysteresis
HOT TEMPERATURE DETECTION
Threshold
Interrupt enabled, T rising, typical hysteresis = +10NC
+125
NC
J
REFERENCE
REFBP Output Voltage
Supply Rejection
0 P I
P 1FA
0.788
0.80
0.2
0.812
V
REFBP
4.1V P V
P 5.5V
mV
IN1_
LOGIC AND CONTROL INPUTS (SDA, SCL, EN, DVS1, PWR_REQ)
Input Low Level
Input High Level
T
T
= +25NC
= +25NC
0.3
+1
V
V
A
1.2
-1
A
0V < V
0V < V
< 5.5V, T = +25NC
A
IN1_
Logic Input Current
FA
< 5.5V, T = +85NC
0.1
IN1_
A
LOGIC AND CONTROL OUTPUTS
SDA Output Low Level
I
= 6mA
0.4
V
SDA
I2C INTERFACE (V
= V
= 1.8V, Note 2, Figure 16)
SCL
SDA
Clock Frequency
400
kHz
Bus Free Time Between START
and STOP (t
1.3
0.6
Fs
)
BUF
Hold Time Repeated START
Fs
Condition (t
)
HD_STA
SCL Low Period (t
)
1.3
0.6
Fs
Fs
LOW
SCL High Period (t
)
HIGH
Setup Time Repeated START
0.6
Fs
Condition (t
)
SU_STA
SDA Hold Time (t
)
0
Fs
HD_DAT
SDA Setup Time (t
)
100
ns
SU_DAT
8
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
GENERAL ELECTRICAL CHARACTERISTICS (continued)
(MAX8982A/MAX8982P: V
= V
= +5.0V and C
= 1000FF, MAX8982X: V
= V
= +3.3V and
IN1A
IN1B
OUT1,2,3+CIN_
IN1A
IN1B
C
= 20FF, C
= 0.1FF, T = -40NC to +85NC. Typical values are at T = +25NC, unless otherwise noted.) (Note 3)
OUT1,2,3+CIN_
REFBP
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum Pulse Width of Spikes
that Must be Suppressed by the
Input Filter of Both SDA and SCL
Signals
50
ns
Setup Time for STOP Condition
0.6
Fs
(t
)
SU_STO
BUCK1 ELECTRICAL CHARACTERISTICS
(MAX8982AMAX8982P: V
= V
= +5.0V and C
= 1000µF, MAX8982X: V
= V = +3.3V and C
IN1B OUT1,2,3+CIN_
IN1A
IN1B
OUT1,2,3+CIN_
IN1A
= 20µF, C
(Note 3)
= 0.1µF, C
= 10µF, L = 2.2µH, T = -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.)
REFBP
OUT
A
A
PARAMETER
CONDITIONS
MIN
TYP
65
MAX
UNITS
FA
Supply Current (Note 4)
Default Output Voltage
No load, no switching
I
= 100mA
0.873
-3
0.9
0.927
+3
V
LOAD
I
= 100mA, V
tested at 0.6V, 0.775V, 1V,
LOAD
BUCK1
Output Voltage Accuracy
Maximum Output Current
%
1.2V in production (0.6V to 1.2V in 25mV steps)
MAX8982A/MAX8982X
MAX8982P
1200
1300
1400
1500
1000
1100
V
= 0.9V, T =
A
BUCK1
mA
+25NC
pFET switch (MAX8982A/MAX8982X)
pFET switch (MAX8982P)
1800
1900
1400
1500
0.3
2500
2600
1900
2000
Current Limit
mA
nFET rectifier (MAX8982A/MAX8982X)
nFET rectifier (MAX8982P)
pFET switch, I
= -150mA
LX1
On-Resistance
I
nFET rectifier, I
= 150mA
0.15
5
LX1
RASD1[0:1] = 00
RASD1[0:1] = 01
10
mV/
Fs
Ramp-Up/Down Rate Control
Same for both up and down
12.5
(default)
RASD1[0:1] = 10
RASD1[0:1] = 11
25
40
40
40
85
Rectifier Off Current Threshold
Minimum On-Time
mA
ns
ns
%
t
t
ON
Minimum Off-Time
OFF
Efficiency (Note 4)
V
= 0.9V, I
= 400mA
BUCK1
LOAD
Shutdown Output Resistance
(Active Discharge Resistance)
2
I C programmable, default OFF
Equal to inductor DC resistance divided by 4
1
kI
Output Load Regulation
R /4
V/A
L
Maxim Integrated
9
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
BUCK2 ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
= V
= +5.0V and C
= 1000FF, MAX8982X: V
= V
= +3.3V and
IN1B
IN1A
IN1B
OUT1,2,3+CIN_
IN1A
C
= 20FF, C
= 0.1FF, C
= 2.2FF, L = 1FH, T = -40NC to +85NC, unless otherwise noted. Typical values are
OUT A
OUT1,2,3+CIN_
REFBP
at T = +25NC.) (Note 3)
A
PARAMETER
Supply Current (Note 4)
Output Voltage
CONDITIONS
No load, no switching
= 100mA
MIN
TYP
26
MAX
UNITS
FA
I
1.746
600
1.8
1.854
V
LOAD
Output Current
V
= 1.8V, T = +25NC
mA
BUCK2
A
pFET switch
nFET rectifier
pFET switch, I
700
1100
750
0.65
0.3
40
1500
1200
Current Limit
mA
500
= -150mA
LX2
On-Resistance
I
nFET rectifier, I
= 150mA
LX2
Rectifier Off Current Threshold
Minimum On-Time
mA
ns
ns
%
t
t
70
ON
Minimum Off-Time
70
OFF
Efficiency (Note 4)
V
= 1.8V, I
= 250mA
85
BUCK2
LOAD
Shutdown Output Resistance
(Active Discharge Resistance)
2
I C programmable, default ON
100
I
Output Load Regulation
Equal to inductor DC resistance divided by 4
R /4
V/A
L
BUCK3 ELECTRICAL CHARACTERISTICS
(MAX8982A/MX8982P only, V
= V
= +5.0V, C
= 1000FF, C
= 0.1FF, C
MIN
= 2.2FF, L = 2.2FH, T =
OUT A
IN1A
IN1B
OUT1,2,3+CIN_
REFBP
-40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
Supply Current (Note 4)
Default Output Voltage
CONDITIONS
No load, no switching
TYP
MAX
UNITS
FA
40
I
= 100mA
3.10
3.2
3.29
V
LOAD
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
I
= 100mA,
LOAD
Programmable Output Voltage
V
programmable output voltage step = 50mV
Maximum Output Current
Efficiency (Note 4)
V
V
= 3.2V, T = +25NC
600
mA
%
BUCK3
BUCK3
A
= 3.2V, I
= 300mA
90
LOAD
10
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
BUCK3 ELECTRICAL CHARACTERISTICS (continued)
(MAX8982A/MAX8982P only, V
= V
= +5.0V, C
= 1000FF, C
= 0.1FF, C
= 2.2FF, L = 2.2FH, T =
OUT A
IN1A
IN1B
OUT1,2,3+CIN_
REFBP
-40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
Current Limit
CONDITIONS
MIN
700
500
TYP
MAX
1500
1200
UNITS
pFET switch
nFET rectifier
pFET switch, I
1100
750
0.65
0.3
80
mA
= -150mA
LX3
On-Resistance
I
nFET rectifier, I
= 150mA
LX3
Rectifier Off Current Threshold
Minimum On-Time
mA
ns
t
t
70
ON
Minimum Off-Time
70
ns
OFF
Shutdown Output Resistance
(Active Discharge Resistance)
2
I C programmable, default off
1
kI
BUCK4 ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P only, V
= V
= +5.0V, C
= 1000FF, C
= 0.1FF, C
= 20FF, L = 1FH, T = -40NC
OUT A
IN1A
IN1B
OUT1,2,3+CIN_
REFBP
to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Default Output Voltage
I
= 100mA
3.298
3.40
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
90
3.502
V
LOAD
I
= 100mA,
LOAD
Programmable Output Voltage
V
programmable output voltage step = 50mV
Efficiency (Note 4)
V
= 3.4V, I
= 500mA
%
mA
mI
mI
mA
mA
%
BUCK4
LOAD
Maximum Output Current
p-Channel On-Resistance
n-Channel On-Resistance
p-Channel Current-Limit Threshold
n-Channel Negative Current Limit
Maximum Duty Cycle
1800
I
I
= 150mA
100
100
LX4
= 150mA
LX4
2700
1500
100
Minimum Duty Cycle
16.5
2.0
%
PWM Frequency
f
1.8
2.2
MHz
OSC
2
Shutdown Output Resistance
(Active Discharge Resistance)
I C programmable,
default off
1
kI
Maxim Integrated
11
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
OUT1 (LDO1) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P:V
=+3.2VandC
=10FF,MAX8982X:V
=+3.3VandC
=20FF,C
=0.1FF,C =4.7FF,
OUT1
DDA
VDD_
DDA
VDD_
REFBP
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
2.619
300
TYP
MAX
UNITS
V
Default Output Voltage
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage (Note 4)
Line Regulation
I
= 50mA
2.70
2.781
LOAD
mA
mA
mV
mV
mV
V
= 90% of its regulation
310
550
50
940
100
OUT1
I
= 200mA, T = +85NC
A
LOAD
2.9V P V
P 3.65V, I
= 150mA
2.4
12
DDA
LOAD
Load Regulation
1mA < I
< 300mA
LOAD
di/dt = I
/0.1Fs, 1kHz < 1/T < 0.5MHz, where T is the
MAX
Transient Response
50
60
mV
dB
period of step load, 1mA to 300mA
Power-Supply Rejection
f = 10Hz to 10kHz, I = 30mA
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 30mA
45
FV
RMS
LOAD
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
Programmable Output Voltages
I
= 50mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
I
I
= 300mA
= 300mA
40
3
100
50
Fs
mV
I
Startup Transient Overshoot
(Note 4)
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
OUT2 (LDO2) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P:V
=+3.2VandC
=10FF,MAX8982X:V
=+3.3VandC
=20FF,C
=0.1FF,C =1FF,
OUT2
DDA
VDD_
DDA
VDD_
REFBP
T
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
A
PARAMETER
Default Output Voltage
CONDITION
MIN
1.746
150
TYP
MAX
UNITS
I
= 50mA
1.80
1.854
V
LOAD
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage (Note 4)
Line Regulation
mA
mA
mV
mV
mV
V
= 90% of its nominal regulation voltage
165
360
150
2.4
25
650
300
OUT2
I
= 100mA, T =+85NC
A
LOAD
2.9V P V
P 3.65V, I
= 100mA
DDA
LOAD
Load Regulation
50FA < I
< 150mA
LOAD
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 30mA
60
45
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 30mA
FV
RMS
LOAD
12
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
OUT2 (LDO2) ELECTRICAL CHARACTERISTICS (continued)
(MAX8982A/MAX8982P:V
=+3.2VandC
=10FF,MAX8982X:V
=+3.3VandC
=20FF,C
=0.1FF,C
=1FF,
OUT2
DDA
VDD_
DDA
VDD_
REFBP
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
TYP
1.50
1.80
2.70
1.70
MAX
UNITS
Programmable Output Voltages
I
= 50mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
I
I
= 150mA
= 150mA
40
3
100
50
Fs
Startup Transient Overshoot
(Note 4)
mV
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
I
OUT3 (LDO3) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P:V
=+3.2VandC
=10FF,MAX8982X:V
=+3.3VandC
=20FF,C
=0.1FF,C =1FF,
OUT3
DDB
VDD_
DDB
VDD_
REFBP
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
2.716
150
TYP
MAX
UNITS
Default Output Voltage
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage
I
= 50mA
2.800
2.884
V
LOAD
mA
mA
mV
mV
mV
V
= 90% of its regulation
165
360
150
2.4
25
650
300
OUT3
I
= 100mA, T = +85NC
A
LOAD
Line Regulation
3.2V P V
P 3.65V, I
= 100mA
DDB
LOAD
Load Regulation
50FA < I
< 150mA
LOAD
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 30mA
60
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 30mA
45
FV
RMS
LOAD
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
Programmable Output Voltage
I
= 50mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
I
I
= 150mA
= 150mA
100
50
Fs
mV
I
Startup Transient Overshoot
(Note 4)
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
Maxim Integrated
13
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
OUT4 (LDO4) ELECTRICAL CHARACTERISTICS
(MAX8982_: V
= V
= 1.8V, C
= 2.2FF, C
= 0.1FF, C = 2.2FF, T = -40NC to +85NC, unless otherwise noted.
OUT4 A
IN3
BUCK2
IN3
REFBP
Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
0.873
50
TYP
MAX
UNITS
V
Default Output Voltage
Maximum Output Current
Current Limit (Note 4)
Load Regulation
I
= 10mA
0.9
0.927
LOAD
mA
mA
mV
V
= 90% of its regulation
55
120
25
220
OUT4
50FA < I
< 10mA
LOAD
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 10mA
60
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 10mA
45
FV
LOAD
RMS
0.80
0.90
1.00
1.10
1.20
Programmable Output Voltage
I
= 10mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
I
I
= 50mA
= 50mA
100
50
Fs
mV
I
Startup Transient Overshoot
(Note 4)
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
OUT5 (LDO5) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
=+3.2VandC
=10FF,MAX8982X:V
=+3.3VandC
=20FF,C
=0.1FF,C =1FF,
OUT5
DDB
VDD_
DDB
VDD_
REFBP
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
2.91
150
165
TYP
MAX
UNITS
Default Output Voltage
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage (Note 4)
Line Regulation
I
= 50mA
3.00
3.09
V
LOAD
mA
mA
mV
mV
mV
V
= 90% of its regulation
360
150
2.4
25
650
300
OUT5
I
= 100mA, T = +85NC
A
LOAD
3.2V P V
P 3.65V, I
= 100mA
DDB
LOAD
Load Regulation
50FA < I
< 150mA, V
= 2.8V
LOAD
OUT
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 30mA
60
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 30mA
45
FV
RMS
LOAD
2.80
2.90
3.00
3.20
Programmable Output Voltage
I
= 50mA, V
= 3.4V for V = 3.2V
OUT
V
LOAD
LOAD
DDB
Startup Time from Shutdown
(Note 4)
I
I
= 150mA
= 150mA
100
50
Fs
mV
I
Startup Transient Overshoot
(Note 4)
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
14
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
OUT6 (LDO6) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P:V
=+3.2VandC
=10FF,MAX8982X:V
=+3.3VandC
=20FF,C
=0.1FF,C
=1FF,
DDB
VDD_
DDB
VDD_
REFBP
OUT6
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
Default Output Voltage
CONDITION
MIN
2.619
150
TYP
MAX
UNITS
I
= 50mA
2.70
2.781
V
LOAD
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage (Note 4)
Line Regulation
mA
mA
mV
mV
mV
V
= 90% of its regulation
165
360
150
2.2
25
650
300
OUT6
I
= 100mA, T = +85NC
A
LOAD
2.90V P V
P 3.65V, I
= 100mA
DDB
LOAD
Load Regulation
50FA < I
< 150mA
LOAD
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 30mA
60
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 30mA
45
FV
RMS
LOAD
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
Programmable Output Voltage
I
= 50mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
I
I
= 150mA
= 150mA
100
50
Fs
mV
I
Startup Transient Overshoot
(Note 4)
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
VSIM (LDO7) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P:V
=+3.2VandC
=10FF, MAX8982X:V
=+3.3VandC
=20FF, C
=0.1FF, C =1FF,
OUT
DDB
VDD_
DDB
VDD_
REFBP
T
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
A
PARAMETER
Output Voltage
CONDITION
MIN
1.746
2.91
150
TYP
1.80
3.00
MAX
1.854
3.09
UNITS
50FA < I
50FA < I
< 20mA, 1.8V mode
LOAD
V
< 20mA, 3.0V mode (default)
LOAD
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage (Note 4)
Line Regulation
2.9V P V
P 3.65V, 1.8V mode
mA
mA
mV
mV
mV
dB
FV
DDB
V
VSIM
= 90% of 1.8V mode
= 20mA, 3V mode
165
360
120
0.1
25
650
200
I
LOAD
2.9V P V
P 3.65V, I
= 50FA (1.8V mode)
DDB
LOAD
Load Regulation
50FA < I
< 20mA (1.8V mode)
LOAD
Power-Supply Rejection
Output Noise Voltage
f = 10kHz, I
= 10mA
57
LOAD
100Hz to 100kHz, I
= 10mA
80
LOAD
VSIM Discharge Resistance
(Active Discharge Resistance)
2
I C programmable, default off
100
I
Maxim Integrated
15
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
OUT8 (LDO8) ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P only, V
= V
= +5.0V, C
= 1.0FF, C
= 0.1FF, C = 1FF, T = -40NC to +85NC, unless
OUT8 A
IN4
IN1_
IN4
REFBP
otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Input Operating Range
Guaranteed by output voltage accuracy
3.0
5.5
V
Overvoltage Lockout
(Shutdown LDO8 Output)
V
rising, V
= V
IN4
5.75
5.93
V
IN4
IN1_
Overvoltage Hysteresis
Default Output Voltage
Maximum Output Current
Current Limit (Note 4)
Dropout Voltage (Note 4)
Line Regulation
250
mV
V
I
= 50mA
2.91
150
165
3.00
3.09
LOAD
mA
mA
mV
mV
mV
V
= 90% of its regulation
360
150
2.2
25
650
300
OUT8
100mA, T = +85NC
A
3.4V P V
P 5.5V, V
= 3.1V, I = 100mA
LOAD
IN4
OUT8
Load Regulation
50FA < I
< 150mA
LOAD
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 30mA
60
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage (RMS)
100Hz to 100kHz, I
= 30mA
45
FV
LOAD
RMS
3.00
3.10
3.20
3.30
Programmable Output Voltage
I
= 50mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
I
I
= 150mA
= 150mA
100
50
Fs
mV
I
Startup Transient Overshoot
(Note 4)
LOAD
2
Shutdown Output Impedance
(Active Discharge Resistance)
I C programmable, default off
100
OUT9 (LDO9) ELECTRICAL CHARACTERISTICS
(MAX8982_: V
= V
= 1.8V, C
= 2.2FF, C
= 0.1FF, C = 2.2FF, T = -40NC to +85NC, unless otherwise noted.
OUT9 A
IN3
BUCK2
IN3
REFBP
Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
0.873
50
TYP
MAX
UNITS
V
Default Output Voltage
Maximum Output Current
Current Limit (Note 4)
Load Regulation
I
= 10mA, V
= 1.8V
0.900
0.927
LOAD
IN3
mA
mA
mV
V
= 90% of its regulation
55
120
25
220
OUT9
50FA < I
< 50mA
LOAD
Power-Supply Rejection
f = 10Hz to 10kHz, I
= 10mA
60
dB
LOAD
DV
/DV
OUT
IN
Output Noise Voltage
100Hz to 100kHz, I
= 10mA
45
FV
LOAD
RMS
0.80
0.90
1.00
1.10
1.20
Programmable Output Voltage
I
I
= 10mA
= 50mA
V
LOAD
LOAD
Startup Time from Shutdown
(Note 4)
100
Fs
16
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
OUT9 (LDO9) ELECTRICAL CHARACTERISTICS (continued)
(MAX8982_: V
= V
= 1.8V, C
= 2.2FF, C
= 0.1FF, C = 2.2FF, T = -40NC to +85NC, unless otherwise noted.
OUT9 A
IN3
BUCK2
IN3
REFBP
Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
Startup Transient Overshoot
(Note 4)
Shutdown Output Impedance
(Active Discharge Resistance)
I
= 50mA
50
mV
LOAD
2
I C programmable, default off
100
I
RESET ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
= V
= +5V, MAX8982X: V
= V
= +3.3V, V
= 1.8V, C
= 2.2FF, C
=
IN1A
IN1B
IN1A
IN1B
BUCK2
BUCK2
REFBP
0.1FF, T = -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
A
PARAMETER
CONDITION
= 0FA
MIN
TYP
MAX
UNITS
V
BUCK2
- 0.3V
Output High Voltage
Output Low Voltage
Internal logic supply I
Internal logic supply I
V
SOURCE
= 500FA
0.3
V
SINK
From BUCK2 enable (Figure 4)
625
14
Fs
Fs
kI
RESET Enabled (Note 4)
RESET Disabled (Note 4)
Pullup Resistance to BUCK2
26
8
78
22
With respect to IRQ = low
IRQ ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
= V
= +5.0V, MAX8982X: V
= V
= +3.3V, V
= 1.8V, C
= 2.2FF, C = 0.1FF,
REFBP
IN1A
IN1B
IN1A
IN1B
BUCK2
BUCK2
T
= -40NC to +85NC. Typical values are at T = +25NC, unless otherwise specified.) (Note 3)
A
A
PARAMETER
CONDITION
= 0FA
MIN
TYP
MAX
UNITS
V
BUCK2
- 0.3V
Output High Voltage
Internal logic supply I
Internal logic supply I
V
SOURCE
Output Low Voltage
= 500FA
0.3
V
SINK
Pullup Resistance to BUCK2
100
200
400
kI
CURRENT REGULATOR ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
= V
= +5V and V
= 3.2V, MAX8982X: V
= V
= +3.3V and V
= 3.3V, C = 0.1FF,
REFBP
IN1A
IN1B
DD_
IN1A
IN1B
DD_
T
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
A
PARAMETER
DR_ Sink Current Range
CONDITION
MIN
TYP
MAX
UNITS
3
24
mA
DR_[2:0] = 000
DR_[2:0] = 001
DR_[2:0] = 010
DR_[2:0] = 011
DR_[2:0] = 100
DR_[2:0] = 101
DR_[2:0] = 110
3
6
9
12
15
18
21
24
DR_ Current Sink Programmable
mA
DR_[2:0] = 111 (default)
T
T
= +25NC
-10
-15
+10
+15
120
DR_ Sink Current Accuracy
(Note 4)
A
%
= -40NC to +85NC
A
V
Voltage Drop
I
= 24mA
60
mV
DR_
DR_
Maxim Integrated
17
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
FLASH TIMER ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P:V
=V
=+5VandV
=+3.2V,MAX8982X:V
=V
=+3.3VandV
=+3.3V,C =0.1FF,
REFBP
IN1A
IN1B
DD_
IN1A
IN1B
DD_
T
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 4, Figure 11)
A
A
PARAMETER
Flash Timer Resolution
CONDITIONS
MIN
TYP
25
MAX
3175
UNITS
ms
0
0 (0000000)
25 (0000001)
50
75
.
Pattern Period, t
7-bit programmable in 25ms steps
ms
P
.
3175 (1111111)
Number of Programmable On
Threshold
4
0
3175
0 (0000000)
25 (0000001)
Time for Flash to Turn On, t
1
7-bit programmable in 25ms steps
ms
50
.
.
3175 (1111111)
0
0
0
3175
0 (0000000)
25 (0000001)
Time for Flash to Turn On, t
2
7-bit programmable in 25ms steps
7-bit programmable in 25ms steps
7-bit programmable in 25ms steps
ms
ms
ms
50
.
.
3175 (1111111)
3175
0 (0000000)
25 (0000001)
Time for Flash to Turn On, t
3
50
.
.
3175 (1111111)
3175
0 (0000000)
25 (0000001)
Time for Flash to Turn On, t
4
50
.
.
3175 (1111111)
18
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
FLASH TIMER ELECTRICAL CHARACTERISTICS (continued)
(MAX8982A/MAX8982P:V
=V
=+5VandV
=+3.2V,MAX8982X:V
=V
=+3.3VandV
=+3.3V,C =0.1FF,
REFBP
IN1A
IN1B
DD_
IN1A
IN1B
DD_
T
= -40NC to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 4, Figure 11)
A
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
400
UNITS
25
25 (0000)
50 (0001)
4-bit programmable in 25ms steps, same for each flash
timer
Programmable On-Time, t
ms
75
.
ON
.
400 (1111)
N32KHZ ELECTRICAL CHARACTERISTICS
(MAX8982A/MAX8982P: V
= +3.2V, MAX8982X: V
= +3.3V, V
= 1.8V, C
= 2.2FF, C
= 0.1FF, T = -40NC
REFBP A
DD_
DD_
BUCK2
BUCK2
to +85NC, unless otherwise noted. Typical values are at T = +25NC.) (Note 3)
A
PARAMETER
CONDITION
= 2mA
MIN
TYP
MAX
UNITS
V
BUCK2
- 0.45V
Output High Voltage
Internal logic supply I
Internal logic supply I
V
SOURCE
Output Low Voltage
Output Duty Cycle
Output Frequency Range
Startup Time
= 2mA
0.45
70
V
%
SINK
30
50
32
Including initial startup, 20% tolerance
From BUCK2 enable (Figure 4)
25.6
38.4
225
10
kHz
Fs
Edge Jitter (Note 4)
ns
Note 3: Limits are 100% production tested at T = +25NC, unless otherwise noted. Limits over the temperature range are guaran-
A
teed by design.
Note 4: Guaranteed by design, not production tested.
Typical Operating Characteristics
(MAX8982A/MAX8982P: V
IN1A
= V
= 5V, MAX8982X: V
= V
= V
DDA
= V
DDB
= V
= 3.3V, C
= 0.1µF, T = -40°C
IN1B
IN1A
IN1B
IN4
REFBP A
to +85°C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at T = +25°C. Limits are 100% production tested at
A
T
= +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.)
A
SHUTDOWN CURRENT
vs. INPUT VOLTAGE (MAX8982A)
SHUTDOWN CURRENT
vs. INPUT VOLTAGE (MAX8982X)
NO LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX8982A)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
300
280
260
240
220
200
180
160
140
120
100
BUCK3, OUT3 ON
ALL OTHER OUTPUTS OFF
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Maxim Integrated
19
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Typical Operating Characteristics (continued)
(MAX8982A/MAX8982P: V
IN1A
= V
= 5V, MAX8982X: V
= V
= V
DDA
= V
DDB
= V
= 3.3V, C
= 0.1µF, T = -40°C
REFBP A
IN1B
IN1A
IN1B
IN4
to +85°C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at T = +25°C. Limits are 100% production tested at
A
T
= +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.)
A
NO LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX8982X)
BUCK1 LOAD REGULATION
300
280
260
240
220
200
180
160
140
120
100
0.950
0.925
0.900
0.875
0.850
0.825
0.800
OUT3 ON
ALL OTHER OUTPUTS OFF
L = 2.2µH, HITACHI METALS LTD
KSLI-252012AG-2R2
DCR = 100mI
3.0
3.5
4.0
4.5
5.0
5.5
0
200
700
1200
INPUT VOLTAGE (V)
LOAD CURRENT (mA)
BUCK1 EFFICIENCY
vs. LOAD CURRENT
BUCK1 LOAD TRANSIENT
MAX8982A toc06
100
90
80
70
60
50
40
30
V
IN
= 4.5V
AC-COUPLED
200mV/div
V
IN
= 4.1V
V
BUCK1
1.2A
1mA
V
= 5V
IN
V
= 1V
OUT
V
= 5.5V
10
I
IN
BUCK1
C
OUT
= 10µF
V
= 0.9V
OUT
1
100
1000
100µs/div
LOAD CURRENT (mA)
BUCK1 SWITCHING FREQUENCY
vs. LOAD CURRENT
BUCK1 SWITCHING FREQUENCY
vs. TEMPERATURE
2.5
2.0
1.5
1.0
0.5
0
2.200
2.150
2.100
2.050
2.000
1.950
1.900
1.850
1.800
1.750
0
200
700
1200
-40
-15
10
35
60
85
LOAD CURRENT (mA)
TEMPERATURE (°C)
20
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Typical Operating Characteristics (continued)
(MAX8982A/MAX8982P: V
IN1A
= V
= 5V, MAX8982X: V
= V
= V
= V
DDB
= V
= 3.3V, C
= 0.1µF, T = -40°C
REFBP A
IN1B
IN1A
IN1B
DDA
IN4
to +85°C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at T = +25°C. Limits are 100% production tested at
A
T
= +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.)
A
BUCK1 RAMP-UP TRANSITION
BUCK1 RAMP-DOWN TRANSITION
MAX8982A toc11
MAX8982A toc10
1.2V
0.6V
1.2V
0.6V
V
BUCK1
V
BUCK1
NO LOAD
12.5mV/µs RAMP RATE
I
= 1.2A
OUT
12.5mV/µs RAMP RATE
20µs/div
20µs/div
BUCK2 LOAD TRANSIENT
BUCK2 LOAD REGULATION
MAX8982A toc13
1.820
1.800
1.780
1.760
1.740
1.720
AC-COUPLED
100mV/div
V
BUCK2
600mA
1mA
I
L = 1.0µH, MURATA LQM2MPN1R0NG0
DCR = 85mI
BUCK2
V
= 1.8V
OUT
40µs/div
0
200
400
600
LOAD CURRENT (mA)
BUCK3 LOAD REGULATION
(MAX8982A/MAX8982P ONLY)
BUCK2 EFFICIENCY
vs. LOAD CURRENT
100
90
80
70
60
50
40
3.300
3.250
3.200
3.150
3.100
3.050
3.000
L = 2.2µH, HITACHI METALS LTD
KSLI-252012AG-2R2
DCR = 100mI
V
= 4.5V
IN
V
= 4.1V
IN
V
= 5V
IN
V
= 5.5V
IN
1
10
100
1000
0
100
200
300
400
500
600
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Maxim Integrated
21
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Typical Operating Characteristics (continued)
(MAX8982A/MAX8982P: V
IN1A
= V
= 5V, MAX8982X: V
= V
= V
DDA
= V
DDB
= V
= 3.3V, C
= 0.1µF, T = -40°C
REFBP A
IN1B
IN1A
IN1B
IN4
to +85°C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at T = +25°C. Limits are 100% production tested at
A
T
= +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.)
A
BUCK3 LOAD TRANSIENT
BUCK3 EFFICIENCY vs. LOAD CURRENT
(MAX8982A/MAX8982P ONLY)
(MAX8982A/MAX8982P ONLY)
MAX8982A toc16
100
95
90
85
80
75
70
65
60
55
50
V
IN
= 4.5V
V
IN
= 4.1V
V
C
= 3.2V
= 10µF
OUT
OUT
V
BUCK3
AC-COUPLED
100mV/div
V
= 5V
IN
V
IN
= 5.5V
600mA
1mA
I
BUCK3
V
= 3.2V
OUT
1
10
100
1000
20µs/div
LOAD CURRENT (mA)
BUCK4 LOAD TRANSIENT
(MAX8982A/MAX8982P ONLY)
BUCK4 LOAD REGULATION
(MAX8982A/MAX8982P ONLY)
MAX8982A toc19
3.410
3.400
3.390
3.380
3.370
3.360
3.350
3.340
3.330
AC-COUPLED
50mV/div
V
BUCK4
1.5A
1mA
L = TAIYO YUDEN NR3015T1R0N
DCR = 30mI
I
BUCK4
V
= 3.4V
OUT
1mA TO 1.5A
0
100
200
300
400
500
600
20µs/div
LOAD CURRENT (mA)
BUCK4 SWITCHING FREQUENCY vs. LOAD CURRENT
BUCK4 EFFICIENCY vs. LOAD CURRENT
(MAX8982A/MAX8982P ONLY)
(MAX8982A/MAX8982P ONLY)
2.5
100
90
80
70
60
50
40
30
20
10
2.0
1.5
1.0
0.5
0
V
V
V
= 4.1V
= 4.5V
= 5V
IN
IN
IN
V
= 5.5V
IN
V
= 3.4V
OUT
0
200
400
600
1
10
100
1000
10,000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
22
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Typical Operating Characteristics (continued)
(MAX8982A/MAX8982P: V
IN1A
= V
= 5V, MAX8982X: V
= V
= V
= V
DDB
= V
= 3.3V, C
= 0.1µF, T = -40°C
REFBP A
IN1B
IN1A
IN1B
DDA
IN4
to +85°C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at T = +25°C. Limits are 100% production tested at
A
T
= +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.)
A
BUCK4 SWITCHING FREQUENCY vs. TEMPERATURE
(MAX8982A/MAX8982P ONLY)
LDO1 LOAD REGULATION
LDO2 LOAD REGULATION
2.20
2.705
2.704
2.703
2.702
2.701
2.700
2.699
2.698
2.697
1.812
1.810
1.808
1.806
1.804
1.802
1.800
1.798
1.796
1.794
1.792
1.790
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
-40
-15
10
35
60
85
0
50
100
150
200
250
300
0
50
100
150
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO3 LOAD REGULATION
LDO4 LOAD REGULATION
2.820
2.815
2.810
2.805
2.800
2.795
2.790
0.903
0.902
0.901
0
50
100
150
0
10
20
30
40
50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO5 LOAD REGULATION
LDO6 LOAD REGULATION
3.020
3.010
3.000
2.990
2.980
2.970
2.960
2.720
2.715
2.710
2.705
2.700
2.695
2.690
0
50
100
150
0
50
100
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Maxim Integrated
23
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Typical Operating Characteristics (continued)
(MAX8982A/MAX8982P: V
IN1A
= V
= 5V, MAX8982X: V
= V
= V
DDA
= V
DDB
= V
= 3.3V, C
= 0.1µF, T = -40°C
REFBP A
IN1B
IN1A
IN1B
IN4
to +85°C, Circuits of Figures 2 and 3, unless otherwise noted. Typical values are at T = +25°C. Limits are 100% production tested at
A
T
= +25NC, unless otherwise noted. Limits over the temperature range are guaranteed by design.)
A
LDO8 LOAD REGULATION
(MAX8982A/MAX8982P ONLY)
LDO7 LOAD REGULATION
3.025
3.020
3.015
3.010
3.005
3.000
2.995
2.990
2.985
3.020
3.015
3.010
3.005
3.000
2.995
2.990
2.985
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LED CURRENT ACCURACY
vs. LED CURRENT SETTING
LDO9 LOAD REGULATION
0.902
10
8
LUMEX SML-LX2832SISUGSBC
6
LED3
4
2
0
LED2
-2
-4
0.900
0
20
40
60
80
100
0
5
10
15
20
25
LOAD CURRENT (mA)
LED CURRENT (mA)
LED FLASH WAVEFORMS
OVERVOLTAGE PROTECTION
MAX8982A toc34
MAX8982A toc33
5V/div
V
IN_
24mA
0V
1V/div
0V
V
V
BUCK1
BUCK2
0A
I
LED2
24mA
1V/div
0V
V
LDO1
I
LED3
0A
2V/div
0V
1s/div
400µs/div
24
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Pin Configurations
TOP VIEW
(BUMP ON BOTTOM)
MAX8982A/MAX8982P
1
2
3
4
5
6
7
N32
kHz
REF
BP
OUT9
GND
OUT6
OUT3
OUT2
A
B
C
V
V
OUT4
IN3
DR1
DR3
DR2
OUT8
OUT5
VSIM
SCL
DDB
DDA
OUT1
RESET
IRQ
PWR_
REQ
BUCK3
BUCK4
PGND4
DVS1
EN
SDA
LX3
BUCK2
BUCK1
LX1
LX2
D
PGND2
PGND1
IN1B
LX4
LX4
PGND3
PGND4
E
F
IN4
IN1A
WLP
Maxim Integrated
25
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Pin Configurations (continued)
TOP VIEW
(BUMP ON BOTTOM)
MAX8982X
1
2
3
4
5
6
7
N32
kHz
REF
BP
OUT9
GND
OUT6
OUT3
OUT2
A
B
C
V
V
OUT4
IN3
DR1
DR3
DR2
DNC
VSIM
SCL
DDB
DDA
OUT5
OUT1
RESET
IRQ
PWR_
REQ
BUCK2
BUCK1
LX1
DVS1
EN
SDA
DNC
DNC
DNC
LX2
D
PGND2
PGND3
IN1B
DNC
DNC
E
F
PGND1
IN4
IN1A
PGND4
PGND4
WLP
26
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Pin Description
NAME
MAX8982A/
MAX8982P
PIN
FUNCTION
MAX8982X
GROUND
A3
GND
GND
Analog Ground
F1
PGND1
PGND2
PGND3
PGND4
PGND1
PGND2
PGND3
PGND4
Power Ground for BUCK1
Power Ground for BUCK2
Power Ground for BUCK3
Power Ground for BUCK4
E1
E7
F6, F7
INPUT SUPPLY
Input Supply to the IC. The operating voltage range for the MAX8982A is 4.1V to 5.5V.
Connect three 330FF tantalum capacitors as close as possible to IN1A and IN1B.
Connect IN1A to IN1B.
IN1A
—
—
F4
Input Supply to the IC. The operating voltage range for the MAX8982X is 2.9V to 5.5V.
Bypass with a 22FF ceramic capacitor as close as possible to IN1A and IN1B. Connect
IN1A to IN1B.
IN1A
E4
C1
IN1B
IN3
IN1B
IN3
Input Supply to the IC. Connect IN1B to IN1A.
Input Supply for LDO4 and LDO9. Connect IN3 to the BUCK2 output. Bypass IN3 with a
2.2FF ceramic capacitor as close as possible to IN3.
Input Supply for LDO8. Bypass with a 1FF ceramic capacitor as close as possible to IN4.
The IN4 operating range is from 3.0V to 5.5V. Connect IN4 to either IN1A and IN1B.
IN4
—
—
IN4
—
F3
Connect IN4 to Both IN1A and IN1B
Power Input for LDO1 and LDO2. Connect V
ceramic capacitor as close as possible to V
to V
to V
. Bypass V
with a 10FF
DDA
.
DDB
DDA
V
DDA
—
B7
B6
DDA
V
V
Power Input for LDO1 and LDO2. Connect V
, IN1A, and IN1B.
to V
DDA
—
DDA
DDB
V
Power Input for LDO3, LDO5, LDO6, and LDO7. Connect V
.
DDA
DDB
—
DDB
Power Input for LDO3, LDO5, LDO6, and LDO7. Connect V
to V
IN1A, and IN1B
DDB
DDB
DDA, .
BUCK CONVERTERS
BUCK1 Inductor Connection. LX1 connects to the drains of the internal p-channel and
n-channel MOSFETs.
F2
LX1
LX2
LX1
LX2
BUCK2 Inductor Connection. LX2 connects to the drains of the internal p-channel and
n-channel MOSFETs.
D1
BUCK3 Inductor Connection. LX3 connects to the drains of the internal p-channel and
n-channel MOSFETs.
LX3
—
—
DNC
—
D7
Do Not Connect
BUCK4 Inductor Connection. LX4 connects to the drains of the internal p-channel and
n-channel MOSFETs. Connect the two LX4 bumps together externally.
LX4
E5, F5
—
DNC
BUCK1
BUCK2
—
Do Not Connect
E2
D2
BUCK1
BUCK2
BUCK3
—
BUCK1 Output Feedback
BUCK2 Output Feedback
BUCK3 Output Feedback
Do Not Connect
D6
E6
DNC
—
BUCK4
—
BUCK4 Output Feedback
Do Not Connect
DNC
Maxim Integrated
27
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Pin Description (continued)
NAME
PIN
FUNCTION
MAX8982A/
MAX8982P
MAX8982X
LDO REGULATORS
LDO1 Output. Bypass OUT1 with a 4.7FF ceramic capacitor. OUT1 supplies loads up to
300mA. The default output voltage is 2.7V.
C7
A7
A6
B1
C4
A5
B5
OUT1
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
VSIM
LDO2 Output. Bypass OUT2 with a 1FF ceramic capacitor. OUT2 supplies loads up to
150mA. The default output voltage is 1.8V.
OUT2
OUT3
OUT4
OUT5
OUT6
VSIM
LDO3 Output. Bypass OUT3 with a 1FF ceramic capacitor. OUT3 supplies loads up to
150mA. The default output voltage is 2.8V.
LDO4 Output. Bypass OUT4 with a 2.2FF ceramic capacitor. OUT4 supplies loads up to
50mA. The default output voltage is 0.9V.
LDO5 Output. Bypass OUT5 with a 1FF ceramic capacitor. OUT5 supplies loads up to
150mA. The default output voltage is 3.0V.
LDO6 Output. Bypass OUT6 with a 1FF ceramic capacitor. OUT6 supplies loads up to
150mA. The default output voltage is 2.7V.
LDO7 Output. Bypass VSIM with a 1FF ceramic capacitor. VSIM supplies loads up to
150mA. The default output voltage is 3V.
LDO8 Output. Bypass OUT8 with a 1FF ceramic capacitor. OUT8 supplies loads up to
150mA. The default output voltage is 3V.
OUT8
—
—
B4
A2
DNC
OUT9
Do Not Connect
LDO9 Output. Bypass OUT9 with a 2.2FF ceramic capacitor. OUT9 supplies loads up to
50mA. The default output voltage is 0.9V.
OUT9
I2C INTERFACE
D4
C5
SDA
SCL
SDA
SCL
I2C Data. SDA is high impedance when off.
I2C Clock. SCL is high impedance when off.
CURRENT REGULATORS
Current Regulated Driver 1. Typically used to drive an LED. DR1 can be programmed to
sink 3mA to 24mA in 8 steps (24mA default). If the flash timer is activated, the LED can
be programmed to turn on/off in a preprogrammed pattern. See the Embedded Flash
Timer section.
Current Regulated Driver 2. Typically used to drive an LED. DR2 can be programmed to
sink 3mA to 24mA in 8 steps (24mA default). If the flash timer is activated, the LED can
be programmed to turn on/off in a preprogrammed pattern. See the Embedded Flash
Timer section.
Current Regulated Driver 3. Typically used to drive an LED. DR3 can be programmed to
sink 3mA to 24mA in 8 steps (24mA default). If the flash timer is activated, the LED can
be programmed to turn on/off in a preprogrammed pattern. See the Embedded Flash
Timer section.
B2
B3
C2
DR1
DR2
DR1
DR2
DR3
EN
DR3
EN
LOGIC INPUTS
E3
Active-High IC Enable Input
Active-High to Enable All Designated Step-Down Regulators and LDOs in Sequence.
Active-high/low to enable/disable all step-down converters and LDOs after power-on.
The values in the BUCK1DVS1 and BUCK1DVS2 registers are reset to their defaults
when PWR_REQ goes low in normal operation.
D5
D3
PWR_REQ PWR_REQ
DVS1
DVS1
BUCK1 Output Selection Input for DVS Function
28
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Pin Description (continued)
NAME
MAX8982A/
MAX8982P
PIN
FUNCTION
MAX8982X
LOGIC OUTPUTS
C6
Active-Low, Open-Drain Interrupt Output. Internal pullup resistor, 200kI, to BUCK2.
IRQ
IRQ
Active-Low, Open-Drain Reset Output. There is an internal 14kI pullup resistor to
BUCK2.
C3
RESET
RESET
REFERENCE OUTPUT
Reference Bypass. Connect the reference bypass capacitor from REFBP to GND. See
A4
REFBP
REFBP
Table 3. High impedance in off condition. V
is 0.8V (typ). Do not use to provide
REFBP
power to external circuitry.
32kHz CLOCK
A1
N32kHz
N32kHz
32kHz Clock Output. This output is supplied from BUCK2.
Table 1. Summary of Power Supplies
OUT7
(VSIM)
PARAMETER BUCK1 BUCK2 BUCK3* BUCK4* OUT1 OUT2 OUT3 OUT4 OUT5 OUT6
OUT8* OUT9
System
IO
LDO
INPUT
USB
BB
Function
Core
PA
RF
RF
Analog PLL
SD
TCXO
SIM
Default
Voltage (V)
3.0
0.9
0.9
1.8
3.2
3.4
2.7
1.8
2.8
0.9
3.0
2.7
3.00
Continuous
Output Current
(mA)
1200**
150
50
600
N/A
600
1800
300
150
150
50
150
150
150
1300***
0.600
3.00
3.10
3.20
3.30
0.8
0.9
1.0
1.1
1.2
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
1.5
1.8
2.7
1.7
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
0.8
0.9
1.0
1.1
1.2
2.80
2.90
3.00
3.20
2.65
2.70
2.75
2.80
2.85
2.90
2.95
3.00
1.80
3.00
25mV
step
Programmable
Voltage
Options (V)
1.20
*BUCK3, BUCK4, and OUT8 are for the MAX8982A/MAX8982P only.
**MAX8982A/MAX8982X.
***MAX8982P.
Maxim Integrated
29
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 1. Summary of Power Supplies (continued)
PARAMETER BUCK1 BUCK2 BUCK3* BUCK4* OUT1 OUT2 OUT3 OUT4 OUT5 OUT6
Default ON
OUT7
(VSIM)
OUT8* OUT9
PWR_
REQ
PWR_ PWR_
PWR_
REQ
PWR_
REQ
ON
ON
at Initial
Startup
ON
ON
OFF
ON
OFF
OFF
REQ
REQ
I2C
or
I2C
or
I2C
or
PWR_
REQ
I2C
or
PWR_
REQ
I2C
or
PWR_
REQ
I2C
or
I2C
or
I2C
or
I2C
or
I2C
or
I2C
or
I2C
or
I2C
or
ON/OFF
Control After
Power-Up
PWR_ PWR_
REQ
PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_ PWR_
REQ
REQ
REQ
REQ
REQ
REQ
REQ
REQ
REQ
Default
Active
Discharge
Resistor
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
*BUCK3, BUCK4, and OUT8 are for the MAX8982A/MAX8982P only.
30
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
USB
INPUT
IN1A
IN1_
UVLO
IN1A
IN1B
ON/OFF SEQUENCE
5V
D-
D+
G
LX4
LX4
3.4V (DEFAULT)
3.0V TO 3.75V IN 50mV STEPS
P
3.8V
2.2µH
STEP-DOWN
CONVERTER 4
(1.8A)
2.7V FOR MAX8982P
OVP
2.2µF
330µF * 3
GSM PA/
UMTS PA
SHUTDOWN SIGNAL
N
5.75V
REFBP
GND
PGND4
0.1µF
PGND4
BUCK4
IN3
IN1A
0.9V
OUT9
BB
0.9V (DEFAULT)
0.6V TO 1.2V
IN 25mV STEPS
CORE
2.2µF
P
2.2µH
LDO9
(50mA)
LX1
STEP-DOWN
IN1B
DC-DC 1
CONVERTER
(1.2A)
2.2µF
N
N
UVLO
(3.8V)
REF
(0.8V)
PGND1
BUCK1
DVS1
V
DDB
THERMAL
SHUTDOWN
+160°C
DCDC 1 SEL
2.7V
OUT6
TCXO
IN1A
1µF
LDO6
(50mA)
P
1µH
1.8V
LX2
STEP-DOWN
DC-DC 2
CONVERTER
(DEFAULT
VCC_IO
N
2.2µF
N
PGND2
ON, 600mA)
ON/OFF
SEQUENCE
BUCK2
IN3
16ms
TIMER
SHUTDOWN
SIGNAL
2.2µF
OUT4
0.9V
PLL
IN1_
BB
EN
2.2µF
CHIPSET
ICE8060
ON E400
PLATFORM
LDO4
(50mA)
BUCK2
N
BB CHIPSET
ICE 8060
200kI
ON E400
PLATFORM
IRQ
INTERRUPT
ON/OFF CONTROL
AND
I C INTERFACE
BUCK2
BUCK2
625µs
RESET
14kI
2
SDA
SDA
SCL
RESET
POR_N
RTBON
IN1A
SCL
3.2V (DEFAULT)
2.9V TO 3.65V
IN 50mV STEPS
P
STEP-DOWN
2.2µH
LX3
DC-DC
3
CONVERTER
(DEFAULT ON)
PWR_REQ
2.2µF
N
PWR_REQ
PGND3
IN1_
1µF
BUCK3
VDDA
VDDB
IN4
MAX8982A
MAX8982P
LDO
10µF
2.8V
INPUT
3.0V
HS USB
ANALOG
BASEBAND
OUT3
OUT2
OUT1
OUT5
VSIM
OUT8
TRANSCEIVER
1µF
V
V
V
V
V
DDB
DDA
DDA
DDB
DDB
1µF
1µF
REF
LDO8
(DEFAULT ON)
150mA
LDO3
DEFAULT ON
150mA
N
N
1.8V
2.7V
3.0V
RF1V8
32kHz
OSCILLATOR
RF
CHIPSET
ICE 8260
LDO2
(150mA)
N
N
N
N
BUCK2
N32kHz
BB
OSC 32kI
RF2V7
4.7µF
LDO1
(300mA)
IN1_
DR1
DR2
DR3
3-CHANNEL
SD CARD
CURRENT
REGULATOR
(24mA,
FLASH
TIMER
1µF
LDO5
(150mA)
DEFAULT)
OPTIONAL
RESISTORS
USIM
1µF
1.8V/3.0V
SIM LDO (LDO7)
150mA
(3—24mA IN 3mA STEPS)
Figure 1. MAX8982A/MAX8982P Typical Application Circuit and Functional Block Diagram
Maxim Integrated
31
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 2. External Component List for Figure 1
LOCATION
EXTERNAL COMPONENTS
NOTES
Buck stability and GSM PA supply
Input for LDO4 and LDO9
Input for LDO8
IN1A, IN1B
IN3
3 x 330FF tantalum capacitors
2.2FF
1.0FF
IN4
LDO compensation and load transient
response
OUT1
4.7FF
OUT2
1.0FF
1.0FF
2.2FF
1.0FF
1.0FF
1.0FF
1.0FF
2.2FF
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
OUT3
OUT4
OUT5
OUT6
VSIM (OUT7)
OUT8
OUT9
Total capacitance R total output capacitance
for LDO1, LDO2, LDO3, LDO5, LDO6, and
V
, V
All LDOs stability
DDA DDB
VSIM. Use a 10FF capacitor on V
/V
DDA DDB
as recommended.
BUCK1 for BB Core
2.2FF
2.2FF
2.2FF
For low noise, 1.2A continuous load
For low noise
BUCK2 for BB System IO
BUCK3 as LDO Input
For low noise
BUCK4 for GSM PA/UMTS PA
2 x 22FF
Supply for both GSM PA and UMTS PA
LX1
LX2
LX3
LX4
REFBP
EN
1FH to 4.7FH
2.2FH recommended (Table 60)
1.0FH recommended (Table 60)
2.2FH recommended (Table 60)
2.2FH recommended (Table 60)
Noise filter
1FH to 4.7FH
1FH to 4.7FH
1FH to 4.7FH
0.1FF
A pulldown resistor, if necessary.
Any Bump Required to Pass 8kV
Module Level ESD
0.1FF
Absorb ESD energy
Note: Input/output capacitance should be as close as possible to the IC. All capacitors are ceramic X5R or X7R, unless otherwise noted.
32
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
IN1A
0.9V (DEFAULT)
0.6V TO 1.2V
IN 25mV STEPS
V
V
DDB
DDA
P
2.2µH
LX1
OVP
CORE
STEP-DOWN
DC-DC 1
CONVERTER
(1.2A)
3.3V
SHUTDOWN SIGNAL
ON/OFF SEQUENCE
INPUT
IN1A
IN1B
IN4
2.2µF
5.75V
N
22µF
PGND1
UVLO
2.7V
BUCK1
DVS1
REFBP
GND
DCDC 1 SEL
VCC_IO
IN1A
0.1µF
P
IN3
1µH
1.8V
0.9V
OUT9
LX2
VCC_USB
STEP-DOWN
DC-DC 2
CONVERTER
(DEFAULT
2.2µF
IN1B
2.2µF
N
LDO9
(50mA)
PGND2
ON, 600mA)
UVLO
(2.7V)
REF
(0.8V)
N
BUCK2
IN3
V
DDB
THERMAL
SHUTDOWN
+160°C
2.7V
OUT6
TCXO
2.2µF
0.9V
1µF
OUT4
LDO6
VCC_PLL
(50mA)
1µF
N
LDO4
(50mA)
N
BB CHIPSET
ICE 8060
ON E400
PLATFORM
BUCK2
ON = BUCK 2EN + 625µs
BB
ON/OFF
14kI
CHIPSET
ICE8060
ON E400
PLATFORM
SEQUENCE
16ms
TIMER
RESET
RESET
SHUTDOWN
SIGNAL
POR_N
IN1_
RTBON
EN
ANALOG
OUT3
2.8V
1.8V
2.7V
3.0V
1.8V
BASEBAND
ON/OFF CONTROL
AND
I C INTERFACE
BUCK2
V
V
V
V
V
DDB
1µF
1µF
LDO3
DEFAULT ON
150mA
200kI
2
N
N
N
N
N
IRQ
INTERRUPT
OUT2
OUT1
OUT5
SDA
RF1V8
SDA
SCL
DDA
DDA
DDB
DDB
RF
CHIPSET
ICE 82 xx
LDO2
(150mA)
SCL
MAX8982X
PWR_REQ
PWR_REQ
RF2V7
4.7µF
LDO1
(300mA)
32kHz
OSCILLATOR
BUCK2
N32kHz
BB
OSC 32kI
SD CARD
1µF
LDO5
(150mA)
3.3V INPUT
DR1
DR2
DR3
3-CHANNEL
CURRENT
REGULATOR
(24mA,
FLASH
TIMER
V
SIM
USIM
1µF
DEFAULT)
1.8V/3.0V
SIM LDO (LDO7)
150mA
OPTIONAL
RESISTORS
(3—24mA IN 3mA STEPS)
Figure 2. MAX8982X Typical Application Circuit and Functional Block Diagram
Maxim Integrated
33
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 3. External Component List for Figure 2
LOCATION
EXTERNAL COMPONENTS
NOTES
IN1A, IN1B
IN3
22FF
Buck stability
2.2FF
Input for LDO4 and LDO9
Connect to IN1A and IN1B
IN4
LDO compensation and load transient
response
OUT1
4.7FF
OUT2
1.0FF
1.0FF
2.2FF
1.0FF
1.0FF
1.0FF
2.2FF
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
LDO compensation
OUT3
OUT4
OUT5
OUT6
VSIM (OUT7)
OUT9
Total capacitance R total output capacitance
for LDO1, LDO2, LDO3, LDO5, LDO6, and
VSIM.
All LDOs stability. Connect V
and
DDA
V
, V
DDA DDB
V
to IN1A and IN1B.
DDB
BUCK1 for BB Core
2.2FF
For low noise, 1.2A continuous load
For low noise
BUCK2 for BB System IO
2.2FF
LX1
1FH to 4.7FH
2.2FH recommended (Table 60)
1.0FH recommended (Table 60)
Noise filter
LX2
1FH to 4.7FH
REFBP
EN
0.1FF
A pulldown resistor, if necessary
Any Bump Required to Pass 8kV
Module Level ESD
0.1FF
Absorb ESD energy
Note: Input/output capacitance should be as close as possible to the IC. All capacitors are ceramic X5R or X7R, unless otherwise noted.
Any regulator that is set to on or off though I2C is not
affected by PWR_REQ, except for BUCK1. The pro-
Detailed Description
Power-On/Off Control
The power-on/off state diagram is shown in Figure 3.
When the IN1_ supply voltage is valid and EN is high,
the default power supplies turn on in sequence (Figure
4). Once powered up, any step-down or LDO output can
be enabled or disabled through I2C, or they can be pro-
grammed to be controlled by the PWR_REQ logic input.
grammed values in BUCK1DVS1 and BUCK1DVS2 are
reset to their defaults when PWR_REQ goes low even in
normal operation.
Group A: BUCK3 (MAX8982A/MAX8982P only)
LDO2 (default is PWR_REQ On mode)
BUCK2
Group B: LDO1 (default is PWR_REQ On mode)
LDO3
PWR_REQ
PWR_REQ is a control input from baseband chipset used
to enable/disable specified regulators.
BUCK4 (MAX8982A/MAX8982P only)
Group C: LDO6 (default is PWR_REQ On mode)
After power-up, when PWR_REQ goes logic-high, any
step-down or LDO output programmed for PWR_REQ
control is enabled in a predefined sequence. The regulators
are powered up in four groups as shown in Figure 5. See the
following for the regulators belonging to each group. When
PWR_REQ goes logic-low, all regulators programmed for
PWR_REQ control are turned off simultaneously.
LDO5
LDO7
LDO8 (MAX8982A/MAX8982P only)
Group D: BUCK1 (default is PWR_REQ On mode)
LDO4 (default is PWR_REQ On mode)
LDO9
34
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
enable this discharge resistor, set the appropriate bit in
the BUCK1-4ADIS, LDO1-8ADIS, or LDO9ADIS register.
The active discharge resistor values are specified in the
General Electrical Characteristics table.
Active Discharge
All regulators include an internal resistor for discharging
the output when the regulator is shut down. In the default
state (except BUCK2), this resistor is not connected so
the output decay depends only on the applied load. To
V
< 3.5V (MAX8982A)
IN1_
OR V
OR V
OR EN = LOW
< 2.4V (MAX8982P/MAX8982X)
> 5.75V
IN1_
IN1_
SHUTDOWN
ALL REGULATORS
DISABLED
FROM
NOTE: ENABLE OF BUCKS AND
LDOS AND CONTROL OF
BUCKS AND LDOS
2
I C HIGH IMPEDANCE
REF DISABLED
32kHz DISABLED
ANY STATE
BY PWR_REQ
CAN BE MODIFIED
AFTER STARTUP THROUGH I C.
V
V
> 3.8V (TYP) (MAX8982A)
> 2.7V (TYP) (MAX8982P/MAX8982X)
IN1_
IN1_
2
AND EN = HIGH
POWER-UP
BUCK1 ENABLED
LDO1 ENABLED
LDO2 ENABLED
LDO4 ENABLED
LDO6 ENABLED
RESET = HIGH
BUCK3 ENABLED (MAX8982A/MAX8982P)
BUCK2 ENABLED
LDO3 ENABLED
LDO8 ENABLED (MAX8982A/MAX8982P)
LDO9 ENABLED
PWR_REQ = HIGH
V
= 0.8V
REFBP
2
RESET = HIGH
I C ENABLE
V
= 0.8V
REFBP
32kHz CLOCK ENABLED
2
I C ENABLED
32kHz CLOCK ENABLED
PWR_REQ
= HIGH
PWR_REQ
= LOW
BUCK1 DISABLED
LDO1 DISABLED
LDO2 DISABLED
LDO4 DISABLED
LDO6 DISABLED
RESET = HIGH
V
= 0.8V
REFBP
2
I C ENABLED
32kHz CLOCK ENABLED
Figure 3. Power-On/Off State Diagram with IN3 Connected to BUCK2 Output and IN4 Connected to IN1_. Default PWR_REQ
Regulators Are Shown.
Maxim Integrated
35
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
ON SEQUENCING RESTARTS
WHEN INPUT IS ABOVE
UVLO RISING
EN AND IN1_
UVLO RISING
~16ms
UVLO FALLING
THRESHOLD
BUCK 3
(3.2V)
125µs
BUCK 2
FOR IO (1.8V)
225µs
32kHz OUTPUT
CONTINUOUS
OUT 3
FOR ANALOG (2.8V)
375µs
OUT 8
125µs
FOR USB (3.0V)
OUT 9
125µs
FOR BB (0.9V)
625µs
RESET
OTHER ON-
31µs
REGULATORS
31µs TO 62µs
IRQ
OPERATING
STATE
POWER-ON
SEQUENCE
POWER-ON
SEQUENCE
OFF
ON
OFF
Figure 4. MAX8982_ Power-On Timing Diagram at Initial Startup with EN Connected to IN1_. BUCK3 and OUT8 Are for the
MAX8982A/MAX8982P Only.
36
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
PWR_REQ
GROUP A : OUT 2,*
(BUILT-IN TIME DELAY TO
~10µs
ENABLE REGULATORS)
BUCK 2, BUCK 3**
OUTPUT DECAY DEPENDS ON THE LOAD
GROUP B : LDO1,*
OUT 3, BUCK 4**
100µs
GROUP C : OUT6,*
200µs
OUT5, OUT7, OUT8**
GROUP D : BUCK 1*, OUT4,*
OUT9
375µs
2
*THESE REGULATORS DEFAULT TO PWR_REQ CONTROL. THE OTHERS MUST BE PROGRAMED TO PWR_REQ CONTROL BY I C.
**BUCK3, BUCK4, AND OUT8 ARE FOR THE MAX8982A/MAX8982P ONLY.
Figure 5. MAX8982_ Power-On Timing Diagram in PWR_REQ ON Mode After Power-Up
BUCK1, BUCK2, and BUCK3
Step-Down Converters
Setting the Output Voltage on BUCK1
The default output is 0.9V. The BUCK1 voltage is program-
mable through I2C from 0.6V to 1.2V in 25mV increments.
The step-down converters are optimized for high effi-
ciency over a wide load range, small external component
size, low output ripple, and excellent transient response.
The step-down converters also feature an internal
MOSFET switch with optimized on-resistance and an
internal synchronous rectifier to maximize the efficiency
and reduce the number of external components. The ICs
use a proprietary hysteretic PWM control scheme that
switches with a nearly fixed frequency. Figure 6 shows
the frequency variation versus load current with a 5V
Dynamic Voltage Scaling (DVS)
Function on Buck 1
BUCK1 includes DVS that allows two output voltages
to be programmed through I2C, and an external con-
trol input to select between the two voltages. Toggling
DVS1 changes the BUCK1 output voltage on-the-fly
between the two programmed voltages (Figure 7). Each
BUCK1DVS_ register specifies a voltage in the 0.6V to
1.2V range in 25mV increments.
input supply and at T = +25°C.
A
FREQUENCY vs. LOAD AT 5V INPUT
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
BUCK1DVS1
(0X3F)
(DEFAULT = 0.9V)
2
I C INTERFACE
BUCK1 OUTPUT
(DEFAULT = 0.9V)
BUCK1
BUCK2
BUCK3
0.6V TO 1.2V
IN 25mV STEPS
BUCK1DVS2
(0X40)
(DEFAULT = 0.9V)
DVS1
Truth Table
DVS1
High
Low
BUCK1 OUTPUT
Set by BUCK1DVS2 register
Set by BUCK1DVS1 register
1
10 50 100 200 300 400 500
LOAD (mA)
Figure 6. Frequency Variation vs. Load Current with a 5V Input
Supply
Figure 7. DVS1 Logic Diagram
Maxim Integrated
37
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Ramp-Up/Down Slope Control on BUCK1
Reference Bypass (REFBP)
BUCK1 uses a controlled ramp rate when it is enabled
and when changing between output voltage settings.
Four programmable slew rates are available for BUCK1.
The default value is 12.5mV/Fs (Table 4). The same slew
rate is applied for ramp-up/down.
The reference bypass is for low noise filtering only and
must not be loaded. Bypass REFBP with a 0.1FF ceramic
capacitor. The REFBP voltage is 0.8V (typ). Do not use
REFBP to provide power to external circuitry.
Thermal Overload Protection
If the internal die temperature of any LDOs or step-
down regulators reaches +160NC, the ICs shut down the
regulator locally. The regulator is reenabled after it cools
by 10NC. The ICs also contain a single +125NC thermal
detector located in the center of the die. When the tem-
perature at the center of the die exceeds +125NC, this
detector triggers and activates an interrupt.
Setting the Output Voltage on BUCK2
The BUCK2 output voltage is fixed at 1.8V. No program-
mable output is available.
Setting the Output Voltage on BUCK3
The BUCK3 default output is 3.2V. The BUCK3 output
voltage is programmable from 2.9V to 3.65V in 50mV
increments through I2C. BUCK3 is only available on the
MAX8982A/MAX8982P.
Undervoltage Lockout (UVLO)
The ICs monitor the voltage at the IN1_ power input.
When this voltage drops below 3.5V (MAX8982A) or 2.4V
(MAX8982P/MAX8982X), the ICs shut down. The ICs
turn on when this voltage rises above 3.8V (MAX8982A)
or 2.7V (MAX8982P/MAX8982X) and EN is high. After a
UVLO event, all registers are reset to their POR value.
BUCK4 Step-Down Converter
for PA (Power Amplifier)
BUCK4 is a 2MHz fixed-frequency PWM step-down
converter, typically used to supply the power amplifier
(PA). The BUCK4 load capability is 1.8A. BUCK4 is only
available on the MAX8982A/MAX8982P.
Overvoltage Protection (OVP)
If the voltage on the IN1_ or IN4 inputs exceeds 5.75V
(typ), the ICs shut down. When the supply voltage
returns to within the valid operating range and EN is
high, the ICs turn on and go through a normal power-up
sequence. All registers are reset to their default power-
on reset (POR) value.
Setting the Output Voltage on BUCK4
The default output voltage is 3.4V. The BUCK4 output
voltage is programmable between 3.0V and 3.75V in
50mV increments through I2C.
Linear Regulators
All linear regulators are designed for low-drop, low noise,
high PSRR, and low quiescent current to minimize power
consumption. If the input voltage is above UVLO thresh-
old and power-on is logic-high, the default linear regula-
tor (LDO3) turns on. The other LDOs are turned on and
off by the baseband processor through the I2C interface
or PWR_REQ control signal. All LDO output voltages are
programmable through the I2C interface within option
voltages.
Power-On Reset (POR)
Power-on reset (POR) for I2C occurs when the ICs turn
off due to UVLO, OVP, or EN = low. This condition puts
the IC into shutdown and then clears all previously pro-
grammed output voltages in the internal registers.
The programmed values in BUCK1DVS1 and
BUCK1DVS2 are also reset to their defaults when
PWR_REQ goes low in normal operation mode.
Table 4. BUCK1 Ramp-Up/Down Slope
Control Settings
DOWN
SLOPE
CONTROL
RASD1[1]
RASD1[0]
SLEW RATE (mV/µs)
0
0
1
1
0
1
0
1
5
V
BUCK1
UP SLOPE
CONTROL
10
12.5 (default)
25
Figure 8. BUCK1 Ramp-Up/Down Slope Control
38
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
POR ON ALL REGISTERS
IN MAX8982A/MAX8982P/
MAX8982X
EN = LOW
OR
EN = HIGH
AND
IN1_ INVALID
IN1_ VALID
THE VALUES IN THE BUCK1DVS1
AND BUCK1DVS2 REGISTERS
ARE RESET TO THEIR DEFAULTS
2
I C ENABLED
PWR _REQ = LOW
WHEN PWR_REQ GOES LOW
Figure 9. POR State Diagram
to four on-pulses can be programmed in this sequence
and the start time for each pulse is programmed indi-
Current Regulators (DR1, DR2, DR3)
The ICs have three current regulators that can handle
up to 24mA. The sink current for each current regulator
is set from 3mA to 24mA in 3mA increments through I2C.
The default set current is 24mA on each channel.
vidually (t –t ). The programmable LED on-time (t )
1
4
ON
for each pulse is the same for each pulse. The flash tim-
ing is shown in Figure 11. The dimming current can be
changed at any time.
If a current other than the programmable options is
required, a series resistor can be added to set a current
from 0mA to 24mA (Figure 10). The resistor forces the
current regulator to operate in dropout. Set the resistor
IRQ Description
The ICs use the IRQ to indicate to the baseband pro-
cessor that their status has changed. The IRQ signal is
asserted (pulls low) whenever an interrupt is triggered.
The baseband controller shall read the interrupt register
to find sources of interrupt. IRQ is cleared (high) as soon
as the read sequence of the last IRQ register that con-
tains an active interrupt starts. If an interrupt is captured
during the read sequence, IRQ becomes active (low)
after minimum 24 cycles of the I2C clock. An interrupt
can be masked to prevent IRQ from being asserted for
the masked event. A mask bit in the IRQM register imple-
ments masking.
value to (V
- V )/I
, where V is the forward volt-
LED F
IN1_
F
age of the LED at the desired current and I
is the
LED
desired LED current. I
must be less than the pro-
LED
grammed current (24mA default).
Each current regulator has an embedded flash timer.
The flash time is programmable through the I2C inter-
face. This feature allows the system designer to generate
a desired pattern on LED.
Embedded Flash Timer
The flash generator is clocked by the internal 32kHz oscil-
lator. It consists of a counter that wraps at a programmable
For UVLO interrupt bit, the bit status is only maintained
as long as V
is higher than 2.0V in any conditions.
BUS
value to provide a configurable sequence period (t ). Up
P
t
P
V
IN1_
DR 1
DR 2
DR 3
3-CHANNEL
CURRENT
REGULATOR
t
t
t
t
ON
ON
ON
ON
t
1
(24mA, DEFAULT)
t
2
t
3
t
4
Figure 10. Adding Series Resistors to Adjust LED Current
Figure 11. Flash Timing Diagram
Maxim Integrated
39
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA ALLOWED
2
Figure 12. I C Bit Transfer
RESET SIGNAL to B/B Chipset
The ICs include one dedicated reset output called
RESET. This is the reset signal for the core and RTB
(real-time block) in baseband. RESET goes high after the
ICs’ power-up sequence is complete. RESET is pulled
low when the ICs are shut down (due to input supply out
of range or EN goes low).
SDA
SCL
I2C Serial Interface
An I2C-compatible, 2-wire serial interface is used for
regulator on/off control, setting output voltages, LED
control, and other functions. See Table 5 for the com-
plete register map.
The I2C serial bus consists of a bidirectional serial-data
line (SDA) and a serial-clock line (SCL). I2C is an open-
drain bus. SDA and SCL require pullup resistors (500I
or greater). Optional 24Iresistors in series with SDA and
SCL help to protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot on bus lines.
START
CONDITION
STOP
CONDITION
Figure 13. START and STOP Conditions
Both SDA and SCL remain high when the bus is not
busy. The master device initiates communication by
issuing a START condition. A START condition is a
high-to-low transition of SDA, while SCL is high. A STOP
condition is a low-to-high transition of the data line while
SCL is high (Figure 13).
Bit Transfer
One data bit is transferred for each SCL clock cycle. The
data on SDA must remain stable during the high portion of
the SCL clock pulse (Figure 12). Changes in SDA while SCL
is high are control signals (START and STOP conditions).
A START condition from the master signals the begin-
ning of a transmission to the ICs. The master terminates
transmission by issuing a not acknowledge followed by a
STOP condition. See the Acknowledge section for more
information. The STOP condition frees the bus. To issue
a series of commands to the slave, the master can issue
START and STOP Conditions
Each transmit sequence is framed by a START (S) condi-
tion and a STOP (P) condition. Each packet is 9 bits long; 8
bits of data followed by the acknowledge bit. The ICs sup-
port data transfer rates with a SCL frequency up to 400kHz.
40
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
REPEATED START (Sr) commands instead of a STOP
Acknowledge
The number of data bytes between the START and STOP
conditions for the transmitter and receiver are unlimited.
Each 8-bit byte is followed by an acknowledge bit. The
acknowledge bit is a high-level signal put on SDA by the
transmitter during which time the master generates an
extra acknowledge-related clock pulse. A slave receiver
that is addressed must generate an acknowledge after
each byte it receives. Also, a master receiver must
generate an acknowledge after each byte it receives
that has been clocked out of the slave transmitter. See
Figure 15.
command to maintain control of the bus. In general, a
REPEATED START command is functionally equivalent
to a regular START command.
When a STOP condition or incorrect address is detected,
the ICs internally disconnect SCL from the serial inter-
face until the next START condition, minimizing digital
noise and feedthrough.
System Configuration
A device on the I2C bus that generates a message is
called a transmitter, and a device that receives the mes-
sage is a receiver. The device that controls the message
is the master, and the devices that are controlled by the
master are called slaves (Figure 14).
The device that acknowledges must pull down the DATA
line during the acknowledge clock pulse, so that the
DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowl-
edge on the last byte that has been clocked out of the
slave. In this case, the transmitter must leave SDA high
to enable the master to generate a STOP condition.
The ICs are slave transmitter/receiver devices, and the
B/B chipset is a master transmitter/receiver. The master
initiates data transfer on the bus and generates SCL to
permit data transfer.
SDA
SCL
MASTER
TRANSMITTER/RECEIVER
SLAVE
TRANSMITTER/RECEIVER
SLAVE RECEIVER
Figure 14. Master/Slave Configuration
SDA OUTPUT
FROM TRANSMITTER
D0
D7
D6
NOT ACKNOWLEDGE
SDA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
8
SCL FROM
MASTER
1
2
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START CONDITION
2
Figure 15. I C Acknowledge
Maxim Integrated
41
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
SDA
t
BUF
t
SU_STA
t
SU_DAT
t
HD_STA
t
LOW
t
SU_STO
t
HD_DAT
t
SCL
HIGH
t
HD_STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 16. I C Timing Diagram
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
7
1
0
1
8
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
A
REGISTER POINTER
A
DATA
A
P
R/W
b) WRITING TO MULTIPLE REGISTERS
NUMBER OF BITS
1
7
1
1
8
1
8
1
8
1
...
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
DATA X
A
DATA X+1
A
R/W
8
1
8
1
NUMBER OF BITS
...
DATA X+n-1
A
DATA X+n
A
P
Figure 17. Writing to the ICs
Slave Address
Write Operations
The ICs act as a slave transmitter/receiver. The slave
address of the ICs is:
Use the following procedure to write to a sequential
block of registers (Figure 17):
10000010 (0x82) for write operations
10000011 (0x83) for read operations
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit (0x82).
The least significant bit is the read/write indicator.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
1
0
0
0
0
0
1
R/W
42
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
4) The master sends the 8-bit register pointer of the first
4) The master sends an 8-bit register pointer of the first
register in the block.
register to write.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
5) The slave acknowledges the register pointer.
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave address followed
by a read bit.
8) The slave asserts an acknowledge by pulling SDA low.
9) The slave sends the 8-bit data (contents of the register).
9) Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
10) The master asserts an acknowledge by pulling
SDA low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
10) The master sends a STOP condition.
Read Operations
Use the following method to read a sequential block of
registers (Figure 18):
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
1) The master sends a start command.
2) The master sends the 7-bit slave address followed
by a write bit (0x83).
12) The master sends a STOP condition.
The register pointer can be omitted from the above pro-
cedure when starting from register 0x00.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
1
7
1
0
1
8
1
1
7
1
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS
A
REGISTER POINTER
A
Sr
SLAVE ADDRESS
1
A
DATA
A
P
R/W
R/W
b) READING MULTIPLE REGISTERS
NUMBER OF BITS
1
7
1
1
8
1
1
7
1
8
1
1
1
...
S
SLAVE ADDRESS
0
A
REGISTER POINTER X
A
Sr
SLAVE ADDRESS
A
DATA X
A
R/W
...
R/W
1
8
1
8
8
1
1
NUMBER OF BITS
...
A
DATA X+1
DATA X+n-1
A
DATA X+n
A
P
Figure 18. Reading from the ICs
Maxim Integrated
43
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 5. Register Map
ADDRESS POR
(HEX) (HEX)
BIT 7
(MSB)
BIT 0
(LSB)
R/W
NAME
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
02
03
13
14
18
19
1A
1B
1C
1D
20
21
22
23
24
25
28
29
2A
2B
2C
2D
3D
3F
40
45
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
—
R
CHIPID
IRQM
Reserved Reserved
PASS[1:0]
Reserved Reserved Reserved VOPTION
00 R/W
00 R/W
Reserved Reserved Reserved Reserved Reserved Reserved UVLOFM HIGHTMPM
Reserved Reserved Reserved Reserved Reserved Reserved UVLOF HIGHTMP
Reserved Reserved Reserved Reserved Reserved Reserved UVLOF HIGHTMP
IRQ
N/A
R
STATUS
LED1FT1
LED1FT2
LED1FT3
LED1FT4
LED1FT5
LED1FT6
LED2FT1
LED2FT2
LED2FT3
LED2FT4
LED2FT5
LED2FT6
LED3FT1
LED3FT2
LED3FT3
LED3FT4
LED3FT5
LED3FT6
BUCK1
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
00 R/W
47 R/W
Reserved Reserved Reserved FLASHEN
LD1TON[3:0]
LD2TON[3:0]
LD3TON[3:0]
Reserved
LD1T1[6:0]
LD1T2[6:0]
LD1T3[6:0]
LD1T4[6:0]
LD1TP[6:0]
Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved FLASHEN
Reserved
LD2T1[6:0]
LD2T2[6:0]
LD2T3[6:0]
LD2T4[6:0]
LD2TP[6:0]
Reserved
Reserved
Reserved
Reserved
Reserved Reserved Reserved FLASHEN
Reserved
Reserved
Reserved
Reserved
Reserved
LD3T1[6:0]
LD4T2[6:0]
LD4T3[6:0]
LD4T4[6:0]
LD4TP[6:0]
Reserved Reserved Reserved Reserved Reserved Reserved
BUCK1[1:0]
0C R/W BUCK1DVS1 Reserved Reserved Reserved
0C R/W BUCK1DVS2 Reserved Reserved Reserved
SD1[4:0]
SD1[4:0]
45 R/W
03 R/W
04 R/W
03 R/W
04 R/W
01 R/W
07 R/W
03 R/W
00 R/W
00 R/W
07 R/W
01 R/W
07 R/W
00 R/W
0B R/W
BUCK2
LDO1
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved
BUCK2[1:0]
LDO1[1:0]
LDO1V
LDO2
Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L2[4:0]
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L3[4:0]
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L4[4:0]
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L5[4:0]
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L6[4:0]
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L7[4:0]
L1[4:0]
LDO2[1:0]
LDO3[1:0]
LDO4[1:0]
LDO5[1:0]
LDO6[1:0]
LDO7[1:0]
LDO2V
LDO3
LDO3V
LDO4
LDO4V
LDO5
LDO5V
LDO6
LDO6V
VSIM
VSIMV
44
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 5. Register Map (continued)
ADDRESS POR
(HEX) (HEX)
BIT 7
(MSB)
BIT 0
(LSB)
R/W
NAME
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
5A
5B
5C
5D
6B
70
72
73
75
76
77
78
79
7A
01 R/W
06 R/W
01 R/W
00 R/W
00 R/W
03 R/W
06 R/W
08 R/W
LDO8
LDO8V
LDO9
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L8[4:0]
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved L9[4:0]
Reserved Reserved Reserved Reserved Reserved LED3EN LED2EN LED1EN
LDO8[1:0]
LDO9[1:0]
LDO9V
LED_EN
ON/OFF
BUCK3
BUCK4
Reserved Reserved Reserved
BUCK4[1:0]
BUCK3[1:0]
SD3[3:0]
32KCLK
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
SD4[3:0]
3F R/W CURRENTREG1 Reserved Reserved
07 R/W CURRENTREG2 Reserved Reserved Reserved Reserved Reserved
02 R/W RAMP Reserved Reserved Reserved Reserved Reserved Reserved
DR1[2:0]
DR2[2:0]
DR3[2:0]
RASD1[1:0]
04 R/W BUCK1-4ADIS Reserved Reserved Reserved Reserved SD1ADIS SD2ADIS SD3ADIS SD4ADIS
00 R/W LDO1-8ADIS LDO1ADIS LDO2ADIS LDO3ADIS LDO4ADIS LDO5ADIS LDO6ADIS LDO7ADIS LDO8ADIS
00 R/W LDO9ADIS
Reserved Reserved Reserved Reserved Reserved Reserved Reserved LDO9ADIS
Table 6. CHIPID Register
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
02
—
R
Reserved Reserved
PASS[1:0]
Reserved Reserved Reserved VOPTION
NAME
POR
DESCRIPTION
0: 5V input option (MAX8982A)
1: 3.3V input option (MAX8982X/MAX8982P)
VOPTION
PASS[1:0]
—
—
Chip revision version
Table 7. IRQM Register (Interrupt Mask)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HIGH
TMPM
03
00
R/W
Reserved Reserved Reserved Reserved Reserved Reserved UVLOFM
NAME
POR
DESCRIPTION
HIGH
TMPM
0: Interrupt enabled.
1: Mask HIGHTMP interrupt.
0
0
0: Interrupt enabled.
1: Mask UVLOF interrupt.
UVLOFM
Note: The IRQM register is effective only as long as IN1A and IN1B are higher than the falling UVLO threshold. If the IN1A and
IN1B are below the falling UVLO threshold, this IRQM register resets to the POR value.
Maxim Integrated
45
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 8. IRQ Register
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HIGH
TMP
13
00
R/W
Reserved Reserved Reserved Reserved Reserved Reserved
UVLOF
NAME
POR
DESCRIPTION
HIGH
TMP
0: No high temperature event detected.
1: Temperature sensor detects +125NC.
0
0
0: No UVLO event detected.
1: UVLO falling is detected.
UVLOF
Note: The IRQ register is effective only as long as IN1A and IN1B are higher than 2.0V. If the IN1A and IN1B are below 2.0V,
these registers reset to the POR value.
Table 9. STATUS Register
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HIGH
TMP
14
N/A
R
Reserved Reserved Reserved Reserved Reserved Reserved
UVLOF
NAME
POR
DESCRIPTION
0: T < +125NC
J
HIGHTMP
—
—
1: T > +125NC
J
0: Falling UVLO threshold is not detected.
1: Falling UVLO threshold is detected.
UVLOF
Table 10. LED1FT1 Register (LED1 (DR1) Flash Timer On/Off and TON Adjust)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
18
00
R/W Reserved Reserved Reserved FLASHEN
LD1TON[3:0]
NAME
POR
DESCRIPTION
1: Flasher is enabled.
0: Flasher is disabled.
FLASHEN
0
BIT
t
ON
(ms)
3
0
2
0
1
0
0
0
25
0
.
.
0
.
.
0
.
.
1
.
.
50
LD1TON[3:0]
0000
.
.
1
1
1
1
400
From 25ms to 400ms in 25ms increments.
46
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 11. LED1FT2 Register (LED1 (DR1) Flash Timer t Setting)
1
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
19
00
R/W
Reserved
LD1T1[6:0]
NAME
POR
DESCRIPTION
BIT
3
t TIME
1
(ms)
6
0
0
5
0
0
4
0
0
2
0
0
1
0
0
0
0
1
0
0
0
25
LD1T1[0:6]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 12. LED1FT3 Register (LED1 (DR1) Flash Timer t Setting)
2
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1A
00
R/W Reserved
POR
LD1T2[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
2
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
0
0
0
0
0
25
50
0
LD1T2[0:6]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 13. LED1FT4 Register (LED1 (DR1) Flash Timer t Setting)
3
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1B
00
R/W Reserved
POR
LD1T3[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
3
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
0
25
50
LD1T3[6:0]
0000000
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Maxim Integrated
47
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 14. LED1FT5 Register (LED1 (DR1) Flash Timer t Setting)
4
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1C
00
R/W Reserved
POR
LD1T4[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
4
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
0
25
50
LD1T4[6:0]
0000000
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 15. LED1FT6 Register (LED1 (DR1) Flash Timer t Setting)
P
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1D
00
R/W Reserved
POR
LD1TP[6:0]
NAME
DESCRIPTION
BIT
3
t
TIME
(ms)
P
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
0
25
50
0
LD1TP[6:0]
0000000
0
.
.
0
.
.
0
.
.
0
.
.
0
.
.
1
.
.
1
.
.
75
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 16. LED2FT1 Register (LED2 (DR2) Flash Timer On/Off and t
Adjust)
ON
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
20
00
R/W Reserved Reserved Reserved
POR
Flash EN
LD2TON[3:0]
NAME
DESCRIPTION
1: Flasher is enabled.
0: Flasher is disabled.
BIT
t
ON
TIME (ms)
3
0
0
2
0
0
1
0
0
0
0
1
25
50
LD2TON[3:0]
0000
.
.
.
.
.
.
.
.
.
.
1
1
1
1
400
From 25ms to 400ms in 25ms increments.
48
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 17. LED2FT2 Register (LED2 (DR2) Flash Timer t Setting)
1
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
21
00
R/W Reserved
LD2T1[6:0]
NAME
POR
DESCRIPTION
BIT
3
t TIME
1
(ms)
6
0
5
0
4
0
2
0
1
0
0
0
0
0
0
.
.
0
.
.
0
.
.
0
.
.
0
.
.
0
.
.
1
.
.
25
.
.
LD2T1[6:0]
0000000
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 18. LED2FT3 Register (LED2 (DR2) Flash Timer t Setting)
2
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
22
00
R/W Reserved
POR
LD2T2[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
2
(ms)
6
0
5
0
4
0
2
0
1
0
0
0
0
0
0
.
.
0
.
.
0
.
.
0
.
.
0
.
.
0
.
.
1
.
.
25
.
.
LD2T2[6:0]
0000000
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 19. LED2FT4 Register (LED2 (DR2) Flash Timer t Setting)
3
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
23
00
R/W Reserved
POR
LD2T3[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
3
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
0
25
50
0
LD2T3[6:0]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Maxim Integrated
49
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 20. LED2FT5 Register (LED2 (DR2) Flash Timer t Setting)
4
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
24
00
R/W Reserved
POR
LD2T4[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
4
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
25
50
0
0
LD2T4[6:0]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 21. LED2FT6 Register (LED2 (DR2) Flash Timer t Setting)
P
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
25
00
R/W Reserved
POR
LD2TP[6:0]
NAME
DESCRIPTION
BIT
t
P
TIME
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
25
50
LD2TP[6:0]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 22. LED3FT1 Register (LED3 (DR3) Flash Timer On/Off and t
Adjust)
ON
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
28
00
R/W Reserved Reserved Reserved FLASHEN
LD3TON[3:0]
NAME
POR
DESCRIPTION
1: Flasher is enabled.
0: Flasher is disabled.
FLASHEN
0
BIT
t
TIME (ms)
ON
3
0
2
0
1
0
0
0
25
0
.
.
0
.
.
0
.
.
1
.
.
50
LD3TON[3:0]
0000
.
.
1
1
1
1
400
From 25ms to 400ms in 25ms increments.
50
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 23. LED3FT2 Register (LED3 (DR3) Flash Timer t Setting
1
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
29
00
R/W Reserved
POR
LD3T1[6:0]
NAME
DESCRIPTION
BIT
t TIME
1
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
25
50
LD3T1[6:0]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 24. LED3FT3 Register (LED3 (DR3) Flash Timer t Setting)
2
ADRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
2A
00
R/W Reserved
POR
LD3T2[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
2
(ms)
6
0
0
5
0
0
4
0
0
2
0
0
1
0
0
0
0
1
0
0
0
25
LD3T2[6:0]
0000000
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 25. LED3FT4 Register (LED3 (DR3) Flash Timer t Setting)
3
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
2B
00
R/W Reserved
POR
LD3T3[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
3
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
0
25
50
LD3T3[6:0]
0000000
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Maxim Integrated
51
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 26. LED3FT5 Register (LED3 (DR3) Flash Timer t Setting)
4
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
2C
00
R/W Reserved
POR
LD3T4[6:0]
NAME
DESCRIPTION
BIT
3
t TIME
4
(ms)
6
0
0
0
5
0
0
0
4
0
0
0
2
0
0
0
1
0
0
1
0
0
1
0
0
0
0
25
50
LD3T4[6:0]
0000000
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 27. LED3FT6 Register (LED3 (DR3) Flash Timer t Setting)
P
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
2D
00
R/W Reserved
POR
LD3TP[6:0]
NAME
DESCRIPTION
BIT
3
t
TIME
(ms)
P
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
2
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
25
50
75
0
LD3TP[6:0]
0000000
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
3175
From 0ms to 3175ms in 25ms increments.
Table 28. BUCK1 Register (On/Off Control for BUCK1)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3D
47
R/W Reserved Reserved Reserved Reserved Reserved Reserved
BUCK1[1:0]
BITS 7:2
Reserved, write 010001 to these bits.
BIT 1
BIT 0
DESCRIPTION
2
0
0
1
1
0
1
0
1
BUCK1 off (in I C on mode).
2
BUCK1 on (in I C on mode).
BUCK1 on (in PWR_REQ on mode) (Group D).
BUCK1 on (in PWR_REQ on mode) (Group D).
52
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 29. BUCK1DVS1 Register (Output Voltage Setting for BUCK1 (DVS1 = Low))
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
3F
0C
R/W Reserved Reserved Reserved
SD1[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
V
(V)
PROG
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
X
X
X
X = Don’t care.
Maxim Integrated
53
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 30. BUCK1DVS2 Register (Output Voltage Setting for BUCK1 (DVS1 = High))
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
40
0C
R/W Reserved Reserved Reserved
SD1[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
V
PROG
(V)
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
X
X
X
X = Don’t care.
54
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 31. BUCK2 Register (On/Off Control for BUCK2)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
45
45
R/W Reserved Reserved Reserved Reserved Reserved Reserved
BUCK2[1:0]
BITS 7:2
Reserved, write 010001 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
1
0
1
BUCK2 off (in I2C on mode).
BUCK2 on (in I2C on mode).
BUCK2 on (in PWR_REQ on mode) (Group A).
BUCK2 on (in PWR_REQ on mode) (Group A).
Table 32. LDO1 Register (On/Off Control for LDO1)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
4C
03
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO1[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
1
0
1
LDO1 off (in I2C on mode).
LDO1 on (in I2C on mode).
LDO1 on (in PWR_REQ on mode) (Group B).
LDO1 on (in PWR_REQ on mode) (Group B).
Table 33. LDO1V Register (Output Voltage Setting for OUT1)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
4D
04
R/W Reserved Reserved Reserved
L1[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
PROG
(V)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
2.65
2.65
2.65
2.65
2.70
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.00
3.00
X = Don’t care.
Maxim Integrated
55
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 34. LDO2 Register (ON/OFF Control for LDO2)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
4E
03
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO2[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
1
0
1
LDO2 off (in I2C on mode).
LDO2 on (in I2C on mode).
LDO2 on (in PWR_REQ on mode) (Group A).
LDO2 on (in PWR_REQ on mode) (Group A).
Table 35. LDO2V Register (Output Voltage Setting for OUT2)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
4F
04
R/W Reserved Reserved Reserved
L2[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
(V)
PROG
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1.50
1.50
1.50
1.50
1.80
2.70
2.70
2.70
2.70
2.70
2.70
1.70
1.70
1.70
X = Don’t care.
Table 36. LDO3 Register (On/Off Control for LDO3)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
50
01
R/W
Reserved Reserved Reserved Reserved Reserved Reserved
Reserved, write 000000 to these bits.
DESCRIPTION
LDO3[1:0]
BITS 7:2
BIT 1
BIT 0
0
0
1
1
0
1
0
1
LDO3 off (in I2C on mode).
LDO3 on (in I2C on mode).
LDO3 on (in PWR_REQ on mode) (Group B).
LDO3 on (in PWR_REQ on mode) (Group B).
56
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 37. LDO3V Register (Output Voltage Setting for OUT3)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
51
07
R/W Reserved Reserved Reserved
L3[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
PROG
(V)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
2.65
2.65
2.65
2.65
2.70
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.00
3.00
X = Don’t care.
Table 38. LDO4 Register (On/Off Control for LDO4)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
52
03
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO4[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
1
0
1
LDO4 off (in I2C on mode).
LDO4 on (in I2C on mode).
LDO4 on (in PWR_REQ on mode) (Group D).
LDO4 on (in PWR_REQ on mode) (Group D).
Maxim Integrated
57
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 39. LDO4V Register (Output Voltage Setting for OUT4)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
53
00
R/W Reserved Reserved Reserved
L4[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
(V)
PROG
0.90
0
0
0
0
0
X
1
X
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
X
X
0
1.00
1.20
1.10
0.80
0.80
0.80
0
0
X
X
1
X = Don’t care.
Table 40. LDO5 Register (On/Off Control for LDO5)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
54
00
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO5[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
1
0
1
LDO5 off (in I2C on mode).
LDO5 on (in I2C on mode).
LDO5 on (in PWR_REQ on mode) (Group C).
LDO5 on (in PWR_REQ on mode) (Group C).
58
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 41. LDO5V Register (Output Voltage Setting for OUT5)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
55
07
R/W Reserved Reserved Reserved
L5[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
PROG
(V)
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
3.20
3.20
3.20
3.20
3.20
2.80
2.80
3.00
3.00
2.90
2.90
3.00
3.00
3.00
X = Don’t care.
Table 42. LDO6 Register (On/Off Control for LDO6)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
56
01
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO6[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
LDO6 on (in PWR_REQ on mode) (Group C).
0
0
1
1
0
1
0
1
LDO6 on (in PWR_REQ on mode) (Group C).
LDO6 off (in I2C off mode).
LDO6 on (in I2C on mode).
Note: The enable mapping for LDO6 is different from all other LDOs.
Maxim Integrated
59
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 43. LDO6V Register (Output Voltage Setting for OUT6)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
57
07
R/W Reserved Reserved Reserved
L6[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
PROG
(V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
2.65
2.65
2.65
2.65
2.65
2.70
2.70
2.70
2.75
2.80
2.85
2.90
2.95
3.00
3.00
3.00
X = Don’t care.
Table 44. VSIM Register (On/Off Control for VSIM (LDO7))
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
58
00
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO7[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
LDO7 off (in I2C off mode).
LDO7 on (in I2C on mode).
1
0
1
LDO7 on (in PWR_REQ on mode) (Group C).
LDO7 on (in PWR_REQ on mode) (Group C).
60
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 45. VSIMV Register (Output Voltage Setting for VSIM)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
59
0B
R/W Reserved Reserved Reserved
L7[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
(V)
PROG
0
0
0
0
0
0
0
0
0
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
X
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1.80
0
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
3.00
3.00
3.00
0
0
0
0
0
0
0
0
0
0
0
1
X = Don’t care.
Table 46. LDO8 Register (On/Off Control for LDO8)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
5A
01
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO8[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
LDO8 off (in I2C off mode).
LDO8 on (in I2C on mode).
1
0
1
LDO8 on (in PWR_REQ on mode) (Group C).
LDO8 on (in PWR_REQ on mode) (Group C).
Note: This register is not used by the MAX8982X.
Maxim Integrated
61
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 47. LDO8V Register (Output Voltage Setting for OUT8)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
5B
06
R/W Reserved Reserved Reserved
L8[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0
V
(V)
PROG
3.00
0
0
0
0
1
3.00
3.00
3.00
3.00
3.00
3.00
3.10
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.20
3.30
3.30
3.30
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
X
X
X
1
0
1
X
X
1
1
X
Note: This register is not used by the MAX8982X.
X = Don’t care.
Table 48. LDO9 Register (On/Off Control for LDO9)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
5C
01
R/W Reserved Reserved Reserved Reserved Reserved Reserved
LDO9[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
BIT 1
BIT 0
DESCRIPTION
0
0
1
1
0
1
0
1
LDO9 off (in I2C off mode).
LDO9 on (in I2C on mode).
LDO9 on (in PWR_REQ on mode) (Group D).
LDO9 on (in PWR_REQ on mode) (Group D).
62
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 49. LDO9V Register (Output Voltage Setting for OUT9)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
5D
00
R/W Reserved Reserved Reserved
L9[4:0]
BITS 7:5
Reserved, write 000 to these bits.
DESCRIPTION
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
V
(V)
PROG
0.90
0
0
0
0
X
X
1
0
0
0
0
X
1
X
0
0
0
0
1
X
X
0
0
1
1
X
X
X
0
1
0
1
X
X
X
1.00
1.20
1.10
0.80
0.80
0.80
X = Don’t care.
Table 50. LED_EN Register (On/Off Control for 3 Current Regulators)
ADDRESS
(HEX)
POR
(HEX)
R/W
R/W Reserved Reserved Reserved Reserved Reserved
POR DESCRIPTION
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LED3
EN
LED2
EN
LED1
EN
6B
00
NAME
LED3EN
1: Turn on LED3.
0
0
0
0: Turn off LED3.
1: Turn on LED2.
LED2EN
LED1EN
0: Turn off LED2.
1: Turn on LED1.
0: Turn off LED1.
Maxim Integrated
63
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 51. On/Off Register (On/Off Control for BUCK3, BUCK4, and the Internal 32kHz Clock)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
70
03
R/W Reserved Reserved Reserved
BUCK4[1:0]
BUCK3[1:0]
32KCLK
BITS 7:5
NAME
BUCK4[1] BUCK4[0]
Reserved, write 000 to these bits.
DESCRIPTION
0
0
BUCK4 off (in I2C on mode).
0
1
BUCK4 on (in I2C on mode).
1
0
BUCK4 on (in PWR_REQ on mode) (Group B).
BUCK4 on (in PWR_REQ on mode) (Group B).
1
1
BUCK3[1]
BUCK3[0]
DESCRIPTION
0
0
1
BUCK3 OFF (in I2C on mode).
BUCK3 ON (in I2C on mode).
0
1
1
0
BUCK3 ON (in PWR_REQ on mode).
BUCK3 ON (in PWR_REQ on mode).
1
NAME
POR
DESCRIPTION
1: Turn on 32kHz.
0: Turn off 32kHz.
32KCLK
1
Note: The BUCK3 and BUCK4 bits are not used by the MAX8982X.
Table 52. BUCK3 Register (Output Voltage Setting for BUCK3)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
72
06
R/W Reserved Reserved Reserved Reserved
Reserved, write 0000 to these bits.
DESCRIPTION
SD3[3:0]
BITS 7:4
BIT 3
BIT 2
BIT 1
BIT 0
V
PROG
(V)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.90
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
Note: This register is not used by the MAX8982X.
64
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 53. BUCK4 Register (Output Voltage Setting for BUCK4)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
73
08
R/W Reserved Reserved Reserved Reserved
Reserved, write 0000 to these bits.
DESCRIPTION
SD4[3:0]
BITS 7:4
BIT 3
BIT 2
BIT 1
BIT 0
V
PROG
(V)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.40
3.45
3.50
3.55
3.60
3.65
3.70
3.75
Note: This register is not used by the MAX8982X.
Maxim Integrated
65
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 54. CURRENTREG1 Register (Current Setting for Current Regulators DR1 and DR2)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
75
3F
R/W Reserved Reserved
Reserved, write 00 to these bits.
DESCRIPTION
DR1[2:0]
DR2[2:0]
BITS 7:6
DR1[2]
DR1[1]
DR1[0]
I
(mA)
DR1 PROG
0
0
0
3
0
0
1
6
0
1
0
9
0
1
1
12
15
18
21
24
1
0
0
1
0
1
1
1
0
1
1
1
DR2[2]
DR2[1]
DR2[0]
I
(mA)
DR2 PROG
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
6
9
12
15
18
21
24
Table 55. CURRENTREG2 Register (Current Setting for Current Regulator DR3)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
76
07
R/W Reserved Reserved Reserved Reserved Reserved
Reserved, write 00000 to these bits.
DESCRIPTION
DR3[2:0]
BITS 7:3
DR3[2]
DR3[1]
DR3[0]
I
(mA)
DR3 PROG
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
6
9
12
15
18
21
24
66
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 56. RAMP Register (Slope Setting for BUCK1)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
77
02
R/W Reserved Reserved
Reserved Reserved Reserved Reserved
RASD1[1:0]
BITS 7:2
Reserved, write 000000 to these bits.
DESCRIPTION
BIT 1
BIT 0
SLEW RATE (mV/µs)
0
0
1
1
0
1
0
1
5
10
12.5
25
Table 57. BUCK1-4ADIS Register (Active Discharge Settings for BUCK1–BUCK4)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SD1
ADIS
SD2
ADIS
SD3
ADIS
SD4
ADIS
78
04
R/W Reserved Reserved Reserved Reserved
BITS 7:4
Reserved, write 0000 to these bits.
DESCRIPTION
1: Enable BUCK1 active discharge.
0: Disable BUCK1 active discharge.
SD1ADIS
SD2ADIS
SD3ADIS
SD4ADIS
0
1
0
0
1: Enable BUCK2 active discharge.
0: Disable BUCK2 active discharge.
1: Enable BUCK3 active discharge.
0: Disable BUCK3 active discharge.
1: Enable BUCK4 active discharge.
0: Disable BUCK4 active discharge.
Note: The SD3ADIS and SD4ADIS bits are not used by the MAX8982X.
Maxim Integrated
67
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 58. LDO1-8ADIS Register (Active Discharge Settings for LDO1–LDO8)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LDO1
ADIS
LDO2
ADIS
LDO3
ADIS
LDO4
ADIS
LDO5
ADIS
LDO6
ADIS
LDO7
ADIS
LDO8
ADIS
79
00
R/W
DESCRIPTION
1: Enable LDO1 active discharge.
0: Disable LDO1 active discharge.
LDO1ADIS
LDO2ADIS
LDO3ADIS
LDO4ADIS
LDO5ADIS
LDO6ADIS
LDO7ADIS
LDO8ADIS
0
0
0
0
0
0
0
0
1: Enable LDO2 active discharge.
0: Disable LDO2 active discharge.
1: Enable LDO3 active discharge.
0: Disable LDO3 active discharge.
1: Enable LDO4 active discharge.
0: Disable LDO4 active discharge.
1: Enable LDO5 active discharge.
0: Disable LDO5 active discharge.
1: Enable LDO6 active discharge.
0: Disable LDO6 active discharge.
1: Enable LDO7 active discharge.
0: Disable LDO7 active discharge.
1: Enable LDO8 active discharge.
0: Disable LDO8 active discharge.
Note: The LDO8ADIS bit is not used by the MAX8982X.
Table 59. LDO9ADIS Register (Active Discharge Setting for LDO9)
ADDRESS
(HEX)
POR
(HEX)
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LDO9
ADIS
7A
00
R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved
BITS 7:1
Reserved, write 0000000 to these bits.
DESCRIPTION
1: Enable LDO9 active discharge.
0: Disable LDO9 active discharge.
LDO9ADIS
0
68
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
For optimum voltage positioning load transients, choose
Applications Information
an inductor with DC series resistance in the 30mW
to 100mW range. For higher efficiency at heavy load
(above 200mA) or minimal load regulation (but some
transient overshoot), the resistance should be kept
below 100mW. For light load applications up to 200mA,
a higher resistance is acceptable with very little impact
on performance.
Inductor Selection
The step-down converters operate with inductors of 1FH
to 4.7FH. Low inductance values are physically smaller,
but require faster switching, which results in some effi-
ciency loss. The inductor’s DC current rating only needs
to match the maximum load current of the application
plus 100mA because the step-down converters feature
zero current overshoot during startup and load transients.
Recommended inductors are listed in Table 60.
Table 60. Recommended Inductors
CURRENT
RATING (mA)
DT = +40NC RISE
INDUCTANCE
DC RESISTANCE
DIMENSIONS
L x W x H (mm)
MANUFACTURER
SERIES
(FH)
(I typ)
1.0
1.5
2.2
3.3
1.5
2.2
3.3
4.7
1.5
2.0
3.3
4.7
2.2
2.2
1
0.06
0.08
0.09
0.10
0.06
1550
1400
1350
1300
2000
1600
1300
1100
2600
2300
1700
1500
2550
2200
2600
1800
1800
1700
1900
1500
1300
1300
1500
1300
1200
1100
1900
MDT2520-CR
2.5 x 2.0 x 1.0
3.0 x 2.8 x 1.0
3.0 x 2.8 x 1.2
0.085
0.130
0.180
0.050
0.067
0.100
0.130
0.040
0.039
0.050
0.100
0.100
0.115
0.090
0.140
0.180
0.200
0.120
0.190
0.230
0.270
0.1
DE2810C
Flat Wire
TOKO
DE2812C
Flat Wire
DEM3518C
DEM2818C*
3.9 x 3.7 x 1.8
3.0 x 3.0 x 1.8
2.2
3.3
4.7
1
KSLI-252010AG
KSLI-201610AG
2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.0
2.2
3.3
4.7
1
Hitachi-Metals
2.2
3.3
4.7
2.2
KSLI-201210AG
2.0 x 1.2 x 1.0
2.5 x 2.0 x 1.2
KSLI-252012AG-2R2**
Maxim Integrated
69
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Table 60. Recommended Inductors (continued)
CURRENT
RATING (mA)
DT = +40NC RISE
INDUCTANCE
DC RESISTANCE
DIMENSIONS
L x W x H (mm)
MANUFACTURER
SERIES
(FH)
(I typ)
1.5
2.2
3.3
4.7
1.5
2.2
3.3
4.7
1.0
2.2
3.3
4.7
1.0
2.2
3.3
4.7
1.0
1.5
2.2
1.0
2.2
3.3
4.7
1.0
1.0
2.2
3.3
4.7
2.2
1.0
2.2
4.7
1.0
2.2
3.3
4.7
1.0
2.2
3.3
4.7
0.070
0.080
0.100
0.110
0.110
0.110
0.130
0.160
0.090
0.230
0.190
0.230
0.055
0.80
0.100
0.110
0.190
0.260
0.340
0.085
0.110
0.120
0.140
0.030
0.080
0.090
0.120
0.150
0.090
0.080
0.110
0.110
0.060
0.080
0.100
0.110
0.130
0.200
0.250
0.300
1500
1300
1200
1100
1100
1100
1000
900
MIPF2520D
2.5 x 2.0 x 1.0
2.0 x 1.6 x 1.0
2.0 x 1.2 x 1.0
FDK
MIPF2016D***
MIPF2012D
1100
700
800
700
1500
1300
1200
1100
800
LQM2HP_G0
LQM21P
2.5 x 2.0 x 1.0
700
2.0 x 1.25 x 0.50
Murata
600
1400
1200
1200
1100
2100
1400
1300
1200
1100
1000
1500
1200
1000
1500
1300
1200
1100
1050
810
LQM2MPN***
NR3015T1R0N***
CKP2520
2.0 x 1.6 x 1.0
3.0 x 3.0 x 1.5
2.5 x 2.0 x 1.0
Taiyo Yuden
MLP2520S2R2M
MLP2520S_S
2.5 x 2.0 x 1.0
2.5 x 2.0 x 1.2
TDK
CIG22L_
CIG21W_
2.5 x 2.0 x 1.0
2.0 x 1.25 x 1.0
Samsung Electro-
Mechanics
730
650
*Recommended for BUCK4.
**Recommended for BUCK1.
***Recommended for BUCK2 and BUCK3.
70
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Output Capacitor Selection
The output capacitor, C , is required to keep the
PCB Layout Guidelines
Due to fast switching waveforms and high current paths,
careful PCB layout is required to achieve optimal perfor-
mance. Minimize trace lengths between the IC and the
inductor, the input capacitor, and the output capacitor
for each step-down converter. Keep these traces short,
direct, and wide. Route noise sensitive traces away from
the switching nodes (LX_).
OUT
output voltage ripple small and to ensure regulation loop
stability. C must have low impedance at the switch-
OUT
ing frequency. Ceramic capacitors with X5R or X7R tem-
perature characteristics are highly recommended due to
their small size, low ESR, and small temperature coef-
ficients. Due to the unique feedback network, the output
capacitance can be very low. Recommended capacitor
values are shown in Figures 1 and 2.
Chip Information
Input Capacitor Selection
The input capacitor, C
or C , reduces the current
PROCESS: BiCMOS
IN1_
IN_
peaks drawn from the input power source and reduces
switching noise in the IC. The impedance of C at the
IN2
switching frequency should be kept very low. Ceramic
capacitors with X5R or X7R temperature characteristics
are highly recommended due to their small size, low
ESR, and small temperature coefficients. Recommended
capacitor values are shown in Figures 1 and 2.
Maxim Integrated
71
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0440
LAND PATTERN NO.
42 WLP
W423D3+1
Refer to Application Note 1891
72
Maxim Integrated
MAX8982A/MAX8982P/MAX8982X
Power-Management ICs for
ICERA E400 Platform
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
12/10
1/11
0
1
2
Initial release
—
72
Added 42 WLP package diagram
4/11
Added MAX8982P to data sheet and removed references to E450
1–72
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
73
©
2011 Maxim Integrated
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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