MAX9111_V01 [MAXIM]
Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23;
| 型号： | MAX9111_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 |
| 文件： | 总12页 (文件大小：1656K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
General Description
Features
The MAX9111/MAX9113 single/dual low-voltage differ-
ential signaling (LVDS) receivers are designed for high-
speed applications requiring minimum power consump-
tion, space, and noise. Both devices support switching
rates exceeding 500Mbps while operating from a single
+3.3V supply, and feature ultra-low 300ps (max) pulse
skew required for high-resolution imaging applications
such as laser printers and digital copiers.
● Low 300ps (max) Pulse Skew for High-Resolution
Imaging and High-Speed Interconnect
● Space-Saving 8-Pin SOT23 and SO Packages
● Pin-Compatible Upgrades to DS90LV018A and
DS90LV028A (SO Packages Only)
● Guaranteed 500Mbps Data Rate
● Low 29mW Power Dissipation at 3.3V
● Conform to EIA/TIA-644 Standard
● Single +3.3V Supply
The MAX9111 is a single LVDS receiver, and the MAX9113
is a dual LVDS receiver.
● Flow-Through Pinout Simplifies PCB Layout
Both devices conform to the EIA/TIA-644 LVDS standard
and convert LVDS to LVTTL/CMOS-compatible outputs. A
fail-safe feature sets the outputs high when the inputs are
undriven and open, terminated, or shorted. The MAX9111/
MAX9113 are available in space-saving 8-pin SOT23 and
SO packages. Refer to the MAX9110/MAX9112 data
sheet for single/dual LVDS line drivers.
●
Fail-Safe Circuit Sets Output High for Undriven Inputs
● High-Impedance LVDS Inputs when Powered Off
● AEC-Q100 Qualified, Refer to Ordering Information
for the Specific /V Versions
Typical Operating Circuit appears at end of data sheet.
Applications
● Laser Printers
● Digital Copiers
● Cellular Phone Base
Stations
● Telecom Switching
Equipment
● Network Switches/
Routers
● LCD Displays
● Backplane Interconnect
● Clock Distribution
● Automotive
19-1803; Rev 7; 6/19
MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Absolute Maximum Ratings
V
to GND..............................................................-0.3V to +4V
8-Pin SO (derate 5.88mW°C above +70°C).................471mW
8-Pin TDFN (derate 6.20mW°C above +70°C) ...........496mW
Operating Temperature Ranges
MAX911_E.......................................................-40°C to +85°C
MAX911_A .....................................................-40°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
IN_ _ to GND .........................................................-0.3V to +3.9V
OUT_ _ to GND..........................................-0.3V to (V
ESD Protection All Pins
+ 0.3V)
CC
(Human Body Model, IN_+, IN_-)...................................±11kV
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 5.10mW/°C above +70°C) ...408.60mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
SOT23-8
PACKAGE CODE
K8+1
Outline Number
21-0078
90-0176
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
195.80°C/W
70°C/W
JA
Junction to Case (θ
)
JC
SO-8
PACKAGE CODE
S8-2/S8+2
Outline Number
21-0041
90-0096
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θ
)
170°C/W
40°C/W
JA
Junction to Case (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
136°C/W
38°C/W
JA
Junction to Case (θ
)
JC
TDFN-8
PACKAGE CODE
T822CY+2
Outline Number
21-100341
90-100117
Land Pattern Number
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θ
)
162°C/W
20°C/W
JA
Junction to Case (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Electrical Characteristics
CC
(V
= +3.0V to +3.6V, magnitude of input voltage, |V | = +0.1V to +1.0V, V
= |V |/2 to (2.4V - (|V |/2)), T = T
to T
MAX
.
ID
CM
ID
ID
A
MIN
Typical values are at V
= +3.3V and T = +25°C, unless otherwise noted.) (Notes 1, 2)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Input High Threshold
(Note 3)
V
V
V
= 0.05V, 1.2V, 2.75V at 3.3V
100
mV
TH
CM
Differential Input Low Threshold
(Note 3)
V
= 0.05V, 1.2V, 2.75V at 3.3V
-100
5
mV
TL
CM
V
V
= 0.2V or 2.2V, V = ±0.4V,
ID
= 0 or 3.6V
CM
CC
Differential Input Resistance
R
18
kΩ
DIFF
V
= +200mV
2.7
2.7
ID
Inputs shorted, undriven
Output High Voltage (OUT_)
V
I
I
= -4mA
V
OH
OH
OL
100Ω parallel
termination, undriven
2.7
Output Low Voltage (OUT_)
Output Short-Circuit Current
V
= 4mA, V = -200mV
0.4
-100
-120
6
OL
ID
V
= +200mV, V
_ = 0
ID
OUT
I
mA
mA
OS
MAX9113ATA/VY+
MAX9111
4.2
8.7
8.7
No-Load Supply Current
I
MAX9113
11
CC
MAX9113ATA/VY+
16
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Switching Characteristics
(V
= +3.0V to +3.6V, T = T
to T
. Typical values are at V
= +3.3V and T = +25°C, unless otherwise noted.) (Notes 4, 5, 6)
CC
A
MIN
MAX
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
2.5
UNITS
T
= +85°C
1.0
1.77
A
A
T
= +125°C
3.0
Differential Propagation Delay
High to Low
C = 15pF, V = ±200mV,
L
CM
ID
t
t
ns
PHLD
PLHD
V
= 1.2V (Figures 1, 2)
T
= +125°C
A
3.5
MAX9113ATA/VY+
T
T
= +85°C
= +125°C
= +125°C
1.0
1.68
2.5
3.0
A
A
Differential Propagation Delay
Low to High
C = 15pF, V = ±200mV,
L
CM
ID
ns
V
= 1.2V (Figures 1, 2)
T
A
3.5
MAX9113ATA/VY+
90
300
1200
400
Differential Pulse Skew
t
t
ps
ps
SKD1
SKD2
|t
- t
| (Note 7)
PLHD PHLD
MAX9113ATA/VY+
Differential Channel-to-Channel
Skew; Same Device
(MAX9113 only) (Note 8)
Differential Part-to-Part Skew
(Note 9)
140
C = 15pF, V = ±200mV,
L
ID
900
MAX9113ATA/VY+
MAX9113ATA/VY+
V
= 1.2V (Figures 1, 2)
CM
1
1200
1.5
t
t
ns
ns
SKD3
SKD4
Differential Part-to-Part Skew
(MAX9113 only) (Note 10)
2000
0.8
MAX9113ATA/VY+
T
T
= +85°C
= +125°C
= +125°C
0.6
0.6
A
1.0
C = 15pF, V = ±200mV,
A
L
CM
ID
Rise Time
Fall Time
t
ns
ns
TLH
V
= 1.2V (Figures 1, 2)
T
A
1.6
(MAX9113ATA/VY+)
T
T
= +85°C
0.8
1.0
A
A
C = 15pF, V = ±200mV,
= +125°C
= +125°C
L
CM
ID
t
THL
V
= 1.2V (Figures 1, 2)
T
A
1.8
(MAX9113ATA/VY+)
All channels
switching, C = 15pF,
250
300
300
L
V
V
(max) = 0.4V,
(min) = 2.7V,
OL
OH
Maximum Operating Frequency
f
MHz
MAX
MAX9113ATA/VY+T
only
40% < duty cycle <
60% (Note 6)
Note 1: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Note 2: Current into the device is defined as positive. Current out of the devices is defined as negative. All voltages are referenced
to ground except V and V
.
TH
TL
Note 3: Guaranteed by design, not production tested.
Note 4: AC parameters are guaranteed by design and characterization.
Note 5:
Note 6:
Note 7:
Note 8:
C
includes probe and test jig capacitance.
L
f
t
t
generator output conditions: t = t < 1ns (0 to 100%), 50% duty cycle, V
= 1.3V, V = 1.1V.
MAX
SKD1
SKD2
R
F
OH OL
is the magnitude difference of differential propagation delays in a channel. t
= |t
- t
|.
SKD1
PLHD
PLHD PHLD
is the magnitude difference of the t
or t
of one channel and the t
or t
of the other channel on
PLHD
PHLD
PHLD
the same device.
Note 9:
t
is the magnitude difference of any differential propagation delays between devices at the same V
and within 5°C
CC
SKD3
of each other.
Note 10: t , is the magnitude difference of any differential propagation delays between devices operating over the rated supply
SKD4
and temperature ranges.
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Test Circuit Diagrams
IN_+
IN_-
OUT_
R
GENERATOR
C
L
50Ω
50Ω
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
IN_-
+1.3V
0V DIFFERENTIAL
V = 200mV
ID
+1.2V
IN_+
+1.1V
t
t
PHLD
PLHD
V
OH
80%
50%
80%
50%
20%
20%
OUT_
V
OL
t
t
THL
TLH
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Typical Operating Characteristics
(V
= 3.3V, |V | = 200mV, V
= 1.2V, f = 200MHz, C = 15pF, T = +25°C and over recommended operating conditions, unless
CC
ID
CM IN L A
otherwise specified.)
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
3.7
3.6
3.5
3.4
3.3
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
130
120
110
100
90
83
78
73
68
63
58
53
48
I
= 4mA
I
= 4mA
V
ID
= 200mV
OUT_
OUT_
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
-40
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9113 POWER-SUPPLY CURRENT
vs. FREQUENCY
POWER-SUPPLY CURRENT
vs. TEMPERATURE
7.7
7.6
7.5
7.4
7.3
7.2
7.1
7.0
6.9
6.8
6.7
6.6
6.5
24
22
20
18
16
14
60
50
40
30
20
10
0
f
IN
= 1MHz
BOTH CHANNELS SWITCHING
LOW-HIGH
HIGH-LOW
BOTH CHANNELS SWITCHING
ONE SWITCHING
0.01
0.1
1
10
100
1000
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-15
10
35
60
85
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
2.20
120
100
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
t
PHLD
t
PHLD
80
60
40
t
PLHD
t
PLHD
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-40
-15
10
35
60
85
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Typical Operating Characteristics (continued)
(V
= 3.3V, |V | = 200mV, V
= 1.2V, f = 200MHz, C = 15pF, T = +25°C and over recommended operating conditions, unless
CC
ID
CM IN L A
otherwise specified.)
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PULSE SKEW
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
250
200
150
100
50
2.2
2.1
2.0
1.9
1.8
1.7
1.6
f
IN
= 20MHz
f
= 20MHz
IN
t
PHLD
t
PHLD
t
PLHD
t
PLHD
0
0
500
1000
1500
2000
2500
-40
-15
10
35
60
85
0
0.5
1.0
1.5
2.0
2.5
3.0
DIFFERENTIAL INPUT VOLTAGE (mV)
TEMPERATURE (°C)
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
TRANSITION TIME vs. TEMPERATURE
680
3.1
t
THL
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
630
580
530
480
430
380
330
t
PHLD
PLHD
t
TLH
t
-40
-15
10
35
60
85
10 15 20 25 30 35 40 45 50
LOAD (pF)
TEMPERATURE (°C)
TRANSITION TIME vs. LOAD
2200
1800
1400
1000
600
t
THL
t
TLH
200
10 15 20 25 30 35 40 45 50
LOAD (pF)
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Pin Configurations/Functional Diagrams/Truth Table
TOP VIEW
MAX9113
MAX9111
MAX9111
MAX9113
MAX9113
ꢄ
IN1-
1
8
7
VCC
V
1
2
3
4
8
7
6
5
IN1-
IN1+
IN2+
IN2-
IN-
IN+
1
2
3
4
8
7
6
5
V
IN1-
IN1+
IN2+
IN2-
1
2
3
4
8
7
6
5
V
CC
V
1
2
3
4
8
7
6
5
IN-
CC
CC
CC
2
3
4
IN1+
OUT1
OUT2
GND
GND
OUT1
OUT2
OUT
N.C.
GND
OUT1
OUT2
GND
GND
OUT
N.C.
IN+
N.C.
N.C.
MAX9113
IN2+
IN2-
6
5
N.C.
N.C.
SOT23
TDꢆꢂ
2ꢇꢇ ꢈ 2ꢇꢇ
SO
SO
SOT23
ꢀꢁꢂꢃꢄꢅ - ꢀꢁꢂꢃ-ꢅ
OUTꢃ
≥ 100mV
H
L
≥ -100mV
H = LOGIC LEVEL HIGH
L = LOGIC LEVEL LOW
OPEN
H
H
SHORT
100Ω PARALLEL TERMINATION (UNDRIVEN)
H
Pin Description
PIN
MAX9111
MAX9113
NAME
FUNCTION
SOT23-8
SO-8
SOT23-8
SO-8
1
2
8
5
1
2
8
5
V
Power Supply
Ground
CC
GND
IN-/IN1-
IN+/IN1+
IN2-
8
1
8
1
Receiver Inverting Differential Input
Receiver Noninverting Differential Input
Receiver Inverting Differential Input
Receiver Noninverting Differential Input
7
2
7
2
—
—
3
—
—
7
5
4
6
3
IN2+
3
7
OUT/OUT1 Receiver Output
—
4, 5, 6
—
3, 4, 6
4
6
OUT2
N.C.
Receiver Output
No Connection. Not internally connected.
—
—
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
ESD Protection
Detailed Description
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The receiver inputs of the MAX9111/MAX9113 have extra
protection against static electricity. Maxim’s engineers
have developed state-of-the-art structures to protect
these pins against ESD of ±11kV without damage. The
ESD structures withstand high ESD in all states: normal
operation, shutdown, and powered down.
LVDS Inputs
The MAX9111/MAX9113 feature LVDS inputs for inter-
facing high-speed digital circuitry. The LVDS interface
standard is a signaling method intended for point-to-point
communication over a controlled impedance media, as
defined by the ANSI/EIA/TIA-644 standards. The technol-
ogy uses low-voltage signals to achieve fast transition
times, minimize power dissipation, and noise immunity.
Receivers such as the MAX9111/MAX9113 convert LVDS
signals to CMOS/LVTTL signals at rates in excess of
500Mbps. The devices are capable of detecting differ-
ential signals as low as 100mV and as high as 1V within
a 0V to 2.4V input voltage range. The LVDS standard
specifies an input voltage range of 0 to 2.4V referenced
to ground.
ESD protection can be tested in various ways; the receiv-
er inputs of this product family are characterized for pro-
tection to the limit of ±11kV using the Human Body Model.
Human Body Model
Figure 3a shows the Human Body Model, and Figure
3b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
Fail-Safe
The fail-safe feature sets the output to a high state when
the inputs are undriven and open, terminated, or shorted.
When using one channel in the MAX9113, leave the
unused channel open. The fail-safe feature is not guaran-
teed to be operational above +85°C.
R
C
R
D
1MΩ
1500Ω
I
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
P
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 3a. Human Body ESD Test Modules
Figure 3b. Human Body Current Waveform
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MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate less
EMI due to canceling effects. Balanced cables tend to
pick up noise as common mode, which is rejected by the
LVDS receiver.
Applications Information
Supply Bypassing
Bypass V
with high-frequency surface-mount ceramic
CC
0.1μF and 0.001μF capacitors in parallel, as close to the
device as possible, with the 0.001μF valued capacitor the
closest to the device. For additional supply bypassing,
place a 10μF tantalum or ceramic capacitor at the point
where power enters the circuit board.
Termination
The MAX9111/MAX9113 input differential voltage depends
on the driver current and termination resistance. Refer to
the MAX9110/MAX9112 differential driver data sheet for
this information.
Differential Traces
Output trace characteristics affect the performance of the
MAX9111/MAX9113. Use controlled impedance traces
to match trace impedance to both transmission medium
impedance and the termination resistor. Eliminate reflec-
tions and ensure that noise couples as common mode
by running the differential traces close together. Reduce
skew by matching the electrical length of the traces.
Excessive skew can result in a degradation of magnetic
field cancellation.
Minimize the distance between the termination resistor
and receiver inputs. Use a single 1% to 2% surface-mount
resistor across the receiver inputs.
Board Layout
For LVDS applications, a four-layer PCB that provides
separate power, ground, LVDS signals, and input signals
is recommended. Isolate the input and LVDS signals from
each other to prevent coupling. For best results, separate
the input and LVDS signal planes with the power and
ground planes.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid 90°
turns and minimize the number of vias to further prevent
impedance discontinuities.
Cables and Connectors
Transmission media should have a differential characteristic
impedance of about 100Ω. Use cables and connectors
that have matched impedance to minimize impedance
discontinuities.
Typical Operating Circuit
+3.3V
+3.3V
0.001µF
0.1µF
0.001µF
0.1µF
DIN_
DRIVER
R = 100Ω
T
RECEIVER
OUT_
LVDS
MAX9111
MAX9113
MAX9110
MAX9112
Maxim Integrated
│ 10
www.maximintegrated.com
MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
TEMP
RANGE
PIN-
TOP
PART
PACKAGE MARK
MAX9111EKA
MAX9111ESA
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
8 SOT23
8 SO
AAEE
—
MAX9113EKA
MAX9113ESA
MAX9113ASA/V+
MAX9113ATA/VY+T
8 SOT23
8 SO
AAED
—
PACKAGE TYPE PACKAGE CODE
OUTLINE NO.
21-0078
8 SOT23
8 SO
K8+1
S8+2
8 SO
—
21-0041
8 TDFN
+BST
/V denotes an automotive qualified part.
8 TDFN
T822CY+2
21-100341
+Denotes a lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: CMOS
Maxim Integrated
│ 11
www.maximintegrated.com
MAX9111/MAX9113
Single/Dual LVDS Line Receivers with
Ultra-Low Pulse Skew in SOT23
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
—
Initial release
—
—
2/07
1, 2, 8, 10, 11
Updated Ordering Information, temperature, Switching Characteristics, Fail-Safe
section.
2
3
12/07
3/09
1, 2, 3, 7
1, 8
Added /V designation to Ordering Information and updated Termination section.
Updated Ordering Information, Applications, Pin Configuration, Absolute Maximum
Rating, Package Information
4
1/19
1, 2, 9
5
6
7
5/19
5/19
6/19
Updated Pin Configuration and Ordering Information table
Updated Electrical Characteristics table
1, 8, 11
3
4
Updated Electrical Characteristics table
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
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