MAX9218ECM/V+TGB [MAXIM]
Line Receiver;
| 型号： | MAX9218ECM/V+TGB |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver 接口集成电路 |
| 文件： | 总15页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-±557; Rev 5; 8/09
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
General Description
Features
♦ Proprietary Data Decoding for DC Balance and
The MAX9218 digital video serial-to-parallel converter
deserializes a total of 27 bits during data and control
phases. In the data phase, the LVDS serial input is con-
verted to 18 bits of parallel video data and in the control
phase, the input is converted to 9 bits of parallel control
data. The separate video and control phases take
advantage of video timing to reduce the serial data rate.
The MAX9218 pairs with the MAX9217 serializer to form
a complete digital video transmission system.
Reduced EMI
♦ Control Data Deserialized During Video Blanking
♦ Five Control Data Inputs Are Single Bit-Error
Tolerant
♦ Output Transition Time Is Scaled to Operating
Frequency for Reduced EMI
♦ Staggered Output Switching Reduces EMI
♦ Output Enable Allows Busing of Outputs
♦ Clock Pulse Stretch on Lock
♦ Wide ±±2 Reference Clock Tolerance
♦ Synchronizes to MAX9±17 Serializer Without
Proprietary data decoding reduces EMI and provides
DC balance. The DC balance allows AC-coupling, pro-
viding isolation between the transmitting and receiving
ends of the interface. The MAX9218 features a selec-
table rising or falling output latch edge.
External Control
♦ ISO 10605 ESD Protection
ESD tolerance is specified for ISO 10605 with ±10kV
contact discharge and ±±0kV air discharge.
♦ Separate Output Supply Allows Interface to 1.8V
to 3.3V Logic
♦ +3.3V Core Power Supply
The MAX9218 operates from a +±.±V core supply and
features a separate output supply for interfacing to 1.8V
to ±.±V logic-level inputs. This device is available in 48-
lead Thin QFN and LQFP packages and is specified
from -40°C to +85°C.
♦ Space-Saving Thin QFN and LQFP Packages
♦ -40°C to +85°C Operating Temperature
Ordering Information
Applications
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
48 LQFP
Navigation System Display
In-Vehicle Entertainment System
Video Camera
MAX9218ECM+
MAX9218ECM/V+
MAX9218ETM+
48 LQFP
48 Thin QFN-EP*
LCD Displays
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
Pin Configurations
TOP VIEW
V GND 37
CCO
24 DE_OUT
V
38
23 CNTL_OUT8
22 CNTL_OUT7
21 CNTL_OUT6
20 CNTL_OUT5
19 CNTL_OUT4
18 CNTL_OUT3
17 CNTL_OUT2
16 CNTL_OUT1T
24
23
22
21
20
19
18
17
16
15
14
13
CCO
V
GND 37
DE_OUT
CCO
RGB_OUT8 39
RGB_OUT9 40
RGB_OUT10 41
RGB_OUT11 42
RGB_OUT12 43
RGB_OUT13 44
RGB_OUT14 45
RGB_OUT15 46
V
CCO
38
CNTL_OUT8
CNTL_OUT7
CNTL_OUT6
CNTL_OUT5
CNTL_OUT4
CNTL_OUT3
CNTL_OUT2
CNTL_OUT1
CNTL_OUT0
OUTEN
RGB_OUT8 39
RGB_OUT9 40
RGB_OUT10
41
MAX9218
RGB_OUT11 42
RGB_OUT12 43
RGB_OUT13 44
RGB_OUT14 45
RGB_OUT15 46
RGB_OUT16 47
RGB_OUT17 48
MAX9218
15
14
13
CNTL_OUT0
OUTEN
RGB_OUT16
RGB_OUT17
47
48
PWRDWN
+
PWRDWN
+
LQFP
THIN QFN-EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-6±9-464±,
or visit Maxim's website at www.maxim-ic.com.
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
ABSOLUTE MAXIMUM RATINGS
CC_
Any Ground to Any Ground...................................-0.5V to +0.5V
IN+, IN- to LVDS GND...........................................-0.5V to +4.0V
V
to _GND........................................................-0.5V to +4.0V
ESD Protection
Machine Model (R = 0Ω, C = 200pF)
D
S
All Pins to GND ...........................................................±200V
IN+, IN- Short Circuit to LVDS GND or V
IN+, IN- Short Through 0.125µF (or smaller),
......Continuous
Human Body Model (R = 1.5kΩ, C = 100pF)
CCLVDS
D
S
All Pins to GND ..........................................................±±.0kV
25V Series Capacitor..........................................-0.5V to +16V
ISO 10605 (R = 2kΩ, C = ±±0pF)
D
S
(R/F, OUTEN, RNG_, REFCLK,
PWRDWN) to GND .................................-0.5V to (V
Contact Discharge (IN+, IN-) to GND............................±10kV
Air Discharge (IN+, IN-) to GND....................................±±0kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+±00°C
+ 0.5V)
CC
(RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT,
LOCK) to V GND...........................-0.5V to (V + 0.5V)
MAX9218
CCO
CCO
Continuous Power Dissipation (T = +70°C)
A
48-Lead LQFP (derate 21.7mW/°C above +70°C) ....17±9mW
48-Lead Thin QFN (derate ±7mW/°C above +70°C) .296±mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +±.0V to +±.6V, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.05V to 1.2V, input common-mode voltage V
= ⏐V /2⏐
CM
CC_
ID
CM ID
to V
- ⏐V /2⏐, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +±.±V, ⏐V ⏐ = 0.2V, V
= 1.2V,
CC
ID
A
CC_
ID
T
A
= +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN)
High-Level Input Voltage
Low-Level Input Voltage
V
2.0
V
+ 0.±
CC
V
V
IH
V
-0.±
+0.8
+70
-1.5
IL
V
= -0.±V to (V
+ 0.±V),
IN
CC
Input Current
I
-70
µA
V
IN
PWRDWN = high or low
I = -18mA
CL
Input Clamp Voltage
V
CL
SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK)
I
= -100µA
V
- 0.1
OH
CCO
I
= -2mA,
OH
V
- 0.±5
CCO
RNG1, RNG0 = high
= -2mA, RNG1, RNG0 both not high
High-Level Output Voltage
V
V
OH
I
OH
V
- 0.4
CCO
simultaneously
I
= 100µA
0.1
0.±
OL
I
= 2mA,
OL
RNG1, RNG0 = high
= 2mA, RNG1, RNG0 both not high
Low-Level Output Voltage
V
V
OL
I
OL
0.±5
+10
simultaneously
PWRDWN = low or OUTEN = low,
V
High-Impedance Output Current
I
-10
µA
OZ
= -0.±V to V
+ 0.±V
O
CCO
±
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +±.0V to +±.6V, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.05V to 1.2V, input common-mode voltage V
= ⏐V /2⏐
CC_
ID
CM ID
= +±.±V, ⏐V ⏐ = 0.2V, V
to V
- ⏐V /2⏐, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 1.2V,
UNITS
mA
CC
ID
A
CC_
ID
CM
T
= +25°C.) (Notes 1, 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
RNG1, RNG0 = high, V = 0
O
-10
-50
Output Short-Circuit Current
I
OS
RNG1, RNG0 both not high
-7
-40
simultaneously, V = 0
O
LVDS INPUT (IN+, IN-)
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
50
mV
mV
µA
TH
V
-50
-20
±5
TL
I
I
PWRDWN = high or low
PWRDWN = high or low
+20
65
IN+, IN-
50
50
kΩ
Input Bias Resistor
R
IB
V
= 0 or open,
CC_
±5
65
kΩ
PWRDWN = 0 or open, Figure 1
V
= 0 or open,
CC_
Power-Off Input Current
I
I
-40
+40
µA
INO+, INO-
PWRDWN = 0 or open
POWER SUPPLY
±MHz
20
±5
25
47
±7
70
50
RNG1 = low,
RNG0 = low
7MHz
C = 8pF,
L
7MHz
worst-case
pattern,
Figure 2
Worst-Case Supply Current
Power-Down Supply Current
RNG1 = high,
RNG0 = low
I
mA
µA
CCW
15MHz
15MHz
±5MHz
RNG1 = high,
RNG0 = high
I
(Note ±)
CCZ
_______________________________________________________________________________________
3
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
AC ELECTRICAL CHARACTERISTICS
(V
= +±.0V to ±.6V, C = 8pF, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.1V to 1.2V, input common-mode voltage
CC_
L
I
D
V
= ⏐V /2⏐ to V - ⏐V /2⏐, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +±.±V, ⏐V ⏐ = 0.2V, V
=
CM
ID
CC
ID
A
CC_
ID
CM
1.2V, T = +25°C.) (Notes 4, 5)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFCLK TIMING REQUIREMENTS
Period
t
28.57
±
±±±.00
±5
ns
MHz
%
T
Frequency
f
CLK
MAX9218
Frequency Variation
Duty Cycle
Δf
CLK
REFCLK to serializer PCLK_IN
20% to 80%
-2.0
40
+2.0
60
DC
50
%
Transition Time
t
6
ns
TRAN
SWITCHING CHARACTERISTICS
RNG1, RNG0 = high
±.2
±.8
2.7
±.6
4.4
5.5
4.5
5.±
t
R
Output Rise Time
Output Fall Time
Figure ±
Figure ±
ns
ns
RNG1, RNG0 both not high
simultaneously
RNG1, RNG0 = high
t
F
RNG1, RNG0 both not high
simultaneously
0.4 x
0.45 x
0.6 x
t
T
PCLK_OUT High Time
PCLK_OUT Low Time
t
Figure 4
Figure 4
ns
ns
HIGH
t
T
t
T
0.4 x
0.45 x
0.6 x
t
T
t
LOW
t
T
t
T
Data Valid Before PCLK_OUT
Data Valid After PCLK_OUT
t
Figure 5
Figure 5
0.±5 x t
0.±5 x t
0.4 x t
0.4 x t
ns
ns
DVB
DVA
T
T
T
t
T
2.575 x
2.725 x
Input-to-Output Delay
t
Figure 6
t +
T
t +
T
ns
DELAY
8.5
12.8
16±85 x
PLL Lock to REFCLK
t
Figure 7
ns
PLLREF
t
T
Power-Down Delay
Output Enable Time
Output Disable Time
t
Figure 7
Figure 8
Figure 9
100
±0
ns
ns
ns
PDD
t
t
OE
OZ
±0
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V and V
.
TL
TH
Note ±: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.±V or ≥ V
- 0.±V. PWRDWN is ≤ 0.±V.
CC
Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 5: C includes probe and test jig capacitance.
L
4
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
Typical Operating Characteristics
(V _ = +±.±V, C = 8pF, T = +25°C, unless otherwise noted.)
CC
L
A
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
)
CCO
80
70
60
50
40
30
20
10
0
7
6
5
4
3
2
1
0
t
R
t
F
RNG1 = RNG0 = HIGH
2.4 2.7
3
7
11 15 19 23 27 31 35
FREQUENCY (MHz)
1.8
2.1
3.0
3.3
OUTPUT SUPPLY VOLTAGE (V)
BIT-ERROR RATE
OUTPUT TRANSITION TIME
vs. CABLE LENGTH
vs. OUTPUT SUPPLY VOLTAGE (V
)
CCO
10-14
10-13
10-12
10-11
10-10
7
6
5
4
3
2
1
0
CAT5e
t
R
t
F
35MHz CLOCK
700Mbps DATA RATE
-12
RNG1 = RNG0 = BOTH NOT HIGH
FOR <12m, BER < 10
0
4
8
12
16
20
1.8
2.1
2.4
2.7
3.0
3.3
CAT5e CABLE LENGTH (m)
OUTPUT SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Pin Description
PIN
NAME
FUNCTION
Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for
latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch
edge. Internally pulled down to GND.
1
R/F
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internally pulled down to GND.
2
±
RNG1
MAX9218
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
V
CCLVDS
4
5
6
7
IN+
IN-
Noninverting LVDS Serial Data Input
Inverting LVDS Serial Data Input
LVDS Supply Ground
LVDS GND
PLL GND
PLL Supply Ground
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
8
V
CCPLL
LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input
frequency. Internal pulldown to GND.
9
RNG0
GND
10
Digital Supply Ground
Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with
0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value
capacitor closest to the supply pin.
11
V
CC
LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within 2% of the serializer
PCLK_IN frequency. Internally pulled down to GND.
12
1±
14
REFCLK
PWRDWN
OUTEN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places
the single-ended outputs in high impedance. Internally pulled down to GND.
LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising or
15–2±
CNTL_OUT [8:0] falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state
when DE_OUT is high.
LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates
CNTL_OUT[8:0] are active.
24
DE_OUT
25, ±7
26, ±8
V
GND
Output Supply Ground
CCO
Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the
device as possible, with the smallest value capacitor closest to the supply pin.
V
CCO
27
28
LOCK
LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low.
PCLK_OUT
RGB_OUT [17:0]
EP
LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F.
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into
the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the
last state when DE_OUT is low.
29–±6,
±9–48
—
Exposed Pad for Thin QFN Package Only. Connect to GND.
6
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
Functional Diagram
R/F
OUTEN
1
0
RGB_OUT[17:0]
IN+
IN-
DC BALANCE/
DECODE
SER-TO-PAR
CNTL_OUT[8:0]
DE_OUT
PCLK_OUT
REFCLK
RNG0
RNG1
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
MAX9218
IN+
0.9V
0.1V
CCO
DE_OUT
LOCK
R
IB
LVDS
RECEIVER
1.2V
PCLK_OUT
CCO
RGB_OUT[17:0]
CNTL_OUT[8:0]
t
t
F
R
IB
R
IN-
Figure 1. LVDS Input Bias
Figure ±. Output Rise and Fall Times
PCLK_OUT
PCLK_OUT
2.0V
0.8V
t
HIGH
ODD
RGB_OUT
CNTL_OUT
EVEN
RGB_OUT
CNTL_OUT
t
LOW
RISING LATCH EDGE SHOWN (R/F = HIGH).
Figure 2. Worst-Case Output Pattern
Figure 4. High and Low Times
_______________________________________________________________________________________
7
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
2.0V
PCLK_OUT
0.8V
PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE)
2
t
t
DVB
DVA
DE_OUT
2.0V
2.0V
0.8V
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
0.8V
Figure 5. Synchronous Output Timing
20 SERIAL BITS
PCLK_OUT SHOWN FOR R/F = HIGH
SERIAL-WORD N
SERIAL-WORD N + 1
IN+, IN-
t
DELAY
PCLK_OUT
CNTL_OUT
RGB_OUT
PARALLEL-WORD N - 1
PARALLEL-WORD N
Figure 6. Deserializer Delay
8
_______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
2.0V
0.8V
PWRDWN
REFCLK
TRANSITION
WORD
FOUND
t
PLLREF
t
PDD
RECOVERED CLOCK
HIGH IMPEDANCE
HIGH IMPEDANCE
PCLK_OUT
CLOCK STRETCH
VALID DATA
RGB_OUT
CNTL_OUT
DE_OUT
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
HIGH IMPEDANCE
LOCK
NOTE: R/F = HIGH
Figure 7. PLL Lock to REFCLK and Power-Down Delay
2.0V
OUTEN
OUTEN
0.8V
t
OE
t
OZ
DE_OUT
LOCK
DE_OUT
LOCK
RGB_OUT[17:0]
CNTL_OUT[8:0]
HIGH-Z
ACTIVE
RGB_OUT[17:0]
CNTL_OUT[8:0]
ACTIVE
HIGH-Z
Figure 8. Output Enable Time
Figure 9. Output Disable Time
_______________________________________________________________________________________
9
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Detailed Description
Applications Information
The MAX9218 DC-balanced deserializer operates at a
Selection of AC-Coupling Capacitors
See Figure 12 for calculating the capacitor values for
AC-coupling, depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
parallel clock frequency of ±MHz to ±5MHz, deserializ-
ing video data to the RGB_OUT[17:0] outputs when the
data enable output DE_OUT is high, or control data to
the CNTL_OUT[8:0] outputs when DE_OUT is low. The
video phase words are decoded using 2 overhead bits,
EN0 and EN1. Control phase words are decoded with 1
overhead bit, EN0. Encoding, performed by the
MAX9217 serializer, reduces EMI and maintains DC
balance across the serial cable. The serial input word
formats are shown in Table 1 and Table 2.
MAX9218
Termination and Input Bias
The IN+ and IN- LVDS inputs are internally connected
to +1.2V through ±5kΩ (min) to provide biasing for AC-
coupling (Figure 1). Assuming 100Ω interconnect, the
LVDS input can be terminated with a 100Ω resistor.
Match the termination to the differential impedance of
the interconnect.
Control data inputs C0 to C4, each repeated over ± seri-
al bit times by the serializer, are decoded using majority
voting. Two or three bits at the same state determine the
state of the recovered bit, providing single bit-error tol-
erance for C0 to C4. The state of C5 to C8 is deter-
mined by the level of the bit itself (no voting is used).
Use a Thevenin termination, providing 1.2V bias, on an
AC-coupled link in noisy environments. For intercon-
nect with 100Ω differential impedance, pull each LVDS
line up to V
with 1±0Ω and down to ground with 82Ω
CC
AC-Coupling Benefits
AC-coupling increases the input voltage of the LVDS
receiver to the voltage rating of the capacitor. Two
capacitors are sufficient for isolation, but four capaci-
tors—two at the serializer output and two at the deseri-
alizer input—provide protection if either end of the
cable is shorted to a high voltage. AC-coupling blocks
low-frequency ground shifts and common-mode noise.
The MAX9217 serializer can also be DC-coupled to the
MAX9218 deserializer. Figure 10 is the AC-coupled
serializer and deserializer with two capacitors per link,
and Figure 11 is the AC-coupled serializer and deseri-
alizer with four capacitors per link.
at the deserializer input (Figure 10 and Figure 11). This
termination provides both differential and common-
mode termination. The impedance of the Thevenin ter-
mination should be half the differential impedance of
the interconnect and provide a bias voltage of 1.2V.
Table 1. Serial Video Phase Word Format
0
1
2
±
4
5
6
7
8
9
10
S8
11
S9
12
1±
14
15
16
17
18
19
EN0 EN1 S0
S1
S2
S±
S4
S5
S6
S7
S10 S11 S12 S1± S14 S15 S16 S17
Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table ±. Serial Control Phase Word Format
0
1
2
±
4
5
6
7
8
9
10
11
12
1±
14
15
16
17
18
19
EN0 C0
C0
C0
C1
C1
C1
C2
C2
C2
C±
C±
C±
C4
C4
C4
C5
C6
C7
C8
Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs.
10 ______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
V
CC
130Ω
130Ω
R/F
OUTEN
*
RGB_IN
1
0
RGB_OUT
1
0
OUT
IN
*
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
82Ω
CMF
DE_IN
PCLK_OUT
REFCLK
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9217
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
*CAPS CAN BE AT EITHER END.
Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link
V
CC
130Ω
82Ω
130Ω
R/F
OUTEN
RGB_OUT
RGB_IN
1
0
1
0
IN
OUT
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
CMF
DE_IN
PCLK_OUT
REFCLK
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9217
MAX9218
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link
______________________________________________________________________________________ 11
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
Input Frequency Detection
A frequency-detection circuit detects when the LVDS
input is not switching. When not switching, all outputs
AC-COUPLING CAPACITOR VALUE
vs. PARALLEL CLOCK FREQUENCY
except LOCK are low, LOCK is high, and PCLK_OUT
140
follows REFCLK. This condition occurs, for example, if
125
the serializer is not driving the interconnect or if the
interconnect is open.
FOUR CAPACITORS PER LINK
TWO CAPACITORS PER LINK
110
95
Frequency Range Setting (RNG[1:0])
MAX9218
The RNG[1:0] inputs select the operating frequency
80
range of the MAX9218 and the transition time of the out-
65
puts. Select the frequency range that includes the
MAX9217 serializer PCLK_IN frequency. Table ± shows
50
the selectable frequency ranges and the corresponding
35
data rates and output transition times.
20
Power Down
18
21
24
27
30
33
36
Driving PWRDWN low puts the outputs in high imped-
ance and stops the PLL. With PWRDWN ≤ 0.±V and all
PARALLEL CLOCK FREQUENCY (MHz)
LVTTL/LVCMOS inputs ≤ 0.±V or ≥ V
- 0.±V, the sup-
CC
Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to ±5MHz
ply current is reduced to less than 50µA. Driving
PWRDWN high initiates lock to the local reference clock
(REFCLK) and afterwards to the serial input.
If a transition word is not detected within 220 cycles of
PCLK_OUT, LOCK is driven high and the other outputs
except PCLK_OUT are driven low. REFCLK is output on
PCLK_OUT and the deserializer continues monitoring
the serial input for a transition word. See Figure 7 for
the synchronization timing diagram.
Lock and Loss of Lock (LOCK)
When PWRDWN is driven high, the PLL begins locking
to REFCLK, drives LOCK from high impedance to high
and the other outputs from high impedance to low
except PCLK_OUT. PCLK_OUT outputs REFCLK while
the PLL is locking to REFCLK. Locking to REFCLK
takes a maximum of 16,±85 REFCLK cycles. When
locking to REFCLK is complete, the serial input is moni-
tored for a transition word. When a transition word is
found, LOCK is driven low indicating valid output data,
and the parallel rate clock recovered from the serial
input is output on PCLK_OUT. PCLK_OUT is stretched
on the change from REFCLK to recovered clock (or
vice versa).
Output Enable (OUTEN) and
Busing Outputs
The outputs of two MAX9218s can be bused to form a
2:1 mux with the outputs controlled by the output
enable. Wait ±0ns between disabling one deserializer
(driving OUTEN low) and enabling the second one (dri-
ving OUTEN high) to avoid contention of the bused out-
puts. OUTEN controls all outputs.
Rising or Falling Output Latch Edge (R/F)
The MAX9218 has a selectable rising or falling output
latch edge through a logic setting on R/F. Driving R/F
high selects the rising output latch edge, which latches
the parallel output data into the next chip on the rising
edge of PCLK_OUT. Driving R/F low selects the falling
output latch edge, which latches the parallel output
data into the next chip on the falling edge of
PCLK_OUT. The MAX9218 output-latch-edge polarity
does not need to match the MAX9217 serializer input-
latch-edge polarity. Select the latch-edge polarity
required by the chip being driven by the MAX9218.
Table 3. Frequency Range Programming
PARALLEL
CLOCK
(MHz)
SERIAL
DATA RATE TRANSITION
OUTPUT
RNG1 RNG0
(Mbps)
TIME
0
0
1
1
0
1
0
1
± to 7
60 to 140
Slow
Fast
7 to 15
140 to ±00
±00 to 700
15 to ±5
1± ______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
(V
supply and V
GND). The grounds are
Staggered and Transition Time Adjusted
Outputs
CCLVDS
CCLVDS
isolated by diode connections. Bypass each V
,
CC
V
, V
, and V
pin with high-frequency,
RGB_OUT[17:0] are grouped into three groups of six,
with each group switching about 1ns apart in the video
phase to reduce EMI and ground bounce.
CNTL_OUT[8:0] switch during the control phase. Output
transition times are slower in the ±MHz-to-7MHz and
7MHz-to-15MHz ranges and faster in the 15MHz-to-
±5MHz range.
CCO CCPLL
CCLVDS
surface-mount ceramic 0.1µF and 0.001µF capacitors
in parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin. The
outputs are powered from V
, which accepts a
CCO
1.71V to ±.6V supply, allowing direct interface to inputs
with 1.8V to ±.±V logic levels.
Cables and Connectors
Interconnect for LVDS typically has a differential
impedance of 100Ω. Use cables and connectors that
have matched differential impedance to minimize
impedance discontinuities.
Data Enable Output (DE_OUT)
The MAX9218 deserializes video and control data at dif-
ferent times. Control data is deserialized during the video
blanking time. DE_OUT high indicates that video data is
being deserialized and output on RGB_OUT[17:0].
DE_OUT low indicates that control data is being deserial-
ized and output on CNTL_OUT[8:0]. When outputs are
not being updated, the last data received is latched on
the outputs. Figure 1± shows the DE_OUT timing.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Power-Supply Circuits and Bypassing
There are separate on-chip power domains for digital
Board Layout
Separate the LVTTL/LVCMOS outputs and LVDS inputs
to prevent crosstalk. A four-layer PCB with separate lay-
ers for power, ground, and signals is recommended.
circuits and LVTTL/LVCMOS inputs (V
supply and
GND), PLL
CC
GND), outputs (V
supply and V
CCO
CCO
(V
supply and V
GND), and the LVDS input
CCPLL
CCPLL
CONTROL DATA
VIDEO DATA
CONTROL DATA
PCLK_OUT
CNTL_OUT
DE_OUT
RGB_OUT
PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE)
= OUTPUT DATA HELD
Figure 1±. Output Timing
______________________________________________________________________________________ 13
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
The Human Body Model discharge components are C
ESD Protection
S
= 100pF and R = 1.5kΩ (Figure 14). The ISO 10605
D
The MAX9218 ESD tolerance is rated for the Human
Body Model, Machine Model, and ISO 10605. ISO
10605 specifies ESD tolerance for electronic systems.
discharge components are C = ±±0pF and R = 2kΩ
S
D
(Figure 15). The Machine Model discharge components
are C = 200pF and R = 0Ω (Figure 16).
S
D
R
D
R
0Ω
D
1MΩ
1.5kΩ
MAX9218
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
200pF
C
S
100pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
SOURCE
SOURCE
Figure 14. Human Body ESD Test Circuit
Figure 16. Machine Model ESD Test Circuit.
R
D
50Ω TO 100Ω
2kΩ
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 15. ISO 10605 Contact Discharge ESD Test Circuit
Package Information
Chip Information
For the latest package outline information and land patterns, go
PROCESS: CMOS
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 LQPF
48 TQFN
C48+5
±1-0054
±1-0141
T4866+1
14 ______________________________________________________________________________________
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Deserializer
MAX9218
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
±
4
5
2/08
5/08
8/09
Corrected typo (REF_IN should be REFCLK) in Figure 11
11
Corrected LQFP package, added Machine Model ESD, and corrected
diagrams
1, 2, 6, 7, 10,
11, 14–18
Added automotive qualified part to Ordering Information
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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