MAX9223_V01 [MAXIM]
22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipsets;
| 型号： | MAX9223_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipsets |
| 文件： | 总15页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3861; Rev 1; 12/07
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipsets
General Description
Features
♦ Ideal for Serializing Cell Phone LCD or Imager
The MAX9223/MAX9224 serializer/deserializer chipsets
reduce wiring by serializing 22 bits onto a single differen-
tial pair. 22 bits are serialized in each cycle of the paral-
lel input clock resulting in a 110Mbps to 220Mbps net
serial-data rate ideal for cell phone QVGA and QCIF dis-
plays. The MAX9223 serializes the 18-bit RGB, VSYNC,
HSYNC, and two control signals from the baseband
processor to reduce wiring through the hinge to the LCD
controller. The 2-wire serial interface uses low-current dif-
ferential signaling (LCDS) for low EMI, high common-
mode noise immunity, and ground-shift tolerance. The
MAX9223/MAX9224 automatically identify the word
boundary in serial data in case of signal interruption. The
MAX9224 power-down is controlled by the MAX9223.
The MAX9223 and MAX9224 consume 3.5µA or less in
power-down mode.
Parallel Interface
♦ MAX9223 Serializes 18-Bit RGB, VSYNC, HSYNC,
and Two Control Signals
♦ LCDS Rejects Common-Mode Noise
♦ Automatic Location of Word Boundary After Signal
Interruption
♦ Power-Down Control Through the Serial Link
♦ Power-Down Supply Current
0.5µA (max)—MAX9223
3.0µA (max)—MAX9224
♦ +2.375V to +3.465V Core Supply Voltage
♦ Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic
The MAX9223 serializer operates from a single +2.375V
to +3.465V supply and accepts +1.71V to +3.465V
inputs. The MAX9224 deserializer operates from a
+2.375V to +3.465V core supply and has a separate
♦
15kV Human Body Model ꢀSD Protection
♦ -40°C to +85°C Operating Temperature Range
output buffer supply (V
), allowing +1.71V to
DDO
Ordering Information
+3.465V output high levels.
The MAX9223/MAX9224 are specified over the -40°C to
+85°C extended temperature range and are available
in 28-pin TQFN (4mm x 4mm x 0.8mm) packages with
an exposed paddle.
PIN-
PACKAGꢀ
PKG
CODꢀ
PART
TꢀMP RANGꢀ
MAX9223ETI
-40°C to +85°C 28 TQFN-EP*
T2844-1
T2844-1
T2844-1
T2844-1
MAX9223ETI+ -40°C to +85°C 28 TQFN-EP*
MAX9224ETI -40°C to +85°C 28 TQFN-EP*
Applications
MAX9224ETI+ -40°C to +85°C 28 TQFN-EP*
Cell Phones
LCDs
+Denotes lead-free package.
*EP = Exposed paddle.
Digital Cameras
Pin Configurations appear at end of data sheet.
Typical Application Circuit
LCDS
PARALLEL
TO
SERIAL
TO
PARALLEL
LATCH
INPUT
PARALLEL
DATA IN
OUTPUT
LATCH
PARALLEL
DATA OUT
SERIAL
TIMING
AND
PIXEL
CLOCK IN
CONTROL
POWER-DOWN
CONTROL
PIXEL
CLOCK OUT
TIMING AND CONTROL
DLL
MAX9223
MAX9224
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
ABSOLUTꢀ MAXIMUM RATINGS
V
V
to GND...........................................................-0.5V to +4.0V
Single-Layer PCB (derate 20.8mW/°C
DD
DDO
to GND.........................................................-0.5V to +4.0V
above +70°C).............................................................1667mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (Human Body Model)
Serial Interface (SDO+, SDO-, SDI+,
SDI-) to GND .....................................................-0.5V to +4.0V
Single-Ended Inputs (DIN_, PCLKIN,
PWRDN) to GND ....................................-0.5V to (V
+ 0.5V)
DD
Single-Ended Outputs (DOUT_,
PCLKOUT) to GND ..............................-0.5V to (V
Continuous Power Dissipation (T = +70°C)
SDO+, SDO-, SDI+, SDI- to GND ...............................> 15kV
All Other Pins ................................................................> 2kV
+ 0.5V)
DDO
A
28-Pin TQFN (4mm x 4mm x 0.8mm)
Multilayer PCB (derate 28.6mW/°C
above +70°C).............................................................2286mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ꢀLꢀCTRICAL CHARACTꢀRISTICS—MAX9223
(V = +2.375V to +3.465V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +2.5V, T = +25°C.) (Notes 1, 2)
DD
A
DD
A
PARAMꢀTꢀR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLꢀ-ꢀNDꢀD INPUTS (PCLKIN, DIN_, PWRDN)
High-Level Input Voltage
Low-Level Input Voltage
V
1.19
-0.3
-20
V
+ 0.3
DD
V
V
IH
V
+0.3
+20
IL
V
= 0V to V
DD
IN
Input Current
I
-0.3V ≤ V < 0V
µA
IN
IN
-100
+100
V
< V ≤ (V
+ 0.3V)
DD
IN
DD
LCDS OUTPUT (SDO+, SDO-)
I
High level
Low level
600
200
643
229
880
300
880
ODH
Differential Output Current (Note 3)
µA
µA
I
ODL
Output Short-Circuit Current
I
Shorted to 0V or V
DD
OS
POWꢀR SUPPLY
PCLKIN = 5MHz
(110Mbps)
4.4
5.6
4.1
5.4
8.2
8.2
V
= 2.5V,
DD
DIN_ = all low or
all high
Supply Current
I
mA
DD
PCLKIN = 10MHz
(220Mbps)
PCLKIN = 5MHz
(110Mbps)
10.6
V
= 2.5V,
DD
Worst-Case Pattern Supply Current
Power-Down Supply Current
I
mA
µA
DDW
Figure 1
PCLKIN = 10MHz
(220Mbps)
10.6
0.5
I
All inputs = low
DDZ
2
_______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
DC ꢀLꢀCTRICAL CHARACTꢀRISTICS—MAX9224
(V
= +2.375V to +3.465V, V
= +1.71V to +3.465V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
DD
DDO
A
DD
V
= +2.5V, T = +25°C.) (Notes 1, 2)
DDO
A
PARAMꢀTꢀR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLꢀ-ꢀNDꢀD OUTPUTS (PCLKOUT, DOUT_)
High-Level Output Voltage
Low-Level Output Voltage
V
V
V
= +2.375V to +3.465V, I
= -1mA
0.8 x V
DDO
V
V
OH
DDO
DDO
OH
V
= +2.375V to +3.465V, I = 1mA
0.2
OL
OL
V
V
V
= 2.375V
= 3.135V
= 3.465V
-2
-9
DDO
DDO
DDO
Output shorted
to ground
Output Short-Circuit Current
I
mA
OS
-25
LCDS INPUT (SDI+, SDI-)
Differential Input-Current Threshold
Common-Mode Input Current
I
400
500
90
µA
µA
ID
I
IC
-300
69
+300
109
132
153
112
136
375
I
I
I
I
I
I
= 0µA at V
= 0µA at V
= 0µA at V
= 3.3V 5ꢀ
= 2.8V 5ꢀ
= 2.5V 5ꢀ
IC
IC
IC
IC
IC
IC
DD
DD
DD
82
108
125
91
Differential Input Impedance
Z
Z
95
Ω
ID
IC
=
=
=
300µA at V
300µA at V
300µA
= 3.3V 5ꢀ
67
DD
DD
= 2.8V 5ꢀ
86
108
167
2
Common-Mode Input Impedance
Input Capacitance
90
Ω
C
SDI+ or SDI- to ground
pF
IN
POWꢀR SUPPLY
PCLKOUT = 5MHz
(110Mbps)
9
9
12
12
12
12
V
= V
= 2.5V
DDO
DD
DOUT_ = all high or
all low
Supply Current (Note 4)
I
mA
mA
TOT
PCLKOUT = 10MHz
(220Mbps)
PCLKOUT = 5MHz
(110Mbps)
10
10
0.08
C = 5pF, V
V
Figure 2
=
L
DD
Worst-Case Pattern
Supply Current (Note 4)
= 2.5V,
I
DDO
TOTW
PCLKOUT = 10MHz
(220Mbps)
Power-Down Supply Current
(Note 4)
I
3
µA
ꢀ
TOTZ
Supply Difference
V
MAX9223 V
to MAX9224 V
-5
+5
SD
DD
DD
GROUND POTꢀNTIAL
Ground Difference
V
MAX9223 to MAX9224 ground difference
-0.2
+0.2
V
GD
_______________________________________________________________________________________
3
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
AC ꢀLꢀCTRICAL CHARACTꢀRISTICS—MAX9223
(V = +2.375V to +3.465V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +2.5V, T = +25°C.) (Note 3)
DD
A
DD
A
PARAMꢀTꢀR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLKIN INPUT RꢀQUIRꢀMꢀNTS (Figure 3)
Input Rise Time
Input Fall Time
PCLKIN Period
High-Level Pulse Width
Low-Level Pulse Width
Setup Time
t
2
2
ns
ns
ns
ns
ns
ns
ns
R
t
F
t
100
0.3 x t
0.3 x t
3
200
P
t
0.7 x t
0.7 x t
PWH
P
P
P
P
t
PWL
t
S
Hold Time
t
1
H
AC ꢀLꢀCTRICAL CHARACTꢀRISTICS—MAX9224
(V
= V
= +2.375V to +3.465V, C = 5pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= V
=
DDO
DD
DDO
L
A
DD
+2.5V, T = +25°C.) (Notes 3, 5)
A
PARAMꢀTꢀR
PCLKOUT Period
SYMBOL
CONDITIONS
MIN
100
0.4 x t
0.4 x t
5
TYP
MAX
UNITS
ns
t
Figure 4
200
0.6 x t
0.6 x t
P
High-Level Pulse Width
Low-Level Pulse Width
Data Valid Before PCLKOUT
Data Valid After PCLKOUT
t
Figure 4
Figure 4
Figure 4
Figure 4
ns
PWH
P
P
P
P
t
ns
PWL
t
t
ns
VB
VA
5
ns
SꢀRIALIZꢀR AND DꢀSꢀRIALIZꢀR LINK
From V = V
are ramping up
= 2.375V when supplies
DDO
6144 x
t
P
DD
t
PU1
Power-Up Time
ns
µs
4096 x
t
From PWRDN low to high
From PWRDN high to low
PU2
t
P
Power-Down Time
t
2.8
10
PWRDN
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +85°C.
A
Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma.
Note 4: I
= I
+ I
.
TOT
DD
DDO
Note 5: C includes probe and test jig capacitance.
L
4
_______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Test Circuits/Timing Diagrams
ODD DOUT_
ODD DIN_
EVEN DOUT_
PCLKOUT
EVEN DIN_
PCLKIN
Figure 1. Serializer Worst-Case Switching Pattern
Figure 2. Deserializer Worst-Case Switching Pattern
t
P
t
t
PWH
PWL
V
V
V
IH
IH
IH
PCLKIN
V
V
IL
IL
t
F
t
R
t
t
H
S
V
V
IH
IH
DIN_
PWRDN
V
V
IL
IL
V
IS THE MINIMUM HIGH-LEVEL INPUT AND V IS THE MAXIMUM LOW-LEVEL INPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE).
IL
IH
Figure 3. Serializer Input Timing
t
P
t
PWH
t
PWL
V
V
V
OH
OH
OH
PCLKOUT
DOUT_
V
V
V
OL
OL
t
t
VA
VB
V
OH
OH
V
V
OL
OL
V
IS THE MINIMUM HIGH-LEVEL OUTPUT AND V IS THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE).
OL
OH
Figure 4. Deserializer Output Timing
_______________________________________________________________________________________
5
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Typical Operating Characteristics
(V
= V
= +2.8V, logic input levels = 0 to +2.8V, logic output load C = 5pF, T = +25°C, unless otherwise noted.)
DDO L A
DD
MAX9223
MAX9223
MAX9223
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
10
8
10
8
10
8
DIN[21:0] = ALL LOW
DIN[21:0] = ALL HIGH
DIN[21:0] = WORST-CASE SWITCHING PATTERN
PCLKIN = 10MHz
PCLKIN = 10MHz
PCLKIN = 10MHz
6
6
6
4
4
4
PCLKIN = 5MHz
PCLKIN = 5MHz
PCLKIN = 5MHz
2
2
2
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MAX9223
SUPPLY CURRENT vs. FREQUENCY
MAX9223
SUPPLY CURRENT vs. FREQUENCY
MAX9223
SUPPLY CURRENT vs. FREQUENCY
10
8
8
6
4
2
8
6
4
2
DIN[21:0] = ALL HIGH
DIN[21:0] = ALL LOW
DIN[21:0] = WORST-CASE SWITCHING PATTERN
V
= 3.3V
DD
V
= 3.3V
DD
V
= 3.3V
DD
V
= 2.8V
DD
V
= 2.8V
DD
V
= 2.8V
DD
6
V
= 2.5V
DD
V
= 2.5V
DD
8
4
V
= 2.5V
DD
8
2
5
6
7
9
10
5
6
7
9
10
5
6
7
8
9
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
MAX9223 POWER-DOWN
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9224
MAX9224
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.20
0.16
0.12
0.08
0.04
12
11
10
9
12
11
10
9
PCLKIN = LOW
PWRDN = LOW
DIN[21:0] = ALL LOW
DOUT[21:0] = ALL LOW
PCLKOUT = 10MHz
DOUT[21:0] = ALL HIGH
PCLKOUT = 10MHz
PCLKOUT = 5MHz
PCLKOUT = 5MHz
8
8
0
7
7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Typical Operating Characteristics (continued)
(V
= V
= +2.8V, logic input levels = 0 to +2.8V, logic output load C = 5pF, T = +25°C, unless otherwise noted.)
DDO L A
DD
MAX9224
SUPPLY CURRENT vs. FREQUENCY
MAX9224
SUPPLY CURRENT vs. FREQUENCY
MAX9224
SUPPLY CURRENT vs. SUPPLY VOLTAGE
12
11
10
9
12
11
10
9
12
11
10
9
DOUT[21:0] = ALL LOW
DOUT[21:0] = ALL HIGH
DOUT[21:0] = WORST-CASE SWITCHING
PATTERN
V
= 3.3V
DD
PCLKOUT = 10MHz
V
= 3.3V
DD
V
= 2.8V
DD
V
= 2.8V
DD
V
= 2.5V
DD
V
= 2.5V
DD
8
PCLKOUT = 5MHz
8
8
8
7
7
7
5
6
7
8
9
10
5
6
7
9
10
2.3
2.5
2.7
2.9
3.1
3.3
3.5
FREQUENCY (MHz)
FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
MAX9224
SUPPLY CURRENT vs. FREQUENCY
MAX9224 POWER-DOWN
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9224 DOUT OUTPUT-HIGH VOLTAGE
vs. SOURCE CURRENT
12
11
10
9
0.6
0.5
0.4
0.3
0.2
2.75
2.50
2.25
2.00
1.75
1.50
1.25
SDI+/SDI- PULLED UP TO V
DD
DOUT[21:0] = ALL LOW
DOUT[21:0] = WORST-CASE SWITCHING
PATTERN
V
= 2.375V
V
= 2V
DDO
DDO
V
= 3.3V
DD
V
= 2.8V
DD
V
= 2.5V
DD
8
8
V
= 1.71V
DDO
0.4
7
5
6
7
9
10
2.3
2.5
2.7
2.9
3.1
3.3
3.5
0
0.2
0.6
0.8
1.0
FREQUENCY (MHz)
SUPPLY VOLTAGE (V)
SOURCE CURRENT (mA)
MAX9224 DOUT OUTPUT-LOW VOLTAGE
vs. SINK CURRENT
MAX9224 DIFFERENTIAL INPUT
IMPEDANCE vs. SUPPLY VOLTAGE
150
120
90
60
30
0
160
140
120
100
80
V
= +1.71V TO +2.375V
DDO
0
0.2
0.4
0.6
0.8
1.0
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SINK CURRENT (mA)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Pin Description (MAX9223)
PIN
NAMꢀ
FUNCTION
DIN13–DIN2,
DIN1, DIN0,
DIN21–DIN14
1–12, 14, 15,
21–28
Single-Ended Parallel Data Inputs. The 22 data bits are loaded into the input latch on the rising
edge of PCLKIN. DIN[21:0] are 1.71V to 3.465V tolerant. Internally pulled down to GND.
Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel
data input. Internally pulled down to GND.
13
16
PCLKIN
Power-Down Input. Pull PWRDN low to place the MAX9223 and MAX9224 in power-down mode.
Drive PWRDN high for normal operation. Internally pulled down to GND.
PWRDN
17
18
19
SDO-
SDO+
GND
Inverting LCDS Serial-Data Output
Noninverting LCDS Serial-Data Output
Ground
Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
20
—
V
DD
EP
Exposed Paddle. Connect EP to ground.
Pin Description (MAX9224)
PIN
NAMꢀ
FUNCTION
DOUT21,
DOUT0, DOUT1,
DOUT2–DOUT20
1, 7, 8, 10–28
Single-Ended Parallel Data Outputs. DOUT[21:0] are valid on the rising edge of PCLKOUT.
Output Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
2
V
DDO
3
4
5
GND
SDI+
SDI-
Ground
Noninverting LCDS Serial-Data Input
Inverting LCDS Serial-Data Input
Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
6
V
DD
Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically
the pixel clock).
9
PCLKOUT
EP
—
Exposed Paddle. Connect EP to ground.
8
_______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
MAX9223 Functional Diagram
MAX9224 Functional Diagram
SDO+
SDO-
SDI+
SDI-
PARALLEL
TO
SERIAL
SERIAL
TO
PARALLEL
LATCH
INPUT
OUTPUT
LATCH
DIN[21:0]
PCLKIN
DOUT[21:0]
TIMING
AND
CONTROL
PWRDN
TIMING AND CONTROL
PCLKOUT
DLL
MAX9223
MAX9224
and PCLKOUT. Output data is valid on the rising edge
of PCLKOUT.
Detailed Description
The MAX9223 serializer operates at a 5MHz to 10MHz
parallel clock frequency, serializing 22 bits of parallel
input data DIN[21:0] in each cycle of the parallel clock.
DIN[21:0] are latched on the rising edge of PCLKIN.
The data and internally generated serial clock are com-
bined and transmitted through SDO+/SDO- using multi-
level LCDS. The MAX9224 deserializer receives the
LCDS signal on SDI+/SDI-. The deserialized data and
recovered parallel clock are available at DOUT[21:0]
The first bit (G) is internally grounded and transmitted
first. Bit 0 (DIN[0]) is the first valid data bit. Boundary
bits OH are used by the MAX9224 deserializer to identi-
fy the word boundary and are the inverse polarity of
data bit 21 (DIN[21]). Therefore, at least one level tran-
sition is guaranteed in one word. The clock is recov-
ered from the serial input.
Serial word format:
G
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 OH OH
to data transmission, the MAX9223 serializer adds
boundary bits (OH) to the end of the latched word.
These boundary bits are the inverse of the last bit of the
latched word. During data transmission, the MAX9224
deserializer continuously monitors the state of the
boundary bits of each word. If a word boundary error is
LCDS
The MAX9223/MAX9224 use a proprietary multilevel
LCDS interface. Figure 5 provides a representation of
the data and clock in the multilevel LCDS interface.
This interface offers advantages over other chipsets,
such as requiring only one differential pair as the trans-
mission medium, the inherently aligned data and clock,
and much smaller current levels than the 4mA typically
found in traditional LVDS interfaces.
detected, the serial link is pulled up to V
and the
DD
MAX9224 powers down. The MAX9223 detects the
pullup of the serial link and powers down for 1.0µs. After
1.0µs, the MAX9223 powers up, causing the power-up
of the MAX9224. Then the word boundary is reestab-
lished, and data transfer resumes. The handshaking
function is disabled when PWRDN is pulled low.
MAX9223/MAX9224 Handshaking
The handshaking function of the MAX9223/MAX9224
provides bidirectional communication between the two
devices in case a word boundary error is detected. Prior
_______________________________________________________________________________________
9
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
PARALLEL DATA INPUT
PCLK IN
DIN[21:0]
2
0
9
1
21
1
1
1
12
1
DIN
0
1
3
1
10 11
0
13 14
20
1
EXAMPLE
INPUT
0
0
1
LCDS SERIAL DATA OUTPUT FOR EXAMPLE INPUT (SD0±)
G*
0
0
1
1
1
1
0
1
0
1
1
1
OH
OH
*INTERNALLY PREPENDED BIT—ALWAYS 0.
NOTE: THERE IS NO TRANSITION BETWEEN OH BITS.
Figure 5. Multilevel LCDS Output Representation
LCDS output is not driven until the DLL locks. 4096
clock cycles are required for the power-up and link
synchronization, before valid DIN can be latched. See
Figure 6 for an overall power-up and power-down tim-
ing diagram. For normal operation, PCLKIN must be
running and settled before driving PWRDN high.
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9223 serializer is
latched on the rising edge of PCLKIN. Figure 3 shows
the serializer input timing.
If V
= 0, the LCDS outputs are high impedance to
DD
PCLKOUT Strobe
The serial-data output of the MAX9224 deserializer is
valid on the rising edge of PCLKOUT. Figure 4 shows
the deserializer output timing.
ground and differential.
Ground-Shift Tolerance
The MAX9223/MAX9224 are designed to function nor-
mally in the event of a slight shift in ground potential.
However, the MAX9224 deserializer ground must be
within 0.2V relative to the MAX9223 serializer ground
to maintain proper operation.
Power-Down and Power-Up
Driving PWRDN low puts the MAX9223 in power-down
mode and sends a pulse to power down the MAX9224. In
power-down mode, the DLL is stopped, SDO+/SDO- are
high impedance to ground and differential, and the LCDS
MAX9224 Output Buffer Supply (V
)
DDO
DDO
link is weakly biased around V
- 0.8V. With PWRDN
DD
The MAX9224 parallel outputs are powered from V
which accepts a +1.71V to +3.465V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
,
and all inputs low, the combined MAX9223/MAX9224
supply current is reduced to 3.5µA or less.
Driving PWRDN high starts DLL lock to PCLKIN and ini-
tiates a MAX9224 power-up sequence. The MAX9223
10 ______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
IN POWER-
DOWN
POWER-UP AND LINK
SYNCHRONIZATION
POWER-
DOWN
IN POWER-
DOWN
DATA TRANSFER
t
PWRDN
PWRDN
PCLKIN
DIN_
1
2
4096
DON'T CARE
DON'T CARE
1
N
1
LOW
HIGH
N
LOW
DOUT_
HIGH
PCLKOUT
Figure 6. MAX9223/MAX9224 Power-Up/Power-Down Sequence
Flex Cable, PCB Interconnect,
and Connectors
R
D
1MΩ
1.5kΩ
Interconnect for LCDS typically has a differential imped-
ance of 110Ω. Use interconnect and connectors that have
matched differential impedance to minimize impedance
discontinuities.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
100pF
Board Layout and Supply Bypassing
Separate the logic and LCDS signals to prevent
crosstalk. A PCB or flex with separate layers for power,
ground, and signals is recommended.
SOURCE
Figure 7. Human Body Model ESD Test Circuit
Bypass each V
and V
pin with high-frequency,
DDO
DD
surface-mount ceramic 0.1µF and 0.01µF capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
Chip Information
ESD Protection
The MAX9223/MAX9224 LCDS inputs and outputs
(SDO+/SDO-, SDI+/SDI-) are rated for 15kV ESD pro-
tection using the Human Body Model. The Human Body
PROCESS: CMOS
Model discharge components are C = 100pF and R =
S
D
1.5kΩ (Figure 7).
______________________________________________________________________________________ 11
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Pin Configurations
TOP VIEW
21 20 19 18 17 16 15
21 20 19 18 17 16 15
14
13
14
13
DIN20 22
DIN19 23
DIN18 24
DIN1
DOUT14 22
DOUT15 23
DOUT16 24
DOUT6
DOUT5
PCLKIN
12 DIN2
12 DOUT4
DIN3
11
DOUT3
DOUT2
PCLKOUT
DOUT1
25
26
27
28
25
26
27
28
11
10
9
DIN17
DIN16
DIN15
DIN14
DOUT17
DOUT18
DOUT19
DOUT20
MAX9223
MAX9224
10
9
DIN4
DIN5
DIN6
8
8
1
2
3
4
5
6
7
1
2
3
4
5
6
7
TQFN-ꢀP
TQFN-ꢀP
12 ______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 13
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
14 ______________________________________________________________________________________
22-Bit, Low-Power, 5MHz to 10MHz
Serializer and Deserializer Chipset
Revision History
RꢀVISION RꢀVISION
PAGꢀS
DꢀSCRIPTION
CHANGꢀD
NUMBꢀR
DATꢀ
0
10/05
Initial release
—
Changed min output short-circuit current from -20 to -25 and updated package
outlines.
1
12/07
3, 13
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2007 Maxim Integrated Products
Springer
is a registered trademark of Maxim Integrated Products, Inc.
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