MAX9226ETE-T [MAXIM]
Line Transceiver, 1 Func, CMOS, PQCC16, 3 X 3 MM, 0.80 MM HEIGHT, MO220, TQFN-16;
| 型号： | MAX9226ETE-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Transceiver, 1 Func, CMOS, PQCC16, 3 X 3 MM, 0.80 MM HEIGHT, MO220, TQFN-16 接口集成电路 |
| 文件： | 总15页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3680; Rev 1; 12/07
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
General Description
Features
♦ Ideal for Serializing Cell Phone Camera Parallel
The MAX9225/MAX9226 serializer/deserializer chipset
reduces wiring by serializing 10 bits onto a single differ-
ential pair. Ten bits are serialized in each cycle of the
parallel input clock resulting in a 100Mbps to 200Mbps
net serial-data rate. The MAX9225 serializes the 8-bit
YUV, HSYNC and VSYNC outputs from a camera mount-
ed in the flip part of the phone, reducing wiring through
the hinge to the baseband processor in the base of the
phone. The 2-wire serial interface uses low-current differ-
ential signaling (LCDS) for low EMI, high common-mode
noise immunity, and ground-shift tolerance. The
MAX9225/MAX9226 automatically identify the word
boundary in the serial data in case of signal interruption.
The MAX9226 power-down is controlled by the
MAX9225. The MAX9225/MAX9226 consume 3.5µA or
less in power-down mode.
Interface
♦ MAX9225 Serializes 8-Bit YUV, HSYNC, and VSYNC
♦ LCDS Rejects Common-Mode Noise
♦ Automatic Location of Word Boundary After
Signal Interruption
♦ Power-Down Control Through the Serial Link
♦ Power-Down Supply Current
0.5µA (max) for MAX9225
3.0µA (max) for MAX9226
♦ +2.375V to +3.465V Core Supply Voltage
♦ Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic
♦
15kV Human Body Model ꢀSD Protection
The MAX9225 serializer operates from a single +2.375V
to +3.465V supply and accepts +1.71V to +3.465V
inputs. The MAX9226 deserializer operates from a
+2.375V to +3.465V core supply and has a separate
♦ -40°C to +85°C Operating Temperature Range
Ordering Information
output buffer supply (V
), allowing +1.71V to
DDO
+3.465V output high levels.
TꢀMP
PIN-
PKG
TOP
PART
RANGꢀ
PACKAGꢀ CODꢀ MARK
The MAX9225/MAX9226 are specified over the -40°C to
+85°C extended temperature range and are available
in 16-pin TQFN (3mm x 3mm x 0.8mm) packages with
an exposed paddle.
MAX9225ETE -40°C to +85°C 16 TQFN-EP* T1633-4 ADO
MAX9225ETE+ -40°C to +85°C 16 TQFN-EP* T1633-4 ADO
MAX9226ETE -40°C to +85°C 16 TQFN-EP* T1633-4 ADX
MAX9226ETE+ -40°C to +85°C 16 TQFN-EP* T1633-4 ADX
Applications
+Denotes lead-free package.
*EP = Exposed paddle.
Cell Phone Cameras
Digital Cameras
Pin Configurations appear at end of data sheet.
Typical Application Circuit
LCDS
PARALLEL
SERIAL
TO
PARALLEL
INPUT
LATCH
PARALLEL
DATA IN
OUTPUT
LATCH
PARALLEL
DATA OUT
TO
SERIAL
TIMING
AND
PIXEL
CLOCK IN
CONTROL
POWER-DOWN
CONTROL
PIXEL
CLOCK OUT
TIMING AND CONTROL
DLL
MAX9225
MAX9226
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
ABSOLUTꢀ MAXIMUM RATINGS
V
V
to GND...........................................................-0.5V to +4.0V
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection (Human Body Model)
SDO+, SDO-, SDI+, SDI- to GND ...............................> 15kV
All Other Pins to GND ...................................................> 2kV
DD
DDO
to GND.........................................................-0.5V to +4.0V
Serial Interface (SDO+, SDO-, SDI+,
SDI-) to GND .....................................................-0.5V to +4.0V
Single-Ended Inputs (DIN_, PCLKIN,
PWRDN) to GND ....................................-0.5V to (V
+ 0.5V)
DD
Single-Ended Outputs (DOUT_,
PCLKOUT) to GND ..............................-0.5V to (V
+ 0.5V)
DDO
Continuous Power Dissipation (T = +70°C)
A
16-Pin TQFN (3mm x 3mm x 0.8mm)
Multilayer PCB (derate 20.8mW/°C
above +70°C).............................................................1667mW
Single-Layer PCB (derate 15.6mW/°C
above +70°C).............................................................1250mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
5/MAX926
DC ꢀLꢀCTRICAL CHARACTꢀRISTICS (MAX9225)
(V = +2.375V to +3.465V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +2.5V, T = +25°C.) (Notes 1, 2)
DD
A
DD
A
PARAMꢀTꢀR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLꢀ-ꢀNDꢀD INPUTS (PCLKIN, DIN_, PWRDN)
High-Level Input Voltage
Low-Level Input Voltage
V
1.19
-0.3
-20
V
+ 0.3
DD
V
V
IH
V
+0.3
+20
IL
V
= 0V to V
DD
IN
Input Current
I
-0.3V ≤ V < 0V
µA
IN
IN
-100
+100
V
< V ≤ (V
+ 0.3V)
DD
IN
DD
LCDS OUTPUT (SDO+, SDO-)
I
High level
Low level
575
200
643
229
880
300
880
ODH
Differential Output Current
µA
µA
I
ODL
Output Short-Circuit Current
I
Shorted to 0V or V
DD
OS
POWꢀR SUPPLY
PCLKIN = 10MHz,
100Mbps
4.7
6.2
4.7
6.2
8.2
8.2
Supply Current
I
V
V
= 2.5V
= 2.5V,
mA
DD
DD
PCLKIN = 20MHz,
200Mbps
PCLKIN = 10MHz,
100Mbps
10.6
DD
Worst-Case Pattern Supply Current
Power-Down Supply Current
I
mA
µA
DDW
Figure 1
PCLKIN = 20MHz,
200Mbps
10.6
0.5
I
All inputs = low
DDZ
2
_______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
DC ꢀLꢀCTRICAL CHARACTꢀRISTICS (MAX9226)
(V
= +2.375V to +3.465V, V
= +1.71V to +3.465V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
=
DD
DD
DDO
A
V
DDO
= +2.5V, T = +25°C.) (Notes 1, 2)
A
PARAMꢀTꢀR
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.2
UNITS
SINGLꢀ-ꢀNDꢀD OUTPUTS (PCLKOUT, DOUT_)
High-Level Output Voltage
Low-Level Output Voltage
V
V
V
= +2.375V to +3.465V, I
= -1mA
0.8 x V
DDO
V
V
OH
DDO
DDO
OH
V
= +2.375V to +3.465V, I = 1mA
OL
OL
V
V
V
= 2.375V
= 3.135V
= 3.465V
-2
-9
DDO
DDO
DDO
Output shorted
to ground
Output Short-Circuit Current
I
mA
OS
-25
LCDS INPUT (SDI+, SDI-)
Differential Input-Current Threshold
Common-Mode Input Current
I
400
400
90
µA
µA
ID
IC
I
-300
69
+300
114
137
161
117
141
375
I
I
I
I
I
I
= 0µA, V
= 0µA, V
= 0µA, V
= 3.3V 5ꢀ
= 2.8V 5ꢀ
= 2.5V 5ꢀ
IC
IC
IC
IC
IC
IC
DD
DD
DD
82
108
125
91
Differential Input Impedance
Z
Z
95
Ω
ID
IC
=
=
=
300µA, V
300µA, V
300µA
= 3.3V 5ꢀ
67
DD
DD
= 2.8V 5ꢀ
86
108
167
2
Common-Mode Input Impedance
Input Capacitance
90
Ω
C
SDI+ or SDI- to ground
pF
IN
POWꢀR SUPPLY
PCLKOUT = 10MHz,
100Mbps
8.4
9.1
9.7
12
12
12
13
V
= V
= 2.5V
DDO
DD
Supply Current
I
mA
mA
TOT
(Note 4)
PCLKOUT = 20MHz,
200Mbps
PCLKOUT = 10MHz,
100Mbps
C = 5pF, V
V
Figure 2 (Note 4)
=
DD
L
Worst-Case Pattern
Supply Current
= 2.5V,
I
DDO
TOTW
PCLKOUT = 20MHz,
200Mbps
11.6
0.3
Power-Down Supply Current
Supply Difference
I
(Note 4)
3.0
+5
µA
ꢀ
TOTZ
V
MAX9225 V
to MAX9226 V
DD
-5
SD
DD
GROUND POTꢀNTIAL
Ground Difference
V
MAX9225 to MAX9226 ground difference
-0.2
+0.2
V
GD
_______________________________________________________________________________________
3
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
AC ꢀLꢀCTRICAL CHARACTꢀRISTICS (MAX9225)
(V = +2.375V to +3.465V, T = -40°C to +85°C, unless otherwise noted. Typical values are at V = +2.5V, T = +25°C.) (Note 3)
DD
A
DD
A
PARAMꢀTꢀR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLKIN INPUT RꢀQUIRꢀMꢀNTS (Figure 3)
Input Rise Time
Input Fall Time
PCLKIN Period
High-Level Pulse Width
Low-Level Pulse Width
Setup Time
t
2
2
ns
ns
ns
ns
ns
ns
ns
R
t
F
t
50
0.3 x t
0.3 x t
3
100
P
t
0.7 x t
0.7 x t
PWH
P
P
P
P
t
PWL
t
S
Hold Time
t
1
H
AC ꢀLꢀCTRICAL CHARACTꢀRISTICS (MAX9226)
(V
= V
= +2.375V to +3.465V, C = 5pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= V
=
DDO
5/MAX926
DD
DDO
L
A
DD
+2.5V, T = +25°C.) (Notes 3, 5)
A
PARAMꢀTꢀR
PCLKOUT Period
SYMBOL
CONDITIONS
MIN
50
TYP
MAX
UNITS
ns
t
Figure 4
100
0.6 x t
0.6 x t
P
High-Level Pulse Width
Low-Level Pulse Width
Data Valid Before PCLKOUT
Data Valid After PCLKOUT
t
Figure 4
Figure 4
Figure 4
Figure 4
0.4 x t
0.4 x t
5
ns
PWH
P
P
P
P
t
ns
PWL
t
t
ns
VB
VA
5
ns
SꢀRIALIZꢀR AND DꢀSꢀRIALIZꢀR LINK
From V = V
are ramping up
= 2.375V when supplies
DDO
11,264 x
DD
t
PU1
PU2
t
P
Power-Up Time
ns
µs
4096 x
t
From PWRDN low to high
From PWRDN high to low
t
P
Power-Down Time
t
2.8
10
PWRDN
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +85°C.
A
Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma.
Note 4: I
= I
+ I
.
TOT
DD
DDO
Note 5: C includes probe and test jig capacitance.
L
4
_______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
Test Circuits/Timing Diagrams
ODD DOUT_
ODD DIN_
EVEN DOUT_
PCLKOUT
EVEN DIN_
PCLKIN
Figure 1. Serializer Worst-Case Switching Pattern
Figure 2. Deserializer Worst-Case Switching Pattern
t
P
t
t
PWH
PWL
V
IH
V
V
IH
IH
PCLKIN
V
V
IL
IL
t
F
t
R
t
H
t
S
V
V
IH
IH
DIN_
PWRDN
V
IL
V
IL
V
IH
IS THE MINIMUM HIGH-LEVEL INPUT, AND V IS THE MAXIMUM LOW-LEVEL INPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE)
IL
Figure 3. Serializer Input Timing
t
P
t
PWH
t
PWL
V
V
OH
V
OH
OH
PCLKOUT
DOUT_
V
OL
V
V
OL
t
t
VB
VA
V
OH
OH
V
OL
V
OL
V
OH
IS THE MINIMUM HIGH-LEVEL OUTPUT, AND V IS THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE)
OL
Figure 4. Deserializer Output Timing
_______________________________________________________________________________________
5
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
Typical Operating Characteristics
(V
DD
= V
= +2.8V, logic input levels = 0 to +2.8V, logic output load C = 5pF, T = +25°C, unless otherwise noted.)
DDO L A
MAX9225
MAX9225
MAX9225
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
10
8
10
8
10
8
DIN[9:0] = ALL LOW
DIN[9:0] = ALL HIGH
DIN[9:0] = WORST-CASE SWITCHING PATTERN
PCLKIN = 20MHz
PCLKIN = 20MHz
PCLKIN = 20MHz
6
6
6
PCLKIN = 10MHz
PCLKIN = 10MHz
PCLKIN = 10MHz
4
4
4
2
2
2
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
5/MAX926
MAX9225
MAX9225
MAX9225
SUPPLY CURRENT vs. FREQUENCY
SUPPLY CURRENT vs. FREQUENCY
SUPPLY CURRENT vs. FREQUENCY
10
8
10
8
10
8
DIN[9:0] = ALL LOW
DIN[9:0] = ALL HIGH
DIN[9:0] = WORST-CASE SWITCHING PATTERN
V
DD
= 3.3V
V
DD
= 3.3V
V
= 3.3V
DD
V
DD
= 2.8V
V
DD
= 2.8V
V
= 2.8V
DD
6
6
6
V
DD
= 2.5V
V
DD
= 2.5V
V
= 2.5V
DD
4
4
4
2
2
2
10
12
14
16
18
20
10
12
14
16
18
20
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
MAX9225 POWER-DOWN
SUPPLY CURRENT vs. FREQUENCY
MAX9226
MAX9226
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.20
0.16
0.12
11
10
9
11
10
9
PCLKIN = LOW
DIN[9:0] = ALL LOW
DIN[9:0] = ALL HIGH
PWRDN = LOW
DIN[9:0] = ALL LOW
PCLKOUT = 20MHz
PCLKOUT = 20MHz
0.08
0.04
0
8
8
PCLKOUT = 10MHz
PCLKOUT = 10MHz
7
7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SUPPLY VOLTAGE (MHz)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
6
_______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
Typical Operating Characteristics (continued)
(V
DD
= V
= +2.8V, logic input levels = 0 to +2.8V, logic output load C = 5pF, T = +25°C, unless otherwise noted.)
DDO
L
A
MAX9226
MAX9226
MAX9226
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. FREQUENCY
SUPPLY CURRENT vs. FREQUENCY
11
10
9
11
10
9
11
10
9
DIN[9:0] = WORST-CASE SWITCHING PATTERN
DIN[9:0] = ALL LOW
DIN[9:0] = ALL HIGH
PCLKOUT = 20MHz
V
= 3.3V
DD
V
DD
= 3.3V
V
DD
= 2.8V
V
DD
= 2.8V
V
DD
= 2.5V
V
DD
= 2.5V
8
8
8
PCLKOUT = 10MHz
7
7
7
2.3
2.5
2.7
2.9
3.1
3.3
3.5
10
12
14
16
18
20
10
12
14
16
18
20
SUPPLY VOLTAGE (V)
FREQUENCY (MHz)
FREQUENCY (MHz)
MAX9226
SUPPLY CURRENT vs. FREQUENCY
MAX9226 POWER-DOWN
SUPPLY CURRENT vs. FREQUENCY
MAX9226 DOUT OUTPUT-HIGH VOLTAGE
vs. SOURCE CURRENT
11
10
9
2.75
2.50
2.25
0.6
DIN[9:0] = WORST-CASE SWITCHING PATTERN
SDI+/SDI- PULLED UP TO V
DOUT[9:0] = ALL LOW
DD
V
= 2.375V
= 2V
DDO
V
0.5
0.4
V
= 3.3V
DD
V
= 2.8V
DD
DDO
2.00
1.75
V
= 2.5V
DD
V
= 1.71V
DDO
8
0.3
0.2
1.50
1.25
7
10
12
14
16
18
20
0
0.2
0.4
0.6
0.8
1.0
2.3
2.5
2.7
2.9
3.1
3.3
3.5
FREQUENCY (MHz)
SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
MAX9226 DOUT OUTPUT-LOW VOLTAGE
vs. SINK CURRENT
MAX9226 DIFFERENTIAL INPUT
IMPEDANCE vs. SUPPLY VOLTAGE
150
120
90
160
140
120
100
80
V
= +1.71V TO +2.375V
DDO
60
30
0
0
0.2
0.4
0.6
0.8
1.0
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SINK CURRENT (mA)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
Pin Description (MAX9225)
PIN
NAMꢀ
FUNCTION
1–7,
DIN6–DIN0,
Single-Ended Parallel Data Inputs. The 10 data bits are loaded into the input latch on the rising
14, 15, 16
DIN9, DIN8, DIN7 edge of PCLKIN. 1.71V to 3.465V tolerant. Internally pulled down to GND.
Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel
data input. Internally pulled down to GND.
8
9
PCLKIN
Power-Down Input. Pull PWRDN low to place the MAX9225/MAX9226 in power-down mode.
Drive PWRDN high for normal operation. Internally pulled down to GND.
PWRDN
10
11
12
SDO-
SDO+
GND
Inverting LCDS Serial-Data Output
Noninverting LCDS Serial-Data Output
Ground
Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible with the smallest value capacitor closest to the supply pin.
13
—
V
DD
EP
Exposed Paddle. Connect EP to ground.
5/MAX926
Pin Description (MAX9226)
PIN
1
NAMꢀ
GND
SDI+
SDI-
FUNCTION
Ground
2
Noninverting LCDS Serial-Data Input
Inverting LCDS Serial-Data Input
3
Core Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
4
V
DD
Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically
the pixel clock).
5
6–15
16
PCLKOUT
DOUT0–DOUT9 Single-Ended Parallel Data Output. DOUT[9:0] are valid on the rising edge of PCLKOUT.
Output Supply Voltage. Bypass to GND with 0.1µF and 0.01µF capacitors in parallel as close to
the device as possible with the smallest value capacitor closest to the supply pin.
Exposed Paddle. Connect EP to ground.
V
DDO
EP
—
8
_______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
Functional Diagram (MAX9225)
Functional Diagram (MAX9226)
SDO+
SDO-
SDI+
SDI-
PARALLEL
TO
SERIAL
SERIAL
TO
PARALLEL
INPUT
LATCH
OUTPUT
LATCH
DIN[9:0]
PCLKIN
DOUT[9:0]
TIMING
AND
CONTROL
PWRDN
TIMING AND CONTROL
PCLKOUT
DLL
MAX9225
MAX9226
LCDS
Detailed Description
The MAX9225/MAX9226 use a proprietary multilevel
LCDS interface. Figure 5 provides a representation of
the data and clock in the multilevel LCDS interface. This
interface offers advantages over other chipsets, such
as requiring only one differential pair as the transmis-
sion medium, the inherently aligned data and clock,
and much smaller current levels than the 4mA typically
found in traditional LVDS interfaces.
The MAX9225 serializer operates at a 10MHz-to-20MHz
parallel clock frequency, serializing 10 bits of parallel
input data DIN[9:0] in each cycle of the parallel clock.
DIN[9:0] are latched on the rising edge of PCLKIN. The
data and internally generated serial clock are com-
bined and transmitted through SDO+/SDO- using multi-
level LCDS. The MAX9226 deserializer receives the
LCDS signal on SDI+/SDI-. The deserialized data and
recovered parallel clock are available at DOUT[9:0]
and PCLKOUT. Output data is valid on the rising edge
of PCLKOUT.
MAX9225/MAX9226 Handshaking
The handshaking function of the MAX9225/MAX9226
provides bidirectional communication between the two
devices in case a word boundary error is detected. Prior
to data transmission, the MAX9225 serializer adds
boundary bits (OH) to the end of the latched word.
These boundary bits are the inverse of the last bit of the
latched word. During data transmission, the MAX9226
deserializer continuously monitors the state of the
boundary bits of each word. If a word boundary error is
Bit 0 (DIN[0]) is transmitted first. Boundary bits OH1
and OH2 are used by the MAX9226 deserializer to
identify the word boundary. OH1 is the inverse polarity
of data bit 9 (DIN[9]), and OH2 is the inverse polarity of
OH1. Therefore, at least two level transitions are guar-
anteed in one word. The clock is recovered from the
serial input.
detected, the serial link is pulled up to V
and the
DD
Serial word format:
MAX9226 powers down. The MAX9225 detects the
pullup of the serial link and powers down for 1.0µs. After
1.0µs, the MAX9225 powers up, causing the power-up
of the MAX9226. Then the word boundary is reestab-
lished, and data transfer resumes. The handshaking
function is disabled when PWRDN is pulled low.
0
1
2
3
4
5
6
7
8
9
OH1 OH2
_______________________________________________________________________________________
9
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
PARALLEL DATA INPUT
PCLK IN
DIN[9:0]
0
1
1
1
2
0
3
1
4
0
5
0
6
1
7
0
8
1
9
1
DIN
EXAMPLE
INPUT
LCDS SERIAL-DATA OUTPUT FOR EXAMPLE INPUT (SD0+/SDO-)
5/MAX926
1
1
0
1
0
1
0
1
1
OH2
0
OH1
NOTE: OH1 AND OH2 ARE OPPOSITE POLARITY.
Figure 5. Multilevel LCDS Output Representation
LCDS output is not driven until the DLL locks. 11,264
clock cycles are required for the power-up and link syn-
chronization before valid DIN can be latched. See
Figure 6 for an overall power-up and power-down tim-
ing diagram. For normal operation, PCLKIN must be
running and settled before driving PWRDN high.
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9225 serializer is
latched on the rising edge of PCLKIN. Figure 3 shows
the serializer input timing.
If V
= 0, the LCDS outputs are high impedance to
DD
PCLKOUT Strobe
The serial-data output of the MAX9226 deserializer is
valid on the rising edge of PCLKOUT. Figure 4 shows
the deserializer output timing.
ground and differential.
Ground-Shift Tolerance
The MAX9225/MAX9226 are designed to function nor-
mally in the event of a slight shift in ground potential.
However, the MAX9226 deserializer ground must be
within 0.2V relative to the MAX9225 serializer ground
to maintain proper operation.
Power-Down and Power-Up
Driving PWRDN low puts the MAX9225 in power-down
mode and sends a pulse to power down the MAX9226.
In power-down mode, the DLL is stopped, SDO+/SDO-
are high impedance to ground and differential, and the
MAX9226 Output Buffer Supply (V
)
DDO
DDO
LCDS link is weakly biased around (V
- 0.8V). With
DD
The MAX9226 parallel outputs are powered from V
which accepts a +1.71V to +3.465V supply, allowing
direct interface to inputs with 1.8V to 3.3V logic levels.
,
PWRDN and all inputs low, the combined MAX9225/
MAX9226 supply current is reduced to 3.5µA or less.
Driving PWRDN high starts DLL lock to PCLKIN and ini-
tiates a MAX9226 power-up sequence. The MAX9225
10 ______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
IN POWER-
DOWN
POWER-UP AND LINK
SYNCHRONIZATION
POWER-
DOWN
IN POWER-
DOWN
DATA TRANSFER
t
PWRDN
PWRDN
PCLKIN
DIN_
t
1
2
PU2
DON'T CARE
DON'T CARE
1
N
1
LOW
HIGH
N
LOW
DOUT_
HIGH
PCLKOUT
Figure 6. MAX9225/MAX9226 Power-Up/Power-Down Sequence
Flex Cable, PCB Interconnect,
and Connectors
R
D
1MΩ
1.5kΩ
Interconnect for LCDS typically has a differential imped-
ance of 100Ω. Use interconnect and connectors that have
matched differential impedance to minimize impedance
discontinuities.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
100pF
Board Layout and Supply Bypassing
Separate the LVTTL/LVCMOS and LCDS signals to pre-
vent crosstalk. A PCB or flex with separate layers for
power, ground, and signals is recommended.
SOURCE
Bypass each V
and V
pin with high-frequency,
DDO
Figure 7. Human Body Model ESD Test Circuit
DD
surface-mount ceramic 0.1µF and 0.01µF capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
Chip Information
ESD Protection
The MAX9225/MAX9226 are rated for 15kV ESD
protection using the Human Body Model. The Human
PROCESS: CMOS
Body Model discharge components are C = 100pF and
S
R = 1.5kΩ (Figure 7).
D
______________________________________________________________________________________ 11
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
Pin Configurations
TOP VIEW
12
11
10
9
12
11
10
9
PCLKIN
DIN0
DOUT2
8
13
14
13
14
V
8
7
6
5
DOUT7
DOUT8
DD
DOUT1
7
6
5
DIN9
MAX9225
MAX9226
DIN1
DOUT0
DIN8 15
16
DOUT9 15
16
DIN2
PCLKOUT
DIN7
V
DDO
1
2
3
4
1
2
3
4
TQFN-ꢀP
TQFN-ꢀP
5/MAX926
12 ______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
(NE - 1)
X e
MARKING
E
E/2
D2/2
(ND - 1)
e
X e
D/2
AAAA
C
D2
D
L
k
b
0.10 M
C A B
C
L
E2/2
L
E2
C
L
C
L
0.10
C
0.08
A
C
A2
A1
L
L
e
e
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
1
21-0136
I
2
______________________________________________________________________________________ 13
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PKG
8L 3x3
12L 3x3
16L 3x3
EXPOSED PAD VARIATIONS
REF. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
D2
E2
PKG.
PIN ID
JEDEC
CODES
A
b
0.70 0.75 0.80 0.70 0.75 0.80
0.25 0.30 0.35 0.20 0.25 0.30
0.70 0.75 0.80
0.20 0.25 0.30
MIN.
0.25
0.95
0.95
0.95
0.95
0.65
0.65
0.95
0.95
NOM. MAX.
MIN.
0.25
0.95
0.95
0.95
NOM. MAX.
TQ833-1
T1233-1
T1233-3
0.70
1.10
1.10
1.10
1.25
1.25
1.25
0.70
1.10
1.10
1.10
1.10
0.80
0.80
1.10
1.10
1.25
1.25
1.25
1.25
1.25
0.95
0.95
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.35 x 45°
0.225 x 45°
0.225 x 45°
0.35 x 45°
0.35 x 45°
WEEC
D
2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10
2.90 3.00 3.10 2.90 3.00 3.10 2.90 3.00 3.10
WEED-1
WEED-1
WEED-1
WEED-2
WEED-2
WEED-2
WEED-2
WEED-2
E
e
0.65 BSC.
0.50 BSC.
0.50 BSC.
T1233-4
T1633-2
1.25
1.25
0.95
0.95
1.25
1.25
L
0.35 0.55 0.75 0.45 0.55 0.65 0.30 0.40 0.50
1.10
0.80
0.80
1.10
0.95
0.65
0.65
0.95
N
ND
NE
A1
A2
k
8
12
16
T1633F-3
T1633FH-3
T1633-4
2
3
4
2
3
4
1.25
1.25
0
0.02 0.05
0
0.02 0.05
0
0.02 0.05
T1633-5
1.10
0.95
0.20 REF
0.20 REF
0.20 REF
-
-
-
-
-
-
0.25
0.25
0.25
5/MAX926
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED 0.10mm.
PACKAGE OUTLINE
8, 12, 16L THIN QFN, 3x3x0.8mm
2
21-0136
I
2
14 ______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz
Serializer and Deserializer Chipset
5/MAX926
Revision History
RꢀVISION
NUMBꢀR
RꢀVISION
DATꢀ
PAGꢀS
DꢀSCRIPTION
CHANGꢀD
0
1/06
Initial release
—
Changed max output short-circuit current from -20 to -25 in EC table; various
style changes.
1
12/07
2, 3, 11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2007 Maxim Integrated Products
Springer
is a registered trademark of Maxim Integrated Products, Inc.
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