MAX9236EUM-TD [MAXIM]
Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48;
| 型号： | MAX9236EUM-TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Line Receiver, 4 Func, 4 Rcvr, CMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48 光电二极管 接口集成电路 |
| 文件： | 总15页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3641; Rev 1; 10/07
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
General Description
Features
The MAX9234/MAX9236/MAX9238 deserialize three
LVDS serial-data inputs into 21 single-ended
LVCMOS/LVTTL outputs. A parallel-rate LVDS clock
received with the LVDS data streams provides timing for
deserialization. The outputs have a separate supply,
allowing 1.8V to 5V output logic levels. All these devices
are hot-swappable and allow “on-the-fly” frequency
programming.
♦ DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦ On-the-Fly Frequency Programming
♦ Operating Frequency Range
8MHz to 34MHz (MAX9234/MAX9236)
16MHz to 66MHz (MAX9238)
♦ Falling-Edge Output Strobe (MAX9236/MAX9238)
The MAX9234/MAX9236/MAX9238 feature DC balance,
which allows isolation between a serializer and deseri-
alizer using AC-coupling. Each deserializer decodes
data transmitted by one of the MAX9209/MAX9211/
MAX9213/MAX9215 serializers.
♦ Slower Output Transitions for Reduced EMI
(MAX9234/MAX9236)
♦ High-Impedance Outputs when PWRDWN Is Low
Allow Output Busing
The MAX9234 has a rising-edge output strobe. The
MAX9236/MAX9238 have a falling-edge output strobe.
The MAX9234/MAX9236/MAX9238 operate in DC-
balanced mode only.
♦ 5V-Tolerant PWRDWN Input
♦ PLL Requires No External Components
♦ Up to 1.386Gbps Throughput
The MAX9234/MAX9236 operate with a parallel input
clock of 8MHz to 34MHz, while the MAX9238 operates
from 16MHz to 66MHz. The transition time of the single-
ended outputs is increased on the low-frequency version
parts (MAX9234/MAX9236) for reduced EMI. The LVDS
inputs meet ISO 10605 ESD specification, 25kV for Air-
Gap Discharge and 8kV Contact Discharge.
♦ Separate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V Logic
♦ LVDS Inputs Meet ISO 10605 ESD Requirements
♦ LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
The MAX9234/MAX9236/MAX9238 are available in 48-pin
TSSOP packages and operate over the -40°C to +85°C
temperature range.
♦ Low-Profile, 48-Lead TSSOP Package
♦ +3.3V Main Power Supply
♦ -40°C to +85°C Operating Temperature Range
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
Laser Printers
MAX9234EUM
MAX9236EUM
MAX9238EUM
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
48 TSSOP
48 TSSOP
48 TSSOP
U48-1
U48-1
U48-1
Functional Diagram and Pin Configuration appear at end of
data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
to GND...........................................................-0.5V to +4.0V
ESD Protection
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
All Pins to GND ..................................…………………. 5kV
PWRDWN to GND....................................................-0.5V to 6.0V
IEC 61000-4-2 (R = 330Ω, CS = 150pF)
Contact Discharge (RxIN_, RxCLK IN_) to GND ......... 8kV
Air-Gap Discharge (RxIN_, RxCLK IN_) to GND ....... 15kV
D
RxOUT_, RxCLK OUT to GND................-0.5V to (V
+ 0.5V)
CCO
Continuous Power Dissipation (T = +70°C)
A
48-Pin TSSOP (derate 16mW/°C above +70°C) ....... 1282mW
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
ISO 10605 (R = 2kΩ, C = 330pF)
D S
Contact Discharge (RxIN_, RxCLK IN_) to GND ........ 8kV
Air Discharge (RxIN_, RxCLK IN_) to GND ............... 25kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, V
= +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.05V to 1.2V, input common-
CCO ID
CC
mode voltage V
= ⏐V /2⏐ to 2.4V - ⏐V /2⏐, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= V
=
CM
ID
ID
A
CC
CCO
+3.3V, ⏐V ⏐ = 0.2V, V
= 1.25V, T = +25°C.) (Notes 1, 2)
CM A
ID
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUT (PWRDWN)
High-Level Input Voltage
Low-Level Input Voltage
Input Current
V
2.0
-0.3
-70
5.5
+0.8
+70
-1.5
V
V
IH
V
IL
IN
I
V
= high or low
µA
V
IN
Input Clamp Voltage
V
I
CL
= -18mA
CL
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT)
V
V
V
V
-
-
-
-
CCO
0.1
I
I
= -100µA
= -2mA
OH
CCO
0.25
RxCLK OUT
RxOUT_
MAX9234/
MAX9236
High-Level Output Voltage
V
V
OH
CCO
0.40
OH
CCO
0.25
MAX9238
I
I
= 100µA
= 2mA
0.1
0.2
OL
RxCLK OUT
RxOUT_
MAX9234/
MAX9236
Low-Level Output Voltage
V
V
OL
0.26
0.2
OL
MAX9238
PWRDWN = low,
High-Impedance Output Current
I
-20
+20
µA
OZ
V
= -0.3V to V
+ 0.3V
CCO
OUT_
RxCLK OUT
RxOUT_
-10
-5
-40
-20
-40
-75
-37
-75
MAX9234/
MAX9236
V
= 3.0V to
CCO
3.6V, V
= 0
OUT
Output Short-Circuit Current
(Note: Short one output at a
time.)
MAX9238
-10
-28
-14
-28
I
mA
OS
RxCLK OUT
RxOUT_
MAX9234/
MAX9236
V
= 4.5V to
CCO
5.5V, V
= 0
OUT
MAX9238
2
_______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, V
= +3.0V to +5.5V, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.05V to 1.2V, input common-
CCO ID
CC
mode voltage V
= ⏐V /2⏐ to 2.4V - ⏐V /2⏐, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= V
=
CM
ID
ID
A
CC
CCO
+3.3V, ⏐V ⏐ = 0.2V, V
= 1.25V, T = +25°C.) (Notes 1, 2)
CM A
ID
PARAMETER
LVDS INPUTS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Input-High Threshold
Differential Input-Low Threshold
Input Current
V
50
mV
mV
µA
TH
V
-50
-25
TL
I
I
PWRDWN = high or low
= V = 0 or open,
PWRDWN = 0 or open
+25
+40
IN+, IN-
V
CC
CCO
Power-Off Input Current
I
I
-40
42
µA
INO+, INO-
PWRDWN = high or low (Figure 1)
Input Resistor 1
R
78
kΩ
IN1
V
= V
= 0 or open (Figure 1)
CCO
CC
POWER SUPPLY
8MHz
42
57
MAX9234/
MAX9236
C = 8pF,
L
worst-case
16MHz
34MHz
16MHz
34MHz
66MHz
98
Worst-Case Supply Current
Power-Down Supply Current
I
pattern; V
=
CC
mA
µA
CCW
63
V
= 3.0V to
CCO
MAX9238
106
177
50
3.6V, Figure 2
I
PWRDWN = low
CCZ
_______________________________________________________________________________________
3
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
AC ELECTRICAL CHARACTERISTICS
(V
= V
= +3.0V to +3.6V, 100mV
at 200kHz supply noise, C = 8pF, PWRDWN = high, differential input voltage ⏐V ⏐ =
CC
CCO
P-P L ID
0.1V to 1.2V, input common mode voltage V
= ⏐V /2⏐ to 2.4V - ⏐V /2⏐, T = -40°C to +85°C, unless otherwise noted. Typical
ID ID A
CM
values are at V
= V
= +3.3V, ⏐V ⏐ = 0.2V, V
= 1.25V, T = +25°C.) (Notes 3, 4, 5)
CC
CCO
ID
CM
A
PARAMETER
SYMBOL
CONDITIONS
MIN
3.52
2.2
TYP
5.04
3.15
3.15
3.18
2.12
2.12
7044
3137
1327
685
MAX
6.24
3.9
UNITS
RxOUT
MAX9234/
MAX9236
0.1V
0.9V
Figure 3
to
to
CCO
CCO
Output Rise Time
CLHT
CHLT
ns
,
,
RxCLK OUT
MAX9238
2.2
3.9
RxOUT
1.95
1.3
4.35
2.9
MAX9234/
MAX9236
0.9V
0.1V
Figure 3
CCO
CCO
Output Fall Time
RxCLK OUT
ns
ps
MAX9238
1.3
2.9
8MHz
6600
2560
900
330
16MHz
34MHz
66MHz
Figure 4
(Note 6)
RxIN Skew Margin
RSKM
MAX9238
0.35 x
RCOP
RxCLK OUT High Time
RxCLK OUT Low Time
RCOH
RCOL
RSRC
Figures 5a, 5b
Figures 5a, 5b
Figures 5a, 5b
ns
ns
ns
0.35 x
RCOP
0.30 x
RCOP
RxOUT Setup to RxCLK OUT
0.45 x
RCOP
RxOUT Hold from RxCLK OUT
RxCLK IN to RxCLK OUT Delay
RHRC
RCCD
RPLLS
RPDD
Figures 5a, 5b
Figures 6a, 6b
Figure 7
ns
ns
ns
ns
4.9
6.17
8.1
Deserializer Phase-Locked Loop
Set
32800
x RCIP
Deserializer Power-Down Delay
Figure 8
100
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except V and V
.
TL
TH
Note 2: Maximum and minimum limits overtemperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma.
Note 4: C includes probe and test jig capacitance.
L
Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.
Note 6: RSKM measured with ≤ 150ps cycle-to-cycle jitter on RxCLK IN.
4
_______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Typical Operating Characteristics
(V
= V
= +3.3V, C = 8pF, PWRDWN = high, differential input voltage ⏐V ⏐ = 0.2V, input common-mode voltage V
= 1.2V,
CM
CC
CCO
L
ID
T
A
= +25°C, unless otherwise noted.)
MAX9234/MAX9236
MAX9238
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
100
90
80
70
60
50
40
30
180
160
140
120
100
80
WORST CASE
WORST CASE
27 - 1 PRBS
27 - 1 PRBS
60
40
5
10
15
20
25
30
35
40
10
20
30
40
50
60
70
FREQUENCY (MHz)
FREQUENCY (MHz)
MAX9238
MAX9234/MAX9236
RxOUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
RxOUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
)
)
CCO
CCO
5
4
3
2
1
0
7
6
5
4
3
2
1
CLHT
CLHT
CHLT
CHLT
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Pin Description
PIN
NAME
FUNCTION
1, 2, 4, 5, 45,
46, 47
RxOUT14–RxOUT20 Channel 2 Single-Ended Outputs
3, 25, 32, 38,
44
GND
Ground
6
N.C.
LVDS GND
RxIN0-
No Connection
LVDS Ground
7, 13, 18
8
9
Inverting Channel 0 LVDS Serial-Data Input
Noninverting Channel 0 LVDS Serial-Data Input
Inverting Channel 1 LVDS Serial-Data Input
Noninverting Channel 1 LVDS Serial-Data Input
RxIN0+
RxIN1-
10
11
RxIN1+
LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as
close to LVDS V as possible, with the smallest value capacitor closest to the supply pin.
CC
12
LVDS V
CC
14
15
RxIN2-
RxIN2+
Inverting Channel 2 LVDS Serial-Data Input
Noninverting Channel 2 LVDS Serial-Data Input
Inverting LVDS Parallel Rate Clock Input
Noninverting LVDS Parallel Rate Clock Input
PLL Ground
16
RxCLK IN-
RxCLK IN+
PLL GND
17
19, 21
PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as
close to PLL V as possible, with the smallest value capacitor closest to the supply pin.
CC
20
22
23
PLL V
CC
5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs are
high impedance when PWRDWN = low or open.
PWRDWN
Parallel Rate Clock Single-Ended Output. The MAX9234 has a rising-edge strobe. The
MAX9236/MAX9238 have a falling-edge strobe.
RxCLK OUT
24, 26, 27, 29,
30, 31, 33
RxOUT0–RxOUT6 Channel 0 Single-Ended Outputs
Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as
close to V as possible, with the smallest value capacitor closest to the supply pin.
28, 36, 48
V
CCO
CCO
34, 35, 37, 39,
40, 41, 43
RxOUT7–RxOUT13 Channel 1 Single-Ended Outputs
Digital Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close
to V as possible, with the smallest value capacitor closest to the supply pin.
42
V
CC
CC
6
_______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Table 1. Part Equivalent Table
OPERATING
FREQUENCY (MHz)
PART
EQUIVALENT WITH DCB/NC = HIGH OR OPEN
OUTPUT STROBE
MAX9234
MAX9236
MAX9238
MAX9210
MAX9220
MAX9222
8 to 34
8 to 34
16 to 66
Rising edge
Falling edge
Falling edge
link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V).
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than 1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the dif-
ferential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling.
However, two capacitors—one at the serializer output
and one at the deserializer input—provide protection in
case either end of the cable is shorted to a high voltage.
Detailed Description
The MAX9234/MAX9236 operate at a parallel clock fre-
quency of 8MHz to 34MHz. The MAX9238 operates at a
parallel clock frequency of 16MHz to 66MHz. The tran-
sition times of the single-ended outputs are increased
on the MAX9234/MAX9236 for reduced EMI.
DC Balance
Data coding by the MAX9209/MAX9211/MAX9213/
MAX9215 serializers (which are companion devices to
the MAX9234/MAX9236/MAX9238 deserializers) limits
the imbalance of ones and zeros transmitted on each
channel. If +1 is assigned to each binary 1 transmitted
and -1 is assigned to each binary 0 transmitted, the varia-
tion in the running sum of assigned values is called the
digital sum variation (DSV). The maximum DSV for the
data channels is 10. At most, 10 more zeros than ones,
or 10 more ones than zeros, are transmitted. The maxi-
mum DSV for the clock channel is five. Limiting the DSV
and choosing the correct coupling capacitors maintains
differential signal amplitude and reduces jitter due to
droop on AC-coupled links.
RxIN_ + OR
RxCLK IN+
RIN1
1.2V
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9234/
MAX9236/MAX9238 deserializers whether the data bits
are inverted (see Figure 9). The deserializer restores
the original state of the parallel data. The LVDS clock
signal alternates duty cycles of 4/9 and 5/9, which
maintain DC balance.
RIN1
RxIN_ - OR
RxCLK IN-
Figure 1. LVDS Input Circuit
RCIP
AC-Coupling Benefits
RxCLK OUT
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
the voltage rating of the capacitor. The typical LVDS dri-
ver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0 to
2.4V, allowing approximately 1V common-mode differ-
ence between the driver and receiver on a DC-coupled
ODD RxOUT
EVEN RxOUT
RISING-EDGE STROBE SHOWN.
Figure 2. Worst-Case Test Pattern
_______________________________________________________________________________________
7
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
90%
90%
RxOUT_ OR
RxCLK OUT
10%
10%
RxOUT_ OR
RxCLK OUT
8pF
CLHT
CHLT
Figure 3. Output Load and Transition Times
IDEAL SERIAL BIT TIME
1.3V
1.1V
RxCLK IN
V
= 0
ID
RCCD
1.5V
RSKM
RSKM
RxCLK OUT
IDEAL
IDEAL
Figure 6a. MAX9234 Clock-IN to Clock-OUT Delay
MIN
MAX
INTERNAL STROBE
+
RxCLK IN
V
= 0
Figure 4. LVDS Receiver Input Skew Margin
ID
-
RCCD
RCIP
1.5V
RxCLK OUT
RxCLK OUT
2.0V
2.0V
2.0V
0.8V
0.8V
RCOL
RCOH
RHRC
2.0V
Figure 6b. MAX9236/MAX9238 Clock-IN to Clock-OUT Delay
RSRC
2.0V
0.8V
RxOUT_
0.8V
2V
PWRDWN
Figure 5a. MAX9234 Output Setup/Hold and High/Low Times
3V
RCIP
V
CC
RPLLS
2.0V
0.8V
2.0V
RxCLK OUT
RxOUT_
0.8V
0.8V
RxCLK IN
RCOH
RSRC
RCOL
RHRC
2.0V
0.8V
2.0V
0.8V
RxCLK OUT
HIGH-Z
Figure 5b. MAX9236/MAX9238 Output Setup/Hold and High/Low
Times
Figure 7. Phase-Locked Loop Set Time
8
_______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Applications Information
PWRDWN
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
0.8V
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
RxCLK IN
RPDD
acceptable level.
RxOUT_
RxCLK OUT
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R ), the LVDS driver
HIGH-Z
T
output resistor (R ), and the series AC-coupling capac-
O
itors (C). The RC time constant for two equal-value
Figure 8. Power-Down Delay
series capacitors is (C x (R + R )) / 2 (Figure 10). The
T
O
RC time constant for four equal-value series capacitors
is (C x (R + R )) / 4 (Figure 11).
MAX9234/MAX9236/MAX9238 vs.
MAX9210/MAX9220/MAX9222
T
O
R is required to match the transmission line imped-
T
The MAX9234/MAX9236/MAX9238 operate in DC-bal-
ance mode only. Pinouts are the same as the
MAX9210/MAX9220/MAX9222 except that pin 6 on the
MAX9234/MAX9236/MAX9238 is no connect (N.C.). DC
balance allows AC-coupling with series capacitors. The
MAX9234/MAX9236/MAX9238 are hot-swappable and
the input frequency can be changed on the fly, but oth-
erwise the specifications and functionality are the same
as the MAX9210/MAX9220/MAX9222 operating in DC-
balance mode. See Table 1.
ance (usually 100Ω) and R is determined by the LVDS
O
driver design (the minimum differential output resis-
tance of 78Ω for the MAX9209/MAX9211/MAX9213/
MAX9215 serializers is used in the following example).
This leaves the capacitor selection to change the sys-
tem time constant.
+
-
RxCLK IN
CYCLE N - 1
CYCLE N
CYCLE N + 1
DCA2
RxIN2
DCB2
TxIN20 TxIN19 TxIN18
TxIN13 TxIN12 TxIN11
TxIN17 TxIN16 TxIN15
TxIN14
TxIN7
TxIN0
DCA2
DCA1
DCA0
DCB2
DCB1
DCB0
TxIN20
TxIN13
TxIN6
TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
DCA1
RxIN1
DCB1
DCB0
TxIN10
TxIN3
TxIN9
TxIN2
TxIN8
TxIN1
TxIN12 TxIN11 TxIN10
TxIN9
TxIN2
TxIN8
TxIN1
TxIN7
TxIN0
DCA0
RxIN0
TxIN6
TxIN5
TxIN4
TxIN5
TxIN4
TxIN3
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
Figure 9. Deserializer Serial Input
_______________________________________________________________________________________
9
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
MAX9209
MAX9211
MAX9213
MAX9215
MAX9234
MAX9236
MAX9238
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
RxIN
7
7
7
7
7
7
100Ω
100Ω
100Ω
100Ω
(7 + 2):1
(7 + 2):1
(7 + 2):1
PLL
1:(9 - 2)
1:(9 - 2)
1:(9 - 2)
PLL
TxIN
RxOUT
PWRDWN
TxCLK IN
PWRDWN
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 10. Two Capacitors per Link, AC-Coupled
MAX9209
MAX9211
MAX9213
MAX9215
MAX9234
MAX9236
MAX9238
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
TxOUT
RxIN
7
7
7
7
100Ω
(7 + 2):1
1:(9 - 2)
7
100Ω
100Ω
100Ω
TxIN
(7 + 2):1
(7 + 2):1
PLL
1:(9 - 2)
1:(9 - 2)
PLL
RxOUT
7
PWRDWN
TxCLK IN
PWRDWN
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 11. Four Capacitors per Link, AC-Coupled
10 ______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
pullup resistor between the noninverting input and V
,
CC
and a 10kΩ 1% pulldown resistor between the invert-
ing input and ground. These bias resistors, along with
the 100Ω 1% tolerance termination resistor, provide
+15mV of differential input.
C = - (2 x t x DSV) / (ln (1 - D) x (R + R )) (Eq 1)
B
T
O
where:
C = AC-coupling capacitor (F).
Unused LVDS Data Inputs
t = bit time (s).
B
At each unused LVDS data input, pull the inverting input
DSV = digital sum variation (integer).
ln = natural log.
up to V using a 10kΩ resistor, and pull the noninverting
CC
input down to ground using a 10kΩ resistor. Do not con-
nect a termination resistor. The pullup and pulldown resis-
tors drive the corresponding outputs low and prevent
switching due to noise.
D = droop (% of signal amplitude).
R = termination resistor (Ω).
T
O
R
= output resistance (Ω).
Equation 1 is for two series capacitors (Figure 10). The
PWRDWN
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
bit time (t ) is the period of the parallel clock divided by
B
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 11).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x t x DSV) / (ln (1 - D) x (R + R ))
B
T
O
C = - (2 x 13.9ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.0773µF
Jitter due to droop is proportional to the droop and
transition time:
Input Clock and PLL Lock Time
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock-time specification. When the PLL is locking, the
outputs are low.
t = t x D (Eq 2)
J
T
where:
t = jitter (s).
J
t = transition time (s) (0 to 100%).
T
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
t = 1ns x 0.02
J
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
t = 20ps
J
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
V
, V
CC CCO
, PLL V , and LVDS V
pin with high-fre-
CC
CC
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Equation 1 altered for four series capacitors (Figure 11) is:
C = - (4 x t x DSV) / (ln (1 - D) x (R + R )) (Eq 3)
B
T
O
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Input Bias and Frequency Detection
The inverting and noninverting LVDS inputs are internally
connected to +1.2V through 42kΩ (min) to provide bias-
ing for AC-coupling (Figure 1). A frequency-detection
circuit on the clock input detects when the input is not
switching, or is switching at low frequency. In this case,
all outputs are driven low. To prevent switching due to
noise when the clock input is not driven, bias the clock
input to differential +15mV by connecting a 10kΩ 1%
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
______________________________________________________________________________________ 11
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
R1
1MΩ
R2
1.5kΩ
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
ESD Protection
The MAX9234/MAX9236/MAX9238 ESD tolerance is
rated for IEC 61000-4-2 Human Body Model and ISO
10605 standards. IEC 61000-4-2 and ISO 10605 specifiy
ESD tolerance for electronic systems. The Human Body
DEVICE
UNDER
TEST
C
S
100pF
STORAGE
CAPACITOR
SOURCE
Model discharge components are C = 100pF and R =
S
D
1.5kΩ (Figure 12). For the Human Body Model, all pins
Figure 12. Human Body ESD Test Circuit
are rated for 5kV contact discharge. The ISO 10605 dis-
charge components are C = 330pF and R = 2kΩ
S
D
(Figure 13). For ISO 10605, the LVDS outputs are rated
for 8kV contact and 25kV air discharge. The IEC
R1
R2
2kΩ
50Ω TO 100Ω
61000-4-2 discharge components are C = 150pF and
S
R
= 330Ω (Figure 14). For IEC 61000-4-2, the LVDS
D
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
inputs are rated for 8kV Contact Discharge and 15kV
Air-Gap Discharge.
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND.
SOURCE
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
Figure 13. ISO 10605 Contact Discharge ESD Test Circuit
R
D
50Ω TO 100Ω
330Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
150pF
STORAGE
CAPACITOR
V
Output Supply and Power Dissipation
CCO
The outputs have a separate supply (V
) for interfacing
SOURCE
CCO
to systems with 1.8V to 5V nominal input-logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for V
= 3.6V with 8pF load at several
CCO
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
tal supply current for V
other than 3.6V with the same
CCO
The incremental current is added to (for V
> 3.6V)
CCO
8pF load and worst-case pattern can be calculated using:
or subtracted from (for V
< 3.6V) the DC Electrical
CCO
I = C V 0.5f x 21 (data outputs)
I
T I
C
Characteristics table maximum supply current. The
internal output buffer capacitance is C = 6pF. The
+ C V f x 1 (clock output)
T I C
INT
worst-case pattern-switching frequency of the data out-
puts is half the switching frequency of the output clock.
where:
I = incremental supply current.
I
C = total internal (C ) and external (C ) load capaci-
T
INT
L
In the following example, the incremental supply current is
tance.
calculated for V
= 5.5V, f = 34MHz, and C = 8pF:
C L
CCO
V = incremental supply voltage.
I
V = 5.5V - 3.6V = 1.9V
I
f = output clock-switching frequency.
C
C = C
T
+ C = 6pF + 8pF = 14pF
L
INT
12 ______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
where:
Rising- or Falling-Edge Output Strobe
The MAX9234 has a rising-edge output strobe, which
I = C V 0.5F x 21 (data outputs) + C V f x 1 (clock
I
T I
C
T I C
latches the parallel output data into the next chip on the
rising edge of RxCLK OUT. The MAX9236/MAX9238
have a falling-edge output strobe, which latches the
parallel output data into the next chip on the falling
edge of RxCLK OUT. The deserializer output strobe
polarity does not need to match the serializer input
strobe polarity. A deserializer with rising- or falling-
edge output strobe can be driven by a serializer with a
rising-edge input strobe.
output).
I = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
I
34MHz).
I = 9.5mA + 0.9mA = 10.4mA.
I
The maximum supply current in DC-balanced mode for
V
= V
= 3.6V at f = 34MHz is 106mA (from the
CCO C
CC
DC Electrical Characteristics table). Add 10.4mA to get
the total approximate maximum supply current at V
CCO
= 5.5V and V
= 3.6V.
CC
Pin Configuration
If the output supply voltage is less than V
= 3.6V,
CCO
the reduced supply current can be calculated using the
same formula and method.
TOP VIEW
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power-dissipation rating. Do not exceed
the maximum package power-dissipation rating. See
the Absolute Maximum Ratings for maximum package
power-dissipation capacity and temperature derating.
RxOUT17
RxOUT18
GND
1
2
3
4
5
6
7
8
9
48
V
CCO
47 RxOUT16
46 RxOUT15
45 RxOUT14
44 GND
RxOUT19
RxOUT20
N.C.
43 RxOUT13
Functional Diagram
LVDS GND
RxIN0-
42
V
CC
41 RxOUT12
40 RxOUT11
39 RxOUT10
38 GND
DATA
CHANNEL 0
LVDS DATA
RECEIVER 0
RxIN0+
MAX9234
MAX9236
MAX9238
RxOUT0–6
RxIN1- 10
RxIN1+ 11
RxIN0+
RxIN0-
SERIAL-TO-
PARALLEL
CONVERTER
STROBE
STROBE
STROBE
LVDS V
12
37 RxOUT9
CC
DATA
CHANNEL 1
LVDS GND 13
RxIN2- 14
36
V
CCO
LVDS DATA
RECEIVER 1
35 RxOUT8
34 RxOUT7
33 RxOUT6
32 GND
RxOUT7–13
RxOUT14–20
RxCLK OUT
RxIN1+
RxIN1-
SERIAL-TO-
PARALLEL
CONVERTER
RxIN2+ 15
RxCLK IN- 16
RxCLK IN+ 17
LVDS GND 18
PLL GND 19
DATA
CHANNEL 2
LVDS DATA
RECEIVER 2
31 RxOUT5
30 RxOUT4
29 RxOUT3
RxIN2+
RxIN2-
SERIAL-TO-
PARALLEL
CONVERTER
PLL V
20
CC
PLL GND 21
PWRDWN 22
RxCLK OUT 23
RxOUT0 24
28
V
CCO
27 RxOUT2
26 RxOUT1
25 GND
LVDS CLOCK
RECEIVER
RxCLK IN+
RxCLK IN-
REFERENCE
CLOCK
GENERATOR
9x
PLL
TSSOP
PWRDWN
Chip Information
MAX9234 TRANSISTOR COUNT: 14,104
MAX9236 TRANSISTOR COUNT: 14,104
MAX9238 TRANSISTOR COUNT: 14,104
PROCESS: CMOS
______________________________________________________________________________________ 13
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
N
MARKING
AAA A
E
H
1
2
3
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
b
A1
A2
A
C
L
c
e
END VIEW
SEATING
PLANE
D
SIDE VIEW
b
(
)
PARTING
LINE
b1
0.25
WITH PLATING
L
DETAIL A
c1
c
NOTES:
1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH.
BASE METAL
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE.
3. CONTROLLING DIMENSION: MILLIMETERS.
SECTION C-C
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L).
5. "N" REFERS TO NUMBER OF LEADS.
6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL
PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE
FROM (-C-) IN THE DIRECTION INDICATED.
7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
PACKAGE OUTLINE,
48 & 56L TSSOP, 6.1mm BODY
8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
1
21-0155
C
1
14 ______________________________________________________________________________________
Hot-Swappable, 21-Bit, DC-Balanced LVDS
Deserializers
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
4/05
Initial release
Added IEC 61000-4-2 ESD Performance; various style changes
—
10/07
1, 2, 4, 5, 6, 12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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