MAX9242EUM [MAXIM]
21-Bit Deserializers with Programmable Spread Spectrum and DC Balance; 21位解串器，提供可编程扩频和直流平衡
| 型号： | MAX9242EUM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 21-Bit Deserializers with Programmable Spread Spectrum and DC Balance |
| 文件： | 总22页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3954; Rev 0; 1/06
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
General Description
Features
The MAX9242/MAX9244/MAX9246 deserialize three
LVDS serial-data inputs into 21 single-ended LVCMOS/
LVTTL outputs. A separate parallel-rate LVDS clock pro-
vides the timing for deserialization. The MAX9242/
MAX9244/MAX9246 feature spread-spectrum capability,
allowing the output data and clock frequency to spread
over a specified range to reduce EMI. The single-ended
data and clock outputs are programmable for a frequency
spread of 2ꢀ, 4ꢀ, or no spread. The spread-spectrum
function is also available when the MAX9242/MAX9244/
MAX9246 operate in non-DC-balanced mode. The modu-
lation rate of the spread is 32kHz for a 33MHz LVDS clock
input and scales linearly with frequency. The single-
ended outputs have a separate supply, allowing +1.8V to
+5V output logic levels.
♦ Programmable ±±4% ±ꢀ4% or ꢁꢂꢂ FꢃreaꢄꢅFꢃepꢆrtm
ꢁtꢆꢃtꢆ for Reꢄtpeꢄ EMI
♦ Programmable DCꢅBalanpeꢄ or NonꢅDCꢅBalanpeꢄ
Moꢄes
♦ DC Balanpe Allows ACꢅCotꢃling for Wiꢄer Inꢃtꢆ
CommonꢅMoꢄe Volꢆage Range
♦ Fꢃreaꢄ Fꢃepꢆrtm ꢁꢃeraꢆes in DCꢅBalanpeꢄ or
NonꢅDCꢅBalanpeꢄ Moꢄe
♦ π / ± Deskew by ꢁversamꢃling (MAX9ꢀ±ꢀ/MAX9ꢀ±±)
♦ 16MHzꢅꢆoꢅ3±MHz (DCꢅBalanpeꢄ) anꢄ ꢀ0MHzꢅꢆoꢅ
±0MHz (NonꢅDCꢅBalanpeꢄ) ꢁꢃeraꢆion
(MAX9ꢀ±ꢀ/MAX9ꢀ±±)
The MAX9242/MAX9244/MAX9246 feature program-
mable DC balance, allowing isolation between a serial-
izer and deserializer using AC-coupling. The MAX9242/
MAX9244/MAX9246 operate with the MAX9209/
MAX9213 serializers and are available with a rising-
edge strobe (MAX9242) or falling-edge strobe
(MAX9244/MAX9246). The LVDS inputs meet ISO
10605 ESD specifications with 30kV Air-ꢁap
Discharge and 6kV Contact Discharge ratings.
♦ 6MHzꢅꢆoꢅ18MHz (DCꢅBalanpeꢄ) anꢄ 8MHzꢅꢆoꢅꢀ0MHz
(NonꢅDCꢅBalanpeꢄ) ꢁꢃeraꢆion (MAX9ꢀ±6)
♦ RisingꢅEꢄge (MAX9ꢀ±ꢀ) or ꢂallingꢅEꢄge
(MAX9ꢀ±±/MAX9ꢀ±6) ꢁtꢆꢃtꢆ Fꢆrobe
♦ HighꢅImꢃeꢄanpe ꢁtꢆꢃtꢆs when PWRDWN is Low
Allow ꢁtꢆꢃtꢆ Btsing
♦ ꢂailꢅFafe Inꢃtꢆs in NonꢅDCꢅBalanpeꢄ Moꢄe
The MAX9242/MAX9244/MAX9246 are available in a
48-pin TSSOP package and operate over the -40°C to
+85°C temperature range.
♦ Feꢃaraꢆe ꢁtꢆꢃtꢆ Ftꢃꢃly Allows Inꢆerfape ꢆo +1.8V%
+ꢀ.5V% +3.3V% anꢄ +5V Logip
♦ LVDF Inꢃtꢆs Meeꢆ IFꢁ 10605 EFD Proꢆepꢆion aꢆ
±30kV Airꢅ-aꢃ Dispharge anꢄ ±6kV Conꢆapꢆ
Dispharge
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
♦ LVDF Inꢃtꢆs Meeꢆ IEC 61000ꢅ±ꢅꢀ Level ± EFD
Proꢆepꢆion aꢆ ±15kV Airꢅ-aꢃ Dispharge anꢄ ±8kV
Conꢆapꢆ Dispharge
Laser Printers
♦ LVDF Inꢃtꢆs Conform ꢆo ANFI TIA/EIAꢅ6±± Fꢆanꢄarꢄ
♦ +3.3V Main Power Ftꢃꢃly
Selector Guide
ꢂREQUENCY RAN-E
Ordering Information
FTRꢁBE
ED-E
ꢁVERꢅ
FAMPLIN-
NꢁNꢅDC
DC
PART
BALANCE BALANCE
PK-
PART
TEMP RAN-E PINꢅPACKA-E
(MHz)
(MHz)
CꢁDE
U48-1
U48-1
U48-1
MAX9242
MAX9244
MAX9246
Rising
Falling
Falling
Yes
Yes
No
20 to 40
20 to 40
8 to 20
16 to 34
16 to 34
6 to 18
MAX9ꢀ±ꢀEUM -40°C to +85°C 48 TSSOP
MAX9ꢀ±±EUM -40°C to +85°C 48 TSSOP
MAX9ꢀ±6EUM -40°C to +85°C 48 TSSOP
Devices are available in lead-free packaging. Specify lead free by
adding a + symbol at the end of the part number when ordering.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
ABFꢁLUTE MAXIMUM RATIN-F
(All voltages referenced to ꢁND.)
IEC 61000-4-2 (R = 330Ω, C = 150pF)
D S
LVDS Inputs to ꢁND (Air-ꢁap Discharge)..................... 15kV
LVDS Inputs to ꢁND (Contact Discharge)....................... 8kV
V
V
, LVDSV , PLLV .......................................-0.5V to +4.0V
CC
CC
CC
......................................................................-0.5V to +6.0V
CCO
RxIN_, RxCLKIN_ ..................................................-0.5V to +4.0V
PWRDWN ..............................................................-0.5V to +6.0V
ISO 10605 (R = 2.0kΩ, C = 330pF)
D S
LVDS Inputs to ꢁND (Air-ꢁap Discharge)..................... 30kV
LVDS Inputs to ꢁND (Contact Discharge)....................... 6kV
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
SSꢁ, DCB...................................................-0.5V to (V
+ 0.5V)
+ 0.5V)
CC
RxOUT_, RxCLKOUT ...............................-0.5V to (V
CCO
Continuous Power Dissipation (T = +70°C)
A
48-Pin TSSOP (derate 16mW/°C above +70°C) ........1282mW
ESD Protection
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
All Pins to ꢁND ............................................................. 2.5kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERIFTICF
(V
= LVDSV
= PLLV
= +3.0V to +3.6V, V
= +3.0V to +5.5V, PWRDWN = high; SSꢁ = high, open, or low; DCB = high or
CC
CC
CC
CCO
low, differential input voltage |V | = 0.05V to 1.2V, input common-mode voltage V
= |V / 2| to 2.4V - |V / 2|, unless otherwise
ID ID
= +1.25V, T = +25°C.) (Notes 1, 2)
CM A
ID
CM
noted. Typical values are at V
= V
= LVDSV
= PLLV
= +3.3V, |V | = 0.2V, V
CC
CCO
CC
CC
ID
PARAMETER
FYMBꢁL
CꢁNDITIꢁNF
MIN
TYP
MAX UNITF
PꢁWER FUPPLY
V
,
CC
LVDSV
PLLV
,
Power-Supply Range
Output-Supply Range
3.0
1.8
3.6
V
V
CC
CC
V
5.5
61
CCO
16MHz
34MHz
20MHz
33MHz
40MHz
16MHz
34MHz
20MHz
33MHz
40MHz
45
72
59
80
93
57
93
71
98
115
DC-balanced
mode (SSꢁ = low)
96
79
C = 8pF,
L
Non-DC-balanced
mode (SSꢁ = low)
106
123
78
worst-case pattern,
= V = 3.0V
V
CC
CCO
Worst-Case Supply Current
I
mA
CCW
to 3.6V, Figure 2
(MAX9242,
MAX9244)
DC-balanced mode
(SSꢁ = high or open)
125
96
Non-DC-balanced
mode
(SSꢁ = high or open)
129
145
ꢀ
_______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
DC ELECTRICAL CHARACTERIFTICF (ponꢆinteꢄ)
(V
= LVDSV
= PLLV
= +3.0V to +3.6V, V
ID
= +3.0V to +5.5V, PWRDWN = high; SSꢁ = high, open, or low; DCB = high or
CC
CC
CC
CCO
low, differential input voltage |V | = 0.05V to 1.2V, input common-mode voltage V
= |V / 2| to 2.4V - |V / 2|, unless otherwise
ID ID
CM
noted. Typical values are at V
= V
= LVDSV
= PLLV
= +3.3V, |V | = 0.2V, V
= +1.25V, T = +25°C.) (Notes 1, 2)
CM A
CC
CCO
CC
CC
ID
PARAMETER
FYMBꢁL
CꢁNDITIꢁNF
MIN
TYP
27
30
43
33
37
52
32
38
57
41
46
66
MAX UNITF
6MHz
8MHz
41
45
61
47
52
DC-balanced
mode (SSꢁ = low)
18MHz
8MHz
Non-DC-balanced
mode (SSꢁ = low)
C = 8pF,
L
10MHz
20MHz
6MHz
worst-case pattern,
= V = 3.0V
73
Worst-Case Supply Current
I
V
mA
47
CCW
CC
CCO
to 3.6V, Figure 2
(MAX9246)
DC-balanced mode
(SSꢁ = high or open)
8MHz
57
81
58
65
92
18MHz
8MHz
Non-DC-balanced
mode
(SSꢁ = high or open)
10MHz
20MHz
Power-Down Supply Current
I
PWRDWN = low
50
µA
CCZ
5VꢅTꢁLERANT Lꢁ-IC INPUT (PWRDWN)
High-Level Input Voltage
Low-Level Input Voltage
Input Current
V
2.0
-0.3
-20
5.5
+0.8
+20
V
V
IH
V
IL
IN
I
PWRDWN = high or low level
= -18mA
µA
V
Input Clamp Voltage
V
I
CL
-1.5
CL
THREEꢅLEVEL Lꢁ-IC INPUTF (DCB% FF-)
V
+
CC
0.3
High-Level Input Voltage
V
2.5
V
IH
DCB, SSꢁ open or connected to a driver with
output in high-impedance state (Note 3)
Mid-Level Input Current
Low-Level Input Voltage
Input Current
I
-10
-0.3
-20
+10
+0.8
+20
µA
V
IM
V
IL
IN
DCB, SSꢁ = high or low level,
PWRDWN = high or low
I
µA
V
Input Clamp Voltage
V
I
CL
= -18mA
-1.5
CL
FIN-LEꢅENDED ꢁUTPUTF (RxꢁUT_% RxCLKꢁUT)
V
CCO
- 0.1
I
I
= -100µA
OH
V
CCO
High-Level Output Voltage
Low-Level Output Voltage
V
RxCLKOUT (Note 4)
V
V
OH
- 0.25
= -2mA
OH
V
CCO
RxOUT_
- 0.43
I
I
= 100µA
= 2mA
0.1
0.2
OL
V
RxCLKOUT (Note 4)
RxOUT_
OL
OL
0.26
_______________________________________________________________________________________
3
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
DC ELECTRICAL CHARACTERIFTICF (ponꢆinteꢄ)
(V
= LVDSV
= PLLV
= +3.0V to +3.6V, V
ID
= +3.0V to +5.5V, PWRDWN = high; SSꢁ = high, open, or low; DCB = high or
CC
CC
CC
CCO
low, differential input voltage |V | = 0.05V to 1.2V, input common-mode voltage V
= |V / 2| to 2.4V - |V / 2|, unless otherwise
ID ID
CM
noted. Typical values are at V
= V
= LVDSV
= PLLV
= +3.3V, |V | = 0.2V, V
= +1.25V, T = +25°C.) (Notes 1, 2)
CM A
CC
CCO
CC
CC
ID
PARAMETER
FYMBꢁL
CꢁNDITIꢁNF
MIN
-30
-10
-5
TYP
MAX UNITF
High-Impedance Output Current
I
PWRDWN = low, V
= -0.3V to (V + 0.3V)
CCO
+30
-40
-20
-75
-37
µA
OZ
OS
OUT
RxCLKOUT (Note 4)
RxOUT_
V
V
= 3.0V to 3.6V,
CCO
OUT
= 0V
Output Short-Circuit Current
(Note 5)
I
mA
RxCLKOUT (Note 4)
RxOUT_
-28
-13
VCCO = 4.5V to 5.5V,
VOUT = 0V
LVDF INPUTF (RxIN_% RxCLKIN_)
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
(Note 6)
50
mV
mV
µA
µA
TH
V
(Note 6)
-50
-25
-40
TL
I
, I
PWRDWN = high or low
+25
+40
IN+ IN-
Power-Off Input Current
I
, I
V
= V
= 0V or open
CCO
INO+ INO-
CC
PWRDWN = high or low, V
open, Figure 1
= V
= V
= 0V or
= 0V or
CC
CC
CCO
CCO
Input Resistor 1
R
R
42
78
kΩ
kΩ
IN1
IN2
PWRDWN = high or low, V
open, Figure 1
Input Resistor 2
246
410
AC ELECTRICAL CHARACTERIFTICF
(V
= LVDSV
= PLLV
= +3.0V to +3.6V, V
= +3.0V to +3.6V, C = 8pF, PWRDWN = high; SSꢁ = high, open, or low;
CC
CC
CC
CCO L
DCB = high or low, differential input voltage |V | = 0.1V to 1.2V, input common-mode voltage V
= |V / 2| to 2.4V - |V / 2|, unless
ID ID
= +1.25V, T = +25°C.) (Notes 6, 7, 8)
ID
CM
otherwise noted. Typical values are at V = V
= LVDSV = PLLV = +3.3V, |V | = 0.2V, V
CC
CCO
CC
CC
ID
CM A
PARAMETER
Output Rise Time
FYMBꢁL
CꢁNDITIꢁNF
MIN
TYP
4.7
MAX
6.5
UNITF
RxOUT_
2.9
2.0
0.1 x V
Figure 3
to 0.9 x V
,
CCO
CCO
CLHT
CHLT
ns
RxCLKOUT
RxOUT_
RxCLKOUT
16MHz
3.3
4.1
2.1
3.0
4.2
0.9 x V
Figure 3
to 0.1 x V
,
CCO
CCO
Output Fall Time
ns
ps
1.10
2560
900
2500
960
1.94
3142
1386
3164
1371
2.70
DC-balanced mode,
Figure 4
34MHz
RxIN Skew Margin (Note 9)
RSKM
20MHz
Non-DC-balanced mode,
Figure 4
40MHz
0.35 x
RCOP
RxCLKOUT High Time
RCOH
RCOL
RSRC
RHRC
RCCD
Figures 5a, 5b
ns
ns
ns
ns
ns
0.35 x
RCOP
RxCLKOUT Low Time
Figures 5a, 5b
0.3 x
RCOP
RxOUT Setup to RxCLKOUT
RxOUT Hold from RxCLKOUT
RxCLKIN to RxCLKOUT Delay
Figures 5a, 5b
0.45 x
RCOP
Figures 5a, 5b
4.5 +
6.5 +
8.2 +
SSꢁ = low, Figures 6a, 6b
(RCIP / 2) (RCIP / 2) (RCIP / 2)
±
_______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
AC ELECTRICAL CHARACTERIFTICF (ponꢆinteꢄ)
(V
= LVDSV
= PLLV
= +3.0V to +3.6V, V
= +3.0V to +3.6V, C = 8pF, PWRDWN = high; SSꢁ = high, open, or low;
CC
CC
CC
CCO L
DCB = high or low, differential input voltage |V | = 0.1V to 1.2V, input common-mode voltage V
= |V / 2| to 2.4V - |V / 2|, unless
ID ID
ID
CM
otherwise noted. Typical values are at V = V
= LVDSV = PLLV = +3.3V, |V | = 0.2V, V
= +1.25V, T = +25°C.) (Notes 6, 7, 8)
CM A
CC
CCO
CC
CC
ID
PARAMETER
FYMBꢁL
CꢁNDITIꢁNF
MIN
TYP
MAX
UNITF
ns
Deserializer Phase-Locked-
Loop Set
65,600 x
RCIP
RPLLS
RPDD
Figure 7
Figure 8
Deserializer Power-Down Delay
100
ns
Deserializer Phase-Locked-
Loop Set from SSꢁ Change
32,800 x
RCIP
RPLLS2 Figure 9
ns
Maximum output
frequency
f
f
f
f
f
f
f
f
f
f
f
f
f
f
RxCLKIN
+ 3.6ꢀ
RxCLKIN
+ 4.0ꢀ
RxCLKIN
+ 4.4ꢀ
SSꢁ = high,
Figure 10
Minimum output
frequency
RxCLKIN
- 4.4ꢀ
RxCLKIN
- 4.0ꢀ
RxCLKIN
- 3.6ꢀ
Spread-Spectrum Output
Frequency
f
MHz
Maximum output
frequency
RxCLKOUT
RxCLKIN
+ 1.8ꢀ
RxCLKIN
+ 2.0ꢀ
RxCLKIN
+ 2.2ꢀ
SSꢁ = open,
Figure 10
Minimum output
frequency
RxCLKIN
- 2.2ꢀ
RxCLKIN
- 2.0ꢀ
RxCLKIN
- 1.8ꢀ
SSꢁ = low
Figure 10
RxCLKIN
RxCLKIN
Spread-Spectrum Modulation
Frequency
f
/
RxCLKIN
1016
f
Hz
SSM
Noꢆe 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except V and V
.
TL
TH
Noꢆe ꢀ: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Noꢆe 3: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than 10µA.
Noꢆe ±: RxCLKOUT limits are scaled based on RxOUT_ measurements, design, and characterization data.
Noꢆe 5: One output shorted at a time. Current out of the pin.
Noꢆe 6: V , V , and AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set
TH TL
at 6 sigma.
Noꢆe 7: C includes probe and test jig capacitance.
L
Noꢆe 8: RCIP is the period of RxCLKIN. RCOP is the period of RxCLKOUT.
Noꢆe 9: RSKM is measured with less than 150ps cycle-to-cycle jitter on RxCLKIN.
_______________________________________________________________________________________
5
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Test Circuits/Timing Diagrams
V
CC
R
FAIL-SAFE
IN2
COMPARATOR
RCOP
RxIN_ + OR
RxCLKIN+
RxIN_ + OR
RxCLKIN+
RxCLKOUT
V
- 0.3V
CC
R
R
R
R
IN1
IN1
IN1
IN1
1.2V
ODD RxOUT
EVEN RxOUT
RxIN_ - OR
RxCLKIN-
RxIN_ - OR
RxCLKIN-
NON-DC-BALANCED MODE
DC-BALANCED MODE
Figure 2. Worst-Case Test Pattern
Figure 1. LVDS Input Circuits
90%
90%
RxOUT_ OR
RxCLKOUT
10%
10%
RxOUT_ OR
RxCLKOUT
8pF
CLHT
CHLT
Figure 3. Output Load and Transition Times
IDEAL SERIAL BIT TIME
1.3V
1.1V
RCOP
RxCLK OUT
RxOUT_
2.0V
2.0V
2.0V
0.8V
0.8V
RCOL
RCOH
RHRC
2.0V
RSKM
RSKM
RSRC
IDEAL
IDEAL
2.0V
0.8V
MIN
MAX
0.8V
INTERNAL STROBE
Figure 4. LVDS Receiver Input Skew Margin
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
6
_______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Test Circuits/Timing Diagrams (continued)
RCOP
RCIP
RxCLKIN
V
= 0V
ID
2.0V
0.8V
2.0V
RxCLKOUT
RxOUT_
0.8V
0.8V
RCCD
RCOH
RSRC
RCOL
RHRC
1.5V
RxCLKOUT
2.0V
0.8V
2.0V
0.8V
Figure 6a. Clock-IN to Clock-OUT Delay (MAX9244/MAX9246)
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
2V
PWRDWN
RCIP
+
3V
RxCLKIN
V
ID
= 0
-
V
CC
RPLLS
RCCD
RxCLKIN
RxCLKOUT
1.5V
1.5V
Figure 6b. Clock-IN to Clock-OUT Delay (MAX9242)
RxCLKOUT
HIGH IMPEDANCE
Figure 7. Phase-Locked-Loop Set Time
PWRDWN
1.5V
RxCLKIN
RPDD
RxOUT_
RxCLKOUT
1.5V
HIGH IMPEDANCE
Figure 8. Power-Down Delay
_______________________________________________________________________________________
7
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Test Circuits/Timing Diagrams (continued)
2.5V
0.8V
SSG
OPEN OR LESS THAN 10µA LEAKAGE
RPLLS2
RxCLKIN_
RxCLKOUT
RxOUT_
TIMING SHOWN FOR FALLING-EDGE STROBE (MAX9244/MAX9246)
=
PWRDWN HIGH
Figure 9. Phase-Locked-Loop Set Time from SSG Change
FREQUENCY
1 / f
SSM
f
(MAX)
RxCLKOUT
f
TIME
RxCLKIN
f
(MIN)
RxCLKOUT
Figure 10. Simplified Modulation Profile
8
_______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Typical Operating Characteristics
(V
CC
= PLLV
= LVDSV
= V
= +3.3V, C = 8pF, PWRDWN = high, differential input voltage |V | = 0.2V, input common-mode
CC
CC
CCO
L
ID
voltage V
= 1.2V, T = +25°C, MAX9244, unless otherwise noted.)
CM
A
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
(NON-DC-BALANCED MODE, NO SPREAD)
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
(DC-BALANCED MODE, NO SPREAD)
(DC-BALANCED MODE, 2% SPREAD)
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
WORST-CASE PATTERN
WORST-CASE PATTERN
WORST-CASE PATTERN
7
2 - 1 PRBS
7
2 - 1 PRBS
7
2 - 1 PRBS
15
20
25
30
35
40
15
20
25
30
35
40
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
WORST-CASE AND PRBS SUPPLY CURRENT
vs. FREQUENCY
RxOUT_TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (V
)
CCO
(DC-BALANCED MODE, 4% SPREAD)
14
100
90
80
70
60
50
40
30
12
10
8
WORST-CASE PATTERN
C
LHT
6
7
2 - 1 PRBS
4
2
C
HLT
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT SUPPLY VOLTAGE (V)
15
20
25
30
35
40
FREQUENCY (MHz)
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, NO SPREAD)
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 2% SPREAD)
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 4% SPREAD)
20
10
20
10
20
10
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
-70
-80
-70
-80
-70
-80
30
33
36
30
33
36
30
33
36
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
9
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Typical Operating Characteristics (continued)
(V
CC
= PLLV
= LVDSV
= V
= +3.3V, C = 8pF, PWRDWN = high, differential input voltage |V | = 0.2V, input common-mode
CC
CC
CCO
L
ID
voltage V
= 1.2V, T = +25°C, MAX9244, unless otherwise noted.)
CM
A
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, NO SPREAD)
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 2% SPREAD)
RxCLKOUT POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 4% SPREAD)
20
10
20
10
20
10
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
-70
-70
-80
-70
-80
-80
14
16
18
14
15.0
7
16
18
14
16
18
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, NO SPREAD)
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 2% SPREAD)
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 33MHz, 4% SPREAD)
20
10
20
10
20
10
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
-70
-70
-80
-70
-80
-80
15.0
16.5
18.0
16.5
18.0
15.0
16.5
18.0
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, NO SPREAD)
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 2% SPREAD)
RxOUT_ POWER SPECTRUM
vs. FREQUENCY
(RxCLKIN_ = 16MHz, 4% SPREAD)
20
10
20
10
20
10
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
RESOLUTION BW = 100kHz
VIDEO BW = 100kHz
ATTENUATION = 50dB
-70
-70
-80
-70
-80
-80
7
8
9
8
9
7
8
9
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
10 ______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Pin Description
PIN
1
NAME
ꢂUNCTIꢁN
RxOUT17
RxOUT18
Channel 2 Single-Ended Outputs
ꢁround
2
3, 25, 32,
38, 44
ꢁND
4
5
RxOUT19
RxOUT20
Channel 2 Single-Ended Outputs
Three-Level-Logic, Spread-Spectrum ꢁenerator Control Input. SSꢁ selects the frequency spread of
RxCLKOUT relative to RxCLKIN (see Table 3).
6
7
SSꢁ
DCB
Three-Level-Logic, DC-Balance Control Input. DCB selects DC-balanced, non-DC-balanced, or reserved
operation (see Table 1).
8
9
RxIN0-
RxIN0+
RxIN1-
RxIN1+
Inverting Channel 0 LVDS Serial-Data Input
Noninverting Channel 0 LVDS Serial-Data Input
Inverting Channel 1 LVDS Serial-Data Input
Noninverting Channel 1 LVDS Serial-Data Input
10
11
LVDS Supply Voltage. Bypass LVDSV to ꢁND with 0.1µF and 0.001µF capacitors in parallel as close to
CC
the pin as possible.
12
LVDSV
CC
13, 18
14
LVDSꢁND LVDS ꢁround
RxIN2-
Inverting Channel 2 LVDS Serial-Data Input
Noninverting Channel 2 LVDS Serial-Data Input
15
RxIN2+
16
RxCLKIN- Inverting LVDS Parallel-Rate Clock Input
RxCLKIN+ Noninverting LVDS Parallel-Rate Clock Input
17
19, 21
PLLꢁND
PLL ꢁround
PLL Supply Voltage. Bypass PLLV
the pin as possible.
to ꢁND with 0.1µF and 0.001µF capacitors in parallel as close to
CC
20
22
23
PLLV
CC
5V-Tolerant LVTTL/LVCMOS Power-Down Input. PWRDWN is internally pulled down to ꢁND. Outputs are
high impedance when PWRDWN = low or open.
PWRDWN
Parallel-Rate Clock Single-Ended Output. The MAX9242 has a rising-edge strobe. The MAX9244/MAX9246
have a falling-edge strobe.
RxCLKOUT
24
26
27
RxOUT0
RxOUT1
RxOUT2
Channel 0 Single-Ended Outputs
Output Supply Voltage. Bypass each V
close to the pin as possible.
to ꢁND with 0.1µF and 0.001µF capacitors in parallel as
CCO
28, 36, 48
V
CCO
29
30
31
33
RxOUT3
RxOUT4
RxOUT5
RxOUT6
Channel 0 Single-Ended Outputs
______________________________________________________________________________________ 11
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Pin Description (continued)
PIN
34
35
37
39
40
41
NAME
RxOUT7
RxOUT8
RxOUT9
RxOUT10
RxOUT11
RxOUT12
ꢂUNCTIꢁN
Channel 1 Single-Ended Outputs
Digital Supply Voltage. Bypass V
pin as possible.
to ꢁND with 0.1µF and 0.001µF capacitors in parallel as close to the
CC
42
V
CC
43
45
46
47
RxOUT13 Channel 1 Single-Ended Output
RxOUT14
Channel 2 Single-Ended Outputs
RxOUT15
RxOUT16
Functional Diagram
CHANNEL 0
RxIN0+
RxIN0-
7
7
7
7
7
7
SERIAL-TO-PARALLEL
RxOUT0–RxOUT6
RxOUT7–RxOUT13
CHANNEL 1
RxIN1+
RxIN1-
SERIAL-TO-PARALLEL
FIFO
CHANNEL 2
RxIN2+
RxIN2-
SERIAL-TO-PARALLEL
RxOUT14–RxOUT20
PARALLEL
CLOCK
7x OR 9x STROBES
PLL1
CLK CLK
IN
OUT
RxCLKIN+
RxCLKIN-
DCB
FIFO
CONTROL
MAX9242/
MAX9244/
MAX9246
SPREAD-
SPECTRUM
PLL (SSPLL)
RxCLKOUT
SSG
PWRDWN
1ꢀ ______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Data coding by the MAX9209/MAX9213 serializers (that
are companion devices to the MAX9242/MAX9244/
Detailed Description
The MAX9242/MAX9244/MAX9246 deserialize three
MAX9246 deserializers) limits the imbalance of ones
and zeros transmitted on each channel. If +1 is
assigned to each binary 1 transmitted and -1 is
assigned to each binary 0 transmitted, the variation in
the running sum of assigned values is called the digital
sum variation (DSV). The maximum DSV for the data
channels is 10. At most, 10 more zeros than ones, or 10
more ones than zeros, are ever transmitted. The maxi-
mum DSV for the clock channel is 5. Limiting the DSV
and choosing the correct coupling capacitors maintain
differential signal amplitude and reduces jitter due to
droop on AC-coupled links.
LVDS serial-data inputs into 21 single-ended LVCMOS/
LVTTL outputs. The outputs are programmable for no
spread or for a spread of 2ꢀ or 4ꢀ, relative to the
LVDS input clock frequency. The MAX9242/MAX9244
operate at a parallel clock frequency of 16MHz to 34MHz
in DC-balanced mode and 20MHz to 40MHz in non-DC-
balanced mode. The MAX9246 operates at a 6MHz-to-
18MHz parallel clock frequency in DC-balanced mode
and 8MHz-to-20MHz parallel clock frequency in non-DC-
balanced mode. DC-balanced or non-DC-balanced oper-
ation is controlled by the DCB input. The MAX9242 has a
rising-edge strobe and the MAX9244/MAX9246 have a
falling-edge strobe.
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel-input data bits to indicate to the MAX9242/
MAX9244/MAX9246 deserializer whether the data bits
are inverted (see Figures 11 and 12). The deserializer
restores the original state of the parallel data. The LVDS
clock signal alternates duty cycles of 4/9 and 5/9 to
maintain DC balance.
DC Balance (DCB)
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB input (see Table 1). In the non-DC-
balanced mode, each channel deserializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are deserialized every clock cycle (7 data bits + 2
DC-balanced bits). The highest serial-data rate on each
channel in DC-balanced mode is 34MHz x 9 = 306Mbps.
In non-DC-balanced mode, the maximum data rate is
40MHz x 7 = 280Mbps.
Spread-Spectrum Generator (SSG)
The MAX9242/MAX9244/MAX9246 single-ended data
and clock outputs are programmable for a variation of
2ꢀ or 4ꢀ around the LVDS input clock frequency.
The modulation rate of the frequency variation is
32.48kHz for a 33MHz LVDS clock input and scales lin-
early with the input clock frequency (see Table 2). The
spread spectrum can also be turned off. The output
spread is controlled through the SSꢁ input (see Table 3).
Table 1. DCB ꢂtnpꢆion
DCB INPUT LEVEL
ꢂUNCTIꢁN
Non-DC-balanced mode
Reserved
High
Mid
Low
DC-balanced mode
+
-
RxCLKIN
CYCLE N - 1
CYCLE N
CYCLE N + 1
TxIN15 TxIN14 TxIN20 TxIN19 TxIN18
RxIN2
TxIN17 TxIN16 TxIN15 TxIN14 TxIN20 TxIN19 TxIN18
TxIN17 TxIN16 TxIN15 TxIN14
TxIN8
RxIN1
TxIN7
TxIN0
TxIN13 TxIN12 TxIN11
TxIN10
TxIN3
TxIN9
TxIN2
TxIN8
TxIN1
TxIN7
TxIN0
TxIN13 TxIN12 TxIN11
TxIN10
TxIN3
TxIN9
TxIN2
TxIN8
TxIN1
TxIN7
TxIN0
TxIN1
RxIN0
TxIN6
TxIN5
TxIN4
TxIN6
TxIN5
TxIN4
TxIN_ IS DATA FROM THE SERIALIZER.
Figure 11. Deserializer Serial Input in Non-DC-Balanced Mode
______________________________________________________________________________________ 13
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
+
-
RxCLKIN
CYCLE N - 1
CYCLE N
CYCLE N + 1
DCA2
RxIN2
DCB2
TxIN20 TxIN19 TxIN18
TxIN13 TxIN12 TxIN11
TxIN17 TxIN16 TxIN15
TxIN14
TxIN7
TxIN0
DCA2
DCA1
DCA0
DCB2
DCB1
DCB0
TxIN20
TxIN13
TxIN6
TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14
DCA1
RxIN1
DCB1
DCB0
TxIN10
TxIN3
TxIN9
TxIN2
TxIN8
TxIN1
TxIN12 TxIN11 TxIN10
TxIN9
TxIN2
TxIN8
TxIN1
TxIN7
TxIN0
DCA0
RxIN0
TxIN6
TxIN5
TxIN4
TxIN5
TxIN4
TxIN3
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
Figure 12. Deserializer Serial Input in DC-Balanced Mode
To select the mid level, leave the input open, or if driven,
put the driver output in high impedance. The driver high-
impedance leakage current must be less than 10µA.
Any spread change causes a maximum delay time of
32,800 x RCIP before output data is valid. When the
spread amount is changed from 2ꢀ to 4ꢀ or vice-
versa, the data outputs go low for one delay time (see
Figure 13). Similarly, when the spread is changed from
no spread to 2ꢀ or 4ꢀ, the data outputs go low for
one delay time (see Figure 14). The data outputs contin-
ue to switch but are not valid when the spread amount is
changed from 2ꢀ or 4ꢀ to no spread (see Figure
15). The spread-spectrum function is also available
when the MAX9242/MAX9244/MAX9246 operate in non-
DC-balanced mode.
Table ꢀ. Moꢄtlaꢆion Raꢆe
f
(MHz)
f
(kHz) = f
/ 1016
RxCLKIN
RxCLKIN
M
6
5.91
7.87
8
10
16
18
20
33
34
40
9.84
15.75
17.72
19.68
32.48
33.46
39.37
Hot Swap
When the MAX9242/MAX9244/MAX9246 are connected
to an active serializer, they synchronize correctly. The
PLL control voltage does not saturate in response to
high-frequency glitches that may occur during a hot
swap. The PWRDWN input on the MAX9242/MAX9244/
MAX9246 does not need to be cycled when these
devices are connected to an active serializer.
Table 3. FF- ꢂtnpꢆion
FF- INPUT LEVEL
ꢂUNCTIꢁN
RxCLKOUT frequency spread
4ꢀ relative to RxCLKIN
High
Mid
PLL Lock Time
The MAX9242/MAX9244/MAX9246 use two PLLs. The
first PLL (PLL1) generates a 7x clock (non-DC-balanced
mode) or a 9x clock (DC-balanced mode) from RxCLKIN
for deserializing the LVDS inputs. The second PLL
(SSPLL) is used for spread-spectrum modulation. During
initial power-up, the PLL1 locks, and SSPLL locks imme-
diately after. The PLL lock times are set by an internal
counter. The maximum time to lock for each PLL is
32,800 clock periods. Power and clock should be stable
to meet the lock time specification. After initialization, if
the first PLL loses lock, it locks again and then the
RxCLKOUT frequency spread
2ꢀ relative to RxCLKIN
No spread on RxCLKOUT
relative to RxCLKIN
Low
Note: RxOUT_ data outputs are spread because RxCLKOUT
strobes the output of the FIFO.
1± ______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
SSG
4% OR 2% SPREAD
2% OR 4% SPREAD
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
LOW
Figure 13. Output Waveforms when Spread Amount is Changed
SSG
NO SPREAD
2% OR 4% SPREAD
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
LOW
Figure 14. Output Waveforms when Spread is Added
SSG
4% OR 2% SPREAD
NO SPREAD
RPLLS2 (32,800 x RCIP)
RxCLKOUT
RxOUT_
DATA SWITCHING BUT NOT VALID
Figure 15. Output Waveforms when Spread is Removed
spread-spectrum PLL locks immediately after (see
Figure 16). If the spread-spectrum PLL loses lock, it
locks again with only one PLL lock delay (see Figure 17).
increases the common-mode voltage range of an LVDS
receiver to nearly the voltage rating of the capacitor. The
typical LVDS driver output is 350mV centered on a 1.25V
offset voltage, making single-ended output voltages of
1.425V and 1.075V. An LVDS receiver accepts signals
from 0 to 2.4V, allowing approximately 1V common-
mode difference between the driver and receiver on a
AC-Coupling Benefits
Bit errors experienced with DC-coupling (Figure 18)
can be eliminated by increasing the receiver common-
mode voltage range through AC-coupling. AC-coupling
______________________________________________________________________________________ 15
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
RPLLS (65,600 x RCIP)
INTERNAL
PLL1 LOCK
INTERNAL
SSPLL LOCK
RxCLKOUT
RxOUT_
LOW
LOW
LOW
LOW
Figure 16. Output Waveforms when PLL1 Loses Lock and Locks Again
RPLLS2 (32,800 x RCIP)
INTERNAL
SSPLL LOCK
RxCLKOUT
RxOUT_
LOW
TIMING SHOWN FOR STABLE CLOCK AND DATA INPUTS
Figure 17. Output Waveforms if Spread-Spectrum PLL Loses Lock and Locks Again
DC-coupled link (2.4V - 1.425V = 0.975V and 1.075V -
0V = 1.075V). Common-mode voltage differences may
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
be due to ground potential variation or common-mode
noise. If there is more than 1V of difference, the receiver
is not guaranteed to read the input signal correctly and
may cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the
differential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling. However,
two capacitors—one at the serializer output and one at
the deserializer input—provide protection in case either
end of the cable is shorted to a high voltage.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (R ), the LVDS driver
T
output resistor (R ), and the series AC-coupling capac-
O
itors (C). The RC time constant for two equal-value
series capacitors is (C x (R + R )) / 2 (Figure 19). The
T
O
RC time constant for four equal-value series capacitors
is (C x (R + R )) / 4 (Figure 20).
T
O
16 ______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246
TRANSMISSION LINE
TxOUT
RxIN
R
R
T
O
7
7
7
7
7
7
100Ω
100Ω
100Ω
100Ω
7:1
7:1
7:1
PLL
1:7 FIFO
TxIN
1:7 FIFO
1:7 FIFO
RxOUT
PWRDWN
TxCLK IN
PWRDWN
PLL1 +
SSPLL
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 18. DC-Coupled Link, Non-DC-Balanced Mode
R is required to match the transmission line impedance
The DSV is 10. See equation 3 for four series capacitors
(Figure 20).
T
(usually 100Ω) and R is determined by the LVDS dri-
O
ver design (the minimum differential output resistance of
78Ω for the MAX9209/MAX9213 serializers is used in
the following example). This condition leaves the capac-
itor selection to change the system time constant.
The capacitor for 2ꢀ maximum droop at 16MHz parallel
rate clock is:
C = -(2 x t x DSV) / (ln (1 - D) x (R + R ))
B
T
O
C = -(2 x 6.95ns x 10) / (ln (1 - 0.02) x (100Ω + 78Ω))
C = 0.038µF
In the following example, the capacitor value for a 2ꢀ
droop is calculated. Jitter due to this droop is then cal-
culated assuming a 1ns transition time:
Jitter due to droop is proportional to the droop and
transition time:
C = -(2 x t x DSV) / (ln (1 - D) x (R + R )) (Eq 1)
B
T
O
where:
t = t x D (Eq 2)
J T
C = AC-coupling capacitor (F)
where:
t = jitter (s)
T
t = bit time (s)
B
J
DSV = digital sum variation (integer)
ln = natural log
t = transition time (s) (0 to 100ꢀ)
D = droop (ꢀ of signal amplitude)
D = droop (ꢀ of signal amplitude)
Jitter due to 2ꢀ droop and assumed 1ns transition time is:
R = termination resistor (Ω)
T
R
O
= output resistance (Ω)
t = 1ns x 0.02
J
Equation 1 is for two series capacitors (Figure 19). The bit
time (t ) is the period of the parallel clock divided by 9.
t = 20ps
J
B
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
______________________________________________________________________________________ 17
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246
SERIALIZER INSTEAD OF THE DESERIALIZER.
TxOUT
RxIN
R
R
T
O
7
7
7
7
7
7
1:(9 - 2)
+ FIFO
100Ω
100Ω
100Ω
100Ω
(7 + 2):1
1:(9 - 2)
+ FIFO
TxIN
(7 + 2):1
(7 + 2):1
PLL
RxOUT
1:(9 - 2)
+ FIFO
PWRDWN
TxCLK IN
PWRDWN
PLL1 +
SSPLL
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 19. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
RxCLKIN-) to differential +15mV by connecting a 10kΩ
1ꢀ pullup resistor between the noninverting input and
LVDSV , and a 10kΩ 1ꢀ pulldown resistor between
CC
the inverting input and ground. These bias resistors,
along with the 100Ω 1ꢀ tolerant termination resistor,
provide +15mV of differential input. The +15mV bias
causes some small degradation of RSKM proportional to
the slew rate of the clock input. For example, if the clock
transitions 250mV in 500ps, the slew rate of 0.5mV/ps
reduces RSKM by 30ps.
Equation 1 altered for four series capacitors (Figure 20) is:
C = -(4 x t x DSV) / (ln (1 - D) x (R + R )) (Eq 3)
B
T
O
Fail-Safe
The MAX9242/MAX9244/MAX9246 have fail-safe LVDS
inputs in non-DC-balanced mode (Figure 1). Fail-safe
drives the outputs low when the corresponding LVDS
input is open, undriven and shorted, or undriven and
parallel terminated. The fail-safe on the LVDS clock
input drives all outputs low when power is stable. Fail-
safe does not operate in DC-balanced mode.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC-balanced mode, the input fail-
safe circuit drives the corresponding outputs low, and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ (min) to provide biasing for AC-coupling (Figure 1).
To prevent switching due to noise when the clock input
is not driven, bias the clock inputs (RxCLKIN+,
input up to LVDSV
using a 10kΩ resistor, and pull the
CC
noninverting input down to ground using a 10kΩ resistor.
Do not connect a termination resistor. The pullup and
pulldown resistors drive the corresponding outputs low
and prevent switching due to noise.
18 ______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
MAX9209/MAX9213
MAX9242/MAX9244/MAX9246
TxOUT
RxIN
R
R
T
7
7
7
7
7
7
O
1:(9 - 2)
+ FIFO
100Ω
100Ω
100Ω
100Ω
(7 + 2):1
1:(9 - 2)
+ FIFO
TxIN
(7 + 2):1
(7 + 2):1
PLL
RxOUT
1:(9 - 2)
+ FIFO
PWRDWN
TxCLK IN
PWRDWN
PLL1 +
SSPLL
RxCLK OUT
TxCLK OUT
RxCLK IN
21:3 SERIALIZER
3:21 DESERIALIZER
Figure 20. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
surface-mount ceramic 0.1µF and 0.001µF capacitors in
parallel as close to the device as possible, with the
smallest value capacitor closest to the supply pin.
Link Power-Up Sequence
The recommended link power-up sequence is to power
up the serializer, wait until the serializer PLL locks, and
then power up the deserializer. This sequence prevents
the deserializer from seeing an undriven or unstable
input when powering up.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
PWRDWN
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer PC
board with separate layers for power, ground, LVDS
inputs, and digital signals is recommended. Layout PC
board traces for 100Ω differential characteristic imped-
ance. The trace dimensions depend on the type of
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
V
, V
CC CCO
, PLLV , and LVDSV
with high-frequency,
CC
CC
______________________________________________________________________________________ 19
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
trace used (microstrip or stripline). Note that two 50Ω
PC board traces do not have 100Ω differential imped-
ance when brought close together—the impedance
goes down when the traces are brought closer.
The incremental current is added to (for V
> 3.6V)
CCO
or subtracted from (for V
< 3.6V) the DC Electrical
CCO
Characteristics table maximum supply current. The
internal output buffer capacitance is C = 6pF. The
INT
worst-case pattern switching frequency of the data out-
puts is half the switching frequency of the output clock.
Route the PC board traces for an LVDS channel (there
are two conductors per LVDS channel) in parallel to
maintain the differential characteristic impedance.
Place the termination resistor at the end of the PC
board traces within a 1/4 inch of the LVDS receiver
input. Avoid vias. If vias must be used, use only one
pair per LVDS channel and place the via for each line
at the same point along the length of the PC board
traces. This way, any reflections will occur at the same
time. Do not make vias into test points for ATE. Make
LVDS clock and data pairs the same length on the PC
board to avoid pair-to-pair skew. Make the PC board
traces that make up a differential pair the same length
to avoid skew within the differential pair.
In the following example, the incremental supply current
of the MAX9244 in spread and DC-balanced mode is cal-
culated for V
= 5.5V, f = 34MHz, and C = 8pF:
C L
CCO
V = 5.5V - 3.6V = 1.9V
I
C = C
T
+ C = 6pF + 8pF = 14pF
L
INT
where:
I = C V 0.5f x 21 (data outputs) + C V f x 1 (clock
I
T I
C
T I C
output)
I = (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
I
34MHz)
I = 9.5mA + 0.9mA = 10.4mA.
I
5V-Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
ꢁND. SSꢁ and DCB are not 5V tolerant. The input voltage
The maximum supply current in DC-balanced mode for
V
= V
= 3.6V at f = 34MHz is 125mA (from the
CC
CCO C
DC Electrical Characteristics table). Add 10.4mA to get
range for SSꢁ and DCB is nominally ground to V
.
CC
the total approximate maximum supply current at V
= 5.5V and V
CCO
= 3.6V.
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial-data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
CC
If the output supply voltage is less than V
= 3.6V,
CCO
the reduced supply current can be calculated using the
same formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power dissipation rating. Do not exceed
the maximum package power dissipation rating. See
the Absolute Maximum Ratings for maximum package
power dissipation capacity and temperature derating.
V
Output Supply and Power Dissipation
CCO
The outputs have a separate supply (V
) for interfacing
CCO
Rising- or Falling-Edge Output Strobe
The MAX9242 has a rising-edge output strobe, which
latches the parallel output data into the next chip on the
rising edge of RxCLKOUT. The MAX9244/MAX9246
have a falling-edge output strobe, which latches the
parallel output data into the next chip on the falling
edge of RxCLKOUT The deserializer output strobe
.
polarity does not need to match the serializer input
strobe polarity.
to systems with 1.8V to 5V nominal input logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for V
= 3.6V with 8pF load at several
CCO
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for V
other than 3.6V with the same
CCO
8pF load and worst-case pattern can be calculated using:
I = C V 0.5f x 21 (data outputs)
I
T I
C
+ C V f x 1 (clock output)
T I C
Three-Level Logic Inputs
SSꢁ and DCB (DCB mid level is reserved) are three-
level-logic inputs. A logic-high input voltage must be
greater than +2.5V and a logic-low input voltage must
be less than +0.8V. A mid-level logic is recognized by
the MAX9242/MAX9244/MAX9246 when the input is left
open or connected to a driver in a high-impedance
state. A weak inverter on the input stage of SSꢁ and
where:
I = incremental supply current
I
C = total internal (C ) and external (C ) load capaci-
T
INT
L
tance
V = incremental supply voltage
I
f = output clock switching frequency
C
ꢀ0 ______________________________________________________________________________________
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
DCB provides the proper mid-level voltage under con-
R
2kΩ
D
ditions of low input current. The mid-level input current
must not be greater than 10µA, and the mid-level logic
state cannot be driven with an external voltage source.
50Ω TO 100Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
IEC 61000-4-2 Level 4 and ISO 10605
ESD Protection
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
The MAX9242/MAX9244/MAX9246 ESD tolerance is
rated for Human Body Model, IEC 61000-4-2 and ISO
10605. The ISO 10605 and IEC 61000-4-2 standards
specify ESD tolerance for electronic systems. All LVDS
inputs on the MAX9242/MAX9244/MAX9246 meet ISO
10605 ESD protection at 30kV Air-ꢁap Discharge and
6kV Contact Discharge and IEC 61000-4-2 ESD pro-
tection at 15kV Air-ꢁap Discharge and 8kV Contact
Discharge. All other pins meet the Human Body Model
ESD tolerance of 2.5kV. The Human Body Model dis-
SOURCE
Figure 23. ISO 10605 Contact Discharge ESD Test Circuit
Pin Configuration
TOP VIEW
charge components are C = 100pF and R = 1.5kΩ
S
D
(Figure 21). The IEC 61000-4-2 discharge components
are C = 150pF and R = 330Ω (see Figure 22). The
RxOUT17
RxOUT18
GND
1
2
3
4
5
6
7
8
9
48
V
CCO
S
D
47 RxOUT16
46 RxOUT15
45 RxOUT14
44 GND
ISO 10605 discharge components are C = 330pF and
S
R = 2kΩ (Figure 23).
D
RxOUT19
RxOUT20
SSG
R
D
43 RxOUT13
1MΩ
1.5kΩ
DCB
42
V
CC
RxIN0-
RxIN0+
41 RxOUT12
40 RxOUT11
39 RxOUT10
38 GND
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
DISCHARGE
RESISTANCE
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
VOLTAGE
DC
RxIN1- 10
RxIN1+ 11
100pF
SOURCE
LVDSV
12
37 RxOUT9
CC
MAX9242/
MAX9244/
MAX9246
LVDSGND 13
RxIN2- 14
36
V
CCO
35 RxOUT8
34 RxOUT7
33 RxOUT6
32 GND
Figure 21. Human Body ESD Test Circuit
RxIN2+ 15
RxCLKIN- 16
RxCLKIN+ 17
LVDSGND 18
PLLGND 19
R1
R2
50Ω TO 100Ω
330Ω
31 RxOUT5
30 RxOUT4
29 RxOUT3
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
PLLV
20
21
22
CC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
PLLGND
28
V
CCO
150pF
27 RxOUT2
26 RxOUT1
25 GND
PWRDWN
SOURCE
RxCLKOUT 23
RxOUT0 24
Figure 22. IEC 61000-4-2 Contact Discharge ESD Test Circuit
TFFꢁP
Chip Information
PROCESS: CMOS
______________________________________________________________________________________ ꢀ1
21-Bit Deserializers with Programmable
Spread Spectrum and DC Balance
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maximꢅip.pom/ꢃapkages.)
3
2
1
E
H
N
TOP VIEW
BOTTOM VIEW
SEE DETAIL A
;
b
A1
A2
A
e
C
L
c
SEATING
PLANE
D
SIDE VIEW
b
END VIEW
b1
WITH PLATING
c1
c
(
)
;
PARTING
LINE
BASE METAL
0.25
L
DETAIL A
SECTION C-C
NOTES:
1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE.
3. CONTROLLING DIMENSION: MILLIMETERS.
DALLAS
SEMICONDUCTOR
PROPRIETARYINFORMATION
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED.
5. "N" REFERS TO NUMBER OF LEADS.
TITLE:
PACKAGE OUTLINE, 48L TSSOP, 6.1mm BODY
6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO
APPROVAL
DOCUMENT CONTROL NO.
REV.
PARALLEL PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE
SPECIFIED DISTANCE FROM (-C-) IN THE DIRECTION INDICATED.
1
21-0155
B
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
ꢀꢀ ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Springer
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