MAX9247 [MAXIM]
27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer; 27位，为2.5MHz至42MHz直流平衡的LVDS串行器
| 型号： | MAX9247 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Serializer |
| 文件： | 总17页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3955; Rev 4; 4/12
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
General Description
Features
o Preemphasis Improves Eye Diagram and Signal
The MAX9247 digital video parallel-to-serial converter
serializes 27 bits of parallel data into a serial-data stream.
Eighteen bits of video data and 9 bits of control data are
encoded and multiplexed onto the serial interface, reduc-
ing the serial-data rate. The data-enable input determines
when the video or control data is serialized.
Integrity at the Output
o Proprietary Data Encoding for DC Balance and
Reduced EMI
o Control Data Sent During Video Blanking
o Five Control Data Inputs are Single-Bit-Error
Tolerant
The MAX9247 pairs with the MAX9248/MAX9250 dese-
rializers to form a complete digital video serial link.
Interconnect can be controlled-impedance PCB traces or
twisted-pair cable. Proprietary data encoding reduces
EMI and provides DC balance. DC balance allows AC-
coupling, providing isolation between the transmitting
and receiving ends of the interface. The LVDS output is
internally terminated with 100Ω. For operating frequen-
cies less than 35MHz, the MAX9247 can also pair with
the MAX9218 deserializer.
o Programmable Phase-Shifted LVDS Signaling
Reduces EMI
o Output Common-Mode Filter Reduces EMI
o Greater Than 10m STP Cable Drive
o Wide ±±2 Reference Clock Tolerance
o ISO 10605 and IEC 61000-4-± Level 4
ESD Protection
o Separate Input Supply Allows Interface to 1.8V
to 3.3V Logic
ESD tolerance is specified for ISO 10605 with 10kV
Contact Discharge and 30kV Air-ꢀap Discharge.
o +3.3V Core Supply
o Space-Saving LQFP Package
The MAX9247 operates from a +3.3V core supply and
features a separate input supply for interfacing to 1.8V
to 3.3V logic levels. This device is available in a 48-lead
LQFP package and is specified from -40°C to +85°C or
-40°C to +105°C.
o -40°C to +85°C and -40°C to +105°C Operating
Temperature Ranges
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +105°C
-40°C to +105°C
PIN-PACKAGE
48 LQFP
Applications
MAX9247ECM+
MAX9247ECM/V+
MAX9247ꢀCM+
MAX9247ꢀCM/V+
Navigation System Displays
In-Vehicle Entertainment Systems
Video Cameras
48 LQFP
48 LQFP
48 LQFP
LCDs
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin Configuration
TOP VIEW
+
GND
1
2
3
4
5
6
7
8
9
36 RNG0
35 RNG1
V
CCIN
RGB_IN10
34
V
CCLVDS
RGB_IN11
RGB_IN12
RGB_IN13
RGB_IN14
RGB_IN15
RGB_IN16
33 OUT+
32 OUT-
31 LVDSGND
30 LVDSGND
29 CMF
MAX9247
28 PWRDWN
RGB_IN17 10
27
26
25
V
CCPLL
CNTL_IN0
CNTL_IN1
PLLGND
PRE
11
12
LQFP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-6±9-464±,
or visit Maxim’s website at www.maxim-ic.com.
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
ABSOLUTE MAXIMUM RATINGS
CC_
Any ꢀround to Any ꢀround...................................-0.5V to +0.5V
OUT+, OUT-, CMF to LVDSꢀND...........................-0.5V to +4.0V
OUT+, OUT- Short Circuit to LVDSꢀND
V
to _ꢀND........................................................-0.5V to +4.0V
All Pins to ꢀND .............................................................. 200V
Human Body Model (R = 1.5kΩ, C = 100pF)
D
S
All Pins to ꢀND ................................................................ 3kV
ISO 10605 (R = 2kΩ, C = 330pF)
D
S
or V
.............................................................Continuous
Contact Discharge (OUT+, OUT-) to LVDSꢀND ........... 10kV
CCLVDS
OUT+, OUT- Short Through 0.125µF (or smaller),
25V Series Capacitor..........................................-0.5V to +16V
RꢀB_IN[17:0], CNTL_IN[8:0], DE_IN,
Air-ꢀap Discharge (OUT+, OUT-) to LVDSꢀND ........... 30kV
IEC 61000-4-2 (R = 330Ω, C = 150pF)
D
S
Contact Discharge (OUT+, OUT-) to LVDSꢀND ........... 10kV
Air-ꢀap Discharge (OUT+, OUT-) to LVDSꢀND ........... 15kV
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering,10s)..................................+300°C
Soldering Temperature (reflow) .......................................+260°C
RNꢀ0, RNꢀ1, PRE, PCLK_IN,
PWRDWN to ꢀND ...............................-0.5V to (V
MAX9247
+ 0.5V)
CCIN
Continuous Power Dissipation (T = +70°C)
A
48-Lead LQFP (derate 20.8mW/°C above +70°C)....1666.7mW
ESD Protection
Machine Model (R = 0Ω, C = 200pF)
D
S
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 100Ω 1ꢁ, PWRDWN = high, PRE = low, T = -40°C to +105°C, unless otherwise noted. Typical
CC_
L A
= +3.3V, T = +25°C.) (Notes 1, 2)
A
values are at V
CC_
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
+ 0.3
UNITS
SINGLE-ENDED INPUTS (RGB_IN[17:0], CNTL_IN[8:0], DE_IN, PCLK_IN, PWRDWN, RNG_, PRE)
V
V
V
V
= 1.71V to < 3V (Note 3)
= 3.0V to 3.6V
0.65 x V
2
V
CCIN
CCIN
CCIN
CCIN
CCIN
CCIN
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
0.3 + V
0.3 x V
CCIN
CCIN
= 1.71V to < 3V (Note 3)
= 3.0V to 3.6V
-0.3
V
IL
-0.3
+0.8
V
= -0.3V to 0V
IN
V
= 1.71V
CCIN
(MAX9247ECM),
= -0.15V to 0V
-100
-20
+20
to 3.6V,
PWRDWN =
high or low
V
Input Current
I
IN
µA
V
IN
(MAX9247ꢀCM)
V
IN
= 0V to (V
+ 0.3V)
+20
-1.5
CCIN
Input Clamp Voltage
V
I
CL
= -18mA
CL
LVDS OUTPUTS (OUT+, OUT-)
Differential Output Voltage
V
Figure 1
Figure 1
Figure 1
Figure 1
250
335
450
20
mV
mV
V
OD
Change in V
Between
OD
∆V
OD
OS
Complementary Output States
Common-Mode Voltage
V
1.125
-15
1.29
1.475
20
Change in V Between
OS
Complementary Output States
∆V
mV
mA
mA
OS
Output Short-Circuit Current
I
V
V
or V = 0V or 3.6V
OUT-
8
+15
15
OS
OUT+
Magnitude of Differential
Output Short-Circuit Current
I
= 0V
OD
5.5
OSD
V
V
= 0V,
= 3.6V
OUT+
OUT-
Output High-Impedance
Current
PWRDWN = low
or V = 0V
I
-1
+1
µA
OZ
CC_
V
V
= 3.6V,
= 0V
OUT+
OUT-
±
_______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, R = 100Ω 1ꢁ, PWRDWN = high, PRE = low, T = -40°C to +105°C, unless otherwise noted. Typical
CC_
L A
= +3.3V, T = +25°C.) (Notes 1, 2)
A
values are at V
CC_
PARAMETER
SYMBOL
CONDITIONS
MIN
78
TYP
110
15
MAX
147
25
27
25
27
28
30
39
42
65
69
70
75
50
UNITS
Differential Output Resistance
R
Ω
O
PRE = 0
PRE = 1
PRE = 0
PRE = 1
PRE = 0
PRE = 1
PRE = 0
PRE = 1
PRE = 0
PRE = 1
PRE = 0
PRE = 1
2.5MHz
18
23
33
50
60
5MHz
R = 100Ω 1ꢁ,
L
10MHz
20MHz
35MHz
42MHz
Worst-Case Supply Current
C = 5pF,
L
I
mA
CCW
continuous 10
transition words
Power-Down Supply Current
I
(Note 4)
µA
CCZ
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 100Ω 1ꢁ, C = 5pF, PWRDWN = high, PRE = low, T = -40°C to +105°C, unless otherwise noted.
CC_
L L A
= +3.3V, T = +25°C.) (Note 3)
A
Typical values are at V
CC_
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PCLK_IN TIMING REQUIREMENTS
MAX9247ECM
MAX9247ꢀCM
23.8
28.6
2.5
400.0
400.0
42.0
Clock Period
t
Figure 2
ns
MHz
ꢁ
T
MAX9247ECM
MAX9247ꢀCM
Clock Frequency
f
CLK
2.5
35.0
Clock Frequency Difference from
Deserializer Reference Clock
∆f
CLK
-2
+2
Clock Duty Cycle
DC
t /t or t
HIꢀH T
/t , Figure 2
LOW T
35
50
65
ꢁ
Clock Transition Time
t , t
R
Figure 2
2.5
ns
F
SWITCHING CHARACTERISTICS
PRE = low
PRE = high
PRE = low
PRE = high
280
240
280
240
370
320
370
320
20ꢁ to 80ꢁ,
≥ 250mV, Figure 3
Output Rise Time
t
ps
ps
RISE
V
OD
80ꢁ to 20ꢁ,
≥ 250mV, Figure 3
Output Fall Time
t
FALL
V
OD
Input Setup Time
Input Hold Time
t
Figure 4
Figure 4
3
3
ns
ns
SET
t
HOLD
_______________________________________________________________________________________
3
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
AC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, R = 100Ω 1ꢁ, C = 5pF, PWRDWN = high, PRE = low, T = -40°C to +105°C, unless otherwise noted.
CC_
L L A
= +3.3V, T = +25°C.) (Note 3)
A
Typical values are at V
CC_
PARAMETER
Serializer Delay
SYMBOL
CONDITIONS
MIN
3.10 x
t + 2.0
T
TYP
MAX
3.10 x
t + 8.0
T
UNITS
t
Figure 5
ns
SD
17,100 x
PLL Lock Time
t
Figure 6
Figure 7
ns
µs
ps
LOCK
t
T
MAX9247
Power-Down Delay
Peak-to-Peak Output Jitter
t
1
PD
Measured with PRBS input pattern at
840Mbps data rate
t
150
JITT
840Mbps data rate,
CMF open, Figure 8
22
12
70
50
Peak-to-Peak Output Offset
Voltage
V
mV
OS(P-P)
840Mbps data rate,
CMF 0.1µF to ground, Figure 8
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,
except V , ∆V , and ∆V
.
OS
OD
OD
Note ±: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at T = +25°C.
A
Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma.
Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ V
- 0.3V. PWRDWN is ≤ 0.3V.
CCIN
4
_______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
Typical Operating Characteristics
(V
= +3.3V, R = 100Ω, T = +25°C, unless otherwise noted.)
L A
CC_
WORST-CASE PATTERN
SUPPLY CURRENT vs. FREQUENCY
EYE DIAGRAM WITHOUT PREEMPHASIS
EYE DIAGRAM WITH PREEMPHASIS
70
60
50
40
30
20
10
0
2 METER CAT5 CABLE
100Ω TERMINATION
2 METER CAT5 CABLE
100Ω TERMINATION
PRE = LOW
= 42MHz
PRE = HIGH
f = 42MHz
REFCLK
f
REFCLK
WITH PREEMPHASIS
GND
100mV/div
100mV/div
GND
WITHOUT PREEMPHASIS
200ps/div
200ps/div
0
10
20
30
40
FREQUENCY (MHz)
CABLE LENGTH
vs. FREQUENCY BIT-ERROR RATE < 10-9
BIT-ERROR RATE vs. CABLE LENGTH
1.00E-14
1.00E-13
1.00E-12
1.00E-11
45
40
35
30
25
20
15
10
5
CAT5 CABLE
f
= 42MHz
REFCLK
840Mbps DATA RATE
FOR CABLE LENGTH < 10m
-12
BER < 10
1.00E-10
0
2
4
6
8
10
12
0
2
4
6
8
10 12 14 16 18 20
CAT5 CABLE LENGTH (m)
CABLE LENGTH (m)
_______________________________________________________________________________________
5
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Pin Description
PIN
1, 13, 37
NAME
ꢀND
FUNCTION
Input Buffer Supply and Digital Supply ꢀround
Input Buffer Supply Voltage. Bypass to ꢀND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
2
V
CCIN
RꢀB_IN10–
RꢀB_IN17,
RꢀB_IN0–
RꢀB_IN9
LVTTL/LVCMOS Red, ꢀreen, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
ꢀND.
3–10,
39–48
MAX9247
CNTL_IN0,
CNTL_IN1,
CNTL_IN2–
CNTL_IN8
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to ꢀND.
11, 12, 15–21
Digital Supply Voltage. Bypass to ꢀND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
14, 38
22
V
CC
LVTTL/LVCMOS Data-Enable Input. Logic-high selects RꢀB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to ꢀND.
DE_IN
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to ꢀND.
23
PCLK_IN
24
25
26
I.C.
PRE
Internally Connected. Leave unconnected for normal operation.
Preemphasis Enable Input. Drive PRE high to enable preemphasis.
PLL Supply ꢀround
PLLꢀND
PLL Supply Voltage. Bypass to PLLꢀND with 0.1µF and 0.001µF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
27
28
29
V
CCPLL
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to ꢀND.
Common-Mode Filter. Optionally connect a capacitor between CMF and LVDSꢀND to filter
common-mode switching noise.
CMF
30, 31
32
LVDSꢀND
OUT-
LVDS Supply ꢀround
Inverting LVDS Serial-Data Output
Noninverting LVDS Serial-Data Output
33
OUT+
LVDS Supply Voltage. Bypass to LVDSꢀND with 0.1µF and 0.001µF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
34
35
36
V
CCLVDS
RNꢀ1
RNꢀ0
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to ꢀND.
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to ꢀND.
6
_______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
Functional Diagram
PRE
RGB_IN
1
0
OUT+
DC BALANCE/
ENCODE
INPUT LATCH
PAR-TO-SER
OUT-
CMF
CNTL_IN
DE_IN
PCLK_IN
RNG0
PLL
TIMING AND CONTROL
RNG1
MAX9247
PWRDWN
R /2
L
OUT+
OUT-
V
OD
V
OS
R /2
L
GND
((OUT+) + (OUT-))/2
OUT-
OUT+
V
(-)
V (+)
OS
V
(-)
OS
OS
∆V = |V (+) - V (-)|
OS
OS
OS
V
OD
(+)
V
OD
= 0V
V
(-)
V
OD
(-)
OD
∆V = |V (+) - V (-)|
OD
OD
OD
(OUT+) - (OUT-)
Figure 1. LVDS DC Output Load and Parameters
_______________________________________________________________________________________
7
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
t
T
V
IHmin
t
HIGH
PCLK_IN
V
ILmax
MAX9247
t
t
F
t
LOW
R
Figure 2. Parallel Clock Requirements
OUT+
OUT-
R
L
C
L
C
L
80%
80%
20%
20%
(OUT+) - (OUT-)
t
t
FALL
RISE
Figure 3. Output Rise and Fall Times
V
IHmin
PCLK_IN
V
ILmax
t
t
HOLD
SET
RGB_IN[17:0]
V
V
V
IHmin
IHmin
ILmax
CNTL_IN[8:0]
V
ILmax
DE_IN
Figure 4. Synchronous Input Timing
8
_______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
EXPANDED TIME SCALE
RGB_IN
CNTL_IN
N
N + 2
N + 3
N + 4
N + 1
PCLK_IN
N - 1
N
OUT_
t
SD
BIT 0
BIT 19
Figure 5. Serializer Delay
V
ILmax
PWRDWN
t
LOCK
V
= 0V
HIGH IMPEDANCE
OD
(OUT+) - (OUT-)
PCLK_IN
Figure 6. PLL Lock Time
PWRDWN
V
ILmax
t
PD
HIGH IMPEDANCE
(OUT+) - (OUT-)
PCLK_IN
Figure 7. Power-Down Delay
_______________________________________________________________________________________
9
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
OUT-
OUT+
((OUT+) + (OUT-))/2
V
V
OS(P-P)
OS(P-P)
MAX9247
Figure 8. Peak-to-Peak Output Offset Voltage
maintains DC balance across the serial cable. Two
transition words, which contain a unique bit sequence,
are inserted at the transition boundaries of video-to-
control and control-to-video phases.
Detailed Description
The MAX9247 DC-balanced serializer operates at a
2.5MHz-to-42MHz parallel clock frequency, serializing
18 bits of parallel video data RꢀB_IN[17:0] when the
data-enable input DE_IN is high, or 9 bits of parallel
control data CNTL_IN[8:0] when DE_IN is low. The
RꢀB video input data are encoded using 2 overhead
bits, EN0 and EN1, resulting in a serial word length of
20 bits (see Table 1). Control inputs are mapped to 19
bits and encoded with 1 overhead bit, EN0, also result-
ing in a 20-bit serial word. Encoding reduces EMI and
Control data inputs C0 to C4 are mapped to 3 bits each
in the serial control word (see Table 2). At the deserial-
izer, 2 or 3 bits at the same state determine the state of
the recovered bit, providing single-bit-error tolerance
for C0 to C4. Control data that may be visible if an error
occurs, such as VSYNC and HSYNC, can be connect-
ed to these inputs. Control data inputs C5 to C8 are
mapped to 1 bit each.
Table 1. Serial Video Phase Word Format
0
1
2
3
4
5
6
7
8
9
10
S8
11
S9
12
13
14
15
16
17
18
19
EN0 EN1 S0
S1
S2
S3
S4
S5
S6
S7
S10 S11 S12 S13 S14 S15 S16 S17
Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.
Table ±. Serial Control Phase Word Format
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
EN0 C0
C0
C0
C1
C1
C1
C2
C2
C2
C3
C3
C3
C4
C4
C4
C5
C6
C7
C8
Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.
10 ______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
TRANSITION
PHASE
TRANSITION
PHASE
CONTROL
PHASE
CONTROL
PHASE
VIDEO PHASE
PCLK_IN
CNTL_IN
DE_IN
RGB_IN
= NOT SAMPLED BY PCLK_IN
Figure 9. Transition Timing
13 show the AC-coupled serializer and deserializer with
four capacitors per link.
Transition Timing
The transition words require interconnect bandwidth
and displace control data. Therefore, control data is not
sampled (see Figure 9):
Selection of AC-Coupling Capacitors
See Figure 14 for calculating the capacitor values for
AC-coupling depending on the parallel clock frequen-
cy. The plot shows capacitor values for two- and four-
capacitor-per-link systems. For applications using less
than 18MHz clock frequency, use 0.1µF capacitors.
• Two clock cycles before DE_IN goes high
• During the video phase
• Two clock cycles after DE_IN goes low
The last sampled control data are latched at the deserial-
izer control data outputs during the transition and video
phases. Video data are latched at the deserializer RꢀB
data outputs during the transition and control phases.
Frequency-Range Setting RNG[1:0]
The RNꢀ[1:0] inputs select the operating frequency
range of the MAX9247 serializer. An external clock with-
in this range is required for operation. Table 3 shows
the selectable frequency ranges and corresponding
data rates for the MAX9247.
Applications Information
AC-Coupling Benefits
AC-coupling increases the common-mode voltage to
the voltage rating of the capacitor. Two capacitors are
sufficient for isolation, but four capacitors—two at the
serializer output and two at the deserializer input—pro-
vide protection if either end of the cable is shorted to a
high voltage. AC-coupling blocks low-frequency
ground shifts and common-mode noise. The MAX9247
serializer can also be DC-coupled to the MAX9248/
MAX9250 deserializers.
Table 3. Parallel Clock Frequency Range
Select
PARALLEL
SERIAL-DATA RATE
RNG1
RNG0
CLOCK (MHz)
(Mbps)
0
0
1
1
0
1
0
1
2.5 to 5
50 to 100
100 to 200
200 to 400
400 to 840
5 to10
10 to 20
20 to 42
Figures 10 and 12 show an AC-coupled serializer and
deserializer with two capacitors per link. Figures 11 and
______________________________________________________________________________________ 11
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
V
CC
130Ω
130Ω
R/F
OUTEN
PRE
*
RGB_IN
1
0
RGB_OUT
1
0
OUT
IN
*
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
82Ω
CMF
DE_IN
MAX9247
PCLK_OUT
REF_IN
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
*CAPACITORS CAN BE AT EITHER END.
100Ω DIFFERENTIAL STP CABLE
Figure 10. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link
V
CC
130Ω
82Ω
130Ω
82Ω
R/F
OUTEN
RGB_OUT
PRE
RGB_IN
1
0
1
0
IN
OUT
CNTL_OUT
DE_OUT
CNTL_IN
CMF
DE_IN
PCLK_OUT
REF_IN
RNG0
RNG1
PLL
PCLK_IN
RNG0
RNG1
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9250
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 11. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link
1± ______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
V
CC
130Ω
130Ω
R/F
PRE
*
IN+
RGB_IN
1
0
RGB_OUT
1
0
OUT
*
IN-
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
82Ω
CMF
DE_IN
PCLK_OUT
REFCLK
PLL
PCLK_IN
RNG0
RNG1
SSPLL
SS
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9248
RNG[0:1]
CERAMIC RF SURFACE-MOUNT CAPACITOR
*CAPACITORS CAN BE AT EITHER END.
100Ω DIFFERENTIAL STP CABLE
Figure 12. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link
V
CC
130Ω
82Ω
130Ω
R/F
PRE
IN+
RGB_IN
1
0
RGB_OUT
1
0
OUT
IN-
CNTL_OUT
DE_OUT
CNTL_IN
82Ω
CMF
DE_IN
PCLK_OUT
REFCLK
PLL
PCLK_IN
RNG0
RNG1
SSPLL
SS
TIMING AND
CONTROL
PLL
PWRDWN
LOCK
TIMING AND
CONTROL
PWRDWN
MAX9247
MAX9248
RNG[0:1]
CERAMIC RF SURFACE-MOUNT CAPACITOR
100Ω DIFFERENTIAL STP CABLE
Figure 13. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link
______________________________________________________________________________________ 13
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
LVDS Output Preemphasis (PRE)
The MAX9247 features a preemphasis mode where extra
current is added to the output and causes the ampli-
tude to increase by 40ꢁ to 50ꢁ at the transition point.
Preemphasis helps to get a faster transition, better eye
diagram, and improve signal integrity. See the Typical
Operating Characteristics. The additional current is
turned on for a short time (360ps, typ) during data transi-
tion, and then turned off. Enable preemphasis by driving
PRE high.
AC-COUPLING CAPACITOR VALUE
vs. PARALLEL CLOCK FREQUENCY
140
120
100
80
FOUR CAPACITORS PER LINK
MAX9247
60
Power-Down and Power-Off
40
Driving PWRDWN low stops the PLL, switches out the
integrated 100Ω output termination, and puts the output
in high impedance to ground and differential. With PWRD-
WN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥
20
TWO CAPACITORS PER LINK
0
18 21 24 27 30 33 36 39 42
PARALLEL CLOCK FREQUENCY (MHz)
V
CCIN
- 0.3V, supply current is reduced to 50µA or less.
Driving PWRDWN high starts PLL lock to PCLK_IN and
switches in the 100Ω output termination resistor. The
LVDS output is not driven until the PLL locks. The LVDS
output is high impedance to ground and 100Ω differen-
tial. The 100Ω integrated termination pulls OUT+ and
Figure 14. AC-Coupling Capacitor Values vs. Clock Frequency
of 18MHz to 42MHz
Termination
The MAX9247 has an integrated 100Ω output-termina-
tion resistor. This resistor damps reflections from
induced noise and mismatches between the transmis-
sion line impedance and termination resistors at the
deserializer input. With PWRDWN = low or with the sup-
ply off, the output termination is switched out and the
LVDS output is high impedance.
OUT- together while the PLL is locking so that V
= 0V.
OD
If V = 0, the output resistor is switched out and the LVDS
CC
outputs are high impedance to ground and differential.
PLL Lock Time
The PLL lock time is set by an internal counter. The lock
time is 17,100 PCLK_IN cycles. Power and clock should
be stable to meet the lock-time specification.
Common-Mode Filter
The integrated 100Ω output termination is made up of
two 50Ω resistors in series. The junction of the resistors
is connected to the CMF pin for connecting an optional
common-mode filter capacitor. Connect the filter
capacitor to ground close to the MAX9247 as shown in
Figure 15. The capacitor shunts common-mode switch-
ing current to ground to reduce EMI.
Input Buffer Supply
The single-ended inputs (RꢀB_IN[17:0], CNTL_IN[8:0],
DE_IN, RNꢀ0, RNꢀ1, PRE, PCLK_IN, and PWRDWN)
are powered from V
. V
can be connected to a
CCIN CCIN
1.71V to 3.6V supply, allowing logic inputs with a nomi-
nal swing of V
. If no power is applied to V
CCIN
CCIN
when power is applied to V , the inputs are disabled
CC
and PWRDWN is internally driven low, putting the
device in the power-down state.
Power-Supply Sequencing of MAX9247
and MAX9248/MAX9250 Video Link
OUT+
The MAX9247 and MAX9248/MAX9250 video link can
be powered up in several ways. The best approach is
to keep both MAX9247 and MAX9248 powered down
while supplies are ramping up and PCLK_IN of the
MAX9247 and REFCLK of the MAX9248/MAX9250 are
stabilizing. After all of the power supplies of the
MAX9247 and MAX9248/MAX9250 are stable, including
PCLK_IN and REFCLK, do the following:
R /2
O
CMF
OUT-
R /2
O
C
CMF
1) Power up the MAX9247 first
Figure 15. Common-Mode Filter Capacitor Connection
14 ______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
2) Wait for at least t
of MAX9247 (or 17100 x t )
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
LOCK
T
to get activity on the link
3) Power up the MAX9248
Power-Supply Circuits and Bypassing
The MAX9247 has isolated on-chip power domains. The
Board Layout
Separate the LVTTL/LVCMOS inputs and LVDS output
to prevent crosstalk. A four-layer PCB with separate lay-
ers for power, ground, and signals is recommended.
digital core supply (V ) and single-ended input supply
CC
(V
CCIN
) are isolated but have a common ground (ꢀND).
The PLL has separate power and ground (V
and
CCPLL
PLLꢀND) and the LVDS input also has separate power
and ground (V and LVDSꢀND). The grounds are
CCLVDS
ESD Protection
The MAX9247 ESD tolerance is rated for IEC 61000-4-
2, Human Body Model, Machine Model, and ISO 10605
standards. IEC 61000-4-2 and ISO 10605 specify ESD
tolerance for electronic systems. The IEC 61000-4-2
isolated by diode connections. Bypass each V , V
,
CC CCIN
V
, and V
pin with high-frequency, surface-
CCPLL
CCLVDS
mount ceramic 0.1µF and 0.001µF capacitors in parallel
as close to the device as possible, with the smallest value
capacitor closest to the supply pin.
discharge components are C = 150pF and R
=
D
S
330Ω (Figure 16). For IEC 61000-4-2, the LVDS outputs
are rated for 8kV Contact Discharge and 15kV Air-
ꢀap Discharge. The Human Body Model discharge
LVDS Output
The LVDS output is a current source. The voltage swing
is proportional to the termination resistance. The output
is rated for a differential load of 100Ω 1ꢁ.
components are C = 100pF and R = 1.5kΩ (Figure
S
D
17). For the Human Body Model, all pins are rated for
3kV Contact Discharge. The ISO 10605 discharge
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
components are C = 330pF and R = 2kΩ (Figure
S
D
18). For ISO 10605, the LVDS outputs are rated for
10kV contact and 30kV air discharge. The Machine
Model discharge components are C = 200pF and
S
R = 0Ω (Figure 19).
D
R
2kΩ
D
R
D
330Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
330pF
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
C
S
STORAGE
CAPACITOR
150pF
SOURCE
SOURCE
Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Figure 18. ISO 10605 Contact Discharge ESD Test Circuit
R
D
R
0Ω
D
1MΩ
1.5kΩ
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
100pF
C
S
200pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
SOURCE
SOURCE
Figure 17. Human Body ESD Test Circuit
Figure 19. Machine Model ESD Test Circuit
______________________________________________________________________________________ 15
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: CMOS
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
±1-0054
MAX9247
90-0093
48 LQFP
C48+5
16 ______________________________________________________________________________________
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
MAX9247
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
Corrected LQFP package, added +105°C part, changed temperature limits
for +105°C rated part, and added Machine Model ESD text and diagram
2
5/08
1–6, 15–19
Added /V parts in the Ordering Information table and added new Power-
Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section
3
4
4/09
4/12
1, 14
2, 6
Corrected errors in Absolute Maximum Ratings and Pin Description sections
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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