MAX9259GCB/V+ [MAXIM]
Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel; 吉比特多媒体串行链路，提供扩频功能和全双工控制通道
| 型号： | MAX9259GCB/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Gigabit Multimedia Serial Link with Spread Spectrum and Full-Duplex Control Channel |
| 文件： | 总51页 (文件大小：2397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4968; Rev 3; 1/11
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
General Description
Features
S 2.5Gbps Payload Rate, AC-Coupled Serial Link
The MAX9259/MAX9260 chipset presents Maxim’s
gigabit multimedia serial link (GMSL) technology. The
MAX9259 serializer pairs with the MAX9260 deserializer
to form a complete digital serial link for joint transmission
of high-speed video, audio, and control data.
with 8B/10B Line Coding
S 24-Bit or 32-Bit Programmable Parallel Input Bus
Supports Up to XGA (1280 x 768) or Dual-View
WVGA (2 x 854 x 480) Panels with 18-Bit or 24-Bit
Color
The MAX9259/MAX9260 allow a maximum serial payload
data rate of 2.5Gbps for a 15m shielded twisted-pair
(STP) cable. The 24-bit or 32-bit width parallel interface
operates up to a maximum bus clock of 104MHz or
78MHz, respectively. This serial link supports display
panels from QVGA (320 x 240) up to XGA (1280 x 768),
or dual-view WVGA (2 x 854 x 480).
S 8.33MHz to 104MHz (24-Bit Bus) or 6.25MHz to
78MHz (32-Bit Bus) Parallel Data Rate
S Support Two/Three 10-Bit Camera Links at
104MHz/78MHz Maximum Pixel Clock
2
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I S
Audio Channel Supports High-Definition Audio
The 24-bit or 32-bit mode handles 21 or 29 bits of data,
along with an I S input, supporting 4- to 32-bit audio
S Embedded Half-/Full-Duplex Bidirectional Control
2
Channel (100kbps to 1Mbps)
word lengths and an 8kHz to 192kHz sample rate. The
embedded control channel forms a full-duplex, differen-
tial 100kbps to 1Mbps UART link between the serializer
and deserializer. The host electronic control unit (ECU)
or microcontroller (FC) resides either on the MAX9259
(for video display) or on the MAX9260 (for image sens-
ing). In addition, the control channel enables ECU/FC
control of peripherals in the remote side of the serial link
S Separate Interrupt Signal Supports Touch-Screen
Functions for Display Panels
2
S Remote-End I C Master for Peripherals
S Preemphasis Line Driver (MAX9259)/Line
Equalizer (MAX9260)
S Programmable Spread Spectrum on the Serial or
Parallel Data Outputs Reduce EMI
2
through I C (base mode) or a user-defined full-duplex
UART format (bypass mode).
S Deserializer Does Not Require an External Clock
S Auto Data-Rate Detection Allows “On-The-Fly”
The MAX9259 serializer driver preemphasis and chan-
nel equalizer on the MAX9260 extend the link length and
enhance the link reliability. Spread spectrum is available
on the MAX9259/MAX9260 to reduce EMI on the serial
and parallel output data signals. The differential link
complies with the ISO 10605 and IEC 61000-4-2 ESD-
protection standards.
Data-Rate Change
S Input Clock PLL Jitter Attenuator (MAX9259)
S Built-In PRBS Generator/Checker for BER Testing
S Line-Fault Detector Detects Wire Shorts to
Ground, Battery, or Open Link
S ISO 10605 and IEC 61000-4-2 ESD Protection
S -40NC to +105NC Operating Temperature Range
S Patent Pending
The core supplies for the MAX9259/MAX9260 are 1.8V
and 3.3V, respectively. Both devices use an I/O sup-
ply from 1.8V to 3.3V. These devices are available in
a 64-pin TQFP package (10mm x 10mm) and a 56-pin
TQFN package (8mm x 8mm x 0.75mm) with an exposed
pad. Electrical performance is guaranteed over the
-40NC to +105NC automotive temperature range.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9259GCB/V+
-40NC to +105NC 64 TQFP-EP*
MAX9259GCB/V+T -40NC to +105NC 64 TQFP-EP*
MAX9259GTN/V+T -40NC to +105NC 56 TQFN-EP*
Applications
High-Speed Serial-Data Transmission for Display
MAX9260GCB/V+
-40NC to +105NC 64 TQFP-EP*
MAX9260GCB/V+T -40NC to +105NC 64 TQFP-EP*
High-Speed Serial-Data Transmission for Image
Sensing
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Automotive Navigation, Infotainment, and Image-
Sensing Systems
T = Tape and reel.
Typical Applications Circuit appears at end of data sheet.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND
ESD Protection
Human Body Model (R = 1.5kI, C = 100pF)
MAX9259...........................................................-0.5V to +1.9V
MAX9260...........................................................-0.5V to +3.9V
DVDD to GND (MAX9259) ...................................-0.5V to +1.9V
DVDD to DGND (MAX9260).................................-0.5V to +3.9V
IOVDD to GND (MAX9259)..................................-0.5V to +3.9V
IOVDD to IOGND (MAX9260) ..............................-0.5V to +3.9V
Any Ground to Any Ground .................................-0.5V to +0.5V
OUT+, OUT- to AGND (MAX9259) ......................-0.5V to +1.9V
IN+, IN- to AGND (MAX9260)..............................-0.5V to +1.9V
LMN_ to GND (MAX9259)
(60kI source impedance)................................-0.5V to +3.9V
All Other Pins to GND (MAX9259) .......-0.5V to (IOVDD + 0.5V)
All Other Pins to IOGND (MAX9260) ...-0.5V to (IOVDD + 0.5V)
OUT+, OUT- Short Circuit to Ground or
Supply (MAX9259).................................................Continuous
IN+, IN- Short Circuit to Ground or
D
S
(OUT+, OUT-) to AGND (MAX9259) ............................Q8kV
(IN+, IN-) to AGND (MAX9260)....................................Q8kV
All Other Pins to Any Ground (MAX9259) ....................Q4kV
All Other Pins to Any Ground (MAX9260) ....................Q4kV
IEC 61000-4-2 (R = 330I, C = 150pF)
D
S
Contact Discharge
(OUT+, OUT-) to AGND (MAX9259) ..........................Q10kV
(IN+, IN-) to AGND (MAX9260)....................................Q8kV
Air Discharge
(OUT+, OUT-) to AGND (MAX9259) ..........................Q12kV
(IN+, IN-) to AGND (MAX9260)..................................Q10kV
ISO 10605 (R = 2kI, C = 330pF)
D
S
Contact Discharge
(OUT+, OUT-) to AGND (MAX9259) ..........................Q10kV
(IN+, IN-) to AGND (MAX9260)....................................Q8kV
Air Discharge
Supply (MAX9260).................................................Continuous
(OUT+, OUT-) to AGND (MAX9259) ..........................Q25kV
(IN+, IN-) to AGND (MAX9260)..................................Q20kV
Operating Temperature Range........................ -40NC to +105NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Continuous Power Dissipation (T = +70NC)
A
64-Pin TQFP (derate 31.3mW/NC above +70NC).......2508mW
56-Pin TQFN (derate 47.6mW/NC above +70NC)....3809.5mW
PACKAGE THERMAL CHARACTERISTICS (Note 1)
64 TQFP
Junction-to-Ambient Thermal Resistance (B ) .......31.9NC/W
56 TQFN
Junction-to-Ambient Thermal Resistance (B ) ..........21NC/W
JA
JA
Junction-to-Case Thermal Resistance (B ).................1NC/W
Junction-to-Case Thermal Resistance (B ).................1NC/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
MAX9259 DC ELECTRICAL CHARACTERISTICS
(V
DVDD
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 1.8V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (DIN_, PCLKIN, PWDN, SSEN, BWS, ES, DRS, MS, CDS, AUTOS, SD, SCK, WS)
0.65 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH1
V
IOVDD
0.35 x
V
IL1
V
IOVDD
Input Current
I
V
IN
= 0 to V
IOVDD
-10
+10
FA
IN1
Input Clamp Voltage
SINGLE-ENDED OUTPUT (INT)
V
I
= -18mA
-1.5
V
CL
CL
V
IOVDD
- 0.2
High-Level Output Voltage
Low-Level Output Voltage
Output Short-Circuit Current
V
I
I
= -2mA
= 2mA
= 0V
V
V
OH1
OH
V
0.2
64
21
OL1
OL
V
V
= 3.0V to 3.6V
= 1.7V to 1.9V
16
3
35
12
IOVDD
I
V
mA
OS
O
IOVDD
2
______________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259 DC ELECTRICAL CHARACTERISTICS (continued)
(V
DVDD
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 1.8V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, LFLT)
0.7 x
High-Level Input Voltage
V
V
IH2
V
IOVDD
0.3 x
Low-Level Input Voltage
Input Current
V
V
FA
V
IL2
IN2
OL2
V
IOVDD
I
V
= 0 to V
(Note 2)
IOVDD
-110
+5
IN
V
= 1.7V to 1.9V
= 3.0V to 3.6V
0.4
Low-Level Open-Drain Output
Voltage
IOVDD
IOVDD
V
I
OL
= 3mA
V
0.3
DIFFERENTIAL OUTPUT (OUT+, OUT-)
Preemphasis off (Figure 1)
300
350
400
500
610
3.3dB preemphasis setting, V
(Figure 2)
OD(P)
Differential Output Voltage
V
OD
mV
P-P
3.3dB deemphasis setting, V
(Figure 2)
OD(D)
240
425
15
Change in V
Complementary Output States
Between
OD
DV
mV
OD
Output Offset Voltage,
V
Preemphasis off
1.1
-60
1.4
1.56
15
V
OS
(V + + V -)/2 = V
OUT OUT OS
Change in V
Between
OS
DV
mV
mA
OS
Complementary Output States
V
V
or V
or V
= 0V
OUT+
OUT+
OUT-
Output Short-Circuit Current
I
OS
= 1.9V
25
25
OUT-
Magnitude of Differential Output
Short-Circuit Current
I
V
= 0V
OD
mA
OSD
Output Termination Resistance
(Internal)
R
From OUT+, OUT- to V
45
54
63
27
I
O
AVDD
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold
Low Switching Threshold
V
CHR
mV
mV
V
-27
CLR
LINE-FAULT-DETECTION INPUT (LMN_)
Short-to-GND Threshold
Normal Thresholds
V
V
Figure 3
Figure 3
0.3
V
V
TG
TN
0.57
1.45
1.07
V
IO
+
Open Thresholds
V
TO
Figure 3
V
0.06
Open Input Voltage
Short-to-Battery Threshold
POWER SUPPLY
V
Figure 3
Figure 3
1.47
2.47
1.75
V
V
IO
V
TE
f
f
f
f
= 16.6MHz
= 33.3MHz
= 66.6MHz
= 104MHz
100
105
116
135
40
125
145
155
175
110
70
PCLKIN
PCLKIN
PCLKIN
PCLKIN
Worst-Case Supply Current
(Figure 4)
I
BWS = GND
mA
WCS
Sleep-Mode Supply Current
Power-Down Supply Current
I
FA
FA
CCS
CCZ
I
5
= GND
PWDN
_______________________________________________________________________________________
3
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259 AC ELECTRICAL CHARACTERISTICS
(V
DVDD
= V
= 1.7V to 1.9V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 1.8V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK INPUT (PCLKIN)
V
V
V
V
= V
= V
= V
= V
, V
= V
= V
8.33
16.66
6.25
12.5
35
16.66
104
12.5
78
BWS
BWS
BWS
BWS
GND DRS
IOVDD
, V
GND DRS
GND
Clock Frequency
f
MHz
PCLKIN
, V
= V
IOVDD
= V
GND
IOVDD DRS
, V
IOVDD DRS
Clock Duty Cycle
Clock Transition Time
Clock Jitter
DC
t
/t or t
/t (Figure 5)
LOW T
50
65
%
HIGH T
t , t
(Figure 5)
3.125Gbps, 300kHz sinusoidal jitter
4
ns
R
F
t
800
ps
J
(P-P)
2
I C/UART PORT TIMING (Note 3)
30% to 70%, C = 10pF to 100pF, 1kI
pullup to IOVDD
L
Output Rise Time
Output Fall Time
t
20
20
150
150
ns
ns
R
70% to 30%, C = 10pF to 100pF, 1kI
L
t
F
pullup to IOVDD
2
Input Setup Time
Input Hold Time
t
I C only (Figure 6)
100
0
ns
ns
SET
2
t
I C only (Figure 6)
HOLD
SWITCHING CHARACTERISTICS (Note 3)
Differential Output Rise-and-Fall
Time
20% to 80%, V
serial-data rate = 3.125Gbps
≥ 400mV, R = 100I,
OD L
t , t
90
150
ps
UI
R
F
3.125Gbps PRBS signal, measured at
Total Serial Output Jitter
t
V
OD
= 0V differential, preemphasis
0.25
0.15
TSOJ1
disabled (Figure 7)
Deterministic Serial Output Jitter
Parallel Data Input Setup Time
Parallel Data Input Hold Time
t
3.125Gbps PRBS signal
(Figure 8)
UI
ns
ns
DSOJ2
t
1
SET
t
(Figure 8)
1.5
HOLD
Spread spectrum enabled
Spread spectrum disabled
2830
270
3.5
Serializer Delay (Note 4)
t
(Figure 9)
Bits
SD
Link Start Time
Power-Up Time
t
(Figure 10)
(Figure 11)
ms
ms
LOCK
t
3.5
PU
2
I S INPUT TIMING
WS Frequency
f
(Table 4)
(Table 4)
8
4
192
32
kHz
Bits
WS
Sample Word Length
n
WS
(8 x 4)
x 2
(192 x
32) x 2
SCK Frequency
f
f
= f
x n x 2
WS
kHz
ns
SCK
SCK
WS
0.35 x
SCK Clock High Time (Note 3)
SCK Clock Low Time (Note 3)
t
V
≥ V , t
= 1/f
HC
SCK
SCK
IH SCK
SCK
t
SCK
0.35 x
t
V
≤ V , t
= 1/f
ns
LC
IL SCK
SCK
t
SCK
SD, WS Setup Time
SD, WS Hold Time
t
(Figure 12, Note 3)
(Figure 12, Note 3)
2
ns
ns
SET
t
2
HOLD
4
______________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 DC ELECTRICAL CHARACTERISTICS
(V
DVDD
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 3.3V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (ENABLE, INT, PWDN, SSEN, BWS, ES, DRS, MS, CDS, EQS, DCS)
0.65 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH1
V
IOVDD
0.35 x
V
IL1
V
IOVDD
Input Current
I
V
IN
= 0 to V
IOVDD
-10
+10
FA
IN1
Input Clamp Voltage
V
I
= -18mA
-1.5
V
CL
CL
SINGLE-ENDED OUTPUTS (DOUT_, SD, WS, SCK, PCLKOUT)
V
IOVDD
- 0.3
V
= V
= V
DCS
IOGND
High-Level Output Voltage
Low-Level Output Voltage
V
I
= -2mA
= 2mA
V
V
OH
OH
OL
V
IOVDD
- 0.2
V
DCS
IOVDD
V
V
= V
= V
0.3
0.2
DCS
IOGND
IOVDD
V
V
OL1
I
DCS
=
IOVDD
15
3
25
7
39
13
63
21
50
17
97
32
3.0V to 3.6V
V
V
= 0V,
DCS
O
= V
IOGND
IOVDD
IOGND
IOVDD
V
=
IOVDD
DOUT_,
SD, WS,
SCK
1.7V to 1.9V
V
=
IOVDD
20
5
35
10
33
10
54
16
3.0V to 3.6V
V
O
V
= 0V,
DCS
= V
V
=
IOVDD
1.7V to 1.9V
Output Short-Circuit Current
I
mA
OS
V
=
IOVDD
15
5
3.0V to 3.6V
V
O
V
= 0V,
DCS
= V
V
=
IOVDD
1.7V to 1.9V
PCLKOUT
V
=
IOVDD
30
9
3.0V to 3.6V
V
O
V
= 0V,
DCS
= V
V
=
IOVDD
1.7V to 1.9V
2
I C AND UART I/O, OPEN-DRAIN OUTPUTS (RX/SDA, TX/SCL, ERR, GPIO_, LOCK)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
Input Current
V
V
V
IH2
V
IOVDD
0.3 x
V
IL2
IN2
OL2
V
IOVDD
RX/SDA, TX/SCL
-110
-80
+1
V
= 0 to V
IOVDD
IN
I
FA
(Note 2)
+1
GPIO, ERR, LOCK
V
= 1.7V to 1.9V
= 3.0V to 3.6V
0.4
V
V
Low-Level Open-Drain Output
Voltage
IOVDD
IOVDD
V
I
OL
= 3mA
V
0.3
_______________________________________________________________________________________
5
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 DC ELECTRICAL CHARACTERISTICS (continued)
(V
DVDD
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 3.3V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIFFERENTIAL OUTPUTS FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Differential High Output Peak
Voltage, (V +) - (V -)
No high-speed data transmission
(Figure 13)
V
30
60
mV
mV
ROH
IN
IN
Differential Low Output Peak
Voltage, (V +) - (V -)
No high-speed data transmission
(Figure 13)
V
-60
-30
ROL
IN
IN
DIFFERENTIAL INPUTS (IN+, IN-)
Differential High Input Threshold
V
(Figure 14)
(Figure 14)
40
-40
1.3
100
90
mV
mV
V
IDH(P)
(Peak), (V +) - (V -)
IN
IN
Differential Low Input Threshold
(Peak), (V +) - (V -)
V
-90
1
IDL(P)
IN
IN
Input Common-Mode Voltage,
((V +) + (V -))/2
V
1.6
CMR
IN
IN
Differential Input Resistance
(Internal)
R
I
80
130
I
POWER SUPPLY
2% spread
spectrum active
113
105
122
110
137
120
159
135
166
155
181
165
211
188
247
214
V
BWS
= V
,
IOGND
f
= 16.6MHz
PCLKOUT
Spread spectrum
disabled
2% spread
spectrum active
V
BWS
= V
,
IOGND
f
= 33.3MHz
PCLKOUT
Spread spectrum
disabled
Worst-Case Supply Current
(Figure 15)
I
mA
WCS
2% spread
spectrum active
V
= V
,
BWS
IOGND
f
= 66.6MHz
PCLKOUT
Spread spectrum
disabled
2% spread
spectrum active
V
= V
,
BWS
IOGND
f
= 104MHz
PCLKOUT
Spread spectrum
disabled
Sleep-Mode Supply Current
Power-Down Supply Current
I
80
19
130
70
FA
FA
CCS
I
V
= V
IOGND
CCZ
PWDN
6
______________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 AC ELECTRICAL CHARACTERISTICS
(V
DVDD
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 3.3V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PARALLEL CLOCK OUTPUT (PCLKOUT)
V
V
V
V
= V
= V
= V
= V
, V
= V
= V
8.33
16.66
6.25
12.5
40
16.66
104
12.5
78
BWS
BWS
BWS
BWS
IOGND DRS
IOVDD
IOGND
IOVDD
IOGND
, V
IOGND DRS
Clock Frequency
f
MHz
PCLKOUT
DC
, V
= V
= V
IOVDD DRS
, V
IOVDD DRS
Clock Duty Cycle
Clock Jitter
t
/t or t
/t (Figure 16)
LOW T
50
60
%
HIGH T
Period jitter, RMS, spread off, 3.125Gbps,
PRBS pattern, UI = 1/f
t
0.05
UI
J
PCLKOUT
2
I C/UART PORT TIMING
30% to 70%, C = 10pF to 100pF, 1kI
pullup to IOVDD
L
Output Rise Time
Output Fall Time
t
20
20
150
150
ns
ns
R
70% to 30%, C = 10pF to 100pF, 1kI
L
t
F
pullup to IOVDD
2
Input Setup Time
t
I C only
100
0
ns
ns
SET
2
Input Hold Time
t
I C only
HOLD
SWITCHING CHARACTERISTICS
V
= V
,
DCS
IOVDD
0.4
0.5
0.25
0.3
0.5
0.6
0.3
0.4
2.2
2.8
1.7
2.0
3.1
3.8
2.2
2.4
C = 10pF
L
20% to 80%,
= 1.7V to 1.9V
V
IOVDD
V
= V
,
DCS
IOGND
C = 5pF
L
PCLKOUT Rise-and-Fall Time
t , t
ns
R
F
V
= V
,
DCS
IOVDD
C = 10pF
L
20% to 80%,
= 3.0V to 3.6V
V
IOVDD
V
= V
,
DCS
IOGND
C = 5pF
L
V
= V
,
DCS
IOVDD
C = 10pF
L
20% to 80%,
= 1.7V to 1.9V
V
IOVDD
V
= V
,
DCS
IOGND
C = 5pF
L
Parallel Data Rise-and-Fall Time
(Figure 17)
t , t
ns
R
F
V
= V
,
DCS
IOVDD
C = 10pF
L
20% to 80%,
= 3.0V to 3.6V
V
IOVDD
V
= V
,
DCS
IOGND
C = 5pF
L
Spread spectrum enabled (Figure 18)
Spread spectrum disabled (Figure 18)
Spread spectrum enabled (Figure 19)
Spread spectrum off (Figure 19)
(Figure 20)
2880
750
Deserializer Delay
t
Bits
SD
1500
1000
2500
Lock Time
t
Fs
Fs
ns
LOCK
Power-Up Time
t
PU
Reverse Control-Channel Output
Rise Time
t
No high-speed transmission (Figure 13)
No high-speed transmission (Figure 13)
180
180
400
400
R
Reverse Control-Channel Output
Fall Time
t
F
ns
_______________________________________________________________________________________
7
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 AC ELECTRICAL CHARACTERISTICS (continued)
(V
DVDD
= V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100IQ1% (differential), T = -40NC to +105NC, unless otherwise noted.
IOVDD L A
AVDD
Typical values are at V
= V
= V = 3.3V, T = +25NC.)
IOVDD A
DVDD
AVDD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I S OUTPUT TIMING
f
= 48kHz or
0.4e - 3 0.5e - 3
x t x t
WS
44.1kHz
WS
WS
t
= 1/f , rising
WS
WS
(falling) edge to
falling (rising) edge
(Note 5)
0.8e - 3 1e - 3
x t x t
WS Jitter
t
f
= 96kHz
ns
AJ-WS
WS
WS
WS
WS
1.6e - 3 2e - 3
x t x t
f
= 192kHz
= 16 bits,
WS
WS
n
13e - 3 16e - 3
x t x t
WS
f
= 48kHz or 44.1kHz
WS
SCK
SCK
t
= 1/f
, rising n
= 24 bits,
= 96kHz
39e - 3 48e - 3
SCK
SCK
WS
SCK Jitter
t
ns
AJ-SCK
edge to rising edge f
x t
SCK
x t
WS
SCK
SCK
n
= 32 bits,
= 192kHz
0.1
0.13
WS
f
x t
SCK
x t
WS
Audio Skew Relative to Video
Video and audio synchronized
3 x t
4 x t
µs
ns
ns
ASK
WS
WS
V
= V
, C = 10pF
0.3
0.4
3.1
3.8
DCS
DCS
IOVDD
IOGND
L
SCK, SD, WS Rise-and-Fall Time
t , t
20% to 80%
R
F
DVB
DVA
V
= V
, C = 5pF
L
0.35
0.5
SD, WS Valid Time Before SCK
SD, WS Valid Time After SCK
t
t
t
t
= 1/f
= 1/f
(Figure 21)
(Figure 21)
ns
ns
SCK
SCK
x t
SCK
x t
SCK
0.35
x t
0.5
SCK
SCK
x t
SCK
SCK
Note 2: Minimum I due to voltage drop across the internal pullup resistor.
IN
Note 3: Not production tested.
Note 4: Bit time = 1/(30 x f ) (BWS = 0), = 1/(40 x f ) (BWS = V
RXCLKIN RXCLKIN
).
IOVDD
Note 5: Rising to rising edge jitter can be twice as large.
Typical Operating Characteristics
(V
DVDD
= V
= V
= 1.8V (MAX9259), V
= V
= V
= 3.3V (MAX9260), T = +25NC, unless otherwise noted.)
AVDD
IOVDD
DVDD
AVDD
IOVDD A
MAX9260 SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (24-BIT MODE)
MAX9259 SUPPLY CURRENT
vs. PCLKIN FREQUENCY (24-BIT MODE)
MAX9259 SUPPLY CURRENT
vs. PCLKIN FREQUENCY (32-BIT MODE)
135
130
125
120
115
110
105
100
95
135
130
125
120
115
110
105
100
95
155
150
145
140
135
130
125
120
115
110
105
ALL EQUALIZER SETTINGS
PREEMPHASIS =
0x0B TO 0x0F
PREEMPHASIS =
0x0B TO 0x0F
PREEMPHASIS =
0x01 TO 0x04
PREEMPHASIS =
0x01 TO 0x04
PREEMPHASIS = 0x00
PREEMPHASIS = 0x00
90
90
5
25
45
65
85
105
5
20
35
50
65
80
5
25
45
65
85
105
PCLKIN FREQUENCY (MHz)
PCLKIN FREQUENCY (MHz)
PCLKOUT FREQUENCY (MHz)
8
______________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Typical Operating Characteristics (continued)
(V
DVDD
= V
= V
= 1.8V (MAX9259), V
= V
= V
= 3.3V (MAX9260), T = +25NC, unless otherwise noted.)
AVDD
IOVDD
DVDD
AVDD
IOVDD A
MAX9260 SUPPLY CURRENT
MAX9260 SUPPLY CURRENT
MAX9260 SUPPLY CURRENT
vs. PCLKOUT FREQUENCY (32-BIT MODE)
vs. PCLKOUT FREQUENCY (24-BIT MODE)
vs. PCLKOUT FREQUENCY (32-BIT MODE)
180
170
160
150
140
130
120
110
100
180
170
160
150
140
130
120
110
100
155
ALL EQUALIZER SETTINGS
150
145
140
135
130
125
120
115
110
105
2%, 4% SPREAD
2%, 4% SPREAD
NO SPREAD
NO SPREAD
5
25
45
65
85
105
5
20
35
50
65
80
5
20
35
50
65
80
PCLKOUT FREQUENCY (MHz)
PCLKOUT FREQUENCY (MHz)
PCLKOUT FREQUENCY (MHz)
OUTPUT POWER SPECTRUM
vs. PCLKOUT FREQUENCY
SERIAL LINK SWITCHING PATTERN
WITHOUT PREEMPHASIS
SERIAL LINK SWITCHING PATTERN
WITH 14dB PREEMPHASIS
(MAX9259 SPREAD ON, MAX9260 SPREAD OFF)
(PARALLEL BIT RATE = 104MHz, 10m STP CABLE) (PARALLEL BIT RATE = 104MHz, 10m STP CABLE)
MAX9259/60 toc07
MAX9259/60 toc08
0
3.12Gbps
f
= 20MHz
400.0mV
3.12Gbps
250.0mV
PCLKOUT
-10
-20
-30
-40
-50
-60
-70
-80
0% SPREAD
0.5% SPREAD
-400.0mV
52.00ps/div
-250.0mV
52.00ps/div
2% SPREAD 4% SPREAD
18.5 19.0 19.5 20.0 20.5 21.0 21.5
PCLKOUT FREQUENCY (MHz)
OUTPUT POWER SPECTRUM
OUTPUT POWER SPECTRUM
MAXIMUM PCLKIN FREQUENCY vs.
STP CABLE LENGTH (BER < 10 )
vs. PCLKOUT FREQUENCY
vs. PCLKOUT FREQUENCY
(MAX9259 SPREAD ON, MAX9260 SPREAD OFF)
(MAX9260 SPREAD ON, MAX9259 SPREAD OFF)
-9
0
0
120
100
80
60
40
20
0
f
= 42MHz
f
= 42MHz
PCLKOUT
PCLKOUT
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-50
-60
-70
-80
0.5% SPREAD
0% SPREAD
0% SPREAD
OPTIMUM PE/EQ
SETTINGS
NO PE, EQS = LOW
NO PE, EQS = HIGH
-12
BER CAN BE < 10 FOR
2% SPREAD
41
PCLKOUT FREQUENCY (MHz)
4% SPREAD
2% SPREAD
41
4% SPREAD
43
CABLE LENGTHS LESS THAN 10m
39
40
42
43
44
45
39
40
42
44
45
0
5
10
15
20
PCLKOUT FREQUENCY (MHz)
CABLE LENGTH (m)
_______________________________________________________________________________________
9
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Pin Configurations
TOP VIEW
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
32
31
30
49
50
32
31
30
DOUT8
IOGND
DOUT24
IOGND
IOVDD
DIN0
GND
MS
GND
IOVDD
IOVDD 51
DOUT7 52
IOVDD 51
DIN1 52
29 DOUT25
29 AUTOS
53
54
55
28
27
53
54
55
28
27
DOUT6
DOUT5
DOUT4
DOUT26
DOUT27
DIN2
DIN3
DIN4
WS
SCK
26 DOUT28/MCLK
25 SD
26 SD
DOUT3 56
DOUT2
DIN5 56
DIN6 57
DIN7 58
DIN8 59
DIN9 60
GND 61
25 DIN28
MAX9260
MAX9259
24
23
22
21
20
19
18
17
57
SCK
24
23
22
21
20
19
18
17
DIN27
DIN26
DIN25
DIN24
GND
DOUT1 58
DOUT0 59
IOGND 60
WS
LOCK
IOGND
ERR
SSEN
DRS
61
62
63
64
62
PWDN
TX/SCL
RX/SDA
DVDD
DVDD
AGND
DIN23
EP*
EP*
AVDD
AGND
DIN10 63
DIN11 64
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
TQFP
(10mm × 10mm × 1mm)
TQFP
(10mm × 10mm × 1mm)
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
22
21
20
DIN0
CDS
43
44
IOVDD
MS
DIN1 45
DIN2 46
DIN3 47
DIN4 48
DIN5 49
DIN6 50
DIN7 51
DIN8 52
DIN9 53
DVDD 54
DIN10 55
DIN11 56
IOVDD
AUTOS
WS
SCK
SD
MAX9259
DIN28
DIN27
19 DIN26
18 DIN25
17 DIN24
16 DVDD
15 DIN23
EP*
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14
TQFN
(8mm x 8mm x 0.75mm)
*CONNECT EP TO GROUND PLANE
10 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259 Pin Description
PIN
NAME
FUNCTION
TQFP
TQFN
1–5, 11–17, 1–5, 9–15,
Data Input[0:28]. Parallel data inputs. All pins internally pulled down to GND. Selected
edge of PCLKIN latches input data. Set BWS = low (24-bit mode) to use DIN0–DIN20
(RGB and SYNC). DIN21–DIN28 are not used in 24-bit mode. Set BWS = high (32-bit
mode) to use DIN0–DIN28 (RGB, SYNC, and two extra inputs).
21–25, 49,
52–60, 63,
64
17–21, 43,
45–53, 55,
56
DIN0–
DIN28
6
6
PCLKIN Parallel Clock Input. Latches parallel data inputs and provides the PLL reference clock.
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with
IOVDD 0.1FF and 0.001FF capacitors as close as possible to the device with the smaller value
capacitor closest to IOVDD.
7, 30, 51
7, 26, 44
8, 20, 31,
50, 61
—
—
GND
AGND
AVDD
Digital and I/O Ground
Analog Ground
9, 18, 39
1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller value capacitor closest to AVDD.
10, 42
8, 36
1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller value capacitor closest to DVDD.
19, 62
26
16, 54
22
DVDD
SD
2
2
I S Serial-Data Input with Internal Pulldown to GND. Disable I S to use SD as an
additional data input latched on the selected edge of PCLKIN.
2
27
28
23
24
SCK
WS
I S Serial-Clock Input with Internal Pulldown to GND
2
I S Word-Select Input with Internal Pulldown to GND
Autostart Setting. Active-low power-up mode selection input requires external pulldown or
pullup resistors. Set AUTOS = high to power up the device with no link active. Set AUTOS
= low to have the MAX9259 power up the serial link with autorange detection (see Tables
13 and 14).
29
25
AUTOS
Mode Select. Control-link mode-selection input requires external pulldown or pullup
resistors. Set MS = low, to select base mode. Set MS = high to select the bypass mode.
32
33
34
35
27
28
29
30
MS
CDS
Control-Direction Selection. Control-link-direction selection input requires external
pulldown or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial
link. Set CDS = high for FC use on the MAX9260 side of the serial link.
Power-Down. Active-low power-down input requires external pulldown or pullup
resistors.
PWDN
2
Receive/Serial Data. UART receive or I C serial-data input/output with internal 30kI
2
RX/SDA pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9259’s UART. In I C
2
mode, RX/SDA is the SDA input/output of the MAX9259’s I C master.
______________________________________________________________________________________ 11
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9259 Pin Description (continued)
PIN
NAME
FUNCTION
TQFP
TQFN
2
Transmit/Serial Clock. UART transmit or I C serial-clock output with internal 30kI
2
36
31
TX/SCL pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In I C
2
mode, TX/SCL is the SCL output of the MAX9259’s I C master.
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external
pulldown or pullup resistors. The state of SSEN latches upon power-up or when resuming
from power-down mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on
37
32
SSEN
the serial link. Set SSEN = low to use the serial link without spread spectrum.
38
40, 41
43
33
34, 35
37
LMN1
Line-Fault Monitor Input 1 (see Figure 3 for details)
Differential CML Output -/+. Differential outputs of the serial link.
Line-Fault Monitor Input 0 (see Figure 3 for details)
OUT-,
OUT+
LMN0
Line Fault. Active-low open-drain line-fault output with a 60kIinternal pullup resistor.
LFLT = low indicates a line fault. LFLT is high impedance when PWDN = low.
44
38
LFLT
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when
PWDN = low. A transition on the INT input of the MAX9260 toggles the MAX9259’s INT
output.
45
46
39
40
INT
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data rates
of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
DRS
Edge Select. PCLKIN trigger edge-selection input requires external pulldown or pullup
resistors. Set ES = low to trigger on the rising edge of PCLKIN. Set ES = high to trigger on
the falling edge of PCLKIN.
47
48
—
41
42
—
ES
BWS
EP
Bus-Width Select. Parallel input bus-width selection input requires external pulldown or
pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus mode.
Exposed Pad. EP internally connected to AGND (TQFP package) or AGND and GND
(TQFN package). MUST externally connect EP to the AGND plane to maximize thermal
and electrical performance.
12 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 Pin Description
PIN
NAME
FUNCTION
Enable. Active-low parallel output-enable input requires external pulldown or pullup
resistors. Set ENABLE = low to enable PCLKOUT, SD, SCK, WS, and the parallel out-
puts, DOUT_. Set ENABLE = high to put PCLKOUT, SD, SCK, WS, and DOUT_ to high
impedance.
1
ENABLE
Bus-Width Select. Parallel output bus-width selection input requires external pulldown
or pullup resistors. Set BWS = low for 24-bit bus mode. Set BWS = high for 32-bit bus
mode.
2
3
4
BWS
INT
Interrupt. Interrupt input requires external pulldown or pullup resistors. A transition on
the INT input of the MAX9260 toggles the MAX9259’s INT output.
Control-Direction Selection. Control-link-direction selection input requires external pull-
down or pullup resistors. Set CDS = low for FC use on the MAX9259 side of the serial
link. Set CDS = high for FC use on the MAX9260 side of the serial link.
CDS
GPIO0. Open-drain general-purpose input/output with internal 60kI pullup resistors to
IOVDD. GPIO0 is high impedance during power-up and when PWDN = low.
5
6
GPIO0
ES
Edge Select. PCLKOUT edge-selection input requires external pulldown or pullup
resistors. Set ES = low for a rising-edge trigger. Set ES = high for a falling-edge trigger.
3.3V Analog Power Supply. Bypass AVDD to AGND with 0.1µF and 0.001µF capacitors
as close as possible to the device with the smallest value capacitor closest to AVDD.
7, 63
AVDD
8 , 9
IN+, IN-
AGND
Differential CML Input +/-. Differential inputs of the serial link.
10, 64
Analog Ground
Equalizer Select. Deserializer equalizer-selection input requires external pulldown or
pullup resistors. The state of EQS latches upon power-up or rising edge of PWDN. Set
EQS = low for 10.7dB equalizer boost (EQTUNE = 1001). Set EQS = high for 5.2dB
equalizer boost (EQTUNE = 0100).
11
12
13
EQS
GPIO1
DCS
GPIO1. Open-drain general-purpose input/output with internal 60kI pullup resistors to
IOVDD. GPIO1 is high impedance during power-up and when PWDN = low.
Drive Current Select. Driver current-selection input requires external pulldown or pul-
lup resistors. Set DCS = high for stronger parallel data and clock output drivers. Set
DCS = low for normal parallel data and clock drivers (see the MAX9260 DC Electrical
Characteristics table).
Mode Select. Control-link mode-selection/autostart mode selection input requires
external pulldown or pullup resistors. MS sets the control-link mode when CDS = high
(see the Control-Channel and Register Programming section). Set MS = low to select
base mode. Set MS = high to select the bypass mode. MS sets autostart mode when
CDS = low (see Tables 13 and 14).
14
MS
3.3V Digital Power Supply. Bypass DVDD to DGND with 0.1FF and 0.001FF capacitors
as close as possible to the device with the smaller value capacitor closest to DVDD.
15
16
DVDD
DGND
Digital Ground
2
Receive/Serial Data. UART receive or I C serial-data input/output with internal 30kI
17
RX/SDA
pullup to IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9260’s UART. In
I C mode, RX/SDA is the SDA input/output of the MAX9259’s I C master.
2
2
______________________________________________________________________________________ 13
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 Pin Description (continued)
PIN
NAME
FUNCTION
2
Transmit/Serial Clock. UART transmit or I C serial-clock output with internal 30kI
18
TX/SCL
pullup to IOVDD. In UART mode, TX/SCL is the Tx output of the MAX9259’s UART. In
I C mode, TX/SCL is the SCL output of the MAX9260’s I C master.
2
2
Power-Down. Active-low power-down input requires external pulldown or pullup resis-
tors.
19
PWDN
Error. Active-low open-drain video data error output with internal pullup to IOVDD.
ERR goes low when the number of decoding errors during normal operation exceed a
programmed error threshold or when at least one PRBS error is detected during PRBS
test. ERR is high impendence when PWDN = low.
20
21, 31, 50, 60
22
ERR
IOGND
LOCK
Input/Output Ground
Open-Drain Lock Output with Internal Pullup to IOVDD. LOCK = high indicates PLLs
are locked with correct serial-word-boundary alignment. LOCK = low indicates PLLs
are not locked or incorrect serial-word-boundary alignment. LOCK remains low when
the configuration link is active. LOCK is high impedance when PWDN = low.
2
23
24
WS
Word Select. I S word-select output.
2
SCK
Serial Clock. I S serial-clock output
2
2
Serial Data. I S serial-data output. Disable I S to use SD as an additional data output
latched on the selected edge of PCLKOUT.
25
SD
Data Output[0:28]. Parallel data outputs. Output data can be strobed on the selected
edge of PCLKOUT. Set BWS = low (24-bit mode) to use DOUT0–DOUT20 (RGB and
SYNC). DOUT21–DOUT28 are not used in 24-bit mode and are set to low. Set BWS =
high (32-bit mode) to use DOUT0–DOUT28 (RGB, SYNC, and two extra outputs).
DOUT28 can be used to output MCLK (see the Additional MCLK Output for Audio
Applications section).
DOUT0–
DOUT27,
DOUT28/MCLK
26–29, 32–40,
42–49, 52–59
1.8V to 3.3V Logic I/O Power Supply. Bypass IOVDD to IOGND with 0.1FF and 0.001FF
capacitors as close as possible to the device with the smaller value capacitor closest
to IOVDD.
30, 51
41
IOVDD
PCLKOUT
Parallel Clock Output. Used for DOUT0–DOUT28.
Spread-Spectrum Enable. Parallel output spread-spectrum enable input requires
external pulldown or pullup resistors. The state of SSEN latches upon power-up or
when resuming from power-down mode (PWDN = low). Set SSEN = high for Q2%
spread spectrum on the parallel outputs. Set SSEN = low to use the parallel outputs
without spread spectrum.
61
SSEN
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup
resistors. Set DRS = high for parallel input data rates of 8.33MHz to 16.66MHz (24-bit
mode) or 6.25MHz to 12.5MHz (32-bit mode). Set DRS = low for parallel input data
rates of 16.66MHz to 104MHz (24-bit mode) or 12.5MHz to 78MHz (32-bit mode).
62
—
DRS
EP
Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the
AGND plane to maximize thermal and electrical performance.
14 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Functional Diagram
LFLT
PCLKIN
FILTER
PLL
SPREAD
PLL
LMN0
LMN1
LINE-
FAULT
DET
CLKDIV
8B/10B
ENCODE
PARITY
DIN[N:0]
CML
Tx
FIFO
P
S
OUT+
OUT-
WS, SD, SCK
AUDIO
FIFO
PRBS
GEN
TERM
MAX9259
TX/SCL
RX/SDA
REV CH
Rx
2
UART/I C
SERIALIZER
SPREAD
PLL
CDR
PLL
STP CABLE
(Z = 50)
PCLKOUT
DOUT[N:0]
EQ
0
CLKDIV
8B/10B
DECODE
PARITY
CML
Rx
FIFO
P
S
IN-
IN+
WS, SD, SCK
AUDIO
FIFO
PRBS
CHECK
TERM
MAX9260
TX/SCL
RX/SDA
REV CH
Tx
2
UART/I C
DESERIALIZER
______________________________________________________________________________________ 15
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
R /2
L
OUT+
V
OD
V
OS
OUT-
R /2
L
GND
((OUT+) + (OUT-))/2
OUT-
OUT+
V
V
OS(+)
V
OS(-)
OS(-)
DV = |V
- V
|
OS
OS(+) OS(-)
V (+)
OD
V
= 0V
OD
V
OD(-)
V
OD(-)
DV = |V
- V
|
OD(+) OD(-)
OD
(OUT+) - (OUT-)
Figure 1. MAX9259 Serial Output Parameters
OUT+
V
V
OD(D)
OD(P)
V
OS
OUT-
SERIAL-BIT
TIME
Figure 2. Output Waveforms at OUT+ and OUT-
16 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
1.7V TO 1.9V
MAX9259
45.3kI*
45.3kI*
LMN0
LMN1
OUTPUT
LOGIC
4.99kI*
4.99kI*
(OUT+)
TWISTED PAIR
OUT+
OUT-
49.9kI*
49.9kI*
CONNECTORS
2.1V
LFLT
REFERENCE
VOLTAGE
GENERATOR
1.5V
0.5V
OUTPUT
LOGIC
(OUT-)
*Q1% TOLERANCE
Figure 3. Fault-Detector Circuit
PCLKIN
DIN_
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
Figure 4. MAX9259 Worst-Case Pattern Input
______________________________________________________________________________________ 17
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
t
T
V
IH MIN
t
HIGH
PCLKIN
V
IL MAX
t
R
t
F
t
LOW
Figure 5. MAX9259 Parallel Input Clock Requirements
t
F
t
R
TX/
SCL
t
t
HOLD
SET
RX/
SDA
S
P
S
P
2
Figure 6. I C Timing Parameters
800mV
t
t
TSOJ1
2
TSOJ1
2
Figure 7. Differential Output Template
18 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
V
IH MIN
PCLKIN
V
IL MAX
t
t
HOLD
SET
V
V
V
V
IH MIN
IH MIN
IL MAX
DIN_
IL MAX
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. MAX9259 Input Setup-and-Hold Times
EXPANDED TIME SCALE
DIN_
N
N+2
N+3
N+4
N+1
PCLKIN
OUT+/-
N-1
N
t
SD
FIRST BIT
LAST BIT
Figure 9. MAX9259 Serializer Delay
______________________________________________________________________________________ 19
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
PCLKIN
t
LOCK
350Fs
SERIAL LINK INACTIVE
SERIAL LINK ACTIVE
REVERSE CONTROL CHANNEL
DISABLED
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL
AVAILABLE
PWDN MUST BE HIGH
Figure 10. MAX9259 Link Startup Time
PCLKIN
V
IH1
PWDN
t
PU
POWERED UP,
SERIAL LINK INACTIVE
POWERED DOWN
POWERED UP, SERIAL LINK ACTIVE
350µs
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
Figure 11. MAX9259 Power-Up Delay
WS
SCK
SD
t
SCK
t
t
SET
HOLD
t
LC
t
t
t
HC
HOLD
SET
2
Figure 12. MAX9259 Input I S Timing Parameters
20 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
R /2
L
IN+
MAX9260
V
OD
REVERSE
CONTROL-CHANNEL
TRANSMITTER
V
CMR
IN-
R /2
L
IN+
IN-
IN-
V
CMR
IN+
V
ROH
0.9 x V
ROH
0.1 x V
ROH
(IN+) - (IN-)
0.1 x V
ROL
t
R
0.9 x V
ROL
V
ROL
t
F
Figure 13. MAX9260 Reverse Control-Channel Output Parameters
R /2
L
IN+
IN-
PCLKOUT
DOUT_
V
ID(P)
R /2
L
_
V
IN+
+
_
C
C
IN
IN
+
V
IN-
_
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCH EDGE.
V | V - V |
ID(P) = IN+ IN-
V (V + V )/2
CMR = IN+ IN-
Figure 15. MAX9260 Worst-Case Pattern Output
Figure 14. MAX9260 Test Circuit for Differential Input Measurement
______________________________________________________________________________________ 21
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
t
T
V
OH MIN
t
HIGH
PCLKOUT
V
OL MAX
t
LOW
Figure 16. MAX9260 Clock Output High-and-Low Times
C
L
MAX9260
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VCC
0.2 x V
I0VCC
t
t
F
R
Figure 17. MAX9260 Output Rise-and-Fall Times
SERIAL-WORD LENGTH
SERIAL WORD N
SERIAL WORD N+1
SERIAL WORD N+2
IN+/-
FIRST BIT
LAST BIT
DOUT_
PARALLEL WORD N-1
PARALLEL WORD N
PARALLEL WORD N-2
PCLKOUT
t
SD
NOTE: PCLKOUT PROGRAMMED FOR RISING LATCHING EDGE.
Figure 18. MAX9260 Deserializer Delay
22 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
IN+ - IN-
t
LOCK
LOCK
V
OH
PWDN MUST BE HIGH
Figure 19. MAX9260 Lock Time
IN+/-
V
PWDN
IH1
t
PU
LOCK
V
OH
Figure 20. MAX9260 Power-Up Delay
WS
t
t
t
R
DVA
DVB
SCK
SD
t
t
t
F
DVB
DVA
2
Figure 21. MAX9260 Output I S Timing Parameters
______________________________________________________________________________________ 23
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
side, such as backlight control, grayscale gamma cor-
rection, camera module, and touch screen. All serial
Detailed Description
The MAX9259/MAX9260 chipset presents Maxim’s
communication (forward and reverse) uses differential
GMSL technology. The MAX9259 serializer pairs with the
MAX9260 deserializer to form a complete digital serial
link for joint transmission of high-speed video, audio,
and control data for video-display or image-sensing
applications. The serial-payload data rate can reach up
to 2.5Gbps for a 15m STP cable. The parallel interface
is programmable for 24-bit or 32-bit width modes at the
maximum bus clock of 104MHz or 78MHz, respectively.
The minimum bus clock is 6.25MHz for the 32-bit mode
and 8.33MHz for the 24-bit mode. With such a flexible
data configuration, the GMSL is able to support XGA
(1280 x 768) or dual-view WVGA (2 x 854 x 480) display
panels. For image sensing, it supports three 10-bit cam-
era links simultaneously with a pixel clock up to 78MHz.
The 24-bit mode handles 21-bit data and control signals
2
signaling. The peripheral programming uses I C format
or the default GMSL UART format. A separate bypass
mode enables communication using a full-duplex, user-
defined UART format. The control link between the
MAX9259 and MAX9260 allows FC connectivity to either
device or peripherals to support video-display or image-
sensing applications.
The AC-coupled serial link uses 8B/10B coding. The
MAX9259 serializer features a programmable driver
preemphasis and the MAX9260 deserializer features
a programmable channel equalizer to extend the link
length and enhance the link reliability. Both devices have
a programmable spread-spectrum feature for reducing
EMI on the serial link output (MAX9259) and parallel data
outputs (MAX9260). The differential serial link input and
output pins comply with the ISO 10605 and IEC 61000-
4-2 ESD-protection standards. The core supplies for the
MAX9259/MAX9260 are 1.8V and 3.3V, respectively.
Both devices use an I/O supply from 1.8V to 3.3V
2
plus an I S audio signal. The 32-bit mode handles 29-bit
2
data and control signals plus an I S audio signal. Any
combination and sequence of color video data, video
sync, and control signals make up the 21-bit or 29-bit
2
parallel data on DIN_ and DOUT_. The I S port supports
the sampled audio data at a rate from 8kHz to 192kHz
and the audio word length of anywhere between 4 to
32 bits. The embedded control channel forms a UART
link between the serializer and deserializer. The UART
link can be set to half-duplex mode or full-duplex mode
depending on the application. The GMSL supports
UART rates from 100kbps to 1Mbps. Using this control
link, a host ECU or FC communicates with the serializer
and deserializer, as well as the peripherals in the remote
Register Mapping
The FC configures various operating conditions of the
GMSL through registers in the MAX9259/MAX9260.
The default device addresses stored in the R0 and
R1 registers of the MAX9259/MAX9260 are 0x80 and
0x90, respectively. Write to the R0/R1 registers in both
devices to change the device address of the MAX9259
or MAX9260.
Table 1. MAX9259 Power-Up Default Register Map (see Table 18)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SERID =1000000, serializer device address is 1000 000
RESERVED = 0
0x00
0x01
0x80
0x90
DESID =1001000, deserializer device address is 1001 000
RESERVED = 0
SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings
depend on SSEN pin state at power-up
2
0x02
0x03
0x1F, 0x3F
0x00
AUDIOEN = 1, I S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking
SDIV = 000000, auto calibrate sawtooth divider
24 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 1. MAX9259 Power-Up Default Register Map (see Table 18) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default
depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0 or 1, sleep mode state depends on CDS and AUTOS pin state at
power-up (see the Link Startup Procedure section)
0x03, 0x13, 0x83, or
0x93
0x04
0x05
2
INTTYPE = 00, base mode uses I C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
2
I2CMETHOD = 0, I C packets include register address
DISFPLL = 1, filter PLL disabled
CMLLVL = 11, 400mV CML signal level
PREEMP = 0000, preemphasis disabled
0x70
0x06
0x07
0x40
0x22
RESERVED = 01000000
RESERVED = 00100010
RESERVED = 0000
LFNEG = 10, no faults detected
LFPOS = 10, no faults detected
0x0A
(read only)
0x08
SETINT = 0, interrupt output set to low
RESERVED = 0001111
0x0D
0x1E
0x1F
0x0F
0x01
(read only)
ID = 00000001, device ID is 0x01
0x0X
(read only)
RESERVED = 0000
REVISION = XXXX, revision number
Table 2. MAX9260 Power-Up Default Register Map (see Table 19)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
SERID =1000000, serializer device identifier is 1000 000
RESERVED = 0
0x00
0x01
0x80
0x90
DESID =1001000, deserializer device identifier is 1001 000
RESERVED = 0
SS = 00 (SSEN = low), SS = 01 (SSEN = high), spread-spectrum settings depend
on SSEN pin state at power-up
RESERVED = 0
AUDIOEN = 1, I S channel enabled
0x02
0x1F or 0x5F
2
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
______________________________________________________________________________________ 25
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 2. MAX9260 Power-Up Default Register Map (see Table 19) (continued)
REGISTER
ADDRESS
(hex)
POWER-UP DEFAULT
(hex)
POWER-UP DEFAULT SETTINGS
(MSB FIRST)
AUTOFM = 00, calibrate spread-modulation rate only once after locking
RESERVED = 0
SDIV = 00000, autocalibrate sawtooth divider
0x03
0x04
0x00
LOCKED = 0, LOCK output = low (read only)
OUTENB = 0 (ENABLE = low), OUTENB = 1 (ENABLE = high), OUTENB default
depends on ENABLE pin state at power-up
PRBSEN = 0, PRBS test disabled
0x03, 0x13, 0x83, or
0x93
SLEEP = 0 or 1, SLEEP setting default depends on CDS and MS pin state at pow-
er-up (see the Link Startup Procedure section)
2
INTTYPE = 00, base mode uses I C
REVCCEN = 1, reverse control channel active (sending)
FWDCCEN = 1, forward control channel active (receiving)
RESERVED = 0
HPFTUNE = 01, 3.75MHz equalizer highpass cutoff frequency
PDHF = 0, high-frequency boosting disabled
EQTUNE = 1000 (EQS = high, 10.7dB), EQTUNE = 1001 (EQS = low, 5.2dB),
EQTUNE default setting depends on EQS pin state at power-up
0x05
0x06
0x28 or 0x29
DISSTAG = 0, staggered outputs enabled
AUTORST = 0, error registers/output auto reset disabled
DISINT = 0, INT transmission enabled
INT = 0, INT output = low (read only)
0x0F
GPIO1OUT = 1, GPIO1 output set to high
GPIO1 = 1, GPIO1 input = high (read only)
GPIO0OUT = 1, GPIO0 output set to high
GPIO0 = 1, GPIO0 input = high (read only)
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x54
0x30
0xC8
0x12
0x20
0x00
RESERVED = 01010100
RESERVED = 00110000
RESERVED = 11001000
RESERVED = 00010010
RESERVED = 00100000
ERRTHR = 00000000, error threshold set to zero for decoding errors
0x00
(read only)
0x0D
0x0E
0x12
0x1E
0x1F
DECERR = 00000000, zero decoding errors detected
PRBSERR = 00000000, zero PRBS errors detected
0x00
(read only)
MCLKSRC = 0, MCLK is derived from PCLKOUT (see Table 5)
MCLKDIV = 0000000, MCLK output is disabled
0x00
0x02
(read only)
ID = 00000010, device ID is 0x02
0x0X
(read only)
RESERVED = 0000
REVISION = XXXX
26 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
nal through the serial link. The MAX9260 deserializer
recovers the embedded serial clock and then samples,
decodes, and descrambles the data onto the paral-
lel output bus. Figures 22 and 23 show the serial-data
packet format prior to scrambling and 8B/10B coding.
For the 24-bit or 32-bit mode, the first 21 or 29 serial
bits come from DIN[20:0] or DIN[28:0], respectively.
The audio channel bit (ACB) contains an encoded audio
Parallel Inputs and Outputs
The parallel bus uses two selectable bus widths, 24
bits and 32 bits. BWS selects the bus width according
to Table 3. In 24-bit mode, DIN21–DIN28 are not used
and are internally pulled down. For both modes, SD,
2
SCK, and WS pins are dedicated for I S audio data. The
assignments of the first 21 or 29 signals are interchange-
able and appear in the same order at both sides of the
serial link. In image-sensing applications, disabling the
2
signal derived from the three I S inputs (SD, SCK, and
2
WS). The forward control channel (FCC) bit carries the
forward control data. The last bit (PCB) is the parity bit of
the previous 23 or 31 bits.
I S audio channel (through the MAX9259 and MAX9260
internal registers) allows the MAX9259 to serialize three
10-bit camera data streams through DIN[0:28] plus SD
inputs. The parallel bus accepts data clock rates from
8.33MHz to 104MHz for the 24-bit mode and 6.25MHz to
78MHz for the 32-bit mode.
Reverse Control Channel
The MAX9259/MAX9260 use the reverse control channel
2
to send I C/UART and interrupt signals in the opposite
direction of the video stream from the deserializer to
the serializer. The reverse control channel and forward
video data coexist on the same twisted pair forming a
bidirectional link. The reverse control channel operates
independently from the forward control channel. The
reverse control channel is available 500Fs after power-
up. The MAX9259 temporarily disables the reverse con-
trol channel for 350Fs after starting/stopping the forward
serial link.
Serial Link Signaling and Data Format
The MAX9259 high-speed data serial output uses
CML signaling with programmable preemphasis and
AC-coupling. The MAX9260 high-speed receiver uses
AC-coupling and programmable channel equalization.
Together, the GMSL operates at up to 3.125Gbps over
STP cable lengths up to 15m.
The MAX9259 serializer scrambles and encodes the
parallel input bits, and sends the 8B/10B coded sig-
Table 3. Bus-Width Selection Using BWS
BWS INPUT STATE
BUS WIDTH
PARALLEL BUS SIGNALS USED
DIN[0:20]/DOUT[0:20], WS, SCK, SD
DIN[0:28]/DOUT[0:28], WS, SCK, SD
Low
24
32
High
24 BITS
32 BITS
DIN0 DIN1
DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB
DIN0 DIN1
DIN17 DIN18 DIN19 DIN20 ACB FCC PCB
HSYNC,
VSYNC,
DE
ADDITIONAL
VIDEO
DATA/
CONTROL
BITS
24-BIT
RGB DATA
AUDIO
CHANNEL
BIT
18-BIT
RGB
DATA
HSYNC,
AUDIO
VSYNC,
CHANNEL BIT
DE
FORWARD
FORWARD
CONTROL-
CHANNEL BIT
CONTROL-
CHANNEL
BIT
PACKET
PARITY
CHECK BIT
PACKET
PARITY
CHECK BIT
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE
INTERCHANGEABLE ACCORDINGLY ON BOTH SIDES OF THE LINK.
Figure 22. 24-Bit Mode Serial Link Data Format
Figure 23. 32-Bit Mode Serial Link Data Format
______________________________________________________________________________________ 27
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 4. Maximum Audio Sampling Rates for Various PCLK_ Frequencies
PCLK_ FREQUENCY
(DRS = LOW)
(MHz)
PCLK_ FREQUENCY
(DRS = HIGH)
(MHz)
WORD LENGTH
(Bits)
12.5
> 192
> 192
185.5
174.6
152.2
123.7
15
16.6
> 20
6.25
> 192
> 192
185.5
174.6
152.2
123.7
7.5
8.33
> 10
8
> 192
> 192
> 192
> 192
182.7
148.4
> 192
> 192
> 192
> 192
> 192
164.3
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
> 192
182.7
148.4
> 192
> 192
> 192
> 192
> 192
164.3
> 192
> 192
> 192
> 192
> 192
> 192
16
18
20
24
32
Parallel Data-Rate Selection
Additional MCLK Output
for Audio Applications
Some audio DACs such as the MAX9850 do not require
a synchronous main clock (MCLK), while other DACs
require MCLK to be a specific multiple of WS. If an audio
DAC chip needs the MCLK to be a multiple of WS, syn-
The MAX9259/MAX9260 use the DRS inputs to set the
parallel data rate. Set DRS high to use a low-speed par-
allel data rate in the range of 6.25MHz to 12.5MHz (32-bit
mode) or 8.33MHz to 16.66MHz (24-bit mode). Set DRS
low for normal operation with parallel data rates higher
than 12.5MHz (32-bit mode) or 16.66MHz (24-bit mode).
2
chronize the I S audio data with PCLK_ of the GMSL,
which is typical for most applications. Select the PCLK_
to be the multiple of WS, or use a clock synthesis chip,
such as the MAX9491, to regenerate the required MCLK
from PCLK_ or SCK.
Audio Channel
2
The I S audio channel supports audio sampling rates
from 8kHz to 192kHz and audio word lengths from 4 bits
to 32 bits. The audio bit clock (SCK) does not need to be
synchronized with PCLKIN. The MAX9259 automatically
encodes audio data into a single bit stream synchronous
with PCLKIN. The MAX9260 decodes the audio stream
and stores audio words in a FIFO. Audio rate detection
uses an internal oscillator to continuously determine the
For audio applications that cannot directly use the
PCLKOUT output, the MAX9260 provides a divided
MCLK output on DOUT28 at the expense of one less
parallel line in 32-bit mode (24-bit mode is not affected).
By default, DOUT28 operates as a parallel data output
and MCLK is turned off. Set MCLKDIV (MAX9260 regis-
ter 0x12, D[6:0]) to a non-zero value to enable the MCLK
output. Set MCLKDIV to 0x00 to disable MCLK and set
DOUT28 as a parallel data output.
2
audio data rate and output the audio in I S format. The
audio channel is enabled by default. When the audio
channel is disabled, the SD pins on both sides are
treated as a regular parallel data pin.
The output MCLK frequency is:
PCLK_ frequencies can limit the maximum supported
audio sampling rate. Table 4 lists the maximum audio
sampling rate for various PCLK_ frequencies. Spread-
f
SRC
f
=
MCLK
MCLKDIV
2
spectrum settings do not affect the I S data rate or WS
clock frequency.
where f
is the MCLK source frequency (Table 5) and
SRC
MCLKDIV is the divider ratio from 1 to 127.
28 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 5. MAX9260 f
Settings
SRC
MCLKSRC SETTING
(REGISTER 0x12, D7)
MCLK SOURCE
FREQUENCY (f
DATA-RATE SETTING
BIT-WIDTH SETTING
)
SRC
24-bit mode
32-bit mode
24-bit mode
32-bit mode
3 x f
4 x f
6 x f
8 x f
PCLKOUT
High speed
Low speed
—
PCLKOUT
PCLKOUT
PCLKOUT
0
1
Internal oscillator
(120MHz typ)
—
2
2
Choose MCLKDIV values so that f
is not greater
MAX9259 or MAX9260 to I C. The converted I C bit rate
is the same as the original UART bit rate.
MCLK
than 60MHz. MCLK frequencies derived from PCLK_
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer (MAX9260). Enabling spread
spectrum in the serializer (MAX9259), however, intro-
duces spread spectrum into MCLK. Spread-spectrum
settings of either device do not affect MCLK frequencies
derived from the internal oscillator. The internal oscilla-
tor frequency ranges from 100MHz to 150MHz over all
process corners and operating conditions.
In bypass mode, the FC bypasses the MAX9259/
MAX9260 and communicates with the peripherals direct-
ly using its own defined UART protocol. The FC cannot
access the MAX9259/MAX9260’s registers in this mode.
Peripherals accessed through the forward control chan-
nel using the UART interface need to handle at least one
PCLK_ period of jitter due to the asynchronous sampling
of the UART signal by PCLK_.
Control-Channel and Register Programming
The FC uses the control link to send and receive control
data over the STP link simultaneously with the high-speed
data. Configuring the CDS pin allows the FC to control the
link from either the MAX9259 or the MAX9260 side to sup-
port video-display or image-sensing applications.
The MAX9259 embeds control signals going to the
MAX9260 in the high-speed forward link. Do not send
a low value longer than 100Fs in either base or bypass
mode. The MAX9260 uses a proprietary differential line
coding to send signals back towards the MAX9259. The
speed of the control link ranges from 100kbps to 1Mbps
in both directions. The MAX9259/MAX9260 automatically
detect the control-channel bit rate in base mode. Packet
bit rates can vary up to 3.5x from the previous bit rate
(see the Changing the Data Frequency section). Figure
24 shows the UART protocol for writing and reading in
base mode between the FC and the MAX9259/MAX9260.
The control link between the FC and the MAX9259 or
MAX9260 runs in base mode or bypass mode accord-
ing to the mode selection (MS) input of the device con-
nected to the FC. Base mode is a half-duplex control link
and the bypass mode is a full-duplex control link. In base
mode, the FC is the host and accesses the registers of
both the MAX9259 and MAX9260 from either side of the
link by using the GMSL UART protocol. The FC can also
program the peripherals on the remote side by sending
the UART packets to the MAX9259 or MAX9260, with
Figure 25 shows the UART data format. Even parity is
used. Figures 26 and 27 detail the formats of the SYNC
byte (0x79) and ACK byte (0xC3). The FC and the con-
nected slave chip generate the SYNC byte and ACK
byte, respectively. Certain events such as device wake-
up and interrupt generate signals on the control path and
should be ignored by the FC. All data written to the inter-
nal registers do not take affect until after the acknowl-
edge byte is sent. This allows the FC to verify that write
commands are processed without error, even if the result
of the write command directly affects the serial link. The
slave uses the SYNC byte to synchronize with the host
UART data rate automatically. If the INT or MS inputs of
the MAX9260 toggles while there is control-channel com-
munication, the control-channel communication can be
corrupted. In the event of a missed acknowledge, the FC
2
UART packets converted to I C by the device on the
remote side of the link (MAX9260 for LCD or MAX9259
for image-sensing applications). The FC communicates
with a UART peripheral in base mode (through INTTYPE
register settings) using the half-duplex default GMSL
UART protocol of the MAX9259 and MAX9260. The
device addresses of the MAX9259 and MAX9260 in the
base mode are programmable. The default values are
0x80 and 0x90, respectively.
2
In base mode, when the peripheral interface uses I C
(default), the MAX9259/MAX9260 only convert packets
that have device addresses different from those of the
______________________________________________________________________________________ 29
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FRMAT
SYNC
DEV ADDR + R/W
REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 24. UART Protocol for Base Mode
1 UART FRAME
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
Figure 25. UART Data Format for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
PARITY STOP
START
1
PARITY STOP
Figure 26. SYNC Byte (0x79)
Figure 27. ACK Byte (0xC3)
should assume there was an error in the packet when the
slave device receives it, or that an error occurred during
the response from the slave device. In base mode, the
FC must keep the UART Tx/Rx lines high for 16 bit times
before starting to send a new packet.
Interfacing Command-Byte-Only
2
I C Devices
2
The MAX9259/MAX9260 UART-to-I C conversion inter-
faces with devices that do not require register address-
es, such as the MAX7324 GPIO expander. Change the
2
communication method of the I C master using the
As shown in Figure 28, the remote-side device converts
the packets going to or coming from the peripherals from
I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-
only mode, while I2CMETHOD = 0 sets normal mode
where the first byte in the data stream is the register
2
the UART format to the I C format and vice versa. The
remote device removes the byte number count and adds
2
address. In this mode, the I C master ignores the reg-
2
or receives the ACK between the data bytes of I C. The
ister address byte and directly reads/writes the subse-
quent data bytes (Figure 29).
2
I C’s data rate is the same as the UART data rate.
30 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
MAX9259/MAX9260
FC
11
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS
NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
MAX9259/MAX9260
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
MAX9259/MAX9260
FC
11
11
11
REGISTER ADDRESS
11
NUMBER OF BYTES
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
MAX9259/MAX9260
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
Figure 28. Format Conversion between UART and I C with Register Address (I2CMETHOD = 0)
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
MAX9259/MAX9260
11
11
11
11
11
DATA 0
11
DATA N
11
ACK FRAME
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS
NUMBER OF BYTES
MAX9259/MAX9260
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
FC
MAX9259/MAX9260
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS
NUMBER OF BYTES
ACK FRAME
MAX9259/MAX9260
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
: MASTER TO SLAVE
: SLAVE TO MASTER
S: START
P: STOP
A: ACKNOWLEDGE
2
Figure 29. Format Conversion between UART and I C in Command-Byte-Only Mode (I2CMETHOD = 1)
______________________________________________________________________________________ 31
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 6. MAX9259 CML Driver Strength (Default Level, CMLLVL = 11)
SINGLE-ENDED VOLTAGE SWING
PREEMPHASIS LEVEL
(dB)*
PREEMPHASIS SETTING
(0x05, D[3:0])
I
I
PRE
(mA)
CML
MAX
(mV)
MIN
(mV)
(mA)
-6.0
-4.1
-2.5
-1.2
0
0100
0011
0010
0001
0000
1000
1001
1010
1011
1100
1101
1110
1111
12
13
14
15
16
16
16
16
16
15
14
13
12
4
3
2
1
0
1
2
3
4
5
6
7
8
400
400
400
400
400
425
450
475
500
500
500
500
500
200
250
300
350
400
375
350
325
300
250
200
150
100
1.1
2.2
3.3
4.4
6.0
8.0
10.5
14.0
*Negative preemphasis levels denote deemphasis.
preemphasis levels are deemphasis levels in which the
preemphasized swing level is the same as normal swing,
but the no-transition data is deemphasized. Program the
preemphasis levels through register 0x05 D[3:0] of the
MAX9259. This preemphasis function compensates the
high-frequency loss of the cable and enables reliable
transmission over longer link distances. Additionally, a
lower power drive mode can be entered by program-
ming CMLLVL bits (0x05 D[5:4]) to reduce the driver
strength down to 75% (CMLLVL = 10), or 50% (CMLLVL
= 01) from 100% (CMLLVL = 11, default).
Interrupt Control
The INT of the MAX9259 is the interrupt output and the
INT of the MAX9260 is the interrupt input. The interrupt
output on the MAX9259 follows the transitions at the
interrupt input of the MAX9260. This interrupt function
supports remote-side functions such as touch-screen
peripherals, remote power-up, or remote monitoring.
Interrupts that occur during periods where the reverse
control channel is disabled, such as link startup/shut-
down, are automatically resent once the reverse control
channel becomes available again. Bit D4 of register
0x06 in the MAX9260 also stores the interrupt input state.
Writing to the SETINT register bit also sets the INT output
of the MAX9259. In addition, the FC sets the INT output
of the MAX9259 by writing to the SETINT register bit. In
normal operation, the state of the interrupt output chang-
es when the interrupt input on the MAX9260 toggles.
Line Equalizer
The MAX9260 includes an adjustable line equalizer to
further compensate cable attenuation at high frequen-
cies. The cable equalizer has 11 selectable levels of
compensation from 2.1dB to 13dB (Table 7). The EQS
input selects the default equalization level at power-up.
The state of EQS is latched upon power-up or when
resuming from power-down mode. To select other
equalization levels, set the corresponding register bits
in the MAX9260 (0x05 D[3:0]). Use equalization in the
MAX9260, together with preemphasis in the MAX9259 to
create the most reliable link for a given cable.
Preemphasis Driver
The serial line driver in the MAX9259 employs current-
mode logic (CML) signaling. The driver generates
an adjustable preemphasized waveform according to
the cable length and characteristics. There are 13
preemphasis settings, as shown in Table 6. Negative
32 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Spread Spectrum
To reduce the EMI generated by the transitions on the
serial link and parallel outputs, both the MAX9259 and
MAX9260 support spread spectrum. Turning on spread
spectrum on the MAX9260 spreads the parallel video
outputs. Turning on spread spectrum on the MAX9259
spreads the serial link, along with the MAX9260 parallel
outputs. Do not enable spread spectrum for both the
MAX9259 and MAX9260. The six selectable spread-
spectrum rates at the MAX9259 serial output are Q0.5%,
Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 8). Some
spread-spectrum rates can only be used at lower PCLK_
frequencies (Table 9). There is no PCLK_ frequency limit
for the 0.5% spread rate. The two selectable spread-
spectrum rates at the MAX9260 parallel outputs are Q2%
and Q4% (Table 10).
Table 7. MAX9260 Cable Equalizer Boost
Levels
BOOST SETTING
TYPICAL BOOST GAIN (dB)
(0x05 D[3:0])
0000
0001
0010
0011
2.1
2.8
3.4
4.2
5.2
0100
Power-up default
(EQS = high)
0101
0110
0111
1000
6.2
7
8.2
9.4
Set the MAX9259 SSEN input high to select 0.5% spread
at power-up and SSEN input low to select no spread at
power-up. Set the MAX9260 SSEN input high to select
2% spread at power-up and SSEN input low to select no
spread at power-up. The state of SSEN is latched upon
power-up or when resuming from power-down mode.
Whenever the MAX9259 spread spectrum is turned on
10.7
1001
Power-up default
(EQS = low)
1010
1011
11.7
13
Table 8. MAX9259 Serial Output Spread
SS
SPREAD (%)
000
001
010
011
100
101
110
111
No spread spectrum. Power-up default when SSEN = low.
Q0.5% spread spectrum. Power-up default when SSEN = high.
Q1.5% spread spectrum
Q2% spread spectrum
No spread spectrum
Q1% spread spectrum
Q3% spread spectrum
Q4% spread spectrum
Table 9. MAX9259 Spread-Spectrum Rate Limitations
24-BIT MODE PCLKIN
FREQUENCY
(MHz)
32-BIT MODE PCLKIN
FREQUENCY
(MHz)
SERIAL LINK BIT RATE
(Mbps)
AVAILABLE SPREAD RATES
< 33.3
33.3 to < 66.7
66.7+
< 25
20 to < 50
50+
< 1000
1000 to < 2000
2000+
All rates available
1.5%, 1.0%, 0.5%
0.5%
______________________________________________________________________________________ 33
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 10. MAX9260 Parallel Output Spread
SS
00
01
10
11
SPREAD (%)
No spread spectrum. Power-up default when SSEN = low.
Q2% spread spectrum. Power-up default when SSEN = high.
No spread spectrum
Q4% spread spectrum
Table 11. MAX9259 Modulation Coefficients and Maximum SDIV Settings
SPREAD-SPECTRUM
SETTING (%)
MODULATION
COEFFICIENT (decimal)
SDIV UPPER LIMIT (deci-
mal)
BIT-WIDTH MODE
1
0.5
3
104
104
152
152
204
204
80
40
63
27
54
15
30
52
63
37
63
21
42
32-Bit
1.5
4
2
1
0.5
3
80
112
112
152
152
24-Bit
1.5
4
2
Table 12. MAX9260 Modulation Coefficients and Maximum SDIV Settings
MODULATION COEFFICIENT (deci-
SPREAD-SPECTRUM SETTING (%)
SDIV UPPER LIMIT (decimal)
mal)
208
208
4
2
15
30
or off, the serial link automatically restarts and remains
unavailable while the MAX9260 relocks to the serial data.
Manual Programming of the Spread-
Spectrum Divider
The modulation rates for the MAX9259 or the MAX9260
relate to the PCLK_ frequency as follows:
Turning on spread spectrum on either the MAX9259 or
MAX9260 side does not affect the audio data stream.
Changes in the MAX9259 spread settings only affect
MCLK output if it is derived from PCLK_ (MCLKSRC = 0).
f
PCLK_
f
= 1+ DRS
(
)
M
MOD× SDIV
where:
= Modulation frequency
Both devices include a sawtooth divider to control the
spread-modulation rate. Autodetection or manual pro-
gramming of the PCLK_ operation range guarantees a
spread-spectrum modulation frequency within 20kHz to
40kHz. Additionally, manual configuration of the saw-
tooth divider (SDIV, 0x03 D[5:0]) allows the user to set a
specific modulation frequency for a specific PCLK_ rate.
Always keep the modulation frequency between 20kHz
to 40kHz to ensure proper operation.
f
M
DRS = DRS pin input value (0 or 1)
= Parallel clock frequency (12.5MHz to 104MHz)
f
PCLK_
MOD = Modulation coefficient given in Table 11 for the
MAX9259 and Table 12 for the MAX9260
SDIV = 6-bit (MAX9259) or 5-bit (MAX9260) SDIV setting,
manually programmed by the FC
34 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
To program the SDIV setting, first look up the modulation
coefficient according to the part number and desired
bit-width and spread-spectrum settings. Solve the above
equation for SDIV using the desired parallel clock and
modulation frequencies. If the calculated SDIV value is
larger than the maximum allowed SDIV value in Tables
11 or 12, set SDIV to the maximum value.
Video-Display Applications
For the video-display application, with a remote display
unit, connect the FC to the serializer (MAX9259) and set
CDS = low for both the MAX9259 and MAX9260. Table
13 summarizes the four startup cases based on the set-
tings of AUTOS and MS.
Case 1: Autostart Mode
After power-up or when PWDN transitions from low
to high for both the serializer and deserializer, the
serial link establishes if a stable PCLK_ is present. The
MAX9259 locks to PCLK_ and sends the serial data to
the MAX9260. The MAX9260 then detects activity on the
serial link and locks to the input serial data.
Sleep Mode
The serializer/deserializer include a low-power sleep
mode to reduce power consumption on the device not
attached to the FC (MAX9260 in LCD applications and
MAX9259 in camera applications). Set the correspond-
ing remote IC’s SLEEP bit to 1 to initiate sleep mode. The
MAX9259 sleeps immediately after setting its SLEEP =
1. The MAX9260 sleeps after serial link inactivity or 8ms
(whichever arrives first) after setting its SLEEP = 1. See
the Link Startup Procedure section for details on waking
up the device for different FC and starting conditions.
Case 2: Standby Start Mode
After power-up, or when PWDN transitions from low
to high for both the serializer and deserializer, the
MAX9260 starts up in sleep mode, and the MAX9259
stays in standby mode (does not send serial data). Use
the FC and program the MAX9259 to set SEREN = 1 to
establish a video link or CLINKEN = 1 to establish the
configuration link. After locking to a stable PCLK_ (for
SEREN = 1) or the internal oscillator (for CLINKEN = 1),
the MAX9259 sends a wake-up signal to the deserial-
izer. The MAX9260 exits sleep mode after locking to the
serial data and sets SLEEP = 0. If after 8ms the deserial-
izer does not lock to the input serial data, the MAX9260
goes back to sleep, and the internal sleep bit remains
uncleared (SLEEP = 1).
The FC side device cannot enter into sleep mode, and its
SLEEP bit remains at 0. Use the PWDN input pin to bring
the FC side device into a low-power state.
Configuration Link Mode
The MAX9259/MAX9260 include a low-speed configura-
tion link to allow control-data connection between the two
devices in the absence of a valid parallel clock input. In
either display or camera applications, the configuration
link can be used to program equalizer/preemphasis
or other registers before establishing the video link.
An internal oscillator provides PCLK_ for establishing
the serial configuration link between the MAX9259 and
MAX9260. The parallel output clock and data lines are
disabled in the MAX9260. The LOCK output remains
low even after a successful configuration link lock. Set
CLINKEN = 1 on the MAX9259 to turn on the configura-
tion link. The configuration link remains active as long as
the video link has not been enabled. The video link over-
rides the configuration link and attempts to lock when
SEREN = 1.
Case 3: Remote Side Autostart Mode
After power-up, or when PWDN transitions from low to
high, the remote device (MAX9260) starts up and tries
to lock to an incoming serial signal with sufficient power.
The host side (MAX9259) is in standby mode and does
not try to establish a link. Use the FC and program the
MAX9259 to set SEREN = 1 (and apply a stable PCLK_)
to establish a video link, or CLINKEN = 1 to establish the
configuration link. In this case, the MAX9260 ignores the
short wake-up signal sent from the MAX9259.
Case 4: Remote Side in Sleep Mode
After power-up or when PWDN transitions from low to
high, the remote device (MAX9260) starts up in sleep
mode. The high-speed link establishes automatically
after MAX9259 powers up with a stable PCLK_ and
sends a wake-up signal to the MAX9260. Use this mode
in applications where the MAX9260 powers up before
the MAX9259.
Link Startup Procedure
Table 13 lists four startup cases for video-display
applications. Table 14 lists two startup cases for image-
sensing applications. In either display or image-sensing
applications, the control link is always available after
the high-speed data link or the configuration link is
established and the MAX9259/MAX9260 registers or the
peripherals are ready for programming.
______________________________________________________________________________________ 35
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 13. Startup Selection for Video-Display Applications (CDS = Low)
MAX9259
POWER-UP STATE
MS
(MAX9260)
MAX9260
POWER-UP STATE
AUTOS
(MAX9259)
CASE
LINK STARTUP MODE
Normal
(SLEEP = 0)
Both devices power up with
serial link active (autostart)
1
Low
Serialization enabled
Low
Serial link is disabled and
the MAX9260 powers up in
sleep mode. Set SEREN = 1 or
CLINKEN = 1 in the MAX9259
to start the serial link and wake
up the MAX9260.
Serialization dis-
abled
Sleep mode
(SLEEP = 1)
2
High
High
Both devices power up in nor-
mal mode with the serial link
is disabled. Set SEREN = 1 or
CLINKEN = 1 in the MAX9259
to start the serial link.
Serialization dis-
abled
Normal
(SLEEP = 0)
3
4
High
Low
Low
MAX9260 starts in sleep mode.
Link autostarts upon MAX9259
power-up. Use this case when
the MAX9260 powers up before
the MAX9259.
Sleep mode
(SLEEP = 1)
Serialization enabled
High
SEREN BIT
POWER-UP VALUE
AUTOS PIN
SETTING
LOW
HIGH
CLINKEN = 0 OR
SEREN = 1
1
0
CLINKEN = 0 OR
SEREN = 1
CONFIG LINK
CONFIG LINK
PWDN = HIGH,
POWER-ON
UNLOCKED
OPERATING
POWER-DOWN
OR POWER-OFF
POWER-ON
IDLE
CONFIG
LINK STARTING
PROGRAM
REGISTERS
AUTOS = LOW
CLINKEN = 1
CONFIG LINK
LOCKED
SEREN = 0,
NO PCLKIN
PWDN = LOW OR
POWER-OFF
SEREN = 1,
PCLKIN RUNNING
PWDN = HIGH
POWER-ON,
AUTOS = LOW
SEREN = 0, OR
NO PCLKIN
PRBSEN = 0
PRBSEN = 1
VIDEO LINK
LOCKED
VIDEO
LINK LOCKING
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
VIDEO LINK
UNLOCKED
Figure 30. MAX9259 State Diagram, CDS = Low (LCD Application)
36 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
CONFIG LINK
UNLOCKED
MS PIN
SLEEP BIT
CONFIG LINK
OPERATING
SETTING POWER-UP VALUE
WAKE-UP
SIGNAL
SIGNAL
DETECTED
POWER-ON
IDLE
SERIAL PORT
LOCKING
SLEEP
LOW
HIGH
0
1
PROGRAM
REGISTERS
CONFIG LINK
LOCKED
0
SLEEP
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
PWDN = HIGH,
POWER-ON
FC SETS SLEEP = 1
INT CHANGES FROM
LOW TO HIGH OR
PRBSEN = 0
PRBSEN = 1
SEND INT TO
POWER-DOWN
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
HIGH TO LOW
PWDN = LOW OR
POWER-OFF
ALL STATES
OR
POWER-OFF
MAX9259
0
SLEEP
Figure 31. MAX9260 State Diagram, CDS = Low (LCD Application)
Case 2: Sleep Mode
Image-Sensing Applications
For image-sensing applications, with remote camera
unit(s), connect the FC to the deserializer (MAX9260)
and set CDS = high for both the MAX9259 and MAX9260.
The MAX9260 powers up normally (SLEEP = 0) and con-
tinuously tries to lock to a valid serial input. Table 14
summarizes the two startup cases, based on the state of
the MAX9259 AUTOS pin.
After power-up, or when PWDN transitions from low to
high, the MAX9259 starts up in sleep mode. To wake up
the MAX9259, use the FC to send a regular UART frame
containing at least three rising edges (e.g., 0x66), at a
bit rate no greater than 1Mbps. The low-power wake-up
receiver of the MAX9259 detects the wake-up frame over
the reverse control channel and powers up. Reset the
sleep bit (SLEEP = 0) of the MAX9259 using a regular
control-channel write packet to power up the device fully.
Send the sleep bit write packet at least 500Fs after the
wake-up frame. The MAX9259 goes back to sleep mode
if its sleep bit is not cleared within 8ms (typ) after detect-
ing a wake-up frame.
Case 1: Autostart Mode
After power-up, or when PWDN transitions from low to
high, the MAX9259 locks to a stable PCLKIN and sends
the high-speed data to the MAX9260. The MAX9260
locks to the serial data and outputs the parallel video
data and PCLKOUT.
Table 14. Startup Selection for Image-Sensing Applications (CDS = High)
MAX9259 POWER-UP
STATE
MAX9260 POWER-UP
STATE
AUTOS
(MAX9259)
CASE
LINK STARTUP MODE
Normal
(SLEEP = 0)
1
Low
Serialization enabled
Autostart
MAX9259 is in sleep mode. Wake
up the MAX9259 through the control
channel (FC attached to MAX9260).
Sleep mode
(SLEEP = 1)
Normal
(SLEEP = 0)
2
High
______________________________________________________________________________________ 37
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
POWER-UP VALUE
AUTOS PIN
SETTING
SEREN
SLEEP
CLINKEN = 0 OR
SEREN = 1
LOW
HIGH
1
0
0
1
CLINKEN = 0 OR
SEREN = 1
SLEEP = 1
FOR > 8ms
CONFIG LINK
UNLOCKED
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
SLEEP = 0,
SEREN = 0
POWER-ON
IDLE
CONFIG
LINK STARTED
SLEEP
WAKE-UP
CLINKEN = 1
CONFIG LINK
LOCKED
REVERSE LINK
WAKE-UP SIGNAL
SEREN = 1,
PCLKIN RUNNING
PWDN = HIGH,
POWER-ON,
AUTOS = HIGH
SEREN = 0 OR
NO PCLKIN
SLEEP = 0,
SLEEP = 1
SLEEP = 1
SEREN = 0 OR
NO PCLKIN
PWDN = HIGH,
POWER-ON
PRBSEN = 0
PRBSEN = 1
POWER-DOWN
OR
POWER-OFF
VIDEO LINK
LOCKED
PWDN = LOW OR
POWER-OFF
VIDEO
LINK LOCKING
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
ALL STATES
AUTOS = LOW
VIDEO LINK
UNLOCKED
Figure 32. MAX9259 State Diagram, CDS = High (Camera Application)
CONFIG LINK
UNLOCKED
CONFIG
LINK OPERATING
POWER-ON
IDLE
(REVERSE
CHANNEL
ACTIVE)
SIGNAL
DETECTED
SERIAL PORT
LOCKING
PROGRAM
REGISTERS
CONFIG LINK
LOCKED
NO SIGNAL
DETECTED
PWDN = HIGH,
POWER ON
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
POWER-DOWN
OR
POWER-OFF
PRBSEN = 0
PRBSEN = 1
PWDN = LOW OR
POWER-OFF
ALL STATES
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
Figure 33. MAX9260 State Diagram, CDS = High (Camera Application)
38 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
MAX9260 are set to low, and for the later case, the
CDS pins are set to high. However, if the CDS pin of the
Applications Information
MAX9260 Error Checking
The MAX9260 checks the serial link for errors and stores
the number of detected decoding errors in the 8-bit
register (DECERR, 0x0D). If a large number of decoding
errors are detected within a short duration, the deserial-
izer loses lock and stops the error counter. The deserial-
izer then attempts to relock to the serial data. DECERR
resets upon successful video link lock, successful
readout of DECERR (through UART), or whenever auto-
error reset is enabled. The MAX9260 does not check
for decoding errors during the internal PRBS test and
DECERR is reset to 0x00.
MAX9259 is low and the CDS pin of the MAX9260 is high,
then the MAX9259/MAX9260 can both connect to FCs
simultaneously. In such a case, the FCs on either side
can communicate with the MAX9259/MAX9260 UART
protocol.
Contentions of the control link may happen if the FCs
on both sides are using the link at the same time. The
MAX9259/MAX9260 do not provide the solution for
contention avoidance. The serializer/deserealizer do not
send an acknowledge frame when communication fails
due to contention. Users can always implement a higher-
layer protocol to avoid the contention. In addition, if UART
communication across the serial link is not required, the
FCs can disable the forward and reverse control channel
through the FWDCCEN and REVCCEN bits (0x04 D[1:0])
in the MAX9259/MAX9260. UART communication across
the serial link is stopped and contention between FCs no
longer occurs. During the dual FC operation, if one of the
CDS pins on either side changes state, the link resumes
the corresponding state described in the Link Startup
Procedure section.
ERR Output
The MAX9260 has an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceed the error threshold (ERRTHR, 0x0C) dur-
ing normal operation, or when at least one PRBS error is
detected during PRBS test. ERR reasserts high when-
ever DECERR (0x0D) resets, due to DECERR readout,
video link lock, or autoerror reset.
Autoerror Reset
The default method to reset errors is to read the respec-
tive error registers in the MAX9260 (0x0D, 0x0E). Auto-
error reset clears the decoding-error counter (DECERR)
and the ERR output ~1Fs after ERR goes low. Autoerror
reset is disabled on power-up. Enable autoerror reset
through AUTORST (0x06 D6). Autoerror reset does not
run when the device is in PRBS test mode.
As an example of dual FC use in an image-sensing link,
the MAX9259 may be in sleep mode and waiting to be
waked up by the MAX9260. After wake-up, the serializer-
side FC sets the MAX9259 CDS pin low and assumes
master control of the MAX9259 registers.
Jitter-Filtering PLL
In some applications, the parallel bus input clock to the
MAX9259 (PCLKIN) includes noise, which reduces link
reliability. The MAX9259 has a narrow-band jitter-filtering
PLL to attenuate frequency components outside the
PLL’s bandwidth (< 100kHz typ). Enable the jitter-filtering
PLL by setting DISFPLL = 0 (0x05 D6).
Self PRBS Test
The MAX9259/MAX9260 link includes a PRBS pat-
tern generator and bit-error verification function. Set
PRBSEN = 1 (0x04 D5) first in the MAX9259 and then
the MAX9260 to start the PRBS test. Set PRBSEN = 0
(0x04 D5) first in the MAX9260 and then the MAX9259
to exit the PRBS self test. The MAX9260 uses an 8-bit
register (0x0E) to count the number of detected errors.
The control link also controls the start and stop of the
error counting. During PRBS mode, the device does not
count decoding errors and the ERR output reflects PRBS
errors only. Autoerror reset does not run when the device
is in PRBS mode.
Changing the Data Frequency
Both the video data rate (f
) and the control data
PCLK_
rate (f
) can be changed on-the-fly to support
UART
applications with multiple clock speeds. Slow speed/
performance modes allow significant power savings
when a system’s full capabilities are not required. Enable
the MAX9259/MAX9260 link after PCLK_ stabilizes.
Stop PCLKIN for 5µs and restart the serial link or toggle
SEREN after each change in the parallel clock frequency
to recalibrate any automatic settings if a clean frequency
change cannot be guaranteed. The reverse control
channel remains unavailable for 350Fs after serial link
Microcontrollers on Both Sides
of the GMSL Link (Dual µC Control)
Usually the FC is either on the serializer (MAX9259)
side for video-display applications, or on the deserial-
izer (MAX9260) side for image-sensing applications. For
the former case, both the CDS pins of the MAX9259/
start or stop. Limit on-the-fly changes in f
to fac-
UART
tors of less than 3.5 at a time to ensure that the device
______________________________________________________________________________________ 39
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps and then at 100kbps to have
reduction ratios of 3 and 3.333, respectively.
Staggered Parallel Data Outputs
The MAX9260 staggers the parallel data outputs to
reduce EMI and noise. Staggering outputs also reduce
the power-supply transient requirements. By default,
the deserializer staggers outputs according to Table
16. Disable output staggering through the DISSTAG bit
(0x06 D7)
LOCK Output Loopback
Connect the LOCK output to the INT input of the
MAX9260 to loopback LOCK to the MAX9259. The
interrupt output on the MAX9259 follows the transitions
at the LOCK output of the MAX9260. Reverse-channel
communication does not require an active forward link
to operate and accurately tracks the LOCK status of the
video link. LOCK asserts for video link only and not for
the configuration link.
2
Choosing I C/UART Pullup Resistors
2
Both I C/UART open-drain lines require pullup resistors
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise must
be made in choosing pullup resistor values. Every device
connected to the bus introduces some capacitance even
2
when the device is not in operation. I C specifies 300ns
MAX9260 GPIOs
The MAX9260 has two open-drain GPIOs available.
GPIO1OUT and GPIO0OUT (0x06 D3, D1) set the output
state of the GPIOs. The GPIO input buffers are always
enabled. The input states are stored in GPIO1 and
GPIO0 (0x06 D2, D0). Set GPIO1OUT/GPIO0OUT to 1
when using GPIO1/GPIO0 as an input.
rise times to go from low to high (30% to 70%) for fast
mode, which is defined for data rates up to 400kbps (see
2
the I C specifications in the Electrical Characteristics
table for details). To meet the fast-mode rise-time
requirement, choose the pullup resistors so that rise time
t
= 0.85 x R
x C
< 300ns. The waveforms
R
PULLUP
BUS
are not recognized if the transition time becomes too
Line-Fault Detection
The line-fault detector in the MAX9259 monitors for line
failures such as short to ground, short to power supply,
and open link for system fault diagnosis. Figure 3 shows
the required external resistor connections. LFLT = low
when a line fault is detected and LFLT = high when the
line returns to normal. The line-fault type is stored in
0x08 D[3:0] of the MAX9259. The fault-detector thresh-
old voltages are referenced to the MAX9259 ground.
Additional passive components set the DC level of the
cable (Figure 3). If the MAX9259 and MAX9260 grounds
are different, the link DC voltage during normal operation
can vary and cross one of the fault-detection thresholds.
For the fault-detection circuit, select the resistor’s power
rating to handle a short to the battery. Table 15 lists the
mapping for line-fault types.
Table 16. Staggered Output Delay
OUTPUT DELAY RELATIVE
TO DOUT0 (ns)
OUTPUT
DISSTAG = 0
DISSTAG = 1
DOUT0–DOUT5,
DOUT21, DOUT22
0
0.5
1
0
DOUT6–DOUT10,
DOUT23, DOUT24
0
0
DOUT11–DOUT15,
DOUT25, DOUT26
DOUT16–DOUT20,
DOUT27, DOUT28
1.5
0
0
PCLKOUT
0.75
Table 15. MAX9259 Line-Fault Mapping
REGISTER
ADDRESS
BITS
NAME
VALUE
LINE-FAULT TYPE
00
01
10
11
00
01
10
11
Negative cable wire shorted to battery
Negative cable wire shorted to ground
Normal operation
D[3:2]
LFNEG
Negative cable wire open
0x08
Positive cable wire shorted to battery
Positive cable wire shorted to ground
Normal operation
D[1:0]
LFPOS
Positive cable wire open
40 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
2
slow. The MAX9259/MAX9260 support I C/UART rates
up to 1Mbps.
MAX9260 derive power from an IOVDD of 1.7V to 3.6V.
The input levels or output levels scale with IOVDD.
Proper voltage-supply bypassing is essential for high-
frequency circuit stability.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to
the voltage rating of the capacitor. Four capacitors—two
at the serializer output and two at the deserializer input—
are needed for proper link operation and to provide
protection if either end of the cable is shorted to a high
voltage. AC-coupling blocks low-frequency ground shifts
and low-frequency common-mode noise.
Cables and Connectors
Interconnect for CML typically has a differential imped-
ance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Twisted-pair and shielded twisted-pair
cables offer superior signal quality compared to ribbon
cable and tend to generate less EMI due to magnetic-
field canceling effects. Balanced cables pick up noise
as common mode rejected by the CML receiver. Table
17 lists the suggested cables and connectors used in
the GMSL link.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start
from different voltage levels. Because the transition time
is finite, starting the signal transition from different volt-
age levels causes timing jitter. The time constant for an
AC-coupled link needs to be chosen to reduce droop
and jitter to an acceptable level. The RC network for an
AC-coupled link consists of the CML receiver termination
Board Layout
Separate the parallel signals and CML high-speed serial
signals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML, and digital
signals. Layout PCB traces close to each other and have
a 100I differential characteristic impedance. The trace
dimensions depend on the type of trace used (microstrip
or stripline). Note that two 50I PCB traces do not
have 100I differential impedance when brought close
together—the impedance goes down when the traces
are brought closer.
resistor (R ), the CML driver termination resistor (R ),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
TR
TD
(R + R ))/4. R and R are required to match the
TD
TR
TD
TR
transmission line impedance (usually 100I). This leaves
the capacitor selection to change the system time con-
stant. Use at least 0.2FF (100V) high-frequency surface-
mount ceramic capacitors to pass the lower speed
reverse-channel signal. Use capacitors with a case size
less than 3.2mm x 1.6mm to have lower parasitic effects
to the high-speed signal.
Route the PCB traces for a CML channel (there are two
conductors per CML channel) in parallel to maintain the
differential characteristic impedance. Avoid vias. If vias
must be used, use only one pair per CML channel and
place the via for each line at the same point along the
length of the PCB traces. This way, any reflections occur
at the same time. Do not make vias into test points for
Power-Supply Circuits and Bypassing
The MAX9259 uses an AVDD and DVDD of 1.7V to 1.9V.
The MAX9260 uses an AVDD and DVDD of 3.0V to 3.6V.
All single-ended inputs and outputs on the MAX9259/
Table 17. Suggested Connectors and Cables for GMSL
SUPPLIER
CONNECTOR
MX38-FF
CABLE
A-BW-Lxxxxx
F-2WME AWG28
Dacar 538
JAE Electronics, Inc.
Nissei Electric Co., Ltd.
GT11L-2S
Rosenberger Hochfrequenztechnik GmbH
D4S10A-40ML5-Z
______________________________________________________________________________________ 41
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
ATE. Keep PCB traces that make up a differential pair
R
D
equal in length to avoid skew within the differential pair.
1MI
1.5kI
ESD Protection
The MAX9259/MAX9260 ESD tolerance is rated for
Human Body Model, IEC 61000-4-2, and ISO 10605. The
ISO 10605 and IEC 61000-4-2 standards specify ESD
tolerance for electronic systems. Serial outputs on the
MAX9259 and serial inputs on the MAX9260 meet ISO
10605 ESD protection and IEC 61000-4-2 ESD protec-
tion. All other pins meet the Human Body Model ESD
tolerances. The Human Body Model discharge compo-
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
100pF
SOURCE
Figure 34. Human Body Model ESD Test Circuit
nents are C = 100pF and R = 1.5kI (Figure 34). The
S
D
IEC 61000-4-2 discharge components are C = 150pF
S
and R = 330I (Figure 35). The ISO 10605 discharge
D
R
D
components are C = 330pF and R = 2kI (Figure 36).
S
D
330I
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
150pF
SOURCE
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit
R
D
2kI
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
330pF
SOURCE
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
42 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 18. MAX9259 Register Table (see Table 1 for Default Value Details)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
D[7:1]
D0
SERID
—
XXXXXXX
Serializer device address
Reserved
1000000
0x00
0x01
0
XXXXXXX
0
0
1001000
0
D[7:1]
D0
DESID
—
Deserializer device address
Reserved
No spread spectrum. Power-up default
when SSEN = low.
000
001
Q0.5% spread spectrum. Power-up default
when SSEN = high.
010
011
100
101
110
111
0
Q1.5% spread spectrum
Q2% spread spectrum
No spread spectrum
Q1% spread spectrum
Q3% spread spectrum
Q4% spread spectrum
D[7:5]
SS
000, 001
0x02
2
Disable I S channel
D4
AUDIOEN
PRNG
1
2
1
Enable I S channel
00
12.5MHz to 25MHz pixel clock
25MHz to 50MHz pixel clock
01
D[3:2]
11
10
50MHz to 104MHz pixel clock
Automatically detect the pixel clock range
0.5 to 1Gbps serial-data rate
11
00
01
1 to 2Gbps serial-data rate
D[1:0]
D[7:6]
D[5:0]
SRNG
AUTOFM
SDIV
11
00
10
2 to 3.125Gbps serial-data rate
Automatically detect serial-data rate
11
Calibrate spread-modulation rate only once
after locking
00
01
10
Calibrate spread-modulation rate every 2ms
after locking
Calibrate spread-modulation rate every
16ms after locking
0x03
Calibrate spread-modulation rate every
256ms after locking
11
000000
Autocalibrate sawtooth divider
Manual SDIV setting (see the Manual
Programming of the Spread-Spectrum
Divider section)
000000
XXXXXX
______________________________________________________________________________________ 43
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Disable serial link. Power-up default when
AUTOS = high. Reverse-channel
communication remains unavailable for
350Fs after the MAX9259 starts/stops the
serial link.
0
D7
SEREN
0, 1
Enable serial link. Power-up default when
AUTOS = low. Reverse-channel
communication remains unavailable for
350Fs after the MAX9259 starts/stops the
serial link.
1
0
1
0
1
Disable configuration link
Enable configuration link
Disable PRBS test
D6
D5
CLINKEN
PRBSEN
0
0
Enable PRBS test
Normal mode. Default value depends on
CDS and AUTOS pin values at power-up.
0
1
0x04
D4
D[3:2]
D1
SLEEP
INTTYPE
REVCCEN
0, 1
00
1
Activate sleep mode. Default value depends
on CDS and AUTOS pin values at power-up.
2
00
01
Base mode uses I C peripheral interface
Base mode uses UART peripheral interface
Base mode peripheral interface disabled
10, 11
Disable reverse control channel from
deserializer (receiving)
0
1
0
1
Enable reverse control channel from
deserializer (receiving)
Disable forward control channel to
deserializer (sending)
D0
FWDCCEN
1
Enable forward control channel to
deserializer (sending)
44 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
I2CMETHOD
DISFPLL
VALUE
FUNCTION
2
0
1
I C conversion sends the register address
2
D7
0
1
Disable sending of I C register address
(command-byte-only mode)
0
1
Filter PLL active
D6
Filter PLL disabled
Do not use
00
01
200mV CML signal level
300mV CML signal level
400mV CML signal level
Preemphasis off
D[5:4]
CMLLVL
11
10
11
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
01000000
00100010
-1.2dB preemphasis
-2.5dB preemphasis
-4.1dB preemphasis
-6.0dB preemphasis
Do not use
0x05
Do not use
Do not use
D[3:0]
PREEMP
0000
1.1dB preemphasis
2.2dB preemphasis
3.3dB preemphasis
4.4dB preemphasis
6.0dB preemphasis
8.0dB preemphasis
10.5dB preemphasis
14.0dB preemphasis
Reserved
0x06
0x07
D[7:0]
D[7:0]
—
—
01000000
00100010
Reserved
0000
(read only)
D[7:4]
—
0000
Reserved
00
01
10
11
00
01
10
11
Negative cable wire shorted to battery
Negative cable wire shorted to ground
Normal operation
10
D[3:2]
LFNEG
(read only)
0x08
Negative cable wire open
Positive cable wire shorted to battery
Positive cable wire shorted to ground
Normal operation
10
D[1:0]
LFPOS
(read only)
Positive cable wire open
______________________________________________________________________________________ 45
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 18. MAX9259 Register Table (see Table 1 for Default Value Details) (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Set INT low when SETINT transitions from 1
to 0
0
1
D7
SETINT
0
Set INT high when SETINT transitions from
0 to 1
0x0D
0x1E
D[6:4]
D[3:0]
—
—
000
Reserved
Reserved
000
1111
1111
Device identifier
(MAX9259 = 0x01)
00000001
(read only)
D[7:0]
ID
00000001
0000
(read only)
D[7:4]
D[3:0]
—
0000
XXXX
Reserved
0x1F
REVISION
Device revision
(read only)
X = Don’t care.
Table 19. MAX9260 Register Table
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
D[7:1]
D0
SERID
—
XXXXXXX
Serializer device address
Reserved
1000000
0x00
0
XXXXXXX
0
0
1001000
0
D[7:1]
D0
DESID
—
Deserializer device address
Reserved
0x01
No spread spectrum. Power-up default
when SSEN = low.
00
01
Q2% spread spectrum. Power-up default
when SSEN = high.
D[7:6]
SS
00, 01
10
11
0
No spread spectrum
Q4% spread spectrum
Reserved
D5
D4
—
0
1
2
0
Disable I S channel
AUDIOEN
2
0x02
1
Enable I S channel
00
01
10
11
00
01
10
11
12.5MHz to 25MHz pixel clock
25MHz to 50MHz pixel clock
D[3:2]
D[1:0]
PRNG
SRNG
11
11
50MHz to 104MHz pixel clock
Automatically detect the pixel clock range
0.5 to 1Gbps serial-data rate
1 to 2Gbps serial-data rate
2 to 3.125Gbps serial-data rate
Automatically detect serial-data rate
46 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 19. MAX9260 Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Calibrate spread-modulation rate only once
after locking
00
Calibrate spread-modulation rate every 2ms
after locking
01
D[7:6]
AUTOFM
00
Calibrate spread-modulation rate every
16ms after locking
10
0x03
Calibrate spread-modulation rate every
256ms after locking
11
D5
—
0
Reserved
0
00000
Autocalibrate sawtooth divider
Manual SDIV setting (see the Manual
Programming of the Spread-Spectrum
Divider section)
D[4:0]
SDIV
00000
XXXXX
0
1
LOCK output is low
LOCK output is high
0
D7
D6
D5
D4
LOCKED
OUTENB
PRBSEN
SLEEP
(read only)
Enable outputs. A transition on ENABLE
changes the state of OUTENB.
0
1
0, 1
0
Disable outputs. A transition on ENABLE
changes the state of OUTENB.
0
1
Disable PRBS test
Enable PRBS test
Normal mode default value depends on
CDS and MS pin values at power-up)
0
1
0, 1
Activate sleep mode default value depends
on CDS and MS pin values at power-up)
0x04
2
00
01
Base mode uses I C peripheral interface
D[3:2]
D1
INTTYPE
Base mode uses UART peripheral interface
Base mode peripheral interface disabled
00
1
10, 11
Disable reverse control channel to serializer
(sending)
0
1
0
1
REVCCEN
Enable reverse control channel to serializer
(sending)
Disable forward control channel from
serializer (receiving)
D0
FWDCCEN
1
Enable forward control channel from
serializer (receiving)
______________________________________________________________________________________ 47
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 19. MAX9260 Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
2
0
1
I C conversion sends the register address
2
D7
I2CMETHOD
0
Disable sending of I C register address
(command-byte-only mode)
7.5MHz Equalizer highpass cutoff frequency
3.75MHz cutoff frequency
00
01
D[6:5]
D4
HPFTUNE
PDHF
01
0
10
2.5MHz cutoff frequency
11
1.87MHz cutoff frequency
0
High-frequency boosting enabled
High-frequency boosting disabled
2.1dB equalizer boost gain
2.8dB equalizer boost gain
3.4dB equalizer boost gain
4.2dB equalizer boost gain
1
0000
0001
0010
0011
0x05
5.2dB equalizer boost gain. Power-up
default when EQS = high.
0100
0101
0110
0111
1000
6.2dB equalizer boost gain
7dB equalizer boost gain
8.2dB equalizer boost gain
9.4dB equalizer boost gain
D[3:0]
EQTUNE
0100, 1001
10.7dB equalizer boost gain. Power-up
default when EQS = low.
1001
1010
1011
11XX
0
11.7dB equalizer boost gain
13dB equalizer boost gain
Do not use
Enable staggered outputs
Disable staggered outputs
D7
D6
DISSTAG
AUTORST
0
0
0
1
Do not automatically reset error registers
and outputs
0
1
Automatically reset error registers and
outputs
0
1
0
1
0
1
0
1
0
1
0
1
Enable interrupt transmission to serializer
Disable interrupt transmission to serializer
INT input = low (read only)
INT input = high (read only)
Output low to GPIO1
D5
D4
D3
D2
D1
D0
DISINT
INT
0
0x06
(read only)
GPIO1OUT
GPIO1
1
Output high to GPIO1
GPIO1 is low
1
(read only)
GPIO1 is high
Output low to GPIO0
GPIO0OUT
GPIO0
1
Output high to GPIO0
GPIO0 is low
1
(read only)
GPIO0 is high
48 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Table 19. MAX9260 Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0x07
0x08
0x09
0x0A
0x0B
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:0]
—
—
—
—
—
01010100
00110000
11001000
00010010
00100000
Reserved
Reserved
Reserved
Reserved
Reserved
01010100
00110000
11001000
00010010
00100000
Error threshold for decoding errors. ERR =
low when DECERR > ERRTHR.
0x0C
0x0D
0x0E
D[7:0]
ERRTHR
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000000
Decoding error counter. This counter
remains zero while the device is in PRBS
test mode.
00000000
(read only)
D[7:0]
DECERR
00000000
(read only)
D[7:0]
D7
PRBSERR
MCLKSRC
MCLKDIV
ID
PRBS error counter
0
MCLK derived from PCLKOUT (see Table 5)
MCLK derived from internal oscillator
MCLK disabled
0
1
0x12
0x1E
0000000
XXXXXXX
D[6:0]
D[7:0]
0000000
MCLK divider
Device identifier
(MAX9260 = 0x02)
00000010
(read only)
00000010
0000
(read only)
D[7:4]
D[3:0]
—
0000
XXXX
Reserved
0x1F
REVISION
Device revision
(read only)
X = Don’t care.
Typical Application Circuit
1.8V
ECU
MAX9259
MAX9260
PCLK
RGB
PCLK
RGB
HSYNC
VSYNC
PCLKIN
PCLKOUT
DOUT(0:27)
CDS
DISPLAY
45.3kI
4.99kI
45.3kI
DIN(0:27)
DIN28
VIDEO
HSYNC
LMN1
LMN0
VSYNC
CDS
AUTOS
4.99kI
TO PERIPHERALS
INT
RX/SDA
TX
RX
TX/SCL
RX/SDA
TX/SCL
IN+
IN-
OUT+
OUT-
UART
SCL
SDA
LOCK
LFLT
LFLT
INT
INT
49.9kI
49.9kI
IMS
MS
MAX9850
WS
SCK
SD
WS
SCK
SD
WS
SCK
SD
WS
SCK
SD
AUDIO
DOUT28/MCLK
MCLK
______________________________________________________________________________________ 49
Gigabit Multimedia Serial Link with Spread
Spectrum and Full-Duplex Control Channel
Chip Information
Package Information
PROCESS: CMOS
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
56 TQFN-EP
64 TQFP-EP
T5688+2
C64E+10
21-0135
21-0084
90-0046
90-0329
50 _____________________________________________________________________________________
Gigabit Multimedia Serial Link with Spread
-Spectrum and Full-Duplex Control Channel
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
9/09
Initial release
—
3, 4, 8, 11, 12, 13, 15,
16, 17, 25, 28, 33, 39,
44, 48
1
7/10
Added clarification of fault thresholds and updated Pin Description table
Added TQFN package to Ordering Information, Absolute Maximum
Ratings, Pin Configurations, Pin Description, and Package Information
2
3
11/10
1/11
1, 2, 10, 11, 50
1
Added Patent Pending to Features
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
51
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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