MAX9288_V01 [MAXIM]
3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output;
| 型号： | MAX9288_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output |
| 文件： | 总103页 (文件大小：2495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
Click here for production status of specific part numbers.
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
General Description
Benefits and Features
The MAX9288/MAX9290 gigabit multimedia serial link
(GMSL) deserializers receive data from a GMSL serializer
over 50Ω coax or 100Ω shielded twisted-pair (STP) cable
and output deserialized data on the CSI-2 outputs.
● Ideal for High-Definition Video Applications
• 4-Lane CSI-2 Output with Up to 1Gbps Per Lane
• Works with Low-Cost 50Ω Coax Cable and FAKRA
Connectors or 100Ω STP
• 104MHz High-Bandwidth Mode Supports
1920 x 720p/60Hz Display with 24-Bit Color
• Equalization Allows 15m Cable at Full Speed
• Up to 192kHz Sample Rate and 32-Bit Sample
Depth For 7.1 Channel HD Audio
• Audio Clock from Audio Source or Audio Sink
• Color Lookup Table for Gamma Correction
• CNTL0–CNTL3 Control Outputs for HDMI/MHL
The MAX9290 has HDCP content protection but other-
wise is the same as the MAX9288. The deserializers pair
with any GMSL serializer capable of coax output. When
programmed for STP input, they are backward compatible
with any GMSL serializer.
2
The audio channel supports L-PCM I S stereo and up to
eight channels of L-PCM in TDM mode. Sample rates of
32kHz to 192kHz are supported with sample depth up to
32 bits.
● Multiple Data Rates for System Flexibility
• Up to 3.12Gbps Serial-Bit Rate
The embedded control channel operates at 9.6kbps
• 6.25MHz to 104MHz Pixel Clock
• 9.6kbps to 1Mbps Control Channel in UART, Mixed
2
to 1Mbps in UART-to-UART and UART-to-I C modes,
2
2
and up to 1Mbps in I C-to-I C mode. Using the control
channel, a µC can program serializer, deserializer, and
peripheral device registers at any time, independent of
video timing, and manage HDCP operation (MAX9290).
Two GPIO ports are included, allowing display power-
up and switching of the backlight, among other uses. A
continuously sampled GPI input supports touch-screen
controller interrupt requests in display applications.
2
2
UART/I C, or I C Mode with Clock-Stretch
Capability
● Reduces EMI and Shielding Requirements
• Tracks Spread Spectrum on Input
• High-Immunity Mode for Maximum Control-
Channel Noise Rejection
● Peripheral Features for System Power-Up and
Verification
For use with longer cables, the deserializers have a pro-
grammable cable equalizer. The serial input meets ISO
10605 and IEC 61000-4-2 ESD standards. The GMSL
supply is 3.0V to 3.6V, the MIPI CSI-2 supply is 1.7V to
1.9V, and the I/O supply is 1.7V to 3.6V.
• Built-In PRBS Tester for BER Testing of the Serial
Link
• Programmable Choice of 8 Default Device
Addresses
• Two Dedicated GPIO Ports
• Dedicated “Up/Down” GPI for Touch-Screen
Interrupt and Other Uses
The devices are available in lead(Pb)-free, 48-pin, 7mm
x 7mm TQFN and SWTQFN packages with exposed pad
and 0.5mm lead pitch.
• Remote/Local Wake-Up from Sleep Mode
● Meets Rigorous Automotive and Industrial
Requirements
Applications
● High-Resolution Automotive Navigation
● Rear-Seat Infotainment
● Megapixel Camera Systems
• -40°C to +105°C Operating Temperature
•
8kV Contact and 12kV Air ISO 10605 and
IEC 61000-4-2 ESD Protection
Simplified Diagram
CSI-2 VIDEO/
Ordering Information appears at end of data sheet.
VIDEO/AUDIO
AUDIO
GMSL
MAX9288
MAX9290
720p
µC
SERIALIZER
DISPLAY
2
2
I C
I C
19-6916; Rev 5; 8/19
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Thermal Characteristics (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Output Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
GMSL-to-CSI-2 Conversion and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Video Data Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Auto Pixel-Per-Line Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Data-Rate Selection and CSI-2 Clock Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GMSL Clock Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
CSI-2 Clock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
High-Bandwidth Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Audio Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Audio Channel Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Audio Channel Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Additional MCLK Output for Audio Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Audio Output Timing Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Control Channel and Register Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Interfacing Command-Byte-Only I2C Devices
with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Maxim Integrated
│ 2
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
(
)
TABLE OF CONTENTS continued
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Bus Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2
I C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Line Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
HS/VS/DE Tracking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Serial Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Coax Splitter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Cable Type Configuration Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Color Lookup Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Programming and Verifying LUT Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
LUT Color Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
LUT Bit Width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Recommended LUT Program Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
High-Immunity Reverse Control-Channel Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Configuration Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Link Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
High-Bandwidth Digital Content Protection (HDCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Encryption Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Synchronization of Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Repeater Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
HDCP Authentication Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
HDCP Protocol Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Example Repeater Network—Two µCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Detection and Action Upon New Device Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Notification of Start of Authentication and Enable of Encryption to Downstream Links . . . . . . . . . . . . . . . . . . . . . 82
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Self PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Error Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
ERR Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Auto Error Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Changing the Clock Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Maxim Integrated
│ 3
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
(
)
TABLE OF CONTENTS continued
Spread-Spectrum Clock Tracking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Fast Detection of Loss-of-Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Providing a Frame Sync (Camera Applications). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Software Programming of the Device Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Key Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
HS/VS/DE Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
WS/SCK Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Line-Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Choosing I2C/UART Pullup Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Selection of AC-Coupling Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chip Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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3.12Gbps GMSL Deserializers
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LIST OF FIGURES
Figure 1. Line Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 2. Reverse Control-Channel Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3. Test Circuit for Differential Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4. Test Circuit for Single-Ended Input Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5. Worst-Case Pattern Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Output Rise-and-Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Deserializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Output I2S Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. MIPI Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. 24-Bit Mode Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. 32-Bit Mode Serial Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. High-Bandwidth Mode Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Transmitting a Frame from GMSL to MIPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. RGB565 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. RGB666 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. RGB888 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. YUV422 8-Bit (Muxed) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. YUV422 10-Bit (Muxed) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. YUV422 8-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. YUV422 10-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25. YUV422 12-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26. RAW 8-Bit (Double Load) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 27. RAW 10-Bit (Double Load) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28. RAW 12-Bit (Double Load) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 29. RAW 8-Bit Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 30. RAW 10-Bit Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 31. RAW 12-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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3.12Gbps GMSL Deserializers
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(
)
LIST OF FIGURES continued
Figure 32. RAW 14-Bit Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33. User-Defined 24-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 34. User-Defined 24-Bit Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 35. Audio Channel Input Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 36. 8-Channel TDM (24-Bit Samples, Padded with Zeros) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 37. 6-Channel TDM (24-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 38. Stereo I2S (24-Bit Samples, Padded with Zeros). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 39. Stereo I2S (16-Bit Samples, No Padding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 40. Audio Channel Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 41. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 42. GMSL UART Data Format for Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 43. SYNC Byte (0x79). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 44. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 45. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0). . . . . . . . 61
2
Figure 46. Format Conversion Between GMSL UART and I C without Register Address (I2CMETHOD = 1) . . . . . 62
Figure 47. START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 48. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 49. Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 50. Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 51. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 52. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 53. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 54. 2:1 Coax Splitter Connection Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 55. Coax Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 56. LUT Dataflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 57. State Diagram (CDS = High). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 58. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s). . . . . 78
Figure 59. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 60. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 61. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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3.12Gbps GMSL Deserializers
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LIST OF TABLES
Table 1. Device Address Defaults (Register 0x00, 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 2 Video Output Map (RGB and YUV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 3. Video Output Map (RAW and User Defined) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 4. Control Output Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5. GMSL Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6. Input Pixel Clock Range (MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 7. Output CSI-2 Data Rate Range (Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 8. Maximum Audio WS Frequency (kHz) for Various Pixel Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9. f
Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SRC
Table 10. I2C Bit-Rate Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 11. Cable Equalizer Boost Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 12. Configuration Input Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 13. Pixel Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 14. Reverse Control-Channel Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 15. Fast High-Immunity Mode Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 16. Startup Procedure for Image-Sensing Applications (CDS = High, Figure 58) . . . . . . . . . . . . . . . . . . . . . . 72
Table 17. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a Repeater)—First
Part of the HDCP Authentication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 18. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption is Enabled . . . . . . . . . . . 76
Table 19. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After Encryption is Enabled . . . . 77
Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First and Second
Parts of the HDCP Authentication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 21. MAX9288/MAX9290 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 22. Line-Fault Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 23. Additional Supply Current from HDCP (MAX9290 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 24. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 25. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 26. HDCP Register Table (MAX9290 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 26. HDCP Register Table (MAX9290 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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3.12Gbps GMSL Deserializers
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(Note 1)
Absolute Maximum Ratings
AVDD3 to EP........................................................-0.5V to +3.9V
AVDD18, DVDD18 to EP......................................-0.5V to +1.9V
IOVDD to EP........................................................-0.5V to +3.9V
IN+, IN- to EP.......................................................-0.5V to +1.9V
LMN_ to EP (15mA current limit)..........................-0.5V to +3.9V
CLK_, DOUT_ to EP ............................................-0.5V to +1.9V
Continuous Power Dissipation (T = +70°C)
A
TQFN/SWTQFN (derate 40mW/°C above +70°C)....3200mW
Junction Temperature......................................................+150°C
Storage Temperature........................................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
All Other Pins to EP ............................-0.5V to (V
+ 0.5V)
IOVDD
IN+, IN- Short Circuit to Ground or Supply ...............Continuous
Note 1: EP connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 2)
TQFN/SWTQFN
Junction-to-Ambient Thermal Resistance (θ ) ..........25°C/W
JA
Junction-to-Case Thermal Resistance (θ ).....................1°C
JC
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.) (Note 3)
A
AVDD3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (ADD_, I2CSEL, PWDN, MS, GPI, DRS, EQS, CDS, HIM, SCK, WS)
0.65 x
High-Level Input Voltage
V
V
IH1
V
IOVDD
0.35 x
Low-Level Input Voltage
Input Current
V
V
IL1
V
IOVDD
+20
I
V
= 0V to V
IOVDD
-20
µA
IN1
IN
THREE-LEVEL LOGIC INPUTS (BWS, CX/TP)
0.7 x
High-Level Input Voltage
Low-Level Input Voltage
V
V
V
IH
V
IOVDD
0.3 x
IOVDD
+10
V
IL
V
Mid-Level Input Current
Input Current
I
(Note 4)
-10
µA
µA
INM
I
-150
+150
IN
SINGLE-ENDED OUTPUTS (WS, SCK, SD, CNTL_, INTOUT)
V
V
IOVDD
- 0.3
DCS = 0
DCS = 1
High-Level Output Voltage
Low-Level Output Voltage
V
I
I
= -2mA
= 2mA
V
V
OH1
OUT
OUT
IOVDD
- 0.2
DCS = 0
DCS = 1
0.3
0.2
V
OL1
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V
1.8V,
A
AVDD18
DVDD18
IOVDD =
V
= V
= 3.3V, T = +25°C.)
AVDD3
IOVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
15
3
TYP
MAX
39
UNITS
V
V
V
V
= 3.0V to 3.6V
25
7
V
= 0V,
IOVDD
IOVDD
IOVDD
IOVDD
O
DCS = 0
= 1.7V to 1.9V
= 3.0V to 3.6V
= 1.7V to 1.9V
15
Output Short-Circuit Current
I
mA
OS
20
5
35
10
63
V
= 0V,
O
DCS = 1
21
MIPI HIGH-SPEED DIFFERENTIAL OUTPUT PORTS (DOUT0–DOUT3_, CLK_) (Note 3)
Transmit Static Common-Mode
Voltage
V
150
140
200
200
250
mV
CMTX
V
Mismatch When Output
CMTX
|ΔV
|
5
mV
mV
mV
CMT(1,0)
is Differential 1 or 0
Transmit Differential Voltage
|V
|
270
14
OD
V
Mismatch When Output is
OD
|ΔV
|
OD
Differential 1 or 0
Output High Voltage
V
360
mV
Ω
OHHS
Single-Ended Output Impedance
Z
40
50
62.5
OS
Mismatch of the single-ended output
impedance at both DOUT_+ and DOUT_-
pins for both differential 1 and 0
Single-Ended Output
Impedance Mismatch
ΔZ
10
%
OS
MIPI LOW-SPEED SINGLE-ENDED OUTPUT PORTS (DOUT0–DOUT3_, CLK_)
Thevenin Output High Level
Thevenin Output Low Level
V
1.05
-50
1.2
1.3
V
OH
V
+50
mV
OL
Output Impedance of Low
Power Transmitter
Z
110
Ω
OLP
OPEN-DRAIN INPUT/OUTPUT (GPIO0, GPIO1, RX/SDA, TX/SCL, ERR, LOCK, LFLT)
0.7 x
High-Level Input Voltage
V
V
V
IH2
V
IOVDD
0.3 x
Low-Level Input Voltage
V
IL2
V
IOVDD
+5
RX/SDA, TX/SCL
-100
-80
Input Current
I
(Note 5)
µA
LOCK, ERR, GPIO_,
LFLT
IN2
+5
I
= 3mA
V
V
= 1.7V to 1.9V
= 3.0V to 3.6V
0.4
0.3
10
OUT
IOVDD
IOVDD
Low-Level Output Voltage
Input Capacitance
V
V
OL2
C
Each pin (Note 6)
pF
IN
LINE-FAULT DETECTION INPUT (LMN0, LMN1)
Short-to-GND Threshold
Normal Threshold
Open Threshold
V
V
V
Figure 1
Figure 1
Figure 1
Figure 1
0.3
V
V
V
V
TG
TN
TO
0.57
1.45
1.49
1.07
+ 0.06
1.75
V
IO
Open Input Voltage
V
IO
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.)
AVDD3
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Short-to-Battery Threshold
OUTPUT FOR REVERSE CONTROL CHANNEL (IN+, IN-)
Forward channel
V
Figure 1
2.47
V
TB
Legacy reverse control-
channel mode
30
50
60
100
-30
-50
60
Differential High Output Peak
Voltage (V ) - (V
V
disabled,
Figure 2
mV
mV
mV
mV
RODH
)
IN-
IN+
High-immunity mode
Legacy reverse control-
channel mode
Forward channel
disabled,
Figure 2
-60
-100
30
Differential Low Output Peak
Voltage (V ) - (V
V
RODL
)
IN-
IN+
High-immunity mode
Legacy reverse control-
channel mode
Single-Ended High Output Peak
Voltage
Forward channel
disabled
V
ROSH
High-immunity mode
50
100
-30
-50
Legacy reverse control-
channel mode
-60
-100
Single-Ended Low Output Peak
Voltage
Forward channel
disabled
V
ROSL
High-immunity mode
DIFFERENTIAL INPUTS (IN+, IN-)
Activity detector medium
threshold, (0x0B D[6:5] = 01)
60
Differential High Input Threshold
V
Figure 3
Figure 3
mV
mV
IDH(P)
(Peak) Voltage (V ) - (V
)
IN+
IN-
Activity detector low
threshold, (0x0B D[6:5] = 00)
52
Activity detector medium
threshold, (0x0B D[6:5] = 01)
-60
Differential Low Input Threshold
(Peak) Voltage (V ) - (V
V
IDL(P)
)
IN+
IN-
Activity detector low
threshold, (0x0B D[6:5] = 00)
-52
1
Input Common-Mode Voltage
((V ) + (V ))/2
V
1.3
1.6
V
CMR
IN+
IN-
Differential Input Resistance
(Internal)
R
80
100
130
Ω
IN
SINGLE-ENDED INPUTS (IN+, IN-)
Activity detector medium
threshold, (0x0B D[6:5] = 01)
43
36
Single-Ended High Input
Threshold (Peak) Voltage
V
Figure 4
Figure 4
mV
ISH(P)
Activity detector low
threshold, (0x0B D[6:5] = 00)
Activity detector medium
threshold, (0x0B D[6:5] = 01)
-43
Single-Ended Low Input
Threshold (Peak) Voltage
V
mV
Ω
ISL(P)
Activity detector low
threshold, (0x0B D[6:5] = 00)
-36
40
Input Resistance (Internal)
R
50
65
I
Maxim Integrated
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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DC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.) (Note 3)
A
AVDD3
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
AVDD3
DVDD18
IOVDD
97
28
131
38
2
BWS = low, f
16.6MHz, 1 MIPI lane,
=
PCLKOUT
0.3
RGB666
AVDD18
21
146
99
33
197
134
Total
AVDD3
DVDD18
IOVDD
45
0.3
25
62
2
BWS = low, f
33.3MHz, 1 MIPI lanes,
RGB666
=
PCLKOUT
AVDD18
34
Total
170
103
69
227
140
94
AVDD3
DVDD18
IOVDD
BWS = low, f
=
PCLKOUT
66.6MHz, 2 MIPI lanes,
RGB666
0.3
29
2
AVDD18
39
Total Supply Current (AVDD_
+ DVDD_ + IOVDD) (Note 7)
(Worst-Case-Pattern, Figure 5)
Total
201
112
100
0.3
46
270
152
139
2
I
mA
WCS
AVDD3
DVDD18
IOVDD
BWS = low, f
104MHz, 2 MIPI lanes,
RGB666
=
PCLKOUT
AVDD18
63
Total
259
100
51
351
136
70
AVDD3
DVDD18
IOVDD
BWS = mid, f
=
PCLKOUT
36.6MHz, 1 MIPI lanes,
RGB888
0.3
27
2
AVDD18
36
Total
178
112
123
0.3
55
236
153
169
2
AVDD3
DVDD18
IOVDD
BWS = mid, f
=
PCLKOUT
104MHz, 2 MIPI lanes,
RGB888
AVDD18
75
Total
290
394
Sleep-Mode Supply Current
Power-Down Current
ESD PROTECTION
I
44
12
120
75
µA
µA
CCS
I
PWDN = GND
CCZ
Human Body Model, R = 1.5kΩ,
D
±8
C
= 100pF
S
Contact discharge
Air discharge
±8
±12
±8
IEC 61000-4-2, R
=
D
IN+, IN- (Note 8)
V
V
kV
kV
ESD
ESD
330Ω, C = 150pF
S
Contact discharge
Air discharge
ISO 10605, R = 2kΩ,
D
C
= 330pF
±20
S
Human Body Model, R = 1.5kΩ,
D
All Other Pins (Note 9)
±2.5
C
= 100pF
S
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3.12Gbps GMSL Deserializers
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AC Electrical Characteristics
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.)
AVDD3
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C/UART PORT TIMING
2
I C/UART Bit Rate
9.6
1000
150
kbps
30% to 70%, C = 10pF to 100pF, 1kΩ
L
Output Rise Time
Output Fall Time
t
20
ns
R
pullup to V
IOVDD
70% to 30%, C = 10pF to 100pF, 1kΩ
L
t
20
150
ns
F
pullup to V
IOVDD
2
I C TIMING (Figure 6)
Low f
range:
SCL
9.6
100
400
(I2CMSTBT = 010, I2CSLVSH = 10)
Mid f range:
SCL
SCL Clock Frequency
f
> 100
> 400
kHz
SCL
(I2CMSTBT 101, I2CSLVSH = 01)
High f range:
(I2CMSTBT = 111, I2CSLVSH = 00)
SCL
1000
Low
4.0
0.6
0.26
4.7
1.3
0.5
4.0
0.6
0.26
4.7
0.6
0.26
0
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
t
f
f
f
f
f
f
f
f
f
range
range
range
range
range
range
range
range
range
Mid
µs
µs
µs
µs
µs
ns
µs
µs
µs
HD:STA
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
High
Low
Mid
t
LOW
High
Low
Mid
t
HIGH
High
Low
Mid
Repeated START Condition
Setup Time
t
SU:STA
HD:DAT
High
Low
Mid
Data Hold Time
t
0
High
Low
Mid
0
250
100
50
Data Setup Time
t
SU:DAT
SU:STO
High
Low
Mid
4.0
0.6
0.26
4.7
1.3
0.5
Setup Time for STOP Condition
Bus Free Time
t
High
Low
Mid
t
BUF
High
Low
Mid
3.45
0.9
Data Valid Time
t
VD:DAT
High
0.45
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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AC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.)
AVDD3
A
PARAMETER
SYMBOL
CONDITIONS
Low
MIN
TYP
MAX
3.45
0.9
UNITS
Data Valid Acknowledge Time
t
f
f
range
range
Mid
µs
VD:ACK
SCL
SCL
High
0.45
50
Low
Pulse Width of Spikes
Suppressed
t
Mid
50
ns
SP
High
50
Capacitive Load Each Bus Line
C
(Note 8)
100
pF
b
SWITCHING CHARACTERISTICS (Note 10)
Deserializer Delay
t
(Note 11) Figure 8
1388
1500
400
Bits
SD
Reverse Control-Channel
Output Rise Time
No forward channel data transmission,
Figure 2
t
180
180
ns
R
Reverse Control-Channel
Output Fall Time
No forward channel data transmission,
Figure 2
t
400
ns
F
Deserializer GPI to serializer GPO (cable
delay not included), Figure 9
GPI-to-GPO Delay
t
350
µs
GPIO
Lock Time
t
Figure 10 (Note 12)
Figure 11
4
ms
ms
LOCK
Power-Up Time
t
8.5
PU
2
I S/TDM OUTPUT TIMING (Note 10)
e-3
1.2
e-3
1.5
f
= 48kHz or
WS
t
= 1/f
,
44.1kHz
x t
x t
WS
WS
WS
WS
(cycle-to-cycle),
rising-to-falling
edge or falling-to-
rising edge
e-3
1.6
e-3
2
WS Jitter
tj
f
f
= 96kHz
ns
ns
WS
WS
WS
x t
x t
WS
WS
e-3
1.6
2e-3 x
t
WS
= 192kHz
x t
WS
n
f
= 16 bits,
SCK
e-3
e-3
13
x t
16
= 48kHz or
WS
x t
SCK
e-3
SCK
t
= 1/f
,
44.1kHz
SCK
SCK
(cycle-to-cycle),
rising-to-rising
edge
2
e-3
SCK Jitter (2-Channel I S)
tj
SCK1
n
f
= 24 bits,
39
x t
48
x t
SCK
= 96kHz
WS
SCK
SCK
n
= 32 bits,
0.1 x
0.13 x
SCK
f
= 192kHz
t
t
WS
SCK
SCK
n
= 16 bits,
= 48kHz or
SCK
e-3
e-3
52
x t
64
x t
f
WS
SCK
SCK
t
= 1/f
,
44.1kHz
SCK
SCK
(cycle-to-cycle),
rising-to-rising
edge
e-3
e-3
SCK Jitter (8-Channel TDM)
tj
ns
n
= 24 bits,
= 96kHz
156
x t
192
SCK2
SCK
f
x t
SCK
WS
SCK
n
= 32 bits,
0.4 x
0.52 x
SCK
f
= 192kHz
t
t
SCK
WS
SCK
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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AC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.)
AVDD3
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
4 x t
UNITS
3 x
Audio Skew Relative to Video
t
Video and audio synchronized
µs
ASK
WS
t
WS
C = 10pF, DCS = 1
0.3
0.4
3.1
3.8
SCK, SD, WS Rise-and-Fall
Time
L
t , t
20% to 80%
ns
ns
ns
ns
ns
R
F
C = 5pF, DCS = 0
L
SD, WS Valid Time Before SCK
0.5 x
t
SCK
t
t
t
t
t
= 1/f
= 1/f
= 1/f
= 1/f
, Figure 12
0.20 x t
DVB1
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
SCK
2
(2-Channel I S)
SD, WS Valid Time After SCK
0.5 x
t
SCK
t
, Figure 12
, Figure 12
, Figure 12
0.20 x t
0.20 x t
0.20 x t
DVA1
2
(2-Channel I S)
SD, WS Valid Time Before SCK
(8-Channel TDM)
0.5 x
t
DVB2
t
SCK
SD, WS Valid Time After SCK
(8-Channel TDM)
0.5 x
t
DVA2
t
SCK
HIGH-SPEED DIFFERENTAIL OUTPUT PORTS (DOUT0_–DOUT3_, CLK_) (Note 10)
Bit rate ≤ 1Gbps
0.3
UI
ps
UI
ns
20% to 80% Rise Time and Fall
Time
t , t
R
F
100
-0.15
1
Data-to-Clock Skew
UI Instantaneous
t
+0.15
12.5
SKW
UI
INS
Common-Level Variation Above
450MHz
ΔV
15
mV
RMS
CM
Common-Level Variation
Between 50MHz to 450MHz
25
mV
PEAK
LOW-SPEED DIFFERENTIAL OUTPUT PORTS (DOUT0_–DOUT3_, CLK_) (Note 10)
15% to 85% Rise Time and Fall
Time
t
/t
25
35
ns
ns
RLP FLP
30% to 85% Rise Time and Fall
Time Transition from HS to LP
t
REOP
GENERAL CSI-2 TIMING SPECIFICATIONS (Note 10, Figure 13)
Time that the transmitter drives the clock
lane LP-00 line state immediately before
HS-0 line state starting the HS transition
Start of Transmission: Clock
Prepare Time
t
CLK-
38
95
ns
ns
PREPARE
CLK-TRAIL
Time that the transmitter drives the HS-0
state after the last payload clock bit of a
HS transmission burst
End of Transmission: Clock
Trail Time
t
60
t
CLK-
PREPARE
t
+ time that the transmitter
CLK-PREPARE
Clock Start of Transmission
Time
drives the HS-0 state prior to starting the
clock
300
ns
+ t
CLK-
ZERO
Maxim Integrated
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
AC Electrical Characteristics (continued)
(V
= V
= 1.7V to 1.9V, V
= 3.0V to 3.6V, V
= 1.7V to 3.6V, R = 100Ω ±1% (differential), EP connected
IOVDD L
AVDD18
DVDD18
AVDD3
to PCB ground (GND), T = -40°C to +105°C, unless otherwise noted. Typical values are at V
= V
= V = 1.8V,
A
AVDD18
DVDD18
IOVDD
V
= 3.3V, T = +25°C.)
AVDD3
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Transmitted time interval from the start
105ns
+ 12 x
UI
Clock End of Transmission
Time
t
of t
or t to start of the
ns
EOT
HS-TRAIL
CLK-TRAIL
LP-11 state following a HS burst
Time that the transmitter drivesLP-11
following a HS burst
HS Exit Time
t
100
ns
ns
HS-EXIT
Time that the transmitter drives the
data lane LP-00 line state immediately
before the HS-0 line state starting the HS
transmission
Start of Transmission: Data
Prepare Time
t
40ns + 4
x UI
85ns +
6 x UI
HS-
PREPARE
t
HS-
PREPARE
t
+ time that the transmitter
HS-PREPARE
145ns + 10
x UI
Start of Transition Time
drives the HS-0 state prior to transmitting
the sync sequence
ns
+ t
HS-
ZERO
Time that the transmitter drives the
flipped differential state after last payload
data bit of a HS transmission burst
Max(8 x UI,
60ns +
4 x UI)
End of Transmission: Data Trail
Time
t
ns
ns
HS-TRAIL
Transmitted length of any low-power state
period
LP Transmit Time
t
50
LPTX
Note 3: Limits are 100% production tested at T = +105°C. Limits over the operating temperature range are guaranteed by design
A
and characterization, unless otherwise noted.
Note 4: To provide a mid level, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than ±10µA.
Note 5:
I
min due to voltage drop across the internal pullup resistor.
IN_
Note 6: Not production tested. Guaranteed by design.
Note 7: HDCP enabled (MAX9290 only). IOVDD current is not production tested. For the MAX9288 (or when HDCP is disabled on
the MAX9290), subtract the HDCP supply current, as shown in Table 25.
Note 8: Specified pin to ground.
Note 9: Specified pin to all supply/ground.
Note 10: Not production tested, guaranteed by characterization.
Note 11: Measured in serial link bit times. Bit time = 1/(30 x f
) for BWS = 0 or open. Bit time = 1/(40 x f
)
PIXEL
PIXEL
for BWS = 1.
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Typical Operating Characteristics
(V
= V
= V
= 1.8V, V
= 3.3V, T = +25°C, unless otherwise noted.)
AVDD18
DVDD18
IOVDD
AVDD3
A
SUPPLY CURRENT
vs. PIXEL CLOCK FREQUENCY (BWS = LOW)
SUPPLY CURRENT
vs. PIXEL CLOCK FREQUENCY (BWS = OPEN)
SUPPLY CURRENT
vs. PIXEL CLOCK FREQUENCY (BWS = HIGH)
toc01
toc02
toc03
260
240
260
260
240
220
200
180
160
140
120
100
PRBS ON,
COAX MODE,
RGB888,
HDCP ON
2 CHANNELS
PRBS ON,
COAX MODE,
RGB666,
HDCP ON
PRBS ON,
COAX MODE,
RGB888,
HDCP ON
2 CHANNELS
EQ ON
240
220
200
180
160
140
120
100
EQ ON
EQ ON
220
200
180
160
140
120
100
2 CHANNELS
EQ OFF
EQ OFF
75
EQ OFF
5
15 25 35 45 55 65 75 85 95 105
PCLK FREQUENCY (MHz)
15
30
45
60
90
105
5
20
35
50
65
80
PCLK FREQUENCY (MHz)
PCLK FREQUENCY (MHz)
SUPPLY CURRENT
SUPPLY CURRENT
vs. PIXEL CLOCK FREQUENCY (BWS = LOW)
vs. PIXEL CLOCK FREQUENCY (BWS = OPEN)
toc04
toc05
260
240
220
200
180
160
140
120
100
260
240
220
200
180
160
140
120
100
PRBS ON,
COAX MODE,
RGB888,
HDCP ON
4 CHANNELS
PRBS ON,
COAX MODE,
RGB666,
HDCP ON
EQ ON
EQ ON
4 CHANNELS
EQ OFF
EQ OFF
5
15 25 35 45 55 65 75 85 95 105
PCLK FREQUENCY (MHz)
15
30
45
60
75
90
105
PCLK FREQUENCY (MHz)
SUPPLY CURRENT
vs. PIXEL CLOCK FREQUENCY (BWS = HIGH)
MAXIMUM PIXEL CLOCK FREQUENCY
vs. COAX CABLE LENGTH (BER ≤ 10-10
)
toc07
toc06
120
100
80
60
40
20
0
260
240
220
200
180
160
140
120
100
PRBS ON,
COAX MODE,
RGB888,
HDCP ON
4 CHANNELS
EQ ON
OPTIMUM
PE/EQ
NO PE/EQ
NO PE,
10.7dB EQ
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 15m
EQ OFF
5
20
35
50
65
80
0
5
10
15
20
25
PCLK FREQUENCY (MHz)
CABLE LENGTH (m)
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Typical Operating Characteristics (continued)
(V
= V
= V
= 1.8V, V
= 3.3V, T = +25°C, unless otherwise noted.)
AVDD18
DVDD18
IOVDD
AVDD3
A
MAXIMUM PIXEL CLOCK FREQUENCY
MIPI CLOCK EYE PATTERN
MIPI CLOCK EYE PATTERN
vs. STP CABLE LENGTH (BER ≤ 10-9)
80Mbps
1000Mbps
toc09
toc10
toc08
120
100
80
60
40
20
0
OPTIMUM
PE/EQ
NO PE/EQ
NO PE,
10.7dB EQ
100mV/div
100mV/div
6dB PE,
10.7dB EQ
BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 12m
0
5
10
15
20
2ns/div
200ps/div
CABLE LENGTH (m)
MIPI DATA EYE PATTERN
MIPI DATA EYE PATTERN
80Mbps
1000Mbps
toc11
toc12
100mV/div
100mV/div
2ns/div
200ps/div
MIPI SOT
MIPI EOT
toc13
toc14
500mV/div
500mV/div
50ns/div
50ns/div
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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Pin Configuration
TOP VIEW
35 34 33 32 31 30 29 28 27
25
36
26
RSVD
DVDD18
CDS
DVDD18
ADD1/CNTL3
ADD0/CNTL0
24
23
22
37
38
39
21 IOVDD
LOCK 40
ERR 41
DRS 42
20 HIM/CNTL1
19 ADD2/CNTL2
MAX9288
MAX9290
18
43
SD
IOVDD
17 SCK
16 WS
LFLT 44
LMN0 45
PWDN
LMN1
AVDD3
CX/TP
15
14
13
46
47
48
EP*
+
TX/SCL
RX/SDA
2
1
3
4
5
6
7
8
9
10 11 12
TQFN/SWTQFN
(7mm x 7mm x 0.75mm)
CONNECT EP TO GROUND PLANE
Pin Description
PIN
NAME
INTOUT
GPI
FUNCTION
A/V Status Register Interrupt Output. Indicates new data in the A/V status registers. INTOUT is reset
when the A/V status registers are read.
1
2
General-Purpose Input with Internal Pulldown to EP. The serializer GPO (or INT) output follows GPI.
2
I C Select. Control channel interface protocol select input with internal pulldown to EP. Set I2CSEL =
3
I2CSEL
GPIO0
2
high to select I C interface. Set I2CSEL = low to select UART interface.
4
Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD
Three-Level Bus Width Select Input. Set BWS to the same level on both sides of the serial link. Set
BWS = low, with 6kΩ (max) pulldown for 24-bit mode. Set BWS = high, with 6kΩ (max) pullup to
IOVDD for 32-bit mode. Set BWS = open for high-bandwidth mode.
5
BWS
3.3V Analog Power Supply. Bypass AVDD3 to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD3.
6, 47
AVDD3
7
IN+
IN-
Noninverting Coax/Twisted-Pair Serial Input
Inverting Coax/Twisted-Pair Serial Input
8
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3.12Gbps GMSL Deserializers
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Pin Description (continued)
PIN
NAME
FUNCTION
Mode Select with Internal Pulldown to EP. MS sets the control-link mode when CDS = high. Set MS
= low, to select base mode. Set MS = high to select the bypass mode. MS sets autostart mode when
CDS = low.
9
MS
10, 23,
37
1.8V Digital Power Supply. Bypass DVDD18 to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller value capacitor closest to DVDD18.
DVDD18
GPIO1
11
Open-Drain, General-Purpose Input/Output, with Internal 60kΩ Pullup to IOVDD
Equalizer Select Input, with Internal Pulldown to EP. The state of EQS latches upon power-up or
when resuming from power-down mode (PWDN = low). Leave EQS open for 10.7dB equalizer boost
(EQTUNE = 1001). Connect EQS to IOVDD with a 30kΩ resistor for 5.2dB equalizer boost (EQTUNE =
0100).
12
EQS
2
UART Receive/I C Serial Data Input/Output, with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of I2CSEL at power-up. RX/SDA has an open-drain driver and requires a
13
14
RX/SDA
pullup resistor.
RX: Input of the deserializer’s UART.
SDA: Data input/output of the deserializer’s I C Master/Slave.
2
2
UART Transmit/I C Serial Clock Input/Output, with Internal 30kΩ Pullup to IOVDD. Function is
determined by the state of I2CSEL at power-up. TX/SCL has an open-drain driver and requires a pullup
resistor.
TX/SCL
TX: Output of the deserializer’s UART.
SCL: Clock input/output of the deserializer’s I C Master/Slave.
2
Active-Low, Power-Down Input, with Internal Pulldown to EP. Set PWDN low to enter power-down
mode to reduce power consumption.
15
16
PWDN
2
2
I S/TDM Word-Select Input/Output. Powers up as an I S output (deserializer provided clock). Set
AUDIOMODE bit = ‘1’ to change WS to an input with internal pulldown to GND and supply WS
externally (system provided clock).
WS
2
2
I S/TDM Serial-Clock Input/Output. Powers up as an I S output (deserializer provided clock). Set
AUDIOMODE bit = ‘1’ to change SCK to an input with internal pulldown to GND and supply SCK
externally (system provided clock).
17
18
SCK
2
2
I S/TDM Serial-Data Output. Disable I S/TDM encoding to serial data to use SD as an additional
SD
control/data output. Encrypted when HDCP is enabled.
Address Selection Input/Auxiliary Control Signal Output, with Internal Pulldown to EP. Functions as
ADD2 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL2 output automatically after power-up.
19
ADD2/CNTL2 ADD2: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect ADD2/CNTL2 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL2: Used only in 32-bit and high-bandwidth mode (BWS = high, open). CNTL2 is mapped from the
GMSL serializer’s CNTL2 or DIN28 input.
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3.12Gbps GMSL Deserializers
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Pin Description (continued)
PIN
NAME
FUNCTION
High-Immunity Mode Input/Auxiliary Control Signal Output With Internal Pulldown to EP. Functions
as HIM input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL2 output automatically after power-up.
HIM: Default HIGHIMM bit value is latched at power-up or when resuming from power-down mode
(PWDN = low) and is active-high. Connect HIM/CNTL1 to IOVDD with a 30kΩ resistor to set high or
leave open to set low. HIGHIMM can be programmed to a different value after power-up. HIGHIMM in
the serializer must be set to the same value.
20
HIM/CNTL1
CNTL1: Used only in 32-bit and high-bandwidth mode (BWS = high, open). CNTL1 is mapped from the
GMSL serializer’s CNTL1, DIN27, or RES input.
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1µF and 0.001µF
capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD.
21, 43
IOVDD
CDS
Control Direction Selection Input, with Internal Pulldown to EP. Control link direct selection input
with internal pulldown to EP. Set CDS = low when the control channel master µC is connected at the
serializer. Set CDS = high when the control channel master µC is connected at the deserializer.
22
24
RES
Reserved. Leave unconnected
1.8V Analog Power Supply. Bypass AVDD18 to EP with 0.1µF and 0.001µF capacitors as close as
possible to the device with the smaller capacitor closest to AVDD18.
25, 36
AVDD18
26–29,
32–35
DOUT_+,
DOUT_-
CSI-2 Data Outputs
CSI-2 Clock Output
30, 31
CLK+, CLK-
Auxiliary Control Signal Output/Address Selection Input, with Internal Pulldown to EP. Functions as
ADD1 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL3 output automatically after power-up.
38
ADD1/CNTL3
ADD1: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low). See
Table 1. Connect ADD1/CNTL3 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL3: Used only in high-bandwidth mode (BWS = open.
Auxiliary Control Signal Output/Address Selection Input, with Internal Pulldown to EP. Functions as
ADD0 input at power-up or when resuming from power-down mode (PWDN = low), and switches to
CNTL0 output automatically after power-up.
39
ADD0/CNTL0
ADD0: Bit value is latched at power-up or when resuming from power-down mode (PWDN = low).
See Table 1. Connect ADD0/CNTL0 to IOVDD with a 30kΩ resistor to set high or leave open to set low.
CNTL0: Used only in high-bandwidth mode (BWS = open).
Open-Drain Lock Output, with Internal 60kΩ Pullup to IOVDD. LOCK = high indicates that PLLs are
locked with correct serial-word-boundary alignment. LOCK = low indicates that PLLs are not locked or
an incorrect serial-word-boundary alignment. LOCK is high when PWDN = low.
40
41
LOCK
Error Output. Open-drain data error detection and/or correction indication output with internal 60kΩ
pullup to IOVDD. ERR is high when PWDN is low.
ERR
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3.12Gbps GMSL Deserializers
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Pin Description (continued)
PIN
NAME
FUNCTION
Data-Rate Select Input. DRS is latched upon power-up or when PWDN transitions low-to-high. Set
DRS high for pixel clock rates below 16.66MHz (BWS = low), 12.5MHz (BWS = high), or 36.66MHz
(BWS = open). Set DRS = low for faster pixel clock rates.
42
DRS
Active-Low Open-Drain Line-Fault Output. LFLT has a 60kΩ internal pullup to IOVDD. LFLT = low
indicates a line fault. LFLT is high when PWDN = low.
44
LFLT
45
46
LMN0
LMN1
Line Fault Monitor Input 0 (See Figure 1)
Line Fault Monitor Input 1 (See Figure 1)
Three-Level Coax/Twisted Pair Select Input. Use 6kΩ (max) pullup to IOVDD or pulldown resistor for
setting CX/TP = high or low. See Table 12 for function.
48
—
CX/TP
EP
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground plane
through an array of vias for proper thermal and electrical performance.
Functional Diagram
PLL
CLKDIV
HDCP
CDRPLL
MAX9288
MAX9290
CLK±
(MAX9290
ONLY)
CX/TP
RGB
RGB
DOUT0±
DECRYPT
VIDEO
SYNC
IN+
IN-
SERIAL TO
PARALLEL
HS
VS
DE
HS
VS
DE
PARALLEL
DOUT1±
TO CSI-2
CML RX
AND EQ
HDCP
KEYS CONTROL
HDCP
DOUT2±
DOUT3±
8B/10B
DECODE/
DESCRAMBLE
FIFO
TX
CONTROL
(9B10B)
CNTL[3:0]
(9B10B)
ADD0/CNTL0,
HIM/CNTL1,
ADD2/CNTL2,
ADD1/CNTL3
REVERSE
CONTROL
CHANNEL
HDCP
DECRYPT
ACB
ADD[2:0],
HIM
I2S/TDM
FCC
ADD[2:0]
MS
CONTROL
DATA DESCRIPTION
REGISTERS
UART/I2C
PWDN
BWS
INTOUT
CDS
EQS
SD
WS
SCK
GPI GPIO_
I2CSEL
TX/
RX/
SCL SDA
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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1.8V
MAX9288/MAX9290
45.3ꢁΩ*
4.99ꢁΩ*
45.3ꢁΩ*
4.99ꢁΩ*
GMSL
DESERIALIZER
LMN0
LMN1
LMN0
GMSL
DESERIALIZER
OUTPUT
LOGIC
(IN+)
TWISTED PAIR
IN+
IN-
49.9ꢁΩ*
49.9ꢁΩ*
CONNECTORS
LFLT
REFERENCE
VOLTAGE
1.8V
GENERATOR
45.3ꢁΩ*
4.99ꢁΩ*
LMN1
LMN0
GMSL
DESERIALIZER
OUTPUT
LOGIC
(IN-)
COAX
IN+
IN-
49.9ꢁΩ*
49.9Ω*
CONNECTORS
*±1ꢀ
TOLERANCE
Figure 1. Line Fault
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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R /2
L
IN+
IN-
MAX9288
MAX9290
V
OD
REVERSE
CONTROL-CHANNEL
TRANSMITTER
V
CMR
R /2
L
IN+
IN-
V
CMR
IN-
IN+
V
ROH
0.9 x V
ROH
0.1 x V
ROH
(IN+) - (IN-)
0.1 x V
ROL
ROL
t
R
0.9 x V
V
ROL
t
F
Figure 2. Reverse Control-Channel Output Parameters
R /2
L
IN+
IN-
VIS(P)
IN_
0.22µF
49.9Ω
V
ID(P)
R /2
L
_
V
IN+
+
_
C
C
IN
IN
+
-
VIN_
+
_
V
IN-
CIN
V ꢀ V - V ꢀ
ID(P) = IN+ IN-
V
(V + V )/2
CMR = IN+ IN-
Figure 4. Test Circuit for Single-Ended Input Measurement
Figure 3. Test Circuit for Differential Input Measurement
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3.12Gbps GMSL Deserializers
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200 PCLK
CYCLES
200 PCLK
CYCLES
2000 PCLK CYCLES
2000 PCLK CYCLES
SIGNAL1
VS2
DE/HS3
DIN_ (EVEN INPUTS)
DIN_ (ODD INPUTS)
PCLKIN
1. GMSL SERIALIZER INPUT SIGNAL
2. VS STARTS LOW AND REMAINS HIGH
3. REGISTER SETTING DETERMINES IF DE OR HS IS USED
Figure 5. Worst-Case Pattern Output
START
CONDITION
(S)
BIT 7
MSB
(A7)
STOP
CONDITION
(P)
BIT 6
(A6)
BIT 0
(R/W)
ACKNOWLEDGE
(A)
PROTOCOL
t
t
t
HIGH
SUꢀSTA
LOW
1/ꢂ
SCL
V
V
x 0.7
x 0.3
IOVDD
IOVDD
SCL
t
SP
t
t
ꢂ
BUF
t
ꢁ
V
x 0.7
x 0.3
IOVDD
SDA
V
IOVDD
t
t
t
t
t
SUꢀSTO
HDꢀSTA
t
HDꢀDAT
VDꢀDAT
VDꢀACK
SUꢀDAT
2
Figure 6. I C Timing Parameters
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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C
L
SINGLE-ENDED OUTPUT LOAD
0.8 x V
I0VDD
0.2 x V
I0VDD
t
t
R
F
Figure 7. Output Rise-and-Fall Times
SERIAL WORD LENGTH
SERIAL WORD N
(FIRST PIXEL WORD OF A LINE)
SERIAL WORD N+1
SERIAL WORD N+2
FIRST BIT
TxDOUT+
LAST BIT
SERIAL BYTE N, N+1, N+2
TxDOUT-
tSD
Figure 8. Deserializer Delay
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3.12Gbps GMSL Deserializers
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V
IH_MIN
DESERIALIZER
GPI
V
IL_MAX
t
GPIO
t
GPIO
V
OH_MIN
SERIALIZER
GPO
V
OL_MAX
Figure 9. GPI-to-GPO Delay
IN+, IN-
IN+, IN-
V
IH1
PWDN
LOCK
t
LOCK
t
PU
LOCK
V
OH
V
OH
PWDN MUST BE HIGH
Figure 10. Lock Time
Figure 11. Power-Up Delay
WS
SCK
SD
t
t
DVB
DVA
t
R
t
t
DVA
DVB
t
F
2
Figure 12. Output I S Timing Parameters
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
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tLPTX
tCLK-PREPARE
tCLK-ZERO
CLK+/-
NOTE: THE CSI
CLOCK RUNS IN
CONTINUOUS
MODE ONLY.
VIL(max)
VTERM-EN(max)
VIDTH(max)
TD-TERM-EN
LP-01
LP-11
LP-00
tHS-SETTLE
CLK+/-
tLPTX
tHS-PREPARE
tHS-ZERO
tHS-SYNC
DISCONNECT TERMINATOR
VIH(min)
DOUT_+/-
VIL(max)
VTERM-EN(max)
VIDTH(max)
tD-TERM-EN
LP-01
CAPTURE 1ST DATA BIT
tREOT
LP-11
LP-00
tHS-SETTLE
LP-11
tHS-EXIT
tHS-SKIP
tEOT
tHS-TRAIL
Figure 13. MIPI Output Timing Parameters
The control channel enables a µC to program the serial-
izer and deserializer registers and program registers on
peripherals. The control channel is also used to perform
HDCP functions (MAX9290 only). The µC can be located
at either end of the link, or when using two µCs, at both
ends. Two modes of control-channel operation are avail-
Detailed Description
The MAX9288/MAX9290 deserializers, when paired with
the MAX9275/MAX9277/MAX9279/MAX9281 serializ-
ers, provide the full set of operating features, but are
backward-compatible with the MAX9249–MAX9270 fam-
ily of gigabit multimedia serial link (GMSL) devices, and
have basic functionality when paired with any GMSL
device. The MAX9290 has high-bandwidth digital content
protection (HDCP), while the MAX9288 does not.
2
able. Base mode uses either I C or GMSL UART protocol,
while bypass mode uses a user-defined UART protocol.
UART protocol allows full-duplex communication, while
2
I C allows half-duplex communication.
Each deserializer has a maximum serial-bit rate of
3.12Gbps for up to 15m of cable and operates up to a
maximum output clock of 104MHz in 24-bit mode and
27-bit high-bandwidth mode, or 78MHz in 32-bit mode.
This bit rate and output flexibility support a wide range
of displays, from QVGA (320 x 240) to 1920 x 720 and
higher with 24-bit color, as well as megapixel image sen-
The serial input complies with ISO 10605 and IEC 61000-
4-2 ESD protection standards.
Register Mapping
Registers set the operating conditions of the deserial-
izers and are programmed using the control channel
in base mode. The MAX9288/MAX9290 holds its own
device address and the device address of the serial-
izer it is paired with. Similarly, the serializer holds its
own device address and the address of the MAX9288/
MAX9290. Whenever a device address is changed, be
sure to write the new address to both devices. The default
device address of the deserializer is set by the ADD_ and
CX/TP inputs (Table 1). Registers 0x00 and 0x01 in both
devices hold the device addresses.
2
sors. An encoded audio channel supports L-PCM I S
stereo and up to eight channels of L-PCM in TDM mode.
Sample rates of 32kHz to 192kHz are supported with
sample depth from 8 to 32 bits. Input equalization, com-
bined with GMSL serializer pre/deemphasis, extends the
cable length and enhances link reliability.
Maxim Integrated
│ 27
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 1. Device Address Defaults (Register 0x00, 0x01)
SERIALIZER
DEVICE
DESERIALIZER
DEVICE
DEVICE ADDRESS
PIN
(BIN)
ADDRESS
(hex)
ADDRESS
(hex)
CX/TP
ADD2
ADD1
ADD0
D7 D6 D5 D4 D3 D2 D1
D0
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
High/Low
Open**
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
High
High
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
X*
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
80
84
88
44
C0
C4
C8
48
80
84
88
44
C0
C4
C8
48
90
94
98
54
D0
D4
D8
58
92
96
9A
56
D2
D6
DA
5A
0
0
0
0
0
0
X*
X*
X*
X*
X*
X*
X*
X*
Open**
Open**
Open**
Open**
Open**
Open**
Open**
*X = 0 for the serializer address, X = 1 for the deserializer address.
**CX/TP determine the serial-cable type CX/TP = open addresses only for coax mode.
special control-signal packets. In all modes, the last 3 bits
contain the embedded audio channel, the embedded for-
ward control channel, and the parity bit of the serial word
(Figure 14, Figure 15, Figure 16).
Output Bit Map
The input/output bit width depends on settings of the bus
width pin (BWS) and the CSI-2 output mode. Table 4 and
Table 3 list the bit map for video signals. Table 4 lists the
bit map for control signals. Unused control output bits are
pulled low.
GMSL-to-CSI-2 Conversion and Output
The GMSL deserializer recovers the clock from the
serialized input signals and extracts the video, audio,
and control. Video data are packetized to according to
MIPI CSI-2 packet formats and sent out through the MIPI
DPHY serial lanes.
Serial Link Signaling and Data Format
The serializer uses differential CML signaling to drive
twisted-pair cable and single-ended CML to drive
coaxial cable with programmable pre/deemphasis and
AC-coupling. The deserializer uses AC-coupling and
programmable channel equalization.
Video Data Operation
The device converts the video control signal VS to the
CSI-2 Frame Start or Frame End short packet (Figure 17).
The converter also assembles the pixel color data into
the CSI-2 long packets based on the formats and/or pixel
count programmed by the user (Figure 18, Figure 19,
Figure 20, Figure 21, Figure 22, Figure 23, Figure 24,
Figure 25, Figure 26, Figure 27, Figure 28, Figure 29,
Figure 30, and Figure 31). DE low period needs to be a
minimum 200 PCLK cycles to accommodate SOT and
EOT during the DE blanking period.
Input data is scrambled and then 8b/10b coded (9b/10b
in high-bandwidth mode). The deserializer recovers the
embedded serial clock, then samples, decodes, and
descrambles the data. In 24-bit mode, the first 21 bits
contain 18 bits of video data and 3 bits of control data
(HS/VS/DE). In 32-bit mode, the first 29 bits contain
24 bits of video data, 3 bits of control data (HS/VS/DE)
and two bits of control data (CNTL1/CNTL2). In high-
bandwidth mode, the first 24 bits contain video data, or
Maxim Integrated
│ 28
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
24 BITS
SERIAL DATA
D0
D1
D17
D18
D19
D20
ACB
FCC
AUDIO DECODE
SCK
PCB
PACKET
PARITY CHECK
BIT
FORWARD
CONTROL-
CHANNEL BIT
INTERNAL
PARALLEL BIT
DOUT18/ DOUT19/ DOUT20/
HS
RX/
SDA
DOUT0 DOUT1
DOUT17
WS
SD
TX/SCL
VS
DE
HS
VS
DE
UART/I2C
VIDEO DATA (TO
CONTROL BITS
(TO CSI-2)
I2S/TDM
AUDIO
CSI-2)
DE/VS/HS MUST BE SET AT DOUT[20:18]
MAX9290 NOTE: ONLY DOUT[17:0] AND AUDIO HAVE HDCP ENCRYPTION.
Figure 14. 24-Bit Mode Serial Data Format
32 BITS
SERIAL
DATA
D0
D1
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
ACB
FCC
PCB
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
AUDIO DECODE
INTERNAL
PARALLEL
BIT
DOUT DOUT
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
RX/
SDA
TX/
SCL
CNTL1 CNTL2 WS
SCK
SD
0
1
17
18/HS 19/VS 20/DE
21
22
23
24
25
26
HS VS DE
VIDEO DATA
(TO CSI-2)
CONTROL BITS
(TO CSI-2)
VIDEO DATA
(TO CSI-2)
AUX CONTROL
BITS
I2S/TDM
AUDIO
UART/I2C
DE/VS/HS MUST BE SET AT DOUT[20:18].
MAX9290 NOTE: ONLY DOUT[17:0], DOUT[26:21], AND AUDIO HAVE HDCP ENCRYPTION.
Figure 15. 32-Bit Mode Serial Data Format
Maxim Integrated
│ 29
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
27 BITS
27 BITS
SERIAL DATA
D0
D1
D17
D18
D19
D20
D21
D22
D23
ACB
FCC
AUDIO DECODE
SCK
PCB
SPECIAL SERIAL-DATA PACKET
CONTROL-SIGNAL DECODING
FORWARD
CONTROL-
CHANNEL BIT
PACKET
PARITY
CHECK BIT
DOUT
0
DOUT
1
DOUT
17
DOUT
21
DOUT
22
DOUT
23
DOUT
24
DOUT
25
DOUT
26
RX/
TX/
CNTL0/ DOUT27/ DOUT28/ CNTL3
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
INPUT PIN
WS
SD
SDA
SCL
ADD0
CNTL1 CNTL2
ADD1
INPUT
SIGNAL
R0
R1
B5
R6
R7
G6
G7
B6
B7
HS
VS
DE
2
2
I S/TDM
UART/I C
AUX
CONTROL
BITS
CONTROL BITS
RGB DATA
RGB DATA
AUDIO
VS/HS MUST BE SET AT DOUT[20:18].
MAX9290 NOTE: ONLY DOUT[17:0], DOUT[26:21] AND ACB HAVE HDCP ENCRYPTION.
Figure 16. High-Bandwidth Mode Serial-Data Format
≥ 200PCLK
VS
≥ 200PCLK
≥ 200PCLK
≥ 200PCLK
HS*
DE*
≥ 200PCLK
DOUT
CSI-2 DOUT_±
SPKT
SPKT
LPKT
LPKT
LPS SOT FS EOT LPS
LPS SOT PH
DATA
PF EOT LPS
LPS SOT FE EOT LPS
*REGISTER SETTING DETERMINES WHETHER DE OR HS IS USED FOR PACKET TIMING
KEY:
SOT: START OF TRANSMISSION
PH: PACKET HEADER
FS: FRAME START
EOT: END OF TRANSMISSION
PF: PACKET FOOTER
FE: FRAME END
LPS: LOW POWER STATE
Figure 17. Transmitting a Frame from GMSL to MIPI
Maxim Integrated
│ 30
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
NO INPUT WHEN BWS = LOW
RGB565
GMSL
DOUT0 DOUT1
PARALLEL BIT
DOUT18 DOUT19 DOUT20
DOUT4 DOUT5 DOUT6
DOUT10 DOUT11 DOUT12
DOUT15 DOUT16 DOUT17
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
R-0
R-1
R-4
G-0
G-1
G-5
B-0
B-1
B-4
RES
RES
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
B1[4:0]
WRD 2
R1[4:0]
WRD 3
B2[4:0]
WRD 4
R2[4:0]
WORD (WC – 3)
B(N-1)[4:0]
WORD (WC – 2)
R(N-1)[4:0]
WORD (WC -1)
WORD WC
R(N)[4:0]
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
G1[5:0]
G2[5:0]
G(N-1)[5:0]
B(N)[4:0]
G(N)[5:0]
LSB
B-0
MSB
B-3
LSB
G-0
MSB
G-4
LSB
R-0
MSB
R-4
B-1
B-2
B-4
G-1
G-2
G-3
G-5
R-1
R-2
R-3
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
16
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
2
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N
2N
Figure 18. RGB565 Output
Maxim Integrated
│ 31
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
RGB666
GMSL
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
PARALLEL BIT
DOUT5 DOUT6 DOUT7
DOUT11 DOUT12 DOUT13
DOUT17
B-4
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
R-0
R-1
R-4
G-0
G-1
G-5
B-0
B-1
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WORD 1
B1[5:0]
WORD 2
WORD 3
B2[5:0]
WORD 4
WORD (WC) - 3
WORD (WC) - 2
R(N-1)[5:0]
LSB
WORD (WC) -1
WORD WC
R(N)[5:0]
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
G1[5:0]
R1[5:0]
B-2
G2[5:0]
R2[5:0]
B(N-1)[5:0]
G(N-1)[5:0]
B(N)[5:0]
G(N)[5:0]
LSB
B-0
MSB
B-5
MSB
R-5
B-1
B-3
B-4
R-0
R-1
R-2
R-3
R-4
LSB
G-0
MSB
G-5
G-1
G-2
G-3
G-4
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
18
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
2.25
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
9/4 X N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4
Figure 19. RGB666 Output
Maxim Integrated
│ 32
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
RGB888
(BWS = HIGH OR OPEN)
GMSL
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
PARALLEL BIT*
DOUT5 DOUT6 DOUT7
DOUT11 DOUT12 DOUT13
DOUT17
B-5
DOUT21 DOUT22 DOUT23 DOUT24 DOUT25 DOUT26
/HS
/VS
/DE
R-0
R-1
R-5
G-0
G-1
G-5
B-0
B-1
R-6
R-7
G-6
G-7
B-6
B-7
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
B1[7:0]
WRD 2
WRD 3
R1[7:0]
WRD 4
B2[7:0]
WRD 5
WRD 6
R2[7:0]
WRD WC - 5
B(N-1)[7:0]
WRD WC - 4
G(N-1)[7:0]
WRD WC - 3
R(N-1)[7:0]
WRD WC- 2
B(N)[7:0]
WRD WC -1
G(N)[7:0]
WRD WC
R(N)[7:0]
LINE
START
PACKET HEADER
LINE STOP
G1[7:0]
G2[7:0]
PACKET FOOTER
D0
B-0
D1
B-1
D2
B-2
D3
B-3
D4
B-4
D5
B-5
D6
B-6
D7
B-7
D0
G-0
D1
G-1
D2
G-2
D3
G-3
D4
G-4
D5
G-5
D6
G-6
D7
G-7
D0
R-0
D1
R-1
D2
R-2
D3
R-3
D4
R-4
D5
R-5
D6
R-6
D7
R-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
WORD COUNT
PIXEL
1
BYTES
3
BITS
24
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
N
3N
GMSL BIT NAME
MIPI BIT NAME
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
OLDI = 0 (VESA)
OLDI = 1 (oDLI)
R7 (MSB)
R6
R5 (MSB)
R4
R7 (MSB)
R6
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
R5
R4
R3
R2
R1
R0 (LSB)
R3
R2
R1
R0
R7
R6 (LSB)
R5
R4
R3
R2
R1
R0 (LSB)
*VESA AND oLDI DEFINE NAMING CONVENTIONS WITH REGARDS TO MSB AND LSB.
THE GMSL TO MIPI MAPPING IS SHOWN IN THE TABLE TO THE RIGHT.
Figure 20. RGB888 Output
Maxim Integrated
│ 33
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
NO INPUT WHEN BWS =
LOW
GMSL TO CSI-2
YUV422 8 BIT (MUXED)
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
DOUT7 DOUT8
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
CB-0
CB-1
CB-7
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
DOUT7 DOUT8
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
Y-0
Y-1
Y-7
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
DOUT7 DOUT8
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
CR-0
CR-1
CR-7
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
DOUT7 DOUT8
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
Y-0
Y-1
Y-7
RES
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
Y1[7:0]
WRD 3
WRD 4
Y2[7:0]
WRD WC - 3
WRD WC- 2
Y(N-1)[7:0]
WRD WC -1
CR(N)[7:0]
WRD WC
Y(N)[7:0]
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
CB1[7:0]
CR2[7:0]
CB(N-1)[7:0]
D0
CR-0
D1
CR-1
D2
CR-2
D3
CR-3
D4
CR-4
D5
CR-5
D6
CR-6
D7
CR-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
CB-0
D1
CB-1
D2
CB-2
D3
CB-3
D4
CB-4
D5
CB-5
D6
CB-6
D7
CB-7
D0
Y-0
D1
Y-1
D2
Y-2
D3
Y-3
D4
Y-4
D5
Y-5
D6
Y-6
D7
Y-7
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
DATA TYPE
SELECT
WORD COUNT
BYTES
1 OF 4 CHANNEL SELECT
DESCRIPTION
PIXEL
1
BITS
16
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
2
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N
2N
Figure 21. YUV422 8-Bit (Muxed) Output
Maxim Integrated
│ 34
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
NO INPUT WHEN BWS =
LOW
GMSL TO CSI-2
YUV422 10 BIT (MUXED)
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
CB-0
CB-1
CB-2
CB-9
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
Y-0
Y-1
Y-2
Y-9
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
CR-0
CR-1
CR-2
CR-9
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
Y-0
Y-1
Y-2
Y-9
RES
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
Y1[9:2]
WRD 3
WRD 4
Y2[9:2]
WRD 5
LSB
WRD WC - 4
CB(N-1)[9:2]
WRD WC - 3
Y(N-1)[9:2]
WRD WC- 2
CR(N)[9:2]
WRD WC -1
WRD WC
LSB
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
CB1[9:2]
CR2[9:2]
Y(N)[9:2]
D0
CB1-0
D1
CB1-1
D2
Y1-0
D3
Y1-1
D4
D5
D6
Y2-0
D7
Y2-1
CR2-0 CR2-1
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
CR-2
Y-2
D1
CR-3
D2
CR-4
Y-3
CB-3
D3
CR-5
Y-5
CB-5
D4
CR-6
D5
CR-7
Y-7
D6
CR-8
D7
CR-9
Y-9
Y-4
CB-4
Y-6
Y-8
CB-2
CB-6
CB-7
CB-8
CB-9
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
WORD COUNT
BYTES
2.5
PIXEL
1
BITS
20
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
2.5N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2
Figure 22. YUV422 10-Bit (Muxed) Output
Maxim Integrated
│ 35
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
YUV422 8 BIT
NO INPUT WHEN BWS
= LOW
DOUT
0
DOUT
1
DOUT
7
DOUT
8
DOUT
9
DOUT
15
DOUT
16
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
26
CB-0
CB-1
CB-7
Y-0
Y-1
Y-7
RES
RES
HS
VS
DE
RES
RES
DOUT
0
DOUT
1
DOUT
7
DOUT
8
DOUT
9
DOUT
15
DOUT
16
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
26
CR-0
CR-1
CR-7
Y-0
Y-1
Y-7
RES
RES
HS
VS
DE
RES
RES
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
Y1[7:0]
WRD 3
CR2[7:0]
WRD 4
WRD WC - 3
CB(N-1)[7:0]
WRD WC- 2
WRD WC -1
CR(N)[7:0]
WRD WC
Y(N)[7:0]
LINE
START
PACKET HEADER
LINE
STOP
PACKET FOOTER
CB1[7:0]
Y2[7:0]
Y(N-1)[7:0]
D0
CB-0
D1
CB-1
D2
CB-2
D3
CB-3
D4
CB-4
D5
CB-5
D6
CB-6
D7
CB-7
D0
CR-0
D1
CR-1
D2
CR-2
D3
CR-3
D4
CR-4
D5
CR-5
D6
CR-6
D7
CR-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
Y-0
D1
Y-1
D2
Y-2
D3
Y-3
D4
Y-4
D5
Y-5
D6
Y-6
D7
Y-7
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
16
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
2
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N
2N
Figure 23. YUV422 8-Bit Output
Maxim Integrated
│ 36
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
YUV422 10 BIT
(BWS = HIGH OR OPEN)
DOUT
0
DOUT
1
DOUT
2
DOUT
9
DOUT
10
DOUT
11
DOUT
12
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
22
DOUT
23
DOUT
26
CB-0
CB-1
CB-2
CB-9
Y-0
Y-1
Y-2
Y-7
HS
VS
DE
Y-8
Y-9
RES
RES
DOUT
0
DOUT
1
DOUT
2
DOUT
9
DOUT
10
DOUT
11
DOUT
12
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
22
DOUT
23
DOUT
26
CR-0
CR-1
CR-2
CR-9
Y-0
Y-1
Y-2
Y-7
HS
VS
DE
Y-8
Y-9
RES
RES
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
Y1[9:2]
WRD 3
WRD 4
Y2[9:2]
WRD 5
LSB
WRD WC - 4
CB(N-1)[9:2]
WRD WC - 3
Y(N-1)[9:2]
WRD WC- 2
CR(N)[9:2]
WRD WC -1
Y(N)[9:2]
WRD WC
LINE
START
PACKET HEADER
LINE
STOP
PACKET FOOTER
CB1[9:2]
CR2[9:2]
LSB
D0
CB1-0
D1
CB1-1
D2
Y1-0
D3
Y1-1
D4
D5
D6
Y2-0
D7
Y2-1
CR2-0 CR2-1
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
CR-2
Y-2
D1
CR-3
D2
CR-4
Y-3
CB-3
D3
CR-5
Y-5
CB-5
D4
CR-6
D5
CR-7
Y-6
CB-6
D6
CR-8
Y-8
CB-8
D7
CR-9
Y-4
CB-4
Y-7
CB-7
Y-9
CB-9
CB-2
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
WORD COUNT
BYTES
2.5
PIXEL
1
BITS
20
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
2.5N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2
Figure 24. YUV422 10-Bit Output
Maxim Integrated
│ 37
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
YUV422 12 BIT
(USER DEFINED,
BWS = HIGH OR OPEN)
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4
DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DOUT16 DOUT17
DOUT21
Y-6
DOUT26
Y-11
/HS
/VS
/DE
CB-0
CB-1
CB-2
CB-3
CB-4
CB-11
Y-0
Y-1
Y-2
Y-3
Y-4
Y-5
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4
DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DOUT16 DOUT17
DOUT21
Y-6
DOUT26
Y-11
/HS
/VS
/DE
CR-0
CR-1
CR-2
CR-3
CR-4
CR-11
Y-0
Y-1
Y-2
Y-3
Y-4
Y-5
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
WRD 3
LSB
WRD 4
WRD 5
WRD 6
LSB
WRD WC - 4
CB(N-1)[11:4]
WRD WC- 4
Y(N-1)[11:4]
WC - 3
LSB
WRD WC- 2
CR(N)[11:4]
WRD WC -1
Y(N)[11:4]
WC
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
CB1[11:4]
Y1[11:4]
CR2[11:4]
Y2[11:4]
LSB
D0
Y-0
D1
Y-1
D2
Y-2
D3
Y-3
D4
D5
D6
D7
CR-0 CR-1 CR-2 CR-3
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
Y-0
D1
Y-1
D2
Y-2
D3
Y-3
D4
D5
D6
D7
D0
CR-4
Y-4
D1
CR-5
Y-5
CB-5
D2
CR-6
D3
CR-7
Y-6
CB-6
D4
CR-8
Y-7
CB-7
D5
CR-9
Y-8
CB-8
D6
D7
CB-0 CB-1 CB-2 CB-3
CR-10 CR-11
Y-10 Y-11
CB-10 CB-11
Y-9
CB-9
CB-4
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
WORD COUNT
BYTES
YUV DATA
RGB DATA
RAW DATA
YUV 422 12-BIT = 0x30
RESERVED
PIXEL
1
N
BITS
24
3
3N
Figure 25. YUV422 12-Bit Output
Maxim Integrated
│ 38
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL to CSI-2
RAW 8 BIT (DOUBLE LOAD)
NO INPUT WHEN BWS =
LOW
GMSL
PARALLEL BIT
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
DOUT7 DOUT8 DOUT9
DOUT15 DOUT16 DOUT17
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
PA-0
PA-1
PA-7
PB-0
PB-1
PB-7
RES
RES
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
P1[7:0]
WRD 2
P2[7:0]
WRD 3
P3[7:0]
WRD 4
P4[7:0]
WRD WC - 3
P(N-3)[7:0]
WRD WC- 2
P(N-2)[7:0]
WRD WC -1
WRD WC
P(N)[7:0]
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
P(N-1)[7:0]
D0
PA-0
D1
PA-1
D2
PA-2
D3
PA-3
D4
PA-4
D5
PA-5
D6
PA-6
D7
PA-7
D0
PB-0
D1
PB-1
D2
PB-2
D3
PB-3
D4
PB-4
D5
PB-5
D6
PB-6
D7
PB-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
8
DATA TYPE
0x00 – 0x07
0x08 – 0x0F
0x10 – 0x17
0x18 – 0x1F
0x20 – 0x27
0x28 – 0x2F
0x30 – 0x37
0x38 – 0x3F
DESCRIPTION
1
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2
Figure 26. RAW 8-Bit (Double Load) Output
Maxim Integrated
│ 39
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
RAW 10 BIT
(DOUBLE LOAD,
BWS = HIGH OR OPEN)
DOUT
0
DOUT
1
DOUT
2
DOUT
9
DOUT
10
DOUT
11
DOUT
12
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
22
DOUT
23
DOUT
26
PA0
PA1
PA2
PA9
PB0
PB1
PB2
PB7
HS
VS
DE
PB8
PB9
RES
RES
DOUT
0
DOUT
1
DOUT
2
DOUT
9
DOUT
10
DOUT
11
DOUT
12
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
22
DOUT
23
DOUT
26
PA-0
PA-1
PA-2
PA-9
PB-0
PB-1
PB-2
PB-7
HS
VS
DE
PB-8
PB-9
RES
RES
CONTROLS FS & FE AND PACKET
START/END
WRD 1
P1[9:2]
WRD 2
P2[9:2]
WRD 3
P3[9:2]
WRD 4
P4[9:2]
WRD 5
LSB
WRD WC - 4
P(N-3)[9:2]
WRD WC - 3
P(N-2)[9:2]
WRD WC- 2
P(N-1)[9:2]
WRD WC -1
P(N)[9:2]
WRD WC
LSB
LINE
START
PACKET HEADER
LINE
STOP
PACKET FOOTER
D0
PA1-0
D1
PA1-1
D2
PB2-0
D3
PB2-1
D4
PA3-0
D5
PA3-1
D6
PB4-0
D7
PB4-1
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
PA-2
D1
PA-3
D2
PA-4
D3
PA-5
D4
PA-6
D5
PA-7
D6
PA-8
D7
PA-9
D0
PB-2
D1
PB-3
D2
PB-4
D3
PB-5
D4
PB-6
D5
PB-7
D6
PB-8
D7
PB-9
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
10
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
1.25
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
1.25N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4
Figure 27. RAW 10-Bit (Double Load) Output
Maxim Integrated
│ 40
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
RAW 12 BIT (DOUBLE LOAD BWS = HIGH OR OPEN)
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2 DOUT3 DOUT4
DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DOUT16 DOUT17
DOUT21
PB-6
DOUT26
PB-11
/HS
/VS
/DE
PA-0
PA-1
PA-2
PA-3
PA-4
PA-11
PB-0
PB-1
PB-2
PB-3
PB-4
PB-5
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
P1[11:4]
WRD 2
WRD 3
LSB
WRD 4
WRD 5
P4[11:4]
WRD 6
LSB
WRD WC - 4
P(N-3)[11:4]
WRD WC- 4
P(N-2)[11:4]
WC - 3
LSB
WRD WC- 2
P(N-1)[11:4]
WRD WC -1
P(N)[11:4]
WC
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
P2[11:4]
P3[11:4]
LSB
D0
D1
D2
D3
D4
D5
D6
D7
PA-0
PA-1
PA-2
PA-3
PB-0
PB-1
PB-2
PB-3
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
PA-4
D1
PA-5
D2
PA-6
D3
PA-7
D4
PA-8
D5
PA-9
D6
PA-10
D7
PA-11
D0
PB-4
D1
PB-5
D2
PB-6
D3
PB-7
D4
PB-8
D5
PB-9
D6
PB-10
D7
PB-11
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
1.5
PIXEL
1
BITS
12
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
1.5N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2
Figure 28. RAW 12-Bit (Double Load) Output
Maxim Integrated
│ 41
www.maximintegrated.com
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
NO INPUT WHEN BWS
RAW 8 BIT
= LOW
(SINGLE LOAD)
GMSL
PARALLEL BIT
DOUT
0
DOUT
1
DOUT
7
DOUT
8
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
26
P-0
P-1
P-7
RES
RES
HS
VS
DE
RES
RES
CONTROLS FS & FE AND
PACKET START/END
WRD 1
P1[7:0]
WRD 2
P2[7:0]
WRD 3
P3[7:0]
WRD 4
WRD WC - 5
P(N-5)[7:0]
WRD WC - 4
P(N-4)[7:0]
WRD WC - 3
P(N-3)[7:0]
WRD WC- 2
WRD WC -1
WRD WC
P(N)[7:0]
LINE
START
PACKET HEADER
LINE
STOP
PACKET FOOTER
P4[7:0]
P(N-2)[7:0]
P(N-1)[7:0]
D0
P-0
D1
P-1
D2
P-2
D3
P-3
D4
P-4
D5
P-5
D6
P-6
D7
P-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
PIXEL
1
BYTES
1
BITS
8
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
N
N
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
Figure 29. RAW 8-Bit Output
Maxim Integrated
│ 42
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
NO INPUT WHEN BWS =
LOW
GMSL TO CSI-2
RAW 10 BIT
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-0
P-1
P-2
P-9
RES
RES
DOUT17
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-0
P-1
P-2
P-9
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-0
P-1
P-2
P-9
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1 DOUT2
DOUT9 DOUT10
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-0
P-1
P-2
P-9
RES
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WRD 1
P1[9:2]
WRD 2
P2[9:2]
WRD 3
P3[9:2]
WRD 4
WRD 5
LSB
WRD WC - 4
P(N-3)[9:2]
WRD WC - 3
P(N-2)[9:2]
WRD WC- 2
P(N-1)[9:2]
WRD WC -1
WRD WC
LSB
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
P4[9:2]
P(N)[9:2]
D0
P1-0
D1
P1-1
D2
P2-0
D3
P2-1
D4
P3-0
D5
P3-1
D6
P4-0
D7
P4-1
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
P-2
D1
P-3
D2
P-4
D3
P-5
D4
P-6
D5
P-7
D6
P-8
D7
P-9
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
1.25
1.25N
PIXEL
1
N*
BITS
10
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
Figure 30. RAW 10-Bit Output
Maxim Integrated
│ 43
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL to CSI-2
NO INPUT WHEN BWS
RAW 12 BIT
= LOW
DOUT
0
DOUT
1
DOUT
2
DOUT
3
DOUT
4
DOUT
11
DOUT
12
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
26
P-0
P-1
P-2
P-3
P-4
P-11
RES
RES
HS
VS
DE
RES
RES
DOUT
0
DOUT
1
DOUT
2
DOUT
3
DOUT
4
DOUT
11
DOUT
12
DOUT
17
DOUT
18/HS
DOUT
19/VS
DOUT
20/DE
DOUT
21
DOUT
26
P-0
P-1
P-2
P-3
P-4
P-11
RES
RES
HS
VS
DE
RES
RES
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
WRD 3
LSB
WRD 4
P3[11:4]
WRD 5
WRD 6
LSB
WRD WC - 4
P(N-3)[11:4]
WRD WC- 4
P(N-2)[11:4]
WC - 3
LSB
WRD WC- 2
P(N-1)[11:4]
WRD WC -1
P(N)[11:4]
WC
LINE
START
PACKET HEADER
LINE
STOP
PACKET FOOTER
P1[11:4]
P2[11:4]
P4[11:4]
LSB
D0
D1
D2
D3
D4
D5
D6
D7
P1-0 P1-1 P1-2 P1-3 P2-0 P2-1 P2-2 P2-3
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
D0
P-4
D1
P-5
D2
P-6
D3
P-7
D4
P-8
D5
P-9
D6
D7
D0
P-4
D1
P-5
D2
P-6
D3
P-7
D4
P-8
D5
P-9
D6
D7
P-10 P-11
P-10 P-11
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
1.5
PIXEL
1
BITS
12
DATA TYPE
0x00 – 0x07
0x08 – 0x0F
0x10 – 0x17
0x18 – 0x1F
0x20 – 0x27
0x28 – 0x2F
0x30 – 0x37
0x38 – 0x3F
DESCRIPTION
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
1.5N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 2
Figure 31. RAW 12-Bit Output
Maxim Integrated
│ 44
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
NO INPUT WHEN BWS =
LOW
GMSL to CSI-2
RAW 14 BIT
DOUT18 DOUT19 DOUT20
DOUT0
P-0
DOUT5 DOUT6
DOUT13 DOUT14
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-5
P-6
P-13
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0
P-0
DOUT5 DOUT6
DOUT13 DOUT14
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-5
P-6
P-13
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0
P-0
DOUT5 DOUT6
DOUT13 DOUT14
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-5
P-6
P-13
RES
HS
VS
DE
DOUT18 DOUT19 DOUT20
DOUT0
P-0
DOUT5 DOUT6
DOUT13 DOUT14
DOUT17
RES
DOUT21
RES
DOUT26
RES
/HS
/VS
/DE
P-5
P-6
P-13
RES
HS
VS
DE
CONTROLS FS & FE AND PACKET
START/END
WORD (WC – 6) TO (WC – 3)
WORD (WC – 2) TO WC
WRD 1
WRD 2
WRD 3
WRD 4
WRD 5
P1[5:0]
WRD 6
P2[5:0] P3[5:0]
WRD 7
P4[5:0]
LINE
START
PACKET HEADER
LINE STOP
PACKET FOOTER
P1[13:6]
P2[13:6]
P3[13:6]
P4[13:6]
P(N-3) TO P(N) MSB
P(N-3) TO P(N) LSB
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
P-0
P-1
P-2
P-3
P-4
P-5
D0
P-6
D1
P-7
D7
P-13
LSB
MSB
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
8 BITS
8 BITS
CRC LS BYTE
CRC MS BYTE
1 OF 4
CHANNEL
SELECT
DATA TYPE
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
14
DATA TYPE
0x00 – 0x07
0x08 – 0x0F
0x10 – 0x17
0x18 – 0x1F
0x20 – 0x27
0x28 – 0x2F
0x30 – 0x37
0x38 – 0x3F
DESCRIPTION
1.75
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED BYTE BASED DATA
RESERVED
N*
1.75N
*PIXEL COUNT NEEDS TO BE A MULTIPLE OF 4
Figure 32. RAW 14-Bit Output
Maxim Integrated
│ 45
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL TO CSI-2
USER-DEFINED 24 BIT
(BWS = HIGH OR OPEN)
GMSL
DOUT18 DOUT19 DOUT20
DOUT0 DOUT1
PARALLEL BIT
DOUT5 DOUT6 DOUT7
DOUT11 DOUT12 DOUT13
DOUT17
UC-5
DOUT21 DOUT22 DOUT23 DOUT24 DOUT25 DOUT26
/HS
/VS
/DE
UA-0
UA-1
UA-5
UB-0
UB-1
UB-5
UC-0
UC-1
HS
VS
DE
UA-6
UA-7
UB-6
UB-7
UC-6
UC-7
CONTROLS FS & FE AND PACKET
START/END
WRD 1
WRD 2
UB1[7:0]
WRD 3
WRD 4
WRD 5
WRD 6
WRD WC-5
UA(N-1)[7:0]
WRD WC-4
UB(N-1)[7:0]
WRD WC-3
UC(N-1)[7:0]
WRD WC- 2
UA(N)[7:0]
WRD WC-1
WRD WC
LINE
START
PACKET HEADER
LINE STOP
UA1[7:0]
UC1[7:0]
UA2[7:0]
UB2[7:0]
UC2[7:0]
UB(N)[7:0]
UC(N)[7:0]
PACKET FOOTER
D0
UB-0
D1
UB-1
D2
UB-2
D3
UB-3
D4
UB-4
D5
UB-5
D6
UB-6
D7
UB-7
D0
UA-0
D1
UA-1
D2
UA-2
D3
UA-3
D4
UA-4
D5
UA-5
D6
UA-6
D7
UA-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
CRC LS BYTE
8 BITS
CRC MS BYTE
D0
UC-0
D1
UC-1
D2
UC-2
D3
UC-3
D4
UC-4
D5
UC-5
D6
UC-6
D7
UC-7
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
VC0
D7
VC1
D0
DT0
D1
DT1
D2
DT2
D3
DT3
D4
DT4
D5
DT5
D6
0
D7
0
DATA TYPE
SELECT
1 OF 4 CHANNEL
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
24
DATA TYPE
0X00 – 0X07
0X08 – 0X0F
0X10 – 0X17
0X18 – 0X1F
0X20 – 0X27
0X28 – 0X2F
0X30 – 0X37
0X38 – 0X3F
DESCRIPTION
3
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0X12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
RAW DATA
USER DEFINED 24-BIT = 0x30
RESERVED
N
3N
Figure 33. User-Defined 24-Bit Output
Maxim Integrated
│ 46
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
GMSL to CSI-2
USER DEFINED 8 BIT
NO INPUT WHEN
BWS = LOW
GMSL
PARALLEL BIT
DOUT DOUT
DOUT DOUT
DOUT DOUT DOUT DOUT DOUT
DOUT
26
0
1
7
8
17
18/HS 19/VS 20/DE
21
U-0
U-1
U-7
RES
RES
HS VS DE
RES
RES
CONTROLS FS & FE AND
PACKET START/END
LINE
START
PACKET HEADER
LINE
STOP
PACKET FOOTER
WRD 1 WRD 2 WRD 3 WRD 4
U1[7:0] U2[7:0] U3[7:0] U4[7:0]
WRD WC - 5 WRD WC - 4 WRD WC - 3 WRD WC- 2 WRD WC -1
WRD WC
U(N)[7:0]
U(N-5)[7:0]
U(N-4)[7:0]
U(N-3)[7:0]
U(N-2)[7:0]
U(N-1)[7:0]
D0
D1
D2
D3
D4
D5
D6
D7
U-0 U-1 U-2 U-3 U-4 U-5 U-6 U-7
8 BITS
DATA ID
16 BITS
WORD COUNT
8 BITS
ECC
8 BITS
8 BITS
CRC LS BYTE CRC MS BYTE
D0
D1
D2
D3
D4
D5
D6
0
D7
0
DT0 DT1 DT2 DT3 DT4 DT5
D0
D1
D2
D3
D4
D5
D6
D7
DT0 DT1 DT2 DT3 DT4 DT5 VC0 VC1
1 OF 4
DATA TYPE
CHANNEL
SELECT
WORD COUNT
BYTES
PIXEL
1
BITS
8
SELECT
DATA TYPE
DESCRIPTION
1
0x00 – 0x07
0x08 – 0x0F
0x10 – 0x17
0x18 – 0x1F
0x20 – 0x27
0x28 – 0x2F
0x30 – 0x37
0x38 – 0x3F
SYNCHRONIZATION SHORT PACKET DATA TYPES
GENERIC SHORT PACKET DATA TYPES
GENERIC LONG PACKET DATA TYPES (TYPE 0x12 USED FOR EMBEDDED AUDIO
YUV DATA
RGB DATA
N
N
RAW DATA
USER DEFINED BYTE BASED DATA (USER DEFINED 8-BIT = 0x31)
RESERVED
Figure 34. User-Defined 24-Bit Output
Maxim Integrated
│ 47
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 2 Video Output Map (RGB and YUV)
2
YUV422
RGB
GMSL
INPUT
BITS
8-BIT
MUXED
10-BIT
MUXED
3*
3
3**
12-BIT
666
565
888
8-BIT
10-BIT
1
DIN0
DIN1
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
R0
R1
R2
R3
R4
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
—
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Y/Cb/Cr0
Y/Cb/Cr1
Y/Cb/Cr2
Y/Cb/Cr3
Y/Cb/Cr4
Y/Cb/Cr5
Y/Cb/Cr6
Y/Cb/Cr7
—
Y/Cb/Cr0
Y/Cb/Cr1
Y/Cb/Cr2
Y/Cb/Cr3
Y/Cb/Cr4
Y/Cb/Cr5
Y/Cb/Cr6
Y/Cb/Cr7
Y/Cb/Cr8
Y/Cb/Cr9
—
Cb/Cr0
Cb/Cr1
Cb/Cr2
Cb/Cr3
Cb/Cr4
Cb/Cr5
Cb/Cr6
Cb/Cr7
Y0
Cb/Cr0
Cb/Cr1
Cb/Cr2
Cb/Cr3
Cb/Cr4
Cb/Cr5
Cb/Cr6
Cb/Cr7
Cb/Cr8
Cb/Cr9
Y0
Cb/Cr0
Cb/Cr1
Cb/Cr2
Cb/Cr3
Cb/Cr4
Cb/Cr5
Cb/Cr6
Cb/Cr7
Cb/Cr8
Cb/Cr9
Cb/Cr10
Cb/Cr11
Y0
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
—
Y1
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
—
Y2
—
—
Y3
Y1
—
—
Y4
Y2
—
—
Y5
Y3
Y1
—
—
Y6
Y4
Y2
—
—
Y7
Y5
Y3
—
—
—
Y6
Y4
B5
HS
VS
—
HS
VS
—
—
—
Y7
Y5
DIN18
DIN19
DIN20
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
DE
DE
—
—
—
—
—
—
—
—
—
—
—
—
DIN21
DIN22
DIN23
DIN24
DIN25
DIN26
R6
R7
G6
G7
B6
B7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y8
Y9
—
—
—
—
Y6
Y7
Y8
Y9
Y10
Y11
1. Refer to the GMSL serializer data sheet for details.
2. YUV defaults to muxed input mode (Cb, Y0, Cr, Y1). Set INPUTBW = 1 to use normal input mode (CBY0, CrY1).
3. Data type available when BWS = high or open, only.
*VESA/oLDI bits are mapped to MIPI according to OLDI bit (D4 or register 0x60). Set oLDI bit low when using VESA input or high
when using an oLDI input. oLDI defines bits [5:0] as MSB and bits [6:7] as LSB.
**12-bit YUV422 sent using CSI-2 user-defined data type (0x30). The output byte sequence is CB[11:4], Y0[11:4], [CB[3:0], Y0[3:0]],
CR[11:4], Y1[11:4], [CR[3:0], and Y1[3:0]].
pixels in the previous DE high period. If both numbers are
within ±4 pixels of each other, the deserializer accepts
this count as valid count and uses the number to pack-
etize the video data. An AUTOPPL error is issued only
when the current pixel count does not match the previous
pixel count. An invalid count (±5 or more pixels) stops the
packet transmission and issues an AUTOPPL error. This
allows the device to tolerate some noise while alerting the
user of an error.
Auto Pixel-Per-Line Feature
For proper operation, the device requires the information of
number of pixels in DE high period. Program the pixel count
into registers 0x61 and 0x62. Alternatively, the device can
automatically count the number of pixels in DE high period.
Setting the AUTOPPL bit high enables this function. In this
mode, the device counts the number of pixels in every DE
high period and compares the result with the number of
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Clock Operation
Data-Rate Selection and CSI-2 Clock
Limitations
The GMSL deserializer recovers the pixel clock (PCLK)
from the serial input. This pixel clock is used to time
various functions of the device such as the control sig-
nals and MCLK. The pixel, along with the CSI data type,
determines the CSI HS clock (CLK+/-) When the clocks
are stable, the LOCK pin goes high and the clock trans-
mitter starts the SOT, HS prepare and HS zero sequences
and transmits the HS clock in HS differential mode. If the
device loses of lock, the clock lane is disabled, and the
clock transmitter pulls the line to stop state (LP-11).
Three factors affect the overal useable clock range of the
GMSL deserializers: The valid clock range of the GMSL
serial input, the MIPI CSI-2 output, and the data bit width.
Table 5 lists the valid PCLK range at various CSI-2 output
modes. Table 6 shows the valid CSI-2 output-channel bit
rate.
Table 3. Video Output Map (RAW and User Defined)
GMSL
INPUT
BITS
2
2
RAW (DOUBLE LOAD )
RAW (SINGLE LOAD )
USER DEFINED
3
3
3
1
8-BIT
10-BIT
12-BIT
8-BIT
10-BIT
12-BIT
14-BIT
24-BIT
8-BIT
DIN0
DIN1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
—
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PB0
PB1
PB2
PB3
PB4
PB5
P0
P1
P2
P3
P4
P5
P6
P7
—
—
—
—
—
—
—
—
—
—
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
—
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
—
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
—
UA0
UA1
UA2
UA3
UA4
UA5
UB0
UB1
UB2
UB3
UB4
UB5
UC0
UC1
UC2
UC3
UC4
UC5
U0
U1
U2
U3
U4
U5
U6
U7
—
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
DIN9
—
DIN10
DIN11
DIN12
DIN13
DIN14
DIN15
DIN16
DIN17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DIN18
DIN19
DIN20
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
HS
VS
DE
DIN21
DIN22
DIN23
DIN24
DIN25
DIN26
—
—
—
—-
—
—
PB8
PB9
—
PB6
PB7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UA6
UA7
UB6
UB7
UC6
UC7
—
—
—
—
—
—
PB8
—
PB9
—
PB10
PB11
—
1. Refer to the GMSL serializer data sheet for details.
2. RAW datatype defaults to single load. Set INPUTBW = 1 to use double input mode (output sequence PA0, PB0, PA1, PB1).
3. Data type available when BWS = high or open, only.
Maxim Integrated
│ 49
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
HS, VS, and DE low pulse widths at least two pixel clock
cycles. By default, CNTL[3:0] are sampled continuously
when DE is low. CNTL[3:0] are sampled only on HS/VS
transitions when DE is high. If DE triggering of encoded
packets is not desired, set the serializer’s DISDETRIG
= 0 and the CNTLTRIG bits to their desired value (reg-
ister 0x15) to change the CNTL triggering behavior. Set
DETREN = 0 on the deserializer when DE is not periodic.
FRAME
WS
SCK
SD
0
1
2
N
Audio Channel
16 TO 256 BITS
The audio channel supports 8kHz to 192kHz audio
sampling rates and audio word lengths from 8 bits to
2
32 bits (2-channel I S), or 64 to 256 bits (TDM64 to
TDM256). The audio bit clock (SCK) does not have to be
synchronized with pixel clock. The serializer automatically
encodes audio data into a single-bit stream synchronous
with pixel clock. The deserializer decodes the audio
Figure 35. Audio Channel Input Format
GMSL Clock Range
The deserializer uses the DRS pin/bit and the BWS input
to set the GMSL pixel clock frequency range (Table 5).
Set DRS = 1 for low data rate pixel clock frequency range
of 6.25MHz to 16.66MHz. Set DRS = 0 for high data rate
pixel clock frequency range of 12.5MHz to 104MHz.
stream and stores audio words in a FIFO. Audio rate
detection uses an internal oscillator to continuously
2
determine the audio data rate and output the audio in I S
format. The audio channel is enabled by default. When
the audio channel is disabled, the SD is treated as an
auxiliary control signal.
CSI-2 Clock Range
the CSI-2 ports operate from 80Mbps to 1000Mbps per
channel. The CSI-2 output bit rate can be calculated from
the PCLK rate by the following equation:
Since the encoded audio data sent through the serial
link is synchronized with pixel clock (through ACB), low
pixel clock frequencies limit the maximum audio sampling
rate. Table 5 lists the maximum audio sampling rate for
various pixel clock frequencies. Spread spectrum from
CSI RATE = PCLK x WIDTH/LANES
where:
2
the serializer do not affect the I S/TDM data rate or WS
clock frequency.
PCLK = Input PCLK rate
LANES = Number of CSI-2 lanes used
Audio Channel Input
WIDTH = Bit width of the input data (see Table 5 or
Table 6)
The audio channel input works with 8-channel TDM and
2
stereo I S, as well as nonstandard formats. The input
format is shown in Figure 35.
High-Bandwidth Mode
The period of the WS can be 8 to 256 SCK periods. The
WS frame starts with the falling edge and can be low for
1 to 255 SCK periods. SD is one SCK period, sampled
on the rising edge. MSB/LSB order, zero padding, or any
other significance assigned to the serial data does not
affect operation of the audio channel. The polarity for WS
and SCK edges is programmable.
The deserializer uses a 27-bit high-bandwidth mode to
support 24-bit RGB at 104MHz pixel clock. Set BWS =
open in both the serializer and deserializer to use high-
bandwidth mode. In high-bandwidth mode, the deserial-
izer decodes HS, VS, DE, and CNTL[3:0] from special
packets. Packets are sent by replacing a pixel before the
rising edge and after the falling edge of the HS, VS, and
DE signals. However, for CNTL[3:0], which is not always
continuously sampled, packets always replace a pixel
before the transition of the sampled CNTL[3:0]. Keep
Figure 36, Figure 37, Figure 38, and Figure 39 are
examples of acceptable input formats.
Maxim Integrated
│ 50
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 4. Control Output Map
MODE
CONTROL OUTPUTS
24-BIT MODE
(BWS = LOW)
HIGH-BANDWIDTH MODE
(BWS = MID)
32-BIT MODE
(BWS = HIGH)
CNTL0
CNTL1
CNTL2
CNTL3
Not used
Not used
Not used
Not used
Used*
Used*
Used*
Used*
Not used
Used**
Used**
Not used
Note: See the High-Bandwidth Mode section for details on timing requirements.
*Outputs used only when the respective color lookup tables are enabled.
**Not encrypted when HDCP is enabled (MAX9290 only).
Table 5. GMSL Data-Rate Selection Table
DRS BIT SETTING
BWS PIN SETTING
Low (24-bit mode)
Mid (high-bandwidth mode)
High (32-bit mode)
Low
PIXEL CLOCK RANGE (MHz)
16.66 to 104
0 (high data rate)
36.66 to 104
12.5 to 78
8.33 to 16.66
1 (low data rate)
Mid
18.33 to 36.66
6.25 to 12.5
High
Table 6. Input Pixel Clock Range (MHz)
DRS LOW
DRS HIGH
GMSL BIT
WIDTH
CSI-2 OUTPUT
MODES
NUMBER OF
CSI-2 LANES
BWS
LOW
BWS
OPEN
BWS
HIGH
BWS
LOW
BWS
OPEN
BWS
HIGH
16.67 to
104
36.67 to
104
12.5 to
78
10 to
16.67
18.33 to
36.67
10 to
12.5
1
2
3
4
36.67 to
104
Do not
use
20 to
36.67
Do not
use
20 to 104
30 to 104
40 to 104
20 to 78
30 to 78
40 to 78
RAW8
8
(Single Load)
36.67 to
104
Do not
use
30 to
36.67
Do not
use
YUV422 8b Muxed
Do not
use
Do not
use
Do not
use
40 to 104
Maxim Integrated
│ 51
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 6. Input Pixel Clock Range (MHz) (continued)
DRS LOW
DRS HIGH
GMSL BIT
WIDTH
CSI-2 OUTPUT
MODES
NUMBER OF
CSI-2 LANES
BWS
LOW
BWS
OPEN
BWS
HIGH
BWS
LOW
BWS
OPEN
BWS
HIGH
16.67 to
100
36.67 to
100
12.5 to
78
8.333 to
16.67
18.33 to
36.67
1
2
3
4
1
2
3
4
1
2
3
8 to 12.5
16.67 to
104
36.67 to
104
16 to
16.67
18.33 to
36.67
Do not
use
16 to 78
24 to 78
32 to 78
RAW10
10
(Single Load)
36.67 to
104
Do not
use
24 to
36.67
Do not
use
YUV422 10b Muxed
24 to 104
32 to 104
36.67 to
104
Do not
use
32 to
36.67
Do not
use
16.67 to
83.33
36.67 to
83.3
12.5 to
78
8.333 to
16.67
18.33 to
36.67
6.667 to
12.5
16.67 to
104
36.67 to
104
13.33 to
78
13.33 to
16.67
18.33 to
36.67
Do Not
Use
RAW12
(Single Load)
12
36.67 to
104
Do not
use
20 to
36.67
Do not
use
20 to 104
20 to 78
26.67 to
104
36.67 to
104
26.67 to
78
Do not
use
26.67 to
36.67
Do not
use
16.67 to
71.43
36.67 to
71.43
12.5 to
71.43
8.333 to
16.67
18.33 to
36.67
6.25 to
12.5
16.67 to
104
36.67 to
104
12.5 to
78
11.43 to
16.67
18.33 to
36.67
11.43 to
12.5
RAW14
(Single Load)
14
17.14 to
104
36.67 to
104
17.14 to
78
Do not
use
18.33 to
36.67
Do not
use
22.86 to
104
36.67 to
104
22.86 to
78
Do not
use
22.86 to
36.67
Do not
use
4
1
2
3
4
16.67 to
62.5
36.67 to
62.5
12.5 to
62.5
8.333 to
16.67
18.33 to
36.67
6.25 to
12.5
16.67 to
104
36.67 to
104
12.5 to
78
10 to
16.67
18.33 to
36.67
10 to
12.5
RAW8
(Double Load)
YUV442 8b
RGB565
16
16.67 to
104
36.67 to
104
15 to
16.67
18.33 to
36.67
Do Not
Use
15 to 78
20 to 78
36.67 to
104
Do not
use
20 to
36.67
Do not
use
20 to 104
Maxim Integrated
│ 52
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 6. Input Pixel Clock Range (MHz) (continued)
DRS LOW
DRS HIGH
GMSL BIT
WIDTH
CSI-2 OUTPUT
MODES
NUMBER OF
CSI-2 LANES
BWS
LOW
BWS
OPEN
BWS
HIGH
BWS
LOW
BWS
OPEN
BWS
HIGH
16.67 to
55.56
36.67 to
55.56
12.5 to
55.56
8.333 to
16.67
18.33 to
36.67
6.25 to
12.5
1
2
3
4
1
2
3
4
1
2
3
4
16.67 to
104
36.67 to
104
12.5 to
78
8.889 to
16.67
18.33 to
36.67
8.889 to
12.5
18
20
24
RGB666
16.67 to
104
36.67 to
104
13.33 to
78
13.33 to
16.67
18.33 to
36.67
Do not
use
16.67 to
104
36.67 to
104
17.78 to
78
Do not
use
18.33 to
36.67
Do not
use
Do not
use
36.67 to
12.5 to
50
Do not
use
18.33 to
36.67
6.25 to
12.5
50
Do not
use
36.67 to
100
12.5 to
78
Do not
use
18.33 to
36.67
RAW10
(Double Load)
YUV442 10b
8 to 12.5
Do not
use
36.67 to
104
12.5 to
78
Do not
use
18.33 to
36.67
12 to
12.5
Do not
use
36.67 to
104
Do Not
Use
18.33 to
36.67
Do Not
Use
16 to 78
Do not
use
36.67 to
41.67
12.5 to
41.67
Do not
use
18.33 to
36.67
6.25 to
12.5
RAW12
(Double Load)
YUB442 12b
RGB888
Do not
use
36.67 to
83.33
12.5 to
78
Do not
use
18.33 to
36.67
6.667 to
12.5
Do not
use
36.67 to
104
12.5 to
78
Do not
use
18.33 to
36.67
10 to
12.5
User-defined 8b
User-defined 24b
Do not
use
36.67 to
104
13,33 to
78
Do not
use
18.33 to
36.67
Do not
use
Maxim Integrated
│ 53
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 7. Output CSI-2 Data Rate Range (Mbps)
DRS LOW
DRS HIGH
GMSL
BIT
WIDTH
CSI-2 OUTPUT
MODES
NUMBER OF
CSI-2 LANES
BWS
LOW
BWS
OPEN
BWS
HIGH
BWS
LOW
BWS
OPEN
BWS
HIGH
133.3 to
832
293.3 to
832
100 to
624
80 to
133.3
146.7 to
293.3
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
80 to 100
146.7 to
832
Do Not
Use
80 to
146.7
Do Not
Use
80 to 416
80 to 312
80 to 208
80 to 156
RAW8
8
(Single Load)
80 to
277.3
97.78 to
277.3
Do Not
Use
80 to
97.76
Do Not
Use
YUV422 8b Muxed
Do Not
Use
Do Not
Use
Do Not
Use
80 to 208
80 to 208
166.7 to
1000
366.7 to
1000
125 to
780
83.33 to
166.7
183.3 to
366.7
80 to 125
83.33 to
520
183.3 to
520
80 to
83.33
91.67 to
183.3
Do Not
Use
80 to 390
80 to 260
80 to 195
RAW10
10
12
14
(Single Load)
YUV422 10b Muxed
80 to
346.7
122.22 to
346.7
Do Not
Use
80 to
122.2
Do Not
Use
91.67 to
260
Do Not
Use
80 to
91.67
Do Not
Use
80 to 260
200 to
1000
440 to
1000
150 to
936
100 to 200 220 to 440 80 to 150
Do Not
Use
100 to 624 220 to 624 80 to 468
80 to 100
110 to 220
80 to 147
80 to 110
RAW12
(Single Load)
Do Not
Use
Do Not
Use
80 to 416
80 to 312
147 to 416 80 to 312
147 to 312 80 to 234
Do Not
Use
Do Not
Use
233.3 to
1000
513.3 to
1000
175 to
1000
116.7 to
233.3
256.7 to
513.3
87.5 to
175
116.7 to
728
256.7 to
1728
87.5 to
546
80 to
116.7
128.3 to
256.7
80 to
87.5
RAW14
(Single Load)
80 to
485.3
171.1 to
485.3
Do Not
Use
80 to
171.1
Do Not
Use
80 to 364
80 to 273
Do Not
Use
80 to
128.3
Do Not
Use
80 to 364
80 to 364
Maxim Integrated
│ 54
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 7. Output CSI-2 Data Rate Range (Mbps) (continued)
DRS LOW
DRS HIGH
GMSL
BIT
WIDTH
CSI-2 OUTPUT
MODES
NUMBER OF
CSI-2 LANES
BWS
LOW
BWS
OPEN
BWS
HIGH
BWS
LOW
BWS
OPEN
BWS
HIGH
256.7 to
1000
586.7 to
1000
200 to
1000
133.3 to
266.7
293.3 to
586.7
100 to
200
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
133.3 to
832
293.3 to
832
100 to
624
80 to
133.3
146.7 to
293.3
RAW8
80 to 100
(Double Load)
YUV442 8b
RGB565
16
18
20
24
88.89 to
554.7
195.6 to
554.7
80 to
88.89
97.78 to
195.6
Do Not
Use
80 to 416
80 to 312
146.7 to
832
Do Not
Use
80 to
146.7
Do Not
Use
80 to 416
300 to
1000
660 to
1000
225 to
1000
112.5 to
225
150 to 300 330 to 660
112.5 to
702
80 to
112.5
150 to 936 330 to 936
80 to 150
80 to 100
165 to 330
110 to 220
RGB666
Do Not
Use
100 to 624 110 to 624 80 to 468
Do Not
Use
82.5 to
165
Do Not
Use
80 to 468
165 to 468 80 to 351
Do Not
Use
733.3 to
1000
250 to
1000
Do Not
Use
366.6 to
733.3
120 to
250
Do Not
Use
366.7 to
1000
125 to
780
Do Not
Use
183.3 to
366.7
RAW10
(Double load)
YUV442 10b
80 to 125
Do Not
Use
244.4 to
93.3
83.33 to
520
Do Not
Use
122.2 to
244.4
80 to
83.33
Do Not
Use
183.3 to
520
Do Not
Use
91.67 to
183.3
Do Not
Use
80 to 390
Do Not
Use
880 to
1000
300 to
1000
Do Not
Use
150 to
300
440 to 880
RAW12
(Double load)
YUB442 12b
RGB888
Do Not
Use
440 to
1000
150 to
936
Do Not
Use
220 to 440 80 to 150
Do Not
Use
293.3 to
832
100 to
624
Do Not
Use
146.7 to
80 to 100
293.3
User Defined 8b
User Defined 24b
Do Not
Use
Do Not
Use
Do Not
110 to 220
220 to 624 80 to 468
Use
Maxim Integrated
│ 55
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MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 8. Maximum Audio WS Frequency (kHz) for Various Pixel Clock Frequencies
PIXEL CLOCK FREQUENCY
(DRS = 0*)
(MHz)
BITS PER
CHANNEL
12.5
15.0
16.6
20.0
25.0
30.0
35.0
40.0
45.0
50.0
100
8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
+
+
185.5
174.6
152.2
123.7
+
+
+
2
4
6
8
+
182.7
148.4
+
164.3
8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
123.7
112.0
104.2
88.6
148.4
134.4
125.0
106.3
83.8
164.3
148.8
138.3
117.7
92.8
+
+
179.2
166.7
141.8
111.8
+
+
+
+
177.2
139.7
+
69.9
167.6
8
152.2
88.6
80.2
73.3
62.5
48.3
182.7
106.3
93.3
88.0
75.0
57.9
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
117.7
106.6
97.3
83.0
64.1
141.8
128.4
117.3
100
177.2
160.5
146.6
125
+
+
+
+
+
+
+
+
175.9
150
115.9
+
175
135.2
+
+
77.2
96.5
154.5
173.8
8
123.7
69.9
62.5
57.1
48.3
37.1
148.4
83.8
75.0
68.5
57.9
44.5
164.3
92.8
83.0
75.8
64.1
49.3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
16
18
20
24
32
111.8
100.0
91.3
77.2
59.4
139.7
125.0
114.2
96.5
167.6
150.0
137.0
115.9
89.1
+
+
175.0
159.9
135.2
103.9
+
+
+
+
182.7
154.5
118.8
+
173.8
133.6
+
74.2
148.4
COLOR CODING
< 48kHz
48kHz to 96kHz
96kHz to 192kHz
> 192kHz
+Max WS rate is greater than 192kHz.
*DRS = 0 pixel clock frequency is equal to 2x the DRS = 1 pixel clock frequency.
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256 SCK
WS
SCK
SD
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
32 SCK
MSB 24-BIT DATA
LSB 8 BITS ZERO
Figure 36. 8-Channel TDM (24-Bit Samples, Padded with Zeros)
144 SCK
WS
SCK
SD
CH1
CH2
CH3
CH4
CH5
CH6
24 SCK
24-BIT DATA
Figure 37. 6-Channel TDM (24-Bit Samples, No Padding)
144 SCK
WS
SCK
SD
CH1
CH2
CH3
CH4
CH5
CH6
24 SCK
24-BIT DATA
2
Figure 38. Stereo I S (24-Bit Samples, Padded with Zeros)
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32 SCK
WS
SCK
SD
LEFT CHANNEL
16 SCK
RIGHT CHANNEL
16-BIT DATA
2
Figure 39. Stereo I S (16-Bit Samples, No Padding)
in the serializer, however, introduces spread spectrum
Audio Channel Output
into MCLK. Spread-spectrum settings of either device
do not affect MCLK frequencies derived from the internal
oscillator. The internal oscillator frequency ranges
from 100MHz to 150MHz over all process corners and
operating conditions. Alternatively, set MCLKWS = 1
(0x15 D1) to output WS from MCLK.
WS, SCK, and SD are output with the same timing
relationship they had at the audio input, except that WS
is always 50% duty cycle (regardless of the duty cycle of
WS at the input).
The output format is shown in Figure 40.
WS and SCK can be driven by the audio source (clock
master) or the audio sink (clock slave). Buffer underflow and
overflow flags are available to the sink as clock slave through
Audio Output Timing Sources
The deserializer has multiple options for audio data output
timing. By default, the deserializer provides the output
timing based on the incoming data rate (through a FIFO)
and an internal oscillator.
2
I C for clock frequency adjustment. Data are sampled on the
rising edge. WS and SCK polarity is programmable.
Additional MCLK Output for Audio Applications
To use a system-sourced clock, set the AUDIOMODE bit
to 1 (D5 of register 0x02) to set WS and SCK as inputs
on the deserializer side. The deserializer uses a FIFO
to smooth out the differences in input and output audio
timing. Registers 0x78 and 0x79 store the FIFO overflow/
underflow information for use with external WS/SCK
timing. The FIFO drops data packets during FIFO over-
flow. By default, the FIFO repeats the last audio packet
during FIFO underflow when no audio data is available.
Set the AUDUFBEH bit (D2 of register 0x01D) to 1 to
output all zeroes during underflow.
Some audio DACs, such as the MAX9850, do not require
a synchronous main clock (MCLK), while other DACs
require a separate MCLK for operation. For audio applica-
tions that cannot use WS directly, the deserializer provides
a divided MCLK output at either CNTL2 or CNTL0 (deter-
mined by MCLKPIN bit setting) at the expense of one less
control line. By default, MCLK is turned off. Set MCLKDIV
(deserializer register 0x12, D[6:0]) to a nonzero value to
enable the MCLK output. Set MCLKDIV to 0x00 to disable
MCLK and set CNTL2 or CNTL0 as a control output.
The output MCLK frequency is:
Reverse Control Channel
f
SRC
f
=
The serializer uses the reverse control channel to receive
MCLK
MCLKDIV
2
I C/UART, MS, and GPO signals from the deserializer in
where:
is the MCLK source frequency (see Table 9)
the opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable forming a bidirectional link. The reverse
control channel operates independently from the forward
control channel. The reverse control channel is available
2ms after power-up. The serializer temporarily disables
the reverse control channel for 500µs after starting/
stopping the forward serial link.
f
SRC
MCLKDIV is the divider ratio from 1 to 127
Choose MCLKDIV values so that f
is not greater
MCLK
than 60MHz. MCLK frequencies derived from pixel clock
(MCLKSRC = 0) are not affected by spread-spectrum
settings in the deserializer. Enabling spread spectrum
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2
I S
TDM 256
WS
SCK
SD
WS
SCK
SD
8 TO 32 BITS
256 BITS
Figure 40. Audio Channel Output Format
Table 9. f
Settings
SRC
MCLKWS SETTING
(REGISTER 0x15, D1)
MCLKSRC SETTING
(REGISTER 0x12, D7)
DATA RATE
SETTING
MCLK SOURCE
BIT-WIDTH SETTING
FREQUENCY (f
)
SRC
24-bit or high-bandwidth mode
32-bit mode
3 x f
High speed
(DRS = 0)
PIXEL
4 x f
6 x f
8 x f
PIXEL
PIXEL
PIXEL
0
24-bit or high-bandwidth mode
32-bit mode
Low speed
(DRS = 1)
0
Internal oscillator
(120MHz typ)
1
—
—
—
—
1
—
WS*
*MCLK is not divided when using WS as the MCLK source. MCLK divider must still be set to a nonzero number for MCLK to be
enabled.
sending the UART packets to the serializer or deserializer,
with the UART packets converted to I C by the device
Control Channel and Register Programming
2
The control channel is available for the µC to send and
receive control data over the serial link simultaneously
with the high-speed data. The µC controls the link from
either the serializer or the deserializer side to support
video-display or image-sensing applications. The control
channel between the µC and serializer or deserializer
runs in base mode or bypass mode according to the
mode-selection input (MS) of the device connected to
the µC. Base mode is a half-duplex control channel and
bypass mode is a full-duplex control channel. The total
maximum forward or reverse control-channel delay is 2µs
on the remote side of the link. The µC communicates
with a UART peripheral in base mode (through INTTYPE
register settings), using the half-duplex default GMSL
UART protocol of the serializer/deserializer. The device
addresses of the serializer and deserializer in base mode
are programmable.
2
When the peripheral interface is I C, the serializer/
2
deserializer convert UART packets to I C that have
device addresses different from those of the serializer or
2
deserializer. The converted I C bit rate is the same as the
2
(UART) or 2-bit times (I C) from the input of one device
original UART bit rate.
2
to the output of the other. I C delay is measured from a
The deserializer uses differential line coding to send signals
over the reverse channel to the serializer. The bit rate of the
control channel is 9.6kbps to 1Mbps in both directions. The
serializer and deserializer automatically detect the control-
channel bit rate in base mode. Packet bit-rate changes can
be made in steps of up to 3.5 times higher or lower than the
previous bit rate. See the Changing the Clock Frequency
section for more information.
START condition to a STOP condition.
UART Interface
In base mode, the µC is the host and can access the
registers of both the serializer and deserializer from either
side of the link using the GMSL UART protocol. The µC
can also program the peripherals on the remote side by
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Figure 41 shows the UART protocol for writing and reading
in base mode between the µC and the serializer/deserializer.
command directly affects the serial link. The slave uses the
SYNC byte to synchronize with the host UART’s data rate.
If the GPI or MS inputs of the deserializer toggle while there
is control-channel communication, or if a line fault occurs,
the control-channel communication is corrupted. In the
event of a missed or delayed acknowledge (~1ms due to
control channel timeout), the µC should assume there was
an error in the packet transmission or response. In base
mode, the µC must keep the UART Tx/Rx lines high no
more than four bit times between bytes in a packet. Keep
the UART Tx/Rx lines high for at least 16 bit times before
starting to send a new packet.
Figure 42 shows the UART data format. Even parity is
used. Figure 43 and Figure 44 detail the formats of the
SYNC byte (0x79) and the ACK byte (0xC3). The µC and
the connected slave chip generate the SYNC byte and
ACK byte, respectively. Events such as device wake-up
and GPI generate transitions on the control channel that
can be ignored by the µC. Data written to the deserial-
izer registers do not take effect until after the ACK byte
is sent. This allows the µC to verify that write commands
are received without error, even if the result of the write
WRITE DATA FORMAT
DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1
SYNC
BYTE N
ACK
MASTER READS FROM SLAVE
MASTER WRITES TO SLAVE
READ DATA FORMAT
SYNC
DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 41. GMSL UART Protocol for Base Mode
1 UART FRAME
D4
START
D0
D1
D2
D3
D5
D6
D7
PARITY
STOP
FRAME 1
FRAME 2
FRAME 3
STOP
START
STOP
START
Figure 42. GMSL UART Data Format for Base Mode
D0
1
D1
0
D2
0
D3
1
D4
1
D5
1
D6
1
D7
0
D0
1
D1
1
D2
0
D3
0
D4
0
D5
0
D6
1
D7
1
START
PARITY STOP
START
PARITYSTOP
Figure 43. SYNC Byte (0x79)
Figure 44. ACK Byte (0xC3)
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As shown in Figure 45, the remote-side device converts
packets going to or coming from the peripherals from
UART format to I C format and vice versa. The remote
mode. Peripherals accessed through the forward control
channel using the UART interface need to handle at least
one pixel clock period 10ns of jitter due to the asynchro-
nous sampling of the UART signal by pixel clock. Set MS =
high in the serializer to put the control channel into bypass
mode. For applications with the µC connected to the dese-
rializer, set the MS pin on the deserializer. There is a 1ms
wait time between switching MS and the bypass control
channel being active; do not send a UART command
during this time. There is no delay time when switching
to bypass mode when the µC is connected to the serial-
izer. Although MS on either the serializer or deserializer
sets the control-channel byass mode, only the local-side
device (connected to the µC) should be used set bypass
mode, Do not switch MS while a UART command is being
sent. Do not send a logic-low value longer than 100µs to
ensure proper GPO functionality. Bypass mode accepts
bit rates down to 10kbps in either direction. See the
GPO/GPI Control section for GPI functionality limitations.
The control-channel data pattern should not be held low
longer than 100µs if GPI control is used.
2
device removes the byte number count and adds or
2
2
receives the ACK between the data bytes of I C. The I C
bit rate is the same as the UART bit rate.
2
Interfacing Command-Byte-Only I C Devices
with UART
2
The deserializers’ UART-to-I C conversion can interface
with devices that do not require register addresses, such
2
as the MAX7324 GPIO expander. In this mode, the I C
master ignores the register address byte and directly reads/
writes the subsequent data bytes (Figure 46). Change
2
the communication method of the I C master using the
I2CMETHOD bit. I2CMETHOD = 1 sets command-byte-
only mode, while I2CMETHOD = 0 sets normal mode where
the first byte in the data stream is the register address.
UART Bypass Mode
In bypass mode, the deserializers ignore UART commands
from the µC and the µC communicates with the peripher-
als directly using its own defined UART protocol. The µC
cannot access the serializer/deserializer’s registers in this
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
11
11
SYNC FRAME
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
DATA 0
DATA N
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER
11
µC
11
11
11
11
ACK FRAME
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
DEV ID W A REG ADDR
A
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
S: START
P: STOP
A: ACKNOWLEDGE
: MASTER TO SLAVE
: SLAVE TO MASTER
2
Figure 45. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0)
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2
2
device’s control-channel port becomes an I C master
I C Interface
2
2
that interfaces with remote-side I C peripherals. The I C
master must accept clock stretching that is imposed by
the deserializer (holding SCL low). The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition (Figure 6)
sent by a master, followed by the device’s 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
2
2
In I C-to-I C mode, the deserializer’s control-channel
interface sends and receives data through an I C-
2
compatible 2-wire interface. The interface uses a serial-
data line (SDA) and a serial-clock line (SCL) to achieve
bidirectional communication between master and slave(s).
A µC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
2
the data transfer. When an I C transaction starts on the
local-side device’s control-channel port, the remote-side
2
UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
SYNC FRAME
11
11
11
11
DATA 0
11
DATA N
11
DEVICE ID + WR
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
W
A
DATA 0
A
DATA N
A
P
2
UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)
µC
SERIALIZER/DESERIALIZER
11
11
11
11
11
11
DATA 0
11
DATA N
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
ACK FRAME
SERIALIZER/DESERIALIZER
PERIPHERAL
1
7
1
1
8
1
8
1
1
S
DEV ID
R
A
DATA 0
A
DATA N
A
P
: MASTER TO SLAVE
: SLAVE TO MASTER S: START
P: STOP A: ACKNOWLEDGE
2
Figure 46. Format Conversion Between GMSL UART and I C without Register Address (I2CMETHOD = 1)
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START and STOP Conditions
Acknowledge
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (see Figure 47). When the mas-
ter has finished communicating with the slave, it issues
a STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission.
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 49).
Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipi-
ent pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active. To prevent acknowl-
edge generation when the forward control channel is not
active, set the I2CLOCACK bit low.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 48). The data on SDA must remain stable while
SCL is high.
SDA
SCL
P
S
STOP
CONDITION
START
CONDITION
Figure 47. START and STOP Conditions
SDA
SCL
DATA LINE STABLEꢀ
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 48. Bit Transfer
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low for a write command and high for a read command.
Slave Address
The slave address for the deserializer is XX01XXX1 for
read commands and XX01XXX0 for write commands.
See Figure 50.
The deserializers have 7-bit long slave addresses. The
bit following a 7-bit slave address is the R/W bit, which is
START
CONDITION
CLOCK PULSE FOR
ACKNOWLEDGE
1
2
8
9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 49. Acknowledge
X
0
1
X
X
X
R/W
LSB
SDA
SCL
X
ACK
MSB
Figure 50. Slave Address
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address determines which register of the device is to be
written by the next byte, if received. If a STOP (P) condi-
Bus Reset
2
The device resets the bus with the I C START condition
for reads. When the R/W bit is set to 1, the deserializers
transmit data to the master, thus the master is reading
from the device.
tion is detected after the register address is received, the
device takes no further action beyond storing the register
address (Figure 51). Any bytes received after the register
address are data bytes. The first data byte goes into the
register selected by the register address, and subsequent
data bytes go into subsequent registers (Figure 52). If
multiple data bytes are transmitted before a STOP con-
dition, these bytes are stored in subsequent registers
because the register addresses autoincrement.
Format for Writing
Writes to the deserializers comprise the transmission of
the slave address with the R/W bit set to zero, followed
by at least 1 byte of information. The first byte of informa-
tion is the register address or command byte. The register
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
REGISTER 0x00 WRITE DATA
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
2
Figure 51. Format for I C Write
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
0
0
0
0
0
0
0
A
A
0
0
0
0
0
0
0
0
A
N
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
REGISTER 0x00 WRITE DATA
REGISTER 0x01 WRITE DATA
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
P
Figure 52. Format for Write to Multiple Registers
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2
Format for Reading
I C Communication with Remote-Side Devices
2
The deserializers are read using the internally stored
register address as an address pointer, the same way the
stored register address is used as an address pointer for
a write. The pointer autoincrements after each data byte
is read using the same rules as for a write. Thus, a read
is initiated by first configuring the register address by
performing a write (Figure 53). The master can now read
consecutive bytes from the device, with the first data byte
being read from the register address pointed by the previ-
ously written register address. Once the master sends a
NACK, the device stops sending valid data.
The deserializers support I C communication with a
peripheral on the remote side of the communication link
using SCL clock stretching. While multiple masters can
reside on either side of the communication link, arbitration
is not provided. The connected masters need to support
2
SCL clock stretching. The remote-side I C bit rate range
must be set according to the local-side I C bit rate.
Supported remote-side bit rates can be found in Table 10.
Set the I2CMSTBT (register 0x1C) to set the remote I C
bit rate. If using a bit rate different from 400kbps, local- and
remote-side I C setup and hold times should be adjusted
2
2
2
by setting the I2CSLVSH register settings on both sides.
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
S
1
0
0
0
0
0
0
0
A
0
0
0
0
0
0
0
0
A
S = START BIT
P = STOP BIT
A = ACK
1 = READ
ADDRESS = 0x81
REGISTER 0x00 READ DATA
REPEATED START
N = NACK
D_ = DATA BIT
S
1
0
0
0
0
0
0
1
A
D7
D6
D5
D4
D3
D2
D1
D0
N
P
2
Figure 53. Format for I C Read
2
Table 10. I C Bit-Rate Ranges
LOCAL BIT RATE
f > 50kbps
REMOTE BIT RATE RANGE
Up to 1Mbps
I2CMSTBT SETTING
Any
Up to 110
000
20kbps > f > 50kbps
f < 20kbps
Up to 400kbps
Up to 10kbps
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2
deserializer, together with preemphasis in the serializer, to
create the most reliable link for a given cable.
I C Address Translation
2
The deserializers support I C address translation for up to
two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
HS/VS/DE Tracking
The deserializer has tracking to filter out HS/VS/DE bit or
packet errors. HS/VS/DE tracking is on by default when
the device is in high-bandwidth mode (BWS = open),
and off by default when in 24-bit or 32-bit mode (BWS =
low or high). Set/clear HVTREN (D6 of register 0x15) to
enable/disable HS/VS tracking. Set/clear DETREN (D5 of
register 0x15) to enable/disable DE tracking. By default,
the device uses a partial and full periodic tracking of
HS/DE. Set HVTRMODE = 0 (D4 of register 0x15) to
disable full periodic tracking. HS/VS/DE tracking can be
turned on in 24-bit and 32-bit modes to track and correct
against bit errors in HS/VS/DE link bits.
2
I C addresses. Source addresses (address to translate
from) are stored in registers 0x18 and 0x1A. Destination
addresses (address to translate to) are stored in registers
0x19 and 0x1B.
In a multilink situation where there are multiple deserial-
izers and/or peripheral devices connected to these serial-
izers, the deserializers support broadcast commands to
control these multiple devices. Select an unused device
address to use as a broadcast device address. Program
all the remote-side serializer devices to translate the
broadcast device address (source address stored in reg-
isters 0x0F, 0x11) to the peripherals’ address (destination
address stored in registers 0x10, 0x12). Any commands
sent to the broadcast address (selected unused address)
are sent to all deserializers and/or peripheral devices con-
nected to the deserializers whose addresses match the
translated broadcast address.
Serial Input
The device can receive serial data from two kinds of
cable: 100Ω twisted pair and 50Ω coax. (Contact the
factory for devices compatible with 75Ω cables).
GPO/GPI Control
Table 11. Cable Equalizer Boost Levels
GPO on the serializer follows GPI transitions on the dese-
rializer. This GPO/GPI function can be used to transmit
signals such as a frame sync in a surround-view camera
system. The GPI-to-GPO delay is 0.35ms max. Keep
time between GPI transitions to a minimum 0.35ms. This
includes transitions from the other deserializer in coax
splitter mode. Bit D4 of register 0x06 in the deserializer
stores the GPI input state. GPO is low after power-up.
The µC can set GPO by writing to the SETGPO register
bit. Do not send a logic-low value on the deserializer
RX/SDA input (UART mode) longer than 100µs in
either base or bypass mode to ensure proper GPO/GPI
functionality. GPO/GPI commands will override and cor-
rupt an I2C/UART command in progress.
BOOST SETTING
TYPICAL BOOST GAIN (dB)
(0x05 D[3:0])
0000
0001
0010
0011
2.1
2.8
3.4
4.2
5.2
Power-up default when
EQS is set high
6.2
0100
0101
0110
0111
1000
7
8.2
9.4
10.7
Line Equalizer
1001
Power-up default when
EQS is set low
11.7
The deserializer includes an adjustable line equalizer to
further compensate cable attenuation at high frequencies.
The cable equalizer has 11 selectable levels of compen-
sation from 2.1dB to 13dB (Table 11). To select other
equalization levels, set the corresponding register bits
in the deserializer (0x05 D[3:0]). Use equalization in the
1010
1011
13
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3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
50Ω and a capacitor for increased power-supply rejection.
If OUT- is not used, connect OUT- to AVDD through a 50Ω
Coax Splitter Mode
In coax mode, OUT+ and OUT- of the serializer are active.
This enables the use as a 1:2 splitter (Figure 54). In coax
mode, connect OUT+ to IN+ of the deserializer. Connect
OUT- to IN- of the second deserializer. Control-channel
data is broadcast from the serializer to both deserializers
and their attached peripherals. Assign a unique address
to send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground through
resistor (Figure 55). When there are µCs at the serializer,
and at each deserializer, only one µC can communicate
at a time. Disable forward and reverse channel links
according to the communicating deserializer connection
2
2
to prevent contention in I C-to-I C mode. Use ENREVP
or ENREVN register bits to disable/enable the control
channel link. In UART mode, the serializer provides
arbitration of the control-channel link.
GMSL
SERIALIZER
MAX9288
MAX9290
OUT+
OUT-
IN+
IN-
OPTIONAL
COMPONENTS
FOR INCREASED
POWER-SUPPLY
REꢀECTION
MAX9288
MAX9290
IN+
IN-
Figure 54. 2:1 Coax Splitter Connection Diagram
GMSL
SERIALIZER
MAX9288
MAX9290
OUT+
IN+
IN-
OUT-
AVDD
OPTIONAL COMPONENTS FOR
INCREASED POWER-SUPPLY
REꢀECTION
50Ω
Figure 55. Coax Connection Diagram
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3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
the address location stored in the LUTADDR register.
Use 0x00 for LUTADDR and 0x00 as the number of bytes
field in UART packet, when writing a 256-byte data block,
Table 12. Configuration Input Map
CX/TP
High
Mid
FUNCTION
Coax+ input. 7-bit device address is XXXXXX0 (bin).
Coax- input. 7-bit device address is XXXXXX1 (bin).
because 8-bit-wide number of bytes field cannot normally
represent 9-bit wide “256” value. There is no number of
2
2
bytes field in I C-to-I C modes.
Twisted-pair input. 7-bit device address is
XXXXXX0 (bin).
Low
To read back the contents of an LUT, the µC generates
a read packet with register address set to the assigned
register address for respective LUT (0x7D, 0x7E, or
0x7F). The deserializer outputs read data from the
respectiveLUTstartingfromtheLUTaddresslocationsetin
the LUT_ADDR register. Similar to the write operation,
use 0x00 for LUTADDR and 0x00 as the number of bytes
field in UART packet, when reading a 256-byte data block.
Cable Type Configuration Input
CX/TP determine the power-up state of the serial input.
In coax mode, CX/TP also determine which coax input is
active, along with the default device address (Table 12).
Color Lookup Tables
The deserializer includes three color lookup tables (LUT)
to support automatic translation of pixel values. The LUT
can be used for RGB666, RGB888, and user-defined
generic 8-bit CSI-2 outputs. This feature can be used for
color gamma correction, brightness/contrast or for other
purposes. There are three lookup tables, each 8 bits wide
and 256 entries deep, enabling a 1-to-1 translation of 8-bit
input values to any 8-bit output value for each color (24
bits total).
LUT Color Translation
After power-up or going out of sleep or power-down
modes, LUT translation is disabled and LUT contents
are unknown. After program and verify operations are
finished, in order to enable LUT translations, set the
LUTPROG bit to 0 and set the respective LUT enable bits
(RED_LUT_EN, GRN_LUT_EN, BLU_LUT_EN) to 1 to
enable the desired LUT translation function. Only the
selected colors are translated by the LUT (the other
colors are not touched). The µC does not need to fill in all
three color lookup tables if all three color translations are
not needed.
Programming and Verifying LUT Data
The µC must set the LUTPROG register bit to 1 before
programming and verifying the tables. To program a LUT,
the µC generates a write packet with register address set
to the assigned register address for respective LUT (0x7D,
0x7E, or 0x7F). The deserializer writes data in the packet
to the respective LUT starting from the LUT address
location set in the LUTADDR register. Successive bytes
in the data packet are written to the next LUT address
location; however, each new data-packet write starts from
After a pixel is deserialized, decoded, and decrypted (if
necessary), it is segmented into its color components red,
green, and blue (RGB) according to Table 13 and Figure
56. If LUT translation is enabled, each 8-bit pretranslation
color value is used as address to the respective LUT table
to look up the corresponding (translated) 8-bit color value.
Table 13. Pixel Data Format
DOUT
[5:0]
DOUT
[11:6]
DOUT
[17:12]
DOUT
[22:21]
DOUT
[24:23]
DOUT
[26:25]
DOUT18
DOUT19
DOUT20
R[5:0]
G[5:0]
B[5:0]
HS
VS
DE
R[7:6]
G[7:6]
B[7:6]
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32-BIT OR HIGH-
BANDWIDTH MODE
32-BIT OR HIGH-
BANDWIDTH MODE
32-BIT OR HIGH-
BANDWIDTH MODE
R7
R6
G7
G6
B7
B6
24-BIT MODE
0
0
24-BIT MODE
0
0
24-BIT MODE
0
0
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
LSB
LSB
LSB
MSB
MSB
MSB
REDLUTEN
GRNLUTEN
BLULUTEN
ADDR
RED LUT
EN
ADDR
GREEN LUT
ADDR
BLUE LUT
EN
EN
DATA
DATA
DATA
LSB
LSB
LSB
MSB
MSB
MSB
OUTPUT DOUT DOUT
DOUT DOUT DOUT DOUT
DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
DOUT9 DOUT8 DOUT7 DOUT6
PIN
22
21
24
23
11
10
26
25
17
16
15
14
13
12
OUTPUT
SIGNAL
R7
R6
R5
R4
R3
R2
R1
R0
G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
Figure 56. LUT Dataflow
and 0x40 as number of bytes (UART only) and write 64
bytes. (Optional: Multiple write packets can be used if
LUTADDR is set before each LUT write packet.)
LUT Bit Width
In 32-bit and high-bandwidth modes, 24 bits are
available for color data (8 bits per color) and each LUT is
used for 8-bit to 8-bit color translation. In 24-bit mode, the
deserializer can receive only up to 18-bit color (6 bits per
color). The LUT tables can translate from 6-bit to 6-bit,
using the first 64 locations (0x00 to 0x3F). Program the
MSB 2 bits of each LUT value to 00. Alternatively, pro-
gram full 8-bit values to each LUT for 6-bit to 8-bit color
translation.
3) Read contents of red LUT and verify that they are
correct. Use the same register address and number
of bytes used in the previous step.
4) Repeat steps 2 and 3 for the green LUT, using 0x7E
as the register address.
5) Repeat steps 2 and 3 for the blue LUT, using 0x7F as
the register address.
Recommended LUT Program Procedure
6a) To finish the program and verify routine, without
enabling the LUT color translation, write LUTPROG =
0 (write 0x00 to register 0x7C).
1) Write LUTPROG = 1 to register 0x7C. Keep
BLULUTEN = 0, GRNLUTEN = 0, REDLUTEN = 0
(write 0x08 to register 0x7C).
6b) To finish the program and verify routine, and start LUT
color translation, write LUTPROG = 0, BLULUTEN =
1, GRNLUTEN = 1, REDLUTEN = 1 (write 0x07 to
register 0x7C).
2) Write contents of red LUT with a single write packet.
For 24-bit RGB, use 0x7D as register address and
0x00 as number of bytes (UART only) and write 256
bytes. For 18-bit RGB, use 0x7D as register address
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High-Immunity Reverse Control-Channel Mode
Sleep Mode
The deserializer contains a high-immunity reverse
control-channel mode, which has increased robustness at
half the bit rate over the standard GMSL reverse control-
channel link (Table 14). Set HIM on the serializer and
deserializer to use high-immunity mode at power-up. Set
the HIGHIMM bit high in both the serializer and dese-
rializer to enable high-immunity mode at any time after
power-up. Set the HIGHIMM bit low in both the serializer
and deserializer to use the legacy reverse control-channel
mode. The deserializer reverse channel mode is not avail-
able for 500µs/1.92ms after the reverse control-channel
mode is changed through the serializer/deserializer’s
HIGHIMM bit setting, respectively. The user must set HIM
or the HIGHIMM bits to the same value for proper reverse
control-channel communication.
The deserializers have sleep mode to reduce power
consumption. The devices enter or exit sleep mode by a
command from a remote µC using the control channel.
Set the SLEEP bit to 1 to initiate sleep mode. Entering
sleep mode resets the HDCP registers, but not the con-
figuration registers. The deserializer sleeps after serial
link inactivity or 8ms (whichever arrives first) after setting
its SLEEP = 1. See the Link Startup Procedure section
for details on waking up the device for different µC and
starting conditions.
To wake up from the local side, send an arbitrary control-
channel command to the deserializer, wait for 5ms for the
chip to power up, and then write 0 to SLEEP register bit
to make the wake-up permanent. To wake up from the
remote side, enable serialization. The deserializer detects
the activity on serial link and then when it locks, it auto-
matically sets its SLEEP register bit to 0.
In high-immunity mode, Set HPFTUNE = 00 in the equal-
izer, if the serial bit rate = [pixel clock x 30 (BWS = low
or open) or 40 (BWS = high)] is larger than 1Gbps when
BWS is low or high. When BWS = open, set HPFTUNE =
00 when the serial bit rate is larger than 2GBps.
Power-Down Mode
The deserializers have a power-down mode that further
reduces power consumption compared to sleep mode. Set
PWDN low to enter power-down mode. In power-down, the
parallel outputs remain high impedance. Entering power-
down resets the device’s registers. Upon exiting power-
down, the state of external pins ADD0–ADD2, CX/TP,
I2CSEL, DRS, EQS, HIM/CNTL1, and BWS are latched.
By default, high-immunity mode uses a 500kbps bit rate.
Set REVFAST =1 (D7 in register 0x1A in the serializer and
register 0x11 in the deserializer) in both devices to use a
1Mbps bit rate. Certain limitations apply when using the
fast high-immunity mode (Table 15).
Table 14. Reverse Control-Channel Modes
MAX UART/
2
HIGHIMM BIT OR
SD/HIM PIN SETTING
REVFAST
REVERSE CONTROL-CHANNEL MODE
I C BIT RATE
(kbps)
BIT
Legacy reverse control-channel mode (compatible with all GMSL
Low (0)
X
1000
devices)
0
High-immunity mode
500
High (1)
1
Fast high-immunity mode
1000
X = Don’t care.
Table 15. Fast High-Immunity Mode Requirements
BWS SETTING
Low
ALLOWED PIXEL CLOCK FREQUENCY (MHz)
> 41.66
> 30
High
Open
> 83.33
Fast high-immunity mode requires DRS = 0.
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3.12Gbps GMSL Deserializers
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enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
Configuration Link
The control channel can operate in a low-speed mode
called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscil-
lator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable configuration
link. Configuration link is active until the video link is
Link Startup Procedure
Table 16 lists the startup procedure for image-sensing
applications. The control channel is available after the
video link or the configuration link is established. If the
deserializer powers up after the serializer, the control
channel becomes unavailable for 2ms after power-up.
Table 16. Startup Procedure for Image-Sensing Applications (CDS = High, Figure 58)
SERIALIZER
NO.
µC
DESERIALIZER
(AUTOSTART ENABLED)
(AUTOSTART DISABLED)
Sets all configuration
inputs.
Sets all configuration
inputs.
Sets all configuration
inputs.
—
µC connected to deserializer.
Powers up and loads
default settings.
Establishes video link when
valid PCLK available.
Powers up and loads
default settings.
Locks to video link
signal if available.
Powers up and loads
default settings. Goes to
sleep after 8ms.
1
Powers up.
Configuration
changed from default
settings.
Writes deserializer configuration bits
and gets an acknowledge.
2
Wakes up the serializer by sending
dummy packet, and then writing
SLEEP = 0 within 8ms. May not get
an acknowledge (or gets a dummy
acknowledge) if not locked.
3
Wakes up.
Writes serializer configuration bits.
May not get an acknowledge (or gets
a dummy acknowledge) if not locked.
4
Configuration changed from default settings.
If not already enabled, sets SEREN =
1, gets an acknowledge and waits for
serial link to be established (~3ms).
Locks to video link
signal (if not already
locked).
Establishes video link when valid PCLK available (if not
already enabled).
5
Video data received
and deserialized.
6
Begin sending video data to input.
Video data serialized and sent across serial link.
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every 128 frames. These values are compared internally
(internal comparison mode) or can be compared in the
host µC.
High-Bandwidth Digital Content
Protection (HDCP)
Note: The explanation of HDCP operation in this data
sheet is provided as a guide for general understanding.
Implementation of HDCP in a product must meet the
requirements given in the HDCP System v1.3 Amendment
for GMSL, which is available from DCP.
In addition, the GMSL serializer/deserializer provide
response values for the enhanced link verification.
Enhanced link verification is an optional method of link
verification for faster detection of loss-of-synchronization.
For this option, the GMSL serializer and deserializer
generate 8-bit enhanced link-verification response values
(PJ and PJ’) every 16 frames. The host must detect three
consecutive PJ/PJ’ mismatches before resampling.
HDCP has two main phases of operation, authentication
and the link integrity check. The µC starts authentica-
tion by writing to the START_AUTHENTICATION bit in
the GMSL serializer. The GMSL serializer generates a
64-bit random number. The host µC first reads the 64-bit
random number from the GMSL serializer and writes it
to the deserializer. The µC then reads the GMSL serial-
izer public key selection vector (AKSV) and writes it to
the deserializer. The µC then reads the deserializer KSV
(BKSV) and writes it to the GMSL serializer. The µC
begins checking BKSV against the revocation list. Using
the cipher, the GMSL serializer and deserializer calculate
a 16-bit response value, R0 and R0’, respectively. The
GMSL amendment for HDCP reduces the 100ms mini-
mum wait time allowed for the receiver to generate R0’
(specified in HDCP rev 1.3) to 128 pixel clock cycles in
the GMSL amendment.
Encryption Enable
The GMSL link transfers either encrypted or nonen-
crypted data. To encrypt data, the host µC sets the
encryption enable (ENCRYPTION_ENABLE) bit in both
the GMSL serializer and deserializer. The µC must set
ENCRYPTION_ENABLE in the same VSYNC cycle in
both the GMSL serializer and deserializer (no internal
VSYNC falling edges between the two writes). The same
timing applies when clearing ENCRYPTION_ENABLE to
disable encryption.
Note: ENCRYPTION_ENABLE enables/disables encryp-
tion on the GMSL irrespective of the content. To comply
with HDCP, the µC must not allow content requiring
encryption to cross the GMSL unencrypted.
There are two response-value comparison modes, internal
comparison and µC comparison. Set EN_INT_COMP = 1
to select internal comparison mode. Set EN_INT_COMP
= 0 to select µC comparison mode. In internal compari-
son mode, the µC reads the deserializer response R0’
and writes it to the GMSL serializer. The GMSL serializer
compares R0’ to its internally generated response value
R0, and sets R0_RI_MATCHED. In µC comparison mode,
the µC reads and compares the R0/R0’ values from the
GMSL serializer/deserializer.
The µC must complete the authentication process before
enabling encryption. In addition, encryption must be dis-
abled before starting a new authentication session.
Synchronization of Encryption
The video vertical sync (VSYNC) synchronizes the start
of encryption. Once encryption has started, the GMSL
generates a new encryption key for each frame and each
line, with the internal falling edge of VSYNC and HSYNC.
Rekeying is transparent to data and does not disrupt the
encryption of video or audio data.
During response-value generation and comparison, the
host µC checks for a valid BKSV (having 20 1s and 20
0s is also reported in BKSV_INVALID) and checks BKSV
against the revocation list. If BKSV is not on the list and
the response values match, the host authenticates the
link. If the response values do not match, the µC resam-
ples the response values (as described in HDCP rev 1.3,
Appendix C). If resampling fails, the µC restarts authen-
tication by setting the RESET_HDCP bit in the GMSL
serializer. If BKSV appears on the revocation list, the host
cannot transmit data that requires protection. The host
knows when the link is authenticated and decides when
to output data requiring protection. The µC performs a link
integrity check every 128 frames or every 2s ±0.5s. The
GMSL serializer/deserializer generate response values
Repeater Support
The GMSL serializer/deserializer include features to build
an HDCP repeater. An HDCP repeater receives and
decrypts HDCP content and then encrypts and transmits
on one or more downstream links. A repeater can also use
decrypted HDCP content (e.g., to display on a screen).
To support HDCP repeater-authentication protocol, the
deserializer has a REPEATER register bit. This register
bit must be set to 1 by a µC (most likely on the repeater
module). Both the GMSL serializer and deserializer use
SHA-1 hash-value calculation over the assembled KSV
lists. HDCP GMSL links support a maximum of 15 receiv-
ers (total number including the ones in repeater modules).
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If the total number of downstream receivers exceeds 14,
the µC must set the MAX_DEVS_EXCEEDED register bit
when it assembles the KSV list.
procedures to authenticate the HDCP GMSL encryption
(refer to the HDCP 1.3 Amendment for GMSL for details).
The µC must perform link integrity checks while encryp-
tion is enabled (see Table 17). Any event that indicates
that the deserializer has lost link synchronization should
retrigger authentication. The µC must first write 1 to the
RESET_HDCP bit in the GMSL serializer before starting
a new authentication attempt.
HDCP Authentication Procedures
The GMSL serializer generates a 64-bit random number
exceeding the HDCP requirement. The GMSL serial-
izer/deserializer internal one-time programmable (OTP)
memories contain a unique HDCP keyset programmed at
the factory. The host µC initiates and controls the HDCP
authentication procedure. The GMSL serializer and dese-
rializer generate HDCP authentication response values
for the verification of authentication. Use the following
HDCP Protocol Summary
Table 17, Table 18, and Table 19 list the summaries of the
HDCP protocol. These tables serve as an implementation
guide only. Meet the requirements in the GMSL amend-
ment for HDCP to be in full compliance.
Table 17. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Powers up waiting for HDCP
authentication.
Powers up waiting for HDCP
authentication.
1
Initial state after power-up.
Makes sure that A/V data not requiring
protection (low-value content) is available at
the GMSL serializer inputs (such as blue or
informative screen). Alternatively, uses the
FORCE_VIDEO and FORCE_AUDIO bits of
the GMSL serializer to mask A/V data at the
input of the GMSL serializer. Starts the link by
writing SEREN = H or link starts automatically
if AUTOS is low.
2
—
—
Starts serialization and transmits Locks to incoming data stream and
3
—
low-value content A/V data.
outputs low-value content A/V data.
Reads the locked bit of the deserializer and
makes sure the link is established.
4
—
—
Combines seed with internally
generated random number. If
no seed provided, only internal
random number is used.
Optionally writes a random-number seed to
the GMSL serializer.
5
—
—
If HDCP encryption is required, starts
authentication by writing 1 to the
START_AUTHENTICATION bit of the GMSL
serializer.
Generates (stores) AN, and
resets the
START_AUTHENTICATION bit
to 0.
6
Reads AN and AKSV from the GMSL serializer
and writes to the deserializer.
Generates R0’ triggered by the µC’s
write of AKSV.
7
—
Reads the BKSV and REPEATER bit from the
deserializer and writes to the GMSL serializer.
Generates R0, triggered by the
µC’s write of BKSV.
8
—
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Table 17. Startup, HDCP Authentication, and Normal Operation (Deserializer is Not a
Repeater)—First Part of the HDCP Authentication Protocol (continued)
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Reads the INVALID_BKSV bit of the GMSL
serializer and continues with authentication
if it is 0. Authentication can be restarted if it
fails (set RESET_HDCP = 1 before restarting
authentication).
9
—
—
Reads R0’ from the deserializer and reads
R0 from the GMSL serializer. If they match,
continues with authentication; otherwise,
retries up to two more times (optionally, GMSL
serializer comparison can be used to detect if
R0/R0’ match). Authentication can be restarted
if it fails (set RESET_HDCP = 1 before
restarting authentication).
10
—
—
Waits for the VSYNC falling edge (internal to
the GMSL serializer) and then sets the
ENCRYPTION_ENABLE bit to 1 in the
deserializer and GMSL serializer (if the FC is
not able to monitor VSYNC, it can utilize the
VSYNC_DET bit in the GMSL serializer).
Encryption enabled after the
next VSYNC falling edge.
Decryption enabled after the next
VSYNC falling edge.
11
Checks that BKSV is not in the Key
Revocation list and continues if it is not.
Authentication can be restarted if it fails.
Note: Revocation list check can start after
BKSV is read in step 8.
12
13
—
—
Starts transmission of A/V content that needs
protection.
Performs HDCP encryption on
high-value content A/V data.
Performs HDCP decryption on high-
value content A/V data.
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Table 18. Link Integrity Check (Normal)—Performed Every 128 Frames After Encryption
is Enabled
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Generates Ri and updates the
RI register every 128 VSYNC
cycles.
Generates Ri’ and updates the RI’
register every 128 VSYNC cycles.
1
—
Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
2
3
—
Every 128 video frames (VSYNC cycles) or
every 2s.
—
—
4
Reads RI from the GMSL serializer.
Reads RI’ from the deserializer.
—
—
—
—
5
Reads RI again from the GMSL serializer and
makes sure it is stable (matches the previous
RI that it has read from the GMSL serializer). If
RI is not stable, go back to step 5.
6
7
—
—
—
—
If RI matches RI’, the link integrity check is
successful; go back to step 3.
If RI does not match RI’, the link integrity
check fails. After the detection of failure of
link integrity check, the FC makes sure that
A/V data not requiring protection (low-value
content) is available at the GMSL serializer
inputs (such as blue or informative screen).
Alternatively, the FORCE_VIDEO and
FORCE_AUDIO bits of the GMSL serializer
can be used to mask A/V data input of the
GMSL serializer.
8
—
—
Disables encryption and
transmits low-value content A/V
data.
Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables decryption and outputs low-
value content A/V data.
9
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
10
—
—
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Table 19. Optional Enhanced Link Integrity Check—Performed Every 16 Frames After
Encryption is Enabled
NO.
µC
HDCP GMSL SERIALIZER
HDCP GMSL DESERIALIZER
Generates PJ and updates the
PJ register every 16 VSYNC
cycles.
Generates PJ’ and updates the PJ’
register every 16 VSYNC cycles.
1
—
Continues to encrypt and
transmit A/V data.
Continues to receive, decrypt, and
output A/V data.
2
3
4
—
Every 16 video frames, reads PJ from the
GMSL serializer and PJ’ from the deserializer.
—
—
—
—
If PJ matches PJ’, the enhanced link integrity
check is successful; go back to step 3.
If there is a mismatch, retry up to two more
times from step 3. Enhanced link integrity
check fails after 3 mismatches. After the
detection of failure of enhanced link integrity
check, the µC makes sure that A/V data not
requiring protection (low-value content) is
available at the GMSL serializer inputs (such
as blue or informative screen). Alternatively,
the FORCE_VIDEO and FORCE_AUDIO bits
of the GMSL serializer can be used to mask
A/V data input of the GMSL serializer.
5
—
—
Disables encryption and
transmits low-value content A/V
data.
Writes 0 to the ENCRYPTION_ENABLE bit of
the GMSL serializer and deserializer.
Disables decryption and outputs low-
value content A/V data.
6
7
Restarts authentication by writing 1 to the
RESET_HDCP bit followed by writing 1 to the
START_AUTHENTICATION bit in the GMSL
serializer.
—
—
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Example Repeater Network—Two µCs
Detection and Action Upon New Device
Connection
The example shown in Figure 58 has one repeater and two
µCs. Table 20 summarizes the authentication operation.
When a new device is connected to the system, the
device must be authenticated and the device’s KSV
checked against the revocation list. The downstream
µCs can set the NEW_DEV_CONN bit of the upstream
receiver and invoke an interrupt to notify upstream µCs.
SLEEP = 1, VIDEO LINK OR CONFIG
LINK NOT LOCKED AFTER 8ms
CONFIG LINK
UNLOCKED
CONFIG LINK
OPERATING
WAKE-UP
SIGNAL
SIGNAL
POWER-ON
IDLE
SERIAL PORT
LOCKING
SLEEP
DETECTED
PROGRAM
REGISTERS
CONFIG LINK
LOCKED
0
SLEEP
VIDEO LINK
LOCKED
VIDEO LINK
UNLOCKED
SERIAL LINK ACTIVITY STOPS OR 8ms ELAPSES AFTER
µC SETS SLEEP = 1
PWDN = HIGH,
POWER-ON
GPI CHANGES FROM
LOW TO HIGH OR
PRBSEN = 0
PRBSEN = 1
SEND GPI TO
POWER-DOWN
VIDEO LINK
OPERATING
VIDEO LINK
PRBS TEST
HIGH TO LOW
PWDN = LOW OR
POWER-OFF
ALL STATES
OR
POWER-OFF
GMSL
SERIALIZER
0
SLEEP
Figure 57. State Diagram (CDS = High)
BD-DRIVE
TX_B1
REPEATER
RX_R1
DISPLAY 1
TX_R1
TX_R2
RX_D1
VIDEO
ROUTING
µC_B
DISPLAY 2
RX_D2
MEMORY
WITH SRM
RX_R2
µC_R
VIDEO CONNECTION
CONTROL CONNECTION 1 (µC_B IN BD-DRIVE IS MASTER)
CONTROL CONNECTION 2 (µC_R IN REPEATER IS MASTER)
Figure 58. Example Network with One Repeater and Two µCs (Tx = GMSL Serializer’s, Rx = Deserializer’s)
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Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
All: Power-up waiting for
HDCP authentication.
All: Power-up waiting for
HDCP authentication.
1
Initial state after power-up.
Initial state after power-up.
Writes REPEATER = 1 in
RX_R1. Retries until proper
acknowledge frame received.
Note: This step must be
completed before the first part
of authentication is started
between TX_B1 and RX_R1 by
the µC_B (step 7). For example,
to satisfy this requirement,
RX_R1 can be held at power-
down until µC_R is ready to
write the REPEATER bit, or
µC_B can poll µC_R before
starting authentication.
2
—
—
—
Makes sure that A/V data
not requiring protection (low-
value content) is available at
the TX_B1 inputs (such as
blue or informative screen).
Alternatively, the FORCE_
VIDEO and FORCE_AUDIO
bits of TX_B1 can be used to
mask A/V data input of TX_B1.
Starts the link between TX_B1
and RX_R1 by writing SEREN
= H to TX_B1, or link starts
automatically if serializer’s
AUTOS is low.
TX_B1: Starts
RX_R1: Locks to
serialization and
transmits low-value
content A/V data.
incoming data stream
and outputs low-value
content A/V data.
3
—
Starts all downstream links
by writing SEREN = H to
TX_R1, TX_R2, or links start
automatically if AUTOS of
transmitters are low.
TX_R1, TX_R2: Starts
serialization and
transmits low-value
content A/V data.
RX_D1, RX_D2: Locks
to incoming data stream
and outputs low-value
content A/V data.
4
—
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Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
Reads the locked bit of RX_D1
and makes sure the link
Reads the locked bit of RX_R1
and makes sure the link
between TX_B1 and RX_R1 is
established.
between TX_R1 and RX_D1 is
established. Reads the locked
bit of RX_D2 and makes sure
the link between TX_R2 and
RX_D2 is established.
5
—
—
Writes 1 to the
GPIO_0_FUNCTION and
GPIO_1_FUNCTION bits
in RX_R1 to change GPIO
functionality used for HDCP
purpose. Optionally, writes a
random-number seed to TX_R1
and TX_R2.
Optionally, writes a random
number seed to TX_B1.
6
—
—
Starts and completes the
TX_B1: According
to commands from
µC_B, generates AN,
computes R0.
RX_R1: According to
commands from µC_B,
computes R0’.
first part of the authentication
protocol between TX_B1, RX_R1
(see steps 6–10 in Table 17).
7
—
When GPIO_1 = 1 is detected,
starts and completes the first part TX_R1, TX_R2:
RX_D1, RX_D2:
of the authentication protocol
between the (TX_R1, RX_D1)
and (TX_R2, RX_D2) links (see
steps 6–10 in Table 17).
According to commands According to commands
8
—
from µC_R, generates
AN, computes R0.
from µC_R, computes
R0’.
Waits for the VSYNC falling
edge and then enables
encryption on the (TX_B1,
RX_R1) link. Full authentication
is not complete yet so it makes
sure A/V content that needs
protection is not transmitted.
Since REPEATER = 1 was read
from RX_R1, the second part of
authentication is required.
TX_B1: Encryption
enabled after next
VSYNC falling edge.
RX_R1: Decryption
enabled after next
VSYNC falling edge.
9
—
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Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
When GPIO_0 = 1 is detected,
enables encryption on the
(TX_R1, RX_D1) and (TX_R2,
RX_D2) links.
TX_R1, TX_R2:
Encryption enabled
after next VSYNC
falling edge.
RX_D1, RX_D2:
Decryption enabled
after next VSYNC
falling edge.
10
11
—
RX_R1: Control
Blocks control channel
channel from serializer
side (TX_B1) is blocked
after FWDCCEN =
REVCCEN = 0 is
written.
from µC_B side by setting
REVCCEN = FWDCCEN = 0
in RX_R1. Retries until proper
acknowledge frame received.
—
—
Waits for some time to allow
µC_R to make the KSV list
ready in RX_R1. Then polls
(reads) the KSV_LIST_READY
bit of RX_R1 regularly until
proper acknowledge frame is
received and bit is read as 1.
RX_R1: Triggered by
µC_R’s write of BINFO,
calculates hash value
(V’) on the KSV list,
BINFO and the secret-
value M0’.
Writes BKSVs of RX_D1 and
RX_D2 to the KSV list in RX_
R1. Then, calculates and writes
the BINFO register of RX_R1.
12
13
Writes 1 to the KSV_LIST_
READY bit of RX_R1 and then
unblocks the control channel
from the µC_B side by setting
REVCCEN = FWDCCEN = 1 in
RX_R1.
RX_R1: Control channel
from the serializer side
(TX_B1) is unblocked
after FWDCCEN =
REVCCEN = 1 is
written.
—
Reads the KSV list and BINFO
from RX_R1 and writes them
to TX_B1. If any of the MAX_
DEVS_EXCEEDED or MAX_
CASCADE_EXCEEDED bits
is 1, then authentication fails.
Note: BINFO must be written
after the KSV list.
TX_B1: Triggered by
µC_B’s write of BINFO,
calculates hash value
(V) on the KSV list,
BINFO and the secret-
value M0.
14
—
—
Reads V from TX_B1 and V’
from RX_R1. If they match,
continues with authentication;
otherwise, retries up to two
more times.
15
16
—
—
—
—
—
—
Searches for each KSV in the
KSV list and BKSV of RX_R1 in
the Key Revocation list.
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Table 20. HDCP Authentication and Normal Operation (One Repeater, Two µCs)—First
and Second Parts of the HDCP Authentication Protocol (continued)
HDCP GMSL
SERIALIZER
(TX_B1, TX_R1,
TX_R2)
HDCP GMSL
DESERIALIZER
(RX_R1, RX_D1,
RX_D2)
NO.
µC_B
µC_R
TX_B1 CDS = 0
TX_R1 CDS = 0
TX_R2 CDS = 0
RX_R1 CDS = 1
RX_D1 CDS = 0
RX_D2 CDS = 0
If keys are not revoked,
the second part of the
authentication protocol is
completed.
17
18
—
—
—
—
All: Perform HDCP
encryption on high-
value A/V data.
All: Perform HDCP
decryption on high-
value A/V data.
Starts transmission of A/V
content that needs protection.
Notification of Start of Authentication and
Applications Information
Enable of Encryption to Downstream Links
Self PRBS Test
HDCP repeaters do not immediately begin authentication
upon startup or detection of a new device, but instead wait
for an authentication request from the upstream transmit-
ter/repeaters.
The serializers include a PRBS pattern generator that
works with bit-error verification in the deserializer. To run
the PRBS test, first disable HDCP encryption. Next, set
DISHSFILT, DISVSFILT, and DISDEFILT to 1, to disable
glitch filter in the deserializer. Then, set PRBSEN = 1
(0x04, D5) in the serializer and then in the deserializer.
To exit the PRBS test, set PRBSEN = 0 (0x04, D5) in the
deserializer and then in the serializer.
Use the following procedure to notify downstream links of
the start of a new authentication request:
1) Host µC begins authentication with the HDCP repeater’s
input receiver.
2) When AKSV is written to HDCP repeater’s input
receiver, its AUTH_STARTED bit is automatically set
and its GPIO1 goes high (if GPIO1_FUNCTION is set
to high).
Error Checking
The deserializers check the serial link for errors and
store the number of decoding errors in the 8-bit registers
DECERR (0x0D). If a large number of decoding errors
are detected within a short duration (error rate ≥ 1/4),
the deserializers lose lock and stop the error counter.
The deserializers then attempt to relock to the serial
data. DECERR reset upon successful video link lock,
successful readout of the register (through µC), or when-
ever auto error reset is enabled. The deserializers use a
separate PRBS register during the internal PRBS test,
and DECERR are reset to 0x00.
3) HDCP repeater’s µC waits for a low-to-high transition
on HDCP repeater input receiver’s AUTH_STARTED
bit and/or GPIO1 (if configured) and starts authentica-
tion downstream.
4) HDCP repeater’s µC resets the AUTH_STARTED bit.
Set GPIO0_FUNCTION to high to have GPIO0 follow the
ENCRYPTION_ENABLE bit of the receiver. The repeater
µC can use this function for notification when encryption
is enabled/disabled by an upstream µC.
ERR Output
The deserializers have an open-drain ERR output. This
output asserts low whenever the number of decoding
errors exceeds the error thresholds during normal opera-
tion, or when at least one PRBS error is detected during
PRBS test. ERR reasserts high whenever DECERR
resets, due to DECERR readout, video link lock, or auto
error reset.
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Auto Error Reset
Spread-Spectrum Clock Tracking
The default method to reset errors is to read the respec-
tive error registers in the deserializers (0x0D and 0x0E).
Auto error reset clears the error counters DECERR and
the ERR output ~1µs after ERR goes low. Auto error reset
is disabled on power-up. Enable auto error reset through
AUTORST (0x06, D5). Auto error reset does not run when
the device is in PRBS test mode.
Using a spread-spectrum clock source can reduce EMI/
EMC on the serial and MIPI data. The deserializer can
track a spread-spectrum signal from the serializer. Use
a spread < 1% for CSI-2 output rates ≤ 400MHz. Use a
spread < 0.5% for CSI-2 output rates > 400MHz.
Fast Detection of Loss-of-Synchronization
A measure of link quality is the recovery time from loss-
of-synchronization. The host can be quickly notified of
loss-of-lock by connecting the deserializer’s LOCK out-
put to the GPI input. If other sources use the GPI input,
such as a touch-screen controller, the µC can implement
a routine to distinguish between interrupts from loss-
of-sync and normal interrupts. Reverse control-channel
communication does not require an active forward link
to operate and accurately tracks the LOCK status of the
GMSL link. LOCK asserts for video link only and not for
the configuration link.
Dual µC Control
Usually systems have one microcontroller to run the
control channel, located on the serializer side for display
applications or on the deserializer side for image-sensing
applications. However, a µC can reside on each side
simultaneously and trade off running the control channel.
In this case, each µC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both µCs attempt to use the control
channel at the same time. It is up to the user to
prevent this contention by implementing a higher level
protocol. In addition, the control channel does not provide
Providing a Frame Sync (Camera
Applications)
2
arbitration between I C masters on both sides of the
The GPI/GPO provide a simple solution for camera
applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input, and connect GPO
output to the camera frame sync input. GPI/GPO has
a typical delay of 275µs. Skew between multiple GPI/
GPO channels is typically 115µs. If a lower skew signal is
required, connect the camera’s frame sync input to one of
link. An acknowledge frame is not generated when
communication fails due to contention. If communication
across the serial link is not required, the µCs can disable
the forward and reverse control channel using the
FWDCCEN and REVCCEN bits (0x04, D[1:0]) in the
serializer/deserializer. Communication across the serial
link is stopped and contention between µCs cannot occur.
As an example of dual µC use in an image-sensing appli-
cation, the serializer can be in sleep mode and waiting
for wake-up by µC on the deserializer side. After wake-
up, the serializer-side µC assumes master control of the
serializer’s registers.
2
the deserializer’s GPIOs and use an I C broadcast write
command to change the GPIO output state. This has a
2
maximum skew of 1.5µs, independent from the used I C
bit rate.
Software Programming of the Device
Addresses
Changing the Clock Frequency
It is recommended that the serial link be enabled after the
The serializers and deserializers have programmable
device addresses. This allows multiple GMSL devices,
along with I C peripherals, to coexist on the same control
video clock (f
) and the control-channel clock (f
/
pixel
UART
f ) are stable. When changing the clock frequency,
I2C
2
stop the video clock for 5µs, apply the clock at the new
frequency, then restart the serial link or toggle SEREN.
On-the-fly changes in clock frequency are possible if
the new frequency is immediately stable and without
glitches. The reverse control channel remains unavailable
for 500µs after serial link start or stop. When using the
channel. The serializer device address is in register 0x00
of each device, while the deserializer device address is in
register 0x01 of each device. To change a device address,
first write to the device whose address changes (register
0x00 of the serializer for serializer device address change,
or register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
UART interface, limit on-the-fly changes in f
to
UART
factors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
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Three-Level Configuration Inputs
WS/SCK Inversion
2
CX/TP and BWS are three-level inputs that control the seri-
al interface configuration and power-up defaults. Connect
three-level inputs through a pullup resistor to IOVDD to set
a high level, a pulldown resistor to GND to set a low level,
or open to set a mid level. For digital control, use three-
state logic to drive the three-level logic input.
The deserializers use standard polarities for I S. Set
INVWS and INVSCK in the serializer (register 0x1B) to
invert opposite polarity signals for use with the GMSL
devices. Set INVWS and INVSCK in the deserializer
(register 0x1D) to output reverse-polarity signals for
downstream use.
Configuration Blocking
GPIOs
The deserializers can block changes to registers. Set
CFGBLOCK to make registers 0x00 to 0x1F as read only.
Once set, the registers remain blocked until the supplies
are removed or until PWDN is low.
The deserializers have two open-drain GPIOs available
when not used for HDCP purposes (see the Notification
of Start of Authentication and Enable of Encryption to
Downstream Links section), GPIO1OUT and GPIO0OUT
(0x06, D3 and D1) set the output state of the GPIOs.
Setting the GPIO output bits to 0 low pulls the output low,
while setting the bits to 1 leaves the output undriven, and
pulled high through internal/external pullup resistors. The
GPIO input buffers are always enabled. The input states
are stored in GPIO1 and GPIO0 (0x06, D2 and D0). Set
GPIO1OUT/GPIO0OUT to 1 when using GPIO1/GPIO0
as an input.
Compatibility with Other GMSL Devices
The deserializers are designed to pair with the MAX9275–
MAX9281 serializers, but interoperate with any GMSL
serializers. See Table 21 for operating limitations
Key Memory
Each device has a unique HDCP key set that is stored
in secure nonvolatile memory (NVM). The HDCP key set
consists of 40 56-bit private keys and one 40-bit public
key. The NVM is qualified for automotive applications.
Line-Fault Detection
The line-fault detector monitors for line failures such
as short to ground, short to battery, and open link for
system-fault diagnosis. Figure 1 shows the required
external resistor connections. LFLT = low when a line fault
is detected and LFLT goes high when the line returns to
normal. The line-fault type is stored in 0x08 D[3:0] of the
serializer. Filter LFLT with the µC to reduce the detector’s
susceptibility to short ground shifts. The fault-detector
threshold voltages are referenced to the serializer ground.
Additional passive components set the DC level of the
cable. If the serializer and GMSL deserializer grounds are
different, the link DC voltage during normal operation can
vary and cross one of the fault-detection thresholds.
HS/VS/DE Inversion
The deserializers use an active-high HS, VS, and DE
for encoding and HDCP encryption. Set INVHSYNC,
INVVSYNC, and INVDE in the serializer to invert active-
low input signals for use with the GMSL devices. Set
INVHSYNC, INVVSYNC, and INVDE in the deserializer
(register 0x14) to output active-low signals for use with
downstream devices.
Table 21. MAX9288/MAX9290 Feature Compatibility
FEATURE
HDCP (MAX9290 only)
High-bandwidth mode
GMSL SERIALIZER
If feature not supported in serializer, must not be turned on in the MAX9290.
If feature not supported in serializer, must only use 24-bit and 32-bit modes.
2
2
2
I C-to-I C
If feature not supported in serializer, must use UART-to-I C or UART-to-UART.
If feature not supported in serializer, must connect unused serial output through 200nF and
Coax
50Ω in series to V
and set the reverse control channel amplitude to 100mV.
DD
High-immunity control channel
TDM encoding
If feature not supported in serializer, must use the legacy reverse control-channel mode.
2
If feature not supported in serializer, must use I S encoding (with 50% WS duty cycle), if
supported.
2
2
I S encoding
If feature not supported in serializer, must disable I S in the MAX9288/MAX9290.
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For the fault-detection circuit, select the resistor’s power
rating to handle a short to the battery. In coax mode,
leave the unused line-fault inputs unconnected. To detect
the short-together case, refer to Application Note 4709:
GMSL Line-Fault Detection. Table 23 lists the mapping
for line fault types
change the system time constant. Use at 0.22μF (using
power over coax or legacy reverse control channel), 47nF
(using high-immunity reverse control channel without
power over coax), or larger high-frequency surface-
mount ceramic capacitors, with sufficient voltage rating
to withstand a short to battery, to pass the lower
speed reverse control-channel signal. Use capacitors
with a case size less than 3.2mm x 1.6mm to have lower
parasitic effects to the high-speed signal.
Internal Input Pulldowns
The control and configuration inputs (except three-level
inputs) include a pulldown resistor to GND. External
pulldown resistors are not needed.
Power-Supply Circuits and Bypassing
The deserializers use an AVDD18 and DVDD18 of 1.7V
to 1.9V and an AVDD3 of 3.0V to 3.6V. All single-ended
inputs and outputs except for the serial input derive power
from an IOVDD of 1.7V to 3.6V that scale with IOVDD.
Proper voltage-supply bypassing is essential for high-
frequency circuit stability.
2
Choosing I C/UART Pullup Resistors
2
I C and UART open-drain lines require a pullup resistor
to provide a logic-high level. There are tradeoffs between
power dissipation and speed, and a compromise may
be required when choosing pullup resistor values. Every
device connected to the bus introduces some capacitance
Power-Supply Table
2
even when the device is not in operation. I C specifies
300ns rise times (30% to 70%) for fast mode, which
is defined for data rates up to 400kbps (see the I C
Power-supply currents shown in the DC Electrical
2
Characteristics table is measured at V
= 3.6V. If
IOVDD
specifications in the AC Electrical Characteristics table
for details). To meet the fast-mode rise-time requirement,
using a different IOVDD voltage, the IOVDD worst-case
supply current will vary. HDCP operation (MAX9290 only)
draws additional current. This is shown in Table 24.
choose the pullup resistors so that rise time t = 0.85
R
x R
x C
< 300ns. The waveforms are not
PULLUP
BUS
Cables and Connectors
Interconnect for CML typically has
recognized if the transition time becomes too slow. The
device supports I C/UART rates up to 1Mbps.
a differential
2
impedance of 100Ω. Use cables and connectors that
have matched differential impedance to minimize imped-
ance discontinuities. Coax cables typically have a
characteristic impedance of 50Ω, contact the factory for
75Ω operation). Table 24 lists the suggested cables and
connectors used in the GMSL link.
AC-Coupling
AC-coupling isolates the receiver from DC voltages up
to the voltage rating of the capacitor. Capacitors at the
serializer output and at the deserializer input are needed
for proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Board Layout
Separate LVCMOS logic signals and CML/coax high-
speed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100Ω differential characteristic impedance for
STP. The trace dimensions depend on the type of trace
used (microstrip or stripline). Note that two 50Ω PCB
traces do not have 100Ω differential impedance when
brought close together—the impedance goes down when
the traces are brought closer. Use a 50Ω trace for the
single-ended output when driving coax.
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of
transmitted symbols cause signal transitions to start from
different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
(R ), the CML/coax driver termination resistor (R ),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
TR
TD
Route the PCB traces for differential CML channel in
parallel to maintain the differential characteristic imped-
ance. Avoid vias. Keep PCB traces that make up a
differential pair equal length to avoid skew within the
differential pair.
(R
+ R ))/4. R
and R
are required to match the
TR
TD
TR
TD
transmission line impedance (usually 100Ω differential,
50Ω single ended). This leaves the capacitor selection to
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3.12Gbps GMSL Deserializers
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Table 22. Line-Fault Mapping
REGISTER
ADDRESS
BITS
NAME
VALUE
LINE-FAULT TYPE
00
01
10
11
00
01
10
11
Negative cable wire shorted to supply voltage
Negative cable wire shorted to ground
Normal operation
D[3:2]
LFNEG
Negative cable wire disconnected
Positive cable wire shorted to supply voltage
Positive cable wire shorted to ground
Normal operation
0x76
D[1:0]
LFPOS
Positive cable wire disconnected
Table 23. Additional Supply Current from HDCP (MAX9290 Only)
PIXEL CLOCK
MAXIMUM HDCP CURRENT
(MHz)
(mA)
16.6
33.3
36.6
66.6
104
6
9
9
12
18
Table 24. Suggested Connectors and Cables for GMSL
VENDOR
Rosenberger
Rosenberger
Nissei
CONNECTOR
59S2AX-400A5-Y
D4S10A-40ML5-Z
GT11L-2S
CABLE
Dacar 302
TYPE
Coax
STP
Dacar 535-2
F-2WME AWG28
A-BW-Lxxxxx
STP
JAE
MX38-FF
STP
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ESD Protection
R
330Ω
D
ESD tolerance is rated for Human Body Model, IEC
61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial link inputs are rated for ISO 10605
ESD protection and IEC 61000-4-2 ESD protection. All
pins are tested for the Human Body Model. The Human
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
S
STORAGE
CAPACITOR
150pF
SOURCE
Body Model discharge components are C = 100pF and
S
R
= 1.5kΩ (Figure 59). The IEC 61000-4-2 discharge
D
components are C = 150pF and R = 330Ω (Figure 60).
S
D
The ISO 10605 discharge components are C = 330pF
S
Figure 60. IEC 61000-4-2 Contact Discharge ESD Test Circuit
and R = 2kΩ (Figure 61).
D
R
D
R
D
1MΩ
1.5ꢀΩ
2ꢀΩ
CHARGE-CURRENT- DISCHARGE
CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR
RESISTANCE
LIMIT RESISTOR
RESISTANCE
HIGH-
VOLTAGE
DC
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C
S
C
S
330pF
STORAGE
CAPACITOR
STORAGE
CAPACITOR
100pF
SOURCE
SOURCE
Figure 59. Human Body Model ESD Test Circuit
Figure 61. ISO 10605 Contact Discharge ESD Test Circuit
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Table 25. Register Table
REGISTER
ADDRESS
DEFAULT
BITS
NAME
VALUE
FUNCTION
VALUE
XX00XX0
0
Serializer device address (power-up default
value depends on latched address pin level).
D[7:1]
D0
SERID
—
XXXXXXX
0x00
0
Reserved
Deserializer device address (power-up default
value depends on latched address pin level).
D[7:1]
DESID
XXXXXXX
XX01XXX
0x01
0
1
Normal operation
D0
CFGBLOCK
—
0
Registers 0x00 to 0x1F and 0x60 to 0x67 are
read only.
D[7:6]
00
0
Reserved
00
WS, SCK configured as output (deserializer-
sourced clock).
D5
AUDIOMODE
0
WS, SCK configured as input (system-sourced
clock).
1
0x02
0x03
2
0
Disable I S/TDM channel.
D4
AUDIOEN
1
2
1
1111
Enable I S/TDM channel.
D[3:0]
D[7:0]
—
—
Reserved
1111
00000000
0
Reserved
00000000
LOCK output is low.
0
D7
D6
D5
LOCKED
—
(Read only)
1
0
0
1
LOCK output is high.
Reserved
0
0
Disable PRBS test.
Enable PRBS test.
PRBSEN
Normal mode (power-up default value depends
on CDS and MS pin value at power-up).
0
1
D4
SLEEP
0, 1
01
Activate sleep mode (power-up default value
depends on CDS and MS pin value at power-up).
2
Local control channel uses I C when
00
I2CSEL = 0.
0x04
D[3:2]
INTTYPE
Local control channel uses UART when
I2CSEL = 0.
01
10, 11
0
Local control channel disabled.
Disable reverse control channel to serializer
(sending).
D1
REVCCEN
FWDCCEN
1
1
Enable reverse control channel to serializer
(sending).
1
0
1
Disable forward control channel from serializer
(receiving)
D0
Enable forward control channel from serializer
(receiving).
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
2
I C conversion sends the register address
0
2
when converting UART-to-I C.
D7
I2CMETHOD
2
0
Disable sending of I C register address when
2
1
converting UART-to-I C (command-byte-only
mode).
7.5MHz equalizer highpass filter cutoff
frequency.
00
01
10
11
3.75MHz equalizer highpass filter cutoff
frequency
D[6:5]
HPFTUNE
PDEQ
01
2.5MHz equalizer highpass filter cutoff
frequency.
1.87MHz equalizer highpass filter cutoff
frequency.
0
1
Enable equalizer.
D4
0
Disable equalizer.
0000
2.1dB equalizer-boost gain.
0x05
0001
0010
0011
2.8dB equalizer-boost gain.
3.4dB equalizer-boost gain.
4.2dB equalizer-boost gain.
5.2dB equalizer-boost gain. Power-up default
when EQS is high.
0100
0101
0110
0111
1000
6.2dB equalizer-boost gain.
7dB equalizer-boost gain.
8.2dB equalizer-boost gain.
9.4dB equalizer-boost gain.
D[3:0]
EQTUNE
0100,1001
10.7dB equalizer-boost gain. Power-up default
when EQS is low.
1001
1010
1011
11XX
11.7dB equalizer-boost gain.
13dB equalizer-boost gain.
Do not use.
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0
Device uses standard PRBS test.
Device uses MAX9271/MAX9273-compatible
PRBS test (for use with the MAX9271/
MAX9273 only).
D7
PRBSTYPE
0
1
Do not automatically reset error registers and
outputs.
0
1
0
1
D6
AUTORST
DISGPI
0
0
Automatically reset DECERR register 1µs after
ERR asserts.
Enable GPI-to-GPO signal transmission to
serializer.
D5
Disable GPI-to-GPO signal transmission to
serializer.
0x06
0
GPI input is low.
GPI input is high.
Set GPIO1 to low.
Set GPIO1 to high.
GPIO1 input is low.
GPIO1 input is high.
Set GPIO0 to low.
Set GPIO0 to high.
GPIO0 input is low.
GPIO0 input is high.
Reserved
0
D4
D3
D2
D1
GPIIN
(Read only)
1
0
GPIO1OUT
GPIO1IN
1
1
0
0
(Read only)
1
0
GPIO0OUT
1
1
0
1
0
D0
GPIO0IN
—
(Read only)
0x07
D[7:0]
01010100
01010100
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
D[7:5]
—
001
Reserved
001
00
D18/D19 assigned to HS/VS .
D14/D15 assigned to HS/VS (for use with the
MAX9271).
01
1X
D[4:3]
HVSRC
00
D0/D1 assigned to HS/VS (D[19:2] shifted to
D[17:0]). For use with the MAX9271/MAX9273
with H/V inversion).
Enable DE glitch filter. Power-up default when
BWS = high or low.
0
1
0
1
0
1
D2
D1
D0
DISDEFILT
DISVSFILT
DISHSFILT
X
X
X
0x08
Disable DE glitch filter. Power-up default when
BWS = open.
Enable VS glitch filter. Power-up default when
BWS = high or low.
Disable VS glitch filter. Power-up default when
BWS = open.
Enable HS glitch filter. Power-up default when
BWS = high or low.
Disable HS glitch filter. Power-up default when
BWS = open.
0
Normal CNTL3 operation.
CNTL3 outputs VSYNC.
Automatic pixel count disabled.
Automatic pixel count enabled.
Reserved
D7
D6
VSYNCOUT
AUTOPPL
0
0
1
0
0x09
1
D[5:0]
D[7:0]
D[7:0]
D[7:0]
—
—
000000
00010XXX
00100000
000000
00010XXX
00100000
00000000
0x0A
0x0B
0x0C
Reserved
—
Reserved
ERRTHR
XXXXXXXX Error threshold for decoding errors.
00000000
(Read only)
0x0D
0x0E
D[7:0]
D[7:0]
DECERR
XXXXXXXX Decoding error counter.
00000000
(Read only)
PRBSERR
XXXXXXXX PRBS error counter.
0x0F
0x10
D[7:0]
D[7:0]
—
—
XXXXXXXX Reserved
XXXXXXXX Reserved
(Read only)
(Read only)
High-immunity reverse channel mode uses
500kbps bit rate.
0
D7
REVFAST
—
0
0x11
High-immunity reverse channel mode uses
1Mbps bit rate.
1
D[6:0]
0100010
Reserved
0100010
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
0
1
MCLK derived from PCLKOUT. See Table 9.
MCLK derived from internal oscillator.
MCLK disabled.
D7
MCLKSRC
0
0x12
0000000
XXXXXXX
0X000000
0
D[6:0]
D[7:0]
MCLKDIV
—
0000000
MCLK divider.
0x13
Reserved
0X000000
Normal VSYNC operation.
D7
D6
D5
INVVS
INVHS
INVDE
0
0
0
1
0
1
0
1
Invert VSYNC.
Normal HSYNC operation.
Invert HSYNC.
Normal DE operation.
Invert DE.
High data rate mode. Power-up default when
DRS pin is low (transitions on the DRS pin
override the DRS bit setting).
0
D4
DRS
0, 1
0x14
Low data rate mode. Power-up default when
DRS pin is high (transitions on the DRS pin
override the DRS bit setting).
1
0
1
0
1
0
0
1
Normal parallel output driver current.
Boosted parallel output driver current.
Enable remote wake-up.
Disable remote wake-up.
Reserved
D3
DCS
0
D2
D1
D0
DISRWAKE
—
0
0
0
Drive INTOUT low.
INTOUT
Drive INTOUT high.
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
INTOUT pin output controlled by INTOUT bit
above.
0
D7
AUTOINT
1
Writes to any AVINFO bytes sets INTOUT to
high. Reads to any AVINFO bytes sets INTOUT
to low.
1
Disable HS/VS tracking (power-up default value
depends on state of BWS input value at power-up).
0
1
0
1
D6
HVTREN
DETREN
0, 1
0, 1
Enable HS/VS tracking (power-up default value
depends on state of BWS input value at power-up).
Disable DE tracking (power-up default value
depends on state of BWS input value at power-up).
0x15
D5
Enable DE tracking (power-up default value
depends on state of BWS input value at power-up).
0
1
Partial periodic HS/VS and DE tracking.
Partial and full periodic HS/VS and DE tracking.
Reserved
D4
D[3:2]
D1
HVTRMODE
—
1
00
0
00
0
MCLK output operates normally.
WS is output from MCLK (MCLK mirrors WS).
MCLK output on DOUT28/CNTL2.
MCLK output on ADD0/CNTL0.
MCLKWS
1
0
D0
MCLKPIN
HIGHIMM
0
1
Legacy reverse control channel mode (power-
up default value depends on HIM/CNTL1 at
power-up).
0
D7
0, 1
0x16
High-immunity reverse control channel mode
(power-up default value depends on HIM/
CNTL1 at power-up).
1
D[6:0]
D[7:0]
D[7:1]
D0
—
—
1011010
Reserved
Reserved
1011010
0x17
0x18
000XXXXX
000XXXXX
2
I2CSRCA
—
XXXXXXX
I C address translator source A.
0000000
0
Reserved
0
2
D[7:1]
D0
I2CDSTA
—
XXXXXXX
I C address translator destination A.
0000000
0x19
0x1A
0x1B
0
Reserved
0
2
D[7:1]
D0
I2CSRCB
—
XXXXXXX
I C address translator source B.
0000000
0
XXXXXXX
0
Reserved
0
0000000
0
2
D[7:1]
D0
I2CDSTB
—
I C address translator destination B.
Reserved
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Acknowledge not generated when forward
channel is not available.
0
D7
I2CLOCACK
1
2
2
I C to I C-slave generates local acknowledge
when forward channel is not available.
1
2
00
01
10
11
352ns/117ns I C setup/hold time.
2
469ns/234ns I C setup/hold time.
D[6:5]
I2CSLVSH
01
2
938ns/352ns I C setup/hold time.
2
1046ns/469ns I C setup/hold time.
2
2
8.47kbps (typ) I C to I C-master bit-rate
setting.
000
001
010
2
2
28.3kbps (typ) I C to I C-master bit-rate
setting.
0x1C
2
2
84.7kbps (typ) I C to I C-master bit-rate
setting.
D[4:2]
I2CMSTBT
101
2
2
011
100
101
110
111
00
105kbps (typ) I C to I C-master bit-rate setting.
2
2
173kbps (typ) I C to I C-master bit-rate setting.
2
2
339kbps (typ) I C to I C-master bit-rate setting.
2
2
533kbps (typ) I C to I C-master bit-rate setting.
2
2
837kbps (typ) I C to I C-master bit-rate setting.
2
2
64µs (typ) I C to I C-slave remote timeout.
2
2
01
256µs (typ) I C to I C-slave remote timeout.
D[1:0]
I2CSLVTO
10
2
2
10
1024µs (typ) I C to I C-slave remote timeout.
2
2
11
No I C to I C-slave remote timeout.
D[7:3]
—
00000
Reserved
00000
0
Audio FIFO repeats last audio word when FIFO
is empty.
0
D2
AUDUFBEH
Audio FIFO outputs all zeroes when FIFO is
empty.
1
0x1D
0x1E
0
1
0
1
Do not invert SCK at output.
Invert SCK at output.
D1
INVSCK
INVWS
0
0
Do not invert WS at output.
Invert WS at output.
D0
Device identifier
(MAX9288 = 0x2A)
(MAX9290 = 0x2C)
00101XX0
(Read only)
D[7:0]
ID
00101XX0
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D[7:5]
D4
NAME
—
VALUE
FUNCTION
000
(Read only)
000
Reserved
0x1F
0
1
Not HDCP capable (MAX9288).
HDCP capable (MAX9290).
Device revision.
CAPS
(Read only)
D[3:0]
D[7:0]
REVISION
AVINFO
XXXX
(Read only)
0x40 to 0x59
XXXXXXXX Video/audio format/status/information bytes.
All zeroes
00
01
10
11
CSI-2 outputs with ID as virtual channel 0.
CSI-2 outputs with ID as virtual channel 1.
CSI-2 outputs with ID as virtual channel 2.
CSI-2 outputs with ID as virtual channel 3.
D[7:6]
D5
VC
00
0
RAW8/10/12 mode uses single load. YUV422-
8b/10b uses muxed mode.
0
1
INPUTBW
OLDI
RAW8/10/12 mode uses double load. YUV422-
8b/10b uses normal mode.
RGB888 uses VESA format
(MSB to LSB bit order = 7, 6, 5, 4, 3, 2, 1, 0).
0
D4
1
RGB888 uses oLDI format
(MSB to LSB bit order = 5, 4, 3, 2, 1, 0, 7, 6).
1
CSI-2 output uses RGB888 (Power-on
default).
0x60
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
11XX
CSI-2 output uses RGB565.
CSI-2 output uses RGB666.
CSI-2 output uses YUV 422 8-bit.
CSI-2 output uses YUV 422 10-bit.
CSI-2 output uses RAW8.
D[3:0]
DATATYPE
0000
CSI-2 output uses RAW10.
CSI-2 output uses RAW12.
CSI-2 output uses RAW14.
CSI-2 output uses user defined generic 24-bit (0x30).
CSI-2 output uses user defined YUV422 12-bit (0x30).
CSI-2 output uses user defined generic 8-bit (0x31).
Do not use.
Low byte of pixel count. Set this register
according to the pixel count per line.
0x61
0x62
D[7:0]
D[7:0]
PIXELCNTLOW
PIXELCNTHIGH
XXXXXXXX
XXXXXXXX
00000000
00000000
High byte of pixel count. Set this register
according to the pixel count per line.
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Drive clock lane LP00 for 64ns before starting
HS transmission
00
01
10
11
00
01
10
Drive clock lane LP00 for 72ns before starting
HS transmission.
D[7:6]
TCLKPREPARE
00
Drive clock lane LP00 for 80ns before starting
HS transmission.
Drive clock lane LP00 for 88ns before starting
HS transmission.
0x63
Drive HS0 state for 360ns + 16-24UI before
starting the clock.
Drive HS0 state for 720ns + 16-24UI before
starting the clock.
D[5:4]
D[3:0]
TCLKZERO
00
Drive HS0 state for 1.08µs + 16-24UI before
starting the clock.
Drive HS0 state for 1.44µs + 16-24UI before
starting the clock.
11
—
0000
Reserved
0000
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Drive data lane LP00 for 64ns +4UI before
starting HS transmission.
00
01
1X
00
01
10
11
00
01
10
11
Drive data lane LP00 for 72ns + 4UI before
starting HS transmission.
D[7:6]
THSPREPARE
00
Drive data lane LP00 for 80ns + 4UI before
starting HS transmission.
Drive HS0 state for 160ns + 24 - 32UI before
transmitting the sync sequence.
Drive HS0 state for 176ns + 24 - 32UI before
transmitting the sync sequence.
D[5:4]
THSZERO
00
Drive HS0 state for 200ns + 24 - 32UI before
transmitting the sync sequence.
Drive HS0 state for 240ns + 24 - 32UI before
transmitting the sync sequence.
0x64
Drive HSTRAIL state for 64ns + 8UI after the
last payload data bit of a HS transmission burst.
Drive HSTRAIL state for 80ns + 8UI after the
last payload data bit of a HS transmission burst.
D[3:2]
D[1:0]
THSTRAIL
00
00
Drive HSTRAIL state for 96ns + 8UI after the
last payload data bit of a HS transmission burst.
Drive HSTRAIL state for 120ns + 8UI after the
last payload data bit of a HS transmission burst.
00
01
10
11
0
64ns LPTX period length.
128ns LPTX period length.
192ns LPTX period length.
256ns LPTX period length
Reserved
TLPX
D7
D6
—
0
0
0
Normal DE operation.
HS input is the DE source.
Data lane D0 enabled.
Data lanes D0, D1 enabled.
Data lanes D0–D2 enabled.
Data lanes D0–D3 enabled.
Reserved
DESEL
1
00
01
10
11
0111
0x65
D[5:4]
D[3:0]
DATALANEN
—
01
0111
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3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
NAME
VALUE
FUNCTION
Data-byte 3 maps to lane 0 (data mapping
should be exclusive).
00
D[7:6]
D3LANEMAP
01
10
11
Data-byte 3 maps to lane 1.
Data-byte 3 maps to lane 2.
Data-byte 3 maps to lane 3.
11
Data byte 2 maps to lane 0 (data mapping
should be exclusive).
00
D[5:4]
D[3:2]
D[1:0]
D2LANEMAP
D1LANEMAP
D0LANEMAP
01
10
11
Data byte 2 maps to lane 1.
Data byte 2 maps to lane 2.
Data byte 2 maps to lane 3.
10
01
00
0x66
Data byte 1 maps to lane 0 (data mapping
should be exclusive).
00
01
10
11
Data byte 1 maps to lane 1.
Data byte 1 maps to lane 2
Data byte 1 maps to lane 3.
Data byte 0 maps to lane 0 (data mapping
should be exclusive).
00
01
Data byte 0 maps to lane 1.
Data byte 0 maps to lane 2.
Data byte 0 maps to lane 3.
Reserved
10
11
0x67
0x68
0x69
0x6A
D[7:0]
D[7:0]
D[7:0]
D[7:0]
—
—
—
—
00000000
11001000
00000000
00000000
00000000
11001000
00000000
00000000
Reserved
Reserved
Reserved
XXXXXXXX
(Read only)
0x72
0x73
0x74
0x75
D[7:0]
D[7:0]
D[7:0]
D[7:0]
D[7:4]
—
—
—
—
—
XXXXXXXX Reserved
XXXXXXXX Reserved
XXXXXXXX Reserved
XXXXXXXX Reserved
XXXXXXXX
(Read only)
XXXXXXXX
(Read only)
XXXXXXXX
(Read only)
0000
(Read only)
0000
Reserved
00
01
10
11
00
01
10
11
Negative cable wire shorted to supply voltage.
Negative cable wire shorted to ground.
Normal operation.
00
D[3:2]
D[1:0]
LFNEG
LFPOS
(Read only)
0x76
Negative cable wire disconnected.
Positive cable wire shorted to supply voltage.
Positive cable wire shorted to ground.
Normal operation.
00
(Read only)
Positive cable wire disconnected.
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3.12Gbps GMSL Deserializers
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Table 25. Register Table (continued)
REGISTER
ADDRESS
DEFAULT
VALUE
BITS
D[7:0]
D[7:0]
NAME
—
VALUE
FUNCTION
0x77
XXXXXXXX
XXXXXXXX
(Read only)
Audio FIFO last overflow/underflow period
(AUDIOMODE = 1 only).
0x78
AUDOUPER
(Read only)
(Read only)
Audio FIFO is in underflow (AUDIOMODE = 1
only).
D7
AUDOU
—
0
00
D[6:5]
00
Reserved
(Read only)
0
No pixels-per-line error.
0
D4
APPLERR
PRBSOK
(Read only)
1
Pixels-per-line error detected. Read to clear.
MAX9271/MAX9273-compatible PRBS test not
completed (or completed without success).
0
0
D3
0x79
(Read only)
MAX9271/MAX9273-compatible PRBS test
completed with success.
1
0
1
0
1
0
1
DE tracking not locked.
DE tracking locked.
VS tracking not locked.
VS tracking locked.
0
D2
D1
D0
DLOCKED
VLOCKED
HLOCKED
(Read only)
0
(Read only)
HS tracking not locked.
HS tracking locked.
0
(Read only)
0x7B
0x7C
D[7:0]
D[7:4]
LUTADDR
—
XXXXXXXX LUT start address for write and read.
00000000
0000
0000
Reserved
0
1
0
1
0
1
0
1
Disable LUT write and read.
Enable LUT write and read.
Disable blue LUT.
Enable blue LUT.
D3
D2
D1
D0
LUTPROG
BLULUTEN
GRNLUTEN
REDLUTEN
0
0
0
0
Disable green LUT.
Enable green LUT.
Disable red LUT.
Enable red LUT.
0x7D
0x7E
0x7F
D[7:0]
D[7:0]
D[7:0]
REDLUT
GREENLUT
BLUELUT
XXXXXXXX Red LUT value (see Table 13).
XXXXXXXX Green LUT value (see Table 13).
XXXXXXXX Blue LUT value (see Table 13).
00000000
00000000
00000000
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3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 26. HDCP Register Table (MAX9290 Only)
REGISTER
ADDRESS
SIZE
(BYTES)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
FUNCTION
0X80 to 0x84
0X85 to 0x86
0X87
5
2
1
8
5
BKSV
RI’
Read only
Read only
Read only
Read/write
Read/write
HDCP receiver KSV.
(Read only)
(Read only)
Link verification response.
Enhanced link verification response.
Session random number.
PJ’
(Read only)
0X88 to 0x8F
0X90 to 0x94
AN
0x0000000000000000
0x0000000000
AKSV
HDCP transmitter KSV.
D7 = PD_HDCP
1 = Power down HDCP circuits
0 = HDCP circuits normal
D[6:4] = Reserved
D3 = GPIO1_FUNCTION
1 = GPIO1 mirrors AUTH_STARTED
0 = Normal GPIO1 operation
D2 = GPIO0_FUNCTION
1 = GPIO0 mirrors ENCRYPTION_
ENABLE
0x95
1
BCTRL
Read/write
0x00
0 = Normal GPIO0 operation
D1 = AUTH_STARTED
1 = Authentication started (triggered by
write to AKSV)
0 = Authentication not started
D0 = ENCRYPTION_ENABLE
1 = Enable encryption
0 = Disable encryption
D[7:2] = Reserved
D1 = NEW_DEV_CONN
1 = Set to 1 if a new connected device is
detected.
0 = Set to 0 if no new device is
connected.
0x96
1
BSTATUS
Read/write
0x00
D0 = KSV_LIST_READY
1 = Set to 1 if KSV list and BINFO is
ready
0 = Set to 0 if KSV list or BINFO is not
ready.
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3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
Table 26. HDCP Register Table (MAX9290 Only)
REGISTER
ADDRESS
SIZE
(BYTES)
READ/
WRITE
DEFAULT VALUE
(hex)
NAME
BCAPS
—
FUNCTION
D[7:1] = Reserved
D0 = REPEATER
1 = Set to one if device is a repeater.
0 = Set to zero if device is not a repeater.
0x97
1
Read/write
0x00
0x0000000000000000
(Read only)
0x98 to 0x9F
8
Read only
Reserved
0XA0 to 0xA3
0XA4 to 0xA7
0XA8 to 0xAB
0XAC to 0xAF
0XB0 to 0xB3
4
4
4
4
4
V’.H0
V’.H1
V’.H2
V’.H3
V’.H4
Read/write
Read/write
Read/write
Read/write
Read/write
H0 part of SHA-1 hash value
H1 part of SHA-1 hash value
H2 part of SHA-1 hash value
H3 part of SHA-1 hash value
H4 part of SHA-1 hash value
D[15:12] = Reserved
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
D11 = MAX_CASCADE_EXCEEDED
1 = Set to 1 if more than seven cascaded
devices attached.
0 = Set to 0 if seven or fewer cascaded
devices attached.
D[10:8] = DEPTH
Depth of cascaded devices
0XB4 to 0xB5
2
BINFO
Read/write
0x0000
D7 = MAX_DEVS_EXCEEDED
1 = Set to one if more than 14 devices
attached
0 = Set to zero if 14 or fewer devices
attached
D[6:0] = DEVICE_COUNT
Number of devices attached
0xB6
1
GPMEM
—
Read/write
Read only
General-purpose memory byte.
Reserved
0x00
0xB7 to 0xB9
3
0x000000
List of KSVs downstream repeaters and
receivers (maximum of 14 devices).
0xBA to 0xFF
70
KSV_LIST
Read/write
All zero
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3.12Gbps GMSL Deserializers
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Typical Application Circuit
1.8V
1.8V
45.3kΩ
LMN0
49.9Ω
SENSOR
COPROCESSOR
APPLICATIONS
PROCESSOR
SENSOR
4.99kΩ
49.9kΩ
PCLKIN
OUT-
DCLK+/-
0.22µF
0.22µF
RGB888
CSI-2
DOUT0–
DOUT3+/-
DIN0–DIN26
OUT+
IN+
IN-
0.22µF
49.9kΩ
MAX9275
MAX9279
MAX9288
MAX9290
RX/SDA
CDS
RX/SDA
TX/SCL
GPI
TX/SCL
GPO
I2CSEL
CX/TP
CONF0–
CONF3
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
CAMERA APPLICATION
Chip Information
PROCESS: CMOS
Ordering Information
PART
PIN-PACKAGE
HDCP
MAX9288GTM+
48 TQFN-EP*
48 TQFN-EP*
48 SWTQFN-EP*
48 TQFN-EP*
48 TQFN-EP*
48 SWTQFN-EP*
No
No
No
Package Information
MAX9288GTM/V+
MAX9288GTM/VY+
MAX9290GTM+
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
†
Yes
†
MAX9290GTM/V+
MAX9290GTM/VY+**
Yes
†
Yes
Note: All devices operate over the -40°C to +105°C
temperature range.
LAND
PATTERN
NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V Denotes an automotive-qualified part.
SW = Side-wettable package.
*EP = Exposed pad.
**Future product―contact factory for availability.
21-0144
90-0130
90-0130
48 TQFN-EP
T4877+4
21-100045
48 SWTQFN-EP T4877Y+4
†HDCP parts require registration with Digital Content
Protection, LLC.
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3.12Gbps GMSL Deserializers
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Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
3/14
Initial release
—
1, 28, 33, 48,
49, 51–56, 59,
Added simplified diagram, removed Table 1 and renumbered the subsequent tables,
clarified functions, removed future product designations, and corrected typos
66, 67, 69–72,
74–77, 79–82,
84, 85, 86,
1
9/14
88–102
2
3
11/15
3/17
Clarified timing requirements
8, 27, 30, 50
12, 18, 21, 26,
58, 61, 62, 67,
71, 80, 84, 86,
90, 99
Various updates, beginning with AC Electrical Characteristics
Deleted QFND package and added side-wettable TQFN (SWTQFN) to General
Description, Absolute Maximum Ratings, Package Thermal Characteristics, Pin
Configuration, Ordering Information, and Package Information
4
3/18
8/19
1, 8, 18, 102
71, 85, 102
Updated High-Immunity Reverse Control-Channel Mode, Selection of AC-Coupling
Capacitors, and Typical Application Circuit sections
5
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 103
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