MAX9391ETJ [MAXIM]
Anything-to-LVDS Dual 2 x 2 Crosspoint Switches; 任何对LVDS双路，2 x 2交叉点开关
| 型号： | MAX9391ETJ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Anything-to-LVDS Dual 2 x 2 Crosspoint Switches |
| 文件： | 总14页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2829; Rev 1; 7/03
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
General Description
Features
The MAX9390/MAX9391 dual 2 x 2 crosspoint switches
perform high-speed, low-power, and low-noise signal
distribution. The MAX9390/MAX9391 multiplex one of two
differential input pairs to either or both low-voltage differ-
ential signaling (LVDS) outputs for each channel.
Independent enable inputs turn on or turn off each differ-
ential output pair.
ꢀ 1.5GHz Operation with 250mV Differential Output
Swing
ꢀ 2ps
(max) Random Jitter
(RMS)
ꢀ AC Specifications Guaranteed for 150mV
Differential Input
ꢀ Signal Inputs Accept Any Differential Signaling
Standard
Four LVCMOS/LVTTL logic inputs (two per channel) con-
trol the internal connections between inputs and outputs.
This flexibility allows for the following configurations: 2 x 2
crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater.
This makes the MAX9390/MAX9391 ideal for protection
switching in fault-tolerant systems, loopback switching for
diagnostics, fanout buffering for clock/data distribution,
and signal regeneration.
ꢀ LVDS Outputs for Clock or High-Speed Data
ꢀ High-Level Input Fail-Safe Detection (MAX9390)
ꢀ Low-Level Input Fail-Safe Detection (MAX9391)
ꢀ +3.0V to +3.6V Supply Voltage Range
ꢀ LVCMOS/LVTTL Logic Inputs Control Signal
Routing
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the common-
mode voltage exceeds the specified range. The
MAX9390 provides high-level input fail-safe detection
for LVDS, HSTL, and other GND-referenced differential
inputs. The MAX9391 provides low-level input fail-safe
Ordering Information
PART
MAX9390EHJ
MAX9390ETJ*
MAX9391EHJ
MAX9391ETJ*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
32 Thin QFN
32 TQFP
detection for LVPECL, CML, and other V -referenced
CC
differential inputs.
32 Thin QFN
Ultra-low 82ps
(max) pseudorandom bit sequence
(P-P)
*Future product—contact factory for availability.
(PRBS) jitter ensures reliable communications in high-
speed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switch-
ing performance guarantees 1.5GHz operation and less
than 65ps (max) skew between channels.
Pin Configurations
TOP VIEW
LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS outputs drive
100 loads. The MAX9390/MAX9391 are offered in a
32-pin TQFP and 5mm x 5mm thin QFN package with
exposed paddle and operate over the extended tem-
perature range (-40°C to +85°C).
32 31 30 29 28 27 26 25
ENB1
OUTB1
OUTB1
GND
1
2
3
4
5
6
7
8
24 V
CC
OUTA0
23
22 OUTA0
21 ENA0
20 GND
Also refer to the MAX9392/MAX9393 with flow-through
pinout.
MAX9390
MAX9391
ENB0
Applications
19 OUTA1
18 OUTA1
17 ENA1
OUTB0
OUTB0
High-Speed Telecom/Datacom Equipment
Central-Office Backplane Clock Distribution
DSLAM
V
CC
Protection Switching
9
10 11 12 13 14 15 16
Fault-Tolerant Systems
TQFP
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND...........................................................-0.3V to +4.1V
Junction-to-Case Thermal Resistance
IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _,
_SEL_ to GND.........................................-0.3V to (V
IN_ _ to IN_ _.......................................................................... 3V
Short-Circuit Duration (OUT_ _, OUT_ _) ...................Continuous
32-Pin 5mm x 5mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection (Human Body Model)
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
32-Pin QFP (derate 13.1mW/°C
(IN_ _, IN_ _, OUT_ _, OUT_ _, EN_ _, SEL_ _) ................ 2kV
Soldering Temperature (10s)...........................................+300°C
above +70°C).............................................................1047mW
32-Pin 5mm x 5mm Thin QFN (derate 21.3mW/°C
above +70°C).............................................................1702mW
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin QFP..............................................................+76.4°C/W
32-Pin 5mm x 5mm Thin QFN....................................+47°C/W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, R = 100
1%, EN_ _ = V , V
= 0.05V to (V
- 0.6V) (MAX9390), V
= 0.6V to (V
- 0.05V)
CC
CC
L
CC
CM
CC
CM
(MAX9391) T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, |V | = 0.2V, V
= +1.2V, T = +25°C.)
CM A
A
CC
ID
(Notes 1, 2, and 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS/LVTTL INPUTS (EN_ _, _SEL_)
Input High Voltage
V
2.0
0
V
V
IH
CC
Input Low Voltage
V
0.8
20
10
V
IL
Input High Current
I
V
V
= +2.0V to V
CC
0
µA
µA
IH
IN
IN
Input Low Current
I
= 0 to +0.8V
0
IL
IN_ _
DIFFERENTIAL INPUTS (IN_ _,
)
Differential Input Voltage
V
V
> 0 and V
< V , Figure 1
0.1
0.05
0.6
3.0
V
V
ID
ILD
IHD
CC
MAX9390
MAX9391
MAX9390
MAX9391
V
- 0.6
CC
Input Common-Mode Range
Input Current
V
CM
V
- 0.05
+10
CC
|V | < 3.0V
ID
-75
-10
I
I
,
IN_ _
µA
IN_ _
|V | < 3.0V
ID
+100
450
50
OUT__
LVDS OUTPUTS (OUT_ _,
)
Differential Output Voltage
V
R = 100 , Figure 2
L
250
350
1.0
mV
mV
V
OD
Change in Magnitude of V
Between Complementary Output
States
OD
V
Figure 2
Figure 2
Figure 2
OD
OS
Offset Common-Mode Voltage
V
1.125
1.25
1.0
1.375
50
Change in Magnitude of V
Between Complementary Output
States
OS
V
mV
OS
2
_______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3.0V to +3.6V, R = 100
1%, EN_ _ = V , V
= 0.05V to (V
- 0.6V) (MAX9390), V
= 0.6V to (V
- 0.05V)
CC
CC
L
CC
CM
CC
CM
(MAX9391) T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= +3.3V, |V | = 0.2V, V
= +1.2V, T = +25°C.)
CM A
A
CC
ID
(Notes 1, 2, and 3)
PARAMETER
SYMBOL
|I
CONDITIONS
MIN
TYP
30
MAX
40
UNITS
V
V
or V
= 0
= 0
OUT_ _
OUT_ _
OUT_ _
Output Short-Circuit Current
(Either Output Shorted to GND)
V
= 100mV
ID
|
mA
OS
(Note 4)
= V
= V
18
24
OUT_ _
Output Short-Circuit Current
(Outputs Shorted Together)
V
= 100mV, V
ID OUT_ _
OUT_ _
|I
OSB
|
5.0
12
mA
(Note 4)
SUPPLY CURRENT
R = 100 , EN_ _ = V
68
68
98
98
L
CC
Supply Current
I
CC
mA
R = 100 , EN_ _ = V , switching at
L
CC
670MHz (1.34Gbps)
AC ELECTRICAL CHARACTERISTICS
(V
= +3.0V to +3.6V, f < 1.34GHz, t
= t
= 125ps, R = 100
1%, |V | > 150mV, V
= +0.075V to (V
- 0.6V)
CC
CC
IN
R_IN
F_IN
L
ID
CM
(MAX9390 only), V
= +0.6V to (V
- 0.075V) (MAX9391 only), EN_ _ = V , T = -40°C to +85°C, unless otherwise noted. Typical
CM
CC CC A
values are at V
= +3.3V, |V | = 0.2V, V
= +1.2V, f = 1.34GHz, T = +25°C.) (Note 5)
CC
ID
CM
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
_SEL_ to Switched Output
t
Figure 3
Figure 4
1.1
ns
SWITCH
Disable, Time to Differential
Output Low
t
1.7
1.7
ns
ns
PHD
Enable, Time to Differential
Output High
t
Figure 4
PDH
MAX
Switching Frequency
f
V
> 250mV
1.50
294
286
2.20
409
402
GHz
ps
OD
Low-to-High Propagation Delay
High-to-Low Propagation Delay
t
Figures 1, 5
Figures 1, 5
565
530
PLH
PHL
t
ps
Pulse Skew |t
- t
|
t
Figures 1, 5 (Note 6)
Figures 5, 6 (Note 7)
7
97
65
ps
ps
ps
PLH PHL
SKEW
Output-to-Output Skew
t
10
CCS
Output Low-to-High Transition
Time (20% to 80%)
t
Figures 1, 5; f = 100MHz
112
112
153
185
R
IN
Output High-to-Low Transition
Time (80% to 20%)
t
F
Figures 1, 5; f = 100MHz
153
185
ps
IN
Added Random Jitter
t
f
= 1.34GHz, clock pattern (Note 8)
2
ps
(RMS)
RJ
IN_ _
Added Deterministic Jitter
t
1.34Gbps, 223 - 1 PRBS (Note 8)
55
82
ps
(P-P)
DJ
Note 1: Measurements obtained with the device in thermal equilibrium. All voltages referenced to GND except V , V , and
V
OD
.
ID OD
Note 2: Current into the device defined as positive. Current out of the device defined as negative.
Note 3: DC parameters tested at T = +25°C and guaranteed by design and characterization for T = -40°C to +85°C.
A
A
Note 4: Current through either output.
Note 5: Guaranteed by design and characterization. Limits set at 6 sigma.
Note 6: t
is the magnitude difference of differential propagation delays for the same output over same conditions. t
=
SKEW
SKEW
|t
- t
|.
PHL PLH
Note 7: Measured between outputs of the same device at the signal crossing points for a same-edge transition, under the same
conditions.
Note 8: Device jitter added to the differential input signal.
_______________________________________________________________________________________
3
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Typical Operating Characteristics
(V
= +3.3V, |V | = 0.2V, V
= +1.2V, f = 1.34GHz, T = +25°C.)
CM IN A
CC
ID
OUTPUT RISE AND FALL TIMES
vs. TEMPERATURE
OUTPUT AMPLITUDE
vs. FREQUENCY
SUPPLY CURRENT
vs. TEMPERATURE
180
400
350
300
250
200
150
100
50
82
f
= 100MHz
IN
78
74
70
170
160
150
140
130
120
t
F
V
CC
= +3.6V
t
R
66
62
58
54
V
= +3.3V
60
CC
V
= +3V
CC
0
-40
-15
10
35
60
85
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
FREQUENCY (GHz)
-40
-15
10
35
85
TEMPERATURE ( C)
TEMPERATURE ( C)
MAX9391
DIFFERENTIAL INPUT CURRENT
vs. TEMPERATURE
MAX9390
DIFFERENTIAL INPUT CURRENT
vs. TEMPERATURE
PROPAGATION DELAY
vs. TEMPERATURE
450
440
430
420
410
400
390
380
370
360
350
80
70
60
50
40
30
20
10
0
10
5
0
V
= 3V
IN
V
= 3.2V
IN
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
V
= -0.1V
IN
V
= 0.3V
IN
-10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
MAX9391
DIFFERENTIAL INPUT CURRENT vs. V
MAX9390 INPUT CURRENT vs. V
ILD
IHD
80
70
60
50
40
30
20
10
0
10
5
IN_ _ OR
IN_ _ = GND
IN_ _ OR
IN_ _ = V
V
= +3.6V
CC
CC
0
-5
V
CC
= +3V
-10
-15
-20
-25
-30
-35
-40
-45
-50
V
= +3.6V
CC
V
CC
= +3V
-10
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
(V)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
(V)
V
IHD
V
ILD
4
_______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Pin Description
PIN
NAME
FUNCTION
B1 Output Enable. Drive ENB1 high to enable the B1 LVDS outputs. An internal 435kΩ resistor pulls ENB1
low when unconnected.
1
ENB1
B1 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTB1 and OUTB1 at the
receiver inputs to ensure proper operation.
2
3
OUTB1
OUTB1
GND
B1 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTB1 and OUTB1 at the
receiver inputs to ensure proper operation.
4, 9,
20, 25
Ground
B0 Output Enable. Drive ENB0 high to enable the B0 LVDS outputs. An internal 435kΩ resistor pulls ENB0
low when unconnected.
5
6
7
ENB0
B0 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTB0 and OUTB0 at the
receiver inputs to ensure proper operation.
OUTB0
OUTB0
B0 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTB0 and OUTB0 at the
receiver inputs to ensure proper operation.
8, 13,
24, 29
Power-Supply Input. Bypass each V
bypass capacitors as close to the device as possible, with the 0.01µF capacitor closest to the device.
to GND with 0. 1µF and 0.01µF ceramic capacitors. Install both
CC
V
CC
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V pulls
CC
10
11
12
14
15
16
INB0
INB0
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
CC
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).
Input Select for B0 Output. Selects the differential input to reproduce at the B0 differential outputs. Connect
BSEL0 to GND or leave open to select the INB0 (INB0) set of inputs. Connect BSEL0 to V
INB1 (INB1) set of inputs. An internal 435kΩ resistor pulls BSEL0 low when unconnected.
to select the
BSEL0
INB1
CC
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V pulls
CC
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
CC
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).
INB1
Input Select for B1 Output. Selects the differential input to reproduce at the B1 differential outputs. Connect
BSEL1
BSEL1 to GND or leave open to select the INB0 (INB0) set of inputs. Connect BSEL1 to V
to select the
CC
INB1 (INB1) set of inputs. An internal 435kΩ resistor pulls BSEL1 low when unconnected.
_______________________________________________________________________________________
5
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Pin Description (continued)
PIN
NAME
FUNCTION
A1 Output Enable. Drive ENA1 high to enable the A1 LVDS outputs. An internal 435kΩ resistor pulls ENA1
low when unconnected.
17
ENA1
A1 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTA1 and OUTA1 at the
receiver inputs to ensure proper operation.
18
19
21
22
23
OUTA1
OUTA1
ENA0
A1 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTA1 and OUTA1 at the
receiver inputs to ensure proper operation.
A0 Output Enable. Drive ENA0 high to enable the A0 LVDS outputs. An internal 435kΩ resistor pulls ENA0
low when unconnected.
A0 LVDS Inverting Output. Connect a 100Ω termination resistor between OUTA0 and OUTA0 at the
receiver inputs to ensure proper operation.
OUTA0
OUTA0
A0 LVDS Noninverting Output. Connect a 100Ω termination resistor between OUTA0 and OUTA0 at the
receiver inputs to ensure proper operation.
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
CC
26
27
28
30
31
INA0
INA0
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V pulls
CC
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
unconnected (MAX9391).
Input Select for A0 Output. Selects the differential input to reproduce at the A0 differential outputs. Connect
ASEL0 to GND or leave open to select the INA0 (INA0) set of inputs. Connect ASEL0 to V
INA1 (INA1) set of inputs. An internal 435kΩ resistor pulls ASEL0 low when unconnected.
to select the
ASEL0
INA1
CC
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Noninverting Input. An internal 128kΩ resistor to V
CC
pulls the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low
when unconnected (MAX9391).
LVDS/HSTL (MAX9390) or LVPECL/CML (MAX9391) Inverting Input. An internal 128kΩ resistor to V pulls
CC
the input high when unconnected (MAX9390). An internal 68kΩ resistor to GND pulls the input low when
INA1
unconnected (MAX9391).
Input Select for A1 Output. Selects the differential input to reproduce at the A1 differential outputs. Connect
32
ASEL1
EP
ASEL1 to GND or leave open to select the INA0 (INA0) set of inputs. Connect ASEL1 to V
INA1 (INA1) set of inputs. An internal 435kΩ resistor pulls ASEL1 low when unconnected.
to select the
CC
—
Exposed Paddle (QFN Package Only). Connect to GND for optimal thermal and EMI characteristics.
6
_______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
V
V
V
IN_ _
IHD
V
t
= 0
V
= 0
ID
ID
V
ILD
IN_ _
OUT_ _
V
OD
OS
t
PHL
1/4 MAX9390/MAX9391
PLH
V
V
OUT_ _
R /2
L
V
OD
= 0
V
OD
= 0
IN_ _
IN_ _
V
OUT_ _
R /2
L
80%
= 0
80%
50%
EN_ _ = HIGH
= V - V
IN_ _
V
ID
IN_ _
OUT_ _
50%
20%
V
V
= 0
OD
OD
20%
V
V
=
=
V
- V *
OD
OS
OD
OS
OD
OS
V
- V *
t
t
F
R
V
V
AND V ARE MEASURED WITH V = +100mV
OD
OD
OS ID
* AND V * ARE MEASURED WITH V = -100mV
OS
ID
V
V
= V
- V
ID
IN_ _ IN_ _
= V
- V
OUT_ _
OD
OUT_ _
t
AND t MEASURED FOR ANY COMBINATION OF _SEL0 AND _SEL1.
PHL
PLH
Figure 1. Output Transition Time and Propagation Delay Timing
Diagram
Figure 2. Test Circuit for V and V
OD OS
V
IHD
IN_0
V
V
= 0
= 0
ID
V
ILD
IN_0
V
IHD
IN_1
IN_1
ID
V
ILD
V
V
IH
1.5V
IN_0
1.5V
IL
_SEL_
OUT_ _
OUT_ _
V
OD
= 0
IN_1
IN_0
V
OD
= 0
t
t
SWITCH
SWITCH
EN_0 = EN_1 = HIGH
= V - V
V
ID
IN_ _
IN_ _
Figure 3. Input to Rising/Falling Edge Select and Mux Switch Timing Diagram
_______________________________________________________________________________________
7
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
3V
0
OUT_ _
1.5V
1.5V
V
EN_ _
1/4 MAX9390/MAX9391
C
L
R /2
L
IN_ _
IN_ _
t
t
t
PHD
PDH
V
V
WHEN V = +100mV
ID
OUT_ _
50%
50%
50%
50%
+1.25V
R /2
L
WHEN V = -100mV
OUT_ _
ID
PULSE
GENERATOR
OUT_ _
V
V
WHEN V = -100mV
ID
OUT_ _
C
L
WHEN V = +100mV
50
OUT_ _
ID
t
PHD
PDH
R = 100
L
1%
L
C = 1.0pF
V
ID
= V
- V
IN_ _ IN_ _
Figure 4. Output Active-to-Disable and Disable-to-Active Test Circuit and Timing Diagram
_SEL0
IN_0
C
L
0
OUT_0
OUT_0
IN_0
R
L
1
C
L
PULSE
GENERATOR
MAX9390
MAX9391
50
50
C
L
OUT_1
OUT_1
0
1
R
L
IN_1
IN_1
C
L
_SEL1
EN_0 = EN_1 = HIGH
1 CHANNEL SHOWN
R = 100
L
1%
L
C = 1.0pF
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
8
_______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
V
V
V
V
OUT_0
OUT_0
OUT_1
OUT_1
IN_0
IN_1
OUT_0
OUT_1
V
= 0
V
= 0
OD
OD
t
t
CCS
CCS
2 x 2 CROSSPOINT
V
OD
= 0
V
= 0
OD
V
= V
- V
OD
OUT_ _ OUT_ _
IN_0
IN_1
t
MEASURED WITH _SEL0 = _SEL1 = HIGH OR LOW
(1:2 SPLITTER CONFIGURATION).
CCS
OUT_0 OR OUT_1
Figure 6. Output Channel-to-Channel Skew
2:1 MUX
Detailed Description
OUT_0
OUT_1
The LVDS interface standard provides a signaling
method for point-to-point communication over a con-
trolled-impedance medium as defined by the ANSI
TIA/EIA-644 standard. LVDS utilizes a lower voltage
swing than other communication standards, achieving
higher data rates with reduced power consumption,
while reducing EMI emissions and system susceptibility
to noise.
IN_0 OR IN_1
1:2 SPLITTER
IN_0
IN_1
OUT_0
OUT_1
The MAX9390/MAX9391 1.5GHz dual 2 x 2 crosspoint
switches optimize high-speed, low-power, point-to-
point interfaces. The MAX9390 accepts LVDS and
HSTL signals, while the MAX9391 accepts LVPECL and
CML signals. Both devices route the input signals to
either or both LVDS outputs.
DUAL REPEATER
When configured as a 1:2 splitter, the outputs repeat
the selected inputs. This configuration creates copies
of signals for protection switching. When configured as
a repeater, the device operates as a two-channel
buffer. Repeating restores signal amplitude, allowing
isolation of media segments or longer media drive.
When configured as a 2:1 mux, select primary or back-
up signals to provide a protection-switched, fault-toler-
ant application.
Figure 7. Programmable Configurations
Select Function
The _SEL_ logic inputs control the input and output sig-
nal connections. Two logic inputs control the signal rout-
ing for each channel. _SEL0 and _SEL1 allow the
devices to be configured as a differential crosspoint
switch, 2:1 mux, dual repeater, or 1:2 splitter (Figure 7).
See Table 1 for mode-selection settings (insert A or B for
the _). Channels A and B possess separate select
inputs, allowing different configurations for each channel.
Input Fail-Safe
The differential inputs of the MAX9390/MAX9391 pos-
sess internal fail-safe protection. Fail-safe circuitry
forces the outputs to a differential low condition for
undriven inputs or when the common-mode voltage
exceeds the specified range. The MAX9390 provides
high-level input fail-safe detection for LVDS, HSTL, and
other GND-referenced differential inputs. The MAX9391
provides low-level input fail-safe detection for LVPECL,
Enable Function
The EN_ _ logic inputs enable and disable each set of
differential outputs. Connect EN_ 0 to V
to enable
CC
the OUT_0/OUT_0 differential output pair. Connect
EN_0 to GND to disable the OUT_0/OUT_0 differential
output pair. The differential output pairs assert to a dif-
ferential low condition when disabled.
CML, and other V -referenced differential inputs.
CC
_______________________________________________________________________________________
9
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Table 1. Input/Output Function Table
_SEL0
_SEL1
OUT_0 / OUT_0
IN_0 / IN_0
IN_0 / IN_0
IN_1 / IN_1
IN_1 / IN_1
OUT_1 / OUT_1
IN_0 / IN_0
IN_1 / IN_1
IN_0 / IN_0
IN_1 / IN_1
MODE
1:2 splitter
Repeater
Switch
0
0
1
1
0
1
0
1
1:2 splitter
Output Termination
Applications Information
Terminate LVDS outputs with a 100 resistor between
the differential outputs at the receiver inputs. LVDS out-
puts require 100 termination for proper operation.
Differential Inputs
The MAX9390/MAX9391 inputs accept any differential
signaling standard within the specified common-mode
voltage range. The fail-safe feature detects common-
mode input signal levels and generates a differential
output low condition for undriven inputs or when the
common-mode voltage exceeds the specified range.
Ensure that the output currents do not exceed the cur-
rent limits specified in the Absolute Maximum Ratings.
Observe the total thermal limits of the MAX9390/
MAX9391 under all operating conditions.
Leave unused inputs unconnected or connect to V
for the MAX9390 or to GND for the MAX9391.
CC
Cables and Connectors
Use matched differential impedance for transmission
media. Use cables and connectors with matched differ-
ential impedance to minimize impedance discontinu-
ities. Avoid the use of unbalanced cables. Balanced
cables such as twisted pair offer superior signal quality
and tend to generate less EMI due to canceling effects.
Expanding the Number of LVDS Output
Ports
Cascade devices to make larger switches. Consider
the total propagation delay and total jitter when deter-
mining the maximum allowable switch size.
Board Layout
Use a four-layer printed circuit (PC) board providing
separate signal, power, and ground planes for high-
Power-Supply Bypassing
Bypass each V
to GND with high-frequency surface-
CC
mount ceramic 0.1µF and 0.01µF capacitors in parallel
as close to the device as possible. Install the 0.01µF
capacitor closest to the device.
speed signaling applications. Bypass V
to GND as
CC
close to the device as possible. Install termination
resistors as close to receiver inputs as possible. Match
the electrical length of the differential traces to minimize
signal skew.
Differential Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9390/MAX9391. Connect each input
and output to a 50 characteristic impedance trace.
Maintain the distance between differential traces and
eliminate sharp corners to avoid discontinuities in dif-
ferential impedance and maximize common-mode
noise immunity. Minimize the number of vias on the dif-
ferential input and output traces to prevent impedance
discontinuities. Reduce reflections by maintaining the
50 characteristic impedance through connectors and
across cables. Minimize skew by matching the electri-
cal length of the traces.
10 ______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Typical Operating Circuit
+3.0V TO
+3.6V
0.1 F
0.01 F
INA0
V
CC
Z = 50
0
Z = 50
OUTA0
0
100
100
MAX9390
MAX9391
OUTA0
OUTA1
Z = 50
0
Z = 50
0
INA0
LVDS
RECEIVER
INA1
INA1
INB0
INB0
INB1
INB1
Z = 50
0
MAX9173
Z = 50
0
OUTA1
OUTB0
Z = 50
0
ENA0
ENA1
ENB0
ENB1
OUTB0
OUTB1
Z = 50
0
Z = 50
0
LVCMOS/LVTTL
LOGIC INPUTS
ASEL0
ASEL1
BSEL0
BSEL1
Z = 50
0
OUTB1
GND GND GND GND
______________________________________________________________________________________ 11
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Functional Diagram
Pin Configurations (continued)
TOP VIEW
INA0
MAX9390
0
1
MAX9391
INA0
OUTA0
32 31 30 29 28 27 26 25
OUTA0
ENA0
ENB1
OUTB1
OUTB1
GND
1
2
3
4
5
6
7
8
24
23
V
CC
ASEL0
OUTA0
22 OUTA0
21 ENA0
20 GND
INA1
INA1
1
0
OUTA1
MAX9390
MAX9391
ENB0
OUTA1
ENA1
19 OUTA1
18 OUTA1
17 ENA1
OUTB0
OUTB0
ASEL1
*EXPOSED PADDLE
V
CC
INB0
INB0
9
10 11 12 13 14 15 16
0
1
OUTB0
OUTB0
ENB0
THIN QFN
*CONNECT EXPOSED PADDLE TO GND.
BSEL0
INB1
INB1
1
0
OUTB1
OUTB1
ENB1
Chip Information
TRANSISTOR COUNT: 1565
BSEL1
PROCESS: Bipolar
12 ______________________________________________________________________________________
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D2
0.15
C A
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
PIN # 1
I.D.
0.15
C
B
PIN # 1 I.D.
0.35x45
E/2
E2/2
C
(NE-1) X
e
L
E2
E
k
L
DETAIL A
e
(ND-1) X
e
C
C
L
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0140
C
2
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
REV.
2
21-0140
C
2
______________________________________________________________________________________ 13
Anything-to-LVDS Dual 2 x 2
Crosspoint Switches
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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