MAX9401 [MAXIM]
Quad ECL/PECL Differential Buffers/Receivers ; 四路ECL / PECL差分缓冲器/接收器\n
| 型号： | MAX9401 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad ECL/PECL Differential Buffers/Receivers
|
| 文件： | 总13页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2245; Rev 0; 10/01
Quad ECL/PECL Differential
Buffers/Receivers
General Description
Features
The MAX9401/MAX9404 are extremely fast and low-
skew quad ECL/PECL differential buffers/receivers for
data and clock signals. The four channels can be oper-
ated synchronously with an external clock, or in asyn-
chronous mode, determined by the state of the SEL
input. An enable input provides the ability to force all
the outputs to a differential low state.
ꢀ Differential Double-Swing ECL/PECL Outputs
ꢀ Input Compatible with LVECL/LVPECL
ꢀ Guaranteed 900mV Differential Output at 3.0GHz
Clock Rate
ꢀ 365ps Propagation Delay in Asynchronous Mode
ꢀ 10ps Channel-to-Channel Skew in Synchronous
The MAX9401 has high-impedance (open) input and
the MAX9404 has an integrated 100Ω differential input
termination, which reduces external component count.
Both devices have double amplitude swing open emit-
ter outputs suitable for driving long cables. The
Mode
ꢀ Integrated 100Ω Input Terminations (MAX9404)
ꢀ Compatible +3.3V/+5.0V Nominal Supplies
MAX9401/MAX9404 operate over a V
- V = +3.0V
EE
CC
ꢀ Selectable Synchronous/Asynchronous
to +5.5V supply range, and are specified for operation
from -40°C to +85°C. These devices are offered in
space-saving 32-pin 5mm x 5mm QFN exposed-paddle
(EP) and TQFP packages.
Operation
Ordering Information
TEMP.
PIN-
PACKAGE
INPUT
IMPEDANCE
PART
RANGE
Applications
-40°C to
+85°C
32 QFN-EP**
(5mm x 5mm)
MAX9401EGJ*
MAX9401EHJ
MAX9404EGJ*
MAX9404EHJ
Open
Open
100Ω
100Ω
Data and Clock Driver and Buffer
Central Office Backplane Clock Distribution
DSLAM Backplane
-40°C to
+85°C
32 TQFP
(5mm x 5mm)
-40°C to
+85°C
32 QFN-EP**
(5mm x 5mm)
Base Station
ATE
-40°C to
+85°C
32 TQFP
(5mm x 5mm)
*Future product—contact factory for availability.
**EP = Exposed paddle
Functional Diagram appears at end of data sheet.
Pin Configurations
TOP VIEW
32 31 30 29 28 27 26 25
*
*
V
1
2
3
4
5
6
7
8
24 V
CC
CC
V
1
2
3
4
5
6
7
8
24
V
CC
CC
SEL
SEL
CLK
CLK
EN
23 OUT1
22 OUT1
SEL
SEL
CLK
CLK
EN
23 OUT1
22 OUT1
MAX9401/
MAX9404
21
20
V
V
21
20
V
EE
V
EE
EE
EE
MAX9401
MAX9404
19 OUT2
18 OUT2
19 OUT2
18 OUT2
EN
*
EN
V
CC
17
V
CC
V
17 V
CC
CC
*
*
9
10 11 12 13 14 15 16
TQFP
QFN-EP*
*EXPOSED PAD AND CORNER PINS ARE CONNECTED TO V
EE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad ECL/PECL Differential
Buffers/Receivers
ABSOLUTE MAXIMUM RATINGS
V
CC
to V .............................................................-0.3V to +6.0V
Junction-to-Ambient Thermal Resistance with
EE
All Other Pins to V ...................................-0.3V to (V
+ 0.3V)
500LFPM Airflow
32-Pin TQFP..............................................................+73°C/W
Junction-to-Case Thermal Resistance
32-Pin TQFP..............................................................+25°C/W
32-Pin QFN-EP… ........................................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
EE
CC
Differential Input Voltage…................................................. 3.0V
Continuous Output Current.................................................70mA
Surge Output Current…....................................................100mA
Continuous Power Dissipation (T = +70°C)
A
32-Pin 5mm x 5mm TQFP (derate 9.5mW/°C
above +70°C)..............................................................761mW
32-Pin 5mm x 5mm QFN-EP (derate 21.3mW/°C
above +70°C)..................................................................1.7W
Junction-to-Ambient Thermal Resistance in Still Air
32-Pin TQFP............................................................+105°C/W
32-Pin QFN-EP…. .....................................................+47°C/W
Human Body Model (Inputs and Outputs).................>1.25kV
Soldering Temperature (10s)...........................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
- V = +3.0V to +5.5V, outputs terminated with 50Ω 1ꢀ to V
- 3.3V, inputs are driven, unless otherwise noted. Typical val-
CC
- 1.7V, T = +25°C, unless otherwise noted.) (Notes 1, 2, 3)
CC
EE
ues are at V
- V = +3.3V, V
= V
- 0.9V, V
= V
CC
EE
IHD
CC
ILD
CC A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS (IN_, IN_, CLK, CLK, EN, EN, SEL, SEL)
V
2.0
+
EE
Differential Input High Voltage
V
Figure 3
V
V
IHD
CC
V
0.2
-
CC
Differential Input Low Voltage
Differential Input Voltage
V
Figure 3
Figure 3
V
V
V
ILD
EE
0.2
-10
V
3.0
ID
EN, EN, SEL, SEL, IN_, IN_,
MAX9401
MAX9404
MAX9404
25
25
CLK, or CLK = V
or V
ILD
IHD
Input Current
I
, I
µA
IH IL
EN, EN , SEL, SEL, CLK, or
CLK = V or V
-10
86
IHD
ILD
IN to IN Differential Input
Resistance
R
114
Ω
IN
OUTPUTS (OUT_, OUT_)
Differential Output Voltage
V
- V
Figure 3
Figure 3
1.2
1.4
84
V
V
OH
OL
V
-
V
1.4
-
CC
CC
Output Common-Mode Voltage
V
OCM
1.8
POWER SUPPLY
Supply Current
I
(Note 4)
118
mA
EE
2
_______________________________________________________________________________________
Quad ECL/PECL Differential
Buffers/Receivers
AC ELECTRICAL CHARACTERISTICS
(V
- V = +3.0V to +5.5V, outputs terminated with 50Ω 1ꢀ to V
- 3.3V, outputs are enabled, input transition time = 125ps
CC
CC
EE
(20ꢀ to 80ꢀ), f
= 3.0GHz, f = 1.5GHz, V
= V +2.0V to V , V
= V to V
- 0.2V, V
- V
= 0.2 to 3.0V, unless oth-
CLK
IN
IHD
EE
CC ILD
EE
CC
IHD
ILD
erwise noted. Typical values are at V
(Notes 1, 5)
- V = +3.3V, V
= V
- 0.9V, V
= V
- 1.7V, T = +25°C, unless otherwise noted.)
CC A
CC
EE
IHD
CC
ILD
PARAMETER
SYMBOL
, t
CONDITIONS
MIN
TYP
MAX
UNITS
IN to OUT Differential
Propagation Delay
t
SEL = high, Figure 4
SEL = low, Figure 5
SEL = high (Note 6)
SEL = low (Note 6)
300
365
550
ps
PLH1 PHL1
CLK to OUT Differential
Propagation Delay
t
, t
580
620
15
758
55
ps
ps
ps
PLH2 PHL2
IN to OUT Channel-to-Channel
Skew
t
t
SKD1
SKD2
CLK to OUT Channel-to-
Channel Skew
10
40
Maximum Clock Frequency
Maximum Data Frequency
f
V
- V ≥ 900mV, SEL = low
3.0
1.5
GHz
GHz
CLK(MAX)
OH
OL
f
SEL = high, V
- V ≥ 900mV
OH OL
IN(MAX)
SEL = low, f = 1.5GHz, f
IN
clock
= 3.0GHz,
CLK
1.4
0.9
20
2.5
2.7
30
ps
(RMS)
Added Random Jitter (Note 7)
t
RJ
SEL = high, f = 1.5GHz
IN
SEL = low, f
= 3.0GHz, IN_ = 1.5Gbps,
CLK
223-1 PRBS pattern
Added Deterministic Jitter
(Note 7)
t
ps
p-p
DJ
SEL = high, IN_ = 1.5Gbps, 223-1 PRBS
pattern
36
55
IN to CLK Setup Time
CLK to IN Hold Time
Output Rise Time
Output Fall Time
t
Figure 5
Figure 5
Figure 4
Figure 4
80
80
ps
S
H
R
t
ps
ps
ps
t
116
115
145
145
t
F
Propagation Delay Temperature
Coefficient
∆t /∆T
PD
1
ps/°C
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to V
EE
except V and V
.
ID
OD
Note 3: DC parameters are production tested at T = +25°C. DC limits are guaranteed by design and characterization over the full
A
operating range.
Note 4: Outputs are open. Inputs driven high or low.
Note 5: Guaranteed by design and characterization. Limits are set to 6 sigma.
Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7: Device jitter added to the input signal.
_______________________________________________________________________________________
3
Quad ECL/PECL Differential
Buffers/Receivers
Typical Operating Characteristics
(Outputs terminated with 50Ω to V
- 3.3V, V
- V = +3.3V, V
= V
- 0.9V, V
= V
- 1.7V, output is enabled, SEL = high,
CC
CC
EE
IHD
CC
ILD
CC
SEL = low, input transition time = 125ps (20ꢀ to 80ꢀ), f
= 3.0GHz, f = 1.5GHz, T = +25°C, unless otherwise noted.)
CLK
IN
A
DIFFERENTIAL OUTPUT VOLTAGE
(V - V ) vs. IN_ FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
OH
OL
1.6
1.2
0.8
0.4
0
100
94
88
82
76
70
OUTPUTS ARE OPEN; INPUTS
ARE HIGH OR LOW
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-15
10
35
60
85
IN_ FREQUENCY (GHz)
TEMPERATURE (°C)
PROPAGATION DELAY
vs. TEMPERATURE
TRANSITION TIME vs. TEMPERATURE
130
124
118
112
106
100
700
620
540
460
380
300
CLK-TO-OUT DELAY
t
R
t
F
IN-TO-OUT DELAY
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1, 8, 11, 17,
24, 30
Positive Supply Voltage. Bypass V
CC
capacitors as close to the device as possible with the smaller value capacitor closest to the device.
to V with 0.1µF and 0.01µF ceramic capacitors. Place the
EE
V
CC
Noninverting Differential Select Input. Setting SEL = high and SEL = low (differential high) enables
all four channels to operate asynchronously. Setting SEL = low and SEL = high (differential low)
enables all four channels to operate in synchronized mode.
2
3
SEL
SEL
Inverting Differential Select Input
Inverting Differential Clock Input. A rising edge on CLK (and falling on CLK) transfers data from the
inputs to the outputs when SEL = low.
4
5
CLK
CLK
Noninverting Differential Clock Input
4
_______________________________________________________________________________________
Quad ECL/PECL Differential
Buffers/Receivers
Pin Description (continued)
PIN
NAME
FUNCTION
Noninverting Differential Output Enable Input. Setting EN = high and EN = low (differential high)
enables the outputs. Setting EN = low and EN = high (differential low) sets the outputs to logic low.
6
EN
7
EN
IN3
Inverting Differential Output Enable Input
Noninverting Differential Input 3
Inverting Differential Input 3
9
10
IN3
12
OUT3
OUT3
Inverting Differential Output 3
Noninverting Differential Output 3
Negative Supply Voltage
13
14, 20, 21, 27
V
EE
15
16
18
19
22
23
25
26
28
29
31
32
—
IN2
IN2
Noninverting Differential Input 2
Inverting Differential Input 2
OUT2
OUT2
OUT1
OUT1
IN1
Inverting Differential Output 2
Noninverting Differential Output 2
Noninverting Differential Output 1
Inverting Differential Output 1
Inverting Differential Input 1
IN1
Noninverting Differential Input 1
Noninverting Differential Output 0
Inverting Differential Output 0
Inverting Differential Input 0
OUT0
OUT0
IN0
IN0
Noninverting Differential Input 0
EP*
Exposed Paddle. EP is electrically connected to V . Solder EP to PC board.
EE
*QFN-EP package only.
provides the ability to force all the outputs to a differen-
tial low state.
Detailed Description
The MAX9401/MAX9404 are extremely fast, low-skew
quad ECL/PECL buffers/receivers designed for high-
speed data and clock driver applications. These
devices feature ultra-low propagation delay of 365ps
and channel-to-channel skew of 15ps in asynchronous
mode with 84mA supply current, making them ideal for
driving long cables and double termination applications
(Functional Diagram).
Data Input Termination
Figure 1 shows the input and output configuration of
the MAX9401/MAX9404. The MAX9401 has high-
impedance inputs and requires external termination.
The MAX9404 has integrated 100Ω differential input
termination resistors across each of the four inputs (IN_
to IN_), reducing external component count.
The four channels can be operated synchronously with
an external clock, or in asynchronous mode, deter-
mined by the state of the SEL input. An enable input
Outputs
The MAX9401/MAX9404 have double-swing open-emit-
ter outputs as shown in Figure 1. The double-amplitude
swing outputs can drive double-terminated links or long
_______________________________________________________________________________________
5
Quad ECL/PECL Differential
Buffers/Receivers
nal should be set to either logic low or high state to min-
imize noise coupling.
IN_
IN_
100Ω
Synchronous Operation
Setting SEL = low and SEL = high enables all four
channels to operate in synchronous mode. In this
mode, buffered inputs are clocked into flip-flops simul-
taneously on every rising edge of the differential clock
input (CLK and CLK).
IN_
IN_
MAX9401
MAX9404
V
CC
Differential Signal Input Limit
The maximum differential input signal magnitude is 3.0V.
Supply Voltages
OUT_
OUT_
For interfacing to differential PECL signals, the V
CC
range is from +3.0V to +5.5V (with V grounded). For
EE
interfacing to differential ECL, the V range is -3.0V to
EE
MAX9401
MAX9404
-5.5V (with V
grounded). Output levels are refer-
CC
enced to V
and are considered PECL or ECL,
CC
depending on the level of the V
supply.
Figure 1. MAX9401/MAX9404 Input and Output Configurations
CC
Applications Information
cables. External termination is required. See the Output
Termination section.
Input Bias
Unused inputs should be biased to avoid noise cou-
pling that might cause toggling at the unused outputs.
See Figure 2 for the biasing network.
Enable
Setting EN = high and EN = low enables the outputs.
Setting EN = low and EN = high forces the outputs to a
differential low when disabled. All changes on CLK,
SEL, and IN_ are ignored.
Output Termination
Terminate the outputs through 50Ω to V
- 3.3V or use
CC
an equivalent Thevenin termination. Use identical termi-
nations on each OUT for the lowest skew. When a sin-
gle-ended signal is taken from a differential output,
terminate both outputs. For example, if OUT_ is used as
a single-ended output, terminate both OUT_ and OUT_.
Asynchronous Operation
Setting SEL = high and SEL = low enables four chan-
nels to operate independently as a buffer/receiver
(CLK is ignored). In asynchronous mode, the CLK sig-
V
CC
V
CC
IN_
100Ω
IN_
IN_
IN_
100Ω
MAX9401
MAX9404
1kΩ
1kΩ
V
V
EE
EE
Figure 2. Input Bias Circuits for Unused Pins for MAX9401/MAX9404
_______________________________________________________________________________________
6
Quad ECL/PECL Differential
Buffers/Receivers
V
CC
V
(MAX)
V
CC
IHD
V
V
V
V
= 0
ID
ID
V
V
OH
OL
V
V
(MAX)
(MIN)
ILD
IHD
V
- V
OH OL
V
OCM
= 0
ID
ID
V
V
EE
V
(MIN)
EE
ILD
INPUT VOLTAGE DEFINITION
OUTPUT VOLTAGE DEFINITION
Figure 3. Input and Output Voltage Definitions
IN_
IN_
V
- V
ILD
IHD
t
t
PHL1
PLH1
OUT_
OUT_
V
V
- V
OH
OH
OL
OL
- V
- V
80%
80%
V
20%
20%
OH
OL
DIFFERENTIAL OUTPUT
WAVEFORM
OUT_ - OUT_
t
t
F
R
(SEL = HIGH, EN = HIGH)
Figure 4. IN to OUT Propagation Delay Timing Diagram
Ensure that the output currents do not exceed the cur-
rent limits as specified in the Absolute Maximum
Ratings. Under all operating conditions, the device’s
total thermal limits should be observed.
possible, with the 0.01µF capacitor closest to the
device pins. Use multiple bypass vias for connection to
minimize inductance.
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9401/MAX9404. Connect each of the
inputs and outputs to a 50Ω characteristic impedance
trace. Avoid discontinuities in differential impedance
and maximize common-mode noise immunity by main-
Power-Supply Bypassing
Adequate power-supply bypassing is necessary to
maximize the performance and noise immunity. Bypass
V
to V with high-frequency surface-mount ceramic
EE
CC
0.1µF and 0.01µF capacitors as close to the device as
_______________________________________________________________________________________
7
Quad ECL/PECL Differential
Buffers/Receivers
CLK
V
- V
ILD
IHD
CLK
t
t
t
H
H
S
IN_
IN_
V
- V
ILD
IHD
t
t
PHL2
PLH2
OUT_
OUT_
V
- V
OL
OH
(SEL = LOW, EN = HIGH)
Figure 5. CLK to OUT Propagation Delay Timing Diagram
taining the distance between differential traces and
avoid sharp corners. Minimize the number of vias to
prevent impedance discontinuities. Reduce reflections
by maintaining the 50Ω characteristic impedance
through connectors and across cables. Minimize skew
by matching the electrical length of the traces.
Chip Information
TRANSISTOR COUNT: 748
PROCESS: Bipolar
8
_______________________________________________________________________________________
Quad ECL/PECL Differential
Buffers/Receivers
Functional Diagram
IN0
IN0
1
OUT0
D
D
Q
0
OUT0
Q
CLK
CLK
IN1
IN1
1
0
OUT1
OUT1
D
Q
Q
D
CLK
CLK
IN2
IN2
1
0
OUT2
OUT2
D
Q
Q
D
CLK
CLK
IN3
IN3
1
0
OUT3
OUT3
D
Q
Q
D
CLK
CLK
CLK
CLK
SEL
SEL
EN
EN
_______________________________________________________________________________________
9
Quad ECL/PECL Differential
Buffers/Receivers
Package Information
10 ______________________________________________________________________________________
Quad ECL/PECL Differential
Buffers/Receivers
Package Information (continued)
______________________________________________________________________________________ 11
Quad ECL/PECL Differential
Buffers/Receivers
Package Information (continued)
12 ______________________________________________________________________________________
Quad ECL/PECL Differential
Buffers/Receivers
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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