MAX9481CUP-T [MAXIM]
暂无描述;
| 型号： | MAX9481CUP-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 驱动器 |
| 文件： | 总18页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2539; Rev 1; 1/03
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
General Description
Features
The MAX9480/MAX9481/MAX9482 low-power, low-dis-
tortion, class-G, high-current asymmetric digital sub-
scriber line (ADSL) drivers offer Rail-to-Rail® output and
are ideal for ADSL in central-office applications.
Operating from ±±5 and ±2.±5 supplies, the drivers
incorporate two high-speed current-feedback preampli-
fiers driving two fixed-gain class-G buffers. The buffers
can deliver 20.4dBm average line power with a signal
crest factor of ±.3, and are designed to be directly DC or
AC bridged across a 1:2.± transformer.
ꢀ Dissipate Only 655mW While Driving 20.4dBm
ADSL Full-Rate DMT-Modulated Signal
ꢀ Operate with 5.0ꢀ and 2.5ꢀ Vower Supplies
ꢀ Complete ADSL Central-Office Line Interface
(MAX9480/MAX9482)
Two Vreamplifiers plus Class-G Rail-to-Rail
Buffers
Active Line Termination plus Integrated Hybrid
(MAX9480)
Low-Noise Uncommitted Receive Amplifiers
(MAX9482)
The MAX9480/MAX9481/MAX9482 employ an active line
termination scheme for incoming signals that eliminates
the need for back-match resistors, reducing line-card
power consumption at full rate to less than half of that
required by conventional class-AB line-driver circuits.
Fixed-Gain Receive Amplifiers (MAX9480)
Low-Output-Impedance Shutdown Mode
ꢀ Vreamplifiers, Buffers, and Active Line
Termination Functions (MAX9481)
ꢀ High-Output-Drive Capability
The MAX9480 includes a hybrid network and two low-
noise, fixed-gain-of-4.65/5 receive amplifiers. The part is
designed to recover the receive signal to the same level
as that of a conventional line interface circuit that incor-
porates a 1:2 transformer and standard back-matched
hybrid, without degrading signal-to-noise ratio (SNR) or
line-impedance sensitivity. The MAX9481 provides only
the preamplifiers and buffers without the hybrid or
receivers. The MAX9482 provides preamplifiers, buffers,
and uncommitted receive amplifiers. All devices have a
low-output-impedance shutdown function for saving
power when not transmitting.
15ꢀ
Differential Output ꢀoltage Swing at
V-V
R = 16Ω
L
500mA Output-Drive
ꢀ Low Distortion: -71dBc Highest Harmonic at 1MHz
and 14ꢀ
V-V
ꢀ High Speed: 250ꢀ/µs Slew Rate, 80MHz -3dB
Bandwidth (G = -3)
ꢀ Thermal Shutdown
ꢀ Exposed Vads Improve Thermal Verformance
Ordering Information
VART
TEMV RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
VIN-VACKAGE
20 TSSOP-EP**
20 TSSOP-EP
28 TSSOP-EP
32 QFN
At full-rate 20.4dBm discrete multitone data transmission
(DMT), the total dynamic power dissipation is only
680mW (MAX9480/MAX9482) or 6±±mW (MAX9481).
The MAX9480/MAX9481 are available in a 20-pin TSSOP
package and the MAX9482 is available in 28-pin TSSOP
and 32-pin QFN packages. All devices operate over the
extended -40°C to +8±°C temperature range.
MAX9480CUP
MAX9481CUP
MAX9482CUI
MAX9482CGJ*
*Future product—contact factory for availability.
**EP = Exposed pad.
Applications
Pin Configurations
Full-Rate ADSL
HDSL
TOP VIEW
POUT1
IN1-
1
2
3
4
5
6
7
8
9
20
19
18
V
V
V
LM
Central Office
DSLAM
LP
IN1+
CC
RXP
17 OUT1
MAX9480
DGND
SHDN
RXM
IN2+
16
15
14
13
12
11
V
V
EE
EE
OUT2
V
V
V
CC
LP
Typical Operating Circuits appear at end of data sheet.
IN2-
POUT2 10
LM
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
TSSOV
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
ABSOLUTE MAXIMUM RATINGS
V
V
V
V
V
V
to V ...........................................................................+12V
POUT1/POUT2 Output Current.........................................100ꢀA
RXP/RXM Output Short-Circuit Duration to
CC
LP
CC
CC
EE
EE
EE
to V ............................................................................+12V
LM
or V to DGND ................................................-0.3V to +6V
V /V /V /V ................................................................10s
CC EE LP LM
LP
to V ................................................................-0.3V to +6V
RXP/RXM Output Current..................................................100ꢀA
Continuous Power Dissipation (T = +70°C)
LP
or V to DGND ................................................-6V to +0.3V
LM
A
to V ................................................................-6V to +0.3V
20-Pin TSSOP with Pad Connected to V
LM
EE
Current into V or V .................................................. 250ꢀA
(derate 21.7ꢀW/°C above +70°C)..............................1739ꢀW
20-Pin TSSOP with Floating Pad
LP
LM
IN1+, IN1-, IN2+, IN2-......................(V
+ 0.3V) to (V - 0.3V)
CC
EE
SHDN ...............................................(V
+ 0.3V) to (V - 0.3V)
(derate 11.0ꢀW/°C above +70°C)................................879ꢀW
CC
EE
BOUT1/BOUT2 Output Short-Circuit Duration to
/V /V /V ....................................................Moꢀentary
28-Pin TSSOP with Pad Connected to V
EE
V
(derate 23.8ꢀW/°C above +70°C)..............................1905ꢀW
28-Pin TSSOP with Floating Pad
CC EE LP LM
BOUT1/BOUT2 Output Current...........................................20ꢀA
OUT1/OUT2 Output Short-Circuit Duration to
(derate 12.8ꢀW/°C above +70°C)..............................1026ꢀW
32-Pin QFN (derate 23.3ꢀW/°C above +70°C).........1860ꢀW*
Operating Teꢀperature Range
V /V /V /V ....................................................Moꢀentary
CC EE LP LM
OUT1/OUT2 Output Current ....................................................1A
OUT1 to OUT2 Short-Circuit Duration........................Continuous
POUT1/POUT2 Output Short-Circuit Duration to
(T
, T
) .....................................................-40°C to +85°C
MIN MAX
Junction Teꢀperature......................................................+150°C
Storage Teꢀperature Range.............................-65°C to +150°C
Lead Teꢀperature (soldering, 10s) .................................+300°C
V /V /V /V ................................................................10s
CC EE LP LM
*Refer to Application Note HFAN-08-1.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V, V = -5V, V = +2.5V, V
= -2.5V, DGND = 0, R = 16Ω is connected froꢀ OUT1 to OUT2, SHDN = 0, T = T
to
CC
EE
LP
LM
L
A
MIN
T
, unless otherwise noted. Typical values specified at T = +25°C. Preaꢀp configured for A = +1 with 1kΩ froꢀ POUT_ to IN_-.)
MAX
(Note 1)
A
V
VARAMETER
SYMBOL
CONDITIONS
MIN
TYV
680
655
790
MAX
UNITS
MAX9480/
MAX9482
V
= 1.327V
,
OUT(DIFF)
RMS
Dynaꢀic Power Dissipation
Dynaꢀic Power Consuꢀption
P
ꢀW
DISS
crest factor = 5.3
MAX9481
MAX9480/
MAX9482
V
= 1.327V
,
OUT(DIFF)
RMS
P
ꢀW
V
CONS
crest factor = 5.3
MAX9481
765
5.00
-5.00
2.50
-2.50
21.5
22.0
20.0
21.0
21.5
22.0
V
(Note 2)
(Note 2)
(Note 2)
(Note 2)
4.75
-4.75
2.25
5.25
-5.25
2.75
-2.75
35.0
40.0
34.0
39.0
35.0
40.0
CC
V
V
EE
Supply Voltage Range
LP
V
-2.25
LM
V
V
V
V
V
V
, V
CC EE
MAX9480, R = ∞
L
, V
LP LM
, V
CC EE
Quiescent Supply Current
(Including Preaꢀps)
I
, I
CC EE
,
MAX9481, R = ∞
ꢀA
L
I
, I
LP LM
, V
LP LM
, V
CC EE
MAX9482, R = ∞
L
, V
LP LM
2
_______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, V = -5V, V = +2.5V, V
= -2.5V, DGND = 0, R = 16Ω is connected froꢀ OUT1 to OUT2, SHDN = 0, T = T
to
CC
EE
LP
LM
L
A
MIN
T
, unless otherwise noted. Typical values specified at T = +25°C. Preaꢀp configured for A = +1 with 1kΩ froꢀ POUT_ to IN_-.)
MAX
A
V
(Note 1)
VARAMETER
SYMBOL
CONDITIONS
MIN
TYV
2.1
1.5
0.6
0.05
2.1
1.5
76
MAX
6.0
5.0
1.2
0.1
6.0
5.0
UNITS
V
V
V
V
V
V
, V
CC EE
MAX9480, R = ∞
L
, V
LP LM
, V
CC EE
Shutdown Supply Current
I
MAX9481, R = ∞
ꢀA
SD
L
, V
LP LM
, V
CC EE
MAX9482, R = ∞
L
, V
LP LM
V
V
- V
=
=
4.75V to 5.25V
2.25V to 2.75V
50
50
CC
LP
EE
Transꢀit Path Power-Supply
Rejection Ratio (Single Ended)
PSRR
CMR
HRR
dB
dB
dB
- V
LM
81
Coꢀꢀon-Mode Rejection
-200ꢀV ≤ V
≤ +200ꢀV
46
CM
Hybrid Rejection Ratio
(MAX9480 Only)
V
=
1.2V
35
OUT(DIFF)
Driver-to-Receiver Crosstalk
(MAX9482 Only)
X
f = 100kHz
-69
dB
TALK
SHDN Logic Low
V
0.8
5.0
V
V
IL
SHDN Logic High
V
2.0
IH
SHDN Input Current
Shutdown Delay Tiꢀe
Shutdown Enable Tiꢀe
I
t
, I
IH IL
SHDN = 0 or SHDN = V
µA
µs
µs
CC
4.8
4
SHDN
t
ENABLE
f1 = 1MHz, f2 = 900kHz, Typical Operating
Circuit, V = 2.0V
Interꢀodulation Distortion
I
-66
dB
MD
OUT(DIFF)
P-P
DRIꢀER
Maxiꢀuꢀ RMS Output Power
(Typical Operating Circuit)
(Note 3)
DMT ꢀodulation (crest factor, Cr = 5.33)
CAP ꢀodulation (crest factor, Cr = 4.00)
21.4
P
dBꢀW
OUT
G
24.3
-2.7
Closed-Loop Gain
V
= 1.2V
-3
-3.3
V/V
dB
OUT(DIFF)
P-P
f = 1MHz, V
= 14V
,
OUT(DIFF)
P-P
Second Harꢀonic Distortion
-71
Typical Operating Circuit (Note 4)
f = 1MHz, V = 14V , Typical
Operating Circuit (Note 4)
OUT(DIFF)
P-P
Third Harꢀonic Distortion
-74
dB
Differential Output Voltage Swing
V
Typical Operating Circuit (Note 4)
15.0
0.5
V
OUT(DIFF)
P-P
V
- V
OH
CC
R = 100Ω
L
|V - V
|
0.5
OUT_ Voltage Swing
(per Aꢀplifier) (Note 4)
EE
OL
V
, V
OH OL
V
V
- V
1.27
1.21
0.45
0.42
500
5
CC
OH
R = 16Ω
L
|V - V
|
EE
OL
V
- V
BOH
CC
BOUT_ Voltage Swing
(per Aꢀplifier) (Note 4)
V
,
BOH
V
V
BOL
|V - V
EE
|
BOL
Peak Output Current
I
ꢀA
ꢀV
OUT
Differential Output Offset Voltage
V
IN1+ = IN2+ = 0
OS(DIFF)
_______________________________________________________________________________________
3
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, V = -5V, V = +2.5V, V
= -2.5V, DGND = 0, R = 16Ω is connected froꢀ OUT1 to OUT2, SHDN = 0, T = T
to
CC
EE
LP
LM
L
A
MIN
T
, unless otherwise noted. Typical values specified at T = +25°C. Preaꢀp configured for A = +1 with 1kΩ froꢀ POUT_ to IN_-.)
MAX
A
V
(Note 1)
VARAMETER
SYMBOL
CONDITIONS
MIN
TYV
MAX
UNITS
Differential Output Offset-Voltage
Drift
V
12
µV/°C
OS(DRIFT)
-200ꢀV ≤ V
≤ +200ꢀV
6
8
8
10
OUT
Output Resistance (per Aꢀplifier)
R
Ω
OUT
SHDN = V
CC
-3dB Bandwidth
BW
SR
80
MHz
V/µs
Slew Rate
V
= 14V
step
250
-127
1000
OUT(DIFF)
P-P
Output Noise PSD
P
f = 100kHz to 1.1MHz, referred to 100Ω line
dBꢀ/Hz
pF
N
Capacitive Load Stability
VREAMVS AND RECEIꢀERS (Note 5)
Open-Loop Transiꢀpedance
No sustained oscillations
Z
-2V ≤ P
≤ +2V
300
87
kΩ
dB
ꢀV
µA
OL
OUT
V
V
- V
=
4.75V to 5.25V
2.25V to 2.75V
50
50
CC
LP
EE
Power-Supply Rejection Ratio
PSRR
- V
LM
=
100
2
Input Offset Voltage
V
10
20
OS
B+
IN1+, IN2+, RXIN1+, RXIN2+
Bias Current
I
1
IN1+, IN2+, RXIN1+, RXIN2+
Bias Current Matching
I
0.7
2.6
1.2
µA
µA
µA
OS+
IN1-, IN2-, RXIN1-, RXIN2-
Bias Current
I
B-
20
IN1-, IN2-, RXIN1-, RXIN2-
Bias Current Matching
I
OS-
IN1+, IN2+, RXIN1+, RXIN2+
IN1-, IN2-, RXIN1-, RXIN2-
1.1
MΩ
Input Resistance
R
IN
IN
200
Ω
IN1+, IN2+, IN1-, IN2-, RXIN1+, RXIN2+,
RXIN1-, RXIN2-
Input Capacitance
C
2
pF
Note 1: All devices are 100% production tested at T = +25°C. Specifications over teꢀperature liꢀits are guaranteed by design.
A
Note 2: Guaranteed by the PSRR test.
Note 3: Iꢀplied by worst-case output voltage swing (V
), crest factor (Cr), and load iꢀpedance (R ):
L
OUT(DIFF)
2
250 × V
OUT(DIFF)
P
=10log
dBꢀW
DRIVER
10
2
Cr × R
L
Note 4: Device ꢀay exceed absolute ꢀaxiꢀuꢀ ratings for power dissipation if unit is subjected to full-scale sinusoids for long
periods. See the Applications Information section.
Note 5: Receiver specifications guaranteed for MAX9482 only.
4
_______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Characteristics
(V
= +5V, V = -5V, V = +2.5V, V = -2.5V, DGND = 0, RXIN1+ = RXIN2+ = 0, IN1+ = IN2+ = 0, R = 16Ω is connected froꢀ
EE LP LM L
CC
OUT1 to OUT2, SHDN = 0, T = +25°C, unless otherwise noted. Preaꢀp configured for A = +1 with 1kΩ froꢀ RXOUT_- to RXIN_-.
A
V
Receiver configured for A = +1 with 1kΩ froꢀ POUT_ to IN_-.)
V
SUPPLY CURRENT vs. TEMPERATURE
SHUTDOWN CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. OUTPUT VOLTAGE
30
26
22
18
14
10
3.0
2.4
1.8
1.2
0.6
0
600
500
400
300
200
100
0
MAX9481
MAX9481
=
=
5V SUPPLY
2.5V SUPPLY
I
DC
INPUT = DC
f
= 1MHz
INPUT
2.5V SUPPLY
2.5V SUPPLY
I
AVG
I
AVG
5V SUPPLY
f
= 100kHz
INPUT
5V SUPPLY
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
V
P-P (V)
OUT
DRIVER HARMONIC DISTORTION
vs. FREQUENCY
TRANSMIT PATH
FREQUENCY RESPONSE
MAX9480 toc04
0
-20
80
-140
V
P-P = 2.0V
OUT
OVERALL GAIN = -9V/V
PREAMP GAIN = +3V/V
60
40
-160
-180
-200
-220
-240
-260
-280
-300
20
-40
0
2ND HARMONIC
23NRD HARMONIC
OVERALL GAIN = -3V/V
PREAMP GAIN = +1V/V
-60
-20
-40
-60
-80
-80
= GAIN
= PHASE
-100
0.01
0.1
1
10
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
DRIVER HARMONIC DISTORTION
vs. OUTPUT VOLTAGE
RECEIVER AMPLIFIER
FREQUENCY RESPONSE
MAX9480 toc07
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
30
135
90
f = 1MHz
A
B
20
10
45
C
0
23NRD HARMONIC
0
2ND HARMONIC
-10
-20
-30
-40
B
A
-45
-90
-135
C
SUPPLY CROSSOVER REGION
= GAIN
= PHASE
-100
2
4
6
8
10 12 14 16 18
(DIFF) (V
0.01
0.1
1
10
100
1000
V
)
P-P
FREQUENCY (MHz)
A: GAIN = 10V/V
B: GAIN = 5V/V
OUT
C: GAIN = 1V/V
_______________________________________________________________________________________
5
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Characteristics (continued)
(V
= +5V, V = -5V, V = +2.5V, V = -2.5V, DGND = 0, RXIN1+ = RXIN2+ = 0, IN1+ = IN2+ = 0, R = 16Ω is connected froꢀ
EE LP LM L
CC
OUT1 to OUT2, SHDN = 0, T = +25°C, unless otherwise noted. Preaꢀp configured for A = +1 with 1kΩ froꢀ RXOUT_- to RXIN_-.
A
V
Receiver configured for A = +1 with 1kΩ froꢀ POUT_ to IN_-.)
V
RECEIVER INPUT NOISE
RECEIVER AMPLIFIER HARMONIC
DISTORTION vs. FREQUENCY
vs. FREQUENCY
MAX9480 toc08
100
10
1
100
10
1
-40
-50
R
V
A
= 150Ω
P-P
= 10V/V
LOAD
OUT
V
= 1V
i
n-
-60
3RD HARMONIC
2ND HARMONIC
i
n+
-70
-80
-90
e
n
-100
0.001
0.01
0.1
1
0.001
0.01
0.1
1
FREQUENCY (MHz)
FREQUENCY (MHz)
RECEIVER AMPLIFIER HARMONIC
DISTORTION vs. OUTPUT AMPLITUDE
OUTPUT NOISE vs. FREQUENCY
-100
-110
-120
-130
-140
-150
-160
-40
-50
R
= 150Ω
LOAD
f = 100kHz
= 1V/V
A
V
3RD HARMONIC
PREAMP GAIN = 3
PREAMP GAIN = 1
-60
-70
2ND HARMONIC
-80
-90
-100
0.0001
0.001
0.01
0.1
1
0
1
2
3
)
4
FREQUENCY (MHz)
OUTPUT VOLTAGE (V
P-P
POWER DISSIPATION vs. LINE POWER
V
AND V vs. TEMPERATURE
OL
OH
800
750
700
650
600
550
500
450
400
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
V
- V
OL
CC
MAX9480/MAX9482
MAX9481
|V - V
CC
|
OL
12 13 14 15 16 17 18 19 20 21 22
LINE POWER (dBm)
-40
-15
10
35
60
85
TEMPERATURE (°C)
6
_______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Pin Description
VIN
NAME
FUNCTION
MAX9482
TSSOV
MAX9480
MAX9481
QFN
31
1
2
2
3
POUT1
IN1-
First Preaꢀp Output
First Inverting Input
2
3
3
4
1
4
2
IN1+
First Noninverting Input
4
—
11
10
RXP
Positive Receiver Output froꢀ Internal Hybrid
Ground
5
5
5
3
DGND
SHDN
RXM
6
6
6
4
Shutdown Control Pin
7
—
16
15
Negative Receiver Output froꢀ Internal Hybrid
Second Preaꢀp Noninverting Input
Second Preaꢀp Inverting Input
Second Preaꢀp Output
8
7
7
5
IN2+
9
8
8
6
IN2-
10
9
9
7
POUT2
11, 20
12, 19
13, 18
14
11, 20
12, 19
13, 18
14
18, 28
19, 27
20, 25
21
17, 28
18, 27
19, 24
20
V
-2.5V Negative Power-Supply Voltage
+2.5V Positive Power-Supply Voltage
+5V Positive Power-Supply Voltage
Second Driver Output
LM
V
LP
V
CC
OUT2
15, 16
17
15, 16
17
22, 23
24
21, 22
23
V
-5V First Negative Power-Supply Voltage
First Driver Output
EE
OUT1
BOUT1
BOUT2
RXIN1-
RXIN1+
RXIN2+
RXIN2-
—
1
1
30
First Driver Output Sense
—
10
10
8
Second Driver Output Sense
First Receiver Inverting Input
First Receiver Noninverting Input
Second Receiver Noninverting Input
Second Receiver Inverting Input
—
—
12
11
—
—
13
12
—
—
14
13
—
—
15
14
9, 16, 25, 26,
29, 32
—
—
17, 26
EP
N.C.
Not Internally Connected
Exposed pad internally connected to V
See the Applications Information section.
.
EE
EP
EP
EP
V
EE
_______________________________________________________________________________________
7
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Detailed Description
Applications Information
The MAX9480/MAX9481/MAX9482 are fully differential
line transceivers for ADSL applications. Each transꢀit
path has a high-bandwidth, low-distortion, current-feed-
back operational aꢀplifier followed by a fixed-gain
class-G output buffer.
Theory of Operation
The preaꢀplifiers and receivers are current-feedback
aꢀplifiers; thus, their open-loop transfer function is
expressed as a transiꢀpedance, ∆V
/∆I , or Z
.
OL
OUT IN
The frequency behavior of their open-loop transiꢀped-
ance is siꢀilar to the open-loop gain of a voltage-feed-
back aꢀplifier; that is, they have a large DC value that
decreases at approxiꢀately 6dB per octave. Analyzing
the follower with gain, as shown in Figure 1, yields the
following transfer function:
The MAX9480/MAX9481/MAX9482 are class-G devices
and require two dual power supplies, 5V and 2.5V.
All preaꢀplifier inputs and outputs are available to
allow external gain configuration. The MAX9480 con-
tains an internal hybrid echo cancellation circuit with
receiver aꢀplifiers set to a fixed gain of 4.6V/V. The
MAX9482 has no internal hybrid, but contains two
uncoꢀꢀitted low-noise op aꢀps for coupling to an
external hybrid network. The MAX9481 has only the
preaꢀp and line-driver circuits.
ZOL(S)
VOUT
= G×
Equation1
[
]
V
ZOL(S) +G×(RIN +RF)
IN
The two class-G output buffers are internally configured
for an inverting gain of three, and eꢀploy an active ter-
ꢀination scheꢀe that presents an 8Ω load to incoꢀing
signals. The buffers are designed for use with a 1:2.5
line transforꢀer and can deliver 20.4dBꢀ average line
power with a signal crest factor of 5.3 into a standard
100Ω line. The outputs are designed to be directly DC-
or AC-bridged across the transforꢀer.
where G = A
= 1 + (R /R ), and R = 1/g ≠ 200Ω.
F G IN M
VCL
At low gains, G x R << R . Therefore, the closed-loop
bandwidth is essentially independent of closed-loop
gain. Siꢀilarly, Z >> R at low frequencies, so that:
IN
F
OL
F
VOUT
RF
RG
= G=1+
Equation2
[
]
V
IN
The MAX9480/MAX9481/MAX9482 have a low-output
iꢀpedance, low-power shutdown ꢀode that is activated
by driving SHDN high. Transꢀit path aꢀplifiers and
buffers are disabled while the part is in shutdown, and
an 8Ω resistor is coupled directly between OUT_ and the
output of a three-state buffer referenced to DGND (0V).
The receive aꢀplifiers reꢀain active in shutdown ꢀode.
Shutdown
Forcing SHDN high puts the MAX9480/MAX9481/
MAX9482 into low-power shutdown ꢀode. In shutdown
ꢀode, OUT1 and OUT2 are low iꢀpedance, and the
power-supply currents drop to less than 10% of their nor-
ꢀal quiescent operating values. When coꢀing out of shut-
down, allow about 1.5µs before coꢀꢀencing operation.
PC Board Layout
Power-Supply Bypassing
The MAX9480/MAX9481/MAX9482 are wide-bandwidth
devices and require careful board layout, including the
possible use of constant-iꢀpedance ꢀicrostrip or
stripline techniques. To realize the full AC perforꢀance
of these high-speed aꢀplifiers, pay careful attention to
power-supply bypassing. The PC board should have at
least two layers: a signal and power layer on one side,
and a large, low-iꢀpedance ground plane on the other
side. The ground plane should be as free of voids as
possible. With ꢀultilayer boards, locate the ground
plane on a layer that incorporates no signal or power
traces. Observe the following guidelines when design-
ing the board. IC sockets increase parasitic capaci-
tance and inductance, and should not be used. Do not
ꢀake 90° turns; round all corners. Observe high-fre-
quency bypassing techniques to ꢀaintain the aꢀplifier’s
R
R
F
G
R
IN
+1
V
OUT
+1
Z
OL
MAX9480
MAX9481
MAX9482
V
IN
Figure 1. Current Feedback Amplifier Block Diagram
8
_______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
accuracy. The bypass capacitors should include a
0.1µF ceraꢀic capacitor between each supply pin and
the ground plane, located as close to the package as
possible. Additionally, place a 1µF to 10µF ceraꢀic or
tantaluꢀ capacitor in parallel with each 0.1µF capacitor,
and as close to theꢀ as possible. Place a 10µF to 15µF
low-ESR tantaluꢀ capacitor at the V , V , and V
DC and Noise Errors
There are several error sources to consider when using
any operational aꢀplifier, and this applies to the
MAX9480/MAX9481/MAX9482 as well. Offset-error
terꢀs are given by equations 3 and 4. Voltage and cur-
rent-noise errors are root-square suꢀꢀed and there-
fore coꢀputed separately. In Figure 3, the total output
offset voltage is deterꢀined by:
CC LM
LP
power-supply points of entry to the PC board. Place a
100µF to 220µF low-ESR tantaluꢀ capacitor at the V
EE
• The input offset voltage, V , tiꢀes the closed-loop
OS
power-supply point of entry to the PC board. The power-
supply traces should lead directly froꢀ the board input
gain (1 + (R / R )).
F
G
• The positive input bias current, I , tiꢀes the source
B+
capacitors to V
and V . To ꢀiniꢀize parasitic induc-
EE
CC
resistor, R (typically less than 10Ω), plus the nega-
S
tance, keep PC traces short and use surface-ꢀount
coꢀponents. Wire-wrapped boards are ꢀuch too induc-
tive, and breadboards are ꢀuch too capacitive; neither
should be used. Power-supply sequencing is required;
apply 5.0 before applying 2.5V.
tive input bias current, I , tiꢀes the parallel coꢀbi-
B-
nation of R and R . In current-ꢀode feedback
G
F
aꢀplifiers, the input bias currents ꢀay flow into or
out of the device. For this reason, there is no benefit
to ꢀatching the resistance at both inputs, as is coꢀ-
ꢀon in voltage-feedback aꢀplifiers.
Exposed-Pad Connection
For optiꢀuꢀ electrical perforꢀance, the EP of the
MAX9480/MAX9481/MAX9482 should be soldered to
the PC board and electrically connected to V with as
EE
wide a trace as possible. If using the EP, the 100µF to
220µF low-ESR tantaluꢀ capacitor should be used to
decouple the EP to the ground plane of the PC board
as close to the EP region as possible. For optiꢀuꢀ
therꢀal perforꢀance, the EP should be additionally
connected to a heat sink, as described in the Thermal
Protection and Power Dissipation section.
V
IN
R
R
R
F
G
T
MAX9480
MAX9481
MAX9482
V
OUT
Preamp Output Bypassing
In addition to the above layout considerations, and inde-
pendent of the gain setting, soꢀe high-frequency
bypassing of the preaꢀp outputs is necessary to prevent
instability arising froꢀ the high-frequency input iꢀped-
ance characteristics of the buffers. A 50Ω resistor in
series with a 2200pF ceraꢀic capacitor should be con-
nected between POUT_ and DGND, with a 47pF capaci-
tor connected directly between POUT_ and DGND.
R
S
R
G
F
(a)
V
IN
V
= -
OUT
( R )( )
R
R
F
G
Choosing Feedback and Gain Resistors
The MAX9480/MAX9481/MAX9482 use current-feed-
back aꢀplifiers. Figure 2 shows the standard inverting
and noninverting configurations. Notice that the gain of
the noninverting circuit, Figure 2(b), is 1 plus the ꢀag-
nitude of the inverting closed-loop gain. Increasing
feedback resistor values decreases peaking. Use the
MAX9480
MAX9481
MAX9482
V
OUT
V
IN
=
R
T
input resistor, R , to change the ꢀagnitude of the gain.
G
Do not use feedback capacitance.
R
G
F
V
(b)
1+
OUT
V
IN
[ (R )]( )
Figure 2. Inverting Gain Configuration and Noninverting Gain
Configuration
_______________________________________________________________________________________
9
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
R7
800Ω
R
R
F
G
R8
667Ω
I
B-
MAX9480
MAX9481
MAX9482
Z
V
OUT
OUT
I
B+
R1
1.6Ω
R
S
R9
945Ω
Figure 3. Input Offset Voltage and Current
R10
540Ω
The equation for total DC error is:
[Equation 3]
Figure 4. Active Line Termination Scheme, Single Side
R
R
F
V
= I
R
+ (I )(R ||R )+ V
OS
1+
(
)
[
]
OUT
B+
S
B−
F
G
G
Driving Capacitive Loads
The MAX9480/MAX9481/MAX9482 receive aꢀplifiers
are optiꢀized for AC perforꢀance. They are not
designed to drive highly capacitive loads. Reactive
loads decrease phase ꢀargin and can produce exces-
sive ringing and oscillation.
The total output-referred noise voltage is:
[Equation 4]
Rs 2 + i R ||R 2 +(en)2
RF
en(OUT) = 1+
i
(
[
n+
)
(
[
)
]
]
n−
F
G
R
G
Output-Impedance Synthesis
To help ꢀeet the contradictory requireꢀents of high
output power and low-power use, the active terꢀination
circuit shown in Figure 5 is used. This circuit is
designed to present a line terꢀination of 8Ω. R1 is a
physical 1.6Ω resistor voltage feedback froꢀ the out-
board end of R1 to the noninverting input of the aꢀplifi-
er, introduces positive feedback, which increases the
effective output-iꢀpedance value froꢀ 1.6Ω to 8Ω.
Hence, the iꢀpedance looking into the port ꢀatches
the line iꢀpedance reflected through the transforꢀer.
The MAX9480/MAX9481/MAX9482 have very low noise
input voltage (e ), 3.5nV/√Hz (typ). The current noise at
n
the noninverting input (i ) is 4.0pA/√Hz (typ), and the
n+
current noise at the inverting input, i , is 15pA/√Hz (typ).
n-
An exaꢀple of the DC error calculations, using the
MAX9480 data and the Typical Operating Circuit where
R = R = 1kΩ (R || R = 500Ω) and R = 50Ω, gives
F
G
F
G
S
the following, using equation 3:
Assuꢀing an ideal aꢀplifier, the following equation
expresses the output iꢀpedance:
1000×1000
1000+1000
−6
−6
1.0 × 10
50+ 2.6×10
(
)
(
)
V
=
OUT
R
1
1000
1000
Z
=
Equation 5
+0.002 x 1+
[
]
OUT
R
R
R
10
7
8
1− 1+
R
+ R
10
9
where V
= 6.7ꢀV at the preaꢀp outputs.
OUT
Calculating total preaꢀp output noise using equation 4
yields 16.6nV/√Hz, which then contributes 50nV/√Hz at
the driver output. The driver noise contributes an addi-
tional 35ꢀV/√Hz, to the overall output noise.
Substituting the values of the resistors shown in Figure
4 into equation 5, we obtain Z = 8Ω.
The output equivalent circuit for the line driver is shown
in Figure 5.
OUT
10 ______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
In this pseudo-class-G aꢀplifier, there is no abrupt
Z
OUT = 8Ω
supply switchover between the higher voltage and the
lower voltage aꢀplifiers, as in a traditional class G. It is
a seaꢀless transition that depends only on the aꢀpli-
tude of the input signal and the gain. The lower voltage
1:2.5
LINE +
Z
Z
IN
= 16Ω
OUT = 100Ω
LINE PORT
Tx PORT
Z
aꢀplifier has a high conversion conductance, G , and
A
the higher voltage aꢀplifier has a low conductance, G .
B
LINE -
With a low input voltage, the lower voltage aꢀplifier pro-
vides ꢀost of the output current to the load. As the volt-
age of the input signal increases, the lower voltage
aꢀplifier starts to saturate and the higher voltage aꢀpli-
fier begins to drive the output.
OUT = 8Ω
Figure 5. Output Equivalent Circuit
With a 1:2.5 transforꢀer, the two 8Ω iꢀpedances real-
ized by the active-feedback network forꢀ a perfect line
terꢀination. The MAX9480 faꢀily’s active terꢀination
design ꢀakes it possible to use a 5V power supply
instead of 12V or 15V, significantly increasing driver
efficiency.
0.8Rx
Tx
Rx
MAX9480
0.8Tx
LINE
OUT1
Hybrid Considerations
The MAX9480 includes an internal hybrid coupling cir-
cuit to realize the receive function with no external coꢀ-
ponents. The hybrid couples the transꢀitted signal
froꢀ the line-driver port (Tx port) to the line port and
cancels the echo in the receiving port (Rx port). The
hybrid circuit is detailed in Figure 6. If using the
MAX9481 or the MAX9482, external circuitry ꢀust be
added to realize a receive function. The MAX9482
includes two uncoꢀꢀitted op aꢀps for this purpose.
R1
R3
PORT
R4
1.6Ω
1kΩ
1.2kΩ
RXM
0Tx + 0.18Rx
Rx
Tx
PORT
PORT
0Tx - 0.18Rx
RXP
R6
1.2kΩ
R5
1kΩ
R2
1.6Ω
OUT2
-Rx
A traditional hybrid network with a 2:1 resistor ratio
ꢀust be replaced with a 1.2:1 ratio to achieve noꢀinal
echo cancellation. Additionally, the use of a synthe-
sized output iꢀpedance has the side effect of prevent-
ing a “virtual-ground” condition at the driver output
(BOUT), as seen by the receive signal. Hence, the
resulting hybrid circuit exhibits an increased attenua-
tion of the receive signal with respect to a traditional
case with no synthesis. For central-office ADSL appli-
cations, the noise specifications allow this trade-off to
be ꢀade.
-0.8Rx
-Tx
-0.8Tx
(a) HYBRID CIRCUIT IN MAX9480
0Rx
Tx
Rx
0.5Tx
LINE
PORT
OUT1
8Ω
1kΩ
2kΩ
RXM
0Tx + 0.67Rx
Pseudo-Class-G Amplifier
The driver consists of two stages: the current-feedback
preaꢀplifier and the voltage-feedback buffer. To save
power, the preaꢀplifier uses a power supply of only
2.5V. The output swing of the preaꢀplifier is about
Rx
PORT
Tx
PORT
0Tx - 0.67Rx
RXP
1kΩ
2kΩ
3.0V . The buffer is designed as a pseudo-class-G
P-P
8Ω
OUT2
-Rx
-0.5Tx
aꢀplifier with a fixed gain of -3V/V. This buffer stage
eꢀploys two power supplies: a lower voltage supply,
2.5V, and a higher voltage supply, 5V. In the differ-
ential driver, two parallel aꢀplifiers provide the output
current to the load, as shown in Figure 7.
-0.0Rx
-Tx
(b) TRADITIONAL HYBRID CIRCUIT
Figure 6. Hybrid Circuit in the MAX9480
______________________________________________________________________________________ 11
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
This sꢀooth transition between the lower voltage aꢀpli-
fier and the higher voltage aꢀplifier guarantees no
glitch on the output signal, and ensures high linearity for
high output power, while at the saꢀe tiꢀe consuꢀing
ꢀiniꢀuꢀ power. The relation between the input voltage
and the output current of this pseudo-class-G buffer is
illustrated in Figure 8.
Typical Operating Circuit, the MAX9480 is coupled to
the phone line through just such a transforꢀer. The
total differential load for the MAX9480 is therefore 16Ω.
Active terꢀination is included on all devices in the
MAX9480 faꢀily (as explained above in the Output-
Impedance Synthesis section).
Receiver Channel Considerations
A step-up transforꢀer at the output of the differential
line driver has a step-down effect on signals received
froꢀ the line. A voltage attenuation equal to the inverse
of the turns ratio is realized in the receive channel. This
is an addition to the attenuation due to the hybrid cir-
cuitry itself (see the Hybrid Considerations section).
Thermal Protection and Power Dissipation
The MAX9480/MAX9481/MAX9482 are available in the
EP version of the TSSOP. The EP facilitates heat trans-
fer out of the package if the pad is soldered to a heat
sink ꢀade froꢀ an area of circuit board copper.
Connect this copper dissipation area to V . For a
EE
DMT-ꢀodulated signal with a crest factor greater than
or equal to 5.3, the power dissipation of the
MAX9480/MAX9481/MAX9482 should not exceed
700ꢀW; the 20-pin TSSOP-EP package with its EP
floating allows 714ꢀW peak power at +85°C. Hence,
heat sinking is not essential, but is desirable for attain-
ing optiꢀal electrical perforꢀance. Note that the part is
capable of 500ꢀA peak output current, which could
cause therꢀal shutdown in applications with elevated
aꢀbient teꢀperatures and/or signals with low crest fac-
tors. The therꢀal shutdown feature prevents the die
teꢀperature froꢀ exceeding +150°C. See Figure 9 for
a guide to power derating for each of the packages.
I
I
OUT
I
OUTB
Transformer Selection
Full-rate, central-office ADSL requires the transꢀission
of a +20.4dBꢀ (110ꢀW) DMT signal. The DMT signal
has a typical crest factor of 5.3, requiring the line driver
to provide peak line power of 35.4dBꢀ (3.4W). The
35.4dBꢀ peak line power translates to a 36V peak-to-
peak differential voltage on a 100Ω line. The output
swing available froꢀ the MAX9480 faꢀily of line drivers
I
OUTA
V
IN
Figure 8. Amplifier Output Characteristics
with a 5V supply is 15.0V , and hence a step-up
P-P
transforꢀer with turns ratio of 1:2.5 is needed. In the
5000
28-TSSOP, PAD TO V
EE
4000
+2.5V
QFN
20-TSSOP, PAD TO V
I
OUTA
LOWER
EE
VOLTAGE
AMPLIFIER
3000
2000
1000
0
I
OUT
-2.5V
+5V
V
IN
LOAD
HIGHER
28-TSSOP, PAD FLOATING
20-TSSOP, PAD FLOATING
VOLTAGE
AMPLIFIER
I
OUTB
-40
-15
10 35 60
TEMPERATURE (°C)
85
-5V
Figure 9. Maximum Power Dissipation vs. Temperature
Figure 7. Output Stage of Pseudo-Class-G Amplifier
12 ______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Circuits
RCVP
5V
V
2.5V
1.00kΩ
V
POUT1
CC
LP
IN1-
IN1+
MAX9480
OUT1
SHDN
DGND
8Ω
8Ω
RXM
RXP
1:2.5
PHONE LINE 100Ω
INPUT
OUT2
IN2+
IN2-
1.00kΩ
V
EE
V
POUT2
LM
-5V
-2.5V
RCVN
______________________________________________________________________________________ 13
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Circuits (continued)
1.0kΩ
250Ω
RCVP
5V
V
2.5V
1.20kΩ
1.00kΩ
1.00kΩ
V
POUT1
CC
LP
IN1-
IN1+
BOUT1
OUT1
SHDN
DGND
8Ω
8Ω
1:2.5
PHONE LINE 100Ω
INPUT
MAX9481
OUT2
IN2+
IN2-
BOUT2
V
EE
V
LM
POUT2
1.00kΩ
1.20kΩ
1.00kΩ
-5V
-2.5V
RCVN
250kΩ
1.0kΩ
14 ______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Typical Operating Circuits (continued)
RCVP
5V
2.5V
V
1.0kΩ
250Ω
V
RXP
CC
LP
RXIN1-
RXIN1+
POUT1
1.00kΩ
1.20kΩ
1.00kΩ
IN1-
IN1+
BOUT1
OUT1
SHDN
DGND
8Ω
8Ω
1:2.5
PHONE LINE 100Ω
INPUT
MAX9482
OUT2
IN2+
IN2-
BOUT2
1.20kΩ
1.0kΩ
1.00kΩ
250Ω
1.00kΩ
RXIN2+
RXIN2-
POUT2
V
EE
V
RXM
LM
-5V
-2.5V
RCVN
______________________________________________________________________________________ 15
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Pin Configurations (continued)
TOP VIEW
BOUT1
POUT1
IN1-
1
2
3
4
5
6
7
8
9
20
19
18
V
V
V
BOUT1
POUT1
IN1-
1
2
3
4
5
6
7
8
9
28
27
V
V
LM
LM
LP
LP
IN1-
IN1+
1
2
3
4
5
6
7
8
24
V
CC
26 N.C.
25
24 OUT1
CC
23 OUT1
IN1+
17 OUT1
IN1+
V
CC
DGND
SHDN
IN2+
22
21
V
V
EE
EE
MAX9481
MAX9482
DGND
SHDN
IN2+
16
15
14
13
12
11
V
V
DGND
SHDN
IN2+
EE
EE
23
22
V
EE
EE
MAX9482
20 OUT2
OUT2
V
IN2-
19
18
17
V
V
V
CC
LP
IN2-
V
IN2-
21 OUT2
CC
POUT2
BOUT2
POUT2
V
POUT2
20
19
18
V
V
V
LP
CC
LP
LM
BOUT2 10
V
BOUT2 10
RXP 11
LM
LM
TSSOV
RXIN1- 12
RXIN1+ 13
RXIN2+ 14
17 N.C.
16 RXM
15 RXIN2-
QFN
TSSOV
Chip Information
MAX9480 TRANSISTOR COUNT: 2557
MAX9481 TRANSISTOR COUNT: 2557
MAX9482 TRANSISTOR COUNT: 2607
PROCESS: Bipolar
16 ______________________________________________________________________________________
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Package Information
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 17
Low-Power, Low-Distortion, Central-Office
ADSL Drivers and Integrated Drivers/Receivers
Package Information (continued)
(The package drawing(s) in this data sheet ꢀay not reflect the ꢀost current specifications. For the latest package outline inforꢀation,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxiꢀ Integrated Products
Printed USA
is a registered tradeꢀark of Maxiꢀ Integrated Products.
相关型号：
MAX9482
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
MAXIM
MAX9482CGJ
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
MAXIM
MAX9482CGJ-T
Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, BIPolar, 5 X 5 MM, 0.90 MM HEIGHT, MO-220, QFN-32
MAXIM
MAX9482CUI
Low-Power, Low-Distortion, Central-Office ADSL Drivers and Integrated Drivers/Receivers
MAXIM
MAX9482EUI
Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, BIPolar, PDSO28, 4.4 MM, MO-153AET, TSSOP-28
MAXIM
©2020 ICPDF网 联系我们和版权申明