MAX9492 [MAXIM]
Multiple-Output Clock Generator with Spread Spectrum; 多输出时钟发生器，带有扩频
| 型号： | MAX9492 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multiple-Output Clock Generator with Spread Spectrum |
| 文件： | 总11页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3683; Rev 0; 5/05
Multiple-Output Clock Generator
with Spread Spectrum
General Description
Features
The MAX9492 frequency synthesizer is designed to
generate multiple clocks for clock distribution in net-
work routers or switches. The device provides a total of
six buffered clock outputs (CLK1 to CLK6). CLK1 is the
buffered output of the reference clock. CLK2 through
CLK6 are independently programmable to generate
eight different frequencies based on a 25MHz input
crystal: 133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All
the outputs are LVCMOS single-ended signals. Either a
25MHz crystal or an external clock can serve as the
input reference clock. The MAX9492 incorporates two
phase-locked loops (PLLs) with two internal loop filters.
ꢀ Five LVCMOS Outputs with Independent
Frequency Selections
ꢀ One Buffered Reference Clock Output
ꢀ Eight Selectable Frequencies: 133, 125, 83, 66,
62.5, 50, 33, and 25MHz
ꢀ Crystal or an Input-Clock-Based Clock Reference
2
ꢀ Output Frequency Programmed Through I C
Interface
ꢀ 0, -1.25%, or -2.5% Selectable Downspreading
Rate
Select the MAX9492’s output clock frequency by pro-
gramming on-chip registers through the MAX9492’s
I2C* interface. The device also features spread-spec-
trum capability to reduce electromagnetic interference
(EMI). This technique allows spreading the fundamental
energy over a wider frequency range, hence reducing
the respective energy amplitude. The output frequency
spectrum is downspread by -1.25% or -2.5%.
ꢀ Low Output Period Jitter
(Without Spread Spectrum) < 10ps
RMS
ꢀ <220ps Output-to-Output Skew
ꢀ Available in 20-Lead, 5mm x 5mm, TQFN Package
ꢀ +3.3V Supply
The MAX9492 operates from a 3.3V supply and is guar-
anteed over the extended temperature range (-40°C to
+85°C). The device is available in a space-saving,
20-pin, TQFN, 5mm x 5mm package.
ꢀ -40°C to +85°C Extended Temperature Range
Applications
Network Routers
Ordering Information
Telecom/Networking Equipment
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
Storage Area Networks/Network Attached
Storage
20 Thin QFN-EP**
MAX9492ETP -40°C to +85°C 5mm x 5mm x
T2055-3
0.8mm
**EP = Exposed pad.
Typical Operating Circuit and Pin Configuration appear at
end of data sheet.
2
*Purchase of I C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a
2
2
2
license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C
Standard Specification as defined by Philips.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Multiple-Output Clock Generator
with Spread Spectrum
ABSOLUTE MAXIMUM RATINGS
DD_
All Other Pins to GND.................................-0.3V to (V
Short-Circuit Duration (all LVCMOS outputs).............Continuous
V
to GND .........................................................-0.3V to +4.0V
Storage Temperature Range.............................-65°C to +165°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) ................................+300°C
+ 1.0V)
DD
ESD Protection (Human Body Model)................................. 2ꢀV
Continuous Power Dissipation (T = +70°C)
A
20-Pin TQFN (derate 20.8mW/°C above +70°C) ......1667mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= V
= +3.0V to +3.6V, T = -40°C to +85°C, unless otherwise noted. Typical values at V
= V
= +3.3V, T = +25°C,
DDA A
DD
DDA
A
DD
with CLK1 at 25MHz, and all other CLK_ outputs at 133MHz.) (Note 1)
PARAMETER SYMBOL CONDITIONS
CLOCK INPUT (X1)
MIN
TYP
MAX
UNITS
Input High Level
V
2.0
-20
V
V
IH1
Input Low Level
V
0.8
IL1
Input Current
I
, I
V _ = 0 to V
X DD
+20
µA
IL1 IH1
CLOCK OUTPUTS (CLK_)
V
0.2
-
DD
I
= -100µA
OH
Output High Level
V
V
V
OH
I
I
I
= -4mA
= 100µA
= 4mA
2.4
-60
2.5
OH
OL
OL
0.2
0.4
+69
5
Output Low Level
V
OL
Output Short-Circuit Current
Output Capacitance
I
CLK_ = V
(Note 2)
or GND
mA
pF
OS
DD
C
O
THREE-LEVEL INPUTS (SSC, SA0, SA1)
Input High Level
Input Low Level
Input Open Level
Input Current
V
V
V
IH2
V
0.8
1.90
+15
IL2
V
1.35
-15
V
IO2
I
, I
V
= 0 or V
= V
DD
µA
IL2 IH2
IL2
IH2
SERIAL INTERFACE (SCL, SDA) (Note 3)
0.7 x
Input High Level
Input Low Level
V
V
V
IH
V
DD
0.3 x
V
IL
V
DD
Input Leaꢀage Current
Low-Level Output
I
, I
-1
+1
0.4
10
µA
V
IH IL
V
I
= 4mA
OL
SINK
Input Capacitance
Ci
(Note 2)
pF
POWER SUPPLIES
Digital Power-Supply Voltage
Analog Power-Supply Voltage
Total Supply Current
V
3.0
3.0
3.6
3.6
76
V
DD
V
V
DDA
I
C = 10pF
60
18
mA
mA
DC
OD
L
Output Disabled Supply Current
I
All clocꢀ registers = 0x0F
24
2
_______________________________________________________________________________________
Multiple-Output Clock Generator
with Spread Spectrum
AC ELECTRICAL CHARACTERISTICS
(V
= V
= +3.0V to +3.6V, C = 10pF, unless otherwise noted. Typical values at V
= V
= +3.3V, T = +25°C, with CLK1 at
DDA A
DD
DDA
L
DD
25MHz and all other CLK_ outputs at 133MHz.) (Note 2)
PARAMETER SYMBOL
OUTPUTS (CLK_)
CONDITIONS
MIN
TYP
MAX
UNITS
Crystal Frequency
10
15
35
35
MHz
MHz
ppm
Input Frequency Range
Crystal Frequency Tolerance
External clocꢀ
∆f
A
-50
+50
Output-to-Output Sꢀew
Rise Time
t
Any two CLK_ outputs
220
2.5
2.5
60
ps
ns
ns
%
SKO
t
R1
20% V
80% V
to 80% V
to 20% V
1.9
1.3
DD
DD
DD
DD
Fall Time
t
F1
Duty Cycle
40
RMS (SSC = 0), CLK1 is disabled to high
impedance
Output Period Jitter
Power-Up Time
J
10
15
ps
ms
%
P
t
V
> 2.8V to PLL locꢀ
DD
2
PO
SSC = high
-2.5
-1.25
Frequency Spread
SSC = floating
SERIAL INTERFACE TIMING
(V
= V
= +3.3V, T = -40°C to +85°C.) (Note 1, Figure 1)
DDA A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clocꢀ
f
400
ꢀHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
0.6
µs
µs
µs
BUF
Hold Time, Repeated START
Condition
t
HD,STA
Repeated START Condition
Setup Time
t
SU,STA
STOP Condition Setup Time
Data Hold Time
t
0.6
15
µs
ns
ns
ns
µs
µs
SU,STO
HD,DAT
HD,DAT
t
t
(Note 4)
(Note 4)
900
900
Data Hold Time Slave
Data Setup Time
15
t
100
1.3
0.7
SU,DAT
SCL Clocꢀ Low Period
SCL Clocꢀ High Period
t
LOW
t
HIGH
Rise Time of SDA and SCL,
Receiving
20 +
t
(Notes 2, 5)
(Notes 2, 5)
300
300
ns
ns
R
0.1C
B
Fall Time of SDA and SCL,
Receiving
20 +
0.1C
t
F
B
_______________________________________________________________________________________
3
Multiple-Output Clock Generator
with Spread Spectrum
SERIAL INTERFACE TIMING (continued)
(V
= V
= +3.3V, T = -40°C to +85°C.) (Note 1, Figure 1)
DDA A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
250
50
UNITS
ns
20 +
Fall Time of SDA, Transmitting
t
(Notes 2, 6)
(Notes 2, 7)
(Note 2)
F,TX
0.1C
B
Pulse Width of Spiꢀe Suppressed
t
SP
0
ns
Capacitive Load for Each Bus
Line
C
400
pF
B
Note 1: All DC parameters tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 2: Guaranteed by design.
Note 3: No high output level is specified but only the output resistance to the bus. For I2C, the high-level voltage is provided by
pullup resistors on the bus.
Note 4: The device provides a hold time of at least 300ns for the SDA signal (referred to V of the SCL signal) to bridge the unde-
IL
fined region of SCL’s falling edge.
Note 5: C = total capacitance of one bus line in pF. t and t measured between 0.3 x V
and 0.7 x V
.
B
R
F
DD
DD
Note 6: Bus sinꢀ current is less than 6mA. C is the total capacitance of one bus line in pF. t and t are measured between 0.3 x
B
R
F
V
and 0.7 x V
.
DD
DD
Note 7: Input filters on the SDA and SCL inputs suppress noise spiꢀes less than 50ns.
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT vs. TEMPERATURE
(ALL OUTPUTS SET TO 133MHz)
62.0
FALL TIME vs. TEMPERATURE
(ALL OUTPUTS SET TO 133MHz)
RISE TIME vs. TEMPERATURE
(ALL OUTPUTS SET TO 133MHz)
2.0
1.8
1.6
1.4
1.2
1.0
2.5
2.3
2.1
1.9
1.7
1.5
61.6
61.2
60.8
60.4
60.0
59.6
59.2
58.8
58.4
58.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Multiple-Output Clock Generator
with Spread Spectrum
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
133MHz OUTPUT WAVEFORM
83MHz OUTPUT WAVEFORM
PERIOD JITTER vs. TEMPERATURE
MAX9492 toc05
MAX9492 toc06
20
3.3V
3.3V
16
133MHz
62.5MHz
33.3MHz
12
8
125MHz
4
0V
0V
0
2ns/div
2ns/div
-40
-15
10
35
60
85
TEMPERATURE (°C)
133MHz OUTPUT 0% DOWNSPREADING
PERIOD JITTER vs. FREQUENCY
DUTY CYCLE vs. TEMPERATURE
MAX9492 toc09
20
16
12
8
51.0
50.5
50.0
49.5
49.0
48.5
48.0
47.5
47.0
10dB/REF 0dBm
RBW = 10kHz
VBW = 10kHz
ATN = 20dB
CENTER = 133MHz
SPAN = 4MHz
33.3MHz
62.5MHz
133MHz
125MHz
4
0
25
50
75
100
125
150
-40
-15
10
35
60
85
FREQUENCY (MHz)
TEMPERATURE (°C)
133MHz OUTPUT WITH
0% AND 1.25% DOWNSPREADING
133MHz OUTPUT WITH
0% AND 2.5% DOWNSPREADING
MAX9492 toc10
MAX9492 toc11
10dB/REF 0dBm
VBW = 1kHz
CENTER = 133MHz
RBW = 100kHz
10dB/REF 0dBm
VBW = 1kHz
RBW = 100kHz
ATN = 20dB
ATN = 20dB
SPAN = 15MHz
CENTER = 133MHz SPAN = 15MHz
_______________________________________________________________________________________
5
Multiple-Output Clock Generator
with Spread Spectrum
Pin Description
PIN
NAME
GNDA
X1
FUNCTION
1
Analog Ground
2
Crystal Connection or Clocꢀ Input. If using a 25MHz crystal, connect it to X1 and X2. If using a reference
clocꢀ, connect the clocꢀ signal to X1 and leave X2 floating. See the Typical Operating Circuit.
3
X2
4
V
Power-Supply Input for Analog Circuits. Bypass to GNDA with a 0.1µF capacitor.
Power-Supply Input for Digital Circuits. Bypass to GND with a 0.1µF capacitor.
Serial Clocꢀ Input. Serial interface clocꢀ.
DDA
5, 13, 16
V
DD
6
7
SCL
SDA
Serial Data I/O. Data I/O of serial interface.
8, 20
9
GND
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
Digital Ground
Clocꢀ 1 Output. Buffered reference clocꢀ output.
Clocꢀ 2 Output. Frequency-selectable clocꢀ output.
Clocꢀ 3 Output. Frequency-selectable clocꢀ output.
Clocꢀ 4 Output. Frequency-selectable clocꢀ output.
Clocꢀ 5 Output. Frequency-selectable clocꢀ output.
Clocꢀ 6 Output. Frequency-selectable clocꢀ output.
10
11
12
14
15
Spread-Spectrum-Select Input. Selects the spectrum-spread percentage. When SSC is low, spread
spectrum is disabled. When SSC is floating, spread spectrum is set to -1.25%. When SSC is high, spread
spectrum is set to -2.5%.
17
SSC
18
19
EP
SA1
SA0
Address-Select Inputs for Serial Interface. SA0 and SA1 select the serial interface address, as shown in
Table 1. SA0 and SA1 are three-level inputs, maꢀing nine possible address combinations.
GND
Exposed pad. Connect to GND.
Block Diagram
V
V
DDA
DD
SCL
SDA
CLK1
CLK2
2
I C
SA0
SA1
MUX
266MHz
PLL1
DIVIDE BY
2, 4, 8
X1
X2
25MHz
OSC
250MHz
PLL2
DIVIDE BY
2, 3, 4, 5, 10
MUX
MUX
CLK5
CLK6
SSC
SPREAD
SPECTRUM
MAX9492
AGND
GND
6
_______________________________________________________________________________________
Multiple-Output Clock Generator
with Spread Spectrum
Power-Up State
Detailed Description
At power-up, the CLK1 output is enabled and free run-
ning, the CLK2 to CLK4 outputs are set at 33.3MHz,
and the other CLK outputs are disabled at logic-low.
The output states can be overridden by writing to the
registers through the I2C interface.
The MAX9492 frequency synthesizer is designed to gen-
erate multiple clocꢀs for clocꢀ distribution in networꢀ
routers or switches. The device provides a total of six
buffered clocꢀ outputs (CLK1 to CLK6). CLK1 is the
buffered output of the reference clocꢀ. CLK2 through
CLK6 are independently programmable to generate eight
different frequencies based on a 25MHz input crystal:
133, 125, 83, 66, 62.5, 50, 33, and 25MHz. All the outputs
are LVCMOS single-ended signals.
Serial Interface
The MAX9492 is programmed through its I2C serial
interface. This interface has a clocꢀ, SCL, and a bidi-
rectional data line, SDA. In an I2C system, a master,
typically a microcontroller, initiates all data transfers to
and from slave devices, and generates the clocꢀ to
synchronize the data transfers.
Select the MAX9492’s output frequency by program-
ming on-chip registers through the I2C interface. The
MAX9492 also features spread-spectrum capability to
reduce EMI. Output frequency spectrum can be down-
spread by -2.5% or -1.25%. The 25MHz reference
comes from either a crystal or an external clocꢀ. The
MAX9492 incorporates two PLLs with two internal loop
filters. The MAX9492 operates from a 3.3V supply.
The MAX9492 operates as a slave device. The timing of
the SDA and SCL signals is detailed in Figure 1. SDA
operates as both an input and an open-drain output. A
pullup resistor, typically 4.7ꢀΩ, is required on SDA. SCL
operates only as an input. A pullup resistor, typically
4.7ꢀΩ, is required on SCL.
Reference Frequency Input
The MAX9492 requires a reference frequency. The ref-
erence can be a 25MHz crystal or an external clocꢀ
signal. If using a 25MHz crystal, connect it across X1
and X2, and connect loading capacitors from X1 and
X2 to GND (refer to the crystal manufacturer’s specifi-
cation). If using an external clocꢀ, connect the signal to
X1 and leave X2 floating.
START and STOP Conditions
A master signals the beginning of a transmission with a
START condition by transitioning SDA from high to low
while SCL is high (Figure 2). When communication is
complete, a master issues a STOP condition by transi-
tioning SDA from low to high while SCL is high. The bus
is then free for another transmission.
SDA
t
BUF
t
t
SU,STA
SU,DAT
t
HD,STA
t
LOW
t
t
SU,STO
HD,DAT
SCL
t
HIGH
t
HD,STA
t
t
F
R
START
CONDITION
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. Serial-Interface Timing Diagram
_______________________________________________________________________________________
7
Multiple-Output Clock Generator
with Spread Spectrum
NOT ACKNOWLEDGE
A0 R/W
SDA
1
1
A4
A3
A2
A1
ACK
ACKNOWLEDGE
LSB
MSB
SCL
START
2
Figure 2. I C Address and Acknowledge
Bit Transfer
Device Address
One data bit is transferred during each SCL clocꢀ
cycle. SDA must remain stable during the high period
of SCL, as changes in SDA while SCL is high are
START and STOP control signals. Idle the interface by
pulling both SDA and SCL high.
The MAX9492 features a 7-bit device address, config-
ured by the two three-level address inputs, SA1 and
SA0. To select the device address, connect SA1 and
SA0 to V , GND, or leave floating, as indicated in
DD
Table 1. The MAX9492 has nine possible addresses,
allowing up to nine MAX9492 devices to share the
same interface bus.
After 8 bits are transferred, the receiving device gener-
ates an acꢀnowledge signal by pulling SDA low for the
entire duration of the 9th clocꢀ pulse. If the receiving
device does not pull SDA low, a not acꢀnowledge is
indicated (Figure 2).
Writing to the MAX9492
Writing to the MAX9492 begins with a START condition
(Figure 3). Following the START condition, each pulse
on SCL transfers 1 bit of data. The first 7 bits comprise
the device address (see the Device Address section).
The 8th bit is low to indicate a write operation. An
acꢀnowledge bit is then generated by the MAX9492,
signaling that it recognizes its address. The next 8 bits
form the register address byte (Table 2) and determine
which control register receives the following data byte.
The MAX9492 then generates another acꢀnowledge bit.
The data byte is then written into the addressed register
of the MAX9492. An acꢀnowledge bit by the MAX9492
followed by a required STOP condition by the master
completes the communication. To write to the device
again, the entire write procedure is repeated; I2C burst-
write mode is not supported by the MAX9492.
2
Table 1. Device I C Address Selection
SA0
Open
Low
SA1
Open
Open
Open
Low
DEVICE ADDRESS
110 1000
110 0100
High
Open
Low
110 0010
110 1100
Low
110 1001
High
Open
Low
Low
111 0000
High
High
High
111 0001
111 0010
High
111 0100
8
_______________________________________________________________________________________
Multiple-Output Clock Generator
with Spread Spectrum
MASTER-WRITE DATA STRUCTURE
START
DEVICE ADDRESS
R/W
0
REGISTER ADDRESS
DATA IN
STOP
S
1
1
A4 A3 A2 A1 A0
ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK
D6 D5 D4 D3 D2 D1 D0 ACK
P
D7
MASTER-READ DATA STRUCTURE
START
DEVICE ADDRESS
R/W
0
REGISTER ADDRESS
S
1
1
A4 A3 A2 A1 A0
ACK RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 ACK
DEVICE ADDRESS
1 A4 A3 A2 A1 A0
R/W
1
DATA OUT
ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
STOP
P
RS
1
S = START CONDITION
A_ = DEVICE ADDRESS
ACK = ACKNOWLEDGE
ACK = NOT-ACKNOWLEDGE
RA_ = REGISTER ADDRESS
D_ = DATA
DATA DIRECTION
= MASTER TO SLAVE
= SLAVE TO MASTER
P = STOP CONDITION
RS = REPEATED START
2
Figure 3. I C Interface Data Structure
Device Control Registers
Reading from the MAX9492
The MAX9492 has eight control registers. The register
addresses and functions are shown in Table 2. The first
seven registers are used to set the six outputs, with
register 0x00 controlling all outputs simultaneously, and
the rest are mapped to individual outputs. All other
addresses are reserved and are not to be used.
Reading from the MAX9492 registers begins with a
START condition and a device address with the write bit
set low, then the register address that is to be read, fol-
lowed by a repeated START condition and a device
address with the write bit set high, and finally the data
are shifted out (Figure 3). Following a START condition,
the first 7 bits comprise the device address. The 8th bit
is low to indicate a write operation (to write in the follow-
ing register address). An acꢀnowledge bit is then gener-
ated by the MAX9492, signaling that it recognizes its
address. The next 8 bits form the register address, indi-
cating the location of the data to be read, followed by
another acꢀnowledge, again generated by the
MAX9492. The master then produces a repeated START
condition and readdresess the device, with the R/W bit
high to indicate a read operation (Figure 3). The
MAX9492 generates an acꢀnowledge bit, signaling that it
recognizes its address. The data byte is then clocꢀed
out of the MAX9492. A final not-acꢀnowledge bit, gener-
ated by the master (not required), and a STOP condition,
also generated by the master, complete the communica-
tion. To read from the device again, the entire read pro-
cedure is repeated; I2C burst-read mode is not
supported by the MAX9492.
Table 2. Register Address Mapping
REGISTER
OUTPUT PORT
ADDRESS
00
01
Broadcast to all CLK registers
CLK1
CLK2
02
03
CLK3
04
CLK4
05
CLK5
06
CLK6
All others
Reserved
_______________________________________________________________________________________
9
Multiple-Output Clock Generator
with Spread Spectrum
Setting the Clock Frequencies
Spread-Spectrum Control
Each CLK_ output has an associated control register.
The contents of the registers determine the frequencies
of their associated outputs. Table 3 provides the fre-
quency mapping for the registers. CLK1 only responds
to the 25MHz and high-impedance settings in Table 3.
For example, writing 03h to the CLK1 control register
does not change CLK1’s output frequency to
133.3MHz. The CLK1 output continues to output a
buffered reference clocꢀ signal.
The MAX9492 features spread-spectrum output struc-
tures to spread radiated emissions over the frequency
band. A programmable triangle-wave generator injects
an offset element into the master oscillator to dither its
output by -1.25% or -2.5%. The dither is controlled by
the SSC input. When SSC is low, spread spectrum is
disabled. When SSC is floating, spread spectrum is set
to -1.25%. When SSC is high, spread spectrum is set
to -2.5%.
Power Supply
Table 3. Output Frequency Selection for
CLK1–CLK6
The MAX9492 uses a 3.0V to 3.6V power supply con-
nected to V , and 3.0V to 3.6V connected to V .
DDA
DD
Bypass V
and V
at the device with a 0.1µF
DD
DDA
BITS IN CLKn
REGISTERS
OUTPUT FREQUENCY
(MHz)
capacitor. Additionally, use bulꢀ bypass capacitors of
10µF where power enters the circuit board.
00
01
02
03
04
05
06
07
08
0F
Logic-Low
Applications Information
133.3
Board Layout Considerations
As with all high-frequency devices, board layout is criti-
cal to proper operation. Place the crystal as close as
possible to X1 and X2, and minimize parasitic capaci-
tance around the crystal leads. Ensure that the exposed
pad maꢀes good contact with GND.
125
83.3
66.6
62.5
50
33.3
25
Chip Information
PROCESS: BiCMOS
High Impedance
Typical Operating Circuit
Pin Configuration
+3.3V
+3.3V
TOP VIEW
µ
µ
0.1 F
0.1 F
V
DDA
V
DD
µ
0.1 F
15 14 13 12 11
V
DD
V
DD
µ
0.1 F
X1
V
DD
16
10 CLK2
10pF
10pF
25MHz
SSC 17
SA1 18
SA0 19
GND 20
9
8
7
6
CLK1
GND
SDA
SCL
MAX9492
MAX9492
CLK1
CLK6
X2
CLOCK
OUTPUTS
SERIAL
INTERFACE
SDA
SCL
SA0
SA1
SSC
EXPOSED PADDLE (GND)
1
2
3
4
5
AGND
GND
THIN QFN
10 ______________________________________________________________________________________
Multiple-Output Clock Generator
with Spread Spectrum
Package Information
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
XXXXX
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45¡
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
C
L
L1
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
21-0140
H
-DRAWING NOT TO SCALE-
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX. –0.15
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
DOWN
BONDS
ALLOWED
L
PKG.
CODES
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-1
T1655-2
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
**
**
**
**
A1
A3
b
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-2
T2055-3
T2055-4
T2055-5
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
D
E
**
**
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-1
T2855-2
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
L
**
**
**
**
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
40
T2855-3
T2855-4
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
N
ND
NE
16
20
28
32
4
4
5
5
7
7
8
8
10
10
T2855-5
T2855-6
T2855-7
T2855-8
**
**
**
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
NO
YES
YES
NO
NO
2.80
3.35
3.35
3.20
2.60 2.70
3.15 3.25
2.60 2.70 2.80
3.15 3.25 3.35
3.15 3.25 3.35
3.00 3.10 3.20
0.40
NOTES:
T2855N-1 3.15 3.25
**
**
**
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255-2
T3255-3
T3255-4
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
**
**
**
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
NO
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3, AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", –0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
H
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2005 Maxim Integrated Products
Printed USA
is a registered trademarꢀ of Maxim Integrated Products, Inc.
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