MAX9595_V01 [MAXIM]
Audio/Video Switch for Dual SCART Connector;
| 型号： | MAX9595_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Audio/Video Switch for Dual SCART Connector |
| 文件： | 总28页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3946; Rev 2; 5/07
Audio/Video Switch for Dual SCART Connector
General Description
Features
The MAX9595 dual SCART switch matrix routes audio
and video signals between an MPEG encoder and two
external SCART connectors under I2C control, and
meets the requirements of EN50049-1, IEC 933-1,
Canal+, and BSkyB standards.
♦ Video Outputs Drive 2V
into 150Ω
P-P
♦ Audio Outputs Drive 3V
into 10kΩ
RMS
♦ Clickless, Popless Audio Gain Control and
Switching
The video and audio channels feature input source
selection multiplexers, input buffers, and output buffers
for routing all inputs to selected outputs.
♦ Interrupt Output Detects Changes on Slow
Switching Input
♦ AC-Coupled Video Inputs with Internal Clamp and
The MAX9595 provides programmable gain control from
+5dB to +7dB in 1dB steps for red, green, and blue com-
ponent video signals. All other video outputs have a fixed
+6dB gain. Additional features include an internal luma
and chroma (Y/C) mixer that generates a composite
video signal (CVBS) to supply an RF modulator output,
and internal video reconstruction lowpass filters with
passband ripple between -1dB and +1dB from 100kHz to
5.5MHz. The MAX9595 TV audio channel features click-
less switching and programmable volume control from -
56dB to +6dB in 2dB steps. The VCR audio output also
has programmable gain for -6dB, 0dB, or +6dB. The
device also generates monaural audio from left and right
Bias
♦ DC-Coupled Video Outputs
♦ Composite Video Signal Created Internally from
Y/C Inputs
♦ Internal Video Reconstruction Filters Provide
-40dB at 27MHz
♦ Single-Ended Audio Input
♦ Red/Chroma Switch for Bidirectional I/O
♦ I2C-Programmable RGB Gain from +5dB to +7dB
stereo inputs. All audio drivers deliver a 3.0V
mum output.
mini-
RMS
♦ I2C-Programmable Audio Gain Control from +6dB
to -56dB
The MAX9595 operates with standard 5V and 12V power
supplies and supports slow-switching and fast-switching
signals. The I2C interface programs the gain and volume
control, and selects the input source for routing.
♦ Meets EN50049-1, IEC 933-1, Canal+, and BSkyB
Requirements
The MAX9595 is available in a compact 48-pin thin
QFN package and is specified over the 0°C to +70°C
commercial temperature range.
Ordering Information
PIN-
PKG
PART
TEMP RANGE
PACKAGE
CODE
48 Thin QFN-EP*
(7mm x 7mm)
Applications
MAX9595CTM+ 0°C to +70°C
T4877-6
Satellite Set-Top Boxes
*EP = Exposed paddle.
+Denotes lead-free package.
Cable Set-Top Boxes
TVs
VCRs
DVDs
Pin Configuration and Typical Application Circuit appear at
end of data sheet.
System Block Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Audio/Video Switch for Dual SCART Connector
ABSOLUTE MAXIMUM RATINGS
V
V
V
to GNDVID........................................................-0.3V to +6V
to GNDAUD .....................................................-0.3V to +14V
INTERRUPT_OUT Current ................................................+50mA
All Video Outputs, TVOUT_FS to V , V
VID
12
,
VID AUD
to GNDAUD ....................................................-0.3V to +6V
GNDAUD, GNDVID................................................Continuous
All Audio Outputs to V , V , V
AUD
GNDAUD to GNDVID ............................................-0.1V to +0.1V
,
VID AUD 12
All Video Inputs, ENCIN_FS, VCRIN_FS,
SET to GNDVID......................................-0.3V to (V
All Audio Inputs,
AUDBIAS to GNDAUD .........................-0.3V to (V
SDA, SCL, DEV_ADDR,
INTERRUPT_OUT to GNDVID ..............................-0.3V to +6V
All Audio Outputs, TV_SS,
GNDVID, GNDAUD................................................Continuous
+ 0.3V)
+ 0.3V)
Continuous Power Dissipation (T = +70°C)
VID
A
48-Pin Thin QFN (derate 27mW/°C above +70°C) .....2105.3mW
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
AUD
VCR_SS to GNDAUD...............................-0.3V to (V + 0.3V)
12
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = 12V, V
= V
= 5V; 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
AUD
12
VID
AUD
V
to GNDAUD, and V
to GNDVID; SET = 100kΩ nominal, R = 150Ω, T = 0°C to +70°C, unless otherwise noted. Typical
LOAD A
12
VID
values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
Inferred from video gain test
Inferred from audio gain test
Inferred from slow switching levels
MIN
4.75
4.75
11.4
TYP
5.0
MAX
5.25
5.25
12.6
UNITS
V
V
V
Supply Voltage Range
V
VID
VID
V
Supply Voltage Range
V
5.0
AUD
AUD
Supply Voltage Range
V
12.0
12
12
All video output amplifiers are enabled,
no load
V
Quiescent Supply Current
Standby Supply Current
I
69
100
mA
mA
VID
VID_Q
VID_Q
All video output amplifiers are in shutdown,
and TV_FS_OUT driver is in shutdown,
no load
V
I
40
60
VID
V
V
Quiescent Supply Current
I
No load
No load
2.4
3.6
6
6
mA
mA
AUD
AUD_Q
Quiescent Supply Current
I
12_Q
12
VIDEO CHARACTERISTICS
CVBS and Y-C, 1V
input
+5.5
+4.5
+5.5
+6.5
-1
+6.0
+5.0
+6.0
+7.0
-0.52
40
+6.5
+5.5
+6.5
+7.5
+1
P-P
Voltage Gain
G_V
dB
RGB, 1V
control)
input, (programmable gain
P-P
LP Filter Passband Flatness
LP Filter Attenuation at 27MHz
Slew Rate
T
T
= +25°C, f = 5.5MHz, V = 1V
dB
dB
A
A
IN
P-P
= +25°C, f = 27MHz, V = 1V
30
IN
P-P
SR
V
V
= 2V
16
V/µs
ns
OUT
OUT
P-P
Settling Time
t
= 2V , settle to 0.1% (Note 2)
P-P
300
S
Gain Matching
AG
DG
DP
1V
input, between RGB or Y-C
-0.5
+0.5
dB
P-P
Differential Gain
5-step modulated staircase
5-step modulated staircase
0.4
0.2
%
Differential Phase
degrees
2
_______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 5V; 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, and V
to GNDVID; SET = 100kΩ nominal, R = 150Ω, T = 0°C to +70°C, unless otherwise noted. Typical
LOAD A
12
VID
values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
65
8
MAX
UNITS
Signal-to-RMS Noise
SNR_V
V
= 1V
dB
IN
P-P
f = 0.1MHz to 4.43MHz
f = 0.1MHz to 5.5MHz
Group Delay Variation
Sync-Tip Clamp Level
∆GD
ns
V
12
RGB, composite, and luma input, no signal,
no load
V_CLMP
1.21
1.9
Chroma Bias
V_BIAS Chroma input only, no signal, no load
Set by input current
PSRR_V DC, 0.5V
V
Droop
D
-2
+2
%
Power-Supply Rejection Ratio
48
4
dB
MΩ
kΩ
µA
P-P
CVBS or RGB video inputs, V > V_CLMP
IN
Input Impedance
Z
IN
Chroma video input. V = V_BIAS
11
5
IN
Input Clamp Current
I
V
= 1.75V
IN
2.5
8.0
CLMP
RP
Enable VCR_R/C_OUT and TV_R/C_OUT
pulldown through I2C, (see registers 7 and 9
for loading register details)
Pulldown Resistance
10
Ω
RGB, composite, and luma, no signal,
no load
1.08
2.27
-50
Output Pin Bias Voltage
Crosstalk
V
V
OUT
Chroma, no signal, no load
Between any two active inputs, f = 4.43MHz,
XTLK
dB
dB
V
= 1V
P-P
IN
Mute Suppression
M_SPR_V f = 4.43MHz, V = 1V , on one input only
-50
IN
P-P
AUDIO CHARACTERISTICS (Note 3)
TV or VCR to stereo, gain = 0dB,
= 1V
-0.5
0
+0.5
V
IN
P-P
Voltage Gain (Measured From
Application Input)
G_A
dB
TV or VCR to mono, gain = 0dB, V = 1V
2.5
3.0
3.5
IN
P-P
ENC to stereo, gain = 0dB, V = 1V
3.02
6.02
3.52
6.52
4.02
7.02
IN
P-P
P-P
ENC to mono, gain = 0dB, V = 1V
IN
Gain Matching Between
Channels
∆G_A
∆A
Gain = 0dB, V = 1V
-0.5
0
+0.5
dB
dB
kHz
V
IN
P-P
f = 20Hz to 20kHz, 0.5V
gain = 0dB
input,
RMS
Flatness
0.01
0.5V
input, frequency where output is
RMS
Frequency Bandwidth
BW
230
-3dB referenced to 1kHz
Input DC Level (Excluding
Encoder Inputs which are Hi-Z)
0.2308
x V
12
V
Gain = 0dB
IN
_______________________________________________________________________________________
3
Audio/Video Switch for Dual SCART Connector
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 5V; 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, and V
to GNDVID; SET = 100kΩ nominal, R = 150Ω, T = 0°C to +70°C, unless otherwise noted. Typical
LOAD A
12
VID
values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Single-ended inputs, f = 1kHz, THD < 1%
3
Input Signal Amplitude
(Measured from Application
Input)
V
V
RMS
IN_AC
ENC inputs single-ended, f = 1kHz,
THD < 1%
1.31
0.1
Single ended: VCR_INR, VCR_INL, TV_INR,
TV_INL
Input Resistance (Measured at
Parts Input)
R
IN
MΩ
Encoder, ENC_INL, ENC_INR
0.1
0.5 x
Output DC Level
V
V
= 0V
IN
V
OUT_DC
V
12
Signal-to-Noise Ratio (Measured
from Application Input)
f = 1.0kHz, 1V
gain = 0dB, 20Hz to 20kHz
application input,
RMS
SNR_A
95
dB
R
R
= 10kΩ, f = 1.0kHz, 0.5V
output
0.004
0.004
1
LOAD
RMS
Total Harmonic Distortion Plus
Noise
THD+N
ZO
%
= 10kΩ, f = 1.0kHz, 2V
output
LOAD
RMS
Output Impedance
f = 1kHz
Ω
1.414V
input, programmable gain to TV
P-P
SCART volume control range extends from
-56dB to +6dB
1.5
5.5
2
2.5
6.5
Volume Attenuation Step
ASTEP
dB
1.414V
input, programmable gain to VCR
P-P
6
audio extends from -6dB to +6dB
From V f = 1kHz, 0.5V
,
P-P
12,
AUD_BIAS
75
75
(C
From V
= 47µF), gain = 0dB
Power-Supply Rejection Ratio
Mute Suppression
PSRR_A
dB
dB
, f = 1kHz, 0.5V
V ≥
P-P, AUD
AUD
+4.75V, V
≤ +5.25V, gain = 0dB
AUD
f = 1kHz, 0.5V
see register 1 for loading register details
input, set through I2C,
RMS
M_SPR_A
VCLIP
90
f = 1kHz, 2.5V
THD < 1%
input, gain = 6dB,
RMS
Audio Clipping Level
Left-to-Right Crosstalk
3.6
80
V
RMS
XTLK_LR f = 1kHz, 0.5V
input, gain = 0dB
dB
RMS
TV SCART to VCR SCART or VCR SCART
Crosstalk
XTLK_CC to TV SCART, f = 1kHz, 0.5V
gain = 0dB
input,
90
dB
RMS
4
_______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 5V; 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, and V
to GNDVID; SET = 100kΩ nominal, R = 150Ω, T = 0°C to +70°C, unless otherwise noted. Typical
LOAD A
12
VID
values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INTERFACE: SDA and SCL (Note 4)
Low-Level Input Voltage
High-Level Input Voltage
V
0
0.8
V
V
IL
V
2.6
IH
Hysteresis of Schmitt Trigger
Input
0.2
V
V
I
I
= 3mA
= 6mA
0.4
0.6
250
SINK
SDA Low-Level Output Voltage
V
OL
SINK
Output Fall Time for SDA Line
Spike Suppression
Input Current
400pF bus load
ns
ns
50
5
-10
+10
400
µA
pF
kHz
µs
Input Capacitance
SCL Clock Frequency
Hold Time
0
t
t
0.6
1.3
0.6
HD,STA
Low Period of SCL Clock
High Period of SCL Clock
t
µs
Low
t
µs
HIGH
Setup Time for a Repeated Start
Condition
0.6
µs
SU,STA
Data Hold Time
t
0
0.9
0.8
µs
ns
µs
HD,DAT
Data Setup Time
t
100
0.6
SU,DAT
SU,STO
Setup Time for Stop Condition
t
Bus Free Time Between a Stop
and Start
t
1.3
2.6
µs
BUF
OTHER DIGITAL PINS (Note 4)
DEV_ADDR Low Level
V
V
V
DEV_ADDR High Level
INTERRUPT_OUT Low Voltage
INTERRUPT_OUT sinking 1mA
= 5V
0.15
1
0.4
10
INTERRUPT_OUT High Leakage
Current
V
µA
INTERRUPT_OUT
SLOW SWITCHING SECTION (Note 4)
Input Low Level
0
2
V
V
Input Medium Level
Input High Level
4.5
9.5
7.0
V
V
12
Input Current
50
100
µA
_______________________________________________________________________________________
5
Audio/Video Switch for Dual SCART Connector
ELECTRICAL CHARACTERISTICS (continued)
(V = 12V, V
= V
= 5V; 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, and V
to GNDVID; SET = 100kΩ nominal, R = 150Ω, T = 0°C to +70°C, unless otherwise noted. Typical
LOAD A
12
VID
values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
10kΩ to ground, internal TV,
Output Low Level
0
1.5
V
11.4 < V < 12.6
12
10kΩ to ground, external 16/9,
Output Medium Level
Output High Level
5
6.5
V
V
11.4 < V < 12.6
12
10kΩ to ground, external 4/3,
10
V
12
11.4 < V < 12.6
12
FAST SWITCHING SECTION (Note 4)
Input Low Level
0
1
0.4
3
V
V
Input High Level
Input Current
1
10
0.2
2
µA
V
Output Low Level
I
I
= 0.5mA
0
0.01
0.75
SINK
Output High Level
= 20mA, V
- V
V
SOURCE
VID
OH
Fast Switching Output to RGB
Skew
(Note 5)
30
ns
Fast Switching Output Rise Time
Fast Switching Output Fall Time
150Ω to ground
150Ω to ground
30
30
ns
ns
Note 1: All devices are 100% tested at T = +25°C. All temperature limits are guaranteed by design.
A
Note 2: The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output.
Note 3: Maximum load capacitance is 200pF. All the listed parameters are measured at application’s inputs, unless otherwise
noted. See the Typical Application Circuits.
Note 4: Guaranteed by design.
Note 5: Difference in propagation delays of fast-blanking signal and RGB signals. Measured from 50% input transition to 50%
output transition. Signal levels to be determined.
Typical Operating Characteristics
(V = 12V, V
= V
= 5V, 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, V
to GNDVID no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at T = +25°C.)
12
VID
A
A
RGB LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
Y VIDEO LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
GROUP DELAY vs. FREQUENCY
120
100
80
60
40
20
0
4
3
4
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
100k
1M
10M
100k
1M
10M
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6
_______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Typical Operating Characteristics (continued)
(V = 12V, V
= V
= 5V, 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, V
to GNDVID no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at T = +25°C.)
12
VID
A
A
RGB SMALL-SIGNAL BANDWIDTH
vs. FREQUENCY
Y VIDEO SMALL-SIGNAL BANDWIDTH
vs. FREQUENCY
VIDEO CROSSTALK vs. FREQUENCY
4
3
4
3
0
-20
2
2
1
1
0
0
-40
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
-60
-80
-100
100k
1M
10M
100k
1M
10M
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
AUDIO CROSSTALK
vs. FREQUENCY
AUDIO LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
AUDIO TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
0
4
0
V
= 0.5V
RMS
R = 10kΩ TO GNDAUD
IN
L
V
= 0.5V
RMS
IN
3
2
R = 10kΩ TO GNDAUD
L
-20
-40
0.1
0.01
1
AMPLITUDE = 3.0V
RMS
0
AMPLITUDE = 0.5V
RMS
-60
-1
-2
-3
-4
-5
-6
-80
0.001
-100
AMPLITUDE = 2.0V
RMS
-120
0.0001
1
0.01
0.1
10
100
1
10
100
1000
0.1
0.01
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
V
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
VID
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
80
ALL VIDEO OUTPUT AMPLIFIERS ENABLED
NO LOAD
75
70
65
60
55
50
WITH RESPECT TO V
12
WITH RESPECT TO V
AUD
-100
0.01
0.1
1
10
100
0
25
50
75
FREQUENCY (kHz)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Audio/Video Switch for Dual SCART Connector
Typical Operating Characteristics (continued)
(V = 12V, V
= V
= 5V, 0.1µF X5R capacitor in parallel with a 10µF aluminum electrolytic capacitor from V
to GNDAUD,
12
VID
AUD
AUD
V
to GNDAUD, V
to GNDVID no load, T = 0°C to +70°C, unless otherwise noted. Typical values are at T = +25°C.)
12
VID
A
A
V
VID
STANDBY QUIESCENT SUPPLY
CURRENT vs. TEMPERATURE
V
12
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
V
AUD
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
50
45
40
35
30
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ALL VIDEO OUTPUT AMPLIFIERS DISABLED
0
25
50
75
0
25
50
75
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT CLAMP AND BIAS LEVEL
vs. TEMPERATURE
INPUT CLAMP CURRENT
vs. TEMPERATURE
2.5
2.3
2.1
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
V
= 1.75V
IN
BIAS
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
BOTTOM LEVEL
CLAMP
0
25
50
75
0
25
50
75
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT CLAMP CURRENT
vs. INPUT VOLTAGE
OUTPUT BIAS VOLTAGE
vs. TEMPERATURE
0.5
0.4
3.0
2.5
2.0
1.5
1.0
0.5
0
CHROMA
0.3
0.2
0.1
0
RGB, LUMA, CVBS
-0.1
-0.2
-0.3
-0.4
-0.5
0
1
2
3
4
5
0
25
50
75
INPUT VOLTAGE (V)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Pin Description
PIN
NAME
FUNCTION
1
2
SDA
SCL
Bidirectional Data I/O. I2C -compatible, 2-wire interface data input/output. Output is open drain.
Serial Clock Input. I2C -compatible, 2-wire clock interface.
Device Address Set Input. Connect to GNDVID to set write and read addresses of 94h or 95h,
3
4
5
DEV_ADDR
ENC_INL
respectively. Connect to V
to set write and read address of 96h or 97h, respectively.
VID
Digital Encoder Left-Channel Audio Input
Interrupt Output. INTERRUPT_OUT is an open-drain output that goes high impedance to
indicate a change in the slow switch lines, TV_SS or VCR_SS.
INTERRUPT_OUT
6
7
ENC_INR
N.C.
Digital Encoder Right-Channel Audio Input
No Connection. Not internally connected.
VCR SCART Right-Channel Audio Input
VCR SCART Left-Channel Audio Input
TV SCART Right-Channel Audio Input
TV SCART Right-Channel Audio Input
Audio Ground
8
VCR_INR
VCR_INL
TV_INR
TV_INL
9
10
11
12
GNDAUD
Audio Input Bias Voltage. Bypass AUD_BIAS with a 47µF capacitor and a 0.1µF capacitor to
AUDGND.
13
14
AUD_BIAS
Audio Supply. Connect to a +5V supply. Bypass with a 10µF aluminum electrolytic capacitor in
parallel with a 0.47µF low-ESR ceramic capacitor to GNDAUD.
V
AUD
15
16
17
18
19
20
21
22
23
VCR_OUTR
VCR_OUTL
RF_MONO_OUT
TV_OUTL
VCR SCART Right-Channel Audio Output
VCR SCART Left-Channel Audio Output
RF Modulator Mono Audio Output
TV SCART Left-Channel Audio Output
TV SCART Right-Channel Audio Output
TV_OUTR
V
+12V Supply. Bypass V with a 10µF capacitor in parallel with a 0.1µF capacitor to ground.
12
12
TV_SS
VCR_SS
SET
TV SCART Bidirectional Slow-Switch Signal
VCR SCART Bidirectional Slow-Switch Signal
Filter Cutoff Frequency Set Input. Connect 100kΩ resistor from SET to ground.
Video and Digital Supply. Connect to a +5V supply. Bypass with a 0.01µF capacitor to GNDVID.
24, 36
V
VID
V
also serves as a digital supply for the I2C interface.
VID
25
26
VCRIN_FS
ENCIN_FS
VCR SCART Fast-Switching Input
Digital Encoder Fast-Switching Input
TV SCART Fast-Switching Output. This signal is used to switch the TV to its RGB inputs for on-
screen display purposes.
27
TVOUT_FS
28
29
30
GNDVID
Video Ground
RF_CVBS_OUT
RF Modulator Composite Video Output. Internally biased at 1V.
TV_Y/CVBS_OUT TV SCART Luma/Composite Video Output. Internally biased at 1V.
TV SCART Red/Chroma Video Output. Internally biased at 1V for red video signal and 2.2V for
chroma video signal.
31
TV_R/C_OUT
_______________________________________________________________________________________
9
Audio/Video Switch for Dual SCART Connector
Pin Description (continued)
PIN
NAME
FUNCTION
32
33
34
TV_G_OUT
TV_B_OUT
TV SCART Green Video Output. Internally biased at 1V.
TV SCART Blue Video Output. Internally biased at 1V.
VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output. Internally biased at 1V.
VCR SCART Red/Chroma Video Output. Internally biased at 1V for red video signals and 2.2V
for chroma video signal.
35
37
VCR_R/C_OUT
TV SCART Red/Chroma Video Input. Internally biased at 1V for red video signals, or 2.2V for
chroma video signals.
TV_R/C_IN
38
39
TV_Y/CVBS_IN
TV SCART Luma/Composite Video Input. Internally biased at 1.2V.
VCR SCART Luma/Composite Video Input. Internally biased at 1.2V.
VCR_Y/CVBS_IN
VCR SCART Red/Chroma Video Input. Internally biased at 1.2V for red video signals and 1.9V
for chroma video signals.
40
VCR_R/C_IN
41
42
43
VCR_G_IN
VCR_B_IN
VCR SCART Green Video Input. Internally biased at 1.2V.
VCR SCART Blue Video Input. Internally biased at 1.2V.
ENC_Y/CVBS_IN Digital Encoder Luma/Composite Video Input. Internally biased at 1.2V.
Digital Encoder Red/Chroma Video Input. Internally biased at 1.2V for red video signals, or 1.9V
for chroma video signals.
44
ENC_R/C_IN
45
46
47
48
ENC_G_IN
ENC_B_IN
ENC_Y_IN
ENC_C_IN
Digital Encoder Green Video Input. Internally biased at 1.2V.
Digital Encoder Blue Video Input. Internally biased at 1.2V.
Digital Encoder Luma Video Input. Internally biased at 1.2V.
Digital Encoder Chroma Video Input. Internally biased at 1.9V.
Exposed Paddle. Solder to the circuit board ground (GNDAUD) for proper thermal and electrical
performance.
EP
GNDAUD
using I2C control to make them terminations when
red/chroma is an input (see the Video Inputs section).
Detailed Description
The MAX9595 is a switch matrix that routes audio and
video signals between different ports using the I2C
interface. The ports consist of the MPEG decoder out-
put, and two SCART connectors for the TV and VCR.
Per EN50049 and IEC 933, the encoder can only input
a signal to the SCART connector, while TV and VCR
SCART connectors are bidirectional.
The audio section features an input buffer, a switching
matrix, volume- or gain-control circuitry, and output dri-
vers. The audio inputs are AC-coupled through a 0.1µF
capacitor. The TV output audio path has volume control
from -56dB to +6dB in 2dB steps, while the VCR output
audio path has volume control from -6dB to +6dB in
6dB steps. The MAX9595 can be configured to switch
inputs during a zero-crossing function to reduce clicks.
The MAX9595 circuitry consists of four major sections:
the video section, the audio section, the slow- and fast-
switching section, and the digital interface.
The slow-switching feature allows for bidirectional, tri-
level, slow-switching input and output signals at pin
VCR_SS and TV_SS, respectively. The slow-switching
signals from the VCR set the aspect ratio or video source
of the TV screen. If INTERRUPT_OUT is enabled, then
INTERRUPT_OUT changes to a high-impedance state if
any of the slow-switching inputs change logic levels. See
the Slow Switching section.
The video section consists of clamp and bias circuitry,
input buffers, reconstruction filters, a switch matrix, a
Y/C mixer, and output buffers. All video inputs are AC-
coupled through a 0.1µF capacitor to set an acceptable
DC level using clamp or bias networks. The bidirection-
al red/chroma outputs can be connected to ground
10 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Fast switching consists of two inputs from the encoder
and VCR, and one output to the TV to insert an on-
screen display (OSD). Fast switching is used to route
video signals from the VCR or from the encoder to the
TV. In addition, the fast-switching output can be config-
ured to a high or low voltage. Fast switching is con-
trolled through the I2C interface.
SCART Video Switching
The MAX9595 switches video signals between an MPEG
decoder, TV SCART, and VCR SCART. The video switch
includes reconstruction filters, multiplexed video ampli-
fiers, and a Y-C mixer driver for an RF modulator. See
Figure 1 for the functional diagram of the video section.
While the SCART connector supports RGB, S-video, and
composite video formats, RGB, and S-video typically
share a bidirectional set of SCART connector pins.
The digital block contains the 2-wire interface circuitry,
control, and status registers. The MAX9595 can be
configured through an I2C-compatible interface.
DEV_ADDR sets the I2C-compatible address.
VCR_Y/CVBS_OUT
VCR_R/C_OUT
CLAMP/BIAS
TV_R/C_IN
x2
x2
FILTER
FILTER
CLAMP
TV_Y/CVBS_IN
CLAMP
CLAMP
VCR_B_IN
VCR_G_IN
PULLDOWN
VCRRCOUT
N
CLAMP/BIAS
VCR_R/C_IN
VCRIN_FS
VGA
0.7V
5dB, 6dB, OR 7dB
TV_R/C_OUT
FILTER
CLAMP
CLAMP
VCR_Y/CVBS_IN
ENC_Y/CVBS_IN
ENC_R/C_IN
ENC_G_IN
PULLDOWN
TVRCOUT
N
VGA
CLAMP/BIAS
CLAMP
5dB, 6dB, OR 7dB
FILTER
FILTER
TV_G_OUT
TV_B_OUT
ENC_B_IN
CLAMP
VGA
5dB, 6dB, OR 7dB
CLAMP
ENC_Y_IN
ENCIN_FS
0.7V
BIAS
ENC_C_IN
BIAS
TV_Y/CVBS_OUT
x2
x1
0V
MAX9595
TVOUT_FS
5V
FILTER
2kΩ
2kΩ
MIXER
V
x2
RF_CVBS_OUT
12
TV_SS
INTERRUPT_OUT
SW/MONITOR
VCR_SS
Figure 1. MAX9595 Video Section Functional Diagram
______________________________________________________________________________________ 11
Audio/Video Switch for Dual SCART Connector
75Ω resistor to ground. Thus, a ground state is provid-
ed by an active pulldown to GNDVID on the red/chroma
output to support the bidirectional chroma or red I/O,
turning the output source resistors into terminations
(see Figure 2). The active pulldown also provides the
“Mute Output” function, and disables the deselected
video outputs. The “Mute Output” state is the default
power-on state for video.
Video Inputs
All video inputs are AC-coupled with an external 0.1µF
capacitor. Either a clamp or bias circuit sets the DC
input level of the video signals. The clamp circuit posi-
tions the sync tip of the composite (CVBS), the compo-
nent RGB, or the S-video luma signal. If the signal does
not have a sync tip, then the clamp positions the mini-
mum of the signal at the clamp voltage. The bias circuit-
ry is used to position the S-video chroma signal at
midlevel of the luma (Y) signal. On the video inputs that
can receive either a chroma or a red video signal, the
bias or clamp circuit is selected through I2C. See Tables
3–12 for loading register details.
For high-quality home video, the MPEG decoder, VCR,
and TV use the S-video format. The MAX9595 supports
S-video signals as an input from the VCR, the MPEG
decoder, and the TV, and also as a separately switch-
able output to the TV and VCR. Because S-video sup-
port was not included in the original specifications of
the SCART connector, the luma (Y) signal of S-video
and the CVBS signal share the same SCART connector
pins. If S-video is present, then a composite signal
must be created from the Y and C signals to drive the
RF_CVBS_OUT pin. For S-video, loop-through is not
possible since the chroma SCART port is used for both
input and output.
The MPEG decoder and VCR uses the RGB format and
fast switching to insert an on-screen display (OSD), usu-
ally text, onto the TV. The MAX9595 supports RGB as an
input from either the VCR or the MPEG decoder and as
an output only to the TV. The red video signal of the
RGB format and the chroma video signal of the S-VHS
format share the same SCART connector pin. Therefore,
RGB and S-video signals cannot be present at the same
time. Loop-through is possible with a composite video
signal but not with RGB signals because the RGB
SCART pins are used for both input and output.
The MAX9595 supports composite video (CVBS) for-
mat, with inputs from the VCR, MPEG decoder, and TV.
Full loop-through is possible to the TV and VCR only,
since the MPEG decoder SCART connector has sepa-
rate input and output pins for the CVBS format.
In SCART, there is the possibility of a bidirectional use
of the red/chroma pin. When using the red/chroma pin
as an input port, terminate the red/chroma output with a
0.1µF
0.1µF
MAX9595
MAX9595
75Ω
TV_R/C_OUT
75Ω
TV_R/C_OUT
PIN 15
PIN 15
PIN 13
PIN 13
N
N
SCART
CABLE
PULLDOWN
PULLDOWN
TV_R/C_IN
TV_R/C_IN
CLAMP/BIAS
CLAMP/BIAS
SCART
CONNECTORS
VIDEO INPUT
CLAMP
VIDEO INPUT
CLAMP
Figure 2. Bidirectional SCART Pins
12 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Video Outputs
The DC level at the video outputs is controlled so that
coupling capacitors are not required, and all of the
video outputs are capable of driving a DC-coupled,
150Ω, back-terminated coax load with respect to
ground. In a typical television input circuit (see Figure 3),
the video output driver on the SCART chip only needs
to source current. Users should note that, while the
SCART specification states 75Ω impedance, in prac-
tice, typical SCART chip implementations assume 75Ω
input resistance to ground (and source current from the
video output stage). Since some televisions and VCRs
use the horizontal sync height for automatic gain con-
trol, the MAX9595 accurately reproduces the sync
height to within 2%.
Fast Switching
The VCR or MPEG decoder outputs a fast-switching
signal to the display device or TV to insert on-screen
display (OSD). The fast-switching signal can also be
set to a constant high or low output signal through the
I2C interface. The fast-switching output can be set
through writing to register 07h.
Y/C Mixer
The MAX9595 includes an on-chip mixer to produce
composite video (CVBS) when S-video (Y and C) is pre-
sent. The composite video drives the RF_CVBS_OUT
output pin. The circuit sums Y and C signals to obtain the
CVBS component. A +6dB output buffer drives
RF_CVBS_OUT.
Video Reconstruction Filter
The encoder DAC outputs need to be lowpass-filtered
to reject the out-of-band noise. The MAX9595 inte-
grates the reconstruction filter. The filter is fourth order,
which is composed of two Sallen-Key biquad in cas-
cade, implementing a Butterworth-type transfer func-
tion. The internal reconstruction filters feature a 5.5MHz
cutoff frequency, and -30dB minimum attenuation at
27MHz. Note that the SET pin is used to set the accura-
cy of the filter cutoff frequency. Connect a 100kΩ resis-
tor from SET to ground.
Slow Switching
The MAX9595 supports the IEC 933-1, Amendment 1,
tri-level slow switching that selects the aspect ratio for
the display (TV). Under I2C-compatible control, the
MAX9595 sets the slow-switching output voltage level.
Table 1 shows the valid input levels of the slow-switch-
ing signal and the corresponding operating modes of
the display device.
Two bidirectional ports are available for slow-switching
signals for the TV and VCR. The slow-switching input
status is continuously read and stored in register 0Eh.
The slow-switching outputs can be set to a logic level
or high impedance by writing to registers 07h and 09h.
See Tables 8 and 10 for details. When enabled, INTER-
RUPT_OUT becomes high impedance if the voltage
level changes on TV_SS or VCR_SS.
SCART Audio Switching
Audio Inputs
The audio block has three stereo audio inputs from the
TV, the VCR, and the MPEG decoder SCART. Each input
has a 100kΩ resistor connected to an internally generat-
ed voltage equal to 0.23 x V , and is AC-coupled.
12
Table 1. Slow-Switching Modes
SET-TOP BOX
SLOW-SWITCHING
SIGNAL VOLTAGE
(V)
MODE
MAX9595
+5V
Display device uses an internal source
such as a built-in tuner to provide a
video signal
75Ω
BACK
TERMINATION
RESISTOR
TV
0 to 2
SCART
CABLE
VIDEO
OUTPUT
0.1µF
DC
RESTORE
Display device uses a video signal from
the SCART connector and sets the
display to 16:9 aspect ratio
75Ω
INPUT
4.5 to 7.0
9.5 to 12.6
5kΩ
TERMINATION
RESISTOR
Display device uses a signal from the
SCART connector and sets the display
to 4:3 aspect ratio
Figure 3. Typical TV Input Current
______________________________________________________________________________________ 13
Audio/Video Switch for Dual SCART Connector
Audio Outputs
Both right and left channels have a stereo output for the
TV and VCR SCART. The monaural output, which is a
mix of the TV right and left channels, drives the RF
modulator, RF_MONO_OUT. The monaural mixer, a
resistor summer, attenuates the amplitude of each of
the two signals by 6dB. A 12.54dB gain block follows
the monaural mixer. If the left and right audio channels
were completely uncorrelated, then a 9.54dB gain
block is used. See Figure 4 for the functional diagram
of the audio section.
Clickless Switching
The TV channel incorporates a zero-crossing detect
(ZCD) circuit that minimizes click noise due to abrupt
signal level changes that occur when switching
between audio signals at an arbitrary moment.
AUDIO INPUTS
AUDIO OUTPUTS
ZCD
ENC_INL
VOLUME CONTROL BYPASS
9.54dB
TV_INL
TV_OUTL
VCR_INL
VOLUME CONTROL
+6dB TO -56dB
MUTE
MUTE
MUTE
MUTE
12.54dB
Σ/2
ENC_INR
RF_MONO_OUT
VOLUME CONTROL BYPASS
TV_INR
9.54dB
VCR_INR
TV_OUTR
VOLUME CONTROL
+6dB TO -56dB
MUTE
GNDAUD
2
I C
9.54dB
-6dB, 0dB, OR +6dB
VCR_OUTL
MUTE
9.54dB
-6dB, 0dB, OR +6dB
VCR_OUTR
MUTE
MUTE IS AN INTERNAL SIGNAL
Figure 4. MAX9595 Audio Section Functional Diagram
14 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
To implement the zero-crossing function when switch-
ing audio signals, set the ZCD bit by loading register
00h through the I2C-compatible interface (if the ZCD bit
is not already set). Then set the mute bit low by loading
register 00h. Next, wait for a sufficient period of time for
the audio signal to cross zero. This period is a function
of the audio signal path’s low-frequency 3dB corner
Digital Section
Serial Interface
The MAX9595 uses a simple 2-wire serial interface
requiring only two standard microprocessor port I/O
lines. The fast-mode I2C-compatible serial interface
allows communication at data rates up to 400kbps or
400kHz. Figure 5 shows the timing diagram of the sig-
nals on the 2-wire interface.
(f
). Thus, if f
= 1kHz, the time period to wait for
L3dB
L3dB
a zero-crossing detect is 0.5kHz or 0.5ms.
The two bus lines (SDA and SCL) must be at logic-high
when the bus is not in use. The MAX9595 is a slave
device and must be controlled by a master device.
Pullup resistors from the bus lines to the supply are
required when push-pull circuitry is not driving the
lines.
Next, set the appropriate TV switches using register
01h. Finally, clear the mute bit (while leaving the ZCD
bit high) using register 00h. The MAX9595 switches the
signal out of mute at the next zero crossing.
To implement the zero-cross function for TV volume
changes, or for TV and phono volume bypass switch-
ing, simply ensure the ZCD bit in register 00h is set.
The logic level on the SDA line can only change when
the SCL line is low. The start and stop conditions occur
when SDA toggles low/high while the SCL line is high
(see Figure 5). Data on SDA must be stable for the
Volume Control
The TV channel volume control ranges from -56dB to
+6dB in 2dB steps. The VCR volume control settings
are programmable for -6dB, 0dB, and +6dB. These
gain levels are referenced to the application inputs,
where some dividers are present. With the ZCD bit set,
the TV volume control switches only at zero-crossings,
thus minimizing click noise. The TV outputs can bypass
the volume control. Likewise, the monaural output sig-
nal can be processed by the TV volume control or it
can bypass the volume control.
duration of the setup time (t
) before SCL goes
SU,DAT
high. Data on SDA is sampled when SCL toggles high
with data on SDA stable for the duration of the hold
time (t
). Note that data is transmitted in an 8-bit
HD,DAT
byte. A total of nine clock cycles are required to trans-
fer a byte to the MAX9595. The device acknowledges
the successful receipt of the byte by pulling the SDA
line low during the 9th clock cycle.
SDA
t
BUF
t
t
SU,STA
SU,DAT
t
HD,STA
t
SU,STA
t
t
HD,DAT
LOW
SCL
t
HD,STA
t
R
t
F
START CONDITION
REPEATED START CONDITION
STOP CONDITION
Figure 5. SDA and SCL Signal Timing Diagram
______________________________________________________________________________________ 15
Audio/Video Switch for Dual SCART Connector
2
Data Format of the I C Interface
Programming
Connect DEV_ADDR to ground to set the MAX9595
write and read address as shown in Table 2.
Write Mode
Slave Address
(Write address)
Register
Address
S
A
A
Data
A
P
P
Table 2. Slave Address Programming
ADDRESS PIN
STATE
WRITE
ADDRESS
Read Mode
READ ADDRESS
Slave
Slave
V
96h
94h
97h
95h
VID
Address
(Write
Register
Address
Address
(Read
S
A
A Sr
A Data NA
GNDVID
address)
address)
S = Start Condition, A = Acknowledge, NA = Not Acknowledge,
Sr = Repeat Start Condition, P = Stop Condition
Data Register Writing and Reading
Program the SCART video and audio switches by writ-
ing to registers 00h through 0Dh. Registers 00h through
0Eh can also be read, allowing read-back of data after
programming and facilitating system debugging. The
status register is read-only and can be read from
address 0Eh. See Tables 3–12 for register program-
ming information.
I2C Compatibility
The MAX9595 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs. SDA has an
open drain that pulls the bus line to a logic-low during
the 9th clock pulse. Figure 6 shows a typical I2C inter-
face application. The communication protocol supports
the standard I2C 8-bit communications. The MAX9595
address is compatible with the 7-bit I2C addressing
protocol only; 10-bit format is not supported.
INTERRUPT_OUT Signal
INTERRUPT_OUT is an open-drain output that
becomes high impedance when a change in any of the
slow-switch signals occurs. Clear INTERRUPT_OUT by
setting bit 4 of register 01h low.
Digital Inputs and Interface Logic
The I2C-compatible, 2-wire interface has logic levels
defined as V = 0.8V and V = 2.0V. All of the inputs
IL
IH
include Schmitt-trigger buffers to accept low-transition
interfaces. The digital inputs are compatible with 3V
CMOS logic levels.
Applications Information
Hot-Plug of SCART Connectors
The MAX9595 features high-ESD protection on all
SCART inputs and outputs, and requires no external
transient-voltage suppressor (TVS) devices to protect
against floating chassis discharge. Some set-top boxes
have a floating chassis problem in which the chassis is
not connected to earth ground. As a result, the chassis
can charge up to 500V. When a SCART cable is con-
nected to the SCART connector, the charged chassis
can discharge through a signal pin. The equivalent cir-
cuit is a 2200pF capacitor charged to 311V connected
through less than 0.1Ω to a signal pin. The MAX9595 is
soldered on the PC board when it experiences such a
discharge. Therefore, the current spike flows through
the ESD protection diodes and is absorbed by the sup-
ply bypass capacitors, which have high capacitance
and low ESR.
µC
SDA
SCL
SCL
V
VID
MAX9595
SDA
SCL
V
DD
DEVICE 1
SDA
SCL
To better protect the MAX9595 against excess voltages
during the cable discharge condition, place an addi-
tional 75Ω resistor in series with all inputs and outputs
to the SCART connector. For harsh environments where
15kV protection is needed, the MAX4385E and
MAX4386E single and quad high-speed op amps fea-
ture the industry’s first integrated 15kV ESD protection
on video inputs and outputs.
V
DD
DEVICE 2
SDA
2
Figure 6. Typical I C Interface Application
16 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Power Supplies and Bypassing
The MAX9595 features single 5V and 12V supply opera-
tion and requires no negative supply. The +12V supply
Layout and Grounding
For optimal performance, use controlled-impedance
traces for video signal paths and place input termina-
tion resistors and output back-termination resistors
close to the MAX9595. Avoid routing video traces par-
allel to high-speed data lines.
V
is for the SCART switching function. For pin V
,
12
12
place all bypass capacitors as close as possible with a
10µF capacitor in parallel with a 0.1µF ceramic capacitor.
Connect all V
pins together to +5V and bypass with a
AUD
The MAX9595 provides separate ground connections
for video, audio, and digital supplies. For best perfor-
mance, use separate ground planes for each of the
ground returns and connect all three ground planes
together at a single point. Refer to the MAX9595 evalu-
ation kit for a proven circuit board layout example.
10µF electrolytic capacitor in parallel with a 0.47µF low-
ESR ceramic capacitor to audio ground. Bypass V
AUD
pins with a 0.1µF capacitor to audio ground. Bypass
AUD_BIAS to audio ground with a 10µF electrolytic in
parallel with a 0.1µF ceramic capacitor.
Bypass V
with a 0.1µF ceramic capacitor to digital
DIG
ground. Bypass each V
to video ground with a 0.1µF
VID
ceramic capacitor. Connect V
ferrite bead to the +5V supply.
in series with a 200nH
VID
Table 3. Data Format for Write Mode
REGISTER
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(HEXADECIMAL)
TV volume
bypass
TV audio
output mute
00h
01h
ZCD
TV volume control
Interrupt
enable
VCR volume control
Not used
VCR audio selection
TV audio selection
02h
03h
04h
05h
Not used
Not used
Not used
Not used
TV_R/C_IN
clamp
06h
07h
08h
09h
RGB gain
TV_Y/
TV G and B video switch
TV video switch
RF_CVBS_
Not used
TV fast blank
(fast switching)
TV_R/C_OUT
ground
Set function TV
OUT switch CVBS_OUT switch
VCR_R/
C_IN clamp
ENC_R/
Not used
Not used
Not used
Not used
Not used
VCR video switch
C_IN clamp
VCR_R/C_OUT
ground
Not used
Not used
Not used
Set function VCR
0Ah
0Bh
0Ch
Not used
Not used
Not used
VCR_Y/
CVBS_OUT
enable
VCR_R/
C_OUT
enable
TV_Y/
CVBS_OUT
enable
TVOUT_ RF_CVBS_
TV_R/C_OUT
enable
TV_G_OUT TV_B_OUT
enable enable
0Dh
FS
OUT
enable
enable
______________________________________________________________________________________ 17
Audio/Video Switch for Dual SCART Connector
Table 4. Data Format for Read Mode
REGISTER
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(HEXADECIMAL)
Power-on
reset
0Eh
Thermal SHDN
Not used
VCR slow switch input
TV slow switch input
Table 5. Register 00h: TV Audio Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
1
Off
TV Audio Mute
On (power-on default)
+6dB gain
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+4dB gain
+2dB gain
0dB gain (power-on default)
-2dB gain
TV Volume Control
-4dB gain
-54dB gain
-56dB gain
0
1
Off
TV Zero-Crossing Detector
TV Volume Bypass
On (power-on default)
TV audio passes through volume
control (power-on default)
0
1
TV audio bypasses volume control
18 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Table 6. Register 01h: TV/VCR Audio Control
BIT
DESCRIPTION
COMMENTS
Encoder audio
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
VCR audio
Input Source for TV Audio
TV audio
Mute (power-on default)
Encoder audio
VCR audio
0
0
1
1
0
1
0
1
Input Source for VCR Audio
Interrupt Enable
TV audio
Mute (power-on default)
Clear INTERRUPT_OUT (power-on
default)
0
1
Enable INTERRUPT_OUT
0dB gain (power-on default)
+6dB gain
0
0
1
1
0
1
0
1
VCR Volume Control
-6dB gain
0dB gain
______________________________________________________________________________________ 19
Audio/Video Switch for Dual SCART Connector
Table 7. Register 06h: TV Video Input Control
BIT
DESCRIPTION
COMMENTS
TV_Y/CVBS_OUT
7
6
5
4
3
2
1
0
TV_R/C_OUT
ENC_R/C_IN
ENC_C_IN
VCR_R/C_IN
TV_R/C_IN
Not used
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
ENC_Y/CVBS_IN
ENC_Y_IN
VCR_Y/CVBS_IN
TV_Y/CVBS_IN
Not used
Input Sources for TV Video
Mute
Mute
Mute
Mute
Mute (power-on
default)
Mute (power-on
default)
1
1
1
TV_G_OUT
ENC_G_IN
VCR_G_IN
Mute
TV_B_OUT
ENC_B_IN
VCR_B_IN
Mute
0
0
1
0
1
0
Input Sources for TV_G_OUT and
TV_B_OUT
Mute (power-on
default)
Mute (power-on
default)
1
1
0
0
1
1
0
1
0
1
6dB (power-on default)
7dB
5dB
5dB
RGB Gain
DC restore clamp active at input (power-on
default)
0
1
TV_R/C_IN Clamp/Bias
Chrominance bias applied at input
20 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Table 8. Register 07h: TV Video Output Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
0
Low (< 2V), internal source (power-on default)
Medium (4.5V to 7V), external SCART source
with 16:9 aspect ratio
0
1
1
1
0
1
Set TV Function Switching
High impedance
High (> 9.5V), external SCART source with 4:3
aspect ratio
Normal operation, pulldown on TV_R/C_OUT
is off (power-on default)
0
1
TV_R/C_OUT Ground
Ground, pulldown on TV_R/C_OUT is on, the
output amplifier driving TV_R/C_OUT is turned
off
0
0
1
1
0
1
0
1
0V (power-on default)
Same level as ENC_FB_IN
Same level as VCR_FB_IN
Fast Blank (Fast Switching)
TV_Y/CVBS_OUT Switch
RF_CVBS_OUT Switch
V
VID
0
1
Composite video from the Y/C mixer is output
The TV_Y/CVBS_OUT signal selected in
register 06h is output (power-on default)
Composite video from the Y/C mixer is output
(power-on default)
0
1
The TV_Y/CVBS_OUT signal selected in
register 06h is output
Table 9. Register 08h: VCR Video Input Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
VCR_Y/CVBS_OUT
ENC_Y/CVBS_IN
ENC_Y_IN
VCR_R/C_OUT
ENC_R/C_IN
ENC_C_IN
0
0
0
0
0
1
0
1
0
VCR_Y/CVBS_IN
VCR_R/C_IN
Input Sources for VCR
Video
0
1
1
TV_Y/CVBS_IN
TV_R/C_IN
1
1
1
1
0
0
1
1
0
1
0
1
Not used
Not used
Mute
Mute
Mute
Mute
Mute (power-on default)
Mute (power-on default)
0
1
DC restore clamp active at input (power-on default)
Chrominance bias applied at input
VCR_R/C_IN Clamp/Bias
ENC_R/C_IN Clamp/Bias
0
1
DC restore clamp active at input (power-on default)
Chrominance bias applied at input
______________________________________________________________________________________ 21
Audio/Video Switch for Dual SCART Connector
Table 10. Register 09h: VCR Video Output Control
BIT
DESCRIPTION
COMMENTS
7
6
5
4
3
2
1
0
0
0
Low (< 2V), internal source (power-on default)
Medium (4.5V to 7V), external SCART source
with 16:9 aspect ratio
0
1
1
1
0
1
Set VCR Function
Switching
High impedance
High (> 9.5V), external SCART source with 4:3
aspect ratio
Normal operation, pulldown on VCR_R/C_OUT
is off (power-on default)
0
1
VCR_R/C_OUT Ground
Ground, pulldown on VCR_R/C_OUT is on,
the output amplifier driving VCR_R/C_OUT
is turned off
Table 11. Register 0DH: Output Enable
BIT
DESCRIPTION
COMMENTS
0
7
6
5
4
3
2
1
0
1
Off (power-on default)
RF_CVBS_OUT
TVOUT_FS
On
0
1
Off (power-on default)
On
0
1
Off (power-on default)
TV_Y/CVBS_OUT
TV_B_OUT
On
0
1
Off (power-on default)
On
0
1
Off (power-on default)
TV_G_OUT
On
0
1
Off (power-on default)
TV_R/C_OUT
VCR_R/C_OUT
VCR_Y/CVBS_OUT
On
0
1
Off (power-on default)
On
0
1
Off (power-on default)
On
22 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Table 12. Register 0Eh Status
BIT
DESCRIPTION
COMMENTS
0 to 2V, internal source
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
4.5V to 7V, external source with 16:9 aspect ratio
Not used
TV Slow Switch
Input
9.5V to 12.6V, external source with 4:3 aspect ratio
0 to 2V, internal source
0
0
1
1
0
1
0
1
4.5V to 7V, external source with 16:9 aspect ratio
Not used
VCR Slow Switch
Input
9.5V to 12.6V, external source with 4:3 aspect ratio
0
1
V
V
is too low for digital logic to operate
VID
VID
Power-On Reset
is high enough for digital logic to operate
0
1
The part is in thermal shutdown
Thermal Shutdown
The temperature is below the TSHD limit
______________________________________________________________________________________ 23
Audio/Video Switch for Dual SCART Connector
Typical Application Circuit
48
47
46
45
44
43
42
41
40
39
38
37
V
VID
0.1µF
10µF
SDA
SCL
1
SDA
SCL
36
V
VID
2
3
4
35
34
33
VCR_R/C_OUT_SC
VCR_R/C_OUT
VCR_Y/CVBS_OUT
TV_B_OUT
DEV_ADDR
DEV_ADDR
ENC_INL
VCR_Y/CVBS_OUT_SC
TV_B_OUT_SC
4.7kΩ
4.7kΩ
V
VID
ENC_INL_SC
4.7kΩ
INTERRUPT_OUT
TV_G_OUT
INTERRUPT_OUT
ENC_INR
5
6
32
31
TV_G_OUT_SC
4.7kΩ
TV_R/C_OUT_SC
ENC_INR_SC
VCR_INR_SC
TV_R/C_OUT
4.7kΩ
6.6kΩ
MAX9595
TV_Y/CVBS_OUT_SC
RF_CVBS_OUT_SC
TV_Y/CVBS_OUT
RF_CVBS_OUT
7
8
N.C.
30
29
VCR_INR
3.3kΩ
6.6kΩ
GNDVID
9
VCR_INL
TV_INR
28
VCR_INL_SC
TV_INR_SC
3.3kΩ
6.6kΩ
10
TVOUT_FS
27
26
TVOUT_FS_SC
ENCIN_FS
3.3kΩ
6.6kΩ
11
12
ENCIN_FS
TV_INL
TV_INL_SC
3.3kΩ
GNDAUD
VCRIN_FS 25
VCRIN_FS
13
14
15
16
17
18
19
20
21
22
23
24
10µF
10µF
10µF
10µF
10µF
0.1µF
47µF
100kΩ
10kΩ
10kΩ
V
AUD
V
12
V
VID
0.1µF
0.1µF
0.1µF
10µF
10µF
10µF
ALL CAPACITORS ARE 0.1µF AND ALL RESISTORS ARE 75Ω, UNLESS OTHERWISE NOTED.
24 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
System Block Diagram
V
12
V
VID
V
AUD
5V
5V
12V
RGB
RGB
CVBS, Y-C
R/L AUDIO
CVBS, Y-C
VIDEO
ENCODER
MAX9595
TV
SCART
FAST SWITCHING
CONNECTOR
CVBS/Y SWITCHES
AND FILTERS
SLOW SWITCHING
FAST SWITCHING
R/L AUDIO
AUDIO
DAC
RGB AND CHROMA
SWITCHES AND
FILTERS
ADDRESS
SCL
RGB
µC
CVBS, Y-C
R/L AUDIO
SDA
AUDIO SWITCHES
INTERRUPT_OUT
VCR SCART
CONNECTOR
SLOW SWITCHING
FAST SWITCHING
RF_CVBS
SLOW AND FAST
SWITCHING
RF MOD
MONO AUDIO
GNDAUD
EP
GNDVID
______________________________________________________________________________________ 25
Audio/Video Switch for Dual SCART Connector
Pin Configuration
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
V
TV_R/C_IN
TV_Y/CVBS_IN
VCR_Y/CVBS_IN
24
23
22
37
38
39
VID
SET
VCR_SS
21 TV_SS
20
19 TV_OUTR
18
VCR_R/C_IN 40
VCR_G_IN 41
V
12
VCR_B_IN
42
43
MAX9595
TV_OUTL
ENC_Y/CVBS_IN
17 RF_MONO_OUT
16 VCR_OUTL
ENC_R/C_IN 44
ENC_G_IN 45
VCR_OUTR
ENC_B_IN
ENC_Y_IN
ENC_C_IN
15
14
13
46
47
48
+
V
AUD
AUD_BIAS
2
3
4
5
6
7
8
9
10
1
11
12
THIN QFN
Chip Information
TRANSISTOR COUNT: 13,265
PROCESS: BiCMOS
26 ______________________________________________________________________________________
Audio/Video Switch for Dual SCART Connector
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
E
DETAIL A
(NE-1) X
e
E/2
k
e
e
D/2
C
(ND-1) X
D
D2
L
D2/2
b
L
E2/2
C
L
k
E2
C
C
L
L
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
1
F
21-0144
2
______________________________________________________________________________________ 27
Audio/Video Switch for Dual SCART Connector
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
2
F
21-0144
2
Revision History
Pages changed at Rev 1: 1, 2, 3, 6, 7, 13-16, 20, 21,
28
Pages changed at Rev 2: 1, 16, 25
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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