MAX96705AGTJ/V+_技术文档

EVALUATION KIT AVAILABLE

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

General Description

Beneﬁts and Features

● Ideal for Safety Camera Applications

The MAX96705A is a compact serializer with features

especially suited for automotive camera applications. It is

function and pin compatible with the MAX9271. In high-

bandwidth mode, the parallel-clock maximum is 116MHz

for 12-bit linear or combined HDR data types.

• Works with Low-Cost 50Ω Coax (100Ω STP) Cables

• Error Detection of Video/Control Data

• High-Immunity Mode for Robust Control-Channel

EMC Tolerance

• Retransmission of Control Data Upon Error

Detection

• Best-in-Class Supply Current: 93mA (max)

• Pre/Deemphasis Allows 15m Cable at Full Speed

• 32-Pin (5mm x 5mm) TQFN Package with 0.5mm

Lead Pitch

The embedded control channel operates at 9.6kbps

2

to 1Mbps in UART, I C, and mixed UART/I C modes,

allowing programming of serializer, deserializer, and

camera registers independent of video timing.

For driving longer cables, the IC has programmable

pre/deemphasis. Programmable spread spectrum is

available on the serial output. The serial output meets

ISO 10605 and IEC 61000-4-2 ESD standards. The core

supply range is 1.7V to 1.9V, and the I/O supply range is

1.7V to 3.6V.

● High-Speed Data Serialization for Megapixel

Cameras

• Up to 1.74Gbps Serial-Bit Rate

• 12.5MHz to 87MHz x 14 Bit + H/V Data

• 36.66MHz to 116MHz x 12-Bit + H/V Data

(through Internal Encoding)

The MAX96705A is available in a 32-pin (5mm x 5mm)

TQFN package with 0.5mm lead pitch, and operates over

the -40°C to +115°C temperature range.

● Multiple Modes for System Flexibility

2

• 9.6kbps to 1Mbps Control Channel in UART, I C

2

(with Clock Stretch), or UART-to-I C Modes

Applications

● Automotive Camera Applications

• Crosspoint Switch Accepts Any Input Bitmap

• Modes for Encoded VSYNC and HSYNC

● Reduces EMI and Shielding Requirements

Simpliﬁed Block Diagram

• Programmable Output Spread Spectrum

• Tracks Spread Spectrum Applied at the Parallel

Input

VIDEO

• 1.7V to 3.6V I/O Supply

● Peripheral Features for Camera Power-Up and

Verification

CAM

MAX96705A

MAX96706

GPU

• Built-In PRBS Generator for BER Testing

• Dedicated GPO for Camera Frame-Sync Trigger

and Other Uses

2

I C

• Remote/Local Wake-Up from Sleep Mode

● Meets AEC-Q100 Automotive Specification

• -40°C to +115°C Operating Temperature

• ±8kV Contact and ±15kV Air IEC 61000-4-2 and

ISO 10605 ESD Protection

Ordering Information appears at end of data sheet.

19-100105; Rev 0; 6/17

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

TABLE OF CONTENTS

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

32-Pin TQFN-EP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Serial Link Signaling and Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Video/Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Single/Double Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

HS/VS Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Error Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Bus Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Forward Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Reverse Control Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2

I C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Remote-End Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Clock-Stretch Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

2

Packet-Based I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Packet Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Control-Channel Error Detection and Packet Retransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Cable Type Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Video Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Shutdown/Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Maxim Integrated

│ 2

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

(

)

TABLE OF CONTENTS CONTINUED

Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Serialization Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Link Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

GMSL Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Parallel Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Bus Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Bus Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Crossbar-Switch Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Recommended Crossbar-Switch Program Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Timing-Generator Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Double-Mode Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

External High/Low Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Align from HS or DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Control-Channel Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

2

I C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

2

I C Bit Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Software Programming of Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2

I C Address Translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Configuration Blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Cascaded/Parallel Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Base Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

2

UART-to-I C Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Equation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Power-Supply Circuits and Bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

High-Frequency Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Maxim Integrated

│ 3

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

(

)

TABLE OF CONTENTS CONTINUED

Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Device Configuration and Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Internal Input Pulldowns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2

I C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

PRBS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

GPI/GPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Fast Detection of Loss-of-Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Entering/Exiting Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

LIST OF FIGURES

Figure 1. Serial-Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 2. Output Waveforms at OUT+, OUT-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 5. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

Figure 6. I C Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Input Setup and Hold Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10. Serializer Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 11. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13. 24-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 14. 27-Bit High-Bandwidth Mode Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 15. 32-Bit Mode Serial-Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16. Coax Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 17. Crossbar Switch Dataflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 18. Sync-Signal Format For Video-Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 19. State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 20. Crossbar-Switch Default Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

(

)

LIST OF FIGURES CONTINUED

Figure 21. GMSL-UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 22. GMSL-UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 23. SYNC Byte (0x79). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 24. ACK Byte (0xC3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

2

Figure 25. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0). . . . . . . . 76

2

Figure 26. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 1). . . . . . . . 76

Figure 27. Human Body Model ESD Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 28. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figure 29. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

LIST OF TABLES

Table 1. Reverse Control-Channel Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 2. Link-Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 3. Input Data-Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 4. Data-Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Table 5. Crossbar Output to Serial Link Map (D23:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 6. Crossbar Output to Serial Link Map (D31:24 and Special Packets) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 7. Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 8. Timing-Generator Parameter Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 9. Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 10. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Table 11. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table 12. Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 13. Three-Level Configuration Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 14. Suggested Connectors and Cables for GMSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Absolute Maximum Ratings

AVDD to EP* ........................................................-0.5V to +1.9V

DVDD to EP*........................................................-0.5V to +1.9V

IOVDD to EP*.......................................................-0.5V to +3.9V

OUT+, OUT- to EP*..............................................-0.5V to +1.9V

All Other Pins to EP*............................-0.5V to (IOVDD + 0.5V)

OUT+, OUT- Short Circuit to Ground or Supply........Continuous

Continuous Power Dissipation, T = +70°C

A

TQFN (derate 34.5 mW/°C above +70°C) .............2758.6mW

Operating Temperature Range..........................-40°C to +115°C

Junction Temperature......................................................+150°C

Storage Temperature Range............................ -40°C to +150°C

Soldering Temperature (reflow).......................................+260°C

*EP connected to IC ground.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Information

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

32-Pin TQFN-EP

Package Code

T3255+8

21-0140

90-0013

Outline Number

Land Pattern Number

Single-Layer Board:

Junction-to-Ambient Thermal Resistance (θ

)

47

JA

Junction-to-Case Thermal Resistance (θ

)

1.7

JC

Four-Layer Board:

Junction-to-Ambient Thermal Resistance (θ

Junction-to-Case Thermal Resistance (θ

29

JA

)

1.7

JC

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

DC Electrical Characteristics

(V

= V

= 1.7V to 1.9V, V

= 1.7V to 3.6V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to PCB

DVDD

AVDD

IOVDD L A

ground, typical values are at V

= V

= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)

DVDD

AVDD

IOVDD A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SINGLE-ENDED INPUTS (LCCEN, DIN_, PCLKIN, HS, VS, DE, BWS, DBL, HIM, MS, HVEN, PWDNB)

0.65 x

High-Level Input Voltage

V

IH

V

IOVDD

0.35 x

Low-Level Input Voltage

Input Current

V

IL

V

IOVDD

+20

I

V

= 0 to V

IOVDD

-20

μA

IN

THREE-LEVEL INPUTS (CONF0, CONF1)

0.7 x

High-Level Input Voltage

Low-Level Input Voltage

Mid-Level Input Current

V

IH

V

IOVDD

0.3 x

V

IL

V

IOVDD

Open or connected to a driver with output

in high impedance (Note 2)

I

-10

+10

μA

INM

Input Current

I

High or low, PWDNB high or low

-220

+220

µA

IN

SINGLE-ENDED OUTPUT (GPO)

High-Level Output

Voltage

V

IOVDD

- 0.2

V

I

= -2mA

= 2mA

V

OH

Low-Level Output

Voltage

V

0.2

OL

OS

OL

V

= 0V, V

= 3.0V to 3.6V

= 1.7V to 1.9V

-16

-3

-35

-12

-64

-21

O

IOVDD

Output Short-Circuit Current

I

mA

O

IOVDD

2

UART/I C and GENERAL-PURPOSE I/Os (RX/SDA, TX/SCL, GPIO_) with OPEN-DRAIN OUTPUTS

0.7 x

High-Level Input Voltage

Low-Level Input Voltage

V

IH

V

IOVDD

0.3 x

V

IL

V

IOVDD

V

= 0 to V

(Note 3),

IN

IOVDD

-110

-80

+5

RX/SDA, TX/SCL

Input Current

I

µA

IN

V

I

= 0 to V

(Note 3), GPIO_

= 1.7V to 1.9V

IOVDD

+5

0.4

0.3

10

IN

IOVDD

= 3mA, V

Low-Level Open-Drain

Output Voltage

OL

V

OL

I

= 3.0V to 3.6V

IOVDD

Input Capacitance

C

Each pin (Note 4)

pF

IN

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

DC Electrical Characteristics (continued)

(V

= V

= 1.7V to 1.9V, V

= 1.7V to 3.6V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to PCB

DVDD

AVDD

IOVDD L A

ground, typical values are at V

= V

= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)

DVDD

AVDD

IOVDD A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DIFFERENTIAL OUTPUTS (OUT+, OUT-)

Preemphasis oﬀ, high drive (Figure 1)

3.3dB preemphasis, high drive (Figure 2)

3.3dB deemphasis, high drive (Figure 2)

300

350

240

400

500

610

425

Diﬀerential Output Voltage

V

mV

OD

Change in V

Between

OD

Complementary Output

States

ΔV

25

1.56

25

mV

V

OD

Output Oﬀset Voltage

V

Preemphasis oﬀ

1.1

-60

1.4

OS

(V

+ V

)/2 = V

OUT+

OUT- OS

Change in V

Between

OS

Complementary Output

States

ΔV

mV

OS

V

or V

= 0V

OUT+

OUT-

Output Short-Circuit Current

I

mA

OS

= 1.9V

25

OUT+

OUT-

Magnitude of Diﬀerential

Output Short-Circuit Current

I

V

= 0V

OD

mA

OSD

Output-Termination

Resistance (Internal)

R

From OUT+ or OUT- to AVDD

45

54

63

Ω

O

REVERSE CONTROL-CHANNEL RECEIVER OUTPUTS (OUT+, OUT-)

Legacy

27

40

High-Switching Threshold

Low-Switching Threshold

V

mV

CHR

High immunity

Legacy

-27

-40

V

CLR

High immunity

SINGLE-ENDED SERIAL OUTPUTS (OUT+ or OUT-)

Preemphasis oﬀ, high drive (Figure 3)

375

435

300

-69

500

625

765

535

Single-Ended Output

Voltage

V

O

3.3dB preemphasis, high drive (Figure 2)

3.3dB deemphasis, high drive (Figure 2)

mV

V

or V

= 0V

OUT+

OUT-

Output Short-Circuit Current

I

mA

OS

V

or V

= 1.9V

32

63

Output-Termination

Resistance (Internal)

R

From OUT+ or OUT- to AVDD

45

54

Ω

O

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

DC Electrical Characteristics (continued)

(V

= V

= 1.7V to 1.9V, V

= 1.7V to 3.6V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP Connected to PCB

DVDD

AVDD

IOVDD L A

ground, typical values are at V

= V

= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)

DVDD

AVDD

IOVDD A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

POWER SUPPLY

f

= 116MHz, HIBW = 0, BWS = 0,

PCLKIN

default register values, AVDD + DVDD

(1.9V)

64

1.8

90

2.7

f

= 116MHz, HIBW = 0, BWS = 0,

PCLKIN

default register values, IOVDD (3.6V)

f

= 116MHz, HIBW = 0, BWS =

PCLKIN

0, default register values, IOVDD (1.9V)

0.45

0.69

(Note 4)

f

= 116MHz, HIBW = 1, BWS = 0,

PCLKIN

default register values, AVDD + DVDD

(1.9V)

62

1.8

83

2.7

Supply Current, Worst-Case

Pattern (Figure 4)

I

f

= 116MHz, HIBW = 1, BWS = 0,

PCLKIN

mA

WCS

default register values, IOVDD (3.6V)

f

= 116MHz, HIBW = 1, BWS =

PCLKIN

0, default register values, IOVDD (1.9V)

0.45

0.69

(Note 4)

f

= 87MHz, BWS = 1,

PCLKIN

default register values, AVDD + DVDD

61

85

(1.9V)

f

= 87MHz, BWS = 1, default

PCLKIN

1.4

2.0

register values, IOVDD (3.6V)

f

= 87MHz, BWS = 1, default

PCLKIN

0.37

0.61

register values, IOVDD (1.9V) (Note 4)

Wake-up receiver enabled

PWDNB = low

Sleep-Mode Supply Current

Power-Down Supply Current

ESD PROTECTION

I

40

15

100

70

µA

CCS

I

CCZ

Human Body Model, R = 1.5kΩ,

D

±8

C

= 100pF

S

IEC 61000-4-2, R = 330Ω, C = 150pF,

D

S

Contact Discharge

IEC 61000-4-2, R = 330Ω, C = 150pF,

Air Discharge

D

S

OUT+, OUT- (Note 5)

V

±15

±8

kV

ESD

ISO 10605, R = 2kΩ, C = 330pF,

D

S

Contact Discharge

ISO 10605, R = 2kΩ, C = 330pF,

D

S

±15

±4

Air Discharge

Human Body Model, R = 1.5kΩ,

D

All Other Pins (Note 6)

ESD

C

= 100pF

S

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

AC Electrical Characteristics

(V

= V

= 1.7V to 1.9V, V

= 1.7V to 3.6V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to PCB

DVDD

AVDD

IOVDD L A

ground, typical values are at V

= V

= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)

DVDD

AVDD

IOVDD A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PARALLEL CLOCK INPUT (PCLKIN)

BWS = 0, HIBW = 0, single input

BWS = 0, HIBW = 1, single input

BWS = 1, single input

16.66

36.66

12.5

33.32

73.33

25

58

43.5

116

87

Clock Frequency

f

MHz

PCLKIN

DC

BWS = 0, HIBW = 0, double input

BWS = 0, HIBW = 1, double input

BWS = 1, double input

Clock Duty Cycle

t

/t or t

/t (Note 4, Figure 5)

35

50

65

%

HIGH T

LOW T

Clock Transition Time

t

(Note 4, Figure 5)

4

ns

R, F

1.74Gbps bit rate, 300kHz sinusoidal jitter

(Note 4)

Clock Jitter

t

800

ps

J

2

I C/UART PORT TIMING

2

I C/UART Bit Rate

9.6

20

1000

150

kbps

ns

30% to 70%, C = 10pF to 100pF, 1kΩ

pullup to IOVDD

L

Output Rise Time

Output Fall Time

t

R

70% to 30%, C = 10pF to 100pF, 1kΩ

L

t

20

150

ns

F

pullup to IOVDD

2

I C TIMING (Figure 6)

Low f

I2CSLVSH = 10)

range: (I2CMSTBT = 010,

SCL

9.6

100

400

Mid f range: (I2CMSTBT 101,

SCL

SCL Clock Frequency

f

> 100

> 400

kHz

SCL

I2CSLVSH = 01)

High f range: (I2CMSTBT = 111,

I2CSLVSH = 00)

SCL

1000

f

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

4

SCL

START Condition Hold Time

Low Period of SCL Clock

High Period of SCL Clock

t

0.6

0.26

4.7

1.3

0.5

4

µs

HD:STA

t

LOW

t

0.6

0.26

4.7

0.6

0.26

HIGH

Repeated START Condition

Setup Time

t

SU:STA

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

AC Electrical Characteristics (continued)

(V

= V

= 1.7V to 1.9V, V

= 1.7V to 3.6V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to PCB

DVDD

AVDD

IOVDD L A

ground, typical values are at V

= V

= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)

DVDD

AVDD

IOVDD A

PARAMETER

SYMBOL

CONDITIONS

range, Low

MIN

0

TYP

MAX

UNITS

f

SCL

Data Hold Time

Data Setup Time

t

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

range, Low

range, Mid

range, High

0

ns

HD:DAT

0

250

100

50

t

ns

µs

SU:DAT

SU:STO

4

Setup Time for STOP

Condition

t

0.6

0.26

4.7

1.3

0.5

Bus-Free Time

Data Valid Time

t

BUF

3.45

0.9

t

VD:DAT

VD:ACK

0.45

3.45

0.9

Data Valid-Acknowledge

Time

t

0.45

50

Pulse Width of Spikes

Suppressed

t

50

ns

SP

50

Capacitive Load of Each

Bus Line

C

Note 4

100

pF

B

SWITCHING CHARACTERISTICS (Note 4)

20% to 80%, V , 400mV diﬀerential

OD

Diﬀerential/Single-Ended

Output Rise/Fall Time

t

R = 100Ω, 500mV single-ended R =

250

ps

R, F

L

50Ω, serial bit rate = 1.74Gbps

Total Serial-Output Jitter

(Diﬀerential Output)

1.74Gbps PRBS, measured at V

diﬀerential, preemphasis disabled (Figure 7)

= 0V

OD

t

0.25

0.15

0.25

0.15

UI

ns

TSOJ1

Deterministic Serial-Output

Jitter (Diﬀerential Output)

1.74Gbps PRBS, measured at V = 0V

OD

t

DSOJ2

diﬀerential, preemphasis disabled (Figure 7)

Total Serial-Output Jitter

(Single-Ended Output)

1.74Gbps PRBS, measured at V /2,

O

preemphasis disabled (Figure 3)

t

TSOJ1

Deterministic Serial-Output

Jitter (Single-Ended Output)

1.74Gbps PRBS, measured at V /2,

O

preemphasis disabled (Figure 3)

t

DSOJ2

Parallel Data-Input Setup

Time

t

(Figure 8)

2

SET

Maxim Integrated

│ 11

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

AC Electrical Characteristics (continued)

(V

= V

= 1.7V to 1.9V, V

= 1.7V to 3.6V, R = 100Ω ±1% (differential), T = -40°C to +115°C, EP connected to PCB

DVDD

AVDD

IOVDD L A

ground, typical values are at V

= V

= 1.8V, T = +25°C, unless otherwise noted.) (Note 1)

DVDD

AVDD

IOVDD A

PARAMETER

SYMBOL

t

CONDITIONS

MIN

TYP

MAX

UNITS

ns

Parallel Data Input Hold

Time

(Figure 8) (Note 4)

1

HOLD

GPI-to-GPO Delay

Serializer Delay

t

Deserializer GPI to serializer GPO (Figure 9)

350

µs

GPIO

Spread spectrum enabled (Figure 10)

(Notes 4, 7)

2065

t

Bits

SD

Spread spectrum disabled (Figure 10)

(Notes 4, 7)

1095

Link Start Time

Power-Up Time

t

(Figure 11)

(Figure 12)

2

7

ms

LOCK

t

PU

Note 1: Limits are 100% production tested at T = +115°C. Limits over the operating temperature range are guaranteed by design

A

and characterization, unless otherwise noted.

Note 2: To provide a mid-level voltage, leave the input open; or, if driven, put the driver in high-impedance state. High-impedance

leakage current must be less than ±10μA.

Note 3: I min is due to voltage drop across the internal pullup resistor.

IN

Note 4: Not production tested. Guaranteed by design.

Note 5: Specified pin to ground.

Note 6: Specified pin to all supply/ground.

Note 7: Measured in serial link bit times. Bit time = 1/(30 x f

) for BWS = 0; bit time = 1/(40 x f

) for BWS = 1.

PCLKIN

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Typical Operating Characteristics

(V

= V

= 1.8V, T = +25°C, unless otherwise noted.)

AVDD

DVDD

IOVDD

A

SUPPLY CURRENT vs.

PIXEL CLOCK FREQUENCY

(BWS = 0, HIBW = 0)

SUPPLY CURRENT vs.

PIXEL CLOCK FREQUENCY

(BWS = 0, HIBW = 1)

toc01

toc02

75

70

65

75

70

65

60

55

50

45

40

PRBS ON,

PE = 0xB to 0xF

PE = 0x1 to 0x4

PE = 0xB to 0xF

PE = 0x1 to 0x4

COAX

MODE,

SS OFF

COAX

MODE,

SS OFF

DBL = 0

60

55

50

45

40

DBL = 1

PE OFF

75

PE OFF

75

15

35

55

95

115

15

10

35

55

95

115

PIXEL CLOCK FREQUENCY (MHz)

SUPPLY CURRENT vs.

PIXEL CLOCK FREQUENCY

(BWS = 0, HIBW = 0)

SUPPLY CURRENT vs.

PIXEL CLOCK FREQUENCY

(BWS = 1, HIBW = 0)

toc04

toc03

65

60

55

50

45

40

70

65

60

55

50

45

40

PRBS ON,

COAX

DBL = 1

PE = 0xB to 0xF

ALL SPREAD VALUES

COAX

MODE,

PE OFF

MODE,

SS OFF

DBL = 0

PE = 0x1 to 0x4

DBL = 1

PE OFF

35

55

75

95

115

10

30

50

70

90

PIXEL CLOCK FREQUENCY (MHz)

SUPPLY CURRENT vs.

PIXEL CLOCK FREQUENCY

(BWS = 0, HIBW = 1)

SUPPLY CURRENT vs.

PIXEL CLOCK FREQUENCY

(BWS = 1, HIBW = 0)

toc05

toc06

65

60

55

50

45

40

65

60

55

50

45

40

PRBS ON,

ALL SPREAD

VALUES

ALL SPREAD VALUES

COAX

MODE,

PE OFF

COAX

MODE,

PE OFF

DBL = 0

DBL = 1

15

35

55

75

95

115

30

50

70

90

PIXEL CLOCK FREQUENCY (MHz)

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│ 13

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Typical Operating Characteristics (continued)

(V

= V

= 1.8V, T = +25°C, unless otherwise noted.)

AVDD

DVDD

IOVDD A

OUTPUT POWER SPECTRUM vs.

PCLK FREQUENCY

OUTPUT POWER SPECTRUM vs.

PCLK FREQUENCY

(VARIOUS SPREAD)

toc07

toc08

10

0

10

0

f_PCLKIN= 20MHz

f_PCLKIN= 50MHz

0.5% SPREAD

1% SPREAD

0.5% SPREAD

-10

-20

-30

-40

-50

-60

-70

-80

-10

-20

-30

-40

-50

-60

-70

-80

NO SPREAD

2% SPREAD

NO SPREAD

2% SPREAD

4% SPREAD

18.5 19.0 19.5 20.0 20.5 21.0 21.5

PIXEL CLOCK FREQUENCY (MHz)

47

48

49

50

51

52

53

PIXEL CLOCK FREQUENCY (MHz)

MAXIMUM PIXEL CLOCK FREQUENCY vs.

COAX CABLE LENGTH (BER < 10^-10

MAXIMUM PIXEL CLOCK FREQUENCY vs.

STP CABLE LENGTH

)

(BER < 10^-10

)

toc10

toc09

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

NO PE, DBL = 0

AEQ

NO PE, DBL = 0

AEQ

9.7dB EQ

NO EQ

4.3dB EQ

BER CAN BE AS LOW AS 10-12 FOR

CABLE LENGTHS LESS THAN 15m

BER CAN BE AS LOW AS 10-12 FOR

CABLE LENGTHS LESS THAN 15m

0

10

20

30

40

0

5

10

15

20

25

COAX CABLE LENGTH (m)

STP CABLE LENGTH (m)

SERIAL LINK SWITCHING PATTERN

WITH 4.4dB PREEMPHASIS

SERIAL LINK SWITCHING PATTERN

WITH 3.3dB PREEMPHASIS

(1.5Gbps, 10m STP CABLE)

(1.5Gbps, 20m COAX CABLE)

toc11

toc12

100mV/div

50mV/div

200ps/div

Maxim Integrated

│ 14

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Pin Conﬁguration

TOP VIEW

24 23 22 21 20 19 18 17

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

PCLKIN

DIN0

PWDNB

MS/HVEN

GPIO1/BWS

GPO/HIM

DIN1

DIN2

DVDD

DIN3

DIN4

DIN5

MAX96705A

IOVDD

DIN15/VS

DIN14/HS

+

DIN13/GPIO5/DE

1

2

3

4

5

6

7

8

TQFN

(5mm x 5mm)

Pin Description

REF

SUPPLY

NAME

FUNCTION

TYPE

POWER

1.8V Analog Power Supply. Bypass AVDD to EP with 0.1μF, and

0.001μF capacitors as close as possible to the device with the

smaller value capacitor closest to AVDD.

5, 22

AVDD

IOVDD

DVDD

Power

I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass

IOVDD to EP with 0.1μF and 0.001μF capacitors as close as

possible to the device with the smaller value capacitor closest to

IOVDD.

12

1.8V Digital Power Supply. Bypass DVDD to EP with 0.1μF, and

0.001μF capacitors as close as possible to the device with the

smaller value capacitor closest to DVDD.

29

Maxim Integrated

│ 15

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Pin Description (continued)

REF

SUPPLY

NAME

FUNCTION

TYPE

Exposed Pad. EP is internally connected to device ground. Must

connect EP to the PCB ground plane through a via array for proper

thermal and electrical performance.

EP

—

Power

HIGH-SPEED DIGITAL

Single Function

1

2

3

4

DIN6

Parallel Data Input. Internal pulldown to EP.

IOVDD

Digital

DIN7

DIN8

DIN9

Parallel Clock Input with Internal Pulldown to EP. Latches parallel

data inputs and provides the PLL reference clock.

25

PCLKIN

IOVDD

Digital

26

DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

Parallel Data Input. Internal pulldown to EP.

IOVDD

Digital

27

28

30

31

32

Multifunction

Parallel Data Input/GPIO. Defaults to parallel data input on power-

6

7

8

DIN10/GPIO2 up. Parallel data input has internal pulldown to EP. GPIO2 has an

IOVDD

Digital

open-drain input/output with internal 60kΩ pullup to IOVDD.

Parallel Data Input/GPIO. Defaults to parallel data input on power-

DIN11/GPIO3 up. Parallel data input has internal pulldown to EP. GPIO3 has an

open-drain input/output with internal 60kΩ pullup to IOVDD.

Parallel Data Input/GPIO. Defaults to parallel data input on power-

DIN12/GPIO4 up. Parallel data input has internal pulldown to EP. GPIO4 has an

open-drain input/output with internal 60kΩ pullup to IOVDD.

Parallel Data Input/GPIO/Data Enable with Internal Pulldown to EP.

DIN13/

GPIO5/DE

Defaults to parallel data input on power-up. GPIO5 has an open-

drain input/output with internal 60kΩ pullup to IOVDD. Data enable

input in high-bandwidth mode.

9

IOVDD

Digital

Parallel Data Input/Horizontal Sync with Internal Pulldown to EP.

Defaults to parallel data input on power-up. Defaults to horizontal-

sync input when HS/VS encoding is enabled, or when in high-

bandwidth mode.

10

11

DIN14/HS

DIN15/VS

Parallel Data Input/Vertical Sync with Internal Pulldown to EP.

Defaults to parallel data input on power-up. Defaults to vertical-

sync input when HS/VS encoding is enabled, or when in high-

bandwidth mode.

Multifunction Conﬁguration (from LCCEN)

Maxim Integrated

│ 16

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Pin Description (continued)

REF

SUPPLY

NAME

FUNCTION

TYPE

GPIO1/Bus-Width Select Input. Function is determined by the state

of LCCEN. GPIO1 (LCCEN = high): Open-drain, general-purpose

14

GPIO1/BWS input/output with internal 60kΩ pullup to IOVDD. BWS (LCCEN =

low): Input with internal pulldown to EP. Set BWS = low for 22-bit

input latch. Set BWS = high for 30-bit input latch.

IOVDD

Digital

Mode-Select/HS and VS Encoding Enable Input with Internal

Pulldown to EP. Function is determined by the state of LCCEN.

MS (LCCEN high): Set MS low to select base mode. Set MS high

to select bypass mode. HVEN: (LCCEN low): Set HVEN = high to

enable HS/VS encoding. Set HVEN = low to disable HS/VS

encoding.

15

17

MS/HVEN

IOVDD

Digital

Local Control-Channel Enable input with internal Pulldown to EP.

LCCEN = high enables the control-channel interface pins. LCCEN

= low disables the control-channel interface pins and selects an

LCCEN

alternate function on the indicated pins.

Transmit/Serial Clock/Double Mode. Function is determined by the

state of LCCEN. TX/SCL (LCCEN = high): Input/output with internal

30kΩ pullup to IOVDD. In UART mode, TX/SCL is the Tx output of

2

the serializer's UART. In I C mode, TX/SCL is the SCL input/output

24

TX/SCL/DBL

IOVDD

Digital

2

of the serializer's I C master/slave. TX/SCL has an open-drain

driver and requires a pullup resistor. DBL (LCCEN = low): Input with

internal pulldown to EP. Set DBL = high to use double-input mode.

Set DBL = low to use single-input mode.

Conﬁguration and Interface

General-Purpose Output/High-Immunity Mode Input with internal

Pulldown to EP. HIM is latched at power-up or when resuming from

power-down mode (PWDNB = low), and switches to GPO output

automatically after power-up. Connect HIM to IOVDD with a 30kΩ

resistor to set high, or leave open to set low. HIGHIMM can be

programmed to a diﬀerent value after power-up. HIGHIMM in the

deserializer must be set to the same value. GPO output follows the

state of the GPI (or INT) input on the GMSL deserializer. GPO is

low upon power-up or when PWDNB is low.

13

GPO/HIM

IOVDD

Digital

Active-Low, Power-Down Input with Internal Pulldown to EP.

To reduce power consumption, set PWDNB low to enter power-

down mode.

16

18

19

PWDNB

CONF0

CONF1

IOVDD

Digital

3-Level

Conﬁguration 0. Three-level conﬁguration input (Table 13). CONF0

pin value is latched at power-up, or when resuming from power-

down mode.

Conﬁguration 1. Three-level conﬁguration input (Table 13). CONF1

pin value is latched at power up or when resuming from power-

down mode.

20

21

OUT-

Inverting Coax/Twisted-Pair Serial Output.

Noninverting Coax/Twisted-Pair Serial Output

Digital

OUT+

Receive/Serial Data. Input/output with internal 30kΩ pullup to

IOVDD. In UART mode, RX/SDA is the Rx input of the serializer's

2

23

RX/SDA

UART. In I C mode, RX/SDA is the SDA input/output of the

IOVDD

Digital

2

serializer's I C master/slave. RX/SDA has an open-drain driver and

requires a pullup resistor.

Maxim Integrated

│ 17

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Functional Block Diagram

PCLKIN

SSPLL

MAX96705A

CLKDIV

DIN[9:0]

16 x 1

LATCH

(SINGLE)

VS

HS

TIMING

GENERATOR

DIN14/HS

DIN15/VS

CROSSPOINT

SWITCH

OUT+

VIDEO

OR

PARALLEL

TO SERIAL

SCRAMBLE/

HVEN/CRC/

PARITY/

ANY 32

INPUTS TO

ANY 22/24/30

OUTPUTS

CML TX

OUT-

16 x 2

LATCH

(DBL)

4

FIFO

ENCODE

DIN10/GPIO2

DIN11/GPIO3

DIN12/GPIO4

SYNC

FCC

4

RX

DBL

HIM

DIN13/GPIO5/DE

BWS

CONTROL

GPIO

REVERSE CONTROL

CHANNEL

UART/I²C

GPIO1/BWS

CONF[1:0] LCCEN MS/HVEN

PWDNB

TX/

SCL/

DBL

GPO/HIM

RX/

SDA

R /2

L

OUT+

V

OD

V

OS

OUT-

R /2

L

GND

((OUT+) + (OUT-))/2

OUT-

V

OS(+)

V

OS(-)

OUT+

DV = |V

- V

|

OS(+) OS(-)

OS

V

(+)

OD

V

OD

= 0V

V

OD(-)

V

OD(-)

DV = |V

- V

|

OD(+) OD(-)

OD

(OUT+) - (OUT-)

Figure 1. Serial-Output Parameters

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│ 18

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

OUT+

OUT-

V

OD(P)

V

OD(D)

V

OS

SERIAL-BIT

TIME

Figure 2. Output Waveforms at OUT+, OUT-

OUT+

OR

V /2

O

V

V /2

O

V

O

OUT-

Figure 3. Single-Ended Output Template

PCLKIN

DIN_

NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.

Figure 4. Worst-Case Pattern Input

t

T

V

IH MIN

t

HIGH

PCLKIN

V

IL MAX

t

R

t

F

t

LOW

Figure 5. Parallel Clock Input Requirements

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│ 19

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

START

CONDITION

(S)

BIT 7

MSB

(A7)

STOP

CONDITION

(P)

BIT 6

(A6)

BIT 0

(R/W)

ACKNOWLEDGE

(A)

PROTOCOL

t

HIGH

SU;STA

LOW

1/f

SCL

V

x 0.7

x 0.3

IOVDD

SCL

SDA

IOVDD

t

SP

t

BUF

t

f

r

V

x 0.7

x 0.3

IOVDD

t

SU;STO

HD;STA

t

HD;DAT

VD;DAT

VD;ACK

SU;DAT

2

Figure 6. I C Timing Parameters

800mV

P-P

t

TSOJ1

2

TSOJ1

2

Figure 7. Differential Output Template

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

V

IH MIN

PCLKIN

V

IL MAX

t

HOLD

SET

V

IH MIN

DIN_

IL MAX

NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.

Figure 8. Input Setup and Hold Times

V

IH_MIN

DESERIALIZER

GPI

V

IL_MAX

t

GPIO

t

GPIO

V

OH_MIN

SERIALIZER

GPO

V

OL_MAX

Figure 9. GPI-to-GPO Delay

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│ 21

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

EXPANDED TIME SCALE

DIN_

N

N+2

N+3

N+4

N+1

PCLKIN

OUT+/-

N-1

N

t

SD

FIRST BIT

LAST BIT

Figure 10. Serializer Delay

PCLKIN

t

LOCK

500Fs

SERIAL LINK INACTIVE

SERIAL LINK ACTIVE

REVERSE CONTROL CHANNEL

ENABLED

CHANNEL

DISABLED

REVERSE CONTROL CHANNEL

AVAILABLE

PWDNB MUST BE HIGH

Figure 11. Link Startup Time

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│ 22

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

PCLKIN

V

IH1

PWDNB

t

PU

POWERED UP,

SERIAL LINK INACTIVE

POWERED DOWN

POWERED UP, SERIAL LINK ACTIVE

500µs

REVERSE CONTROL

CHANNEL ENABLED

REVERSE CONTROL CHANNEL DISABLED

Figure 12. Power-Up Delay

Operating Modes

Detailed Description

The GMSL devices are configurable to operate in many

modes depending on the application. These modes allow

for a more efficient use of serial bandwidth. Most of these

settings are set during system design, and are configured

using the external configuration pins or through register

bits.

The MAX96705A is a compact device with features

especially suited for automotive camera applications. The

device operates at a variety of input widths and word

rates up to a total serial-data rate up to 1.74Gbps. High-

bandwidth mode offers a 116MHz parallel clock rate with

12 bits of video data and 2 bits of sync (HS/VS) data. An

embedded 9.6kbps to 1Mbps control channel programs

Video/Conﬁguration Link

2

the serializer, deserializer, and any attached UART or I C

peripherals.

In normal operation, the serializer runs in video link mode

(serializer SEREN = 1) with video data and control data

sent across the serial link. Set SEREN = 0 in the serializer

to turn off serialization. The serializer powers up in video

link mode and requires a valid PCLK for operation.

To promote safety applications, the device features

CRC protection of video and control data. In addition,

control-channel retransmission and high-immunity modes

reduce the effects of bit errors corrupting communication.

Preemphasis and a PRBS tester allow for in-system

evaluation and optimization of the link quality.

A configuration link is available to set up the serializer,

deserializer, and peripherals when PCLK is not available.

Set SEREN = 0 and CLINK = 1 in the serializer to enable

the configuration link (SEREN = 1 forces the serializer into

video link mode). Once PCLK has been established, turn

on the video link (SEREN = 1).

This MAX96705A operates over the -40°C to +115°C

automotive temperature range.

Serial Link Signaling and Data Format

By default, video link mode requires a valid PCLK for

operation. Set AUTO_CLINK bit = 1 and SEREN = 1 in the

serializer to have the device automatically switch between

the video link and configuration link whenever PCLK is

not present.

The serializer scrambles the input parallel data and

combines this with the forward control data. The data

is then encoded for transmission and output as a single

serialized bitstream at several times the input word rate

(depending on bus width). The deserializer receives the

serial data and recovers the clock signal. The data is then

deserialized, decoded, and descrambled into parallel

output data and forward control data.

Maxim Integrated

│ 23

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Single/Double Mode

Bus Widths

Single-/double-mode operation configures the available

1.74Gbps bandwidth into a variety of widths and word

rates. Single-mode operation is compatible with all GMSL

devices and serializers, yielding one parallel word for

each serial word. Double mode serializes two half-width

parallel words for each serial word, resulting in a 2x

increase in the parallel word rate range (compared to

single mode). Set DBL = 0 for single-mode operation and

DBL = 1 for double-mode operation.

The serial link has multiple bus-width settings that

determine the parallel bus width and the resulting parallel

word rate. The serial link operates to a maximum serial

bit rate of 1.74Gbps. The BWS bit determines if each

serial packet is 30 or 40 bits long, which translates to a

maximum serial packet rate (and resulting maximum

parallel word rate) of 58MHz or 43.5MHz when BWS = 0

or 1 respectively. Encoding translates the 24, 27, or 32

parallel bits into 30- or 40-bit serial packets. One bit is

used for parity, while a second is reserved for the control

channel. An additional 6 bits are used during optional

6-bit CRC. In addition, double mode splits the remaining

word size in half, if used. The remaining bits can be used

for video bits (minus any sync bits if H/V encoding is not

used)

HS/VS Encoding

By default, GMSL assigns a video bit slot to HSYNC,

VSYNC, and DE (if used). With HS/VS encoding, the

device instead encodes special packets to sync signals to

free up additional video bit slots. HS/VS encoding is on by

default when the device is in high-bandwidth mode (HIBW

= 1). DE is encoded only when HIBW = 1 and DE_EN =

1. Set HVEN = 1 to turn on HS/VS encoding when HIBW

= 0 (DE, if enabled, uses up a video bit). HS/VS encoding

requires that HSYNC, VSYNC, and DE (if used) remain

high during the active video and low during the blanking

period. Use HS/VS inversion when using reverse-polarity

sync signals.

The following modes list the internal bus widths. The

number of available input and output pins may limit the

actual bus width available.

● 24-Bit Mode (Figure 13)

When BWS = 0 and HIBW = 0, the 30-bit serial packet

corresponds with three 8b/10b symbols representing 24

bits (24-bit mode). After the parity and control channel,

this leaves 16/22 bits of video data if CRC is/or is not used

(single mode), or 8/11 bits of video data if CRC is/or is not

used (double mode).

Error Detection

The serial link's 8b/10b encoding/decoding and 1-bit

parity detect bit errors that occur on the serial link. An

optional 6-bit CRC check is available at the expense of 6

video bits (when HIBW = 0). To activate 6-bit CRC mode,

set PXL_CRC = 1 in the remote-side device first, then in

the local-side device. When using 6-bit CRC mode, the

available internal bus width is reduced by 6 bits in single-

input mode (DBL = 0) and 3 bits in double-input mode

(DBL = 1). Note that the input bus width may already have

been reduced due to pin availability of the serializer or

deserializer; thus, the reduction of bandwidth from CRC

may not be visible (see Table 3).

● 27-Bit High-Bandwidth Mode (Figure 14)

When BWS = 0 and HIBW = 1 (high-bandwidth mode),

the 30-bit serial packet represents three 9b/10b symbols

representing 27 bits. After the parity and control channel,

this leaves 19/25 bits of video data if CRC is/or is not used

(single mode), or 9/12 bits of video data if CRC is/or is not

used (double mode).

● 32-Bit Mode (Figure 15)

When BWS = 1, the 40-bit serial packet corresponds with

four 8b/10b symbols representing 32 bits (32-bit mode).

After parity and control channel, this leaves 24/30 bits of

video data if CRC is/or is not used (single mode), or 12/15

bits of video data if CRC is/or is not used (double mode).

An additional 32-bit video line CRC is available by

setting LINE_CRC_EN = 1. When enabled, the serializer

calculates the 32-bit CRC of the video line and sends this

information during the blanking period. The deserializer

compares the received CRC with the video line data. The

deserializer's LINE_CRC_ERR bit latches when a CRC

error is detected. LINE_CRC_ERR clears when read.

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

24-BIT

MODE

22 BITS

2 BITS

SERIAL

D0

D1

D15

D16

D17

D18

D19

D20

D21

FCC

PCB

DATA

NO PXL_CRC

PXL_CRC ON

PACKET PARITY-

CHECK BIT

6

FORWARD

CONTROL-CHANNEL

BIT

22 VIDEO

BITS

16 VIDEO

BITS

PXL_CRC

BITS

RX/

SDA

TX/

SCL

D0

D1

D21

D0

D1

D15

D16

D17

D18

D19

D20

D21

UART/I²C

DBL = 0

DBL = 1

DBL = 0

11 x 2

VIDEO

BITS*

8 x 2

VIDEO

BITS*

22 VIDEO

BITS*

PXL_CRC

16 VIDEO

BITS*

D11

D0

D12

D21

D10

D0

D1

D21

D8

D0

D9

D15

D1

D0

D1

D15

NO PXL_CRC, DBL = 0

58MHz (max)

D1

D7

NO PXL_CRC, DBL = 1

116MHz (max)

PXL_CRC ON, DBL = 0

58MHz (max)

PXL_CRC ON, DBL = 1

116MHz (max)

*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.

Figure 13. 24-Bit Mode Serial-Data Format

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

27-BIT

MODE

25 BITS

D17

2 BITS

SERIAL

D0

D1

D15

D16

D18

D19

D20

D21

D22

D23

D24

FCC

PCB

DATA

NO PXL_CRC

PXL_CRC ON

PACKET PARITY-

CHECK BIT

6

FORWARD

CONTROL-CHANNEL

BIT

25 VIDEO

BITS

19 VIDEO

BITS

PXL_CRC

BITS

RX/

SDA

TX/

SCL

D0

D1

D24

D0

D1

D15

D16

D17

D18

D22

D23

D24

UART/I²C

DBL = 0

DBL = 1

DBL = 0

12 x 2

VIDEO

BITS*

9 x 2

VIDEO

BITS*

25 VIDEO

BITS*

PXL_CRC

19 VIDEO

BITS*

D12

D0

D13

D23

D11

D24

D0

D1

D24

D9

D0

D10

D17

D18

D1

D0

D1

D18

NO PXL_CRC, DBL = 0

58MHz (max)

D1

D8

NO PXL_CRC, DBL = 1

116MHz (max)

PXL_CRC ON, DBL = 0

58MHz (max)

PXL_CRC ON, DBL = 1

116MHz (max)

*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.

Figure 14. 27-Bit High-Bandwidth Mode Serial-Data Format

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

32-BIT

MODE

30 BITS

2 BITS

SERIAL

D0

D1

D23

D24

D25

D26

D27

D28

D29

FCC

PCB

DATA

NO PXL_CRC

PXL_CRC ON

PACKET

PARITY-

CHECK BIT

6

FORWARD

CONTROL-CHANNEL

BIT

30 VIDEO

BITS

24 VIDEO

BITS

PXL_CRC

BITS

RX/

SDA

TX/

SCL

D0

D2

D29

D0

D2

D23

D24

D25

D26

D27

D28

D29

UART/I²C

DBL = 0

DBL = 1

DBL = 0

15 x 2

VIDEO

BITS*

12 x 2

VIDEO

BITS*

30 VIDEO

BITS*

PXL_CRC

24 VIDEO

BITS*

D15

D0

D16

D29

D14

D0

D1

D29

D12

D0

D13

D23

D1

D0

D1

D23

NO PXL_CRC, DBL = 0

43.5MHz (max)

D1

D11

NO PXL_CRC, DBL = 1

87MHz (max)

PXL_CRC ON, DBL = 0

43.5MHz (max)

PXL_CRC ON, DBL = 1

87MHz (max)

*INTERNAL BITS. INPUT/OUTPUT PIN AVAILABILITY MAY LIMIT THE EXTERNAL BUS WIDTH.

Figure 15. 32-Bit Mode Serial-Data Format

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

2

I C Interface

Control Channel and Register Programming

2

The serial link connects the serializer and deserializer I C

interfaces together through the control channel. When

The control channel sends information across the serial

link for control of the serializer, deserializer, and any

attached peripherals. The control channel is multiplexed

onto the serial link and is available with or without the

video channel.

2

an I C master sends a command to one side of the link

(local side) the control channel forwards this information

to and from the other side of the link (remote side),

allowing a single microcontroller to configure the serializer,

deserializer, and peripherals. The microcontroller can

be located on the serializer side (display applications)

and the deserializer side (camera applications). Dual

microcontroller operations are supported as long as

a software-arbitration method is used. The serial link

assumes that only one microcontroller is talking at any

given time.

Forward Control Channel

Control data sent from the serializer to the deserializer is

sent on the forward control channel. The data is encoded

as one of the serial bits in the forward high-speed link.

After deserialization, the forward control-channel data is

extracted from the serial link. The forward control-channel

bandwidth exceeds the maximum external control data

rate, and all data sent on the forward control channel

appears on the remote side after transmission delay of a

few bit times.

Remote-End Operation

2

When an I C master initiates communication on the local

slave device (the serializer/deserializer directly connected

to the master), the remote-side device acts as a master

device that sends data forwarded from the local-side

device, and forwards any data received from peripherals

attached to the remote-side device. This remote-

side master device operates according to the timing

settings in the I C master setting register. Set the master

settings to match the timing settings used by the

external microcontroller.

Reverse Control Channel

Control data sent from the deserializer to the serializer

is sent on the reverse control channel. The data is

encoded as a series of 1μs pulses, with a maximum raw

data rate of 1Mbps. High-immunity mode is available to

increase the robustness of the reverse control channel

at a reduced raw bit rate of 500kbps. In Table 1, setting

the REV_FAST bit = 1 increases this rate back to 1Mbps.

2

In I C mode, when the input data rate (after encoding)

Clock-Stretch Timing

exceeds the reverse data rate, the input clock is held

through clock stretching to slow the external clock to

match the internal bit rate.

2

The I C interface uses clock stretching to allow time for

data to be forwarded across the serial link. The master

microcontroller, along with any attached peripherals, must

accept clock stretching of the GMSL devices.

UART Interface

The UART interface, compatible with all GMSL devices,

sends commands from device to device through several

UART packets. Two modes are available: base mode

and bypass mode. Base mode is used to communicate

2

Packet-Based I C

A packet-based control channel is available for enhanced

error handling of the control channel. This control-

channel method handles simultaneous GPI/GPO and

2

with the serializer, deserializer, and to I C peripherals

2

using UART-to-I C translation. Bypass mode allows for

I C transmission, along with error detection and

full-duplex UART communication to peripherals using any

UART protocol.

retransmission.

Table 1. Reverse Control-Channel Modes

2

REVERSE CONTROL-

CHANNEL MODE

MAXIMUM UART/I C BIT

RATE (kBPS)

HIM PIN SETTING

REVFAST BIT

Legacy reverse control-channel

mode (compatible with all GMSL

devices)

Low

X

0

1

1000

500

High-immunity mode

Fast high-immunity mode

(requires HIBW = 0, serial-data

rate > 1.25Gbps)

High

1000

X = Don’t care.

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Packet Protocol Summary

Crossbar Switch

The packet-based control channel uses a synchronous,

symbol-based system to send data across the control

channel. Data to be sent across the control channel

is split into symbols and stored in a transmit queue

The crossbar switch routes data between the parallel

input/output and the SerDes. The anything-to-anything

routing assures the mapping between the video source

and destination. For each crossbar output (XBO_) an

input multiplexer selects from the available crossbar

inputs (XBI_) using the CROSSBAR_ register bits (Figure

17). Multiple crossbar outputs can use the same crossbar

input. By default, the sync signals share the same inputs

as the MSBs of the video data.

2

and then sent across the link. If both GPI and I C data

needs to be sent (e.g., when GPI transitions during an

2

I C transmission), the symbols from both commands

are combined in the queue. If the transmit queue is

empty, idle packets are sent across the link to maintain

2

control-channel lock. Received I C packets are output as

Video Timing Generator

determined by the microcontroller SCL rate (local device)

or the programmed master bit rate (remote device). The

device holds SCL low (clock stretch) until data has been

received from the remote-side device.

The serializer includes a programmable video timing

generator to generate/retime the input sync signals. The

timing generator can be used to modify a camera's input

timing, filter out glitches in the sync signals, or to reduce

the number of required input sync signals. Each sync

signal can be individually retimed or left unmodified.

Several registers determine the length of the timing

parameters (in PCLK cycles) shown in Figure 18. Timing

parameters include high/low period length, line count, and

delay from the input VS signal.

Control-Channel Error Detection and Packet

Retransmission

When the packet-based control channel is used, all

packets are checked for errors through CRC. Using 1, 5,

or 8 bits, CRC detects 1, 3, or 4 random bit errors in a

packet. The transmitter retransmits packets whenever an

error is detected. The transmitter sets a flag if a number

of retries exceed 8. The receiver filters out packets with

errors.

The timing generator uses three different trigger modes,

tracking, single trigger, and autorun. Tracking mode looks

at the input VSYNC and locks once it receives three

consecutive identical VSYNC signals. The tracker then

continues to output the same identical signal, erasing

any glitches that may appear on VSYNC. The tracker

attempts to relock to a new signal if three consecutive

input waveforms do not match the locked signal. Single

trigger generates one generated frame for each input

VSYNC edge. Autorun generates a new frame at the rate

determinedbytheVSYNChigh/lowperiod. IfanewVSYNC

signal appears before a frame is complete in either single

trigger or autorun modes, a new frame immediately starts,

cutting the previous frame short.

GPO/GPI Control

GPO on the serializer follows GPI transitions on the

deserializer. This GPO/GPI function can be used to

transmit signals such as a frame sync in a surround-

view camera system (see the Providing a Frame Sync

(Camera Applications) section). Optionally, GPO can be

set directly by register bits.

Spread Spectrum

The serializer contains a programmable spread-spectrum

output to lower emission levels by spreading the clock-

frequency peaks across a frequency spectrum. In addition,

the serializer and deserializer can track a spread input

clock, eliminating the need for multiple spread clocks.

GMSL

SERIALIZER

DESERIALIZER

Cable Type Conﬁguration

The driver output is programmable for two kinds of

cable,100Ω twisted pair and 50Ω coax (contact the

factory for devices compatible with 75Ω cables). In coax

mode, connect OUT+ to IN+ of the deserializer. Leave

the unused IN_ pin unconnected, or connect it to ground

through 50Ω, and a capacitor for increased power-supply

OUT+

IN+

OUT-

IN-

AVDD

OPTIONAL COMPONENTS

FOR INCREASED

POWER-SUPPLY REJECTION

50Ω

rejection. Connect OUT- to V

(Figure 16).

through a 50Ω resistor

DD

Figure 16. Coax Connection

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

DATA

LOW INPUT

DIN0

XBI0

XBI1

:

XBI9

XBI10

XBI11

XBI12

XBI13

XBI14

XBI15

XBO0

XBO1

:

XBO29

XBO30

D0

D1

:

D29

D30

DIN1

:

CROSSBAR_

5

DIN9

DIN10

DIN11

DIN12

DIN13

0

1

XBOHS

XBOVS

XBODE

HS

VS

DE

DIN14/HS

DIN15/VS

FORCE_MUX_

0

SYNC

PCLK

HIGH INPUT

(DBL = 1 only)

DIN0

XBI16

XBI17

:

XBI25

XBI26

XBI27

XBI28

XBI29

XBI30

XBI31

DIN1

:

DIN9

DIN10

DIN11

DIN12

DIN13

DIN14/HS

DIN15/VS

:

INVERT_MUX_

HS/DE*

HI_LO*

HS/DE

1

0

DIN15/VS

DIN14/HS

DIN13

...

XBI31

XBI30

XBI29

XBI15

XBI14

XBI13

XBI31

XBI30

XBI29

XBI15

XBI14

XBI13

...

DIN1

DIN0

XBI17

XBI16

XBI1

XBI0

XBI17

XBI16

XBI1

XBI0

XBO_

34 SWITCHES

*REGISTER SETTINGS DECIDE IF HS, DE, OR HI_LO DETERMINES THE HIGH/LOW INPUT TIMING.

Figure 17. Crossbar Switch Dataflow

VS_IN

VS_DLY

VS_OUT

VS_L

VS_H

HS_DLY

HS OUT

HS_L

HS_H

HS_CNT (PULSE COUNT)

DE_CNT (PULSE COUNT)

DE_DLY

DE_L

DE OUT

DE_H

Figure 18. Sync-Signal Format For Video-Timing Generation

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

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CLINKEN = 0

OR SEREN = 1

CLINKEN = 0

CONFIG LINK

SLEEP = 1

FOR > 8ms

CONFIG LINK

UNLOCKED

OR SEREN = 1

POWER ON

IDLE

CONFIG

LINK

OPERATING

SLEEP = 0,

SEREN = 0

SLEEP

WAKEUP

CLINKEN = 1

CONFIG LINK

LOCKED

STARTED

PROGRAM

LINK WAKEUP SIGNAL

REGISTERS

SEREN = 1,

PCLKIN RUNNING

SEREN = 0 OR

NO PCLKIN

PWDNB = HIGH,

POWER ON

SLEEP = 1

SLEEP = 0,

SEREN = 1

SEREN = 0 OR

NO PCLKIN

PRBSEN = 0

PRBSEN = 1

POWER

DOWN

OR

VIDEO

LINK

LOCKING

PWDNB = LOW OR

POWER OFF

VIDEO LINK

LOCKED

VIDEO LINK

OPERATING

VIDEO LINK

PRBS TEST

ALL STATES

POWER OFF

VIDEO LINK

UNLOCKED

Figure 19. State Diagram

Sleep Mode

Shutdown/Sleep Modes

To reduce power consumption further, the devices can

be put into sleep mode. In this mode, all registers keep

their programmed values, and all functions in the device

are powered down except for the wake-up detectors

on the local control interface, and the serial link. Any

activity seen by the wake-up detectors temporarily turns

on the control-channel interface. During this time, a

microcontroller can command the device to exit sleep

mode. See the Shutdown/Sleep Modes section.

Several sleep and shutdown modes are available when

full operation is not needed.

Conﬁguration Link

When the high-speed video link is not needed, or

unavailable, a configuration link can be used in its place.

In configuration link mode, the parallel digital input/output

is disabled, the LOCK pin remains low, and the serial link

internally generates its own clock to allow full operation of

2

the control channel (UART/I C and GPIO).

Serialization Disable

When the serial link is not needed, such as when

downstream devices are powered off, the user can disable

serialization. In this mode, all forward communication is

shut down. The user can reenable serialization either

locally, or through the reverse channel.

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

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Power-Down Mode

Link Startup Procedure

The lowest power consumption mode is power-down

mode. In this mode, all functions are powered down, and

all register values are lost.

Table 2 lists the startup procedure for image-sensing

applications. The control channel is available after the

video link or the configuration link is established. If the

deserializer powers up after the serializer, the control

channel becomes unavailable until 2ms after power-up.

Table 2. Link-Startup Procedure

NO.

μC

SERIALIZER

DESERIALIZER

—

μC Connected to Deserializer

Set Conﬁguration Inputs

Powers up and loads default

settings. Establishes video link

when valid PCLK is available.

Powers up and loads default

settings. Locks to video link

signal if available.

1

Powers up (wait t ).

PU

If no PCLK, programs CLINKEN, SEREN, and/or

AUTOCLINK bits. Wait 5ms after each command.

Locks to conﬁguration link if

available.

1a

Establishes conﬁguration link.

If not locked, sets any additional conﬁguration bits

that are mismatched between the serializer and

deserializer (e.g., BWS, CX/TP). Wait 5ms for lock

after each command.

Conﬁguration changed.

Reestablishes conﬁguration/video

link if needed.

Conﬁguration changed. Locks

to conﬁguration/video link.

1b

Conﬁguration changed.

Reestablishes conﬁguration/video Loss-of-lock may occur.

link if needed.

Sets register 0x07 conﬁguration bits in the serializer

(DBL, BWS, HIBW, PXL_CRC, etc.). Wait 2ms.

2

3

Sets register 0x07 conﬁguration bits in the deserializer

(DBL, BWS, HIBW, PXL_CRC, etc.). Wait 5ms for

lock to reestablish.

Conﬁguration changed. Locks

to conﬁguration/video link.

—

4

5

Writes rest of serializer/deserializer conﬁguration bits. Conﬁguration changed.

Conﬁguration changed.

Forwards commands from μC to

Forwards commands to

camera/peripherals.

Writes camera/peripheral conﬁguration bits.

serializer.

If in conﬁguration link, when PCLK is available, set

SEREN = 1. Wait 5ms for lock.

5a

Enables video link.

Locks to video link.

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Register Map

GMSL Register Map

OFFSET

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

NAME

seraddr

MSB

LSB

SERADDR[6:0]

DESADDR[6:0]

RSVD

CFGBLOCK

RSVD

desaddr

ss

SS[2:0]

AUTOFM[1:0]

SEREN CLINKEN PRBSEN SLEEP

I2CMETHOD RSVD PRBS_LEN[1:0]

CMLLVL[3:0]

HIBW BWS

RSVD

PRNG[1:0]

SDIV[5:0]

SRNG[1:0]

sdiv

main_control

prbs_len

cmllvl_preemp

conﬁg

INTTYPE[1:0]

REVCCEN FWDCCEN

RSVD

PREEMP[3:0]

DBL

ES

RSVD

HVEN

RSVD

PXL_CRC

RSVD

rsvd_8

RSVD

i2c_source A

i2c_dest A

i2c_source B

i2c_dest B

I2C_SRC_A[6:0]

I2C_DST_A[6:0]

I2C_SRC_B[6:0]

I2C_DST_B[6:0]

RSVD

I2C_LOC_

ACK

0x0D

0x0E

0x0F

0x10

i2c_conﬁg

gpio_en

gpio_out

gpio_in

I2C_SLV_SH[1:0]

I2C_MST_BT[2:0]

I2C_SLV_TO[1:0]

GPIO_

RSVD

GPIO_

EN_4

GPIO_

EN_3

GPIO_

EN_2

RSVD

GPIO_EN_1

RSVD

EN_5

EN_SET_

GPO

GPIO_

RSVD

GPIO_

OUT_4

GPIO_

OUT_3

GPIO_

OUT_2

GPIO_

OUT_1

SET_GPO

OUT_5

GPIO_

RSVD

GPIO_

IN_4

GPIO_

IN_3

GPIO_

IN_2

RSVD

GPIO_IN_1 GPO_L

ERRG_PER ERRG_EN

IN_5

0x11

0x12

errg

ERRG_RATE[1:0]

ERRG_TYPE[1:0]

RSVD

ERRG_CNT[1:0]

RSVD[4:0]

rsvd_12

RSVD

ALLOW_

PKTCC

0x13

pd

SOFT_PD

RSVD

RSVD[1:0]

CC_

WBLOCK CCLOCK

RSVD OUTPUTEN PCLKDET

REM_

0x14

0x15

0x16

pktcc_lock

input_status

max_rt_err

RSVD[1:0]

RSVD

CX_TP

RSVD

LCCEN

MAX_RT_

ERR

RSVD[5:0]

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

rsvd_17

crc 0

RSVD[7:0]

CRC_VALUE_0[7:0]

CRC_VALUE_1[7:0]

CRC_VALUE_2[7:0]

CRC_VALUE_3[7:0]

CC_CRC_ERRCNT[7:0]

RSVD[7:0]

crc 1

crc 2

crc 3

cc_crc_errcnt

rsvd_1d

id[7:0]

ID[7:0]

revision

RSVD

RSVD HDCPCAP

REVISION[3:0]

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

GMSL Register Map (continued)

OFFSET

NAME

crossbar 0

MSB

LSB

FORCE_ INVERT_

MUX_0 MUX_0

FORCE_ INVERT_

MUX_1 MUX_1

FORCE_ INVERT_

MUX_2 MUX_2

FORCE_ INVERT_

MUX_3 MUX_3

FORCE_ INVERT_

MUX_4 MUX_4

FORCE_ INVERT_

MUX_5 MUX_5

FORCE_ INVERT_

MUX_6 MUX_6

FORCE_ INVERT_

MUX_7 MUX_7

FORCE_ INVERT_

MUX_8 MUX_8

FORCE_ INVERT_

MUX_9 MUX_9

0x20

RSVD

CROSSBAR_0[4:0]

CROSSBAR_1[4:0]

CROSSBAR_2[4:0]

CROSSBAR_3[4:0]

CROSSBAR_4[4:0]

CROSSBAR_5[4:0]

CROSSBAR_6[4:0]

CROSSBAR_7[4:0]

CROSSBAR_8[4:0]

CROSSBAR_9[4:0]

CROSSBAR_10[4:0]

CROSSBAR_11[4:0]

CROSSBAR_12[4:0]

CROSSBAR_13[4:0]

CROSSBAR_14[4:0]

CROSSBAR_15[4:0]

CROSSBAR_16[4:0]

CROSSBAR_17[4:0]

CROSSBAR_18[4:0]

CROSSBAR_19[4:0]

CROSSBAR_20[4:0]

CROSSBAR_21[4:0]

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

crossbar 1

crossbar 2

crossbar 3

crossbar 4

crossbar 5

crossbar 6

crossbar 7

crossbar 8

crossbar 9

crossbar 10

crossbar 11

crossbar 12

crossbar 13

crossbar 14

crossbar 15

crossbar 16

crossbar 17

crossbar 18

crossbar 19

crossbar 20

crossbar 21

RSVD

FORCE_ INVERT_

MUX_10 MUX_10

FORCE_ INVERT_

MUX_11 MUX_11

FORCE_ INVERT_

MUX_12 MUX_12

FORCE_ INVERT_

MUX_13 MUX_13

FORCE_ INVERT_

MUX_14 MUX_14

FORCE_ INVERT_

MUX_15 MUX_15

FORCE_ INVERT_

MUX_16 MUX_16

FORCE_ INVERT_

MUX_17 MUX_17

FORCE_ INVERT_

MUX_18 MUX_18

FORCE_ INVERT_

MUX_19 MUX_19

FORCE_ INVERT_

MUX_20 MUX_20

FORCE_ INVERT_

MUX_21 MUX_21

Maxim Integrated

│ 34

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

GMSL Register Map (continued)

OFFSET

NAME

MSB

LSB

FORCE_ INVERT_

MUX_22 MUX_22

0x36

crossbar 22

RSVD

CROSSBAR_22[4:0]

CROSSBAR_23[4:0]

CROSSBAR_24[4:0]

CROSSBAR_25[4:0]

CROSSBAR_26[4:0]

CROSSBAR_27[4:0]

CROSSBAR_28[4:0]

CROSSBAR_29[4:0]

CROSSBAR_30[4:0]

CROSSBARHS[4:0]

CROSSBARVS[4:0]

FORCE_ INVERT_

MUX_23 MUX_23

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

crossbar 23

crossbar 24

crossbar 25

crossbar 26

crossbar 27

crossbar 28

crossbar 29

crossbar 30

crossbar_hs

crossbar_vs

crossbar_de

RSVD

FORCE_ INVERT_

MUX_24 MUX_24

FORCE_ INVERT_

MUX_25 MUX_25

FORCE_ INVERT_

MUX_26 MUX_26

FORCE_ INVERT_

MUX_27 MUX_27

FORCE_ INVERT_

MUX_28 MUX_28

FORCE_ INVERT_

MUX_29 MUX_29

FORCE_ INVERT_

MUX_30 MUX_30

FORCE_ INVERT_

MUX_HS MUX_HS

FORCE_ INVERT_

MUX_VS MUX_VS

FORCE_ INVERT_

MUX_DE MUX_DE

CROSSBARDE[4:0]

GPI_

LINE_

CRC_EN RT_EN

MAX_

GPI_RT_

EN

0x42

link_conﬁg

LINE_CRC_LOC[1:0]

RSVD

COMP_

EN

GPO_EN

VS_

TRIG

0x43

sync_gen_conﬁg

RSVD

GEN_VS GEN_HS GEN_DE

VTG_MODE[1:0]

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

vs_dly 2

vs_dly 1

vs_dly 0

vs_h 2

vs_h 1

vs_h 0

vs_l 2

VS_DLY[7:0]

VS_H[7:0]

VS_L[7:0]

vs_l 1

VS_L[7:0]

vs_l 0

VS_L[7:0]

VSYNC_ HSYNC_

INV INV

HS_DLY[7:0]

0x4D

cxtp

HIGHIMM

CXTP

RSVD

DE_INV

RSVD

0x4E

0x4F

0x50

hs_dly 2

hs_dly 1

hs_dly 0

HS_DLY[7:0]

Maxim Integrated

│ 35

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

GMSL Register Map (continued)

OFFSET

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

NAME

MSB

LSB

rsvd51

rsvd52

rsvd53

hs_h 1

hs_h 0

hs_l 1

hs_l 0

RSVD[7:0]

HS_H[7:0]

HS_L[7:0]

hs_cnt 1

hs_cnt 0

de_dly 2

de_dly 1

de_dly 0

rsvd5D

rsvd5E

rsvd5F

de_h 1

HS_CNT[7:0]

DE_DLY[7:0]

RSVD[7:0]

DE_H[7:0]

de_h 0

DE_H[7:0]

de_l 1

DE_L[7:0]

de_l 0

DE_L[7:0]

de_cnt 1

de_cnt 0

DE_CNT_1[7:0]

DE_CNT_0[7:0]

PRBS_

TYPE

REV_

FAST

DIS_

RWAKE

0x66

0x67

0x68

0x69

prbs_type

dbl_align_to

cc_crc_length

hi_lo

RSVD[1:0]

DE_EN

RSVD

CXSEL

AUTO_

CLINK

RSVD

DBL_ALIGN_TO[2:0]

CC_CRC_

LENGTH[1:0]

RSVD

RSVD[2:0]

RSVD[1:0]

EN_HI_ INVERT_

CROSSBAR_HI_LO[4:0]

LO

HI_LO

0x96

0x97

0x98

0x99

rsvd_96

rsvd_97

rsvd_98

rsvd_99

RSVD

RSVD[1:0]

RSVD[2:0]

RSVD[1:0]

RSVD

RSVD[1:0]

RSVD[2:0]

RSVD

PKTCC_

EN

0x9A

pktcc_en

RSVD[1:0]

RSVD RSVD

RSVD

0xC8

0xC9

rsvd_c8

rsvd_c9

RSVD

RSVD[7:0]

Maxim Integrated

│ 36

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

GMSL Register Map (continued)

OFFSET

0xFC

NAME

rsvd_fc

MSB

LSB

RSVD

0xFD

rsvd_fd

rsvd_fe

rsvd_ﬀ

RSVD[7:0]

0xFE

RSVD[3:0]

0xFF

RSVD

RSVD[3:0]

seraddr (0x00)

BIT

7

6

5

4

3

2

1

0

Field

SERADDR[6:0]

1000000

CFGBLOCK

0b

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

0000000: Write/read device address is 0x00/0x01

0000001: Write/read device address is 0x02/0x03

1111111: Write/read device address is 0xFE/0xFF

SERADDR

7:1

Serializer Address: Serializer device address

Conﬁguration Block: Set to 1 to make all

registers read-only. Set PWDNB low, or a power-on

reset to clear this bit.

0: Make all registers read/write

1: Make all registers read-only

CFGBLOCK

0

desaddr (0x01)

BIT

7

6

5

4

3

2

1

0

RSVD

0b

Field

DESADDR[6:0]

1001000b

Reset

Access Type

Write, Read

BITFIELD

DESADDR

RSVD

BITS

7:1

0

DESCRIPTION

DECODE

0000000: Write/read device address is 0x00/0x01

Deserializer Address: Deserializer device address 0000001: Write/read device address is 0x02/0x03

1111111: Write/read device address is 0xFE/0xFF

Reserved: Do not change from default value

0: Reserved

Maxim Integrated

│ 37

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

ss (0x02)

BIT

7

6

5

4

RSVD

1b

3

2

1

0

Field

SS[2:0]

010

PRNG[1:0]

11b

SRNG[1:0]

11b

Reset

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

000: Spread is oﬀ

001: 0.5% Spread setting

010: 1.5% Spread setting

011: 2% Spread setting

100: Spread is oﬀ

101: 1% Spread setting

110: 3% Spread setting

111: 4% Spread setting

SS

7:5

Spread Spectrum: Spread-spectrum setting

Reserved: Do not change from default value

RSVD

PRNG

4

1: Reserved

00: Select 12.5MHz to 25MHz (DBL = 0) or 25MHz

to 50MHz (DBL = 1) pixel clock range

01: Select 25MHz to 58MHz (DBL = 0) or 50MHz to

116MHz (DBL = 1) pixel clock range

Pixel Clock Range: Pixel clock-range selection

Stated ranges depend on DBL = setting

3:2

10: Automatically detect pixel clock range

11: Automatically detect pixel clock range.

00: 0.5Gbps to 1Gbps serial-data range

01: 1Gbps to 1.74Gbps serial-data range

10: Automatically detect serial-data range

11: Automatically detect serial-data range

SRNG

1:0

Serial-Data Rate Range

sdiv (0x03)

BIT

7

6

5

4

3

2

1

0

Field

AUTOFM[1:0]

SDIV[5:0]

000000b

Reset

00b

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

00: Calibration occurs once

Automatic Frequency Modulation: Modulation-

rate calibration interval

01: Calibration occurs every 2ms

10: Calibration occurs every 16ms

11: Calibration occurs every 256ms

AUTOFM

7:6

000000: Sawtooth divider automatically calibrates

the divider value

000001: Sawtooth divider set to 1

111111: Sawtooth divider set to 63

Sawtooth Divider: Sawtooth divider value

0x00 sets the sawtooth divider to autocalibrate

mode

SDIV

5:0

Maxim Integrated

│ 38

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

main_control (0x04)

BIT

Field

Reset

7

SEREN

1b

6

CLINKEN

0b

5

PRBSEN

0b

4

3

2

1

REVCCEN

1b

0

FWDCCEN

1b

SLEEP

0b

INTTYPE[1:0]

01b

Access Type Write, Read Write, Read Write, Read Write, Read

Write, Read

Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

Serialization Enable: Requires a valid PCLK for

serialization

0: Disable serialization

1: Enable serialization

SEREN

7

Conﬁguration Link Enable: Conﬁguration link

enabled only when the video link is not enabled

(SEREN = 1)

0: Disable conﬁguration link

1: Enable conﬁguration link

CLINKEN

PRBSEN

SLEEP

6

5

4

PRBS Test Enable: See the PRBS test section for 0: Disable PRBS test

more details

1: Enable PRBS test

Sleep Mode Enable: Activates sleep mode

(see the Shutdown/Sleep Modes section for more

information)

0: Disable sleep mode

1: Enable sleep mode

2

00: Device performs UART-to-I C conversion when

functioning as the remote device

01: Device outputs UART packets when functioning

as the remote device

10: Tx/Rx input/outputs disabled when functioning

as the remote device

2

UART/I C Interface Type: Local control-channel

2

INTTYPE

3:2

interface when in UART/UART or UART/I C mode

(I2CSEL = 0)

11: Tx/Rx input/outputs disabled when functioning

as the remote device

Reverse Control-Channel Enable: Enable

reverse control-channel receiver (data from

deserializer)

0: Disable reverse control-channel receiver

1: Enable reverse control-channel receiver

REVCCEN

FWDCCEN

1

0

Forward Control-Channel Enable: Enable

forward control channel receiver

(data to deserializer)

0: Disable forward control channel transmitter

1: Enable forward control channel transmitter

Maxim Integrated

│ 39

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

prbs_len (0x05)

BIT

7

6

5

4

3

2

1

0

Field

I2CMETHOD

0b

RSVD

0b

PRBS_LEN[1:0]

00b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

Reset

Access Type Write, Read Write, Read

Write, Read

Write, Read Write, Read Write, Read Write, Read

BITFIELD

I2CMETHOD

RSVD

BITS

DESCRIPTION

DECODE

2

UART-to-I C Method: When set, skip the sending

of the register address when converting UART to

0: Do not skip the sending of the register address

1: Skip the sending of the register address

7

6

2

I C (I2CSEL = 0).

Reserved: Do not change from default value.

0: Reserved

00: Continuous bit pattern (inﬁnite length)

01: 9.8Mbit length

10: 167.1Mbit length

PRBS_LEN

5:4

PRBS Length: PRBS test pattern length

11: 1341.5Mbit length

RSVD

3

2

1

0

Reserved: Do not change from default value

Reserved: Do not change from default value.

0: Reserved

Maxim Integrated

│ 40

www.maximintegrated.com

MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

cmllvl_preemp (0x06)

BIT

Field

7

6

5

4

3

2

1

0

CMLLVL[3:0]

10X0b

PREEMP[3:0]

Reset

0000b

Access Type

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

0000: Do not use

0001: Do not use

0010: 100mV output

0011: 150mV output

0100: 200mV output

0101: 250mV output

0110: 300mV output

0111: 350mV output

1000: 400mV output (STP default)

1001: 450mV output

1010: 500mV output (coax default)

1011: Do not use

CML Level: Output CML signal level = (register

value) x 50mV

Default level depends on cable type (CXTP)

CMLLVL

7:4

1100: Do not use

1101: Do not use

111X: Do not use

0000: Preemphasis oﬀ

0001: 1.2dB deemphasis

0010: 2.5dB deemphasis

0011: 4.1dB deemphasis

0100: 6.0dB deemphasis

0101: Do not use

011X: Do not use

Preemphasis Level: Preemphasis setting

PREEMP

3:0

1000: 1.1dB preemphasis

1001: 2.2dB preemphasis

1010: 3.3dB preemphasis

1011: 4.4dB preemphasis

1100: 6.0dB preemphasis

1101: 8.0dB preemphasis

1110: 10.5dB preemphasis

1111: 14.0dB preemphasis

Negative preemphasis levels denote deemphasis

Maxim Integrated

│ 41

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

conﬁg (0x07)

BIT

7

6

5

4

3

2

1

0

PXL_CRC

0b

Field

DBL

1b

HIBW

0b

BWS

Xb

ES

Xb

RSVD

0b

HVEN

1b

RSVD

0b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

0: Single-input mode

Double-Input Mode Enable: Set high to enable

double-input mode. Default setting is determined

by LCCEN and TX/SCL/DBL pin setting at

power-up.

DBL

7

1: Double-input mode

High-Bandwidth Mode Enable: High-bandwidth

mode select (eﬀective only when BWS = 0)

0: Use 24-bit mode when BWS = 0

1: Use high-bandwidth mode when BWS = 0

HIBW

BWS

6

5

Bus-Width Select: Default value is determined by 0: 24-bit and high-bandwidth mode

LCCEN and GPIO1/BWS pin setting at power-up.

1: 32-bit mode

Edge Select: Default value is determined by

CONF[1:0] pins at power-up

0: Parallel data clocked in on rising edge

1: Parallel data clocked in on falling edge

ES

4

3

RSVD

Reserved: Do not change from default value.

0: Reserved

HSYNC/VSYNC Encoding Enable: Default value

is determined by LCCEN and MS/HVEN pin setting

at powerup

0: Disable HS/VS encoding

1: Enable HS/VS encoding

HVEN

2

RSVD

1

0

Reserved: Do not change from default value.

0: Reserved

Pixel CRC Type: pixel error-detection type

Eﬀective only when HIBW = 0

0: Serial data uses 1-bit parity

1: Serial data uses 6-bit CRC

PXL_CRC

rsvd_8 (0x08)

BIT

7

6

5

4

3

2

1

0

Field

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

5

4

3

2

1

0

Reserved: Do not change from default value.

0: Reserved

Maxim Integrated

│ 42

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

i2c_source (0x09, 0x0B)

BIT

Field

7

6

5

4

3

2

1

0

RSVD

0b

I2C_SRC[6:0]

0000000b

Write, Read

Reset

Access Type

Write, Read

BITFIELD

I2C_SRC

RSVD

BITS

7:1

0

DESCRIPTION

DECODE

0000000: Write/read device address is 0x00/0x01

0000001: Write/read device address is 0x02/0x03

1111111: Write/read device address is 0xFE/0xFF

2

I C Source: I C address translator source

Reserved: Do not change from default value.

0: Reserved

i2c_dest (0x0A, 0x0C)

BIT

Field

7

6

5

4

3

2

1

0

RSVD

0b

I2C_DST[6:0]

0000000b

Write, Read

Reset

Access Type

Write, Read

BITFIELD

BITS

7:1

DESCRIPTION

DECODE

0000000: Write/read device address is 0x00/0x01

2

I2C_DST

RSVD

I C Destination: I C address translator destination 0000001: Write/read device address is 0x02/0x03

1111111: Write/read device address is 0xFE/0xFF

0

Reserved: Do not change from default value.

0: Reserved

Maxim Integrated

│ 43

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

i2c_conﬁg (0x0D)

BIT

7

6

5

4

3

2

1

0

I2C_LOC_

ACK

Field

I2C_SLV_SH[1:0]

I2C_MST_BT[2:0]

I2C_SLV_TO[1:0]

Reset

1b

01b

101b

10b

Access Type Write, Read

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

0: Do not send local autoacknowledge when

control channel is absent

1: Send local autoacknowledge when control

channel is absent

2

I C Local Acknowledge: I C-to-I C slave

generates local acknowledge when forward

channel is not available

I2C_LOC_

ACK

7

00: (352ns, 117ns) setup/hold time

01: (469ns, 234ns) setup/hold time

10: (938ns, 352ns) setup/hold time

11: (1406ns, 469ns) setup/hold time

2

I2C_SLV_

SH

I C Slave Setup/Hold Time: I C-to-I C slave

6:5

4:2

1:0

setup and hold-time setting (setup, hold) (typ)

000: (6.61, 8.47, 9.92) kbps

001: (22.1, 28.3, 33.2) kbps

010: (66.1, 84.7, 99.2) kbps

011: (82, 105, 123) kbps

100: (136, 173, 203) kbps

101: (265, 339, 397) kbps

110: (417, 533, 625) kbps

111: (654, 837, 980) kbps

2

I2C_MST_

BT

I C Master Bit Rate: I C-to-I C master bit-rate

setting (min, typ, max)

00: 64μs slave timeout

01: 256μs slave timeout

10: 1024μs slave timeout

11: Slave timeout disabled

2

I2C_SLV_

TO

I C Slave Timeout: I C-to-I C slave remote-side

timeout setting (typ).

Maxim Integrated

│ 44

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

gpio_en (0x0E)

BIT

7

6

5

4

3

2

1

0

Field

RSVD

0b

RSVD

0b

GPIO_EN_5 GPIO_EN_4 GPIO_EN_3 GPIO_EN_2 GPIO_EN_1

0b 0b 0b 0b 1b

RSVD

0b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

Reserved: Do not change from default value.

0: Reserved

RSVD

0: Pin functions as a parallel input

1: Pin functions as a GPIO

GPIO_EN_5

GPIO_EN_4

GPIO_EN_3

GPIO_EN_2

5

4

3

2

GPIO Enable: Disabled by default

GPIO Enable: Disabled by default.

GPIO Enable: Disabled by default

0: Pin functions as a parallel input

1: Pin functions as a GPIO

0: Pin functions as a parallel input

1: Pin functions as a GPIO

0: Pin functions as a parallel input

1: Pin functions as a GPIO

0: Pin functions as parallel input

1: Pin functions as GPIO

GPIO_EN_1

RSVD

1

0

GPIO Enable: Disabled by default

Reserved: Do not change from default value

0: Reserved

gpio_out (0x0F)

BIT

7

6

5

4

3

2

1

0

SET_GPO

0b

EN_SET_

GPO

GPIO_

OUT_5

GPIO_

OUT_4

GPIO_

OUT_3

GPIO_

OUT_2

GPIO_

OUT_1

Field

RSVD

Reset

0b

1b

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

EN_SET_GPO

RSVD

BITS

DESCRIPTION

DECODE

Enable Set GPO: Set to 1 to enable setting of GPO

0: Disable setting of GPO through SET_GPO

1: Enable setting of GPO through SET_GPO

7

6

5

from SET_GPO

Reserved: Do not change from default value

0: Reserved

0: Set GPIO output level low

1: Set GPIO output level high

GPIO_OUT_5

GPIO Output Level: Pull down GPIO when 0

0: Set GPIO output level lo

1: Set GPIO output level high

GPIO_OUT_4

GPIO_OUT_3

GPIO_OUT_2

GPIO_OUT_1

SET_GPO

4

3

2

1

0

GPIO Output Level: Pull down GPIO when 0

0: Set GPIO output leve

1: Set GPIO output level high

0: Set GPIO output level low

1: Set GPIO output level high

0: Set GPIO output level low

1: Set GPIO output level high

Set GPO Level: Set GPO output high or low (when

EN_SET_GPO = 1)

0: Set GPO output low

1: Set GPO output high

Maxim Integrated

│ 45

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

gpio_in (0x10)

BIT

7

6

RSVD

0b

5

4

3

2

1

0

Field

RSVD

0b

GPIO_IN_5 GPIO_IN_4 GPIO_IN_3 GPIO_IN_2 GPIO_IN_1

GPO_L

Xb

Reset

Xb

Access Type

Read Only

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

Reserved

0: Reserved

RSVD

0: Reserved

0: GPIO input is low

1: GPIO input is high

GPIO_IN_5

GPIO_IN_4

GPIO_IN_3

GPIO_IN_2

GPIO_IN_1

GPO_L

5

4

3

2

1

0

GPIO Input Level: Input pin level of GPIO

GPO Output Level

0: GPIO input is low

1: GPIO input is high

0: GPIO input is low

1: GPIO input is high

0: GPIO input is low

1: GPIO input is high

0: GPIO input is low

1: GPIO input is high

0: GPO output level is low

1: GPO output level is high

Maxim Integrated

│ 46

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

errg (0x11)

BIT

7

6

5

4

3

2

1

0

Field

ERRG_RATE[1:0]

0b

ERRG_TYPE[1:0]

0b

ERRG_CNT[1:0]

0b

ERRG_PER ERRG_EN

0b 0b

Reset

Access Type

Write, Read

Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

00: Generate errors every 2560 bits

01: Generate errors every 40,960 bits

10: Generate errors every 655,360 bits

11: Generate errors every 10,485,760 bits

Error-Generation Rate: Error-generation rate, on

average

ERRG_RATE

7:6

5:4

3:2

00: Single-bit errors

01: 2 8b/10b symbols

10: 3 8b/10b symbols

11: 4 8b/10b symbols

ERRG_TYPE

ERRG_CNT

Error-Generation Type: Type of generated errors

00: Generate errors continuously

01: Generate16 errors

10: Generate 128 errors

11: Generate 1024 errors

Error-Generation Count: Number of generated

errors

0: Generator creates errors randomly (based on

error rate)

1: Generator creates errors periodically (based

on error rate)

ERRG_PER

ERRG_EN

1

0

Periodic Error Generation Enable

Error Generator Enable

0: Disable error generator

1: Enable error generator

rsvd_12 (0x12)

BIT

Field

7

6

5

4

3

2

1

0

RSVD

0b

RSVD

1b

RSVD

0b

RSVD[4:0]

00000b

Reset

Access Type Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

Reserved: Do not change from default value

0: Reserved

RSVD

1: Reserved

RSVD

5

0: Reserved

RSVD

4:0

00000: Reserved

Maxim Integrated

│ 47

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

pd (0x13)

BIT

7

6

5

4

3

2

1

0

ALLOW_

PKTCC

Field

SOFT_PD

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD[1:0]

10b

Reset

0b

Write 1 to

Set, Read

Access Type

Write, Read Write, Read Write, Read Write, Read Write, Read

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

Soft Power Down: Set this bit to 1 to reset the

device; this bit is cleared after the device resets

0: Normal operation

1: Reset the device (bit clears itself)

SOFT_PD

7

0: Do not allow special signal to turn on packet-

based control channel

1: Allow special signal to turn on packet-based

control channel

Allow Packet Control Channel: Set this bit to 1

before turning on the packet-based control

channel.

ALLOW_

PKTCC

6

RSVD

5

4

Reserved: Do not change from default value

0: Reserved

10: Reserved

3

2

1:0

pktcc_lock (0x14)

BIT

7

6

5

RSVD

Xb

4

RSVD

Xb

3

2

RSVD

Xb

1

0

CC_

WBLOCK

REM_

CCLOCK

Field

RSVD[1:0]

XXb

RSVD

Xb

Reset

Xb

Read Clears

All

Access Type

Read Only

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7:6

5

Reserved

XX: Reserved

RSVD

X: Reserved

RSVD

4

RSVD

3

RSVD

2

CC_

WBLOCK

0: Control-channel word boundary is not locked

1: Control-channel word boundary is locked

1

0

Control-Channel Word Boundary Locked

Remote-Side Control Channel Locked

REM_

CCLOCK

0: Remote side control channel is not locked

1: Remote side control channel is locked

Maxim Integrated

│ 48

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

input_status (0x15)

BIT

Field

7

6

RSVD

Xb

5

4

RSVD

0b

3

RSVD

0b

2

RSVD

0b

1

0

CX_TP

Xb

LCCEN

Xb

OUTPUTEN PCLKDET

Reset

Xb

Access Type

Read Only

BITFIELD

CX_TP

BITS

DESCRIPTION

DECODE

0: CX/TP input is low

1: CX/TP input is high

7

6

5

Coax/Twisted Pair level: CX_TP pin level

Reserved

RSVD

X: Reserved

0: Pin is input low

1: Pin is input high

LCCEN

Detected LCCEN pin level

RSVD

4

3

2

Reserved

0: Reserved

0: Output disabled

1: Output enabled

OUTPUTEN

PCLKDET

1

0

Output Enabled

0: No valid PCLK detected

1: Valid PCLK detected

PCLK Detected: Valid PCLK detected

max_rt_err (0x16)

BIT

7

6

5

4

3

2

RSVD[5:0]

XXXXXXb

Read Only

1

0

MAX_RT_

ERR

Field

RSVD

0b

Reset

Xb

Read Clears

All

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

7

Reserved

0: Reserved

Maximum Retransmission Error: maximum

retransmission error bit

Goes high if packet control channel hits maximum

retransmission limit (8 retries). Cleared when read.

0: Device has not reached maximum

retransmission limit.

1: Device has reached maximum retransmission

limit.

MAX_RT_ERR

RSVD

6

5:0

Reserved

XXXXXX: Reserved

Maxim Integrated

│ 49

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

rsvd_17 (0x17)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[7:0]

XXXXXXXXb

Read Only

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

RSVD

Reserved

XXXXXXXX: Reserved

crc (0x18 to 0x1B)

BIT

Field

7

6

5

4

3

2

1

0

CRC_VALUE[7:0]

XXXXXXXXb

Read Only

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

CRC Value: CRC output for latest line

CRC_VALUE_3 to CRC_VALUE_0 represents

CRC[31:0]

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

CRC_VALUE

7:0

cc_crc_errcnt (0x1C)

BIT

Field

7

6

5

4

3

2

1

0

CC_CRC_ERRCNT[7:0]

XXXXXXXXb

Reset

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

CC_CRC_

ERRCNT

Control-Channel CRC Error Count: Packet-

based control-channel CRC error counter

7:0

rsvd_1d (0x1D)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[7:0]

XXXXXXXXb

Read Only

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

RSVD

Reserved

XXXXXXXX: Reserved

Maxim Integrated

│ 50

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

id (0x1E)

BIT

7

6

5

4

3

2

1

0

Field

ID[7:0]

Reset

XXXXXXXXb

Read Only

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

Device ID: 8-bit value depends on the GMSL

ID

01000001 Device is a MAX96705A

device attached

revision (0x1F)

BIT

Field

7

6

RSVD

0b

5

RSVD

0b

4

3

2

1

0

RSVD

0b

HDCPCAP

Xb

REVISION[3:0]

Reset

XXXXb

Access Type

Read Only

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

7

Reserved

0: Reserved

6

5

Reserved

0: Device does not have HDCP

1: Device is HDCP capable

HDCPCAP

4

HDCP Capability: 1 = HDCP capable

0000: Value is 0

0001: Value is 1

1111: Value is 15

REVISION 3:0

Device Revision

Maxim Integrated

│ 51

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

crossbar (0x20 to 0x3E)

BIT

Field

Reset

7

6

5

4

3

2

1

0

FORCE_

MUX

INVERT_

MUX

RSVD

CROSSBAR[4:0]

0b

XXXXXb

Access Type Write, Read Write, Read Write, Read

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

7

Reserved: Do not change from default value

Force Mux Output

0: Reserved

FORCE_

MUX

0: Input mapped to mux output

1: Force mux output low

6

5

INVERT_

MUX

0: Do not invert mux output

1: Invert mux output

Invert Mux Output

Crossbar Setting

00000: Mux outputs data from input 0

00001: Mux outputs data from input 1

11111: Mux outputs data from input 31

Select 1 of 32 input signals. Default values connect

Mux N with input N for ﬂow-through routing (i.e.,

DIN_ mapped to DOUT_).

CROSSBAR

4:0

crossbar_hs (0x3F)

BIT

Field

Reset

7

6

5

4

3

2

1

0

FORCE_

MUX_HS

INVERT_

MUX_HS

RSVD

0b

CROSSBARHS[4:0]

0b

01110b

Access Type Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

Reserved: Do not change from default value

0: Reserved

FORCE_MUX_

HS

0: Input mapped to mux output

1: Force mux output low

6

5

Force Mux Output

Invert Mux Output

INVERT_MUX_

HS

0: Do not invert mux output

1: Invert mux output

00000: Mux sync signal from DIN0

00001: Mux sync signal from DIN1

01111: Mux sync signal from DIN15

1XXXX: Do Not Use

Crossbar Setting HS: Select 1 of 16 input pins

for HS. Default values connect HS with the

corresponding named input pin.

CROSSBARHS

4:0

Maxim Integrated

│ 52

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

crossbar (0x40)

BIT

7

6

5

4

3

2

1

0

FORCE_

MUX_VS

INVERT_

MUX_VS

Field

RSVD

CROSSBARVS[4:0]

Reset

0b

01111b

Access Type Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

Reserved: Do not change from default value

0: Reserved

FORCE_MUX_

VS

0: Input mapped to mux output

1: Force mux output low

6

5

Force Mux Output

INVERT_MUX_

VS

0: Do not invert mux output

1: Invert mux output

Invert Mux Output

00000: Mux sync signal from DIN0

00001: Mux sync signal from DIN1

01111: Mux sync signal from DIN15

1XXXX: Do Not Use

Crossbar Setting VS: Select 1 of 16 input

pins for VS. Default values connect VS with the

corresponding named input pin.

CROSSBARVS

4:0

crossbar_de (0x41)

BIT

Field

Reset

7

6

5

4

3

2

1

0

FORCE_

MUX_DE

INVERT_

MUX_DE

RSVD

0b

CROSSBARDE[4:0]

0b

01101b

Access Type Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

Reserved: Do not change from default value

0: Reserved

FORCE_MUX_

DE

0: Input mapped to mux output.

1: Force mux output low.

6

5

Force Mux Output

INVERT_MUX_

DE

0: Do not invert mux output.

1: Invert mux output.

Invert Mux Output

00000: Mux sync signal from DIN0

Crossbar Setting DE: Select 1 of 16 input pins for 00001: Mux sync signal from DIN1

CROSSBARDE

4:0

DE. Default values connect DE with DIN13.

01111: Mux sync signal from DIN15

1XXXX: Do Not Use

Maxim Integrated

│ 53

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

link_conﬁg (0x42)

BIT

7

6

5

4

3

2

1

GPI_RT_EN

1b

0

GPO_EN

1b

LINE_CRC_ MAX_RT_

GPI_

COMP_EN

Field

LINE_CRC_LOC[1:0]

RSVD

EN

Reset

01b

0b

1b

0b

Access Type

Write, Read

Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

00: CRC insertion at [1...4]

LINE_CRC_

LOC

Line CRC Location: Video line CRC insertion

location

01: CRC insertion at [5...8]

10: CRC insertion at [9...12]

11: CRC insertion at [13...16]

7:6

5

LINE_CRC_

EN

0: Disable CRC

1: Enable CRC

Line CRC Enable: Video line CRC enable

0: Disable maximum retransmission limit

1: Enable maximum retransmission limit

MAX_RT_EN

RSVD

4

3

2

Maximum Retransmission Limit Enable

Reserved: Do not change from default value

GPI Compensation Enable

1: Reserved

GPI_COMP_

EN

0: Disable GPI compensation

1: Enable GPI compensation

0: Disable GPI retransmission

1: Enable GPI retransmission

GPI_RT_EN

GPO_EN

1

0

GPI Retransmission Enable

0: Disable GPO pin

1: Enable GPO pin

GPO Enable: Enable GPO pin

Maxim Integrated

│ 54

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

sync_gen_conﬁg (0x43)

BIT

Field

Reset

7

6

5

GEN_VS

0b

4

GEN_HS

0b

3

GEN_DE

0b

2

VS_TRIG

1b

1

0

RSVD

0b

RSVD

0b

VTG_MODE[1:0]

01b

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

Reserved: Do not change from default value

0: Reserved

RSVD

0: Disable VS output generation (VS used from

VSYNC Generation: Enable to generate VS output input)

GEN_VS

GEN_HS

5

4

according to the timing deﬁnition

1: Enable VS output generation (VS internally

generated)

0: Disable HS output generation (HS used from

HSYNC Generation: Enable to generate HS

input)

utput according to the timing deﬁnition

1: Enable HS output generation (HS internally

generated)

0: Disable DE output generation (DE used from

DE Generation: Enable to generate DE output

according to the timing deﬁnition

input)

GEN_DE

VS_TRIG

3

2

1: Enable DE output generation (DE internally

generated)

0: VS trigger uses falling edge

1: VS trigger uses rising edge

VSYNC Trigger Edge Select

00: VS input is tracked and then locked after

three consecutive matches (three consecutive

mismatches unlock tracking)

01: VS edge triggers one VS frame (current frame

is extended/cut short to adjust timing to next

trigger)

VTG_

MODE

1:0

Video Timing Generator Mode

10: VS edge triggers VS generation (current frame

is extended/cut short to adjust timing to next

trigger)

11: Same as above

Maxim Integrated

│ 55

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

vs_dly (0x44 to 0x46)

BIT

Field

7

6

5

4

3

2

1

0

VS_DLY[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

VSYNC Delay: VS delay in terms of PCLK cycles;

the output VS delay by VS_DELAY cycles from the 00000001: Value is 1

input VS. 11111111: Value is 255

00000000: Value is 0

VS_DLY

7:0

vs_h (0x47 to 0x49)

BIT

Field

7

6

5

4

3

2

1

0

VS_H[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

VSYNC High: VS high period in terms of PCLK

cycles.

VS_H

7:0

vs_l (0x4A to 0x4C)

BIT

Field

7

6

5

4

3

2

1

0

VS_L[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

VSYNC Low: VS low period in terms of PCLK

cycles

VS_L

7:0

Maxim Integrated

│ 56

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

cxtp (0x4D)

BIT

7

6

5

4

3

2

1

DE_INV

0b

0

VSYNC_

INV

HSYNC_

INV

Field

HIGHIMM

CXTP

RSVD

Reset

Xb

0b

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

High-Immunity Mode: Default value depends on

the state of the HIM input

0: Use legacy reverse-channel mode

1: Use high-immunity mode

HIGHIMM

7

Coax/Twisted Pair Select

Default value depends on the state of the CONF0,

CONF1 inputs

0: Use diﬀerential output (STP mode)

1: Use dual single ended outputs (coax)

CXTP

6

RSVD

5

4

Reserved: Do not change from default value

0: Reserved

VSYNC_

INV

VSYNC Inversion: Invert output VSYNC in

TIMING GEN

0: Do not invert VS in timing generator

1: Invert VS in timing generator

3

2

HSYNC_

INV

HSYNC Inversion: Invert output HSYNC in

TIMING GEN

0: Do not invert HS in timing generator

1: Invert HS in timing generator

0: Do not invert DE in timing generator

1: Invert DE in timing generator

DE_INV

RSVD

1

0

DE Inversion: Invert output DE in TIMING GEN

Reserved: Do not change from default value

0: Reserved

Maxim Integrated

│ 57

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

hs_dly (0x4E to 0x50)

BIT

Field

7

6

5

4

3

2

1

0

HS_DLY[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

VSYNC to HSYNC Delay: VS edge to the rising

edge of the ﬁrst HS in terms of PCLK cycles

(bits [15:8])

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

HS_DLY

7:0

rsvd (0x51 to 0x53, 0x5D to 0x5F)

BIT

Field

7

6

5

4

3

2

1

0

RSVD[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

[7:0]

Reserved: Do not change from default value

00000000: Reserved

Maxim Integrated

│ 58

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

hs_h (0x54, 0x55)

BIT

Field

7

6

5

4

3

2

1

0

HS_H[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

HSYNC High Period: HS high period in terms of

PCLK cycles

HS_H

7:0

hs_l (0x56, 0x57)

BIT

Field

7

6

5

4

3

2

1

0

HS_L[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

HSYNC Low Period: HS low period in terms of

HS_L

PCLK cycles.

hs_cnt (0x58, 0x59)

BIT

Field

7

6

5

4

3

2

1

0

HS_CNT[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

HS_CNT

7:0

HSYNC Count: Lines per panel (bits [7:0]).

11111111: Value is 255

Maxim Integrated

│ 59

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

de_dly (0x5A to 0x5C)

BIT

Field

7

6

5

4

3

2

1

0

DE_DLY[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

VSYNC to DE

VS falling edge to the rising edge of the ﬁrst DE in

terms of PCLK cycles.

00000000: Value is 0.

00000001: Value is 1.

11111111: Value is 255.

DE_DLY

7:0

de_h (0x60, 0x61)

BIT

Field

7

6

5

4

3

2

1

0

DE_H[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

DE High Period: DE high period in terms of PCLK

DE_H

cycles.

de_l (0x62, 0x63)

BIT

Field

7

6

5

4

3

2

1

0

DE_L[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

11111111: Value is 255

DE Low Period: DE low period in terms of PCLK

DE_L

cycles

Maxim Integrated

│ 60

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

de_cnt (0x64, 0x65)

BIT

Field

7

6

5

4

3

2

1

0

DE_CNT[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

DESCRIPTION

DECODE

00000000: Value is 0

00000001: Value is 1

DE_CNT

7:0

DE Count: Active lines per panel

11111111: Value is 255

prbs_type (0x66)

BIT

7

6

5

4

3

DE_EN

0b

2

1

0

PRBS_

TYPE

DIS_

RWAKE

Field

RSVD[1:0]

REV_FAST

0b

RSVD

0b

CXSEL

1b

Reset

01b

1b

0b

Access Type

Write, Read

Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

7:6

Reserved: Do not change from default value

01: Reserved

PRBS_

TYPE

0: Select legacy PRBS mode

1: Select MAX9271–MAX9273 PRBS mode

5

PRBS Type: PRBS type select

REV_

FAST

0: Disable reverse channel fast mode

1: Enable reverse channel fast mode

4

3

Reverse Channel Fast-Mode Enable

0: Disable separate processing of HS and DE

signals

1: Enable separate processing of HS and DE

signals

DE Enable: Enable processing separate HS and

DE signals

DE_EN

DIS_

RWAKE

Disable Remote Wake-Up: Disable wake-up

receiver

0: Do not disable remote wake-up receiver

1: Disable remote wake-up receiver

2

1

0

RSVD

Reserved: Do not change from default value

0: Reserved

0: Coax cable connected to inverting output

1: Coax cable connected to noninverting output

CXSEL

Coax Select

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

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dbl_align_to (0x67)

BIT

7

6

5

4

3

2

1

0

AUTO_

CLINK

Field

RSVD[1:0]

RSVD

DBL_ALIGN_TO[2:0]

Reset

11b

0b

111b

Access Type

Write, Read

Write, Read Write, Read Write, Read

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

7:6

Reserved: Do not change from default value

11: Reserved

0: Enable conﬁguration link only when

AUTO_

CLINK

Auto Conﬁguration Link: Automatic control of

conﬁguration link

CLINKEN = 1 and SEREN = 0

1: Automatically enable conﬁguration link when

5

SEREN = 1 and PCLKDET = 0

RSVD

4

3

Reserved: Do not change from default value

0: Reserved

000: Align at each rising edge of HS. Turn oﬀ

alignment after HS is low (MAX9286). Use this

setting when an external high/low signal is used.

001: Do not use

010: Force align

011: Do not use

100: Align at each rising edge of HS

101: Align at each rising edge of DE

110: Force align

Double Alignment Mode: Sets the alignment

mode when DBL = 1 in the serializer and DBL =

0 in the deserializer. Set DBL_ALIGN_TO = 000

when an external high-low signal is used

(EN_HI_LO =1).

DBL_

ALIGN_TO

2:0

111: No alignment done while in DBL mode

cc_crc_length (0x68)

BIT

Field

Reset

7

6

5

4

3

2

1

0

RSVD

0b

RSVD[2:0]

001b

RSVD[1:0]

10b

CC_CRC_LENGTH[1:0]

01b

Access Type Write, Read

Write, Read

BITFIELD

RSVD

BITS

7

DESCRIPTION

DECODE

Reserved: Do not change from default value

0: Reserved

RSVD

6:4

3:2

001: Reserved

10: Reserved

RSVD

00: 1-bit CC CRC length

01: 5-bit CC CRC length

10: 8-bit CC CRC length

11: Do not use

CC_CRC_

LENGTH

1:0

Control-Channel CRC Length

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

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hi_lo (0x69)

BIT

7

6

EN_HI_LO

0b

5

4

3

2

1

0

INVERT_

HI_LO

Field

RSVD

CROSSBAR_HI_LO[4:0]

Reset

0b

01111b

Access Type Write, Read Write, Read Write, Read

Write, Read

BITFIELD

BITS

DESCRIPTION

DECODE

RSVD

7

Reserved: Do not change from default value

0: Reserved

0: Do not align using a Hi-Lo signal

1: Use a Hi-Lo signal to align input data

EN_HI_LO

6

5

Enable High/Low Signal Alignment

INVERT_HI_

LO

0: Do not invert Hi-Lo signal

1: Invert Hi-Lo signal

Invert High/Low Signal Alignment

Crossbar High Low: Select 1 of 16 input pins for

the Hi-Lo signal. Default values connect the Hi-Lo

signal to the VS input pin (eﬀective when

DBL_ALIGN_TO = 000).

00000: Mux Hi-Lo signal from DIN0

00001: Mux Hi-Lo signal from DIN1

01111: Mux Hi-Lo signal from DIN15

1XXXX: Do Not Use

CROSSBAR_

HI_LO

4:0

rsvd_96 (0x96)

BIT

Field

7

6

5

4

3

2

1

0

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

Xb

RSVD[1:0]

10b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

Reserved: Do not change from default value

0: Reserved

X: Reserved

10: Reserved

5

4

3

2

1:0

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

rsvd_97 (0x97)

BIT

7

6

5

4

3

2

1

0

Field

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

1b

RSVD

1b

RSVD[2:0]

111b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

5

4

3

Reserved: Do not change from default value

0: Reserved

1: Reserved

111: Reserved

RSVD

2:0

rsvd_98 (0x98)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[1:0]

01b

RSVD[2:0]

001b

RSVD[2:0]

010b

Reset

Access Type

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7:6

5:3

2:0

Reserved: Do not change from default value

01: Reserved

001: Reserved

010: Reserved

RSVD

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

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rsvd_99 (0x99)

BIT

7

6

5

4

3

2

1

0

Field

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

1b

RSVD

1b

RSVD[1:0]

01b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

5

4

3

2

Reserved: Do not change from default value

0: Reserved

1: Reserved

01: Reserved

1:0

pktcc_en (0x9A)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[1:0]

00b

RSVD[1:0]

01b

PKTCC_EN

RSVD[1:0]

RSVD

0b

Reset

0b

00b

Access Type

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7:6

5:4

Reserved: Do not change from default value

00: Reserved

01: Reserved

RSVD

PKTCC_

EN

0: Disable packet-based control-channel mode

1: Enable packet-based control-channel mode

3

Packet-Based Control-Channel-Mode Enable

RSVD

2:1

0

Reserved: Do not change from default value

00: Reserved

0: Reserved

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

rsvd_C8 (0xC8)

BIT

7

6

RSVD

Xb

5

RSVD

Xb

4

RSVD

Xb

3

RSVD

0b

2

RSVD

0b

1

RSVD

0b

0

RSVD

0b

Field

RSVD

0b

Reset

Access Type Write, Read

Read Only

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

5

4

3

2

1

0

Reserved: Do not change from default value

0: Reserved

Reserved

X: Reserved

0: Reserved

rsvd_c9 (0xC9)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[7:0]

XXXXXXXXb

Read Only

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

RSVD

Reserved

XXXXXXXX: Reserved

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

rsvd_fc (0xFC)

BIT

7

6

5

4

3

2

1

0

Field

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

Reset

Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7

6

5

4

3

2

1

0

Reserved: Do not change from default value

0: Reserved

rsvd_fd (0xFD)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[7:0]

00000000b

Write, Read

Reset

Access Type

BITFIELD

BITS

7:0

DESCRIPTION

DECODE

RSVD

Reserved: Do not change from default value

00000000: Reserved

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

rsvd_fe (0xFE)

BIT

7

6

5

4

3

2

1

0

Field

RSVD[3:0]

0000b

RSVD[3:0]

0000b

Reset

Access Type

Write, Read

BITFIELD

RSVD

BITS

DESCRIPTION

DECODE

7:4

3:0

Reserved: Do not change from default value

0000: Reserved

RSVD

rsvd_ﬀ (0xFF)

BIT

Field

7

6

5

4

3

2

1

0

RSVD

0b

RSVD

0b

RSVD

0b

RSVD

0b

RSVD[3:0]

Reset

XXXXb

Access Type Write, Read Write, Read Write, Read Write, Read

Read Only

BITFIELD

RSVD

BITS

DESCRIPTION

Reserved: Do not change from default value

Reserved

DECODE

7

6

0: Reserved

XXXX: Reserved

RSVD

5

RSVD

4

RSVD

3:0

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

or when in double mode (DBL = 1). Table 3 shows the

available bit widths and default mapping for various

modes.

Applications Information

Parallel Interface

The CMOS parallel interface-data width is programmable

and depends on the application. Using a larger width

(BWS = 1) results in a lower-pixel clock rate, while a

smaller width (BWS = 0) allows a higher-pixel clock rate.

Bus Data Rates

The bus data rate depends on the settings for BWS and

DBL. Table 4 lists the available PCLK rates available for

different bus-width settings. For lower PCLK rates, set

DBL = 0 (if DBL = 1 in both the serializer and deserializer).

Bus Data Width

The bus data width depends on the selected modes. The

available bus width is less when using error detection

Table 3. Input Data-Width Selection

REGISTER BIT SETTINGS

INPUT MAPPING

(WITH 96706)

INPUT MAPPING

(WITH OTHER)

DBL

1

BWS

1

HIBW

—

1

PXL_CRC

HVEN

1

0

1

0

1

0

1

0

-

1

0

DIN11:0, HS, VS

DIN11:0

DIN11:0, HS, VS

DIN11:0

1

**

1

DIN11:0 , HS, VS

DIN13:0*, HS, VS

DIN14:0

1

0

DIN13:0**

DIN8:0, HS, VS

DIN11:0, HS, VS

DIN7:0, HS, VS

DIN7:0

1

0

—

1

DIN8:0, HS, VS

DIN11:0, HS, VS

DIN7:0, HS, VS

DIN7:0

1

0

1

0

1

0

1

0

1

DIN10:0, HS, VS

DIN10:0

DIN10:0, HS, VS

DIN10:0

1

0

1

—

1

DIN11:0**, HS, VS

DIN13:0**

DIN13:0*, HS, VS

DIN15:0*

0

1

0

1

DIN11:0**, HS, VS

DIN13:0*

DIN13:0*, HS, VS

DIN15:0*

0

1

0

—

1

DIN11:0**, HS, VS

DIN13:0**

DIN13:0*, HS, VS

DIN15:0*

0

1

0

1

DIN11:0**, HS, VS

DIN13:0**

DIN13:0*, HS, VS

DIN15:0*

0

*The input bit width is limited by the number of available inputs.

**The input bit width is limited by the number of available outputs on the deserializer.

Table 4. Data-Rate Selection

DBL

BWS

HIBW

PCLK RANGE (MHz)

1

0

1

0

1

0

1

0

1

25 to 87

33.3 to 116

73.3 to 116

12.5 to 43.5

16.7 to 58

36.6 to 58

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

2. Set the low- and high-input crossbar bits (CROSSBAR0,

CROSSBAR 16) to the desired selected mapped input

(e.g., CROSSBAR0 = 00100, CROSSBAR16 = 10100).

Crossbar Switch

By default, the crossbar switch connects the serializer

input pins DIN_ and HS/VS (when HV encoding is used)

to the corresponding deserializer output pins DOUT_ and

HS/VS. Reprogram the crossbar switch when changing

the input or output pin assignments, or when connecting

to devices that do not have a DBL = 1 mode.

3. Repeat for the other crossbar outputs, making sure

the set of high and low crossbar outputs are assigned

to the same crossbar input set. In general, XBO[i] and

XBO[i+16] should be assigned to XBI[j] and XBI[j+16].

4. For XBOHS, XBOVS, and XBODE, set crossbar to use

the low-input pins (CROSSBAR_ = 00000 to 01111). Note

that HS, VS, and DE use both the low and high input.

Crossbar-Switch Programming

Each crossbar-switch output can select any of the 16

DIN_ inputs for either high or low words (when DBL =

1) for a total of 32 possible inputs. Multiple outputs can

share the same input. HS, VS, and DE remain the same

for both word halves, and should be programmed to use

the low-word input of the corresponding pin. To invert

an input data bit, set the respective INVERT_MUX_ =

1. To force an output low, (and ignore the input) set the

FORCE_MUX_ bit = 1. To force an output high set both

INVERT_MUX_ and FORCE_MUX_ = 1.

● Both Devices' DBL Do Not Match

1. Table 5, Table 6, and Table 7 list which crossbar output

(XBO_) maps to each serial bit.

2. For each crossbar output, select which pin and high/

low clock cycle (if needed) to map (e.g., DIN4 low input).

3. Set the crossbar bits (CROSSBAR_) to select the

desired selected mapped input (e.g., CROSSBAR0 =

00100 maps DIN4 low input to XBO0).

Recommended Crossbar-Switch Program Procedure

4. Repeat for the other crossbar outputs; any unused

serial bits should have a force low mapped to the

respective crossbar output.

The procedure to program the crossbar switch depends on

the DBL settings on the serializer and deserializer. Devices

without double mode can be assumed to have DBL = 0.

5. For XBOHS, XBOVS, and XBODE, set crossbar to use

the low-input pins (CROSSBAR_ = 00000 to 01111). Note

that HS, VS, and DE use both the low and high input.

● Both Devices' DBL Set to the Same Value

1. For the crossbar-output equivalent of DIN0 (XBO0,

XBO16) select which pin to map (e.g., DIN4 ➔ XBI4,

XBI20).

Table 5. Crossbar Output to Serial Link Map (D23:0)

BIT SETTING

SERIAL BITS

10 11 12 13 14 15 16 17 18 19 20 21 22 23

DB HV BW HB CR DE

0

1

2

3

4

5

6

7

8

9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

10 11 12 13 14 15

Z

F

Z

F

Z

5

F

4

Z

E

Z

E

Z

6

Z

E

Z

E

Z

7

Z

E

Z

F

Z

E

Z

8

Z

E

Z

E

Z

E

Z

9

Z

E

Z

F

E

F

E

Z

F

E

Z

F

E

F

P

Z

P

Z

P

E

Z

E

Z

16 17 18 19 20 21 22 23 24 25 26

16 17 18 19 20 21 22 23

0

3

1

4

0

2

5

1

3

6

2

4

7

3

10

E

Z

0

1

2

E

5

E

6

E

7

E

8

16 17 18 19 20 21 22 23 24 25 26 27

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Table 5. Crossbar Output to Serial Link Map (D23:0) (continued)

BIT SETTING

SERIAL BITS

DB HV BW HB CR DE

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

0

1

0

1

0

X

1

0

16 17 18 19 20 21 22 23 24

0

1

2

3

4

5

6

0

7

1

4

5

F

1

4

8

2

5

6

E

2

5

Z

3

6

7

E

3

6

F

4

7

8

E

4

7

E

5

8

9

E

5

8

E

6

E

7

P

8

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

16 17 18 19 20 21 22 23 24 25 26 DH

16 17 18 19 20 21 22 23 24 25 26 27

0

1

4

1

2

5

2

3

6

3

9

10 DL

10 11

3

9

16 17 18 19 20 21 22 23 24 25 DH

16 17 18 19 20 21 22 23 24 25 26

0

3

4

DL

10

E

6

F

E

7

P

8

4

16 17 18 19 20 21 22 DH

16 17 18 19 20 21 22 23

0

1

2

DL

7

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

0

16 17 18 19 20 21 22 23 24 25 26 DH

16 17 18 19 20 21 22 23 24 25 26 27

0

1

2

3

9

10 DL

10 11

3

9

Table 6. Crossbar Output to Serial Link Map (D31:24 and Special Packets)

BIT SETTING

SPECIAL PACKETS

DB HV BW HB CR DE

24

—

Z

25

—

Z

26

—

Z

27

—

Z

28

—

Z

29

—

Z

30

—

F

31

—

P

C0

—

Z

C1

—

Z

C2

—

Z

C3

—

Z

HS

—

H

VS

—

V

DE

—

D

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

E

Z

H

V

D

Z

—

A

—

Z

—

A

—

A

—

H

—

V

—

D

F

E

P

—

Z

—

Z

—

Z

—

Z

—

Z

—

Z

—

F

—

P

H

V

H

V

F

E

P

H

V

—

9

—

10

E

—

11

E

—

12

E

—

13

E

—

14

E

—

F

—

P

—

H

—

V

E

A

Z

A

H

V

D

9

10

E

11

E

—

-

—

-

—

-

—

-

—

-

F

E

P

0

F

E

P

1

—

9

—

10

E

—

11

E

—

12

E

—

13

E

—

14

E

—

F

—

P

HH/L VH/L

0

1

0

X

1

F

E

P

0

F

E

P

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Table 7. Legend

BIT SETTINGS

MAP INPUTS

DB

HV

BW

HB

CR

DE

X

Double-mode bit DBL

H

V

HSYNC ( when DBL = 0 or HIBW = 1)

VSYNC ( when DBL = 0 or HIBW = 1)

DE ( when DBL = 0 or HIBW = 1)

HSYNC (high word, DBL = 1)

VSYNC (high word, DBL = 1)

DE (high word, DBL = 1)

H/V Encoding bit HVEN

BWS bit

D

HIBW bit

HH

VH

DH

HL

VL

DL

#

PXL_CRC bit

DE = 1 when DEEN = 1 and not processed in RGB888 mode

1 or 0

HSYNC (low word, DBL = 1)

VSYNC (low word, DBL = 1)

DE (low word, DBL = 1)

SPECIAL PACKETS

C0

C1

C2

C3

CNT_0

CNT_1

CNT_2

CNT_3

XBO output from crossbar switch

Internal forward control-channel bit

Internal pixel CRC bit

F

E

BIT COLOR

Output bits from crossbar

P

Internal pixel parity bit

—

Z

Serial bit not sent

Internal bits

Zero

Other output bits

Output bits from sync

A

Internal alignment bit (used when HIBW=1)

INPUT PIN

PIXEL

PCLK

N

N+1

DIN15/VS

DIN14/HS

DIN13

DIN12

DIN11

DIN10

DIN9

DIN8

DIN7

DIN6

DIN5

XBI31

XBI30

XBI29

XBI28

XBI27

XBI26

XBI25

XBI24

XBI23

XBI22

XBI21

XBI20

XBI19

XBI18

XBI17

XBI16

XBI15

XBI14

XBI13

XBI12

XBI11

XBI10

XBI9

XBI8

XBI7

XBI6

XBI5

XBI4

XBI3

XBI2

XBI1

XBI0

XBI31

XBI30

XBI29

XBI28

XBI27

XBI26

XBI25

XBI24

XBI23

XBI22

XBI21

XBI20

XBI19

XBI18

XBI17

XBI16

XBI15

XBI14

XBI13

XBI12

XBI11

XBI10

XBI9

XBI8

XBI7

XBI6

XBI5

XBI4

XBI3

XBI2

XBI1

XBI0

DIN4

DIN3

DIN2

DIN1

*REGISTER SETTINGS

DECIDE IF HS, DE, OR HI_LO

DETERMINES THE HIGH/LOW

INPUT TIMING.

DIN0

ALIGNMENT

HS*

HS

DE

HS

DE

DE*

HI_LO*

Figure 20. Crossbar-Switch Default Mapping

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

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Align from HS or DE

Timing-Generator Programming

To align from a sync signal, set the DBL_ALIGN_TO to

select the input signal. When using this mode, ensure

that the signal used for alignment uses the same value

for both the high and low word (e.g., for pixels [1H, 1L,

2H, 2L...], aligning on DE requires values of [DE1, DE1,

DE2, DE2...]).

Timing-generator parameters are stored in the registers

as unsigned integers as PCLK periods. To prevent output

glitches, program all timing-generator parameters while

the device is in configuration-link mode, or when PCLK

is not applied. By default, the timing generator is set to

single trigger, and is disabled. Figure 18 show the timing

waveforms under the default conditions with rising-edge

trigger, and noninverted signals. Do not program the

HSYNC or DE signals such that the total length exceeds

the length of a VSYNC period (Table 8). All delay

parameters are positive. To implement a negative delay,

set the delay value subtracted from the VSYNC period

(e.g., a delay value of VS_HIGH + VS_LOW - N creates

a delay of -N PCLK cycles). Do not set any delay lengths

larger than the VSYNC period.

Control-Channel Interfaces

2

I C

2

Set I2CSEL = 1 to configure the control channel for I C

2

to I C. In this mode, the control channel forwards I C

commands from the microcontroller side to the other

2

side of the GMSL link. The remote device acts as an I C

master to the other peripherals connected to the remote-

2

side device. I C-to-I C mode uses clock stretching to hold

the microcontroller until the data and an acknowledge or

not acknowledge have been sent across the link.

Double-Mode Alignment

When DBL = 1 in both the serializer and deserializer, GMSL

automatically keeps the pixels in order. Use double-mode

alignment when DBL = 1 in the serializer and DBL = 0

(or is not supported) in the deserializer. Two different

methods are available for double-mode alignment.

2

I C Bit Rate

2

The I C interface accepts bit rates from 9.6kbps to

2

1Mbps. The local I C rate is set by the microcontroller.

2

The remote I C rate is set by the remote device. By

2

default, the control channel is set up for a 400kbps I C bit

External High/Low Signal

rate. Program the I2C_MSTBT and SLV_SH bits (register

To use an external alignment signal, set EN_HI_LO =

1, DBL_ALIGN_TO = 000, and select which input DIN_

pin to use by setting the CROSSBAR_HI_LO bits. The

external signal designates whether the clocked word is

the high or low word (e.g., for pixels [1H, 1L, 2H, 2L...] the

high/low signal would be [1, 0, 1, 0...]).

2

0x0D) to match the desired microcontroller I C rate.

Software Programming of Device Addresses

The serializer and deserializer have programmable device

addresses. This allows multiple GMSL devices, along with

2

I C peripherals, to coexist on the same control channel.

The serializer device address is in register 0x00 of each

device, while the deserializer device address is in register

0x01 of each device. To change a device address, first

Table 8. Timing-Generator Parameter Restrictions

MIN VALUE

(HEX)

MAXIMUM VALUE RESTRICTION

(HEX)

SIGNAL

SIZE (BITS)

VS_HIGH

VS_LOW

VS_DLY

HS_HIGH

HS_LOW

HS_CNT

HS_DLY

DE_HIGH

DE_LOW

DE_CNT

DE_DLY

24

16

24

16

24

1

0

1

0

1

0

VS_HIGH + VS_LOW < 0xFFFFFF

VS_DLY < VS_HIGH + VS_LOW

(HS_HIGH + HS_LOW) x HS_CNT < VS_HIGH + VS_LOW

HS_DLY < VS_HIGH + VS_LOW

(DE_HIGH + DE_LOW) x DE_CNT < VS_HIGH + VS_LOW

DE_DLY < VS_HIGH + VS_LOW

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16-Bit GMSL Serializer with High-Immunity/

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write to the device whose address changes (register 0x00

of the serializer for serializer device address change, or

register 0x01 of the deserializer for deserializer device

address change). Then, write the same address into the

corresponding register on the other device (register 0x00

of the deserializer for serializer device address change,

or register 0x01 of the serializer for deserializer device

address change).

UART

Set I2CSEL = 0 to configure the control channel for UART

or UART-to-I C mode. In this mode, the control channel

forwards UART commands from the microcontroller side

to the other side of the GMSL link. When INTTYPE =

00, the remote device acts as an I C master to the other

2

peripherals connected to the remote-side device. UART-

2

to-I C mode does not support devices that use clock

stretching.

2

I C Address Translation

2

The device supports I C address translation for up to

Base Mode

two device addresses. Use address translation to assign

unique device addresses to peripherals with limited

I C addresses. Source addresses (address to translate

from) are stored in registers 0x09 and 0x0B. Destination

addresses (address to translate to) are stored in registers

0x0A and 0x0C.

In base mode, UART packets control the serializer,

deserializer, and attached peripherals.

2

UART Timing

In base mode, the UART idles high (through a pullup

resistor). Each GMSL UART byte consists of a START bit,

8 data bits, an even-parity bit, and a STOP bit (Figure 21).

Keep the idle time between bytes of the same UART packet

to less than 4 bit times. The GMSL-UART protocol is listed in

Figure22.AwritepacketconsistsofaSYNCbyte(Figure23),

device address byte, starting register address byte,

number of bytes to write, and the data bytes. The slave

device responds with an ACK byte (Figure 24) if the write

was successful. A read packet consists of a SYNC byte,

device address byte, starting register address byte, and

number of bytes to read. The slave device responds with

an ACK byte, and the read data bytes.

Conﬁguration Blocking

The device can block changes to its registers. Set

CFGBLOCK to make all registers read-only. Once set, the

registers remain blocked until the supplies are removed or

until PWDNB is low.

Cascaded/Parallel Devices

GMSL supports both cascaded and parallel devices

2

connected through I C. When cascading or using parallel

2

links, all I C commands are forwarded to all links. Each

link attempts to hold the control channel until it receives

an acknowledge/not acknowledge from the remote-side

device. It is important to keep the control channel active

between links to prevent timeout. If a link is unused, keep

the control channel clear by turning on the configuration

2

UART-to-I C Conversion

When using the UART control channel, the remote-side

2

device can communicate to I C peripherals through

2

UART-to-I C conversion. Set the INTTYPE bits in

2

link, disconnecting the I C lines, or powering down the

2

the remote-side device to 00 to activate UART-to-I C

unused device.

2

conversion. The converted I C bit rate is the same as

2

Dual μC Control

the incoming UART bit rate. I C peripherals must not use

clock stretching in order to be compatible with UART-to-

I C conversion.

Most systems use a single microcontroller; however μCs

can reside on each side simultaneously and trade off

in running the control channel. Contention occurs if both

μCs attempt to use the control channel at the same time. It

is up to the user to prevent this contention by implementing

a higher level protocol. In addition, the control channel

2

There are two possible methods the devices use to

2

convert UART to I C. In the first method (I2CMETHOD =

2

0), the register address is sent with the I C communication

(Figure 25). For devices that do not use a register address

(such as the MAX7324), set I2CMETHOD = 1 and send

a dummy byte in place of the register address (Figure

26). In this method, the remote device omits sending the

register address.

2

does not provide arbitration between I C masters on

both sides of the link. An acknowledge frame is not

generated when communication fails due to contention. If

communication across the serial link is not required, the

μCs can disable the forward and reverse control channel

using the FWDCCEN and REVCCEN bits (0x04, D[1:0])

in the serializer/deserializer. Communication across the

serial link is stopped and contention between μCs cannot

occur.

UART Bypass Mode

In UART bypass mode, the control channel acts as a

full-duplex 9.6kbps to 1Mbps link that forwards UART

commands across the serial link without responding to

the packets themselves. Set MS high to enter bypass

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16-Bit GMSL Serializer with High-Immunity/

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1 UART FRAME

START

D0

D1

D2

D3

D4

D5

D6

D7

PARITY*

STOP

FRAME 1

FRAME 2

FRAME 3

STOP

START

STOP

START

*BASE MODE USES EVEN PARITY

Figure 21. GMSL-UART Data Format for Base Mode

WRITE DATA FORMAT

DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1

SYNC

BYTE N

ACK

MASTER READS FROM SLAVE

MASTER WRITES TO SLAVE

READ DATA FORMAT

SYNC

DEV ADDR + R/W REG ADDR NUMBER OF BYTES

MASTER WRITES TO SLAVE

ACK

BYTE 1

BYTE N

MASTER READS FROM SLAVE

Figure 22. GMSL-UART Protocol for Base Mode

D0

1

D1

0

D2

0

D3

1

D4

1

D5

1

D6

1

D7

0

D0

1

D1

1

D2

0

D3

0

D4

0

D5

0

D6

1

D7

1

START

PARITY STOP

START

PARITY STOP

Figure 23. SYNC Byte (0x79)

Figure 24. ACK Byte (0xC3)

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16-Bit GMSL Serializer with High-Immunity/

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mode (wait 1ms after setting bypass mode if the μC is

connected on the deserializer side). Do not send a UART

vommand during this time. Bypass uses bit rates from

9.6kbps to 1Mbps. Although MS on either device sets the

control-channel bypass mode, only the local-side device

(connected to the μC) should be used to set bypass

mode. Do not switch MS while a UART command is being

sent. Do not send a logic-low value longer than 100μs

when using the GPI/GPO functionality.

Device Address

The serializer/deserializer both have a 7-bit-long slave

address stored in registers 0x00 and 0x01. The bit

following a 7-bit slave address is the R/W bit, which is

low for a write command and high for a read command.

The default slave address is 0x80. After startup, a

microcontroller can reprogram the slave address as

needed.

2

UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)

SERIALIZER/DESERIALIZER

11

µC

11

SYNC FRAME

DEVICE ID + WR

REGISTER ADDRESS NUMBER OF BYTES

DATA 0

DATA N

ACK FRAME

SERIALIZER/DESERIALIZER

PERIPHERAL

1

7

1

8

1

8

1

8

1

S

DEV ID

W

A

REG ADDR

A

DATA 0

A

DATA N

A

P

2

UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 0)

SERIALIZER/DESERIALIZER

11

µC

11

ACK FRAME

11

DATA 0

11

DATA N

SYNC FRAME

DEVICE ID + RD

REGISTER ADDRESS NUMBER OF BYTES

SERIALIZER/DESERIALIZER

PERIPHERAL

1

7

1

8

1

7

1

8

1

8

1

S

DEV ID

W

A

REG ADDR

A

S

DEV ID

R

A

DATA 0

A

DATA N

A

P

S: START

P: STOP

A: ACKNOWLEDGE

: MASTER TO SLAVE

: SLAVE TO MASTER

2

Figure 25. Format Conversion Between GMSL UART and I C with Register Address (I2CMETHOD = 0)

2

UART-TO-I C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)

µC

SERIALIZER/DESERIALIZER

11

SYNC FRAME

11

DATA 0

11

DATA N

11

DEVICE ID + WR

REGISTER ADDRESS NUMBER OF BYTES

ACK FRAME

SERIALIZER/DESERIALIZER

PERIPHERAL

1

7

1

8

1

8

1

S

DEV ID

W

A

DATA 0

A

DATA N

A

P

2

UART-TO-I C CONVERSION OF READ PACKET (I2CMETHOD = 1)

SERIALIZER/DESERIALIZER

µC

11

DATA 0

11

DATA N

SYNC FRAME

DEVICE ID + RD

REGISTER ADDRESS NUMBER OF BYTES

ACK FRAME

SERIALIZER/DESERIALIZER

PERIPHERAL

1

7

1

8

1

8

1

S

DEV ID

R

A

DATA 0

A

DATA N

A

P

MASTER TO SLAVE

SLAVE TO MASTER

S: START

P: STOP A: ACKNOWLEDGE

2

Figure 26. Format Conversion Between GMSL UART and I C without Register Address (I2CMETHOD = 1)

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16-Bit GMSL Serializer with High-Immunity/

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where:

Spread Spectrum

Program the SS bits in the serializer to turn on spread

spectrum in the serializer (Table 9). If the deserializer

driven by the serializer has programmable spread

spectrum, do not enable spread for both at the same

time or their interaction cancels benefits. The deserializer

tracks the serializer’s spread and passes the spread to the

deserializer output. Some spread-spectrum amplitudes

can only be used at lower PCLKIN frequencies (Table

10). When the spread spectrum is turned on or off, the

serial link stops for several microseconds and then

restarts in order for the deserializer to lose and relock

to the new serial-data stream. Changing the spread-

spectrum amplitude does not cause a loss of lock.

f

= Modulation frequency

M

= PCLKIN frequency

PCLKIN

MOD = Modulation coefficient given in Table 11

SDIV = 6-bit SDIV setting, manually programmed by the μC

To program the SDIV setting, first look up the modulation

coefficient according to the desired bus-width and spread-

spectrum settings. Solve the above equation for SDIV using

the desired pixel clock and modulation frequencies. If the

calculated SDIV value is larger than the maximum allowed

SDIV value in Table 11, set SDIV to the maximum value.

Board Layout

Power-Supply Circuits and Bypassing

Manual Programming of the Spread-Spectrum

Divider

The serializer uses an AVDD and DVDD of 1.7V to 1.9V.

All inputs and outputs, except for the serial output, derive

power from an IOVDD of 1.7V to 3.6V that scales with

IOVDD. Proper voltage-supply bypassing is essential for

high-frequency circuit stability.

By default, autodetection of the PCLKIN operation range

guarantees a spread-spectrum modulation frequency

within 20kHz to 40kHz. Additionally, manual configuration

of the sawtooth divider (SDIV: 0x03,D[5:0]) allows the

user to set a modulation frequency (typically 20kHz)

according to the PCLKIN frequency.

Equation:

Relation of modulation rate to the PCLKIN frequency:

f

= f

/(MOD x SDIV)

M

PCLKIN

Table 9. Output Spread

SS

000

001

010

011

100

101

110

111

SPREAD (%)

POWER-UP DEFAULT (NO SPREAD SPECTRUM)

±0.5% SPREAD SPECTRUM

±1.5% SPREAD SPECTRUM

±2% SPREAD SPECTRUM

NO SPREAD SPECTRUM

±1% SPREAD SPECTRUM

±3% SPREAD SPECTRUM

±4% SPREAD SPECTRUM

Table 10. Spread Limitations

BWS = 0 MODE, PCLKIN

BWS = 1 MODE, PCLKIN

SERIAL LINK BIT RATE

(MBPS)

AVAILABLE SPREAD

RATES

FREQUENCY (MHz)

< 33.3 (DBL = 0)

< 66.6 (DBL = 1)

< 25 (DBL = 0)

< 1000

All rates available

< 50 (DBL = 1)

33.3 to 58 (DBL = 0)

66.6 to 116 (DBL = 1)

25 to 43.5 (DBL = 0)

50 to 87 (DBL = 1)

≥ 1000

1.5%, 1%, 0.5%

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16-Bit GMSL Serializer with High-Immunity/

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Table 11. Modulation Coefficients and

Maximum SDIV Settings

R

1.5kΩ

D

1MΩ

SPREAD-

SPECTRUM

SETTING (%)

MODULATION

COEFFICIENT

(DEC)

SDIV UPPER

LIMIT (DEC)

CHARGE-CURRENT- DISCHARGE

BWS

LIMIT RESISTOR

RESISTANCE

HIGH-

VOLTAGE

DC

DEVICE

UNDER

TEST

C

100pF

S

STORAGE

CAPACITOR

1

0.5

3

104

152

204

80

40

63

27

54

15

30

52

63

37

63

21

42

SOURCE

1

1.5

4

Figure 27. Human Body Model ESD Test Circuit

2

1

0.5

3

80

R

D

330Ω

112

152

0

1.5

4

CHARGE-CURRENT- DISCHARGE

LIMIT RESISTOR

RESISTANCE

HIGH-

VOLTAGE

DC

DEVICE

UNDER

TEST

2

C

150pF

S

STORAGE

CAPACITOR

SOURCE

High-Frequency Signals

Separate the LVCMOS logic signals and CML/coax

highspeed signals to prevent crosstalk. Use a four-layer

PCB with separate layers for power, ground, CML/coax,

and LVCMOS logic signals. Layout STP-PCB traces

close to each other for a 100Ω differential characteristic

impedance. The trace dimensions depend on the type of

trace used (microstrip or stripline).

Figure 28. IEC 61000-4-2 Contact Discharge ESD Test Circuit

R

D

2kΩ

CHARGE-CURRENT- DISCHARGE

Note: Two 50Ω PCB traces do not have 100Ω differential

impedance when brought close together; the impedance

goes down when the traces are brought closer. Use a 50Ω

trace for the single-ended output when driving coax. Route

the PCB traces for differential CML in parallel to maintain

the differential characteristic impedance. Avoid via arrays.

Keep PCB traces that make up a differential pair equal in

length to avoid skew within the differential pair.

LIMIT RESISTOR

RESISTANCE

HIGH-

VOLTAGE

DC

DEVICE

UNDER

TEST

C

330pF

S

STORAGE

CAPACITOR

SOURCE

Figure 29. ISO 10605 Contact Discharge ESD Test Circuit

ESD Protection

ESD tolerance is rated for Human Body Model, IEC

61000-4-2, and ISO 10605. The ISO 10605 and IEC

61000-4-2 standards specify ESD tolerance for electronic

systems. The serial outputs are rated for ISO 10605

ESD protection and IEC 61000-4-2 ESD protection. All

pins are tested for the Human Body Model. The Human

Body Model discharge components are CS = 100pF and

RD = 1.5kΩ (Figure 27). The IEC 61000-4-2 discharge

components are CS = 150pF and RD = 330Ω (Figure 28).

The ISO 10605 discharge components are CS = 330pF

and RD = 2kΩ (Figure 29).

Compatibility with Other GMSL Devices

The device is designed to pair with the MAX96705A–

MAX96711 family of devices, but interoperates with any

GMSL device. See Table 12 for operating limitations.

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16-Bit GMSL Serializer with High-Immunity/

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Multifunction Inputs

Device Conﬁguration and Component Selection

Internal Input Pulldowns

The control and configuration inputs (except three-level

inputs) include a pulldown resistor to GND; external

pulldown resistors are not needed.

The device has several inputs/outputs that serve multiple

functions. GPO/HIM functions as the GPO output, and as

a configuration pin. On power-up, or when reverting from

a power-down state, the pins act as the HIM input. After

latching the input state, the pin becomes the GPO output.

Connect a configuration input through a 30kΩ resistor to

IOVDD to set a high level. Leave the configuration input

open to set a low level.

Three-Level Conﬁguration Inputs

CONF1 and CONF0 are three-level inputs that control

the serial interface configuration and power-up defaults

(Table 13). Connect CONF1 or CONF0 with 6kΩ (max)

pullup to IOVDD to set a high level, a 6kΩ (max) pulldown

to GND to set a low level, or open to set a mid level. For

digital control, use three-state logic to drive the three-level

logic inputs. CONF pin values are latched at power-up or

resuming from power-down mode.

In addition, several multifunction pins are controlled

by the LCCEN input. When LCCEN = 1, the local

control channel (RX/SDA, TX/SCL) is active, and the

GPIO1/BWS and MS/HVEN pins behave as GPIO1 and

the MS input respectively. When LCCEN = 0, the local

control channel is disabled, and these pins operate as

their alternate function (DBL, BWS, HVEN inputs).

Table 12. Feature Compatibility

SERIALIZER FEATURE

GMSL DESERIALIZER

HSYNC/VSYNC Encoding

If feature not supported in the deserializer, turn oﬀ in the serializer.

2

I C to I C

If feature not supported in the deserializer, use UART to I C or UART to UART.

Packet Control Channel

CRC Error Detection

If feature not supported in the deserializer, use legacy control channel.

If feature not supported in the deserializer, turn oﬀ in the serializer.

If feature not supported in the deserializer, data is output as a single word at half the input

frequency. Use crossbar switch and double-mode alignment to correct input mapping.

Double Input

Coax

If feature not supported in the deserializer, connect unused serial input through 200nF

and 50Ω in series to AVDD, and set the reverse control-channel amplitude to 100mV.

2

I S Encoding

If supported in the deserializer, disable I S in the deserializer.

High-Bandwidth Mode

High-Immunity Mode

Low-Speed Mode

If feature not supported in the deserializer, turn oﬀ in the serializer.

If supported in the deserializer, set DRS to 0 in the deserializer.

Table 13. Three-Level Configuration Input Map

CXTP

ES

I2CSEL

(CONTROL-CHANNEL TYPE)

CONF1

CONF0

(OUT+/OUT- OUTPUT TYPE)

(PCLKIN LATCH EDGE)

LOW

MID

LOW

MID

1 (COAX)

0 (STP)

1 (FALLING)

0 (RISING)

1 (FALLING)

0 (RISING)

DO NOT USE

1 (I²C O I²C)

0 (UART TO I²C/UART)

1 (I²C TO I²C)

0 (UART TO I²C/UART)

1 (I²C TO I²C)

0 (UART TO I²C/UART)

1 (I²C TO I²C)

0 (UART TO I²C/UART)

HIGH

LOW

MID

HIGH

LOW

MID

0 (STP)

HIGH

0 (STP)

HIGH

DO NOT USE

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16-Bit GMSL Serializer with High-Immunity/

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Table 14. Suggested Connectors and Cables for GMSL

VENDOR

Rosenberger

Nissei

CONNECTOR

59S2AX-400A5-Y

D4S10A-40ML5-Z

GT11L-2S

CABLE

TYPE

Coax

STP

Dacar 302

Dacar 535-2

F-2WME AWG28

A-BW-Lxxxxx

STP

JAE

MX38-FF

STP

2

I C/UART Pullup Resistors

Cables and Connectors

2

The I C and UART open-drain lines require a pullup

resistor to provide a logic-high level. There are tradeoffs

between power dissipation and speed, and a compromise

may be required when choosing pullup resistor values.

Every device connected to the bus introduces some

capacitance even when the device is not in operation.

Interconnect for CML typically has a differential

impedance of 100Ω. Use cables and connectors that have

matched differential impedance to minimize impedance

discontinuities. Coax cables typically have a characteristic

impedance of 50Ω; contact the factory for 75Ω operation).

Table 14 lists the suggested cables and connectors used

in the GMSL link.

2

I C specifies 300ns rise times (30% to 70%) for fast

mode, which is defined for data rates up to 400kbps (see

the I C/UART Port Timing section in the AC Electrical

PRBS

2

The serializer includes a PRBS pattern generator that

works with bit-error verification in the deserializer. To

run the PRBS test, set PRBSEN = 1 (0x04, D5) in the

deserializer, then in the serializer. To exit the PRBS

test, set PRBSEN = 0 (0x04, D5) in the serializer. The

deserializer automatically ends PRBS checking and sets

the PRBS_OK bit high. During PRBS mode, the forward

control channel is not available except to exit PRBS

mode if autoacknowledge is enabled in the deserializer;

otherwise, the remote control channel is not available at

all.

Characteristics table for details). To meet the fast-mode

rise-time requirement, choose the pullup resistors so

that rise time t = 0.85 x R

x C

< 300ns.

R

PULLUP

BUS

The waveforms are not recognized if the transition time

2

becomes too slow. GMSL supports I C/UART rates up

2

to 1Mbps (UART-to-I C mode) and 400kbps (I C-to-I C

mode).

AC-Coupling Capacitors

Voltage droop and the digital-sum variation (DSV) of

transmitted symbols cause signal transitions to start

from different voltage levels. Because the transition

time is fixed, starting the signal transition from different

voltage levels causes timing jitter. The time constant for

an AC-coupled link needs to be chosen to reduce droop

and jitter to an acceptable level. The RC network for

an AC-coupled link consists of the CML/coax receiver

To run the PRBS with a 3Gbps SerDes, or when HIBW

= 1, first set the PRBS_TYPE bit = 0 in the MAX967XX.

Then set PRBSEN = 1 (0x04, D5) in the serializer

and then in the deserializer. To exit the PRBS test, set

PRBSEN = 0 (0x04, D5) in the deserializer, then in the

serializer. PRBS_TYPE = 0 does not support DBL = 1.

termination resistor (R ), the CML/coax-driver

TR

During PRBS test, ERRB function changes to reflect

PRBS errors only. ERRB goes low when any PRBS errors

occur. ERRB goes high when the PRBS error counter is

reset when PRBS_ERR is read. Normal ERRB function

resumes when exiting the PRBS test.

termination resistor (R ), and the series AC-coupling

TD

capacitors (C). The RC time constant for four equal-value

series capacitors is (C x (R

+ R ))/4. R

and R

TD TR

TD

TR

are required to match the transmission-line impedance

(usually 100Ω differential, 50Ω single-ended). This

leaves the capacitor selection to change the system time

constant. Use 0.22μF or larger high-frequency, surface-

mount ceramic capacitors with sufficient voltage rating

to withstand a short to battery, to pass the lower speed

reverse control-channel signal. Use capacitors with a case

size less than 3.2mm x 1.6mm to have lower-parasitic

effects to the high-speed signal.

GPI/GPO

GPO on the serializer follows GPI transitions on the

deserializer. By default, the GPI-to-GPO delay is 0.35ms

(max). Keep the time between GPI transitions to a

minimum 0.35ms. GPI_IN the deserializer stores the GPI

input state. GPO is low after power-up. The μC can set

GPO by writing to the SET_GPO register bit. Do not send

a logic-low value on the deserializer RX/SDA input (UART

mode) longer than 100μs in either base or bypass mode

to ensure proper GPO/GPI functionality.

Maxim Integrated

│ 80

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Fast Detection of Loss-of-Lock

Entering/Exiting Sleep Mode

A measure of link quality is the recovery time from loss-

of-synchronization. The host can be quickly notified of

loss-of-lock by connecting the deserializer’s LOCK output

to the GPI input (when PKTCC_EN = 0). If other sources

use the GPI input, such as a touch-screen controller,

the μC can implement a routine to distinguish between

interrupts from loss-of-sync and normal interrupts.

Reverse control-channel communication does not require

an active forward link to operate and accurately tracks the

LOCK status of the GMSL link. LOCK asserts for video

link only and not for the configuration link.

The procedure for entering and exiting sleep mode

depends on the location of the microcontroller, and the

type of control-channel interface used. If wake up from a

remote (deserializer) side microcontroller is not needed or

desired, set the DIS_RWAKE bit = 1 to shut down remote

wake-up for further power savings.

Legacy Control Channel:

To enter sleep mode, set SLEEP = 1. The device sleeps

after 8ms. To wake up the device, send an arbitrary

control-channel command to the serializer (the serializer

does not send an acknowledge), wait for 5ms for the chip

to power up and then set SLEEP = 0 to make the wake-

up permanent.

Providing a Frame Sync (Camera Applications)

The GPI and GPO provide a simple solution for camera

applications that require a frame-sync signal from the

ECU (e.g., surround-view systems). Connect the ECU

frame-sync signal to the GPI input and connect the GPO

output to the camera frame-sync input. GPI/GPO have a

typical delay of 275μs in legacy mode and 21μs in packet

mode (with 5-bit CRC). Skew between multiple GPI/ GPO

channels is 115μs (max) in legacy mode and 21μs (max)

in packet mode. If a lower skew signal is required in

legacy mode, connect the camera’s frame-sync input to

Packet-Based Control Channel:

● When μC is on the deserializer side, set SLEEP = 1 in

serializer. Next set REVCCEN = 0 in the deserializer to

stop reverse-control transmission to the serializer. The

device sleeps after 8ms.

To wake up the serializer, first set REVCCEN = 1, wait

8ms for the device to wake up and then set SLEEP = 0

to exit sleep mode permanently.

2

● When μC is on the serializer side, first set SLEEP =

1 in the deserializer. If the deserializer must remain

awake, switch to legacy control-channel mode. Next,

set SLEEP = 1 in the serializer. The device sleeps after

8ms.

one of the serializer’s GPIOs and use an I C broadcast-

write command to change the GPIO output state. This

has a maximum skew of 1.5μs, independent from the

2

used I C bit rate. In packet-based control-channel mode,

set GPI_COMP_EN = 1 in both the serializer and

deserializer to turn on GPI/GPO compensation. This

reduces the device-to-device skew to 0.35μs.

To wake up the device, send an arbitrary control-

channel command to the serializer (the serializer does

not send an acknowledge). Wait for 5ms for the chip to

power up and then set SLEEP = 0 to make the wake-

up permanent. The deserializer wakes up and clears its

SLEEP bit when serialization is enabled and it locks to

the serializer.

Maxim Integrated

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Typical Application Circuits

PCLKOUT

DOUT[11:0]

DOUT12/HS

PCLK

DIN[11:0]

PCLK

DIN[11:0]

PCLKIN

DIN[11:0]

HS

VS

DIN14/HS

DIN15/VS

HS

VS

DOUT13/VS

MAX96705A

MAX96706

GPU

CAMERA

45.3kΩ

4.99kΩ

SDA

SCL

RX/SDA

49.9Ω

LMN0

TX/SCL/DBL

RX/SDA

TX/SCL

SDA

SCL

OUT-

I²C

OUT+

IN+

IN-

GPI

FSYNC

49.9kΩ

LOCK

LCCEN

49.9Ω

CONF0

CONF1

ERRB

LFLTB

ERR

LFLT

MS/HVEN

I2CSEL = 1, CX/TP = 1

ECU

NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.

CAMERA APPLICATION

Ordering Information

PIN-

PACKAGE

PART NUMBER

TEMP RANGE

MAX96705AGTJ+**

MAX96705AGTJ+T**

MAX96705AGTJ/V+

MAX96705AGTJ/V+T

-40°C to +115°C 32 TQFN-EP*

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

/V denotes an automotive qualified product.

*EP = Exposed pad.

**Future product—contact factory for availability.

Maxim Integrated

│ 82

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MAX96705A

16-Bit GMSL Serializer with High-Immunity/

Bandwidth Mode and Coax/STP Cable Drive

Revision History

REVISION REVISION

PAGES

DESCRIPTION

CHANGED

NUMBER

DATE

0

6/17

Initial release

—

For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and speciﬁcations without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

©

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

2017 Maxim Integrated Products, Inc.

│ 83


型号：	MAX96705AGTJ/V+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	16-Bit GMSL Serializer with High-Immunity/ Bandwidth Mode and Coax/STP Cable Drive
文件：	总83页 (文件大小：1574K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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