MAX9674 [MAXIM]
10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs;型号: | MAX9674 |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | 10-Bit, Programmable Gamma Reference Systems with MTP for TFT LCDs CD |
文件: | 总24页 (文件大小:786K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-4718; Rev 4; 2/11
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
General Description
Features
The MAX9672/MAX9673/MAX9674 output 12/14/16 volt-
age references for gamma correction in TFT LCDs and
one voltage reference for VCOM. Each gamma refer-
ence voltage has its own 10-bit DAC and buffer to
ensure a stable voltage. The VCOM reference voltage
has its own 10-bit DAC and an amplifier to ensure a sta-
ble voltage when critical levels and patterns are dis-
played. The MAX9672/MAX9673/MAX9674 feature
integrated multiple-time programmable (MTP) memory to
store gamma and VCOM values on the chip, eliminating
the need for external EEPROM. The MAX9672/
MAX9673/MAX9674 support up to 300 write operations
to the on-chip nonvolatile memory.
o DAC Reference Input
o 12/14/16-Channel Gamma Correction, 10-Bit
Resolution
o VCOM Driver
o Integrated MTP Memory
o Programmable VCOM Limits
o 200mA Peak Current on Gamma Channels
o 600mA Peak Current on VCOM Channel
Ordering Information
GAMMA
CHANNELS
PART
PIN-PACKAGE
The gamma outputs can drive 200mA peak transient
current and settle within 1µs. The VCOM output can
provide 600mA peak transient current and also settles
within 1µs. The analog supply voltage range extends
from 9V to 20V, and the digital supply voltage range
extends from 2.7V to 3.6V.
*
MAX9672ETI+
MAX9673ETI+
MAX9674ETI+
12
14
16
28 TQFN-EP
*
28 TQFN-EP
*
28 TQFN-EP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Note: All devices are specified over the -40°C to +85°C temper-
ature range.
Gamma values and the VCOM value are programmed
into registers through the I2C interface.
Functional Diagram
Applications
REF
AVDD
TFT LCDs
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10-BIT
DAC
GMA1
10-BIT
DAC
Pin Configuration
GMA2
10-BIT
DAC
GMA3
10-BIT
DAC
TOP VIEW
GMA4
10-BIT
DAC
GMA5
21 20 19 18 17 16 15
10-BIT
DAC
GMA6
10-BIT
DAC
14
13
GMA9 22
GMA3
GMA2
GMA7
10-BIT
DAC
GMA10 23
GMA8
2
MTP
MEMORY
DAC
REGISTERS
10-BIT
DAC
I
C
12 GMA1
GMA9
24
25
26
27
28
GMA11
GMA12
REGISTERS
MAX9672
MAX9673
MAX9674
10-BIT
DAC
GND
GMA10
GMA11
GMA12
GMA13*
GMA14*
GMA15**
11
10
9
10-BIT
DAC
GMA13*
GMA14*
GMA15**
AVDD
10-BIT
DAC
AVDD_AMP
VCOM_FB
†
EP
6
+
10-BIT
DAC
8
10-BIT
DAC
1
2
3
4
5
7
10-BIT
DAC
10-BIT
DAC
GMA16**
AVDD_AMP
VCOM
10-BIT
DAC
THIN QFN
(5mm × 5mm)
AGND_AMP
VCOM_FB
DVDD
SDA
SCL
A0
MAX9672
MAX9673
MAX9674
2
I
C
†
EP = EXPOSED PAD, CONNECT EP TO GROUND PLANE.
*N.C. FOR THE MAX9672
INTERFACE
GND
**N.C. FOR THE MAX9672 AND THE MAX9673
*NOT AVAILABLE FOR THE MAX9672
**NOT AVAILABLE FOR THE MAX9672 AND THE MAX9673
GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
SDA, SCL.......................................................................... 20mA
AVDD, REF to GND ............................................-0.3V to +22V
AVDD_AMP to AGND_AMP................................-0.3V to +22V
AVDD to AVDD_AMP.........................................-0.3V to +0.3V
DVDD to GND.......................................................-0.3V to +4V
AGND_AMP to GND..........................................-0.1V to +0.1V
Outputs
GMA1–GMA16................................................................ 200mA
VCOM ............................................................................. 600mA
Continuous Power Dissipation (T = +70°C)
A
28-Pin TQFN-EP (derate 28.6mW/°C
above +70°C) ........................................................2285.7mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ...................................... +260°C
GMA1–GMA16 ...................................-0.3V to (V
+ 0.3V)
+ 0.3V)
AVDD
VCOM.........................................-0.3V to (V
AVDD_AMP
Inputs
SDA, SCL..............................................................-0.3V to +6V
VCOM_FB...................................-0.3V to (V + 0.3V)
AVDD_AMP
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 18V, V
= V
= 18V, V
= 3.3V, V
= V
= 0, VCOM = VCOM_FB, no load, T = T
to T
,
MAX
AVDD
AVDD_AMP
REF
DVDD
GND
AGND_AMP
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
,
AVDD
Analog Supply Voltage Range
Guaranteed by total output error
9
20
20
V
V
V
V
AVDD_AMP
Analog Supply Voltage Range for
Programming MTP
15
AVDD_MTP
23/MAX9674
Digital Supply Voltage Range
Analog Quiescent Current
VCOM Quiescent Current
V
2.7
3.6
35
V
DVDD
I
20
2.7
mA
mA
AVDD
I
5.6
AVDD_AMP
During a register mode load event
No SCL or SDA transitions
400
260
+160
15
Digital Quiescent Current
I
µA
DVDD
600
2.6
Thermal Shutdown
°C
°C
Thermal-Shutdown Hysteresis
DVDD undervoltage lockout voltage
threshold
Undervoltage Lockout Threshold
UVLO
2.3
V
REF Input Resistance
VCOM OUTPUT (VCOM)
Resolution
384
kΩ
RES
INL
10
Bits
LSB
LSB
Integral Nonlinearity Error
Differential Nonlinearity Error
0.125
0.125
1
1
DNL
Code = 512, V
= +25°C
= 9V and 20V, T
A
AVDD_AMP
Total Output Error
V
-40
+40
mV
ERR
Total Output-Error Drift
Output-Voltage Low
∆V
Code = 512
15
µV/°C
V
ERR
V
T
A
= +25°C, sinking 100mA
0.4
0.85
OUT
2
_______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
ELECTRICAL CHARACTERISTICS (continued)
(V
= 18V, V
= V
= 18V, V
= 3.3V, V
= V
= 0, VCOM = VCOM_FB, no load, T = T
to T
,
MAX
AVDD
AVDD_AMP
REF
DVDD
GND
AGND_AMP
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
Output-Voltage High
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
AVDD_AMP AVDD_AMP
- 1.1
V
T
A
= +25°C, sourcing 100mA
V
OUT
- 0.6
To AVDD_AMP, f = 60kHz, REF shorted to
40
V
Power-Supply Rejection Ratio
PSRR
LR
dB
AVDD_AMP
9V ≤ V
≤ 20V
60
90
0.1
80
AVDD_AMP
Output Load Regulation
Continuous Output Current
Short-Circuit Current
Transient -80mA to +80mA, code = 512
Code = 512 (Note 2)
mV/mA
mA
I
O
9V ≤ V
≤ 20V
600
mA
AVDD_AMP
Swing 4V
R = 10kΩ, C = 50pF (Note 3)
L
at VCOM, 10% to 90%,
L
P-P
Slew Rate
SR
100
V/µs
From SCL rising edge for ACK bit after
programming VCOM to 50% voltage
change at output
Program to Output Delay
t
D
0.8
µs
Bandwidth
BW
R = 10kΩ, C = 50pF (Note 3)
60
MHz
µV
S
L
Noise
e
N
RMS noise voltage (10MHz BW)
375
DAC OUTPUTS (GMA1–GMA16)
Resolution
RES
INL
Guaranteed monotonic
10
Bits
LSB
LSB
Integral Nonlinearity Error
Differential Nonlinearity Error
0.125
0.125
1
1
DNL
Code = 512, V
= 9V and 20V,
AVDD
Total Output Error
Output-Voltage Low
Output-Voltage High
V
-40
+40
0.28
mV
V
ERR
OUT
OUT
T
A
= +25°C
V
V
T
A
= +25°C, sinking 10mA
0.15
V
V
AVDD
- 0.38
AVDD
- 0.25
T
A
= +25°C, sourcing 10mA
V
To AVDD, f = 60kHz, REF shorted to
AVDD
40
Power-Supply Rejection Ratio
PSRR
LR
dB
9V ≤ V
≤ 20V
60
90
0.5
200
84
AVDD
Load Regulation
-12mA to +12mA
mV/mA
mA
Short-Circuit Current
Output Impedance
I
Outputs to AVDD or GND
SC
Z
Output resistance when output is disabled
kΩ
O
Swing 5V
measurement on output
at input, 10% to 90%
P-P
Slew Rate
SR
22
V/µs
From SCL rising edge for ACK bit after
programming gamma to 50% voltage
change at output
Program to Output Delay
t
0.8
µs
D
RMS noise voltage at any output (10MHz
BW)
Noise
e
375
80
µV
dB
N
Channel-to-Channel Isolation
CXTLK
f = 5MHz, all channels to all channels
_______________________________________________________________________________________
3
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 18V, V
= V
= 18V, V
= 3.3V, V
= V
= 0, VCOM = VCOM_FB, no load, T = T
to T
,
MAX
AVDD
AVDD_AMP
REF
DVDD
GND
AGND_AMP
A
MIN
unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (SDA, SCL)
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
V
DVDD
0.3 x
V
IL
V
DVDD
Input Leakage Current
Input Capacitance
I
, I
V
V
= 0V or V
-1
+0.01
5
+1
µA
pF
µA
V
IH IL
IN
DVDD
Power-Down Input Current
I
= 0V, V = 2V
-10
+10
0.4
IN
DVDD
IN
SDA Output Low Voltage
V
I
= 6mA
OL
SINK
2
I C TIMING CHARACTERISTICS (Figure 1)
Serial-Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
Hold Time (REPEATED) START
Condition
t
t
0.6
µs
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a REPEATED
START Condition
0.6
µs
SU,STA
23/MAX9674
Data Hold Time
Data Setup Time
t
0
900
ns
ns
HD,DAT
t
100
SU,DAT
SDA and SCL Receiving Rise
Time
20 +
t
(Note 4)
(Note 4)
(Note 4)
300
300
250
ns
ns
ns
R
0.1C
B
SDA and SCL Receiving Fall
Time
20 +
0.1C
t
F
B
SDA Transmitting Fall
Time
20 +
t
F,TX
0.1C
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
µs
pF
ns
SU,STO
C
400
50
B
Pulse Width of Suppressed Spike
t
0
SP
Note 1: All devices are 100% production tested at T = +25°C. All temperature limits are guaranteed by design.
A
Note 2: Thermal pad attached to multilayered board. Exceeding this limit may cause the thermal shutdown to trip.
Note 3: Measured with the VCOM amplifier configured as an inverting unity-gain amplifier (R = R = 1kΩ).
S
F
Note 4: C is in pF.
B
4
_______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
Typical Operating Characteristics
(V
= V
= V
= 18V, V
= 3.3V, V
= V = 0, no load, unless otherwise noted. Typical values are at
AGND_AMP
AVDD
AVDD_AMP
REF
DVDD
GND
T
A
= +25°C.)
OUTPUT OFFSET-VOLTAGE
DISTRIBUTION
GAMMA LOAD REGULATION
20
30
25
20
15
10
5
15
10
5
0
-5
-10
-15
-20
0
-40 -30 -20 -10
0
10 20 30 40
-20 -15 -10 -5
0
5
10 15 20
OUTPUT OFFSET (mV)
LOAD CURRENT (mA)
DNL
GAMMA
VCOM LOAD REGULATION
0.25
0.20
0.15
0.10
0.05
0
60
40
20
0
-0.05
-0.10
-0.15
-0.20
-0.25
-20
-40
-60
-150 -100
-50
0
50
100
150
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
LOAD CURRENT (mA)
DNL
VCOM
GAMMA
INL
0.25
0.20
0.15
0.10
0.05
0
0.25
0.20
0.15
0.10
0.05
0
V
= 10V
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
-0.25
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
_______________________________________________________________________________________
5
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Typical Operating Characteristics (continued)
(V
= V
= V
= 18V, V
= 3.3V, V
= V
= 0, no load, unless otherwise noted. Typical values are at
AVDD
AVDD_AMP
REF
DVDD
GND
AGND_AMP
T
A
= +25°C.)
VCOM
INL
GAMMA
INL
0.25
0.4
0.3
0.2
0.1
0
V
= 10V
0.20
0.15
0.10
0.05
0
REF
-0.05
-0.10
-0.15
-0.20
-0.25
-0.1
-0.2
-0.3
-0.4
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
VCOM
INL
GAMMA
DNL
0.25
0.20
0.15
0.10
0.05
0
0.12
0.08
0.04
0
23/MAX9674
-0.05
-0.10
-0.15
-0.20
-0.25
-0.04
-0.08
-0.12
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
VCOM
DNL
0.20
V
= 10V
REF
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
0
128 256 384 512 640 768 896 1024
CODE (UNITS)
6
_______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
Typical Operating Characteristics (continued)
(V
= V
= V
= 18V, V
= 3.3V, V
= V = 0, no load, unless otherwise noted. Typical values are at
AGND_AMP
AVDD
AVDD_AMP
REF
DVDD
GND
T
A
= +25°C.)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY, GAMMA OUTPUTS
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY, VCOM OUTPUT
0
-10
-20
-30
-40
-50
-60
-70
-80
0
V
= 200mV
P-P
V
= 200mV
P-P
RIPPLE
RIPPLE
-10
-20
-30
-40
-50
-60
-70
-80
CODE = 512
CODE = 512
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
REFERENCE REJECTION RATIO
vs. FREQUENCY, GAMMA OUTPUTS
REFERENCE REJECTION RATIO
vs. FREQUENCY, VCOM OUTPUT
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
V
= 200mV
V = 200mV
RIPPLE P-P
RIPPLE
P-P
CODE = 512
CODE = 512
10k
100k
1M
10M
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
VCOM PULSE RESPONSE
GAMMA PULSE RESPONSE
R
C
= 10Ω
LOAD
R
C
= 10Ω
ISO
ISO
= 68nF
= 10nF
LOAD
I
I
OUT
OUT
250mA/div
50mA/div
-2.5V TO +2.5V
-2.5V TO +2.5V
R
ISO
R
ISO
GAMMA
DAC
VCOM
DAC
C
LOAD
C
LOAD
V
V
OUT
OUT
250mV/div
1V/div
TIME (2µs/div)
TIME (2µs/div)
_______________________________________________________________________________________
7
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Pin Description
PIN
MAX9673
1, 28
NAME
FUNCTION
MAX9672
MAX9674
1, 26, 27, 28
—
N.C.
GMA16
SCL
No Connection. Not internally connected.
Gamma DAC Analog Output 16
—
2
3
4
5
6
7
8
—
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
I C-Compatible Serial-Clock Input
2
SDA
I C-Compatible Serial-Data Input/Output
2
A0
I C-Compatible Device Address Bit 0
DVDD
Digital Power Supply. Bypass DVDD with a 0.1µF capacitor to GND.
AGND_AMP Ground for VCOM Amplifier
VCOM
VCOM Output
VCOM_FB
Feedback for VCOM Amplifier
Power Supply for VCOM Amplifier. Bypass AVDD_AMP with a 0.1µF
capacitor to AGND_AMP.
9
9
9
AVDD_AMP
10, 21
11
12
13
14
15
16
17
18
19
20
22
23
24
25
—
10, 21
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
—
10, 21
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
AVDD
GND
Analog Power Supply. Bypass AVDD with a 0.1µF capacitor to GND.
Analog Ground
GMA1
GMA2
GMA3
GMA4
GMA5
GMA6
GMA7
GMA8
REF
Gamma DAC Analog Output 1
Gamma DAC Analog Output 2
Gamma DAC Analog Output 3
Gamma DAC Analog Output 4
Gamma DAC Analog Output 5
Gamma DAC Analog Output 6
Gamma DAC Analog Output 7
Gamma DAC Analog Output 8
DAC Reference Input
23/MAX9674
GMA9
GMA10
GMA11
GMA12
GMA13
GMA14
GMA15
Gamma DAC Analog Output 9
Gamma DAC Analog Output 10
Gamma DAC Analog Output 11
Gamma DAC Analog Output 12
Gamma DAC Analog Output 13
Gamma DAC Analog Output 14
Gamma DAC Analog Output 15
—
—
Exposed Pad. EP is internally connected to the analog ground and
digital ground. EP must be connected to the system’s ground.
—
—
—
EP
MTP memory to store gamma and VCOM values on the
chip, eliminating the need for external EEPROM. The
MAX9672/MAX9673/MAX9674 support up to 300 write
operations to the on-chip nonvolatile memory.
Detailed Description
The MAX9672/MAX9673/MAX9674 feature 13/15/17
total programmable reference voltage channels. Each
channel has a 10-bit DAC to create the reference volt-
age. One channel has an amplifier that follows the DAC
while all other channels have a buffer after the DAC.
The MAX9672/MAX9673/MAX9674 feature integrated
The MAX9672/MAX9673/MAX9674 can provide the
gamma, VCOM, and possibly level-shifter reference
voltages for an LCD panel that can potentially replace a
discrete digital variable resistor (DVR), VCOM amplifier,
8
_______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
gamma buffers, high-voltage linear regulator, and resis-
The source drivers can kick back a great deal of cur-
rent to the buffer outputs during a horizontal line
change or a polarity switch. The DAC output buffers
can source/sink 200mA of peak current to reduce the
recovery time of the output voltages when critical levels
and patterns are displayed.
tor strings. The high-voltage linear regulator can be
eliminated because the DAC contains a lowpass filter
that reduces horizontal line frequency noise by 50dB.
Power sequencing is well controlled since a single chip
generates all the various reference voltages needed for
the LCD panel.
VCOM Amplifier
The operational amplifier attached to the VCOM DAC
holds the VCOM voltage stable while providing the abil-
ity to source and sink 600mA into the backplane of a
TFT LCD panel. The operational amplifier can directly
drive the capacitive load of the TFT LCD backplane
without the need for a series resistor in most cases. The
VCOM amplifier has current limiting on its output to pro-
tect its bond wires.
Each part has an I2C interface for programming both
the MTP memory and the I2C registers.
With the MTP memory and the I2C interface, the
MAX9672/MAX9673/MAX9674 enable automatic
gamma and automatic flicker calibration on a panel-by-
panel basis on the production line. Contact your Maxim
representative for more details.
10-Bit DACs
The voltage at REF sets the full-scale output of the
DACs. Determine the output voltage using the following
equation:
If the application requires more than 600mA, buffer the
output of the VCOM amplifier with a MAX9650, a VCOM
power amplifier. The MAX9650 can source or sink 1A of
current.
V
OUT
= (V
x CODE)/2N
REF
Thermal Shutdown
The MAX9672/MAX9673/MAX9674 feature thermal-
shutdown protection with temperature hysteresis. When
the die temperature reaches +165°C, all of the gamma
outputs are disabled. When the die cools down by
15°C, the outputs are enabled again.
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX9672/MAX9673/MAX9674, N = 10 and CODE
ranges from 0 to 1023.
The DAC can never output REF because the maximum
value of CODE is always 1 least significant bit (LSB)
I2C Serial Interface
The MAX9672/MAX9673/MAX9674 feature an I2C/
SMBus™-compatible, 2-wire serial interface consisting of
a serial-data line (SDA) and a serial-clock line (SCL).
SDA and SCL facilitate communication between the
MAX9672/MAX9673/MAX9674 and the master at clock
rates up to 400kHz. Figure 1 shows the 2-wire interface
timing diagram. The master generates SCL and initiates
data transfer on the bus. A master device writes data to
the MAX9672/MAX9673/MAX9674 by transmitting the
less than the reference. For example, if V
CODE = 1023, then the output voltage is:
= 16V and
REF
V
OUT
= (16V x 1023)/210
= 15.98438V
Gamma Buffers
The gamma buffers are guaranteed to source or sink
10mA of DC current within 200mV of the supplies.
SDA
t
BUF
t
t
SU,STA
SU,DAT
t
t
SP
HD,STA
t
t
SU,STO
t
HD,DAT
LOW
SCL
t
HIGH
t
HD,STA
t
t
F
R
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
START
CONDITION
Figure 1. I2C Serial-Interface Timing Diagram
SMBus is a trademark of Intel Corp.
_______________________________________________________________________________________
9
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
proper slave address followed by the register address
and then the data word. Each transmit sequence is
Table 1. Slave Address
A0
READ ADDRESS
WRITE ADDRESS
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each byte is serially trans-
mitted to the MAX9672/MAX9673/MAX9674 as 8 bits and
is followed by an acknowledge clock pulse. A master
reading data from the MAX9672/MAX9673/MAX9674
transmit the proper slave address followed by a series of
nine SCL pulses. The MAX9672/MAX9673/MAX9674
transmit data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater
than 500Ω, is required on the SDA bus. SCL operates as
only an input. A pullup resistor, typically greater than
500Ω, is required on SCL if there are multiple masters on
the bus, or if the master in a single-master system has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX9672/MAX9673/MAX9674 from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
GND
DVDD
E9h
EBh
E8h
EAh
S
Sr
P
SCL
SDA
Figure 2. START, STOP, and REPEATED START Conditions
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
SDA
ACKNOWLEDGE
23/MAX9674
Figure 3. Acknowledge
Slave Address
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 2). A START
condition from the master signals the beginning of a
transmission to the MAX9672/MAX9673/MAX9674. The
master terminates transmission, and frees the bus, by
issuing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
The slave address is defined as the 7 most significant
bits (MSBs) followed by the read/write (R/W) bit. Set the
R/W bit to 1 to configure the MAX9672/MAX9673/
MAX9674 to read mode. Set the R/W bit to 0 to config-
ure the MAX9672/MAX9673/MAX9674 to write mode.
The address is the first byte of information sent to the
MAX9672/MAX9673/MAX9674 after the START condi-
tion. The MAX9672/MAX9673/MAX9674 slave address
is configured with A0. Table 1 shows the possible
addresses for the MAX9672/MAX9673/MAX9674.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9672/MAX9673/MAX9674 use to handshake
receipt of each byte of data when in write mode (see
Figure 3). The MAX9672/MAX9673/MAX9674 pull down
SDA during the entire master-generated ninth clock
pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if
Early STOP Conditions
The MAX9672/MAX9673/MAX9674 use a STOP condi-
tion at any point during data transmission except if the
STOP condition occurs in the same high pulse as a
START condition. For proper operation, do not send a
STOP condition during the same SCL high pulse as the
START condition.
10 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
ACKNOWLEDGE FROM
ACKNOWLEDGE FROM
MAX9672/MAX9673/MAX9674
MAX9672/MAX9673/MAX9674
W1 W0
X
X
X
X
D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE 2
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
S
SLAVE ADDRESS
0
A
0
0
REGISTER ADDRESS
A
DATA BYTE 1
A
A
P
1 WORD
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
R/W
M1 M0
Figure 4. Writing a Word of Data to the MAX9672/MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
W1 W0
X
X
X
X
D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM
ACKNOWLEDGE FROM
MAX9672/MAX9673/MAX9674
MAX9672/MAX9673/MAX9674
S
SLAVE ADDRESS
0
A
0
0
REGISTER ADDRESS
A
DATA BYTE 1
A
DATA BYTE 2
A
1 WORD
R/W
M1 M0
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9672/
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
MAX9673/MAX9674
W1 W0
X
X
X
X
D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE n-1
A
DATA BYTE n
A
P
1 WORD
Figure 5. Writing n Bytes of Data to the MAX9672/MAX9673/MAX9674
a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master may retry communication. The master
pulls down SDA during the ninth clock cycle to
acknowledge receipt of data when the MAX9672/
MAX9673/MAX9674 are in read mode. An acknowledge
is sent by the master after each read byte to allow data
transfer to continue. A not acknowledge is sent when
the master reads the final byte of data from the
MAX9672/MAX9673/MAX9674, followed by a STOP
condition.
The slave address with the R/W bit set to 0 indicates that
the master intends to write data to the MAX9672/
MAX9673/MAX9674. The MAX9672/MAX9673/MAX9674
acknowledge receipt of the address byte during the
master-generated ninth SCL pulse.
The second byte transmitted from the master config-
ures the MAX9672/MAX9673/MAX9674’s internal regis-
ter address pointer. The MAX9672/MAX9673/
MAX9674’s internal address pointer consists of the 6
LSBs of the second byte. The 2 MSBs of the second
byte (M1 and M0) are set to 00b when writing to the
internal registers. See the Memory section for more
details. The pointer tells the MAX9672/MAX9673/
MAX9674 where to write the next byte of data. An
acknowledge pulse is sent by the MAX9672/
MAX9673/MAX9674 upon receipt of the address point-
er data.
Write Data Format
A write to the MAX9672/MAX9673/MAX9674 consists of
transmitting a START condition, the slave address with
the R/W bit set to 0, one data byte of data to configure
the internal register address pointer, one word (two
bytes) of data or more, and a STOP condition. Figure 4
illustrates the proper frame format for writing one word
of data to the MAX9672/MAX9673/MAX9674. Figure 5
illustrates the frame format for writing n-bytes of data to
the MAX9672/MAX9673/MAX9674.
The third and fourth bytes sent to the MAX9672/
MAX9673/MAX9674 contain the data that is written to the
chosen register and which type of register it writes to,
volatile (DAC) or nonvolatile memory (MTP). See the
Registers section for more details. An acknowledge pulse
______________________________________________________________________________________ 11
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Table 2. Register Map
MTP FACTORY
REGISTER
ADDRESS
REGISTER
NAME
REGISTER
DESCRIPTION
READ/
WRITE
INTIALIZATION VALUE
MAX9672
MAX9673
0x3BA
0x376
0x332
0x2EE
0x2AA
0x265
0x221
0x1DD
0x199
0x155
0x110
0x0CC
0x088
0x044
—
MAX9674
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
GMA1
GMA2
Gamma 1
Gamma 2
Gamma 3
Gamma 4
Gamma 5
Gamma 6
Gamma 7
Gamma 8
Gamma 9
Gamma 10
Gamma 11
Gamma 12
Gamma 13
Gamma 14
Gamma 15
Gamma 16
—
0x3B0
0x361
0x312
0x2C4
0x275
0x226
0x1D8
0x189
0x13A
0x0EC
0x09D
0x04E
—
0x3C2
0x386
0x34A
0x30E
0x2D2
0x295
0x259
0x21D
0x1E1
0x1A5
0x169
0x12C
0X0F0
0x0B4
0x078
0x03C
—
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
Read and write
—
GMA3
GMA4
GMA5
GMA6
GMA7
GMA8
GMA9
GMA10
GMA11
GMA12
GMA13
GMA14
GMA15
GMA16
Reserved
Reserved
VCOM
—
—
—
—
—
—
—
—
—
—
—
Common voltage
—
0x193
—
0x193
—
0x193
—
Read and write
—
23/MAX9674
Reserved
Reserved
Reserved
Reserved
Reserved
VCOMMIN
VCOMMAX
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Minimum VCOM value
Maximum VCOM value
0x10D
0x21A
0x10D
0x21A
0x10D
0x21A
Read and write
Read and write
Reserved,
DO NOT WRITE
0x1D
0x1E
—
—
—
—
—
—
—
—
—
—
Reserved,
DO NOT WRITE
from the MAX9672/MAX9673/MAX9674 signals receipt of
each data byte. The address pointer autoincrements to
the next register address after receiving every other data
byte. This autoincrement feature allows a master to write
to sequential register address locations within one contin-
uous frame. The master signals the end of transmission
by issuing a STOP condition.
If data is written into register address 0x1E, the address
pointer autoincrements to 0xFF and stays at 0xFF until
the master writes a new value into the register address
pointer.
Read Data Format
The master presets the address pointer by first sending
the MAX9672/MAX9673/MAX9674’s slave address with
the R/W bit set to 0 followed by the register address
12 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
Table 3. Register Description
REG
ADDR
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
REG
B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
GMA1
GMA2
GMA3
GMA4
GMA5
GMA6
GMA7
GMA8
GMA9
GMA10
GMA11
GMA12
GMA13*
GMA14*
GMA15**
GMA16**
Reserved
Reserved
VCOM
Reserved
Reserved
Reserved
Reserved
Reserved
VCOMMIN
VCOMMAX
Reserved
DO NOT
WRITE
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
W1
—
—
W1
—
—
—
—
—
W1
W1
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
W0
—
—
W0
—
—
—
—
—
W0
W0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
X
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
X
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
X
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
X
—
—
—
—
—
X
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
b9
—
—
b9
—
—
—
—
—
b9
b9
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
b8
—
—
b8
—
—
—
—
—
b8
b8
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
b7
—
—
b7
—
—
—
—
—
b7
b7
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
b6
—
—
b6
—
—
—
—
—
b6
b6
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
b5
—
—
b5
—
—
—
—
—
b5
b5
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
b4
—
—
b4
—
—
—
—
—
b4
b4
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
b3
—
—
b3
—
—
—
—
—
b3
b3
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
b2
—
—
b2
—
—
—
—
—
b2
b2
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
b1
—
—
b1
—
—
—
—
—
b1
b1
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
b0
—
—
b0
—
—
—
—
—
b0
b0
X
X
X
X
0x1D
0x1E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Reserved
DO NOT
WRITE
*Reserved for the MAX9672.
**Reserved for the MAX9672/MAX9673.
with M1 and M0 set to 00 after a START condition. The
MAX9672/MAX9673/MAX9674 acknowledge receipt of
its slave address and the register address by pulling
SDA low during the ninth SCL clock pulse. A REPEAT-
ED START condition is then sent followed by the slave
address with the R/W bit set to 1. The MAX9672/
MAX9673/MAX9674 transmit the contents of the speci-
fied register. Transmitted data is valid on the rising
edge of the master-generated serial clock (SCL). The
address pointer autoincrements after every other read
data byte. This autoincrement feature allows all regis-
ters to be read sequentially within one continuous
frame. A STOP condition can be issued after any num-
ber of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte
to be read is from the register address location set by
the previous transaction and not 0x00. Subsequent
reads autoincrement the address pointer until the next
STOP condition. Attempting to read from register
addresses higher than 0x1E results in repeated reads
from a dummy register containing all one data. The
master acknowledges receipt of each read byte during
the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
______________________________________________________________________________________ 13
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Table 4. Write Control Bits
W1
0
W0
0
ACTION
No update.
2
0
1
All MTP registers get updated when the current I C register has finished updating (end of B0).
2
1
0
All DAC registers get updated when the current I C register has finished updating (end of B0).
1
1
No update.
Table 5. Memory Write Bits
M1
0
M0
0
ACTION
None.
2
0
1
Only the addressed I C registers and DAC registers get set to the MTP values.
2
1
0
All I C registers and DAC registers get set to the MTP values.
1
1
None.
last byte. The final byte must be followed by a not
acknowledge from the master and then a STOP condi-
tion. Figures 6 and 7 illustrate the frame format for read-
ing data from the MAX9672/MAX9673/MAX9674.
full rail-to-rail programmable range for VCOM. Later,
users can define their own limits by programming
VCOMMIN and VCOMMAX registers and MTP.
VCOM register values are limited to the defined range.
This means if the VCOM register accidentally gets pro-
grammed with a value higher than VCOMMAX, it auto-
matically gets locked to the VCOMMAX value. The I2C
bus does acknowledge and receive the data sent on
the bus. However, internally the part recognizes that the
value is outside of the range and adjusts it accordingly.
The same scenario is true if the value programming
VCOM is below VCOMMIN.
Registers
Register Map
The MAX9672/MAX9673/MAX9674 have a bank of non-
volatile MTP memory and two banks of volatile memory
comprised of I2C registers and DAC registers. Each
memory location whether in nonvolatile or volatile mem-
ory holds a 10-bit word. Two bytes must be read or writ-
ten through the I2C interface for every 10-bit word.
23/MAX9674
Memory
The MAX9672/MAX9673/MAX9674 include both volatile
memory (I2C and DAC) and nonvolatile memory (MTP).
It is possible to write to each single DAC memory loca-
tion from an MTP memory location individually or to
write to all at once. This is done with memory write bits
(M1, M0) that are the 2 MSBs of the register address
byte. Table 5 shows the memory write bits. Set both M1
and M0 to low or high when writing to or reading from
the register values through the I2C bus.
Table 2 shows the register map. The same register
address and register name exists in the MTP memory
bank, I2C register bank, and the DAC register bank.
The write control bits determine which memory location
the data is stored into.
Register Description
Only the 10 LSBs are written to the registers (see Table
3). During a write operation, the write control bits (the 2
MSBs) are stripped from the incoming data stream and
are used to determine whether the MTP or DAC regis-
ters are updated (see Table 4).
Volatile Memory
The MAX9672/MAX9673/MAX9674 feature a double-
buffered register structure. The volatile (DAC) memory
can be updated without updating the output voltage.
Figure 8 shows how to program a single DAC. The out-
put voltage is updated after sending the LSB (D0).
VCOM Programmable Range
The MAX9672/MAX9673/MAX9674 feature the program-
mable range for VCOM. VCOMMIN and VCOMMAX
registers provide low and high limits for the VCOM DAC
register. At the factory, VCOMMIN is set to 0 and
VCOMMAX is set to 1023 (default values) to provide the
14 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
S
SLAVE ADDRESS
0
A
0
0
REGISTER ADDRESS
A
Sr
SLAVE ADDRESS
1
A
R/W
REPEATED START
R/W
ACKNOWLEDGE FROM MASTER
D9 D8
M1 M0
NOT ACKNOWLEDGE FROM MASTER
D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
DATA BYTE 1
A
DATA BYTE 2
A
P
1 WORD
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 6. Reading One Indexed Word of Data from the MAX9672/MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
ACKNOWLEDGE FROM MAX9672/
MAX9673/MAX9674
S
X
SLAVE ADDRESS
0
A
0
0
REGISTER ADDRESS
A
Sr
SLAVE ADDRESS
1
A
R/W
REPEATED START
R/W
M1 M0
ACKNOWLEDGE FROM MASTER
D9 D8
ACKNOWLEDGE FROM MASTER
D7 D6 D5 D4 D3 D2 D1 D0
ACKNOWLEDGE FROM MASTER
D9 D8
NOT ACKNOWLEDGE FROM MASTER
D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
X
X
X
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE n-1
A
DATA BYTE n
A
P
1 WORD
1 WORD
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 7. Reading n Bytes of Indexed Data from the MAX9672/MAX9673/MAX9674
______________________________________________________________________________________ 15
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
R/W
= 0
S
1
1
1
0
1
0
B1
A
0
0
D5
D4
D3
D2
D1
D0
A
SLAVE ID
M1 M0
DAC/VCOM ADDRESS
1
0
X
X
X
X
D9
D8
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
DATA
DATA
Figure 8. Single DAC Programming
R/W
= 0
S
1
0
0
1
0
0
1
X
X
0
1
X
X
0
X
X
B1
D9
D9
A
A
A
0
0
D5
D5
D5
D4
D3
D2
D1
D0
D0
D0
A
A
A
SLAVE ID
M1 M0
DAC/VCOM ADDRESS
X
D8
D8
D7
D7
D6
D6
D4
D3
D2
D2
D1
D1
DATA
DATA
X
X
D4
D3
DATA
DATA
DATA
1
0
X
X
X
D9
D8
A
D7
D6
D5
D4
D3
DATA
D2
D1
D0
A
P
23/MAX9674
Figure 9. Multiple (or All) DACs Programming
It is possible to write to multiple DACs first then update
the output voltage of all channels simultaneously, as
shown in Figure 9. In this mode, it is possible for the I2C
master to write to all registers of the MAX9672/
MAX9673/MAX9674 (Gamma and VCOM) in one commu-
nication. In that case, the value programmed on address-
es 0x10, 0x11, and 0x13 through 0x17 are meaningless.
However, the MAX9672/MAX9673/MAX9674 send an
acknowledge bit for each of the 2 bytes on any of these
addresses. The control bits (W1, W0) shown in Figure 9
are set in a way that all DACs are programmed to their
desired value with no changes to the output voltages until
the LSB of the last DAC is received and then all the chan-
nels are updated simultaneously.
can be written to at least 300 times. Figure 10 shows a
single write to a MTP address. The control bits on Figure
10 set in a way that the MTP register is updated at the
end of the LSB (D0).
Figure 11 shows how to program multiple MTP registers
in one communication transition. Similar to program-
ming the volatile memory, the first 2 bytes of data corre-
spond to the DAC/VCOM address specified by the
master on the previous byte and the following 2 bytes
of data correspond to the next address and so on. In
this configuration all the MTP registers are programmed
at the same time following the LSB of the last set of
data bytes. (The last set of data bytes is different than
the previous bytes as it is bits 15 and 14.) If for some
reason the master issues a STOP condition before
sending the last 2 bytes of the data with appropriate
values of bits 15 and 14 (01), then none of the MTP reg-
isters are updated.
Nonvolatile Memory
The MAX9672/MAX9673/MAX9674 are able to write to
nonvolatile memory (MTP) of any single DAC/VCOM reg-
ister in a single or burst I2C transaction. This memory
16 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
R/W
= 0
S
1
1
1
0
1
0
B1
A
0
0
D5
D4
D3
D2
D1
D0
A
SLAVE ID
M1 M0
DAC/VCOM ADDRESS
0
1
X
X
X
X
D9
D8
A
D7
D6
D5
D4
D3
D2
D1
D0
A
P
DATA
DATA
Figure 10. Single MTP Programming
R/W
= 0
S
1
0
0
1
0
0
1
X
X
0
1
X
X
0
X
X
B1
D9
D9
A
A
A
0
0
D5
D5
D5
D4
D3
D2
D1
D0
D0
D0
A
A
A
SLAVE ID
M1 M0
DAC/VCOM ADDRESS
X
D8
D8
D7
D7
D6
D6
D4
D3
D2
D2
D1
D1
DATA
DATA
X
X
D4
D3
DATA
DATA
DATA
0
1
X
X
X
D9
D8
A
D7
D6
D5
D4
D3
DATA
D2
D1
D0
A
P
Figure 11. Multiple MTP Programming
Programming the MTP registers also updates the
DACs/VCOM volatile memory as well as the output volt-
ages. Similar to multiple volatile memory programming,
the update only occurs after the LSB of the last byte is
received. All the outputs are programmed and updated
simultaneously. However, depending on the number of
MTP registers, it takes 31ms to 500ms to store the val-
ues into the nonvolatile memory. During this time, the
MAX9672/MAX9673/MAX9674 are not available on the
I2C and any communication from the master should be
delayed until the MTP is programmed. Any attempt
from the I2C master to talk to the MAX9672/MAX9673/
MAX9674 is not acknowledged.
address to 10 to set all the DACs and the output volt-
ages to the values of MTP (as shown in Figure 12). The
MAX9672/MAX9673/MAX9674 ignore the DAC/VCOM
address in this case.
It is also possible to update the DAC and output volt-
age of only one channel from the MTP. Set the 2 MSBs
(M1 and M0) of the DAC/VCOM address to 01 (as
shown in Figure 13) to move a specific value from MTP
into the DAC and output voltage of a single channel.
The MAX9672/MAX9673/MAX9674 feature a double-
buffered register structure. It is important to note that
updating the volatile (DAC) memory is not the same as
updating the output voltage. It is possible to write to
multiple DACs first then update the output voltage of all
channels simultaneously.
General and Single Acquire Commands
It is possible to update all the DAC outputs to the previ-
ously stored MTP values with one special command.
Set the 2 MSBs (M1 and M0) of the DAC/VCOM
______________________________________________________________________________________ 17
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
R/W
= 0
S
1
1
1
0
1
0
B1
A
1
0
0
0
0
0
0
0
A
P
SLAVE ID
M1 M0
Figure 12. General Acquire Command to Update All Outputs with MTP
R/W
= 0
S
1
1
1
0
1
0
B1
A
0
1
D5
D4
D3
D2
D1
D0
A
P
SLAVE ID
M1 M0
DAC/VCOM ADDRESS
Figure 13. Single Acquire Command to Update One Output with MTP
If REF is powered up after AVDD, then the outputs track
REF. If REF is powered up before AVDD, then the out-
puts track AVDD.
Applications Information
Driving the Resistor Ladders
with More Current
For power-down, AVDD and REF must be powered down
first to 0V, and then DVDD can safely be powered down.
If the gamma buffers cannot provide enough current to
drive the ends of the resistor ladders, then attach an
additional resistor from the nearest supply. For example,
at the very top of the resistor ladder, attach an additional
resistor to AVDD. At the very bottom of the resistor lad-
der, attach an additional resistor to GND. The
MAX9672/MAX9673/MAX9674 greatly diminish any
noise from AVDD supply through the discrete resistor
because the high-frequency noise from AVDD has been
attenuated, and the buffers have excellent AC PSRR.
See Figure 14.
Power Supplies and Bypass Capacitors
The MAX9672/MAX9673/MAX9674 operate from a sin-
gle 9V to 20V analog supply (AVDD) and a 2.7V to 3.6V
digital supply (DVDD). Bypass AVDD to GND with
0.1µF and 10µF capacitors in parallel. Use an extensive
ground plane to ensure optimum performance. Bypass
DVDD to GND with a 0.1µF capacitor. The 0.1µF
bypass capacitors should be as close as possible to
the device.
23/MAX9674
Refer to the MAX9672/MAX9673/MAX9674 evaluation
kit for a proven PCB layout.
VCOM Operational Amplifier
with Feedback Resistors
The output (VCOM) and negative input (VCOM_FB) of
the operational amplifier would usually be connected
together, resulting in a unity-gain configuration. If a
higher, closed-loop gain is desired, add feedback
resistors as shown in Figure 15.
Layout and Grounding
Exposed Pad
If the MAX9672/MAX9673/MAX9674 are mounted using
reflow soldering or wave soldering, the ground via(s) for
the exposed pad should have a finished hole size of at
least 14 mils to insure adequate wicking of soldering
onto the exposed pad. If the MAX9672/MAX9673/
MAX9674 are mounted using the solder mask tech-
nique, the via requirement does not apply. In either
case, the exposed pad must be connected to both digi-
tal and analog grounds through a low thermal resis-
tance path to ensure adequate heat dissipation. Do not
route traces under these packages.
Power-Up and Power-Down
Figures 16 and 17 show the proper startup sequence of
the MAX9672/MAX9673/MAX9674. The digital supply
must be powered up first. The analog supply should not
be powered up for at least 250µs (typ) after the digital
supply has been powered up. During this time, the MTP
register values are overwriting the default values in the
I2C registers. Once AVDD is above approximately 8V,
the output buffers have enough headroom to power up.
18 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
18V
REF
AVDD
GMA1
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10-BIT
DAC
GMA2
10-BIT
DAC
GMA3
10-BIT
DAC
GMA4
10-BIT
DAC
GMA5
10-BIT
DAC
GMA6
10-BIT
DAC
GMA7
10-BIT
DAC
GMA8
10-BIT
DAC
SOURCE
DRIVER
GMA9
2
MTP
MEMORY
DAC
REGISTERS
10-BIT
DAC
I C
REGISTERS
LCD PANEL
GMA10
GMA11
GMA12
GMA13*
GMA14*
GMA15**
GMA16**
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
18V
10-BIT
DAC
AVDD_AMP
VCOM
DVDD
SDA
SCL
A0
VCOM_FB
AGND_AMP
MAX9672
MAX9673
MAX9674
2
I C
INTERFACE
GND
GND
*NOT AVAILABLE FOR THE MAX9672.
**NOT AVAILABLE FOR THE MAX9672/MAX9673.
Figure 14. Typical Application Circuit with Additional Pullup and Pulldown Resistors on GMA1 and GMA16, Respectively
______________________________________________________________________________________ 19
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
VCOM
VCOM_FB
Figure 15. VCOM Operational Amplifier with Feedback Resistors
V
V
= 16.0V
= 3.3V
AVDD
DVDD
23/MAX9674
AVDD
REF
REF
5V/div
0V
5V/div
0V
GMA1
GMA6
GMA6
GMA12
DVDD
4ms/div
4ms/div
Figure 16. Recommended Power-Up Sequence
Figure 17. REF Powered Up After AVDD and DVDD
Chip Information
PROCESS: BiCMOS
20 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
Typical Operating Circuit
18V
REF
AVDD
GMA1
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10-BIT
DAC
GMA2
10-BIT
DAC
GMA3
10-BIT
DAC
GMA4
10-BIT
DAC
GMA5
10-BIT
DAC
GMA6
10-BIT
DAC
GMA7
10-BIT
DAC
GMA8
10-BIT
DAC
SOURCE
DRIVER
GMA9
2
MTP
MEMORY
DAC
REGISTERS
10-BIT
DAC
I C
REGISTERS
LCD PANEL
GMA10
GMA11
GMA12
GMA13*
GMA14*
GMA15**
GMA16**
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
18V
10-BIT
DAC
AVDD_AMP
VCOM
DVDD
SDA
SCL
A0
MAX9672
MAX9673
MAX9674
VCOM_FB
AGND_AMP
2
I C
INTERFACE
GND
GND
*NOT AVAILABLE FOR THE MAX9672.
**NOT AVAILABLE FOR THE MAX9672/MAX9673.
______________________________________________________________________________________ 21
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0140
90-0028
28 TQFN-EP
T2855+8
23/MAX9674
22 ______________________________________________________________________________________
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
23/MAX9674
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
______________________________________________________________________________________ 23
10-Bit, Programmable Gamma Reference
Systems with MTP for TFT LCDs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
9/09
10/09
11/09
Initial release
—
12
MTP factory initialization values changed per customer request in Table 3
Updated write operations and soldering temperature (reflow)
1, 2, 8, 16
2, 3, 4, 6, 8, 11,
14, 19, 21
3
4
3/10
2/11
Added lead temperature and made various corrections
MAX69
Changed MTP factory initialization value of MAX9673 for GMA5
12
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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