MAX9693ESE [MAXIM]
Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable; 单/双，超高速， ECL输出比较器与锁存使能
| 型号： | MAX9693ESE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable |
| 文件： | 总10页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1789; Rev 1; 10/02
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
General Description
Features
The MAX9691/MAX9692/MAX9693 are ultra-fast ECL
comparators capable of very short propagation delays.
Their design maintains the excellent DC matching char-
acteristics normally found only in slower comparators.
ꢀ 1.2ns Propagation Delay
ꢀ 100ps Propagation Delay Skew
ꢀ 150ps Dispersion
The MAX9691/MAX9692/MAX9693 have differential
inputs and complementary outputs that are fully com-
patible with ECL-logic levels. Output current levels are
capable of driving 50Ω terminated transmission lines.
The ultra-fast operation makes signal processing possi-
ble at frequencies in excess of 600MHz.
ꢀ 0.5ns Latch Setup Time
ꢀ 0.5ns Latch-Enable Pulse Width
ꢀ Available in µMAX and QSOP Packages
ꢀ +5V, -5.2V Power Supplies
The MAX9692/MAX9693 feature a latch-enable (LE)
function that allows the comparator to be used in a
sample-hold mode. When LE is ECL high, the compara-
tor functions normally. When LE is driven ECL low, the
outputs are forced to an unambiguous ECL-logic state,
dependent on the input conditions at the time of the
latch input transition. If the latch-enable function is not
used on either of the two comparators, the appropriate
LE input must be connected to ground; the companion
LE input must be connected to a high ECL logic level.
Ordering Information
TEMP
RANGE
PART
PIN-PACKAGE
MAX9691EUA
-40°C to +85°C
-40°C to +85°C
8 µMAX
8 SO
MAX9691ESA
MAX9691EPA
-40°C to +85°C
8 PDIP
Ordering Information continued at the end of data sheet.
These devices are available in SO, QSOP, and tiny
µMAX packages for added space savings.
Selector Guide
COMPARATORS LATCH PIN-
PER PACKAGE ENABLE PACKAGE
________________________Applications
PART
High-Speed Line Receivers
8 µMAX,
8 SO, 8 PDIP
MAX9691
MAX9692
1
1
No
Peak Detectors
Threshold Detectors
High-Speed Triggers
10 µMAX,
16 SO, 16 PDIP
Yes
16 QSOP,
16 SO, 16 PDIP
MAX9693
2
Yes
Pin Configurations appear at end of data sheet.
_________________________________________________________Functional Diagrams
NONINVERTING
INPUT
NONINVERTING
INPUT
IN+
IN-
Q OUT
Q OUT
Q OUT
Q OUT
INVERTING
INPUT
INVERTING
INPUT
R
R
L
L
R
R
R
R
L
L
L
L
MAX9693
MAX9693
MAX9691
LE LE
LATCH ENABLE
LE LE
V
T
V
T
LATCH ENABLE
THE OUTPUTS ARE OPEN EMITTERS, REQUIRING EXTERNAL PULLDOWN
RESISTORS. THESE RESISTORS MAY BE IN THE RANGE OF 50Ω TO 200Ω
CONNECTED TO -2.0V, OR 240Ω TO 2000Ω CONNECTED TO -5.2V.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V ) ...............................................-0.3V to +6V
8-Pin PDIP (derate 10.53mW/°C above +70°C)...........842mW
10-Pin µMAX (derate 5.6mW/°C above +70°C)...........444mW
16-Pin QSOP (derate 8.3mW/°C above +70°C)..........667mW
16-Pin SO (derate 8.7mW/°C above +70°C)...............696mW
16-Pin PDIP (derate 9.09mW/°C above +70°C)..........727mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
Supply Voltage (V )................................................-6V to +0.3V
EE
Input Voltage....................................(V
+ 0.3V) to (V - 0.3V)
CC
EE
Output Short-Circuit Duration ....................................Continuous
Differential Input Voltage ...................................................... 5V
Latch Enable...............................................(V - 0.3V) to +0.3V
EE
Output Current ....................................................................50mA
Input Current .................................................................... 25mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin µMAX (derate 4.1mW/°C above 70°C)...............330mW
8-Pin SO (derate 5.88mW/°C above +70°C)...............471mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V, V = -5.2V, R = 50Ω to V , V = -2V, LE = 0, T = T
to T , unless otherwise noted.)
MAX
CC
EE
L
T
T
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
-6.5
TYP
MAX
6.5
UNITS
mV
T
= +25°C
A
Input Offset Voltage
Temperature Coefficient
Input Offset Current
V
OS
T = T
to T
MAX
-11.5
+11.5
A
MIN
∆V /∆T
10
µV/°C
µA
OS
T
T
T
= +25°C
0.2
5
8
A
A
A
I
OS
= T
to T
MIN
MAX
= +25°C
to T
6
20
Input Bias Current
I
µA
B
T = T
30
A
MIN
MAX
Input Voltage Range
V
Note 1
-2.5
60
+3.0
V
CM
Common-Mode Rejection Ratio
CMRR
-2.5V ≤ V
≤ +3.0V (Note 1)
80
60
dB
CM
Positive Power-Supply Rejection
Ratio
+PSRR
4.5V ≤ V
≤ 5.5V
dB
dB
CC
Negative Power-Supply
Rejection Ratio
-PSRR
AOL
-5.7V ≤ V ≤ -4.7V
60
EE
Open-Loop Gain
V
= 0V
70
60
1.7
3
dB
kΩ
V
CM
Differential Input Resistance
Differential Input Clamp Voltage
Input Capacitance
R
-10mV < V < 10mV
IN
IN
C
pF
µA
µA
V
IN
Latch Enable Input Current High
Latch Enable Input Current Low
Latch Enable Logic High Voltage
Latch Enable Logic Low Voltage
I
V
V
= 1.1V
= 1.5V
60
0.2
120
10
IH(LE)
IH(LE)
IL(LE)
I
IL(LE)
V
-1.1
IH(LE)
V
-1.5
V
IL(LE)
T
T
T
T
T
T
= T
= T
-1.2
-0.87
-0.70
-0.76
-1.57
-1.51
-1.55
A
A
A
A
A
A
MIN
Logic Output High Voltage
V
-0.99
-1.06
-1.93
-1.89
-1.89
V
V
OH
MAX
= +25°C
= T
= T
MIN
MAX
Logic Output Low Voltage
V
OL
= +25°C
2
_______________________________________________________________________________________
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, V = -5.2V, R = 50Ω to V , V = -2V, LE = 0, T = T
to T , unless otherwise noted.)
MAX
CC
EE
L
T
T
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
46
UNITS
T
T
T
T
= +25°C
34
A
A
A
A
MAX9693
= T
to T
50
MIN
MAX
MAX
Supply Current
I
mA
CC
= +25°C
= T to T
18
26
MAX9691/
MAX9692
36
MIN
AC ELECTRICAL CHARACTERISTICS
(V
= 5V, V = -5.2V, R = 50Ω to V , V = -2V, LE = 0, T = T
to T
, unless otherwise noted.)
MAX
CC
EE
L
T
T
A
MIN
SYMBOL
CONDITIONS
MIN
TYP
MAX
PARAMETER
UNITS
MAX9691/MAX9692/MAX9693
T
T
= +25°C
1.2
1.8
2.0
A
A
Propagation Delay (Notes 1, 2)
t
, t
ns
pd+ pd-
= T
to T
MAX
MIN
Rise/Fall Time
t , t
10% to 90%
500
100
150
ps
ps
ps
r
f
Propagation Delay Skew
Dispersion
∆
PD
P
V
from 10mV to 100mV
OD
DSP
MAX9692/MAX9693
T
T
= +25°C
1.0
1.8
2.0
1.0
1.0
1.0
A
A
Latch-Enable Time (Note 1)
T
( )
ns
LE
= T
to T
MAX
MIN
Latch-Enable Pulse Width (Note 1)
Setup Time (Note 1)
t
0.5
0.5
0.5
ns
ns
ns
pw(LE)
t
t
s
Hold Time (Note 1)
h
Channel-to-Channel
Propagation Match
t
Note 2 (MAX9693 only)
100
ps
PDM
Note 1: Guaranteed by design.
Note 2: V = 100mV, V
= 10mV.
IN
OD
_______________________________________________________________________________________
3
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Typical Operating Characteristics
(V
= +5V, V = -5.2V, R = 50Ω to V , V = -2V, V
= 10mV, T = +25°C, unless otherwise noted.)
OD A
CC
EE
L
T
T
WORST-CASE PROPAGATION DELAY
vs. INPUT OVERDRIVE
WORST-CASE PROPAGATION DELAY
vs. SOURCE IMPEDANCE
WORST-CASE PROPAGATION DELAY
vs. C
LOAD
1400
6000
5000
4000
3000
2000
1000
0
1800
1600
1400
1200
1000
800
1200
1000
800
600
400
600
0
10 20 30 40 50 60 70 80 90 100
INPUT OVERDRIVE (mV)
0
50 100 150 200 250 300 350 400 450 500
0
5
10
15
20
25
C
(pF)
LOAD
SOURCE IMPEDANCE (Ω)
WORST-CASE PROPAGATION DELAY
vs. TEMPERATURE
OUTPUT HIGH VOLTAGE
vs. TEMPERATURE
OUTPUT LOW VOLTAGE
vs. TEMPERATURE
-1.60
-1.62
-1.64
-1.66
-1.68
-1.70
-1.72
-1.74
-1.76
-1.78
-1.80
1400
1300
1200
1100
1000
900
-0.6
-0.7
-0.8
-0.9
-1.0
-1.1
R
= 100Ω
R
= 100Ω
PULLDOWN
PULLDOWN
R
= 200Ω
PULLDOWN
R
= 200Ω
PULLDOWN
R
= 50Ω
PULLDOWN
800
R
= 50Ω
PULLDOWN
35
700
V
= 100mV
60
OD
600
-40
-15
10
35
85
-40
-15
10
35
60
85
-40
-15
10
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INPUT BIAS CURRENT
vs. DIFFERENTIAL INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs. TEMPERATURE
INPUT BIAS CURRENT
vs. TEMPERATURE
5000
4000
3000
2000
1000
0
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
2000
1500
1000
500
0
-1000
-2000
-3000
-4000
-5000
-500
-1000
-1500
-2000
-5 -4 -3 -2 -1
0
1
2
3
4
5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (V)
4
_______________________________________________________________________________________
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Typical Operating Characteristics (continued)
(V
= +5V, V = -5.2V, R = 50Ω to V , V = -2V, V
= 10mV, T = +25°C, unless otherwise noted.)
OD A
CC
EE
L
T
T
100MHz OUTPUT RESPONSE
PROPAGATION DELAY
MAX9691/3-12
MAX9691/3-11
V
V
= 100mV
OD
IN
-1.0V
= 10mV
V
IN
200mV/div
Q OUT
200mV/div
-1.8V
-1.0V
Q OUT
200mV/div
Q OUT - Q OUT
200mV/div
-1.8V
1ns/div
1ns/div
plane for the MAX9691/MAX9692. GND1 biases the
input gain stages, while GND2 biases the ECL output
stage. If the LE function is not used, connect the LE pin
to GND (MAX9692/MAX9693) and the complementary
LE to ECL logic high level (MAX9693 only). Do not
leave the inputs of an unused comparator floating for
the MAX9693.
__________ Applications Information
Layout
Because of the MAX9691/MAX9692/MAX9693s’ large
gain-bandwidth characteristic, special precautions
must be taken to use them. A PC board with a ground
plane is mandatory. Mount 0.01µF ceramic decoupling
capacitors as close to the power-supply pins as possi-
ble, and process the ECL outputs in microstrip fashion,
consistent with the load termination of 50Ω to 200Ω (for
Input Slew-Rate Requirements
As with all high-speed comparators, the high gain-
bandwidth product of these devices creates oscillation
problems when the input goes through the linear
region. For clean switching without oscillation or steps
in the output waveform, the input must meet certain
minimum slew-rate requirements. The tendency of the
part to oscillate is a function of the layout and source
impedance of the circuit employed. Poor layout and
larger source impedance will increase the minimum
slew-rate requirement.
V = -2V). For low-impedance applications, microstrip
T
layout and terminations at the input may also be help-
ful. Pay close attention to the bandwidth of the decou-
pling and terminating components. Chip components
can be used to minimize lead inductance. Connect
GND1 and GND2 together to a solid copper ground
V
IN
Q
Figure 1 shows a high-speed receiver application with
50Ω input and output termination. With this configura-
tion, in which a ground plane and microstrip PC board
are used, the minimum slew rate for clean output
switching is 1V/µs.
50Ω
Q
LE
50Ω
-2V
In many applications, adding regenerative feedback
will assist the input signal through the linear region,
which will lower the minimum slew-rate requirement
considerably. For example, with the addition of positive
R
C
50Ω
f
f
50Ω
feedback components, R = 1kΩ and C = 10pF, the
f
f
minimum slew-rate requirement can be reduced by a
factor of four.
Figure 1. Regenerative Feedback—High-Speed Receiver with
50Ω Input and Output Termination
_______________________________________________________________________________________
5
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
INPUT
20mV/div
0V
comparator after time interval t . Output Q and Q tran-
pd
sistors are similar in timing. The input signal must occur
OUTPUT
500mV/div
-0.9V
-1.7V
at time t before the latch falling edge, and must be
s
maintained for time t after the edge to be acquired.
h
After t , the output is no longer affected by the input sta-
h
tus until the latch is again strobed. A minimum latch
pulse width of t
is needed for the strobe opera-
pw(LE)
2ns/div
tion, and the output transitions occur after a time t
.
LE( )
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
Figure 2. Signal Processed at 100MHz with Input Signal Level
of 14mV
RMS
As high-speed receivers, the MAX9691/MAX9692/
MAX9693 are capable of processing signals in excess
of 600MHz. Figure 2 is a 100MHz example with an
input signal level of 14mV
.
RMS
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
COMPARE
LATCH
ENABLE
50%
t
s
t
LATCH
pw(LE)
t
t
h
DIFFERENTIAL
INPUT
V
IN
VOLTAGE
V
OS
V
OD
pd
t
LE(+)
50%
50%
Q
Q
Figure 3. Timing Diagram
6
_______________________________________________________________________________________
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Definition of Terms
Chip Information
V
Input Offset Voltage. The voltage required
OS
MAX9691 TRANSISTOR COUNT: 106
MAX9692 TRANSISTOR COUNT: 106
MAX9693 TRANSISTOR COUNT: 207
between the input terminals to obtain 0V dif-
ferential at the output.
V
V
Input Voltage Pulse Amplitude
Input Voltage Overdrive
IN
OD
pd+
t
t
t
Input to Output High Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output low-to-high transition.
Input to Output Low Delay. The propagation
delay measured from the time the input signal
crosses the input offset voltage to the 50%
point of an output high-to-low transition.
pd-
Ordering Information (continued)
TEMP
RANGE
PART
PIN-PACKAGE
MAX9692EUB
MAX9692ESE
MAX9692EPE
MAX9693ESE
MAX9693EEE
MAX9693EPE
-40°C to +85°C
10 µMAX
Latch-Enable to Output High Delay. The prop-
agation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output low-to-high tran-
sition.
LE(+)
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 Narrow SO
16 PDIP
16 Narrow SO
16 QSOP
t
Latch-Enable to Output Low Delay. The prop-
agation delay measured from the 50% point of
the latch-enable signal low-to-high transition
to the 50% point of an output high-to-low tran-
sition.
LE(-)
16 PDIP
t
t
Latch-Enable Pulse Width. The minimum time
the latch-enable signal must be high to acquire
and hold an input signal.
pw(LE)
Setup Time. The minimum time before the
negative transition of the latch-enable pulse
that an input signal must be present to be ac-
quired and held at the outputs.
s
t
h
Hold Time. The minimum time after the nega-
tive transition of the latch-enable signal that
an input signal must remain unchanged to be
acquired and held at the output.
∆
pd
Propagation Delay Skew. The difference in
propagation delay between the Q and Q out-
puts crossing each other in both directions.
P
DSP
Propagation Delay Dispersion. The change in
propagation delay as a result of the overdrive
of the input signal varying.
t
Propagation Delay Match (MAX9693 only).
The difference in propagation delay between
two separate channels.
pdm
_______________________________________________________________________________________
7
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Pin Configurations
TOP VIEW
MAX9691
MAX9692
V
1
2
3
4
5
10 GND1
CC
V
1
2
3
4
8
7
6
5
GND1
GND2
Q OUT
Q OUT
CC
IN+
IN-
9
8
7
6
GND2
Q OUT
Q OUT
IN+
IN-
N.C.
LE
V
EE
V
EE
DIP/SO/µMAX
µMAX
MAX9692
MAX9693
GND1
1
16 GND2
15 N.C.
14 N.C.
13 N.C.
Q OUT
Q OUT
GND
LEA
1
2
16 Q OUT
15 Q OUT
14 GND
13 LEB
V
2
3
4
5
6
7
8
CC
IN+
IN-
3
4
5
6
7
8
Q OUT
N.C.
LE
12
LEA
12 LEB
11 Q OUT
10 N.C.
V
11
10 INB-
INB+
V
EE
CC
N.C.
INA-
INA+
V
9
N.C.
9
EE
DIP/SO/QSOP
PDIP/SO
8
_______________________________________________________________________________________
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
_______________________________________________________________________________________
9
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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