MAX97000_V01 [MAXIM]
Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier;
| 型号： | MAX97000_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Audio Subsystem with Mono Class D Speaker and Class H Headphone Amplifier |
| 文件： | 总34页 (文件大小：3686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5004; Rev 1; 6/10
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
General Description
Features
Sꢀ1.6V_to_2.0V_Headphone_Supply_Voltage
The MAX97000 audio subsystem combines a mono
speaker amplifier with a stereo headphone amplifier and
an analog DPST switch. The headphone and speaker
amplifiers have independent volume control and on/off
control. The four inputs are configurable as two differen-
tial inputs or four single-ended inputs.
Sꢀ2.7V_to_5.5V_Speaker_Supply_Voltage
SꢀInternal_LDO_Allows_Single-Supply_Operation
Sꢀ725mW_Speaker_Output_(V
_=_3.7V,_Z _=_8I_
SPK
PVDD
+_68µH)
Sꢀ40mW/Channel_Headphone_Output_(R _=_16I)
The entire subsystem is designed for maximum efficiency.
The high-efficiency 725mW Class D speaker amplifier
operates directly from the battery and consumes no more
than 1FA in shutdown mode. The Class H headphone
amplifier utilizes a dual-mode charge pump to maximize
efficiency while outputting a ground-referenced signal
that does not require output coupling capacitors.
HP
SꢀLow-Emission_Class_D_Amplifier
SꢀEfficient_Class_H_Headphone_Amplifier
SꢀGround-Referenced_Headphone_Outputs
SꢀTwo_Stereo_Single-Ended/Mono_Differential_Inputs
SꢀIntegrated_Distortion_Limiter_(Speaker_Outputs)
SꢀIntegrated_DPST_Analog_Switch
The speaker amplifier incorporates a distortion limiter to
automatically reduce the volume level when excessive
clipping occurs. This allows high gain for low-level sig-
nals without compromising the quality of large signals.
SꢀNo_Clicks_and_Pops
SꢀTDMA_Noise_Free
All control is performed using the 2-wire, I2C interface.
The MAX97000 operates in the extended -40NC to +85NC
temperature range, and is available in the 2mm x 2mm,
25-bump WLP package (0.4mm pitch).
Sꢀ2mm_x_2mm,_25-Bump_0.4mm_Pitch_WLP_Package_
Ordering Information
PART
TEMP_RANGE
PIN-PACKAGE
Applications
Cell Phones
MAX97000EWA+
-40NC to +85NC
25 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Portable Multimedia Players
Simplified Block Diagram
BATTERY
2.7V TO 5.5V
2
I C
1.8V
POWER SUPPLY
CONTROL
MAX97000
STEREO/
MONO
INPUT
CLASS D
AMPLIFIER
VOLUME
LIMITER
CLASS H
AMPLIFIER
VOLUME
STEREO/
MONO
INPUT
CHARGE
PUMP
SWITCH
_ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ _Maxim Integrated Products_ _ 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Audio Subsystem with Mono Class D Speaker
and Class H Headphone Amplifier
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional Diagram/Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Digital I/O Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Class D Speaker Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ultra-Low EMI Filterless Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DirectDrive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
I2C Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
I2C Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2
Audio Subsystem with Mono Class D Speaker
and Class H Headphone Amplifier
TABLE OF CONTENTS (CONTINUED)
Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Charge-Pump Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Early STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Supply Bypassing, Layout, and Grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WLP Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Functional Diagram/Typical Application Circuit
OPTIONAL
1.6V TO 2.0V
2.5V TO 5.5V
2.7V TO 5.5V
10µF
1µF
1µF
1µF
10µF
VDD
B1
LDOIN
B2
PVDD
C1
LDO
C5 BIAS
PGAINA
-6dB TO +18dB
BIAS
0.47µF
1µF
INA1 E4
INADIFF
OPTIONAL
HPVDD
LPMODE
HPLMIX
HPLVOL:
-64dB TO +6dB
B5 HPL
CLASS H
0/3dB
PGAINA
-6dB TO +18dB
HPLEN
0.47µF
0.47µF
E5
INA2
HPVSS
HPVDD
+
OPTIONAL
OPTIONAL
HPRVOL:
-64dB TO +6dB
A5 HPR
CLASS H
0/3dB
PGAINB
-6dB TO +18dB
HPREN
HPVSS
INB1 D4
HPRMIX
INBDIFF
PVDD
SPKVOL:
-30dB TO +20dB
E1 OUTP
D1 OUTN
CLASS D
+12dB
SPKEN
PGAINB
-6dB TO +18dB
SPKMIX
PGND
0.47µF
INB2 D5
+
THD LIMITER
THDCLP
OPTIONAL
ANALOG SWITCHES
COM1 D2
COM2 D3
E2 NC1
E3 NC2
VDD
SWEN
SDA B3
SCL B4
VDD
2
I C
INTERFACE/
SHUTDOWN
MAX97000
SHDN C4
CHARGE PUMP
A1
A2
A3
A4
C3
GND
C2
PGND
HPVDD HPVSS
1µF
C1P
C1N
1µF
1µF
4
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
ABSOLUTE_MAXIMUM_RATINGS
(Voltages with respect to GND.)
Continuous Current In/Out of COM1,
VDD, HPVDD........................................................-0.3V to +2.2V
PVDD, LDOIN.......................................................-0.3V to +6.0V
PGND ...................................................................-0.1V to +0.1V
HPVSS .................................................................-2.2V to + 0.3V
C1N .....................................(HPVSS - 0.3V) to (HPVDD + 0.3V)
C1P..........................................................- 0.3V to (VDD + 0.3V)
HPL, HPR ............................. (HPVSS - 0.3V) to (HPVDD +0.3V)
INA1, INA2, INB1, INB2, BIAS .............................-0.3V to +6.0V
SDA, SCL, SHDN .................................................-0.3V to +6.0V
COM1, COM2, NC1, NC2,
COM2, NC1, NC2...................................................... Q150mA
Continuous Input Current (all other pins)........................ Q20mA
Duration of OUT_ Short Circuit to GND
or PVDD.................................................................Continuous
Duration of Short Circuit Between OUTP
and OUTN .............................................................Continuous
Duration of HP_ Short Circuit to GND or VDD ..........Continuous
Continuous Power Dissipation (T = +70NC) Multilayer Board
A
25 WLP (derate 19.2mW/NC above +70NC) ................850mW
Junction Temperature .....................................................+150NC
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflows).....................................+260NC
OUTP, OUTN......................................-0.3V to (PVDD + 0.3V)
Continuous Current In/Out of PVDD, PGND, OUT_...... Q800mA
Continuous Current In/Out of HPR, HPL,
VDD, LDOIN .............................................................. Q140mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL_CHARACTERISTICS
(V
LDOIN
= V
= V
= 3.7V, V
= V
= 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB,
PVDD
SHDN
GND
PGND
HPLVOL = HPRVOL = SPKVOL = 0dB, speaker loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) con-
SPK HP
nected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. Z
= J, R = J. C
= C
= C
= C
HPVSS BIAS
SPK
HP
C1P-C1N
HPVDD
= 1FF. T = T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
Guaranteed by PSRR test
MIN
TYP
MAX
UNITS
Speaker Amplifier Supply-
Voltage Range
V
PVDD
2.7
5.5
V
Headphone Amplifier Supply
Voltage Range
VDD
Guaranteed by PSRR test
Guaranteed by PSRR test
1.6
2.5
2
V
V
LDO Input Supply-Voltage Range
V
5.5
2
LDOIN
I
I
I
I
I
I
1.45
0.4
Low-power mode, T = +25NC,
LDOIN
PVDD
LDOIN
PVDD
LDOIN
PVDD
A
LPMODE = 0x01
0.7
2
1.45
0.79
0.42
1.38
1.45
1.8
HP mode, T = +25NC, stereo SE
A
input on INA, INB disabled
1.2
0.75
2.2
2
Quiescent Supply Current
mA
SPK mode, T = +25NC mono
A
differential input on INB, INA disabled
I
SPK + HP mode, T = +25NC stereo LDOIN
A
SE input on INA, INB disabled
I
I
I
2.7
175
110
PVDD
PVDD
LDOIN
90
T
= +25NC, internal gain, software
A
60
Shutdown Current
Turn-On Time
I
FA
SHDN
T
= +25NC, internal gain, I
+ I
,
A
PVDD
LDOIN
1
hardware
Time from power-on to full operation
including soft-start
t
8
ms
ON
Gain = -6dB, -3dB
Gain = 0dB to +9dB
Gain = +18dB
41.2
20.6
7.2
T
= +25NC,
A
Input Resistance
R
16
5.5
19
27
9.5
21
kI
kI
IN
internal gain
Feedback Resistance
R
T
= +25NC, external gain
A
20
F
5
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
ELECTRICAL_CHARACTERISTICS_(continued)
(V
LDOIN
= V
= V
= 3.7V, V
= V
= 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB,
PVDD
SHDN
GND
PGND
HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (Z
) connected between OUTP and OUTN. Headphone loads (R ) con-
SPK HP
nected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. Z
= J, R = J. C
= C
= C
= C
HPVSS BIAS
SPK
HP
C1P-C1N
HPVDD
= 1FF. T = T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Preamp = 0dB
2.3
Maximum Input Signal Swing
Preamp = +18dB
0.29
V
P-P
Preamp = external gain
2.3 x R /R
IN,EX F
Gain = 0dB
55
f = 1kHz (differential
input mode)
Common-Mode Rejection Ratio
CMRR
dB
Gain = +18dB
32
Input DC Voltage
Bias Voltage
IN__ inputs
1.125
1.13
1.2
1.2
1.275
1.27
V
V
V
BIAS
SPEAKER_AMPLIFIER
T
T
= +25NC, SPKM = 1
Q0.5
Q1.5
Q4
A
A
Output Offset Voltage
Click-and-Pop Level
V
mV
OS
= +25NC, SPKVOL = 0dB, SPKMIX = 0x01,
IN_DIFF = 0V
Peak voltage, T
=
A
Into shutdown
-70
-70
+25NC, A-weighted,
32 samples per
second, volume at
mute (Note 2)
K
dBV
CP
Out of shutdown
V
= 2.7V to 5.5V
50
75
65
PVDD
f = 217Hz,
V
= 200mV
RIPPLR
P-P
P-P
P-P
Power-Supply Rejection Ratio
PSRR
T
= +25NC (Note 2)
dB
A
f = 1kHz,
65
59
V
= 200mV
RIPPLR
f = 20kHz,
V
V
V
= 200mV
RIPPLR
THD+N P 1%,
= 4.2V
= 3.7V
930
725
PVDD
PVDD
Output Power
f = 1kHz,
mW
Z
SPK
= 8I + 68FH
V
PVDD
= 3.3V
562
(Note 3)
Total Harmonic Distortion +
Noise
f = 1kHz, P
= 360mW, T = +25NC,
OUT A
THD+N
SNR
0.05
0.6
%
Z
SPK
= 8Iꢀ+ 68FH
IN_DIFF = 0
(single-ended)
A-weighted, SPKMIX
= 0x03, referenced to
725mW
93
Signal-to-Noise Ratio
dB
IN_DIFF = 1 (differential)
93
250
Q20
12
Oscillator Frequency
Spread-Spectrum Bandwidth
Gain
f
kHz
kHz
dB
A
OSC
11.5
12.5
Current Limit
1.5
87
Efficiency
E
P
OUT
= 725mW, f = 1kHz, Z
= 8Iꢀ+ 68FH
%
SPK
A-weighted, (SPKMIX = 0x01), IN_DIFF = 1,
SPKVOL = 0dB
Output Noise
50
FV
RMS
6
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
ELECTRICAL_CHARACTERISTICS_(continued)
(V
LDOIN
= V
= V
= 3.7V, V
= V
= 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB,
PGND
PVDD
SHDN
GND
HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (Z
) connected between OUTP and OUTN. Headphone loads (R ) con-
SPK HP
nected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. Z
= J, R = J. C
= C
= C
= C
HPVSS BIAS
SPK
HP
C1P-C1N
HPVDD
= 1FF. T = T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
A
MIN
PARAMETER
CHARGE_PUMP
SYMBOL
CONDITIONS
= 0V
MIN
TYP
MAX
UNITS
V
V
V
V
V
V
V
= V
= V
= V
80
83
85
HPL
HPL
HPL
HPR
HPR
HPR
Charge-Pump Frequency
= 0.2V
= 0.5V
665
500
1.8
kHz
, V
HPL HPR
> V
TH
TH
TH
TH
Positive Output Voltage
Negative Output Voltage
V
V
V
HPVDD
, V
HPL HPR
< V
> V
< V
0.9
, V
HPL HPR
-1.8
-0.9
V
HPVSS
, V
HPL HPR
Output voltage at which the charge pump
switches between fast and slow clock
V
0.1
0.16
0.46
32
0.21
0.52
TH1
TH2
Headphone Output Voltage
Threshold
V
Output voltage at which the charge pump
V
0.40
switches modes, V
rising or falling
OUT
Time it takes for the charge pump to
transition from invert to split mode
ms
Mode Transition Timeouts
Time it takes for the charge pump to
transition from split to invert mode
20
Fs
HEADPHONE_AMPLIFIERS
T
T
= +25NC volume at mute
Q0.15
Q0.5
Q0.6
A
A
Output Offset Voltage
V
OS
mV
= +25NC, HP_VOL = 0dB, HP_MIX = 0x1,
IN_DIFF = 0
Peak voltage, T =
A
Into shutdown
-74
-74
+25NC, A-weighted, 32
samples per second,
volume at mute
Click-and-Pop Level
K
CP
dBV
Out of shutdown
(Note 2)
V
= 2.5V to 5.5V
70
85
84
LDOIN
f = 217Hz,
= 200mV
V
RIPPLE
P-P
P-P
P-P
Power-Supply Rejection Ratio
PSRR
T
= +25NC (Note 2)
dB
A
f = 1kHz,
= 200mV
80
62
V
RIPPLE
f = 20kHz,
= 200mV
V
RIPPLE
R
R
R
= 16I
40
23
HP
HP
HP
= 32I
= 32I,
THD+N = 1%,
f = 1kHz
Output Power
P
OUT
mW
%
LPMODE = 1,
LP gain = 3dB
34
T
= +25NC, HPL to HPR, volume at
maximum, HPLMIX = 0x01, HPRMIX = 0x02,
IN_DIFF = 0
A
Channel-to-Channel Gain
Tracking
Q0.3
Q2.5
7
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
ELECTRICAL_CHARACTERISTICS_(continued)
(V
LDOIN
= V
= V
= 3.7V, V
= V
= 0V. Input signal applied at INA configured single-ended, preamp gain = 0dB,
PVDD
SHDN
GND
PGND
HPLVOL = HPRVOL= SPKVOL = 0dB, speaker loads (Z
) connected between OUTP and OUTN. Headphone loads (R ) con-
SPK HP
nected from HPL or HPR to GND. SDA and SCL pullup voltage = 1.8V. Z
= J, R = J. C
= C
= C
= C
HPVSS BIAS
SPK
HP
C1P-C1N
HPVDD
= 1FF. T = T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
RHP = 32I
RHP = 16I
MIN
TYP
MAX
UNITS
0.02
0.03
Total Harmonic Distortion +
Noise
P
= 10mW,
OUT
THD+N
%
f = 1kHz
0.1
A-weighted, R = 16I, HPLMIX = 0x01,
HPRMIX = 0x02, IN_DIFF = 0
HP
Signal-to-Noise Ratio
SNR
SR
100
dB
Slew Rate
0.35
200
65
V/Fs
pF
Capacitive Drive
Crosstalk
C
L
HPL to HPR, HPR to HPL, f = 20Hz to 20kHz
dB
ANALOG_SWITCH
I
= 20mA, V
COM_
T
T
= +25NC
1.6
4
NC_
A
A
On-Resistance
R
ON
= 0V and PVDD,
SWEN = 1
I
= T
to T
5.2
MIN
MAX
10I in series with
each switch
V
V
= 2V
= PV /2,
DD
,
DIFCOM_
CMCOM_
P-P
0.05
0.3
Total Harmonic Distortion +
Noise
%
f = 1kHz, SWEN = 1,
= 8I + 68FH
No series resistors
Z
SPK
SWEN = 0, COM1 and COM2 to GND = 50I,
f = 10kHz, referred to signal applied to NC1
and NC2
Off-Isolation
105
dB
PREAMPLIFIER
PGAIN_ = 000
PGAIN_ = 001
PGAIN_ = 010
PGAIN_ = 011
PGAIN_ = 100
PGAIN_ = 101
PGAIN_ = 110
-6.5
-3.5
-0.5
2.5
-6
-3
0
-5.5
-2.5
0.5
Gain
3
3.5
dB
5.5
6
6.5
8.5
9
9.5
17.5
18
18.5
VOLUME_CONTROL
HP_VOL = 0x1F
HP_VOL = 0x00
SPKVOL = 0x3F
SPKVOL = 0x00
5.5
-68
19
6
6.5
-60
21
-64
20
Volume Level
dB
-31
-30
109
101
-29
Speaker
f = 1kHz
Mute Attenuation
dB
ms
Headphone
Zero-Crossing Detection
Timeout
100
LIMITER
Attack Time
1
ms
s
THDT1 = 0
THDT1 = 1
1.4
2.8
Release Time Constant
8
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
DIGITAL_I/O_CHARACTERISTICS
(V
LDOIN
= V
= V
= 3.7V, V
= V
= 0V. T = T
to T , unless otherwise noted. Typical values are at
MAX
PVDD
SHDN
GND
PGND
A
MIN
T
= +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL_INPUTS_(SDA,_SCL,_SHDN)
Input Voltage High
V
1.3
V
V
IH
Input Voltage Low
V
0.5
IL
Input Hysteresis
V
200
10
mV
pF
HYS
Input Capacitance
C
IN
T
= +25NC
Q1.0
Q1.0
A
Input Leakage Current
I
FA
IN
V
= 0, T = +25NC
A
LDOIN
DIGITAL_OUTPUTS_(SDA_Open_Drain)
Output Low Voltage
V
OL
I
= 3mA
0.4
V
SINK
2
I C_TIMING_CHARACTERISTICS
(V
LDOIN
= V
= V
= 3.7V, V
= V
= 0V. T = T
to T , unless otherwise noted. Typical values are at
MAX
PVDD
SHDN
GND
PGND
A
MIN
T
= +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
Fs
Fs
BUF
Hold Time (Repeated) START
Condition
t
t
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
Fs
SU,STA
HD,DAT
Data Hold Time
Data Setup Time
t
0
900
ns
ns
t
100
SU,DAT
SDA and SCL Receiving
Rise Time
20 +
t
(Note 4)
(Note 4)
(Note 4)
300
300
300
ns
ns
ns
R
0.1C
B
20 +
0.1C
SDA and SCL Receiving Fall Time
SDA Transmitting Fall Time
t
F
F
B
20 +
t
0.1C
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
Fs
pF
ns
SU,STO
C
B
400
50
Pulse Width of Suppressed Spike
t
0
SP
Note_1: 100% production tested at T = +25NC. Specifications overtemperature limits are guaranteed by design.
A
Note_2: Amplifier inputs are AC-coupled to GND.
Note_3: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load.
Note_4: C is in pF.
B
9
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
SP
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
HIGH
t
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 1. I C Interface Timing Diagram
Typical Operating Characteristics
= 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
(V
LDOIN
= V
= 3.7V, V
= V
PVDD
GND PGND
loads (Z
) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z = ∞, R = ∞.
SPK
HP SPK HP
C
= C
= C
= C
= 1μF. T = +25°C, unless otherwise noted.)
A
C1P-C1N
HPVDD
HPVSS BIAS
GENERAL
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
3.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
INPUTS AC-COUPLED TO GND
SOFTWARE
SPEAKER ONLY
INPUTS AC-COUPLED TO GND
INA CONNECTED TO OUTPUT
2.5
2.0
1.5
1.0
0.5
0
HARDWARE
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
10
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
= V = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
PGND
(V
LDOIN
= V
= 3.7V, V
PVDD
GND
loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z
SPK HP SPK
= ∞, R = ∞.
HP
C
= C
= C
HPVSS
= C
BIAS
= 1μF. T = +25°C, unless otherwise noted.)
A
C1P-C1N
HPVDD
SPEAKER_AMPLIFIER
THD+N vs. FREQUENCY
THD+N vs. FREQUENCY
THD+N vs. FREQUENCY
10
10
1
10
1
V
Z
= 3.7V
= 4I + 33µF
V
Z
= 3.7V
= 8I + 68µF
V
Z
= 3.7V
PVDD
PVDD
PVDD
SPRK
= 8I + 68µF
SPRK
SPRK
1
0.1
P
= 1000mW
OUT
P
= 500mW
OUT
0.1
0.1
SSM
P
= 200mW
P
= 200mW
OUT
OUT
0.01
0.001
0.01
0.001
0.01
0.001
FFM
0.01
0.1
1
10
100
0.01
0.1
1
10
100
2.5
3.0
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
THD+N vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
100
10
100
10
100
10
V
Z
= 5.0V
= 8I + 68µF
V
Z
= 5.0V
= 4I + 33µF
V
Z
= 4.2V
= 8I + 68µF
PVDD
SPRK
PVDD
SPRK
PVDD
SPRK
f
= 6kHz
f
= 6kHz
IN
f
= 6kHz
IN
IN
1
1
1
f
IN
= 1kHz
f = 1kHz
IN
f
= 1kHz
IN
0.1
0.1
0.1
f
= 100Hz
1.5
f
= 100Hz
IN
IN
0.01
0.001
0.01
0.001
0.01
0.001
f
= 100Hz
IN
0
0.5
1.0
2.0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
(mW)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(mW)
P
(mW)
P
P
OUT
OUT
OUT
THD+N vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
100
10
100
10
100
10
V
Z
= 4.2V
= 4I + 33µF
V
Z
= 3.7V
= 8I + 68µF
V
Z
= 3.7V
= 4I + 33µF
PVDD
SPRK
PVDD
SPRK
PVDD
SPRK
f
= 6kHz
f
= 6kHz
IN
f
IN
= 6kHz
IN
1
1
1
f = 1kHz
IN
f
= 1kHz
f
= 1kHz
IN
IN
0.1
0.1
0.1
f
= 100Hz
IN
0.01
0.001
0.01
0.001
0.01
0.001
f
IN
= 100Hz
1.5
f
= 100Hz
1.5
IN
0
0.5
1.0
2.0
2.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
(mW)
0
0.5
1.0
2.0
2.5
P
(mW)
P
P
(mW)
OUT
OUT
OUT
11
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
= V = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
PGND
(V
LDOIN
= V
= 3.7V, V
PVDD
GND
loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z
SPK HP SPK
= ∞, R = ∞.
HP
C
= C
= C
HPVSS
= C
BIAS
= 1μF. T = +25°C, unless otherwise noted.)
A
C1P-C1N
HPVDD
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY vs. OUTPUT POWER
OUTPUT POWER vs. SUPPLY VOLTAGE
100
100
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
Z
SPRK
= 8I + 68µF
Z
SPRK
= 8I + 68µF
f
= 1kHz
IN
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
Z
SPRK
= 4I + 33µF
Z
= 4I + 33µF
SPRK
Z
= 4I + 33µF
SPRK
THD+N = 10%
THD+N = 1%
V
= 5.0V
V
IN
= 3.7V
PVDD
f = 1kHz
PVDD
f
= 1kHz
IN
0
0.5
1.0
1.5
(W)
2.0
2.5
3.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
(W)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
P
P
OUT
SUPPLY VOLTAGE (V)
OUT
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
OUTPUT POWER vs. SUPPLY VOLTAGE
OUTPUT POWER vs. LOAD RESISTANCE
0
-20
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
= 3.7V
f
Z
= 1kHz
V
f
= 3.7V
= 1kHz
= LOAD + 68µF
PVDD
IN
PVDD
= 200mV
= 8I + 68µF
RIPPLE
P-P
SPRK
IN
INPUTS AC-COUPLED GND
Z
SPRK
THD+N = 10%
THD+N = 10%
-40
-60
THD+N = 1%
THD+N = 1%
-80
-100
0.01
0.1
1
10
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1
10
100
1000
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (I)
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE
IN-BAND OUTPUT SPECTRUM
IN-BAND OUTPUT SPECTRUM
0
-20
0
-20
0
-20
V
= 200mV
P-P
RIPPLE
FFM
= 1kHz
SSM
= 1kHz
f
= 1kHz
IN
f
f
IN
IN
INPUTS AC-COUPLED GND
-40
-40
-40
-60
-60
-60
-80
-80
-80
-100
-120
-100
-120
-100
0
5
10
15
20
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
5
10
15
20
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
12
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
= V = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
PGND
(V
LDOIN
= V
= 3.7V, V
PVDD
GND
loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z
SPK HP SPK
= ∞, R = ∞.
HP
C
= C
= C
HPVSS
= C = 1μF. T = +25°C, unless otherwise noted.)
BIAS A
C1P-C1N
HPVDD
WIDEBAND OUTPUT SPECTRUM
WIDEBAND OUTPUT SPECTRUM
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
RBW = 100Hz
SSM
RBW = 100Hz
FFM
-20
-40
-60
-80
-100
-120
0.1
1
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
SPEAKER VOLUME GAIN
vs. SPKVOL CODE
HARDWARE SHUTDOWN RESPONSE
MAX97000 toc24
30
20
SHDN
2V/div
10
0
-10
-20
-30
-40
SPKR
OUTPUT
500mV/div
0
10
20
30
40
50
60
70
1ms/div
SPKVOL CODE (NUMERIC)
SOFTWARE SHUTDOWN RESPONSE
SOFTWARE TURN-ON RESPONSE
MAX97000 toc25
MAX97000 toc26
SDA
SDA
2V/div
2V/div
SPKR
SPKR
OUTPUT
1V/div
OUTPUT
1V/div
400µs/div
4ms/div
13
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
= V = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
PGND
(V
LDOIN
= V
= 3.7V, V
PVDD
GND
loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z
SPK HP SPK
= ∞, R = ∞.
HP
C
= C
= C
= C
BIAS
= 1μF. T = +25°C, unless otherwise noted.)
A
C1P-C1N
HPVDD HPVSS
HEADPHONE_AMPLIFIER
THD+N vs. FREQUENCY
THD+N vs. OUTPUT POWER
THD+N vs. FREQUENCY
10
10
1
10
1
R
= 32I
LOAD
R
= 16I
R
= 32I
LOAD
LOAD
1
0.1
f
IN
= 1kHz
f
= 6kHz
IN
P
= 30mW
OUT
0.1
0.1
P
= 25mW
OUT
0.01
0.001
0.01
0.001
0.01
0.001
P
= 10mW
10
OUT
f
IN
= 100Hz
20
P
= 5mW
OUT
0.01
0.1
1
100
0
10
30
40
50
60
0.01
0.1
1
10
100
FREQUENCY (kHz)
OUTPUT POWER (mW)
FREQUENCY (kHz)
POWER DISSIPATION
vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
OUTPUT POWER vs. LOAD RESISTANCE
180
160
140
120
100
80
10
1
80
70
60
50
40
30
20
10
0
f = 1kHz
IN
f
P
= 1kHz
= P + P
HPL HPR
R
= 16I
IN
OUT
LOAD
THD+N = 10%
R
= 16I
f
IN
= 1kHz
LOAD
f
IN
= 6kHz
0.1
THD+N = 1%
R
= 32I
LOAD
60
0.01
0.001
40
f
IN
= 100Hz
20
0
0
10 20 30 40 50 60 70 80 90
OUTPUT POWER (mW)
0
10 20 30 40 50 60 70 80
OUTPUT POWER (mW)
1
10
100
1000
LOAD RESISTANCE (I)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
OUTPUT SPECTRUM
OUTPUT POWER vs. LOAD RESISTANCE
70
60
50
40
30
20
10
0
0
-20
0
-20
f
= 1kHz
IN
V
= 200mV
P-P
R
f
= 32I
= 1kHz
RIPPLE
LOAD
THD+N = 1%
INPUTS AC-COUPLED GND
IN
C
= 2.2µF
CHARGE_PUMP
-40
C
= 1µF
CHARGE_PUMP
-60
-40
-80
-60
-100
-120
-140
-160
C
= 0.47µF
-80
CHARGE_PUMP
-100
0
4
8
12
FREQUENCY (kHz)
16
20
24
1
10
100
1000
0.01
0.1
1
10
100
LOAD RESISTANCE (I)
FREQUENCY (kHz)
14
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued)
= V = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
PGND
(V
LDOIN
= V
= 3.7V, V
PVDD
GND
loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z
SPK HP SPK
= ∞, R = ∞.
HP
C
= C
= C
HPVSS
= C
BIAS
= 1μF. T = +25°C, unless otherwise noted.)
A
C1P-C1N
HPVDD
COMMON-MODE REJECTION RATIO
vs. FREQUENCY
OUTPUT SPECTRUM
CROSSTALK vs. FREQUENCY
0
-20
0
0
-10
-20
-30
-40
-50
-60
R
= 32I
R
= 16I
LOAD
R
= 16I
LOAD
LOAD
= 1kHz
f
IN
-20
-40
-40
PREGAIN = +9dB
-60
-80
-60
-100
-120
-140
-160
-80
HPL TO HPR
HPR TO HPL
PREGAIN = +18dB
-100
-120
PREGAIN = 0dB
10 100
0
4
8
12
16
20
24
0.01
0.1
1
10
100
0.01
0.1
1
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
HEADPHONE VOLUME GAIN
vs. HP_VOL CODE
HARDWARE SHUTDOWN RESPONSE
MAX97000 toc40
10
0
RIGHT AND LEFT
SHDN
2V/div
-10
-20
-30
-40
-50
-60
-70
HPL/HPR
500mV/div
0
5
10
15
20
25
30
35
1ms/div
HP_VOL CODE (NUMERIC)
SOFTWARE TURN-ON RESPONSE
SOFTWARE SHUTDOWN RESPONSE
MAX97000 toc42
MAX97000 toc41
SDA
SDA
2V/div
2V/div
HPL/HPR
HPL/HPR
500mV/div
500mV/div
4ms/div
1ms/div
15
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Typical Operating Characteristics (continued
= V = 0V. Single-ended inputs, preamp gain = 0dB, HPLVOL = HPRVOL = SPKVOL = 0dB. Speaker
PGND
(V
LDOIN
= V
= 3.7V, V
PVDD
GND
loads (Z ) connected between OUTP and OUTN. Headphone loads (R ) connected from HPL or HPR to GND. Z
SPK HP SPK
= ∞, R = ∞.
HP
C
= C
= C
HPVSS
= C
BIAS
= 1μF. T = +25°C, unless otherwise noted.)
A
C1P-C1N
HPVDD
ANALOG_SWITCH
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
CLASS H OPERATION
MAX97000 toc43
10
1
HPVDD
1V/div
R
= 32I
LOAD
EXTERNAL CLASS AB CONNECTED
DIRECTLY TO COM1 AND COMR
HPVDD
0V
HPL/HPR
200mV/div
0.1
f = 6kHz
f = 100kHz
HPVSS
0V
0.01
0.001
f = 100kHz
HPVSS
1V/div
0
5
10
15
20
25
30
10ms/div
OUTPUT POWER (mW)
BYPASS SWITCH OFF-ISOLATION
ON-RESISTANCE vs. V
COM
3.0
2.5
2.0
1.5
1.0
0.5
0
0
-20
I
= 20mA
NC
V
= 2.7V
PVDD
-40
V
= 3.7V
PVDD
-60
V
= 5.0V
PVDD
-80
-100
-120
-140
V
= 3.0V
PVDD
0
1
2
3
4
5
6
0.01
0.1
1
10
100
V
(V)
FREQUENCY (kHz)
COM
16
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
+
MAX97000
A
B
C
D
E
C1P
VDD
C1N
LDOIN
PGND
COM1
NC1
HPVDD
HPVSS
SCL
HPR
HPL
SDA
GND
PVDD
OUTN
OUTP
SHDN
INB1
BIAS
INB2
INA2
COM2
NC2
INA1
2.0mm x 2.0mm
Pin Description
BUMP
NAME
FUNCTION
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF capacitor between C1P and
C1N.
A1
C1P
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF capacitor between C1P and
C1N.
A2
C1N
A3
A4
A5
HPVDD
HPVSS
HPR
Headphone Amplifier Positive Power Supply. Bypass with a 1FF capacitor to PGND.
Headphone Amplifier Negative Power Supply. Bypass with a 1FF capacitor to PGND.
Headphone Amplifier Right Output
LDO Output and Headphone Amplifier Supply. Bypass with a 1FF and a 10FF capacitor to
GND. Power VDD or LDOIN. When powering VDD, leave LDOIN unconnected.
B1
B2
VDD
LDO Input. Generates VDD if no 1.8V power supply is available. Leave unconnected to disable.
Do not power VDD when powering LDOIN.
LDOIN
B3
B4
B5
C1
C2
C3
C4
C5
SDA
SCL
Serial Data Input/Output. Connect a pullup resistor from SDA to the I2C bus supply.
Serial-Clock Input. Connect a pullup resistor from SCL to the I2C bus supply.
Headphone Amplifier Left Output
HPL
PVDD
PGND
GND
Class D Power Supply. Bypass with a 1FF and a 10FF capacitor to PGND.
Class D Power Ground and Charge Pump Ground
Analog Ground.
Active-Low Shutdown
SHDN
BIAS
Common-Mode Bias. Bypass to GND with a 1FF capacitor.
17
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Pin Description (continued)
BUMP
D1
D2
D3
D4
D5
E1
NAME
OUTN
COM1
COM2
INB1
FUNCTION
Negative Speaker Output
Analog Switch 1 Input
Analog Switch 2 Input
Input B1. Left or negative input.
Input B2. Right or positive input.
Positive Speaker Output
INB2
OUTP
NC1
E2
Analog Switch 1 Output
E3
NC2
Analog Switch 2 Output
E4
INA1
Input A1. Left or negative input.
Input A2. Right or positive input.
E5
INA2
Internal Linear Regulator
The MAX97000 includes an internal regulator (LDOIN) to
generate VDD in cases where no 1.8V supply is available.
Using the regulator allows single-supply operation directly
from a Li+ battery. To enable the internal regulator apply
a power supply to LDOIN and do not connect power to
VDD. When not using the internal regulator, leave LDOIN
unconnected and power VDD from a 1.8V supply.
Detailed Description
The MAX97000 audio subsystem combines a mono
speaker amplifier with a stereo headphone amplifier
and an analog DPST switch. The high-efficiency 725mW
Class D speaker amplifier operates directly from the bat-
tery and consumes no more than 1FA when in shutdown
mode. The headphone amplifier utilizes a dual-mode
charge pump and a Class H output stage to maximize
efficiency while outputting a ground-referenced signal
that does not require output coupling capacitors. The
headphone and speaker amplifiers have independent
volume control and on/off control. The four inputs are
configurable as two differential inputs or four single-
ended inputs. All control is performed using the 2-wire,
I2C interface.
Signal Path
The MAX97000 signal path consists of flexible inputs,
signal mixing, volume control, and output amplifiers
(Figure 2). The inputs can be configured for single-
ended or differential signals (Figure 3). The internal
preamplifiers feature programmable gain settings using
internal resistors and an external gain setting using a
trimmed internal feedback resistor. The external option
allows any desired gain to be selected. Following pream-
plification, the input signals are mixed, volume adjusted,
and routed to the headphone and speaker amplifiers
based on the desired configuration.
The speaker amplifier incorporates a distortion limiter to
automatically reduce the volume level when excessive
clipping occurs. This allows high gain for low-level sig-
nals without compromising the quality of large signals.
INA2
INPUT A
-6dB TO +18dB
INA1
-64dB TO +6dB
-64dB TO +6dB
-30dB TO +20dB
0/3dB
0/3dB
+12dB
MIXER
AND
MUX
INB2
INPUT B
-6dB TO +18dB
INB1
Figure 2. Signal Path
18
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
STEREO SINGLE-ENDED
IN_2 (R)
R
TO MIXER
IN_1 (L)
L
DIFFERENTIAL
IN_2 (+)
IN_1 (-)
TO MIXER
Figure 3. Differential and Stereo Single-Ended Input Configurations
Mixers
The MAX97000 features independent mixers for the left
headphone, right headphone, and speaker paths. Each
output can select any combination of any inputs. This
allows for mixing two audio signals together and rout-
ing independent signals to the headphone and speaker
amplifiers. If one of the inputs is not selected by either
mixer, it is automatically powered down to save power.
Class D Speaker Amplifier
The MAX97000 Class D speaker amplifier utilizes active
emissions limiting and spread-spectrum modulation to
minimize the EMI radiated by the amplifier.
19
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters or shielding to meet EN55022B electromag-
netic-interference (EMI) regulation standards. Maxim’s
active emissions limiting edge-rate control circuitry and
spread-spectrum modulation reduces EMI emissions,
while maintaining up to 87% efficiency. Maxim’s spread-
spectrum modulation mode flattens wideband spectral
components, while proprietary techniques ensure that
the cycle-to-cycle variation of the switching period
does not degrade audio reproduction or efficiency.
The MAX97000’s spread-spectrum modulator randomly
varies the switching frequency by Q20kHz around the
center frequency (250kHz). Above 10MHz, the wide-
band spectrum looks like noise for EMI purposes (see
Figure 4).
40
30
20
10
0
-10
30
60
80
100 120 140 160 180 200 220 240 260 280 300
FREQUENCY (MHz)
40
30
20
10
0
-10
300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
FREQUENCY (MHz)
Figure 4. EMI with 15cm of Speaker Cable
20
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Distortion Limiter
The MAX97000 speaker amplifiers integrate a limiter
to provide speaker protection and audio compression.
When enabled, the limiter monitors the audio signal at
the output of the Class D speaker amplifier and decreas-
es the gain if the distortion exceeds the predefined
threshold. The limiter automatically tracks the battery
voltage to reduce the gain as the battery voltage drops.
Headphone Amplifier
DirectDrive
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dis-
sipation and possible damage to both headphone and
headphone amplifier.
Maxim’s DirectDrive® architecture uses a charge
pump to create an internal negative supply voltage.
This allows the headphone outputs of the MAX97000
to be biased at GND while operating from a single
supply (Figure 6). Without a DC component, there is
no need for the large DC-blocking capacitors. Instead
of two large (220FF, typ) capacitors, the MAX97000
charge pump requires three small ceramic capacitors,
Figure 5 shows the typical output vs. input curves with
and without the distortion limiter. The dotted line shows
the maximum gain for a given distortion limit without
the distortion limiter. The solid line shows how, with the
distortion limiter enabled, the gain can be increased
without exceeding the set distortion limit. When the
limiter is enabled, selecting a high gain level results in
peak signals being attenuated while low signals are left
unchanged. This increases the perceived loudness with-
out the harshness of a clipped waveform.
Analog Switch
The MAX97000 integrates a DPST analog audio switch.
This switch can be used to disconnect an independent
audio signal, or drive the 8I speaker by connecting
NC1 and NC2 to OUTN and OUTP, respectively. Unlike
discrete solutions, the switch design reduces coupling
of Class D switching noise to the COM_ inputs. This
eliminates the need for a costly T-switch. Drive COM1
and COM2 with a low-impedance source to minimize
noise on the pins. In applications that do not require
the analog switch, leave COM1, COM2, NC1, and NC2
unconnected.
V
DD
V
/ 2
DD
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
+V
DD
V
OUT
MAXIMUM THD+N
LEVEL
SGND
-V
DD
V
IN
DirectDrive AMPLIFIER BIASING SCHEME
Figure 6. Traditional Amplifier Output vs. MAX97000
DirectDrive Output
Figure 5. Limiter Gain Curve
DirectDrive is a registered trademark of Maxim Integrated Products, Inc.
21
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
conserving board space, reducing cost, and improving
the frequency response of the headphone amplifier.
See the Output Power vs. Load Resistance graph in
the Typical Operating Characteristics for details of the
possible capacitor sizes. There is a low DC voltage on
the amplifier outputs due to amplifier offset. However,
the offset of the MAX97000 is typically Q0.15mV, which,
when combined with a 32I load, results in less than 5FA
of DC current flow to the headphones.
To prevent audible gliches when transitioning from the
Q(VDD/2) output mode to the QVDD output mode, the
charge pump transitions very quickly. This quick change
draws significant current from VDD for the duration of
the transition. The bypass capacitor on VDD supplies the
required current and prevents droop on VDD.
The charge pump’s dynamic switching mode can be
turned off through the I2C interface. The charge pump
can then be forced to output either Q(VDD/2) or QVDD
regardless of input signal level.
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the ampli-
fier’s low-frequency response and can distort the audio
signal. Previous attempts at eliminating the output-cou-
pling capacitors involved biasing the headphone return
(sleeve) to the DC bias voltage of the headphone ampli-
fiers. This method raises some issues:
Class H Operation
A Class H amplifier uses a Class AB output stage with
power supplies that are modulated by the output signal.
In the case of the MAX97000, two nominal power-supply
differentials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V
to -1.8V) are available from the charge pump. Figure 7
shows the operation of the output-voltage-dependent
power supply.
•
•
•
The sleeve is typically grounded to the chassis.
Using the midrail biasing approach, the sleeve must
be isolated from system ground, complicating prod-
uct design.
Low-Power Mode
To minimize power consumption when using the head-
phone amplifier, enable the low-power mode. In this
mode, the headphone mixers and volume control are
bypassed and shut down.
During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the ampli-
fier must be able to withstand the full energy from an
ESD strike.
I2C Slave Address
The MAX97000 uses a slave address of 0x9A or
1001101RW. The address is defined as the 7 most
significant bits (MSBs) followed by the read/write bit.
Set the read/write bit to 1 to configure the MAX97000 to
read mode. Set the read/write bit to 0 to configure the
MAX97000 to write mode. The address is the first byte
of information sent to the MAX97000 after the START (S)
condition.
When using the headphone jack as a line out to
other equipment, the bias voltage on the sleeve may
conflict with the ground potential from other equip-
ment, resulting in possible damage to the amplifiers.
Charge Pump
The MAX97000’s dual-mode charge pump generates
both the positive and negative power supply for the
headphone amplifier. To maximize efficiency, both the
charge pump’s switching frequency and output voltage
change based on signal level.
When the input signal level is less than 10% of VDD,
the switching frequency is reduced to a low rate. This
minimizes switching losses in the charge pump. When
the input signal exceeds 10% of VDD, the switching fre-
quency increases to support the load current.
1.8V
32ms
HPVDD
0.9V
V
TH_H
For input signals below 25% of VDD, the charge pump
generates Q(VDD/2) to minimize the voltage drop across
the amplifier’s power stage and thus improve efficiency.
Input signals that exceed 25% of VDD cause the charge
pump to output QVDD. The higher output voltage allows
for full output power from the headphone amplifier.
OUTPUT
VOLTAGE
V
TH_L
-0.9V
HPVSS
32ms
-1.8V
Figure 7. Class H Operation
22
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
I2C Registers
Nine internal registers program the MAX97000. Table
1 lists all the registers, their addresses, and power-on-
reset states. Register 0xFF indicates the device revision.
Write zeros to all unused bits in the register table when
updating the register, unless otherwise noted. Tables 2
through 7 describe each bit.
Table_1._Register_Map
REGISTER
B7
INADIFF INBDIFF
HPLMIX
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W
STATUS
Input Gain
PGAINA
PGAINB
0x00
0x01
0x02
0x03
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
Headphone
Mixers
HPRMIX
SPKMIX
Speaker Mixer
0
0
0
0
Headphone
Left
HPLM
HPRM
HPLVOL
HPRVOL
ZCD
SLEW
Headphone
Right
LPGAIN
0
0x04
0x00
R/W
Speaker
Reserved
Limiter
FFM
0
SPKM
0
SPKVOL
0x05
0x06
0x07
0x00
0x00
0x00
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
THDCLP
THDT1
Power
Management
LPMODE
SPKEN
0
0
0
HPLEN
0
HPREN
CPSEL
SWEN
FIXED
0x08
0x09
0x01
0x00
R/W
R/W
SHDN
Charge Pump
REVISION_ID
Rev ID
0
0
0
REV
0xFF
0x00
R
Table_2._Input_Register
REGISTER
BIT
NAME
DESCRIPTION
Input_A_Differential_Mode. Configures the input A channel as either a mono differential
signal (INA = INA2 - INA1) or as a stereo signal (INA1 = left, INA2 = right).
0 = Stereo single-ended
7
INADIFF
1 = Differential
Input_B_Differential_Mode. Configures the input B channel as either a mono differential
signal (INB = INB2 - INB1) or as a stereo signal (INB1 = left, INB2 = right).
0 = Stereo single-ended
6
5
4
INBDIFF
1 = Differential
Input_A_Preamp_Gain. Set the input gain to maximize output signal level for a given input
signal range to improve the SNR of the system. PGAINA = 111 switches to a trimmed 20kI
feedback resistor for external gain setting.
0x00
___VALUE _LEVEL_(dB)
000 -6
001 -3
PGAINA
010
011
100
101
0
3
6
9
3
110 18
111 External
23
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Table_2._Input_Register_(continued)
REGISTER
BIT
NAME
DESCRIPTION
Input_B_Preamp_Gain. Set the input gain to maximize output signal level for a given input
signal range to improve the SNR of the system. PGAINB = 111 switches to a trimmed 20kI
feedback resistor for external gain setting.
2
__VALUE LEVEL_(dB)
000 -6
1
0
001 -3
PGAINB
010
011
100
101
0
3
6
9
110 18
111 External
Mixers
Table_3._Mixer_Registers
REGISTER
BIT
NAME
DESCRIPTION
7
Left_Headphone_Mixer. Selects which of the four inputs is routed to the left headphone output.
____VALUE_ _INPUT
6
5
4
3
2
1
0
3
2
1
0
0000 No input
HPLMIX
xxx1 INA1 (Disabled when INADIFF = 1)
xx1x INA2 (Select when INADIFF = 1)
x1xx INB1 (Disabled when INBDIFF = 1)
1xxx INB2 (Select when INBDIFF = 1)
0x01
Right_Headphone_Mixer. Selects which of the four inputs is routed to the right headphone output.
___VALUE _INPUT
0000 No input
HPRMIX
xxx1 INA1 (Disabled when INADIFF = 1)
xx1x INA2 (Select when INADIFF = 1)
x1xx INB1 (Disabled when INBDIFF = 1)
1xxx INB2 (Select when INBDIFF = 1)
Speaker_Mixer. Selects which of the four inputs is routed to the speaker output.
___VALUE _INPUT
0000 No input
0x02
SPKMIX
xxx1 INA1 (Disabled when INADIFF = 1)
xx1x INA2 (Select when INADIFF = 1)
x1xx INB1 (Disabled when INBDIFF = 1)
1xxx INB2 (Select when INBDIFF = 1)
24
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Volume Control
Table_4._Volume_Control_Registers
REGISTER
BIT
NAME
DESCRIPTION
Zero-Crossing_Detection. Determines whether zero-crossing detection is used on all
volume control changes to reduce clicks and pops. Disabling zero-crossing detection
7
allows volume changes to occur immediately.
ZCD
0 = Enabled
1 = Disabled
Volume_Slewing._Determines whether volume slewing is used on all volume control
changes to reduce clicks and pops. When enabled, volume changes cause the
MAX97000 to ramp through intermediate volume settings whenever a change to the
volume is made. If ZCD = 1, slewing occurs at a rate of 0.2ms per step. If ZCD = 0, slew
time depends on the input signal. Write a 1 to this bit to disable slewing and implement
volume changes immediately. This bit also activates soft-start at power-on and soft-stop
and power-off.
6
SLEW
0 = Enabled
1 = Disabled
Left_Headphone_Mute
0 = Unmuted
1 = Muted
5
4
HPLM
0x03
Left_Headphone_Volume
____VALUE LEVEL_(dB)
0x00 -64
0x01 -60
0x02 -56
0x03 -52
0x04 -48
0x05 -44
0x06 -40
0x07 -37
0x08 -34
0x09 -31
0x0A -28
0x0B -25
0x0C -22
0x0D -19
0x0E -16
0x0F -14
VALUE LEVEL_(dB)
0x10 -12
0x11 -10
0x12 -8
3
2
1
0
0x13 -6
0x14 -4
0x15 -2
0x16 -1
HPLVOL
0x17
0x18
0x19
0x1A
0x1B
0
1
2
3
4
0x1C 4.5
0x1D
0x1E 5.5
0x1F
5
6
25
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Table_4._Volume_Control_Registers_(continued)
REGISTER
BIT
NAME
DESCRIPTION
Low-Power_Mode_Gain. Controls the headphone amplifier gain when LPMODE ≠ 0.
7
LPGAIN
0 = 0dB
1 = 3dB
Right_Headphone_Mute
0 = Unmuted
1 = Muted
5
4
HPRM
Right_Headphone_Volume
VALUE LEVEL_(dB)
0x00 -64
0x01 -60
0x02 -56
0x03 -52
0x04 -48
0x05 -44
0x06 -40
0x07 -37
0x08 -34
0x09 -31
0x0A -28
0x0B -25
0x0C -22
0x0D -19
0x0E -16
0x0F -14
VALUE LEVEL_(dB)
0x10 -12
0x11 -10
0x12 -8
3
2
1
0
0x04
0x13 -6
0x14 -4
0x15 -2
HPRVOL
-1
0
1
2
3
4
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C 4.5
0x1D
0x1E 5.5
0x1F
5
6
Fixed-Frequency_Oscillation. Removes spread spectrum from the class D oscillator.
0 = Spread-spectrum mode
1 = Fixed-frequency mode
7
6
FFM
Speaker_Mute
0 = Unmuted
1 = Mute
SPKM
Speaker_Volume
5
4
VALUE LEVEL_(dB)
0x00–0x18 -30
0x19 -26
VALUE LEVEL_(dB)
VALUE LEVEL_(dB)
0x34 14.5
0x35 15
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
3
4
5
6
7
8
9
0x05
0x1A -22
0x36 15.5
0x37 16
0x38 16.5
0x39 17
0x3A 17.5
0x3B 18
0x3C 18.5
0x3D 19
0x1B -18
3
2
1
0
0x1C -14
0x1D -12
0x1E -10
0x1F -8
0x20 -6
SPKVOL
0x2D 10
0x2E 11
0x2F 12
0x30 12.5
0x31 13
0x32 13.5
0x33 14
0x21 -4
0x22 -2
0x3E 19.5
0x3F 20
0x23
0x24
0x25
0
1
2
26
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Distortion Limiter
Table_5._Distortion_Limiter_Register
REGISTER
BIT
NAME
DESCRIPTION
7
Distortion_Limit
VALUE THD_LIMIT_(%)
0000 Disabled
0001–1001 P 4
6
THDCLP
1010 P 5
1011 P 6
1100 P 8
1101 P 11
1110 P 12
1111 P 15
0x07
5
4
Distortion_Release_Time_Constant
0
THDT1
0 = 1.4s
1 = 2.8s
Power Management
Table_6._Power_Management_Register
REGISTER
BIT
NAME
DESCRIPTION
Software_Shutdown
0 = Device disabled
1 = Device enabled
7
SHDN
Low-Power_Headphone_Mode. Enables low-power headphone mode. When activated
this mode directly connects the selected channel to the headphone amplifiers,
bypassing the mixers and the volume control. Additionally, low-power mode disables the
speaker path.
6
5
LPMODE
VALUE INPUT
00 Disabled
01 INA (SE) Connected to the headphone output
10 INB (SE) Connected to the headphone output
11 INA (Diff) to HPL and INB (Diff) to HPR
0x08
Speaker_Amplifier_Enable
0 = Disabled
1 = Enabled
4
2
1
0
SPKEN
HPLEN
HPREN
SWEN
Left_Headphone_Amplifier_Enable
0 = Disabled
1 = Enabled
Right_Headphone_Amplifier_Enable
0 = Disabled
1 = Enabled
Analog_Switch
0 = Open
1 = Closed
27
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Charge-Pump Control
Table_7._Charge-Pump_Control_Register
REGISTER
BIT
NAME
DESCRIPTION
Charge-Pump_Output_Select. Works with the FIXED to set Q1.8V or Q0.9V outputs on
HPVDD and HPVSS. Ignored when FIXED = 0.
0 = Q1.8V on HPVDD/HPVSS
1
CPSEL
1 = Q0.9V on HPVDD/HPVSS
0x09
Class_H_Mode. When enabled, this bit forces the charge pump to generate static power
rails for HPVDD and HPVSS, instead of dynamically adjusting them based on output
0
FIXED
signal level.
0 = Class H mode
1 = Fixed-supply mode
I2C Serial Interface
S
Sr
P
The MAX97000 features an I2C/SMBusK-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL
facilitate communication between the MAX97000 and the
master at clock rates up to 400kHz. Figure 1 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX97000 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) condi-
tion and a STOP (P) condition. Each word transmitted
to the MAX97000 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX97000 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX97000
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a START
or REPEATED START condition, a not acknowledge, and
a STOP condition. SDA operates as both an input and an
open-drain output. A pullup resistor, typically greater than
500I, is required on SDA. SCL operates only as an input.
A pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if
the single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
resistors protect the digital inputs of the MAX97000 from
high-voltage spikes on the bus lines, and minimize cross-
talk and undershoot of the bus signals.
SCL
SDA
Figure 8. START, STOP, and REPEATED START Conditions
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 8). A START
condition from the master signals the beginning of a
transmission to the MAX97000. The master terminates
transmission and frees the bus by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
Early STOP Conditions
The MAX97000 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the read/write bit. For the
MAX97000 the seven most significant bits are 1001101.
Setting the read/write bit to 1 (slave address = 0x9B) con-
figures the MAX97000 for read mode. Setting the read/write
bit to 0 (slave address = 0x9A) configures the MAX97000
for write mode. The address is the first byte of information
sent to the MAX97000 after the START condition.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
SMBus is a trademark of Intel Corp.
28
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that
the MAX97000 uses to handshake receipt each byte
of data when in write mode (Figure 9). The MAX97000
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master will retry communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX97000 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not-acknowledge is
sent when the master reads the final byte of data from
the MAX97000, followed by a STOP condition.
Write Data Format
A write to the MAX97000 includes transmission of a
START condition, the slave address with the R//W bit
set to 0, 1 byte of data to configure the internal register
address pointer, 1 or more bytes of data, and a STOP
condition. Figure 10 illustrates the proper frame format
for writing 1 byte of data to the MAX97000. Figure 11
illustrates the frame format for writing n-bytes of data to
the MAX97000.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
28
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 9. Acknowledge
ACKNOWLEDGE FROM MAX97000
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX97000
ACKNOWLEDGE FROM MAX97000
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Writing 1 Byte of Data to the MAX97000
ACKNOWLEDGE FROM MAX97000
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX97000
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX97000
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX97000
REGISTER ADDRESS
S
0
A
A
A
DATA BYTE 1
1 BYTE
DATA BYTE n
1 BYTE
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 11. Writing n-Bytes of Data to the MAX97000
29
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
The slave address with the R/W bit set to 0 indicates that
the master intends to write data to the MAX97000. The
MAX97000 acknowledges receipt of the address byte
during the master-generated 9th SCL pulse.
The first byte transmitted from the MAX97000 are the
contents of register 0x00. Transmitted data is valid on
the rising edge of SCL. The address pointer autoincre-
ments after each read data byte. This autoincrement
feature allows all registers to be read sequentially within
one continuous frame. A STOP condition can be issued
after any number of read data bytes. If a STOP condition
is issued followed by another read operation, the first
data byte to be read is from register 0x00.
The second byte transmitted from the master configures
the MAX97000’s internal register address pointer. The
pointer tells the MAX97000 where to write the next byte
of data. An acknowledge pulse is sent by the MAX97000
upon receipt of the address pointer data.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX97000’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX97000 then transmits the contents of the
specified register. The address pointer autoincrements
after transmitting the first byte.
The third byte sent to the MAX97000 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX97000 signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This
autoincrement feature allows a master to write to sequen-
tial registers within one continuous frame. The master
signals the end of transmission by issuing a STOP condi-
tion. Register addresses greater than 0x09 are reserved.
Do not write to these addresses.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowl-
edge from the master and then a STOP condition. Figure
12 illustrates the frame format for reading 1 byte from
the MAX97000. Figure 13 illustrates the frame format for
reading multiple bytes from the MAX97000.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The MAX97000 acknowledges receipt
of its slave address by pulling SDA low during the 9th
SCL clock pulse. A START command followed by a read
command resets the address pointer to register 0x00.
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX97000
ACKNOWLEDGE FROM MAX97000
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX97000
REGISTER ADDRESS
A
P
S
0
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Reading 1 Byte of Data from the MAX97000
ACKNOWLEDGE FROM MAX97000
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX97000
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX97000
Sr SLAVE ADDRESS
A
P
S
0
A
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 13. Reading n-Bytes of Data from the MAX97000
30
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Additional RF immunity can also be obtained from rely-
ing on the self-resonant frequency of capacitors as
Applications Information
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filters add cost, increase the solution size of the
amplifier, and can decrease efficiency and THD+N
performance. The traditional PWM scheme uses large
it exhibits the frequency response similar to a notch
filter. Depending on the manufacturer, 10pF to 20pF
capacitors typically exhibit self-resonance at RF frequen-
cies. These capacitors when placed at the input pins
can effectively shunt the RF noise at the inputs of the
MAX97000. For these capacitors to be effective, they
must have a low-impedance, low-inductance path to the
ground plane. Do not use microvias to connect to the
ground plane as these vias do not conduct well at RF
frequencies.
differential output swings (2 x V
peak-to-peak) and
DD
causes large ripple currents. Any parasitic resistance in
the filter components results in a loss of power, lowering
the efficiency.
The MAX97000 does not require an output filter. The
device relies on the inherent inductance of the speaker
coil and the natural filtering of both the speaker and
the human ear to recover the audio component of the
square-wave output. Eliminating the output filter results
in a smaller, less costly, more efficient solution.
Component Selection
Optional Ferrite Bead Filter
Additional EMI suppression can be achieved using a
filter constructed from a ferrite bead and a capacitor to
ground (Figure 14). Use a ferrite bead with low DC resis-
tance, high-frequency (> 600MHz) impedance between
100I and 600I, and rated for at least 1A. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
Because the frequency of the MAX97000 output is well
beyond the bandwidth of most speakers, voice coil
movement due to the square-wave frequency is very
small. Although this movement is small, a speaker not
designed to handle the additional power can be dam-
aged. For optimum results, use a speaker with a series
inductance > 10FH. Typical 8I speakers exhibit series
inductances in the 20FH to 100FH range.
Input Capacitor
An input capacitor, C , in conjunction with the input
IN
impedance of the MAX97000 line inputs forms a high-
pass filter that removes the DC bias from an incoming
analog signal. The AC-coupling capacitor allows the
amplifier to automatically bias the signal to an optimum
DC level. Assuming zero-source impedance, the -3dB
point of the highpass filter is given by:
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its har-
monics that is easily demodulated by audio amplifiers.
The MAX97000 is designed specifically to reject RF
signals; however, PCB layout has a large impact on the
susceptibility of the end product.
1
f
=
−3dB
2πR C
IN IN
Choose C such that f
is well below the lowest fre-
IN
-3dB
In RF applications, improvements to both layout and
component selection decrease the MAX97000’s suscep-
tibility to RF noise and prevent RF signals from being
demodulated into audible noise. Trace lengths should be
kept below 1/4 of the wavelength of the RF frequency of
interest. Minimizing the trace lengths prevents them from
functioning as antennas and coupling RF signals into the
MAX97000. The wavelength (l) in meters is given by: l
= c/f where c = 3 x 108 m/s, and f = the RF frequency
of interest.
quency of interest. For best audio quality, use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with high-
voltage coefficients, such as ceramics, may result in
increased distortion at low frequencies.
OUTP
MAX97000
OUTN
Route audio signals on middle layers of the PCB to allow
ground planes above and below shield them from RF
interference. Ideally the top and bottom layers of the
PCB should primarily be ground planes to create effec-
tive shielding.
Figure 14. Optional Class D Ferrite Bead Filter
31
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mI for optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surface-
mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
Bypass PVDD to PGND with as little trace length as pos-
sible. Connect OUTP and OUTN to the speaker using
the shortest and widest traces possible. Reducing trace
length minimizes radiated EMI. Route OUTP/OUTN as
a differential pair on the PCB to minimize the loop area
and thereby the inductance of the circuit. If filter compo-
nents are used on the speaker outputs, be sure to locate
them as close to the MAX97000 as possible to ensure
maximum effectiveness. Minimize the trace length from
any ground tied passive components to PGND to further
minimize radiated EMI.
Charge-Pump Flying Capacitor
The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the
charge pump. A value that is too small degrades the
device’s ability to provide sufficient current drive, which
leads to a loss of output voltage. Increasing the value
of the flying capacitor reduces the charge-pump output
resistance to an extent. Above 1FF, the on-resistance
of the internal switches and the ESR of external charge-
pump capacitors dominate.
An evaluation kit (EV kit) is available to provide an
example layout for the MAX97000. The EV kit allows
quick setup of the MAX97000 and includes easy-to-use
software allowing all internal registers to be controlled.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profile, as well as the latest information on reliability
testing results, refer to the Application Note: UCSP - A
Wafer-Level Chip-Scale Package on Maxim’s website at
www.maxim-ic.com/ucsp. See Figure 15 for the recom-
mended PCB footprint for the MAX97000.
Charge-Pump Holding Capacitor
The holding capacitor (bypassing HPVDD and HPVSS)
value and ESR directly affect the ripple on the supply.
Increasing the capacitor’s value reduces output ripple.
Likewise, decreasing the ESR reduces both ripple and
output resistance. Lower capacitance values can be used
in systems with low maximum output power levels. See the
Output Power vs. Load Resistance graph in the Typical
Operating Characteristics section for more information.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. Use a large continuous ground plane on
a dedicated layer of the PCB to minimize loop areas.
Connect GND and PGND directly to the ground plane
using the shortest trace length possible. Proper ground-
ing improves audio performance, minimizes crosstalk
between channels, and prevents any digital noise from
coupling into the analog audio signals.
0.24mm
Place the capacitor between C1P and C1N as close
as possible to the MAX97000 to minimize trace length
from C1P to C1N. Inductance and resistance added
between C1P and C1N reduce the output power of
the headphone amplifier. Bypass HPVDD and HPVSS
with capacitors located close to the pins with a short
trace length to PGND. Close decoupling of HPVDD and
HPVSS minimizes supply ripple and maximizes output
power from the headphone amplifier.
0.21mm
Figure 15. Recommended PCB Footprint
32
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages._Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE_TYPE
PACKAGE_CODE
DOCUMENT_NO.
21-0453
25 WLP
W252F2+1
33
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifier
Revision History
REVISION
NUMBER
REVISION_
DATE
PAGES_
CHANGED
DESCRIPTION
0
1
11/09
6/10
Initial release
Updated to show the device allows VDD to be externally supplied
—
1, 4, 5, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
34_____________________ ________ Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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