MAX98088_V01 [MAXIM]
Stereo Audio Codec with FlexSound Technology;
| 型号： | MAX98088_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Stereo Audio Codec with FlexSound Technology |
| 文件： | 总123页 (文件大小：12027K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5335; Rev 1; 6/11
E V A L U A T I O N K I T A V A I L A B L E
General Description
Features
S 5.6mW Power Comsumption (DAC to HP at 97dB DR)
The MAX98088 is a full-featured audio codec whose high
performance and low power consumption make it ideal
for portable applications.
S 101dB DR Stereo DAC (8kHz < f < 96kHz)
S
S 93dB DR Stereo ADC (8kHz < f < 96kHz)
S
Class D speaker amplifiers provide efficient amplification
for two speakers. Low radiated emissions enable com-
pletely filterless operation. Integrated bypass switches
optionally connect an external amplifier to the transducer
when the Class D amplifiers are disabled.
S Stereo Low EMI Class D Amplifiers
950mW/Channel (8I, V
= 4.2V)
SPKVDD�
S Efficient Class H Headphone Amplifier
S Differential Receiver Amplifier/Stereo Line Outputs
S 2 Stereo Single-Ended/Mono Differential Line
The IC features a stereo Class H headphone amplifier
that utilizes a dual-mode charge pump to maximize effi-
ciency while outputting a ground referenced signal that
does not require output coupling capacitors.
Inputs
S 3 Differential Microphone Inputs
S FlexSound Technology
5-Band Parametric EQ
Automatic Level Control (ALC)
Excursion Limiter
The IC also features a mono differential amplifier that can
also be configured as a stereo line output.
Speaker Power Limiter
Speaker Distortion Limiter
Microphone Automatic Gain Control
and Noise Gate
Two differential analog microphone inputs are available as
well as support for two PDM digital microphones. Integrated
switches allow for an additional microphone input as well
as microphone signals to be routed out to external devices.
Two flexible single-ended or differential line inputs may be
connected to an FM radio or other sources.
S Dual I2S/PCM/TDM Digital Audio Interfaces
S Asynchronous Digital Mixing
S Supports Master Clock Frequencies from 10MHz
to 60MHz
Integrated FlexSoundKtechnology improves loudspeak-
er performance by optimizing the signal level and fre-
quency response while limiting the maximum distortion
and power at the output to prevent speaker damage.
Automatic gain control (AGC) and a noise gate optimize
the signal level of microphone input signals to make best
use of the ADC dynamic range.
S RF Immune Analog Inputs and Outputs
S Extensive Click-and-Pop Reduction Circuitry
S Available in 63-Bump WLP Package (3.80mm x
3.30mm, 0.4mm Pitch)
Ordering Information appears at end of data sheet.
The device is fully specified over the -40NC to +85NC
extended temperature range.
For related parts and recommended products to use with this part,
refer to www.maxim-ic.com/MAX98088.related.
FlexSound is a trademark of Maxim Integrated Products, Inc.
Simplified Block Diagram
2
2
I
2
I S/PCM
I
C
S/PCM
RECEIVER/LINEOUT AMPS
DIGITAL
AUDIO
DIGITAL
AUDIO
CONTROL
INTERFACE
INTERFACE
DIGITAL MICROPHONE
INPUT
FlexSound TECHNOLOGY
• 5-BAND PARAMETRIC EQ
• AUTOMATIC LEVEL CONTROL
• LOUDSPEAKER PROCESSING
• EXCURSION LIMITER
• THD LIMITER
• POWER LIMITER
• MICROPHONE PROCESSING
• AUTOMATIC GAIN CONTROL
• NOISE GATE
ADC
ADC
SPEAKER AMP
SPEAKER AMP
HEADPHONE AMP
DAC
DAC
MIX
LINEIN A1
MIX
• ASYNCHRONOUS DIGITAL MIXING
LINEIN A2
LINEIN B1
+
+
MAX98088
LINEIN B2
HEADPHONE AMP
����������������������������������������������������������������� Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX98088
Stereo Audio Codec
with FlexSound Technology
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Digital Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Audio Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Digital Microphone Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
I C Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Microphone to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Line to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Line-In Pin Direct to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DAC to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Line to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DAC to Line Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Line to Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
DAC to Speaker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Line to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
DAC to Headphone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Line to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Speaker Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2
I C Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Line Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
ADC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
����������������������������������������������������������������� Maxim Integrated Products
2
MAX98088
Stereo Audio Codec
with FlexSound Technology
TABLE OF CONTENTS (continued)
Record Path Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Microphone AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
ADC Record Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Digital Audio Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Sample Rate Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Passband Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Playback Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Automatic Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Parametric Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Playback Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
DAC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Receiver Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Receiver Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Speaker Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Speaker Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Speaker Amplifier Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Excursion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Speaker Output Volume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Power Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DirectDrive Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Class H Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Headphone Output Mixers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Headphone Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Output Bypass Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Click-and-Pop Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Jack Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Jack Detection and Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
����������������������������������������������������������������� Maxim Integrated Products
3
MAX98088
Stereo Audio Codec
with FlexSound Technology
TABLE OF CONTENTS (CONTINUED)
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Early STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Device Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Typical Operating Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Startup/Shutdown Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Recommended PCB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
WLP Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
����������������������������������������������������������������� Maxim Integrated Products
4
MAX98088
Stereo Audio Codec
with FlexSound Technology
Functional Diagram
S D I N 2
S D O U T 2
L R C L K 2
B C L K 2
S D I N 1
S D O U T 1
L R C L K 1
B C L K 1
����������������������������������������������������������������� Maxim Integrated Products
5
MAX98088
Stereo Audio Codec
with FlexSound Technology
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.)
REG, INA1/EXTMICP, INA2/EXTMICN, INB1,
DVDD, AVDD, PVDD, HPVDD..............................-0.3V to +2.2V
SPKLVDD, SPKRVDD, DVDDS1, DVDDS2..........-0.3V to +6.0V
DGND, HPGND, SPKLGND, SPKRGND..............-0.1V to +0.1V
HPVSS ...............................(HPGND - 2.2V) to (HPGND + 0.3V)
C1N .................................... (HPVSS - 0.3V) to (HPGND + 0.3V)
C1P.....................................(HPGND - 0.3V) to (HPVDD + 0.3V)
REF, MICBIAS .................................-0.3V to (SPKLVDD + 0.3V)
MCLK, SDINS1, SDINS2, JACKSNS,
INB2, MIC1P/DIGMICDATA, MIC1N/DIGMICCLK,
MIC2P, MIC2N..................................................-0.3V to +2.2V
HPSNS...............................(HPGND - 0.3V) to (HPGND + 0.3V)
HPL, HPR ............................(HPVSS - 0.3V) to (HPVDD + 0.3V)
RECP/LOUTL/RXINP, RECN/LOUTR/
RXINN.....................(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKLP, SPKLN...........(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKRP, SPKRN .........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V)
SDA, SCL, IRQ .................................................-0.3V to +6.0V
LRCLKS1, BCLKS1, SDOUTS1.........-0.3V to (DVDDS1 + 0.3V)
LRCLKS2, BCLKS2, SDOUTS2.........-0.3V to (DVDDS2 + 0.3V)
Continuous Power Dissipation (T = +70NC)
A
63-Bump WLP (derate 25.6mW/NC above +70NC)........2.05W
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
V
V
V
, V
2.8
5.5
SPKLVDD SPKRVDD
Supply Voltage Range
Guaranteed by PSRR
, V
, V
1.65
1.65
1.8
2
3.6
8
V
DVDD AVDD PVDD
, V
DVDDS1 DVDDS2
Analog
Speaker
Digital
4.5
1.6
1.3
1.9
Full-duplex 8kHz mono,
receiver output, MAS = 1
2.3
2
Analog
Speaker
Digital
3
DAC playback 48kHz
stereo, headphone
outputs, MAS = 1
Total Supply Current
(Notes 2 and 3)
I
0.001 0.0058
mA
VDD
2.47
3.6
6.41
2.49
0.2
0.01
1
3.5
6.5
8.5
3.5
2
Analog
DAC playback 48kHz
stereo, speaker outputs, Speaker
MAS = 1
Digital
Analog
Speaker
Digital
Shutdown Supply Current
(Note 2)
T
= +25NC
1
FA
A
5
REF Voltage
REG Voltage
2.5
0.79
30
V
V
VSEN = 0
VSEN = 1
Shutdown to Full Operation
ms
17
����������������������������������������������������������������� Maxim Integrated Products
6
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
MICROPHONE TO ADC PATH
f
= 8kHz, MODE = 0 (IIR voice), AV
= 0dB
MICPRE_
S
Dynamic Range
DR
88
dB
dB
dB
(Note 4)
V
= 0.1V , f = 8kHz, f = 1kHz
-78
-85
-71
IN
P-P S
Total Harmonic Distortion +
Noise
THD+N AV
AV
= 0dB, V = 1V , f = 1kHz
IN P-P
MICPRE_
= +30dB, V = 32mV , f = 1kHz
MICPRE_
IN
P-P
Common-Mode Rejection
Ratio
CMRR
V
= 100mV , f = 217Hz
74
62
IN
P-P
V
= 1.65V to 1.95V, input referred,
AVDD
50
MIC inputs floating
Power-Supply Rejection Ratio
PSRR
f = 217Hz, V
= 200mV , input referred
62
62
53
dB
RIPPLE
P-P
f = 1kHz, V
= 200mV , input referred
P-P
RIPPLE
f = 10kHz, V
= 200mV , input referred
P-P
RIPPLE
MODE = 0 (IIR voice)
8kHz
2.2
1.1
MODE = 0 (IIR voice)
16kHz
1kHz, 0dB input,
highpass filter disabled
measured from analog
input to digital output
Path Phase Delay
ms
MODE = 1 (FIR audio)
8kHz
4.5
MODE = 1 (FIR audio)
48kHz
0.76
MICROPHONE PREAMP
Full-Scale Input
AV
= 0dB
1.05
0
V
P-P
MICPRE_
PA1EN/PA2EN = 01
PA1EN/PA2EN = 10
PA1EN/PA2EN = 11
PGAM1/PGAM2 = 0x00
PGAM1/PGAM2 = 0x14
Preamplifier Gain
AV
(Note 5)
19.5
29.5
19
20
30
20
0
20.5
30.5
21
dB
MICPRE_
PGA Gain
AV
(Note 5)
dB
MICPGA_
All gain settings, measured at MIC1P/
MIC1N/MIC2P/MIC2N
MIC Input Resistance
R
50
kI
IN_MIC
����������������������������������������������������������������� Maxim Integrated Products
7
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
MICROPHONE BIAS
MICBIAS Output Voltage
Load Regulation
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
V
I
I
= 1mA
2.15
2.2
0.5
110
92
2.25
4.5
V
MICBIAS
LOAD
= 1mA to 2mA
= 2.8V to 5.5V
mV
FV
LOAD
Line Regulation
V
SPKLVDD
f = 217Hz, V
f = 10kHz, V
= 100mV
= 100mV
RIPPLE (SPKLVDD)
RIPPLE (SPKLVDD)
P-P
Ripple Rejection
dB
83
P-P
A-weighted, f = 20Hz to 20kHz
P-weighted, f = 20Hz to 4kHz
f = 1kHz
3.9
2.1
50
FV
RMS
Noise Voltage
nV/√Hz
MICROPHONE BYPASS SWITCH
On-Resistance
I
V
= 100mA, INABYP = MIC2BYP = 1,
MIC1_
R
5
30
+1
-74
I
ON
= V = 0V, AVDD, T = +25NC
INA_ A
MIC2_
Total Harmonic Distortion +
Noise
V
= 2V , V
= 0.9V, R = 10kI,
IN
P-P CM L
THD+N
-80
60
dB
dB
FA
f = 1kHz, INABYP = MIC2BYP = 1
Off-Isolation
V
V
= 2V , V
= 0.9V, R = 10kI, f = 1kHz
IN
P-P CM L
= [0V, AVDD], V
/V
=
MIC1_
MIC2_ INA_
Off-Leakage Current
-1
[AVDD, 0V]
LINE INPUT TO ADC PATH
Dynamic Range (Note 4)
INA pin direct, f = 48kHz, MODE = 1
S
(FIR audio)
DR
93
dB
Total Harmonic Distortion +
Noise
THD+N
V
= 1V , f = 1kHz
-82
1
dB
%
IN
P-P
Gain Error
DC accuracy
= 1.65V to 1.95V, input referred,
V
AVDD
57
68
line inputs floating, T = +25NC
A
f = 217Hz, V
= 200mV
,
RIPPLE
P-P
63
63
57
AV
= 0dB, input referred
ADC
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
= 200mV
,
RIPPLE
P-P
AV
= 0dB, input referred
ADC
f = 10kHz, V
= 200mV
P-P
,
RIPPLE
AV
= 0dB, input referred
ADC
����������������������������������������������������������������� Maxim Integrated Products
8
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
LINE INPUT PREAMP
AV
AV
= 0dB
1
1.4
20
14
3
PGAIN_
Full-Scale Input
V
V
P-P
IN
= -6dB
PGAIN_
PGAINA/PGAINB = 0x0
19
13
2
21
15
4
PGAINA/PGAINB = 0x1
PGAINA/PGAINB = 0x2
PGAINA/PGAINB = 0x3
PGAINA/PGAINB = 0x4
T
= +25NC
A
Level Adjust Gain
AV
0
dB
PGAIN_
(Note 5)
-4
-7
-3
-2
-5
PGAINA/PGAINB = 0x5,
0x6, 0x7
-6
AV
AV
AV
AV
AV
AV
= +20dB
= +14dB
= +3dB
= 0dB
14.5
21
20
20
10
20
20
20
28
PGAIN_
PGAIN_
PGAIN_
PGAIN_
PGAIN_
PGAIN_
Input Resistance
R
kI
kI
IN
7.5
14
= -3dB
= -6dB
T
T
= +25NC
18
16
22
24
A
Feedback Resistance
R
INAEXT/INBEXT = 1
IN_FB
= T
to T
MAX
A
MIN
ADC LEVEL CONTROL
ADC Level Adjust Range
ADC Level Step Size
AV
AVL/AVR = 0xF to 0x0 (Note 5)
AVLG/AVRG = 00 to 11 (Note 5)
-12
0
+3
18
dB
dB
dB
dB
ADCLVL
1
6
ADC Gain Adjust Range
ADC Gain Adjust Step Size
ADC DIGITAL FILTERS
AV
ADCGAIN
VOICE MODE IIR LOWPASS FILTER (MODE1 = 0)
Ripple limit cutoff
-3dB cutoff
0.441 x fs
0.449 x fs
-0.1
Passband Cutoff
f
Hz
PLP
Passband Ripple
Stopband Cutoff
f < f
+0.1
dB
Hz
PLP
f
0.47 x f
SLP
S
Stopband Attenuation
(Note 6)
f > f
74
dB
SLP
����������������������������������������������������������������� Maxim Integrated Products
9
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
AVFLT = 0x1 (Elliptical tuned for f = 16kHz +
S
0.0161
217Hz notch)
x f
S
AVFLT = 0x2 (500Hz Butterworth tuned for f
16kHz)
=
0.0319
x f
S
S
Passband Cutoff
(-3dB from Peak)
AVFLT = 0x3 (Elliptical tuned for f = 8kHz +
S
217Hz notch)
0.0321
x f
f
Hz
AHPPB
S
AVFLT = 0x4 (500Hz Butterworth tuned for f
8kHz)
=
0.0632
x f
S
S
0.0043
x f
AVFLT = 0x5 (f /240 Butterworth)
S
S
AVFLT = 0x1 (Elliptical tuned for f = 16kHz +
S
0.0139
217Hz notch)
x f
S
AVFLT = 0x2 (500Hz Butterworth tuned for f
16kHz)
=
0.0156
x f
S
S
Stopband Cutoff
(-30dB from Peak)
AVFLT = 0x3 (Elliptical tuned for f = 8kHz +
S
217Hz notch)
0.0279
x f
f
Hz
AHPSB
S
AVFLT = 0x4 (500Hz Butterworth tuned for f
8kHz)
=
0.0312
x f
S
S
0.0018
x f
AVFLT = 0x5 (f /240 Butterworth)
S
S
DC Attenuation
DC
AVFLT ≠ 000
90
dB
Hz
ATTEN
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 0, LRCLK < 50kHz)
Ripple limit cutoff
0.43 x f
0.48 x f
S
Passband Cutoff
f
-3dB cutoff
PLP
SLP
S
-6.02dB cutoff
0.5 x f
S
Passband Ripple
Stopband Cutoff
f < f
-0.1
+0.1
dB
Hz
PLP
f
0.58 x f
S
Stopband Attenuation
(Note 6)
f < f
60
dB
SLP
ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 1, LRCLK > 50kHz)
Ripple limit cutoff
-3dB cutoff
0.208 x f
S
Passband Cutoff
f
Hz
PLP
0.28 x f
-0.1
S
Passband Ripple
Stopband Cutoff
f < f
+0.1
dB
Hz
dB
PLP
f
0.417 x f
SLP
S
Stopband Attenuation
f < f
60
SLP
���������������������������������������������������������������� Maxim Integrated Products 10
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
ADC STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER (MODE1 = 1)
Passband Cutoff
(-3dB from Peak)
0.000125
x f
f
AVFLT ≠ 000
AVFLT ≠ 000
Hz
dB
AHPPB
S
DC Attenuation
DC
90
Atten
MICROPHONE AUTOMATIC GAIN CONTROL
AGCHLD = 01
50
400
2
AGC Hold Duration
AGC Attack Time
AGC Release Time
ms
ms
s
AGCHLD = 11
AGCATK = 00
AGCATK = 11
123
0.078
10
AGCRLS = 000
AGCRLS = 111
AGCTH = 0x0 to 0xF
AGC Threshold Level
AGC Threshold Step Size
AGC Gain
-3
0
+18
20
dB
dB
dB
1
(Note 5)
ADC NOISE GATE
NG Threshold Level
NG Attenuation
ANTH = 0x3 to 0xF, referred to 0dBFS
(Note 5)
-64
0
-16
12
dB
dB
ADC-TO-DAC DIGITAL SIDETONE (MODE = 0)
DVST = 0x01
DVST = 0x1F
-0.5
Sidetone Gain Adjust Range
AV
dB
dB
ms
STGA
-60.5
Sidetone Gain Adjust Step
Size
2
8kHz
2.2
1.1
1kHz, 0dB input, highpass filter
disabled
Sidetone Path Phase Delay
16kHz
ADC-TO-DAC DIGITAL LOOP-THROUGH PATH
f
= 48kHz, MCLK = 12.288MHz, MODE = 1
S
Dynamic Range (Note 4)
DR
83
93
81
dB
dB
(FIR audio), MIC to HP output, T = +25NC
A
Total Harmonic Distortion +
Noise
f = 1kHz, f = 48kHz, MCLK = 12.288MHz, MODE
S
THD+N
= 1 (FIR audio), MIC to HP output
DV_ = 0xF to 0x0 (Note 5)
DV1G = 00 to 11 (Note 5)
DAC LEVEL CONTROL
DAC Attenuation Range
DAC Attenuation Step Size
DAC Gain Adjust Range
DAC Gain Adjust Step Size
AV
-15
0
0
dB
dB
dB
dB
DACATTN
1
6
AV
18
DACGAIN
���������������������������������������������������������������� Maxim Integrated Products 11
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DAC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (MODE1 = 0)
Ripple limit cutoff
-3dB cutoff
0.448 x f
0.451 x f
-0.1
S
Passband Cutoff
f
Hz
PLP
S
Passband Ripple
f < f
+0.1
0.476 x f
dB
Hz
dB
PLP
Stopband Cutoff
f
SLP
S
Stopband Attenuation (Note 6)
f > f
75
SLP
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
DVFLT = 0x1 (Elliptical tuned for f = 16kHz +
S
217Hz notch)
0.0161
x f
S
DVFLT = 0x2 (500Hz Butterworth tuned for f
16kHz)
=
0.0312
x f
S
S
Passband Cutoff
(-3dB from Peak)
DVFLT = 0x3 (Elliptical tuned for f = 8kHz +
S
217Hz notch)
0.0321
x f
f
Hz
DHPPB
S
DVFLT = 0x4 (500Hz Butterworth tuned for f
8kHz)
=
0.0625
x f
S
S
0.0042
x f
DVFLT = 0x5 (fs/240 Butterworth)
S
DVFLT = 0x1 (Elliptical tuned for f = 16kHz +
S
217Hz notch)
0.0139 x f
0.0156 x f
0.0279 x f
S
DVFLT = 0x2 (500Hz Butterworth tuned for f
16kHz)
=
S
S
S
Stopband Cutoff
(-30dB from Peak)
f
Hz
DHPSB DVFLT = 0x3 (Elliptical tuned for f = 8kHz +
S
217Hz notch)
DVFLT = 0x4 (500Hz Butterworth tuned for f
8kHz)
=
S
0.0312 x f
0.0021 x f
S
DVFLT = 0x5 (f /240 Butterworth)
S
S
DC Attenuation
DC
DVFLT ≠ 000
85
dB
Hz
ATTEN
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 0, LRCLK < 50kHz)
Ripple limit cutoff
-3dB cutoff
0.43 x f
S
Passband Cutoff
f
f
0.47 x f
PLP
SLP
S
-6.02dB cutoff
0.5 x f
S
Passband Ripple
f < f
-0.1
+0.1
dB
Hz
dB
PLP
SLP
Stopband Cutoff
0.58 x f
S
Stopband Attenuation (Note 6)
f > f
60
���������������������������������������������������������������� Maxim Integrated Products 12
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
0.24 x f
TYP
MAX UNITS
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 1 for LRCLK > 50kHz)
Ripple limit cutoff
-3dB cutoff
S
S
Passband Cutoff
f
f
Hz
PLP
0.31 x f
-0.1
Passband Ripple
Stopband Cutoff
f < f
+0.1
dB
Hz
PLP
0.477 x f
SLP
S
Stopband Attenuation
(Note 6)
f < f
60
dB
SLP
STEREO AUDIO MODE DC BLOCKING HIGHPASS FILTER
Passband Cutoff
(-3dB from Peak)
0.000104
x f
f
DVFLT ≠ 000 (DAI1), DCB2 = 1 (DAI2)
DVFLT ≠ 000 (DAI1), DCB2 = 1 (DAI2)
Hz
dB
DHPPB
S
DC Attenuation
DC
90
ATTEN
AUTOMATIC LEVEL CONTROL
Dual Band Lowpass Corner
Frequency
ALCMB = 1
ALCMB = 1
5
5
kHz
kHz
Dual Band Highpass Corner
Frequency
Gain Range
0
12
dB
Low-Signal Threshold
ALCTH = 111 to 001
ALCRLS = 101
-48
-12
dBFS
0.25
8
Release Time
s
ALCRLS = 000
PARAMETRIC EQUALIZER
Number of Bands
5
1
Bands
dB
Per Band Gain Range
Preattenuator Gain Range
Preattenuator Step Size
-12
-15
+12
0
(Note 5)
dB
dB
DAC TO RECEIVER AMPLIFIER PATH
Dynamic Range
DR
f
= 48kHz, f = 1kHz (Note 4)
96
dB
dB
S
Total Harmonic Distortion +
Noise
THD+N f = 1kHz, P
= 15mW, R
= 32I
-70
-63
OUT
REC
V
= 2.8V to 5.5V, T = +25NC
64
75
-59
-59
-59
SPKLVDD
A
f = 217Hz, V
= 200mV
RIPPLE
P-P
Power-Supply Rejection Ratio
Click-and-Pop Level
PSRR
dB
f = 1kHz, V
= 200mV
RIPPLE
P-P
f = 10kHz, V
= 200mV
RIPPLE
P-P
Peak voltage, A-weighted, 32
Into shutdown
-68
-72
K
CP
samples per second, AV
=
REC
dBV
Out of shutdown
0dB
���������������������������������������������������������������� Maxim Integrated Products 13
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
LINE INPUT TO RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Referenced to full-scale output level
94
dB
dB
Total Harmonic Distortion +
Noise
THD+N
-64
Peak voltage, A-weighted, 32
Into shutdown
-51
-49
Click-and-Pop Level
K
CP
samples per second, AV
=
REC
dBV
Out of shutdown
0dB
RECEIVER AMPLIFIER
Output Power
P
R
= 32I, f = 1kHz, THD = 1%
83
1
mW
OUT
REC
Full-Scale Output
(Note 7)
V
RMS
RECVOL = 0x00
RECVOL = 0x1F
+8dB to +6dB
+6dB to +0dB
0dB to -14dB
-14dB to -38dB
-38dB to -62dB
f = 1kHz
-62
8
Volume Control (Note 5)
AV
REC
dB
0.5
1
Volume Control Step Size
2
dB
3
4
Mute Attenuation
88
500
100
dB
pF
R
= 32I
= J
REC
Capacitive Drive Capability
No sustained oscillations
R
REC
DAC TO LINE OUT AMPLIFIER PATH
Dynamic Range (Note 4)
DR
f
= 48kHz, f = 1kHz
83
96
dB
dB
S
Total Harmonic Distortion +
Noise
THD+N f = 1kHz, R = 1kI
-78
-72
L
LINE INPUT TO LINE OUT AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Referenced to full-scale output level
92
76
dB
dB
Total Harmonic Distortion +
Noise
THD+N f = 1kHz, R = 10kI
L
Full-Scale Output
(Note 7)
f = 1kHz
2
V
P-P
Mute Attenuation
85
dB
Output Offset Voltage
Capacitive Drive Capability
V
OS
AV
= -62dB
Q3.0
500
Q4
mV
pF
REC_
No sustained oscillations, R = 1kI
L
���������������������������������������������������������������� Maxim Integrated Products 14
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DAC TO SPEAKER AMPLIFIER PATH
Total Harmonic Distortion +
Noise
THD+N f = 1kHz, P
= 200mW, Z
= 8I + 68FH
-68
-88
dB
dB
OUT
SPK
SPKL to SPKR and SPKR to SPKL,
= 640mW, f = 1kHz
Crosstalk
Output Noise
P
OUT
53
65
FV
RMS
Peak voltage, A-weighted,
32 samples per second,
Into shutdown
Click-and-Pop Level
K
dBV
CP
Out of shutdown
66
AV
= 0dB
SPK_
MIC INPUT TO SPEAKER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Referenced to full-scale output level, AV
= 0dB
82
71
dB
dB
SPK_
Total Harmonic Distortion +
Noise
THD+N f = 1kHz, P
= 200mW, R = 8I + 68FH
OUT
L
Peak voltage, A-weighted, 32
Into shutdown
55
52
Click-and-Pop Level
K
samples per second, AV
= 0dB
dBV
CP
SPK_
Out of shutdown
SPEAKER AMPLIFIER
V
V
V
V
= V
= 5.0V
= 4.2V
= 3.7V
= 3.2V
1323
914
700
514
2
SPKLVDD
SPKLVDD
SPKLVDD
SPKLVDD
SPKRVDD
SPKRVDD
SPKRVDD
SPKRVDD
f = 1kHz,
THD = 1%,
= V
= V
= V
Output Power
P
OUT
mW
Z
SPK
= 8I +
68FH
Full-Scale Output
Volume Control
(Note 7)
(Note 5)
V
RMS
SPVOLL/SPVOLR = 0x00
SPVOLL/SPVOLR = 0x1F
-62
+8
0.5
1
AV
dB
SPK_
+8dB to +6dB
+6dB to +0dB
0dB to -14dB
-14dB to -38dB
-38dB to -64dB
f = 1kHz
Volume Control Step Size
2
dB
3
4
Mute Attenuation
86
dB
Output Offset Voltage
V
AV
= -61dB, T = +25NC
Q0.5
Q3
mV
OS
SPK_
A
���������������������������������������������������������������� Maxim Integrated Products 15
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
EXCURSION LIMITER
Upper Corner Frequency
Range
DHPUCF = 001 to 100
400
1000
Hz
Hz
Lower Corner Frequency
DHPLCF = 01 to 10
DHPUCF = 000 (fixed mode)
DHPUCF = 001
400
100
200
300
400
500
Biquad Minimum Corner
Frequency
DHPUCF = 010
Hz
DHPUCF = 011
DHPUCF = 100
Z
V
= 8I + 68FH,
SPK
DHPTH = 000
DHPTH = 111
0.34
0.95
Threshold Voltage
Release Time
= V
=
=
V
P
SPKLVDD
SPKRVDD
5.5V, AV
= 8dB
SPK_
ALCRLS = 101
ALCRLS = 000
0.25
4
s
POWER LIMITER
Attenuation
-64
dB
W
Z
V
= 8I + 68FH,
SPK
PWRTH = 0x1
PWRTH = 0xF
0.08
Threshold
= V
SPKRVDD
SPKLVDD
1.23
5.5V, AV
= 8dB
SPK_
PWRT1 = 0x1
PWRT1 = 0xF
0.5
8.7
0.5
8.7
Time Constant 1
Time Constant 2
t
t
s
PWR1
PWRT2 = 0x1 to 0xF
PWRT2 = 0xF
min
%
PWR2
Weighting Factor
k
PWRK = 000 to 111
12.5
100
PWR
DISTORTION LIMITER
THDCLP = 0x1
THDCLP = 0xF
THDT1 = 000
THDT1 = 111
< 1
24
Distortion Limit
%
s
0.76
6.2
Release Time Constant
���������������������������������������������������������������� Maxim Integrated Products 16
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DAC TO HEADPHONE AMPLIFIER PATH
Master or slave mode
101
Slave mode
97
95
Dynamic Range (Note 4)
DR
f
= 48kHz
dB
S
Low power mode,
97
T
= +25NC
A
R
R
= 16I
= 32I
-85
-92
-64
dB
Total Harmonic Distortion +
Noise
HP
THD+N f = 1kHz, P
= 20mW
OUT
HP
HPL to HPR and HPR to HPL, P
= 5mW,
OUT
Crosstalk
79.5
54
dB
f = 1kHz, R = 32I
HP
V
= V
= 1.65V to 2.0V
46
AVDD
PVDD
f = 217Hz, V
= 200mV
,
RIPPLE
P-P
72
AV
= 0dB
HP_
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
= 200mV
,
RIPPLE
P-P
63
43
AV
= 0dB
HP_
f = 10kHz, V
= 200mV
P-P
,
RIPPLE
AV
= 0dB
HP_
MODE = 0 (voice)
8kHz
2.2
1.1
4.5
0.76
MODE = 0 (voice)
16kHz
1kHz, 0dB input, highpass
filter disabled measured
from digital input to analog
output
DAC Path Phase Delay
ms
MODE = 1 (music)
8kHz
MODE = 1 (music)
48kHz
Gain Error
1
1
5
%
%
Channel Gain Mismatch
Peak voltage, A-weighted,
32 samples per second,
Into shutdown
-62
-63
Click-and-Pop Level
K
dBV
CP
Out of shutdown
AV
= 0dB
HP_
LINE INPUT TO HEADPHONE AMPLIFIER PATH
Total Harmonic Distortion +
Noise
THD+N
V
= 1V , f =1kHz, R = 32I
81
dB
dB
IN
P-P
HP
Dynamic Range (Note 4)
92.5
-62
Peak voltage, A-weighted,
32 samples per second,
AV
Into shutdown
Click-and-Pop Level
K
CP
dBV
Out of shutdown
-63
= 0dB
HP_
���������������������������������������������������������������� Maxim Integrated Products 17
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
HEADPHONE AMPLIFIER
R
R
= 32I
= 16I
30
HP
Output Power
P
f = 1kHz, THD = 1%
mW
V
OUT
38
HP
V
OUT
V
OUT
V
OUT
V
OUT
≤ V
x 0.25V, R = J
PVDD/2
PVDD
-PVDD/2
-PVDD
Positive Charge-Pump Output
Voltage
PVDD
HP
HPVDD
HPVSS
> V
x 0.25V, R = J
HP
PVDD
PVDD
≤ V
> V
x 0.25V, R = J
HP
Negative Charge-Pump
Output Voltage
V
x 0.25V, R = J
PVDD
HP
Output Voltage Threshold
(Output Voltage at which
the Charge Pump Switches
Modes; VOUT Rising;
Transition from Split to Invert
Mode)
QPVDD
x 0.25
V
RL = J
V
TH
Full-Scale Output
(Note 7)
(Note 5)
1
-67
+3
0.5
1
V
RMS
HPVOL_ = 0x00
HPVOL_ = 0x1F
Volume Control
AV
dB
HP_
+3dB to +1dB
+1dB to -5dB
-5dB to -19dB
-19dB to -43dB
-43dB to -67dB
f = 1kHz
Volume Control Step Size
2
dB
dB
3
4
Mute Attenuation
100
Q0.5
T
T
= +25NC
Q1
Q3
A
Output Offset Voltage
V
R
AV
= -67dB
mV
pF
OS
HP_
= T
to T
MAX
A
MIN
R
HP
R
HP
= 32I
= J
500
100
Capacitive Drive Capability
SPEAKER BYPASS SWITCH
On-Resistance
No sustained oscillations
I
= 100mA, SPKBYP = 1,
SPKL_
2.8
I
ON
V
= [0V, V
]
RXIN_
SPKLVDD
V
Z
= 2V , V
= V
/2,
IN
P-P CM
SPKLVDD
R
R
= 10I
= 0I
60
60
S
Total Harmonic Distortion +
Noise
THD+N
= 8I + 68FH, f = 1kHz,
dB
SPK
S
SPKBYP = 1
V
Z
= 2V , V
= V
/2,
IN
P-P CM SPKLVDD
Off-Isolation
96
dB
= 8I + 68FH, f = 1kHz
SPK
V
V
= [0V, V
],
, 0V]
RXIN_
SPKLVDD
Off-Leakage Current
-20
+20
FA
= [V
SPKL_
SPKLVDD
���������������������������������������������������������������� Maxim Integrated Products 18
MAX98088
Stereo Audio Codec
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR
REC HP
to HPGND. Line out loads (R
) connected from LOUTL or LOUTR to SPKLGND. R
= R = J, R
= J, Z = J, C
SPK REF
LOAD
LOAD
HP
REC
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C
= 1FF. AV
= +20dB, AV
= 0dB, AV
MICPGA_ DACATTN
MICBIAS
REG
C1N-C1P
HPVDD
HPVSS
MICPRE_
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
SPK_
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
REC
MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = T
to T , unless otherwise noted. Typical values are at +25NC.) (Note 1)
MAX
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
RECEIVER BYPASS SWITCH
I
V
= 100mA, RECBYP = 1, V
= [0V,
RECN
RECP
On-Resistance
R
ON
2
I
]
SPKLVDD
Total Harmonic Distortion +
Noise
V
= 2V , V
= V
/2, Z
SPK
S
= 8I +
= 8I +
IN
P-P CM
SPKLVDD
THD+N
60
84
dB
dB
68FH, f = 1kHz, RECBYP = 1, R = 0I
V
IN
= 2V , V
= V
/2, Z
P-P CM
SPKLVDD SPK
Off-Isolation
68FH, f = 1kHz
V
[V
= [0V, V
], V
=
RECP
SPKLVDD
RECN
Off-Leakage Current
-15
+15
FA
, 0V]
SPKLVDD
JACK DETECTION
0.92 x
MICBIAS
0.95 x
MICBIAS MICBIAS
0.98 x
SHDN = 1, JACKSNS rising
V
V
V
JACKSNS Threshold
V
SPKLVDD - 0.7
SHDN = 0, JKSNS
SHDN = 0
JACKSNS Sense Voltage
JACKSNS Sense Current
BATTERY ADC
SPKLVDD
4
V
V
= 0V
10
FA
JACKSNS
Input Voltage Range
LSB Size
2.6
5.6
V
V
0.1
DIGITAL INPUT/OUTPUT CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
1.2
-1
TYP
MAX
UNITS
MCLK
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
V
IH
V
V
V
0.6
+1
IL
I
, I
IH IL
FA
pF
V
= 2.0V, V = 0V, 5.5V; T = +25°C
IN A
DVDD
10
SDINS1, BCLKS1, LRCLKS1—INPUT
0.7 x
DVDDS1
Input High Voltage
Input Low Voltage
V
V
V
IH
0.29 x
DVDDS1
V
IL
Input Hysteresis
200
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
-1
+1
V
= 3.6V, V = 0V, 3.6V; T = +25°C
IN A
DVDDS1
���������������������������������������������������������������� Maxim Integrated Products 19
MAX98088
Stereo Audio Codec
with FlexSound Technology
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
= 1.65V, I = 3mA
MIN
TYP
MAX
UNITS
BCLKS1, LRCLKS1, SDOUTS1—OUTPUT
Output Low Voltage
Output High Voltage
V
V
V
0.4
V
V
OL
DVDDS1
OL
DVDDS1
- 0.4
V
OH
= 1.65V, I
= 3mA
DVDDS1
OH
V
= 2.0V, V = 0V, 5.5V; T = +25°C,
IN A
DVDD
Input Leakage Current
I
, I
IH IL
-1
+1
FA
high-impedance state
SDINS2, BCLKS2, LRCLKS2—INPUT
0.7 x
DVDDS2
Input High Voltage
Input Low Voltage
V
V
V
IH
0.29 x
DVDDS2
V
IL
Input Hysteresis
200
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
-1
+1
V
= 3.6V, V = 0V, 3.6V; T = +25°C
IN A
DVDDS2
BCLKS2, LRCLKS2, SDOUTS2—OUTPUT
Output Low Voltage
V
V
V
V
= 1.65V, I = 3mA
0.4
V
V
OL
DVDDS2
OL
DVDDS2
- 0.4
Output High Voltage
V
OH
= 1.65V, I
= 3mA
DVDDS2
OH
= 2.0V, V = 0V, 5.5V; T = +25NC,
DVDD
IN
A
Input Leakage Current
SDA, SCL—INPUT
Input High Voltage
I
, I
-1
+1
FA
IH IL
high-impedance state
0.7 x
DVDD
V
V
V
IH
0.3 x
DVDD
Input Low Voltage
V
IL
Input Hysteresis
210
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
V
= 2.0V, V = 0V, 5.5V; T = +25NC
-1
+1
DVDD
IN
A
SDA, IRQ—OUTPUT
Output High Current
I
1
mA
V
OH
V
V
= 5.5V, T = +25°C
A
OUT
0.2 x
DVDD
Output Low Voltage
DIGMICDATA—INPUT
Input High Voltage
V
= 1.65V, I = 3mA
DVDD OL
OL
0.65 x
DVDD
V
V
V
IH
0.35 x
DVDD
Input Low Voltage
V
IL
Input Hysteresis
125
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I
, I
IH IL
-25
+25
V
= 2.0V, V = 0V, 2.0V; T = +25°C
IN A
DVDD
���������������������������������������������������������������� Maxim Integrated Products 20
MAX98088
Stereo Audio Codec
with FlexSound Technology
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
= 1.65V, I = 1mA
MIN
TYP
MAX
UNITS
DIGMICCLK—OUTPUT
Output Low Voltage
V
V
V
0.4
V
V
OL
DVDD
OL
DVDD -
0.4
Output High Voltage
V
OH
= 1.65V, I
= 1mA
DVDD
OH
INPUT CLOCK CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
50
MAX
60
UNITS
MCLK Input Frequency
f
MHz
MCLK
PSCLK = 01
40
60
MCLK Input Duty Cycle
%
PSCLK = 10 or 11
30
70
Maximum MCLK Input Jitter
LRCLK Sample Rate (Note 8)
100
ps
RMS
DHF_ = 0
8
48
48
96
kHz
DHF_ = 1
FREQ1 = 0x8 to 0xF
FREQ1 = 0x0
0
0
DAI1 LRCLK Average Frequency
Error (Note 9)
%
%
-0.025
+0.025
DAI2 LRCLK Average Frequency
Error (Note 9)
-0.025
+0.025
Rapid lock mode
2
7
PLL Lock Time
ms
Nonrapid lock mode
12
25
Maximum LRCLK Jitter to Maintain
PLL Lock
100
ns
Soft-Start/Stop Time
10
ms
���������������������������������������������������������������� Maxim Integrated Products 21
MAX98088
Stereo Audio Codec
with FlexSound Technology
AUDIO INTERFACE TIMING CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
90
TYP
MAX
UNITS
ns
BCLK Cycle Time
BCLK High Time
BCLK Low Time
t
Slave mode
Slave mode
Slave mode
BCLK
t
20
ns
BCLKH
t
20
ns
BCLKL
BCLK or LRCLK Rise and Fall Time
SDIN to BCLK Setup Time
LRCLK to BCLK Setup Time
SDIN to BCLK Hold Time
t , t
Master mode, C = 15pF
L
5
ns
R
F
t
20
20
20
20
ns
SETUP
t
Slave mode
ns
SYNCSET
t
ns
HOLD
SYNCHOLD
LRCLK to BCLK Hold Time
t
Slave mode
ns
Minimum Delay Time from LSB
BCLK Falling Edge to
t
Master mode, TDM_ = 1
42
ns
HIZOUT
High-Impedance State
LRCLK Rising Edge to SDOUT
MSB Delay
t
C
C
= 30pF, TDM_ = 1, FSW_ = 1
50
ns
ns
SYNCTX
L
TDM_ = 1, BCLK rising edge
50
50
BCLK to SDOUT Delay
t
= 30pF
CLKTX
L
TDM_ = 0
TDM_ = 1
-15
20
+15
Master
mode
Delay Time from BCLK to LRCLK
t
ns
ns
CLKSYNC
0.8 x
BCLKL
TDM_ = 0
t
Delay Time from LRCLK to BCLK
After LSB
Master
mode
t
TDM_ = 1, FSW_ = 1
ENDSYNC
t
BCLK
t
F
t
R
t
t
BCLKL
BCLKH
BCLK
BCLK
(OUTPUT)
(INPUT)
t
t
CLKSYNC
SYNCSET
HI-Z
LRCLK
(OUTPUT)
LRCLK
(INPUT)
t
t
CLKTX
t
t
HIZOUT
CLKTX
HIZOUT
SDOUT
(OUTPUT)
SDOUT
LSB
LSB
LSB
HI-Z
MSB
MSB
t
HOLD
(OUTPUT)
t
t
t
SETUP
HOLD
SETUP
SDIN
(INPUT)
SDIN
LSB
MSB
MSB
(INPUT)
MASTER MODE
SLAVE MODE
Figure 1. Non-TDM Audio Interface Timing Diagrams (TDM_ = 0)
���������������������������������������������������������������� Maxim Integrated Products 22
MAX98088
Stereo Audio Codec
with FlexSound Technology
t
BCLK
t
F
t
R
t
t
BCLKL
BCLKH
BCLK (OUTPUT)
BCLK (INPUT)
t
t
t
CLKSYNC
SYNCSET
CLKSYNC
t
SYNCHOLD
LRCLK (OUTPUT)
t
LRCLK (INPUT)
t
t
t
CLKTX
CLKTX
HIZOUT
HIZOUT
SDOUT (OUTPUT)
SDOUT (OUTPUT)
LSB
LSB
HI-Z
MSB
LSB
HI-Z
MSB
MSB
t
t
t
t
SETUP HOLD
SETUP HOLD
SDIN (INPUT)
SDIN (INPUT)
MSB
MASTER MODE
LSB
SLAVE MODE
Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 0)
t
BCLK
t
F
t
R
t
t
BCLKL
BCLKH
BCLK (OUTPUT)
BCLK (INPUT)
LRCLK (INPUT)
t
t
CLKSYNC
ENDSYNC
LRCLK (OUTPUT)
t
t
t
t
CLKTX
CLKTX
SYNCTX
SYNCTX
t
t
HIZOUT
HIZOUT
SDOUT (OUTPUT)
LSB
HI-Z
MSB
SDOUT (OUTPUT)
SDIN (INPUT)
LSB
HI-Z
MSB
t
t
t
t
SETUP HOLD
SETUP HOLD
SDIN (INPUT)
LSB
MSB
SLAVE MODE
LSB
MSB
MASTER MODE
Figure 3. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 1)
DIGITAL MICROPHONE TIMING CHARACTERSTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
DIGMICCLK Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MICCLK = 00
MICCLK = 01
MCLK/8
MCLK/6
f
MHz
MICCLK
DIGMICDATA to DIGMICCLK
Setup Time
t
Either clock edge
Either clock edge
20
0
ns
ns
SU,MIC
DIGMICDATA to DIGMICCLK
Hold Time
t
HD,MIC
���������������������������������������������������������������� Maxim Integrated Products 23
MAX98088
Stereo Audio Codec
with FlexSound Technology
1/f
MICCLK
t
t
HD,MIC SU,MIC
t
t
HD,MIC SU,MIC
LEFT
RIGHT
LEFT
RIGHT
Figure 4. Digital Microphone Timing Diagram
2
I C TIMING CHARACTERSTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
PARAMETER
Serial-Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Guaranteed by SCL pulse-width low and
high
f
0
400
kHz
SCL
Bus Free Time Between STOP and
START Conditions
t
1.3
0.6
Fs
Fs
BUF
Hold Time (Repeated) START
Condition
t
t
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for a Repeated START
Condition
0.6
Fs
SU,STA
Data Hold Time
Data Setup Time
t
R
PU
= 475I, CB = 100pF, 400pF
0
900
ns
ns
HD,DAT
t
100
SU,DAT
20 +
SDA and SCL Receiving Rise Time
SDA and SCL Receiving Fall Time
SDA Transmitting Fall Time
t
(Note 10)
(Note 10)
300
300
250
ns
ns
ns
R
0.1C
B
20 +
0.1C
t
t
F
B
20 +
0.05C
R
PU
= 475I, C = 100pF, 400pF (Note 10)
B
F
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
0
Fs
pF
ns
SU,STO
C
B
Guaranteed by SDA transmitting fall time
400
50
Pulse Width of Suppressed Spike
t
SP
���������������������������������������������������������������� Maxim Integrated Products 24
MAX98088
Stereo Audio Codec
with FlexSound Technology
2
I C TIMING CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. T = +25NC, unless otherwise noted.)
SPKRVDD A
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
(Note 1)
SDA
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
SP
t
LOW
t
SU,STO
t
HD,DAT
t
SCL
HIGH
t
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 5. I C Interface Timing Diagram
Note 1: The IC is 100% production tested at T = +25NC. Specifications over temperature limits are guaranteed by design.
A
Note 2: Analog supply current = I
+ I
. Speaker supply current = I
+ I . Digital supply current = I
SPKRVDD DVDD
AVDD
HPVDD
SPKLVDD
+ I
+ I
.
DVDDS1
DVDDS2
Note 3: Clocking all zeros into the DAC.
Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 5: Gain measured relative to the 0dB setting.
Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000.
Note 7: 0dBFS for DAC input. 1V
for INA/INB inputs.
P-P
Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some full-
scale performance degradation compared to synchronous integer related MCLK/LRCLK ratios.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
Power Consumption
(V
AVDD
= V
= V
= V
= V
= 1.8V, V
= V
= 3.7V)
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
I
I
+
I
+
DVDDS1
I
DVDDS2
(mA)
SPKVDD
I
I
I
DVDD
(mA)
POWER
(mW)
DYNAMIC
RANGE (dB)
AVDD
PVDD
MODE
SPKLVDD
(mA)
(mA)
(mA)
PLAYBACK TO HEADPHONE ONLY
DAC Playback 48kHz Stereo HP
DAC ª HP
Low power mode, 24-bit, music fil-
ters, 256Fs
1.25
0.47
0.00
0.00
1.35
0.01
5.55
8.32
97
97
DAC Playback 48kHz Stereo HP
DAC ª HP
Low power mode, 24-bit, music fil-
ters, 256Fs, 0.1mW/channel,
1.25
1.81
1.56
0.01
R
HP
= 32I
���������������������������������������������������������������� Maxim Integrated Products 25
MAX98088
Stereo Audio Codec
with FlexSound Technology
Power Consumption (continued)
(V
AVDD
= V
= V
= V
= V
= 1.8V, V
= V
= 3.7V)
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
I
I
+
I
+
DVDDS1
I
DVDDS2
(mA)
SPKVDD
I
I
I
DVDD
(mA)
POWER
(mW)
DYNAMIC
RANGE (dB)
AVDD
PVDD
MODE
SPKLVDD
(mA)
(mA)
(mA)
DAC Playback 48kHz Stereo HP
DAC ª HP
24-bit, music filters, 256Fs
2.04
1.27
0.00
0.00
0.00
0.00
1.53
0.01
8.72
10.63
8.46
101
101
100
97
DAC Playback 48kHz Stereo HP
DAC ª HP
24-bit, music filters, 256Fs, 0.1mW/
2.04
2.03
1.25
2.11
1.27
0.47
1.74
1.41
1.25
0.01
0.01
0.01
channel, R = 32I
HP
DAC Playback 44.1kHz Stereo HP
DAC ª HP
24-bit, music filters
DAC Playback 44.1kHz Stereo HP
DAC ª HP
Low power mode, 24-bit, music
filters
5.34
DAC Playback 8kHz Stereo HP
DAC ª HP
16-bit, voice filters
2.04
1.26
1.27
0.47
0.00
0.00
1.07
0.90
0.00
0.00
7.89
4.72
95
94
DAC Playback 8kHz Stereo HP
DAC ª HP
16-bit, low power mode, voice filters
DAC Playback 8kHz Mono HP
DAC ª HP
16-bit, low power mode, voice filters
0.77
2.40
0.29
1.27
0.00
0.00
0.79
0.02
0.00
0.00
3.33
6.67
93.7
95
Line Playback Stereo HP
INA ª HP
Single-ended inputs
DAC PLAYBACK TO CLASS D SPEAKER
DAC Playback 48kHz Stereo SPK
DAC ª SPK
2.31
0.00
6.33
2.14
0.01
31.44
86
24-bit, music filters
���������������������������������������������������������������� Maxim Integrated Products 26
MAX98088
Stereo Audio Codec
with FlexSound Technology
Power Consumption (continued)
(V
AVDD
= V
= V
= V
= V
= 1.8V, V
= V
= 3.7V)
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
I
I
+
I
+
DVDDS1
I
DVDDS2
(mA)
SPKVDD
I
I
I
DVDD
(mA)
POWER
(mW)
DYNAMIC
RANGE (dB)
AVDD
PVDD
MODE
SPKLVDD
(mA)
(mA)
(mA)
DAC Playback 48kHz Mono SPK
DAC ª SPK
24-bit, music filters
1.35
0.00
3.23
3.24
1.84
0.01
17.69
13.83
86
83
Line Playback Mono SPK
INA ª SPKL
1.01
0.00
0.03
0.00
Differential inputs
FULL DUPLEX
Full-Duplex 8kHz Mono RCV
MIC1 ª ADC
DAC ª REC
Record = 87
Playback = 94
6.32
0.00
1.27
1.54
0.48
1.24
1.28
0.01
0.01
19.33
26.43
16-bit, voice filters
Full-Duplex 8kHz Stereo HP
MIC1/2 ª ADC
DAC ª HP
Record = 87
Playback = 96
11.19
16-bit, mixer, voice filters
Full-Duplex 8kHz Stereo HP
MIC1/2 ª ADC
DAC ª HP
Record = 87
Playback = 94
7.12
0.47
0.48
1.10
0.02
17.44
16-bit, low power mode, voice filters
LINE RECORD
Line Stereo Record 48kHz
INA ª ADC
24-bit, low power, music filters
6.19
5.69
0.00
0.00
0.20
0.20
1.31
1.31
0.15
0.12
14.47
13.53
91
93
Line Stereo Record 48kHz
INA ª ADC
Direct pin input, 24bit, low power,
music filters
���������������������������������������������������������������� Maxim Integrated Products 27
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
HP_
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Microphone to ADC
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
V
= 1V
V = 1V
V
= 1V
IN
P-P
IN P-P
IN
P-P
AV
= 0dB
AV
= 0dB
MICPRE_
AV
= 0dB
MICPRE_
MICPRE_
-80
-90
-100
10
100
1000
10,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= 1V
V
= 0.1V
V = 0.032V
IN
P-P
IN
P-P
IN P-P
AV
= 0dB
AV
= 0dB
AV
= 0dB
MICPRE_
MICPRE_
MICPRE_
-100
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
10
100
1000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 28
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (MIC TO ADC)
POWER-SUPPLY RECTION RATIO
vs. FREQUENCY (MIC TO ADC)
GAIN vs. FREQUENCY (MIC TO ADC)
10
0
70
60
50
40
30
20
10
0
10
0
MICPRE = 30dB
INPUTS AC GROUNDED
= 200mV
V
RIPPLE
P-P
-10
-20
-30
-40
-50
-60
-70
-80
-10
-20
-30
-40
-50
-60
-70
-80
-90
MODE = 1
MICPRE = 20dB
MODE = 0
RIPPLE ON AVDD,
DVDD, HPVDD
MICPRE = 0dB
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 12.288MHz
LRCLK = 48kHz
FREQ MODE
V
= 1V
IN
P-P
RIPPLE ON SPKLVDD,
SPKRVDD
AV
= 0dB
MICPRE_
-90
10
100
1000
10k
10
100
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, 0dBFS (MIC TO ADC)
FFT, -60dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
20
0
0
-20
20
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
-20
-40
-20
-40
-60
-80
-100
-120
-140
AV
= 0dB
AV
= 0dB
MICPRE_
MICPRE_
AV
= 0dB
MICPRE_
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
���������������������������������������������������������������� Maxim Integrated Products 29
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
FFT, -60dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
0
-20
20
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-40
-60
-80
-100
-120
-140
AV
= 0dB
AV
MICPRE_
= 0dB
-40
MICPRE_
-60
-80
-100
-120
-140
0
5
10
FREQUENCY (kHz)
15
20
0
5
1
15
20
FREQUENCY (kHz)
FFT, -60dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
0
-20
20
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
-20
-40
-60
-80
-100
-120
-140
AV
MICPRE_
= 0dB
AV
MICPRE_
= 0dB
-40
-60
-80
-100
-120
-140
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (kHz)
15
20
���������������������������������������������������������������� Maxim Integrated Products 30
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
ADC ENABLE/DISABLE RESPONSE
(MIC TO ADC)
FFT, -60dBFS (MIC TO ADC)
MAX98088 toc18
0
-20
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
SCL
1V/div
AV
MICPRE_
= 0dB
-40
-60
-80
ADC
OUTPUT
0.5V/div
-100
-120
-140
0
10ms/div
5
10
FREQUENCY (kHz)
15
20
SOFTWARE TURN-ON/OFF RESPONSE
(MIC TO ADC)
MAX98088 toc19
SCL
1V/div
ADC
OUTPUT
0.5V/div
10ms/div
���������������������������������������������������������������� Maxim Integrated Products 31
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Line to ADC
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO ADC)
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO ADC)
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO ADC)
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
IN
= 1.4V
V = 0.1V
V
IN
= 1V
P-P
IN P-P
P-P
AV
= -6dB
= 1µF
AV
PGAIN_
= +20dB
AV
= 0dB
= 1µF
PGAIN_
C
PGAIN_
C
IN
= 1µF
C
IN
IN
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE-IN TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE-IN TO ADC)
0
10
0
V
= 200mV
P-P
MCLK = 12.288MHz
LRCLK = 48kHz
RIPPLE
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
= 1V
IN
RMS
-10
-20
-30
-40
-50
-60
-70
-80
-90
EXTERNAL GAIN MODE
R
= 56kI
IN
C
= 1µF
IN
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON SPKLVDD,
SPKRVDD
10
100
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 32
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Line-In Pin Direct to ADC
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE-IN DIRECT TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE-IN DIRECT TO ADC)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
= 200mV
P-P
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
RIPPLE
V
IN
C
= 1V
P-P
= 1µF
IN
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON SPKLVDD, SPKRVDD
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
Digital Loopback
FFT, 0dBFS (SDINS1 TO SDINS2
DIGITAL LOOPBACK)
FFT, -60dBFS (SDINS1 TO SDINS2
DIGITAL LOOPBACK)
0
-20
0
-20
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
���������������������������������������������������������������� Maxim Integrated Products 33
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Analog Loopback
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
FFT, 0dBFS (LINE TO ADC TO DAC
TO HEADPHONE)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
20
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
-10
-20
-30
-40
-50
-60
-70
-20
-40
-60
-80
-100
-120
-140
R
= 32I
R
= 32I
R
= 32I
HP
HP
HP
C
C
IN
= 1µF
C
IN
= 1µF
= 1µF
IN
P
= 0.020W
OUT
P
= 0.020W
OUT
-80
-90
P
= 0.01W
P
= 0.01W
100
OUT
1000
FREQUENCY (Hz)
OUT
10
100
10,000
100,000
10
1000
10,000
100,000
0
5
10
15
20
FREQUENCY (Hz)
FREQUENCY (kHz)
FFT, -60dBFS (LINE TO ADC TO DAC
TO HEADPHONE)
FFT, 0dBFS (LINE TO ADC TO DAC
TO HEADPHONE)
FFT, -60dBFS (LINE TO ADC TO DAC
TO HEADPHONE)
0
-20
20
0
0
-20
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-40
-60
-80
-100
-120
-140
R
= 32I
R
= 32I
R
= 32I
C = 1µF
IN
-40
-40
HP
C
HP
C
HP
= 1µF
= 1µF
IN
IN
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
���������������������������������������������������������������� Maxim Integrated Products 34
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
DAC to Receiver
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO RECEIVER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO RECEIVER)
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO RECEIVER)
0
0
200
180
160
140
120
100
80
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
R
= 32I
REC
AV
REC
R
= 32I
REC
= +8dB
AV
= +8dB
REC
REC
AV
= +8dB
REC
f = 3000Hz
THD+N = 10%
THD+N = 1%
f = 1000Hz
P
OUT
= 0.02W
P
= 0.08W
OUT
f = 100Hz
60
0
0.02 0.04 0.06 0.08 0.10 0.12
OUTPUT POWER (W)
10
100
1000
10,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
GAIN vs. FREQUENCY
(DAC TO RECEIVER)
POWER CONSUMPTION vs. OUTPUT
POWER (DAC TO RECEIVER)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO RECEIVER)
5
4
250
200
150
100
50
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
INPUTS AC GROUNDED
= 200mV
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
V
RIPPLE
P-P
3
AV
= +8dB
R
= 32I
REC
REC
2
R
= 32I
REC
1
RIPPLE ON AVDD,
DVDD, HPVDD
0
-1
-2
-3
-4
-5
RIPPLE ON SPKLVDD,
SPKRVDD
0
10
100
1000
10,000
0
20
40
60
80
100
120
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
OUTPUT POWER PER CHANNEL (mW)
���������������������������������������������������������������� Maxim Integrated Products 35
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
SOFTWARE TURN-ON/OFF RESPONSE
SOFTWARE TURN-ON/OFF RESPONSE
FFT, 0dBFS (DAC TO RECEIVER)
(DAC TO RECEIVER, VSEN = 1)
(DAC TO RECEIVER, VSEN = 0)
MAX98088 toc42
MAX98088 toc41
20
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
SCL
1V/div
SCL
1V/div
-20
R
= 32I
REC
-40
-60
-80
-100
-120
-140
-160
RECEIVER
OUTPUT
1V/div
RECEIVER
OUTPUT
1V/div
0
5
10
15
20
10ms/div
10ms/div
FREQUENCY (kHz)
WIDEBAND FFT, 0dBFS
(DAC TO RECEIVER)
WIDEBAND FFT, 0dBFS
(DAC TO RECEIVER)
FFT, -60dBFS (DAC TO RECEIVER)
0
0
-20
0
-20
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-20
-40
R
= 32I
R
= 32I
REC
REC
R
= 32I
-40
REC
-40
-60
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-100
-120
0
1
10
100
1000 10,000
0
1
10
100
1000 10,000
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
���������������������������������������������������������������� Maxim Integrated Products 36
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Line to Receiver
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO RECEIVER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO RECEIVER)
0
-10
-20
-30
-40
-50
-60
-70
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
AV
C
= 32I
R
AV
C = 1µF
= 32I
REC
REC
= +8dB
= +8dB
REC
REC
= 1µF
IN
IN
P
P
= 0.02W
= 0.08W
OUT
f = 100Hz
f = 6000Hz
f = 1000Hz
0.04
OUT
0
0.02
0.06
0.08
0.10
10
100
1000
FREQUENCY (Hz)
10,000
100,000
OUTPUT POWER (W)
POWER-SUPPLY
REJECTION RATIO vs. FREQUENCY
(LINE-IN DIRECT TO RECEIVER)
GAIN vs. FREQUENCY
(LINE TO RECEIVER)
5
4
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
C
= 32I
= 1µF
INPUTS AC GROUNDED
REC
IN
V
= 200mV
RIPPLE
P-P
3
2
RIPPLE ON SPKLVDD,
SPKRVDD
1
0
RIPPLE ON AVDD,
DVDD, HPVDD
-1
-2
-3
-4
-5
10
100
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 37
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
DAC to Line Output
FFT, 0dBFS (DAC TO LINE OUT)
FFT, -60dBFS (DAC TO LINE OUT)
20
0
0
-20
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-20
-40
-60
-80
-100
-120
-140
R
= 10kI
R
= 10kI
LOAD
LOAD
-40
-60
-80
-100
-120
-140
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (kHz)
15
20
Line to Line Output
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT LEVEL
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE-IN TO LINE-OUT)
(LINE-IN TO LINE-OUT)
(LINE-IN TO LINE-OUT)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 10kI
R
= 10kI
LOAD
LOAD
V
= 1V , 1kHz
RMS
IN
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 10kI
LOAD
EXTERNAL GAIN MODE
= 56kI
R
EXT
V
= 0.2V
1000
OUT
RMS
f = 6kHz
V
= 0.8V
OUT
RMS
f = 100Hz
f = 1kHz
0.2 0.4 0.6 0.8 1.0 1.2 1.4
OUTPUT LEVEL (V
10
100
10,000
100,000
10
100
1000
10,000
100,000
0
FREQUENCY (Hz)
FREQUENCY (Hz)
)
RMS
���������������������������������������������������������������� Maxim Integrated Products 38
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
DAC to Speaker
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
V
= 4.2V
V
= 3.7V
SPK_VDD
SPKVDD_
-10
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
-60
-70
Z
= 8I + 68µH
= +8dB
Z
= 8I + 68µH
= +8dB
SPK_
SPK_
SP_
AV
AV
SPK_
f = 6000Hz
f = 6000Hz
f = 1000Hz
f = 1000Hz
-80
-90
f = 100Hz
0.6
f = 100Hz
0
0.2 0.4 0.6 0.8 1.0 1.2
OUTPUT POWER (W)
1.4
0
0.2
0.4
0.8
1.0
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(DAC TO SPEAKER)
5
4
3
0
0
-10
-20
-30
-40
-50
-60
-70
-80
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
= 4.2V
V
= 3.7V
SPK_VDD
SPK_VDD
-10
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-30
-40
-50
-60
-70
Z
SPK_
= 8I + 68µH
2
1
Z
= 4I + 33µH
Z
= 4I + 33µH
SP_
SP_
AV
= +8dB
AV
= +8dB
SPK_
SPK_
0
f = 6000Hz
-1
-2
-3
f = 6000Hz
f = 1000Hz
f = 100Hz
f = 1000Hz
-4
-5
-80
-90
f = 100Hz
10
100
1k
FREQUENCY (Hz)
10k
100k
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
OUTPUT POWER (W)
1.5
2.0
OUTPUT POWER (W)
���������������������������������������������������������������� Maxim Integrated Products 39
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(DAC TO SPEAKER)
NOISE vs. FREQUENCY
(DAC TO SPEAKER)
(DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
V
= 4.2V
V
= 3.7V
SPK_VDD
V
= 3V
SPK_VDD
SPK_VDD
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
Z
= 8I + 68µH
= +8dB
Z
= 8I + 68µH
= +8dB
SPK_
Z
= 4I + 33µH
= +8dB
SP_
SP_
SP_
AV
AV
AV
SPK_
SPK_
f = 6000Hz
P
= 0.55W
P
= 0.55W
OUT
OUT
f = 1000Hz
0.8
P
OUT
= 0.25W
2000
P
= 0.25W
OUT
f = 100Hz
0.4 0.6
20
200
2000
20,000
20
200
20,000
0
0.2
1.0
1.2
FREQUENCY (Hz)
FREQUENCY (Hz)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
(DAC TO SPEAKER)
(DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
2200
2000
1800
1600
1400
1200
1000
800
V
= 4.2V
V
= 3.7V
SPK_VDD
SPK_VDD
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
Z
SPK_
= 8I + 68µH
Z
= 4I + 33µH
= +8dB
Z
= 4I + 33µH
= +8dB
SP_
SP_
AV
= +8dB
SPK_
P
= 1W
OUT
AV
AV
SPK_
SPK_
P
= 1W
OUT
THD+N = 10%
P
= 0.5W
OUT
P
= 0.5W
OUT
THD+N = 1%
600
400
100
1000
10,000
100,000
100
1000
10,000
100,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (Hz)
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
���������������������������������������������������������������� Maxim Integrated Products 40
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
GAIN vs. FREQUENCY
(DAC TO SPEAKER)
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
5
4
100
90
80
70
60
50
40
30
20
10
0
4000
3500
3000
2500
2000
1500
1000
500
Z
SPK
= 8I + 68µH
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
3
Z
SPK_
= 4I + 33µH
Z
SPK_
= 8I + 68µH
2
AV
= +8dB
SPK_
1
THD+N = 10%
Z
SPK
= 4I + 33µH
0
-1
-2
-3
-4
-5
V
= 4.2V
SPK_VDD
THD+N = 1%
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
AV
SKP_
= +8dB
0
10
100
1k
FREQUENCY (Hz)
10k
100k
0
0.5
1.0
1.5
2.0
2.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO SPEAKER)
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
18
15
12
9
0
100
90
80
70
60
50
40
30
20
10
0
Z
SPK
= 8I + 68µH
V
= 200mV
P-P
RIPPLE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
Z
SPK_
= 8I + 68µH
SPKVOL_ = +8dB
ALL ZEROS AT INPUT
RIPPLE ON AVDD,
DVDD, HPVDD
Z
SPK
= 4I + 33µH
V
= 3.7V
SPK_VDD
6
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
3
RIPPLE ON SPKLVDD,
SPKRVDD
AV
SKP_
= +8dB
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10
100
1000
10,000
100,000
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 41
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
HP_
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
SOFTWARE TURN-ON/OFF RESPONSE
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO SPEAKER, VSEN = 1)
CROSSTALK vs. FREQUENCY
(DAC TO SPEAKER)
(DAC TO SPEAKER, VSEN = 0)
MAX98088 toc74
MAX98088 toc75
0
-10
-20
-30
-40
-50
-60
-70
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
SCL
1V/div
SCL
1V/div
ZSPK_ = 8I + 68µH
SPEAKER
OUTPUT
1V/div
SPEAKER
OUTPUT
1V/div
-80
10
100
1000
10,000
100,000
10ms/div
10ms/div
FREQUENCY (Hz)
FFT, -60dBFS (DAC TO SPEAKERS)
WIDEBAND FFT (DAC TO SPEAKER)
FFT, -60dBFS (DAC TO SPEAKERS)
0
-20
-40
-60
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.2888MHz
LRCLK = 48kHz
NI MODE
-20
-40
-60
-80
-100
-120
Z
SPK_
= 8I + 68µH
Z
SPK_
= 8I + 68µH
Z
SPK_
= 8I + 68µH
-80
-100
-120
-140
-140
0
0
5000
10,000
FREQUENCY (kHz)
15,000
20,000
1
10
FREQUENCY (MHz)
100
5000
10,000
FREQUENCY (kHz)
15,000
20,000
���������������������������������������������������������������� Maxim Integrated Products 42
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Line to Speaker
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(LINE TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
GAIN vs. FREQUENCY
(LINE TO SPEAKER)
(LINE TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
5
4
3
Z
AV
C
= 8I + 68µH
Z
AV
C = 1µF
= 8I + 68µH
Z
= 8I + 68µH
SPK
SPK
FN
IN
= +8dB
= +8dB
C = 1µF
SPK_
SPK_
= 1µF
IN
IN
2
1
0
P
= 0.5W
OUT
f = 1000Hz
f = 6000Hz
-1
-2
-3
-4
-5
P
= 0.25W
OUT
f = 100Hz
0.4
OUTPUT POWER (W)
0
0.2
0.6
0.8
1.0
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE-IN TO SPEAKER)
CROSSTALK vs. FREQUENCY
(LINE TO SPEAKER)
10
0
0
Z
C
= 8I + 68µH
= 1µF
FN
IN
INPUTS AC GROUNDED
-10
-20
-30
-40
-50
-60
-70
-80
VRIPPLE = 200mV
P-P
-10
-20
-30
-40
-50
-60
-70
-80
-90
RIPPLE ON SPKLVDD,
SPKRVDD
RIGHT TO LEFT
LEFT TO RIGHT
RIPPLE ON AVDD,
DVDD, HPVDD
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 43
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
DAC to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
HP
R
= 32I
HP
AV _ = +3dB
HP
AV
= +3dB
HP_
f = 6000Hz
f = 3000Hz
f = 1000Hz
f = 1000Hz
f = 100Hz
f = 100Hz
0.01
0
0.01
0.02
0.03
0.04
0.05
0
0.02
0.03
0.04
0.05
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
0
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
R
= 32I
R
= 16I
HP
AV
HP
AV
HP
AV
= +3dB
= +3dB
= +3dB
HP_
HP_
HP_
f = 6000Hz
f = 6000Hz
f = 6000Hz
f = 1000Hz
f = 1000Hz
f = 1000Hz
f = 100Hz
0.03
f = 100Hz
0.03
f = 100Hz
0
0.01
0.02
0.04
0.05
0
0.01
0.02
0.04
0.05
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
���������������������������������������������������������������� Maxim Integrated Products 44
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
0
MCLK = 12.288MHz
LRCLK = 48kHz
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
256 Fs MODE
LOW POWER MODE
R
= 32I
HP
AV
R
= 32I
HP
AV
R
= 16I
= +3dB
HP
AV
HP_
= +3dB
HP_
= +3dB
HP_
f = 6000Hz
P
OUT
= 0.01W
P
= 0.01W
OUT
f = 1000Hz
f = 100Hz
P
OUT
= 0.02W
1000
P
OUT
= 0.02W
10
100
10,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
0
0.01
0.02
0.03
0.04
0.05
FREQUENCY (Hz)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
0
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
R
= 32I
R
= 16I
HP
AV
HP
AV
HP
AV
= +3dB
= +3dB
= +3dB
HP_
HP_
HP_
P
= 0.02W
OUT
P
= 0.02W
OUT
P
OUT
= 0.01W
P
= 0.01W
OUT
P
= 0.01W
P
= 0.02W
OUT
OUT
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
���������������������������������������������������������������� Maxim Integrated Products 45
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
PVDD CURRENT vs. OUTPUT POWER
(DAC TO HEADPHONE)
GAIN vs. FREQUENCY
(DAC TO HEADPHONE)
10
0
140
120
100
80
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MODE = 1
-10
-20
-30
-40
-50
-60
-70
R
= 32I
HP
MODE = 0
60
R
= 16I
PH
40
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
20
R
= 32I
R
= 32I
PH
HP
-80
10
0
100
1000
10,000
100,000
0.01
0.1
1
10
100
FREQUENCY (Hz)
OUTPUT POWER PER CHANNEL (mW)
PVDD CURRENT vs. OUTPUT POWER
(DAC TO HEADPHONE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
100
90
80
70
60
50
40
30
20
10
0
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
MCLK = 12.288MHz
LRCLK = 48kHz
LOW POWER MODE
V
= 200mV
V
= 200mV
RIPPLE P-P
RIPPLE
P-P
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
LOW POWER MODE
AV
= +3dB
HP_
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON AVDD,
DVDD, HPVDD
RIPPLE ON SPKLVDD,
SPKRVDD
R
= 16I
PH
RIPPLE ON SPKLVDD,
SPKRVDD
R
= 32I
PH
0.01
0.1
1
10
100
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
OUTPUT POWER PER CHANNEL (mW)
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 46
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
CROSSTALK vs. FREQUENCY
(DAC TO HEADPHONE)
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 0)
MAX98088 toc101
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
SCL
1V/div
R
= 32I
HP
RIGHT TO LEFT
HEADPHONE
OUTPUT
1V/div
LEFT TO RIGHT
-100
10
100
1000
10,000
100,000
10ms/div
FREQUENCY (Hz)
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 1)
MAX98088 toc102
SCL
1V/div
HEADPHONE
OUTPUT
1V/div
10ms/div
���������������������������������������������������������������� Maxim Integrated Products 47
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
FFT, 0dBFS (DAC TO HEADPHONE)
FFT, -60dBFS (DAC TO HEADPHONE)
FFT, 0dBFS (DAC TO HEADPHONE)
20
0
0
20
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
-20
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-40
-60
R
= 32I
R
= 32I
R
= 32I
HP
HP
HP
-80
-100
-120
-140
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
FFT, 0dBFS (DAC TO HEADPHONE)
FFT, -60dBFS (DAC TO HEADPHONE)
20
0
0
-20
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
-20
-40
-60
-80
-100
-120
-140
-40
R
HP
= 32I
R
HP
= 32I
-60
-80
-100
-120
-140
-160
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
���������������������������������������������������������������� Maxim Integrated Products 48
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
SPK_ A
REC
FFT, -60dBFS (DAC TO HEADPHONE)
FFT, 0dBFS (DAC TO HEADPHONE)
0
-20
20
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
-40
-20
-40
-60
-80
-100
-120
-140
R
HP
= 32I
R
HP
= 32I
-60
-80
-100
-120
-140
-160
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
FFT, -60dBFS (DAC TO HEADPHONE)
FFT, -60dBFS (DAC TO HEADPHONE)
0
-20
0
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
LOW POWER MODE
-20
-40
-40
R
HP
= 32I
R
HP
= 32I
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
5
10
15
20
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
���������������������������������������������������������������� Maxim Integrated Products 49
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
WIDEBAND FFT 0BFS
(DAC TO HEADPHONE)
FFT, -60dBFS (DAC TO HEADPHONE)
0
-20
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
LOW POWER MODE
-20
-40
R
HP
= 32I
R
HP
= 32I
-40
-60
-80
-60
-80
-100
-100
-120
-120
-140
0
1
10
100
1000 10,000
0
5
10
15
20
FREQUENCY (kHz)
FREQUENCY (kHz)
WIDEBAND FFT 0BFS
(DAC TO HEADPHONE)
WIDEBAND FFT -60dBFS
(DAC TO HEADPHONE)
WIDEBAND FFT -60dBFS
(DAC TO HEADPHONE)
0
0
-20
0
-20
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
= 32I
LOW POWER MODE
-20
-40
R
HP
= 32I
R
HP
= 32I
R
HP
-40
-40
LOW POWER MODE
-60
-60
-60
-80
-80
-80
-100
-120
-100
-120
-100
-120
0
1
10
100
1000 10,000
0.1
1
10
100
1000 10,000
0.1
1
10
100
1000 10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
���������������������������������������������������������������� Maxim Integrated Products 50
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Line to Headphone
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(LINE TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO HEADPHONE)
0
0
R
AV
C
= 32I
R
AV
C
= 32I
HP
HP
-10
-10
= +3dB
= +3dB
HP_
HP_
= 1µF
= 1µF
-20
-30
-40
-50
-60
-70
IN
-20
-30
-40
-50
-60
-70
IN
f = 100Hz
P
= 0.020W
OUT
f = 6000Hz
0.04
-80
-90
-80
-90
f = 1000Hz
0.02
P
= 0.01W
OUT
10
100
1000
FREQUENCY (Hz)
10,000
100,000
0
0.01
0.03
0.05
OUTPUT POWER (W)
GAIN vs. FREQUENCY
(LINE TO HEADPHONE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
CROSSTALK vs. FREQUENCY
(LINE TO HEADPHONES)
5
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
R
C
= 32I
= 1µF
V
= 200mV
R = 32I
HP
HP
IN
RIPPLE
P-P
4
3
2
1
RIPPLE ON AVDD,
DVDD, HPVDD
0
-1
-2
RIPPLE ON SPKLVDD,
SPKRVDD
-3
-4
-5
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
���������������������������������������������������������������� Maxim Integrated Products 51
MAX98088
Stereo Audio Codec
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z ) connected between
SPK
PVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
SPK_P and SPK_N. Receiver load (R ) connected between RECP and RECN. Headphone loads (R ) connected from HPL or HPR to
REC HP
HPGND. R = J, R
= J, Z
= J, C
= 2.2FF, C
= C
= 1FF, C
= 1FF, C
= C = 1FF. AV
HPVSS MICPRE_
HP
REC
SPK
REF
MICBIAS
REG
C1N-C1P
HPVDD
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
=
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
PGAIN_
HP_
0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1. T = +25NC, unless otherwise noted.)
REC
SPK_
A
Speaker Bypass Switch
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(SPEAKER BYPASS SWITCH)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONES)
0
-10
-20
-30
-40
-50
-60
-70
-80
100
90
80
70
60
50
40
30
20
10
0
RECEIVER AMPLIFIER
DRIVING LOUDSPEAKER
AV
= 20dB
PREGAIN
Z
SPK
= 8I + 68µH
AV
= 0dB
PREGAIN
f = 1000kHz
f = 6000Hz
V
= -6dBV
OUT
f = 100Hz
C
= 1µF
= 32I
IN
R
HP
0
0.05
0.10
0.15
0.20
0.25
10
100
1000
FREQUENCY (Hz)
10,000
100,000
OUTPUT POWER (W)
ON-RESISTANCE vs. VCOM
(SPEAKER BYPASS SWITCH)
OFF-ISOLATION vs. FREQUENCY
(SPEAKER BYPASS SWITCH)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
-20
I
= 20mA
V
= 3.0V
SW
SPK_VDD
SPEAKER AMP DRIVING LOUDSPEAKER
SPEAKER BYPASS SWITCH OPEN
MEASURED AT RXIN_
-40
-60
V
= 3.7V
50I LOAD ON RXIN_
SPK_VDD
V
= 5.0V
SPK_VDD
-80
V
= 4.2V
SPK_VDD
RECEIVER AMP DRIVING RXIN_
-100
-120
0
1
2
3
4
5
6
10
100
1000
10,000
100,000
V
(V)
FREQUENCY (Hz)
COM
���������������������������������������������������������������� Maxim Integrated Products 52
MAX98088
Stereo Audio Codec
with FlexSound Technology
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
6
7
8
9
RECP/
LOUTL/
RXINP
SPKRN
SPKRGND
SPKLVDD
SPKLP
SPKLN
PVDD
HPVSS
HPGND
A
B
C
D
E
RECN/
LOUTR/
RXINN
SPKRN
SPKRP
SPKRGND
SPKRP
SPKLVDD
SPKRVDD
SPKLP
SPKLN
C1P
N.C.
C1N
HPVDD
HPL
SPKLGND
SPKLGND
N.C
HPSNS
MAX98088
BCLKS1
SDOUTS1
SPKRVDD
LRCLKS1
N.C.
N.C.
N.C.
INB2
HPR
INA2/
EXTMICN
MIC1P/
DIGMICDATA
DVDDS1
DGND
MCLK
N.C.
SDINS1
SDA
IRQ
SCL
JACKSNS
INB1
MICBIAS
AGND
MIC1N/
DIGMICCLK
INA1/
EXTMICP
BCLKS2
DVDDS2
LRCLKS2
SDINS2
REG
F
SDOUTS2
DVDD
AVDD
REF
MIC2N
MIC2P
G
���������������������������������������������������������������� Maxim Integrated Products 53
MAX98088
Stereo Audio Codec
with FlexSound Technology
Pin Description
PIN
NAME
SPKRN
FUNCTION
A1, B1
A2, B2
Negative Right-Channel Class D Speaker Output
SPKRGND
Right-Speaker Ground
Left-Speaker, REF, Receiver Amp Power Supply. Bypass to SPKLGND with a 1FF and a
10FF capacitor.
A3, B3
SPKLVDD
A4, B4
A5, B5
SPKLP
SPKLN
Positive Left-Channel Class D Speaker Output
Negative Left-Channel Class D Speaker Output
RECP/LOUTL/
RXINP
Positive Receiver Amplifier Output or Left Line Output. Can be positive bypass switch input
when receiver amp is shut down.
A6
A7
A8
A9
PVDD
HPVSS
HPGND
Headphone Power Supply. Bypass to HPGND with 1FF and 10FF capacitors.
Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
Headphone Ground
RECN/LOUTR/
RXINN
Negative Receiver Amplifier Output or Right Line Output. Can be negative bypass switch
input when receiver amp is shut down.
B6
B7
B8
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor
between C1N and C1P.
C1P
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor
between C1N and C1P.
B9
HPVDD
SPKRP
Noninverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
Positive Right-Channel Class D Speaker Output
C1, C2
C3, D3
C4, C5
SPKRVDD
SPKLGND
Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
Left-Speaker Ground
C6, C7, D5, D6,
D7, E3
N.C.
No Connection
Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or
connect to ground.
C8
C9
D1
D2
HPSNS
HPL
Left-Channel Headphone Output
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the IC is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDS1.
BCLKS1
SDOUTS1
S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1.
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock
and determines whether S1 audio data is routed to the left or right channel. In TDM mode,
LRCLKS1 is a frame sync pulse. LRCLKS1 is an input when the IC is in slave mode and an
output when in master mode.
D4
LRCLKS1
D8
D9
E1
E2
E4
INB2
HPR
Single-Ended Line Input B2. Also positive differential line input B.
Right-Channel Headphone Output
DVDDS1
MCLK
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
S1 Digital Audio Serial-Data DAC Input. The input/output voltage is referenced to DVDDS1.
SDINS1
���������������������������������������������������������������� Maxim Integrated Products 54
MAX98088
Stereo Audio Codec
with FlexSound Technology
Pin Description (continued)
PIN
NAME
FUNCTION
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register
0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults have
no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10kI
pullup resistor to DVDD for full output swing.
E5
IRQ
E6
E7
JACKSNS
INB1
Jack Sense. Detects the insertion of a jack. See the Jack Detection section.
Single-Ended Line Input B1. Also negative differential line input B.
MIC1P/
DIGMICDATA
Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capaci-
tor. Can be retasked as a digital microphone data input.
E8
INA2/
EXTMICN
Single-Ended Line Input A2. Also positive differential line input A or negative differential
external microphone input.
E9
F1
F2
DGND
Digital Ground
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDS2.
BCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock
and determines whether audio data on S2 is routed to the left or right channel. In TDM
mode, LRCLKS2 is a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode
and an output when in master mode. The input/output voltage is referenced to DVDDS2.
F3
LRCLKS2
F4
F5
F6
SDA
SCL
REG
I2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
I2C Serial-Clock Input. Connect a pullup resistor to DVDD for full output swing.
Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external 2.2kI resistor
should be placed between MICBIAS and the microphone output.
F7
F8
F9
MICBIAS
MIC1N/
DIGMICCLK
Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF
capacitor. Can be retasked as a digital microphone clock output.
INA1/
EXTMICP
Single-Ended Line Input A1. Also negative differential line input A or positive differential
external microphone input.
G1
G2
G3
SDOUTS2
DVDDS2
SDINS2
S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2.
S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2.
Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a
1FF capacitor.
G4
DVDD
G5
G6
G7
AVDD
REF
Analog Power Supply. Bypass to AGND with a 1FF capacitor.
Converter Reference. Bypass to AGND with a 2.2FF capacitor.
Analog Ground
AGND
Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF
capacitor.
G8
G9
MIC2N
MIC2P
Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
���������������������������������������������������������������� Maxim Integrated Products 55
MAX98088
Stereo Audio Codec
with FlexSound Technology
When the receiver amplifier is disabled, analog switches
Detailed Description
allow RECP/RXINP and RECN/RXINN to be reused for
signal routing. In systems where a single transducer is
used for both the loudspeaker and receiver, an exter-
nal receiver amplifier can be routed to the left speaker
through RECP/RXINP and RECN/RXINN, bypassing the
Class D amplifier, to connect to the loudspeaker. If the
internal receiver amplifier is used, then leave RECP/
RXINP and RECN/RXINN unconnected. In systems
where an external amplifier drives both the receiver and
the MAX98088’s line input, one of the differential signals
can be disconnected from the receiver when not needed
by passing it through the analog switch that connects
RECP/RXINP to RECN/RXINN.
The MAX98088 is a fully integrated stereo audio codec
with FlexSound technology and integrated amplifiers.
Two differential microphone amplifiers can accept signals
from three analog inputs. One input can be retasked to
support two digital microphones. Any combination of two
microphones (analog or digital) can be recorded simul-
taneously. The analog signals are amplified up to 50dB
and recorded by the stereo ADC. The digital record path
supports voice filtering with selectable preset highpass
filters and high stopband attenuation at f /2. An automat-
S
ic gain control (AGC) circuit monitors the digitized signal
and automatically adjusts the analog microphone gain
to make best use of the ADC’s dynamic range. A noise
gate attenuates signals below the user-defined threshold
to minimize the noise output by the ADC.
The stereo Class D amplifier provides efficient amplifica-
tion for two speakers. The amplifier includes active emis-
sions limiting to minimize the radiated emissions (EMI)
traditionally associated with Class D. In most systems,
no output filtering is required to meet standard EMI limits.
The IC includes two analog line inputs. One of the line
inputs can be optionally retasked as a third analog micro-
phone input. Both line inputs support either stereo single-
ended input signals or mono differential signals. The line
inputs are preamplified and then routed to the ADC for
recording and/or to the output amplifiers for playback.
The single-ended line input signals from INA1 and INA2
can bypass the PGAs, and be connected directly to the
ADC input to provide the best dynamic range.
To optimize speaker sound quality, the IC includes an
excursion limiter, a distortion limiter, and a power limiter.
The excursion limiter is a dynamic highpass filter with
variable corner frequency that increases in response
to high signal levels. Low-frequency energy typically
causes more distortion than useful sound at high sig-
nal levels, so attenuating low frequencies allows the
speaker to play louder without distortion or damage. At
lower signal levels, the filter corner frequency reduces
to pass more low frequency energy when the speaker
can handle it. The distortion limiter reduces the volume
when the output signal exceeds a preset distortion level.
This ensures that regardless of input signal and battery
voltage, excessive distortion is never heard by the user.
The power limiter monitors the continuous power into the
loudspeaker and lowers the signal level if the speaker is
at risk of overheating.
Integrated analog switches allow two differential micro-
phone signals to be routed out the third microphone input
to an external device. This eliminates the need for an
external analog switch in systems that have two devices
recording signals from the same microphone.
Through two digital audio interfaces, the device can
transmit one stereo audio signal and receive two stereo
audio signals in a wide range of formats including I2S,
PCM, and up to four mono slots in TDM. Each interface
can be connected to either of two audio ports (S1 and
S2) for communication with external devices. Both audio
interfaces support 8kHz to 96kHz sample rates. Each
input signal is independently equalized using 5-band
parametric equalizers. A multiband automatic level con-
trol (ALC) boosts signals by up to 12dB. One signal path
additionally supports the same voiceband filtering as the
ADC path.
The stereo Class H headphone amplifier uses a dual-
mode charge pump to maximize efficiency while out-
putting a ground-referenced signal. This eliminates the
need for DC-blocking capacitors or a midrail bias for the
headphone jack ground return. Ground sense reduces
output noise caused by ground return current.
The IC integrates jack detection allowing the detection of
insertion and removal of accessories.
The IC includes a stereo Class D speaker amplifier, a
high-efficiency Class H stereo headphone amplifier, and
a differential receiver amplifier that can be configured as
a stereo single-ended line output.
���������������������������������������������������������������� Maxim Integrated Products 56
MAX98088
Stereo Audio Codec
with FlexSound Technology
2
I C Slave Address
Configure the MAX98088 using the I2C control bus. The
IC uses a slave address of 0x20 or 00100000 for write
operations and 0x21 or 00100001 for read operations.
See the I2C Serial Interface section for a complete inter-
face description.
Registers
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Registers 0x00 to 0x03 and 0xFF
are read-only while all of the other registers are read/
write. Write zeros to all unused bits in the register table
when updating the register, unless otherwise noted.
Table 1. Register Map
REGISTER
STATUS
Status
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
CLD
SLD
NG
ULK
—
—
—
AGC
—
JDET
—
0x00
0x01
0x02
0x03
—
—
—
—
R
R
R
111
70
Microphone
AGC/NG
Jack Status
—
—
JKSNS
—
—
—
—
0
—
—
—
110
Battery
Voltage
VBAT
R/W 110
R/W 111
Interrupt
Enable
ICLD
ISLD
IULK
0
0
0
0
IJDET
0
0
0
0x0F
0x10
0x00
0x00
MASTER CLOCK CONTROL
Master Clock
0
0
PSCLK
R/W
81
DAI1 CLOCK CONTROL
Clock Mode
SR1
FREQ1
0x11
0x12
0x13
0x00
0x00
0x00
R/W 81, 82
PLL1
NI1[14:8]
R/W
R/W
82
82
Any Clock
Control
NI1[7:1]
NI1[0]
WS1
DAI1 CONFIGURATION
Format
Clock
MAS1
WCI1
BCI1
DLY1
0
0
0
TDM1
FSW1
0x14
0x15
0x00
0x00
R/W
R/W
76
77
ADC_OSR1
DAC_ORS1
BSEL1
I/O
SEL1
LTEN1
LBEN1 DMONO1 HIZOFF1 SDOEN1 SDIEN1
SLOTDLY1
DVFLT1
0x16
0x00
R/W 77, 78
Configuration
Time-Division
Multiplex
SLOTL1
SLOTR1
0x17
0x18
0x00
0x00
R/W
R/W
78
86
Filters
MODE1
AVFLT1
DHF1
DAI2 CLOCK CONTROL
Clock Mode
SR2
0
0
0
0
0x19
0x1A
0x1B
0x00
0x00
0x00
R/W
R/W
R/W
81
82
82
PLL2
NI2[14:8]
Any Clock
Control
NI2[7:1]
NI2[0]
WS2
DAI2 CONFIGURATION
Format
MAS2
WCI2
0
BCI2
DLY2
0
0
0
TDM2
FSW2
0x1C
0x1D
0x00
0x00
R/W
R/W
76
77
DAC_
ORS2
Clock
0
BSEL2
I/O
SEL2
0
LBEN2 DMONO2 HIZOFF2 SDOEN2 SDIEN2
0x1E
0x00
R/W 77, 78
Configuration
���������������������������������������������������������������� Maxim Integrated Products 57
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
Time-Division
Multiplex
SLOTL2
SLOTR2
SLOTDLY2
0x1F
0x20
0x00
0x00
R/W
R/W
78
86
Filters
SRC
0
0
0
0
0
0
DHF2
0
0
DCB2
Sample Rate
Converter
SRMIX_ SRMIX_
MODE ENL
SRMIX_
ENR
SRC_
ENL
SRC_
ENR
0
0x21
0x00
R/W
85
MIXERS
DAC Mixer
MIXDAL
MIXDAR
0x22
0x23
0x00
0x00
R/W
R/W
92
69
Left ADC
Mixer
MIXADL
Right ADC
Mixer
MIXADR
MIXHPL
0x24
0x25
0x00
0x00
R/W
69
Left
Headphone
Amplifier
Mixer
R/W 105
Right
Headphone
Amplifier
Mixer
MIXHPR
0x26
0x00
R/W 105
R/W 105
Headphone
Amplifier
Mixer Control
MIXHPR_ MIXHPL_
PATHSEL PATHSEL
0
0
0
0
MIXHPR_GAIN
MIXHPL_GAIN
MIXRECL_GAIN
MIXSPL_GAIN
0x27
0x28
0x00
0x00
Left Receiver
Amplifier
Mixer
MIXRECL
R/W
R/W
94
94
Right
Receiver
Amplifier
Mixer
MIXRECR
0x29
0x00
Receiver
Amplifier
Mixer Control
LINE_
MODE
0
0
MIXRECR_GAIN
0x2A
0x2B
0x00
0x00
R/W
R/W
94
97
Left Speaker
Amplifier
Mixer
MIXSPL
MIXSPR
Right
Speaker
Amplifier
Mixer
0x2C
0x2D
0x00
0x00
R/W
R/W
97
97
Speaker
Amplifier
0
0
0
MIXSPR_GAIN
Mixer Control
���������������������������������������������������������������� Maxim Integrated Products 58
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
LEVEL CONTROL
Sidetone
DSTS
0
DVST
0x2E
0x2F
0x00
0x00
R/W
R/W
74
91
DAI1
Playback
Level
DV1M
0
0
0
0
DV1G
DV1
DAI1
Playback
Level
0
0
0
0
DVEQ1
DV2
0x30
0x31
0x32
0x00
0x00
0x00
R/W
R/W
R/W
90
91
90
EQCLP1
DAI2
Playback
Level
DAI2
Playback
Level
DV2M
0
0
DVEQ2
EQCLP2
Left ADC
Level
Right ADC
Level
Microphone
1 Input Level
Microphone
2 Input Level
INA Input
Level
0
0
0
0
0
0
0
0
AVLG
AVRG
AVL
AVR
0x33
0x34
0x35
0x36
0x37
0x38
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
73
73
66
66
68
68
PA1EN
PA2EN
PGAM1
PGAM2
INAEXT
INBEXT
0
0
0
0
0
0
PGAINA
PGAINB
INB Input
Level
Left
Headphone
Amplifier
Volume
Control
HPLM
0
0
HPVOLL
0x39
0x00
R/W 106
R/W 106
Right
Headphone
Amplifier
Volume
Control
HPRM
RECLM
RECRM
0
0
0
0
0
0
HPVOLR
RECVOLL
RECVOLR
0x3A
0x3B
0x3C
0x00
0x00
0x00
Left Receiver
Amplifier
Volume
R/W
R/W
95
95
Control
Right
Receiver
Amplifier
Volume
Control
���������������������������������������������������������������� Maxim Integrated Products 59
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
Left Speaker
Amplifier
Volume
SPLM
0
0
SPVOLL
0x3D
0x3E
0x00
0x00
R/W
R/W
98
98
Control
Right
Speaker
Amplifier
Volume
Control
SPRM
0
0
SPVOLR
MICROPHONE AGC
Configuration AGCSRC
Threshold
AGCRLS
AGCATK
AGCHLD
0x3F
0x40
0x00
0x00
R/W 70, 71
R/W 71
ANTH
AGCTH
SPEAKER SIGNAL PROCESSING
Excursion
0
DHPUCF
0
0
0
DHPLCF
0x41
0x42
0x00
0x00
R/W 100
R/W 100
Limiter Filter
Excursion
Limiter
0
0
0
0
DHPTH
Threshold
ALC
ALCEN
ALCRLS
ALCMB
0
ALCTH
PWRK
0x43
0x44
0x45
0x00
0x00
0x00
R/W 89, 100
R/W 101
R/W 102
Power Limiter
Power Limiter
PWRTH
PWRT2
PWRT1
Distortion
Limiter
THDCLP
0
0
0
THDT1
0
0x46
0x00
R/W 103
CONFIGURATION
Audio Input INADIFF INBDIFF
0
0
0
0
0
0
0
0
0
0x47
0x48
0x49
0x00
0x00
0x00
R/W
R/W
68
66
Microphone
MICCLK
DIGMICL DIGMICR
EXTMIC
Level Control
0
EQ2EN EQ1EN
R/W 90, 108
VS2EN VSEN
ZDEN
Bypass
Switches
67,
R/W
INABYP
JDETEN
0
0
0
MIC2BYP
0
0
0
0
RECBYP SPKBYP
0x4A
0x4B
0x00
0x00
107
Jack
Detection
0
0
JDEB
R/W 110
POWER MANAGEMENT
Input Enable INAEN INBEN
Output
Enable
0
0
MBEN
0
ADLEN ADREN
0x4C
0x4D
0x00
0x00
R/W
R/W
63
64
HPLEN HPREN SPLEN
SPREN RECLEN RECREN DALEN DAREN
Top-Level
Bias Control
DAC Low
Power
BGEN SPREGEN VCMEN BIASEN
DAI2_DAC_LP
0
0
0
0
0x4E
0x4F
0xF0
0x00
R/W
R/W
64
83
DAI1_DAC_LP
Mode 1
DAC Low
Power
Mode 2
DAC2_IP_ DAC1_IP_ CGM2_ CGM1_
DITH_EN DITH_EN EN EN
0
0
0
0
0
0
0x50
0x51
0x0F
0x00
R/W
R/W
83
System
Shutdown
63,
100
VBATEN
PERFMODE HPPLYBACK PWRSV8K PWRSV
SHDN
���������������������������������������������������������������� Maxim Integrated Products 60
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
DSP COEFFICIENTS
K_1[15:8]
0x52/0x84
0x53/0x85
0x54/0x86
0x55/0x87
0x56/0x88
0x57/0x89
0x58/0x8A
0x59/0x8B
0x5A/0x8C
0x5B/0x8D
0x5C/0x8E
0x5D/0x8F
0x5E/0x90
0x5F/0x91
0x60/0x92
0x61/0x93
0x62/0x94
0x63/0x95
0x64/0x96
0x65/0x97
0x66/0x98
0x67/0x99
0x68/0x9A
0x69/0x9B
0x6A/0x9C
0x6B/0x9D
0x6C/0x9E
0x6D/0x9F
0x6E/0xAE
0x6F/0xA1
0x70/0xA2
0x71/0xA3
0x72/0xA4
0x73/0xA5
0x74/0xA6
0x75/0xA7
0x76/0xA8
0x77/0xA9
0x78/0xAA
0x79/0xAB
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
K_1[7:0]
K1_1[15:8]
K1_1[7:0]
K2_1[15:8]
K2_1[7:0]
c1_1[15:8]
c1_1[7:0]
c2_1[15:8]
c2_1[7:0]
K_2[15:8]
K_2[7:0]
EQ Band 1
(DAI1/DAI2)
K1_2[15:8]
K1_2[7:0]
K2_2[15:8]
K2_2[7:0]
c1_2[15:8]
c1_2[7:0]
c2_2[15:8]
c2_2[7:0]
K_3[15:8]
K_3[7:0]
EQ Band 2
(DAI1/DAI2)
K1_3[15:8]
K1_3[7:0]
K2_3[15:8]
K2_3[7:0]
c1_3[15:8]
c1_3[7:0]
c2_3[15:8]
c2_3[7:0]
K_4[15:8]
K_4[7:0]
EQ Band 3
(DAI1/DAI2)
K1_4[15:8]
K1_4[7:0]
K2_4[15:8]
K2_4[7:0]
c1_4[15:8]
c1_4[7:0]
c2_4[15:8]
c2_4[7:0]
EQ Band 4
(DAI1/DAI2)
���������������������������������������������������������������� Maxim Integrated Products 61
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
K_5[15:8]
0x7A/0xAC
0x7B/0xAD
0x7C/0xAE
0x7D/0xAF
0x7E/0xB0
0x7F/0xB1
0x80/0xB2
0x81/0xB3
0x82/0xB4
0x83/0xB5
0xB6/0xC0
0xB7/0xC1
0xB8/0xC2
0xB9/0xC3
0xBA/0xC4
0xBB/0xC5
0xBC/0xC6
0xBD/0xC7
0xBE/0xC8
0xBF/0xC9
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
89
K_5[7:0]
K1_5[15:8]
K1_5[7:0]
K2_5[15:8]
K2_5[7:0]
c1_5[15:8]
c1_5[7:0]
c2_5[15:8]
c2_5[7:0]
a1[15:8]
a1[7:0]
EQ Band 5
(DAI1/DAI2)
a2[15:8]
a2[7:0]
Excursion
Limiter
Biquad
b0[15:8]
b0[7:0]
(DAI1/DAI2)
b1[15:8]
b1[7:0]
b2[15:8]
b2[7:0]
REVISION ID
Rev ID
REV
0xFF
0x40
R
112
���������������������������������������������������������������� Maxim Integrated Products 62
MAX98088
Stereo Audio Codec
with FlexSound Technology
Power Management
The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply
current.
Table 2. Power Management Registers
REGISTER
BIT
NAME
DESCRIPTION
Global Shutdown. Disables everything except the headset detection circuitry, which is
controlled separately.
0 = Device shutdown
1 = Device enabled
7
SHDN
6
3
VBATEN
See the Battery Measurement section.
Performance Mode. Selects DAC to headphone playback performance mode.
0 = High performance playback mode.
PERFMODE
1 = Low power playback mode.
Headphone Only Playback Mode. Configures System Bias Control register bits for low
power playback when using DAC to headphone playback path only. When enabled,
this bit overrides the System Bias Control register settings. When disabled, the System
Bias Control register is used to enable system bias blocks. Set both HPPLYBCK and
PERFMODE for lowest power consumption when using DAC to headphone playback
path only.
2
1
HPPLYBCK
PWRSV8K
0x51
0 = Disabled
1 = Enabled
8kHz Power Save Mode. PWRSV8K configures the ADC for reduced power consump-
tion when f = 8kHz. PWRSV8K can be used in conjunction with PWRSV when f = 8kHz
S
S
for more power savings.
0 = Normal, high-performance mode.
1 = Low power mode.
Power Save Mode. PWRSV configures the ADC for reduced power consumption for all
sample rates. PWRSV can be used in conjunction with PWRSV8K for more power sav-
0
7
PWRSV
INAEN
ings.
0 = Normal, high-performance mode.
1 = Low power mode.
Line Input A Enable
0 = Disabled
1 = Enabled
Line Input B Enable
0 = Disabled
1 = Enabled
6
3
1
0
INBEN
MBEN
Microphone Bias Enable
0 = Disabled
1 = Enabled
0x4C
Left ADC Enable
0 = Disabled
1 = Enabled
ADLEN
ADREN
Right ADC Enable
0 = Disabled
1 = Enabled
���������������������������������������������������������������� Maxim Integrated Products 63
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 2. Power Management Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
Left Headphone Enable
0 = Disabled
7
HPLEN
1 = Enabled
Right Headphone Enable
0 = Disabled
1 = Enabled
6
5
4
HPREN
SPLEN
SPREN
Left Speaker Enable
0 = Disabled
1 = Enabled
Right Speaker Enable
0 = Disabled
1 = Enabled
0x4D
Receiver/Left Line Output Enable. Use this bit to enable the differential receiver output
or left line output.
0 = Disabled
1 = Enabled
3
RECLEN
Right Line Output Enable. Use this bit to enable the right line output.
2
1
0
RECREN
DALEN
DAREN
0 = Disabled
1 = Enabled
Left DAC Enable
0 = Disabled
1 = Enabled
Right DAC Enable
0 = Disabled
1 = Enabled
Bandgap Enable. Must be enabled for proper operation of 2.5V regulator and associ-
ated circuitry.
0 = Disabled
1 = Enabled
7
6
BGEN
2.5V Regulator Enable. SPREGEN enables a 2.5V internal regulator required for
the ADC, speaker and receiver/line out amplifier. The 2.5V regulator is powered by
SPKLVDD.
SPREGEN
0 = Disabled
1 = Enabled
0x4E
Common-Mode Voltage Resistor String Enable. VCMEN enables the common mode
voltage for the input and output amplifiers in the codec.
0 = Disabled
1 = Enabled
5
4
VCMEN
BIASEN
Chip Bias Enable. BIASEN needs to be set for the codec amplifiers to be enabled.
0 = Disabled
1 = Enabled
���������������������������������������������������������������� Maxim Integrated Products 64
MAX98088
Stereo Audio Codec
with FlexSound Technology
In systems where the codec is not the only device
recording microphone signals, connect microphones to
MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N
then become outputs that route the microphone signals
to an external device as needed. Two devices can then
record microphone signals without needing external
analog switches.
Microphone Inputs
The device includes three differential microphone inputs
and a low-noise microphone bias for powering the micro-
phones (Figure 6). One microphone input can also be con-
figured as a digital microphone input accepting signals
from up to two digital microphones. Any two microphones,
analog or digital, can be recorded simultaneously.
Analog microphone signals are amplified by two stages
of gain and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable-gain amplifier (PGA) adjustable
from 0dB to 20dB in 1dB steps. To maximize the signal-
to-noise ratio, use the gain in the first stage whenever
possible. Zero-crossing detection is included on the PGA
to minimize zipper noise while making gain changes.
In the typical application, one microphone input is used
for the handset microphone and the other is used as an
accessory microphone. In systems using a background
noise microphone, INA can be retasked as another
microphone input.
MCLK
MICBIAS
REG
CLOCK
CONTROL
MBEN
MIC1P/
DIGMICDATA
PGAM1:
+20dB TO 0dB
MIC1N/
DIGMICCLK
AGC CONTROL
EXTMIC
PA1EN:
0/20/30dB
MIC2BYP
ADLEN
MIX
MIC2P
MIC2N
ADCL
PGAM1:
+20dB TO 0dB
MIXADL
EXTMIC
PA2EN:
0/20/30dB
INABYP
MIX
PGAINA:
+20dB TO -6dB
ADCR
ADREN
INA1/EXTMICP
INA2/EXTMICN
INADIFF
MIXADR
PGAINA:
+20dB TO -6dB
Figure 6. Microphone Input Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 65
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 3. Microphone Input Registers
REGISTER
BIT
NAME
DESCRIPTION
MIC1/MIC2 Preamplifier Gain
6
Course microphone gain adjustment.
00 = Preamplifier disabled
01 = 0dB
PA1EN/PA2EN
10 = 20dB
11 = 30dB
5
4
MIC1/MIC2 PGA
Fine microphone gain adjustment.
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
VALUE
0x0B
GAIN (dB)
3
2
1
0
7
6
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
0x35/0x36
+19
0x0C
+18
0x0D
+17
0x0E
PGAM1/PGAM2
+16
0x0F
+15
0x10
+14
0x11
+13
0x12
+12
0x13
+11
0x14 to 0x1F
+10
Digital Microphone Clock Frequency
Select a frequency that is within the digital microphone’s clock frequency range.
Set OSR1 = 1 when using a digital microphone.
00 = PCLK/8
01 = PCLK/6
MICCLK
10 = 64 x LRCLK
11 = Reserved
Left Digital Microphone Enable
Set PA1EN = 00 for proper operation.
0 = Disabled
5
4
DIGMICL
DIGMICR
1 = Enabled
0x48
Right Digital Microphone Enable
Set PA1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
External Microphone Connection
Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using
INA_/EXTMIC_ as a microphone input.
00 = Disabled
01 = MIC1 input
10 = MIC2 input
1
0
EXTMIC
11 = Reserved
���������������������������������������������������������������� Maxim Integrated Products 66
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 3. Microphone Input Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
INA�/EXTMIC� to MIC1� Bypass Switch
7
INABYP
0 = Disabled
1 = Enabled
MIC1� to MIC2� Bypass Switch
0 = Disabled
1 = Enabled
4
1
0
MIC2BYP
RECBYP
SPKBYP
0x4A
See the Output Bypass Switches section.
by choosing the appropriate input resistor and using the
following formula:
AV
Line Inputs
The device includes two sets of line inputs (Figure 7).
Each set can be configured as a stereo single-ended
input or as a mono differential input. Each input includes
adjustable gain to match a wide range of input signal
levels. If a custom gain is needed, the external gain
mode provides a trimmed feedback resistor. Set the gain
= 20 x log (20kI/R )
PGAIN
IN
The external gain mode also allows summing multiple
signals into a single input, by connecting multiple input
resistors as show in Figure 8, and/or inputting signals
larger than 1V
less than 1.
by adjusting the ratio of the 20kI/R
P-P
IN
INABYP
PGAINA:
+20dB TO -6dB
INA1/
EXTMICP
INADIFF
PGAINA:
+20dB TO -6dB
LEFT
INPUT 1
20kI
INA2/
EXTMICN
LEFT
INA1/EXTMICP
INA2/EXTMICN
1V (max)
P-P
INPUT 2
PGAINB:
+20dB TO -6dB
VCM
VCM
RIGHT
INPUT 1
20kI
INB1
INBDIFF
RIGHT
INPUT 2
1V (max)
P-P
PGAINB:
+20dB TO -6dB
INB2
Figure 7. Line Input Block Diagram
Figure 8. Summing Multiple Input Signals into INA/INB
���������������������������������������������������������������� Maxim Integrated Products 67
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 4. Line Input Registers
REGISTER
BIT
NAME
DESCRIPTION
Line Input A/B External Gain
Switches out the internal input resistor and selects a trimmed 20kI feedback resistor.
6
INAEXT/INBEXT
Use an external input resistor to set the gain of the line input.
0 = Disabled
1 = Enabled
Line Input A/B Internal Gain Settings
000 = +20dB
001 = +14dB
2
1
0
0x37/0x38
010 = +3dB
PGAINA/PGAINB 011 = 0dB
100 = -3dB
101 = -6dB
110 = -6dB
111 = -6dB
Line Input A Differential Enable
7
6
INADIFF
INBDIFF
0 = Stereo single-ended input
1 = Mono differential input
0x47
Line Input B Differential Enable
0 = Stereo single-ended input
1 = Mono differential input
ADC Input Mixers
PGAM1:
The IC’s stereo ADC accepts input from the microphone
amplifiers, line inputs amplifiers, and directly from the
INA1 and INA2. The ADC mixer routes any combina-
tion of the eight audio inputs to the left and right ADCs
(Figure 9).
+20dB TO 0dB
PA1EN:
0/20/30dB
PGAM2:
+20dB TO 0dB
ADLEN
ADCL
MIX
MIXADL
PA2EN:
0/20/30dB
MIX
ADCR
ADREN
PGAINA:
+20dB TO -6dB
MIXADR
INADIFF
PGAINA:
+20dB TO -6dB
+
+
PGAINB:
+20dB TO -6dB
INBDIFF
PGAINB:
+20dB TO -6dB
Figure 9. ADC Input Mixer Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 68
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 5. ADC Input Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
7
Left/Right ADC Input Mixer
Selects which analog inputs are recorded by the left/right ADC.
1xxxxxxx = MIC1
x1xxxxxx = MIC2
xx1xxxxx = INA1 pin direct
xxx1xxxx = INA2 pin direct
xxxx1xxx = INA1
xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xxxxxx1x = INB1
6
5
4
0x23/0x24
MIXADL/MIXADR
3
2
1
xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
0
Noise Gate
Since the AGC increases the levels of all signals below
a user-defined threshold, the noise floor is effectively
increased by 20dB. To counteract this, the noise gate
reduces the gain at low signal levels. Unlike typical noise
gates that completely silence the output below a defined
level, the noise gate in the IC applies downward expan-
sion. The noise gate attenuates the output at a rate of
1dB for each 2dB the signal is below the threshold with a
maximum attenuation of 12dB.
Record Path Signal Processing
The device’s record signal path includes both automatic
gain control (AGC) for the microphone inputs and a digi-
tal noise gate at the output of the ADC (Figure 10).
Microphone AGC
The IC’s AGC monitors the signal level at the output of the
ADC and then adjusts the MIC1 and MIC2 analog PGA
settings automatically. When the signal level is below
the predefined threshold, the gain is increased up to its
maximum (20dB). If the signal exceeds the threshold,
the gain is reduced to prevent the output signal level
exceeding the threshold. When AGC is enabled, the
microphone PGA is not user programmable. The AGC
provides a more constant signal level and improves the
available ADC dynamic range.
The noise gate can be used in conjunction with the AGC
or on its own. When the AGC is enabled, the noise gate
reduces the output level only when the AGC has set the
gain to the maximum setting. Figure 11 shows the gain
response resulting from using the AGC and noise gate.
AGC AND NOISE GATE
AMPLITUDE RESPONSE
0
PA1EN:
0/20/30dB
PGAM1:
+20dB TO -6dB
NOISE GATE
AGC ONLY
-20
AUTOMATIC
GAIN
CONTROL
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
AGC AND NOISE GATE
-40
PA2EN:
0/20/30dB
AVLG: 0/6/
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
12/18dB
AVL:0dB
TO -15dB
PGAM2:
+20dB TO 0dB
MIX
ADCL
ADLEN
-60
AGC AND NOISE
GATE DISABLED
MIXADL
SRMIX_ SAMPLE RATE
MODE CONVERTER
-80
NOISE GATE ONLY
MIX
ADCR
ADREN
-100
MIXADR
-120
-120
-100
-80
-60
-40
-20
0
INPUT AMPLITUDE (dBFS)
Figure 10. Record Path Signal Processing Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 69
Figure 11. AGC and Noise Gate Input vs. Output Gain
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 6. Record Path Signal Processing Registers
REGISTER
BIT
NAME
DESCRIPTION
Noise Gate Attenuation
Reports the current noise gate attenuation.
000 = 0dB
7
001 = 1dB
010 = 2dB
6
5
4
NG
011 = 3dB to 5dB
100 = 6dB to 7dB
101 = 8dB to 9dB
110 = 10dB to 11dB
111 = 12dB
AGC Gain
Reports the current AGC gain setting.
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
VALUE
0x0B
GAIN (dB)
0x01
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
3
2
+19
0x0C
+18
0x0D
+17
0x0E
AGC
+16
0x0F
+15
0x10
+14
0x11
1
0
+13
0x12
+12
0x13
+11
0x14 to 0x1F
+10
AGC/Noise Gate Signal Source
Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on
both channels regardless of the AGCSRC setting.
0 = Left ADC output
7
AGCSRC
1 = Maximum of either the left or right ADC output
AGC Release Time
Defined as the duration from start to finish of gain increase in the region shown in Figure
12.
6
5
4
0x3F
000 = 78ms
001 = 156ms
010 = 312ms
011 = 625ms
100 = 1.25s
101 = 2.5s
110 = 5s
AGCRLS
111 = 10s
���������������������������������������������������������������� Maxim Integrated Products 70
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 6. Record Path Signal Processing Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
AGC Attack Time
Defined as the time required to reduce gain by 63% of the total gain reduction (one time
constant of the exponential response). Attack times are longer for low AGC threshold
3
levels. See Figure 12 for details.
00 = 2ms
AGCATK
01 = 7.2ms
10 = 31ms
11 = 123ms
2
1
0x3F
AGC Hold Time
The delay before the AGC release begins. The hold time counter starts whenever the
signal drops below the AGC threshold and is reset by any signal that exceeds the
AGCHLD
threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details.
00 = AGC disabled
01 = 50ms
10 = 100ms
0
7
11 = 400ms
Noise Gate Threshold
Gain is reduced for signals below the threshold to quiet noise. The thresholds are rela-
tive to the ADC’s full-scale output voltage.
THRESHOLD
(dBFS)
THRESHOLD
(dBFS)
VALUE
VALUE
6
5
0x0
Noise gate disabled
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
-45
-41
-38
-34
-30
-27
-22
-16
0x1
Reserved
Reserved
-64
ANTH
0x2
0x3
0x4
-62
0x5
0x6
-58
4
3
-53
0x7
-50
0x40
AGC Threshold
Gain is reduced when signals exceed the threshold to prevent clipping. The thresholds
are relative to the ADC’s full-scale voltage.
THRESHOLD
(dBFS)
THRESHOLD
(dBFS)
VALUE
VALUE
2
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-3
-4
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
-11
-12
-13
-14
-15
-16
-17
-18
AGCTH
-5
1
0
-6
-7
-8
-9
-10
���������������������������������������������������������������� Maxim Integrated Products 71
MAX98088
Stereo Audio Codec
with FlexSound Technology
ATTACK TIME
HOLD TIME
RELEASE TIME
Figure 12. AGC Timing
the digital level control to 0dB whenever possible. Digital
level control is primarily used when adjusting the record
level for digital microphones.
ADC Record Level Control
The IC includes separate digital level control for the left
and right ADC outputs (Figure 13). To optimize dynamic
range, use analog gain to adjust the signal level and set
NOISE GATE
AUDIO/
VOICE
FILTERS
AUTOMATIC
GAIN
CONTROL
MODE1
AVFLT
AVLG: 0/6/
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
12/18dB
AVL:0dB
TO -15dB
ADCL
ADLEN
SRMIX_ SAMPLE RATE
MODE CONVERTER
ADCR
ADREN
Figure 13. ADC Record Level Control Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 72
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 7. ADC Record Level Control Register
REGISTER
BIT
NAME
DESCRIPTION
Left/Right ADC Gain
00 = 0dB
5
AVLG/AVRG
01 = 6dB
10 = 12dB
11 = 18dB
4
Left/Right ADC Level
3
2
VALUE
0x0
GAIN (dB)
VALUE
0x8
GAIN (dB)
+3
+2
+1
0
-5
-6
0x33/0x34
0x1
0x9
0x2
0xA
0xB
0xC
0xD
0xE
-7
AVL/AVR
1
0
0x3
-8
0x4
-1
-2
-3
-4
-9
0x5
-10
-11
-12
0x6
0x7
0xF
speak, providing a more natural user experience. The
IC implements sidetone digitally. Doing so helps prevent
unwanted feedback into the playback signal path and
better matches the playback audio signal.
Sidetone
Enable sidetone during full-duplex operation to add a
low-level copy of the recorded audio signal to the play-
back audio signal (Figure 14). Sidetone is commonly
used in telephony to allow the speaker to hear himself
DV1G:
0/6/12/18dB
DVST:
0dB TO -60dB
SIDETONE
MIX
+
DSTS
MULTI BAND ALC
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
AUTOMATIC
GAIN
CONTROL
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
NOISE GATE
EQ1EN
EQ2EN
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
EXCURSION LIMITER
DACL
MIX
DALEN
AVLG: 0/6/
12/18dB
AVL:0dB
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
ADLEN
ADCL
MIXDAL
AUDIO/
FILTERS
DV2:
0dB TO -15dB
TO -15dB
DCB2
SAMPLE RATE
CONVERTER
SRMIX_
MODE
AUDIO/
VOICE
FILTERS
ADCR
ADREN
DV1:
0dB TO -15dB
MIX
DACR
MODE1
DVFLT
DAREN
MIXDAR
Figure 14. Sidetone Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 73
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 8. Sidetone Register
REGISTER
BIT
NAME
DESCRIPTION
Sidetone Source
Selects which ADC output is fed back as sidetone. When mixing the left and right ADC
outputs, each is attenuated by 6dB to prevent full-scale signals from clipping.
7
DSTS
00 = Sidetone disabled
01 = Left ADC
6
4
10 = Right ADC
11 = Left + Right ADC
Sidetone Level
Adjusts the sidetone signal level. All levels are referenced to the ADC’s full-scale output.
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
LEVEL (dB)
Sidetone disabled
-0.5
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
LEVEL (dB)
-30.5
-32.5
-34.5
-36.5
-38.5
-40.5
-42.5
-44.5
-46.5
-48.5
-50.5
-52.5
-54.5
-56.6
-58.5
-60.5
3
2
1
0
-2.5
0x2E
-4.5
-6.5
-8.5
DVST
-10.5
-12.5
-14.5
-16.5
-18.5
-20.5
-22.5
-24.5
-26.5
-28.5
slots per interface, leaving the remaining two slots avail-
able for another device. Table 9 shows how to configure
the device for common digital audio formats. Figures 16
and 17 show examples of common audio formats. By
default, SDOUTS1 and SDOUTS2 are set high imped-
ance when the IC is not outputting data to facilitate shar-
ing the bus. Configure the interface in TDM mode using
only slot 1 to transmit and receive mono PCM voice data.
Digital Audio Interfaces
The IC includes two separate playback signal paths and
one record signal path. Digital audio interface 1 (DAI1)
is used to transmit the recorded stereo audio signal and
receive a stereo audio signal for playback. Digital audio
interface 2 (DAI2) is used to receive a second stereo
audio signal. Use DAI1 for all full-duplex operations and
for all voice signals. Use DAI2 for music and to mix two
playback audio signals. The digital audio interfaces are
separate from the audio ports to enable either interface
to communicate with any external device connected to
either audio port.
The IC’s digital audio interfaces support both ADC to DAC
loop-through and digital loopback. Loop-through allows
the signal converted by the ADC to be routed to the DAC
for playback. The signal is routed from the record path to
the playback path in the digital audio interface to allow
the IC’s full complement of digital signal processing to
be used. Loopback allows digital data input to either
SDINS1 or SDINS2 to be routed from one interface to the
Each audio interface can be configured in a variety of for-
mats including left justified, I2S, PCM, and time division
multiplexed (TDM). TDM mode supports up to 4 mono
audio slots in each frame. The IC can use up to 2 mono
���������������������������������������������������������������� Maxim Integrated Products 74
MAX98088
Stereo Audio Codec
with FlexSound Technology
other for output on SDOUTS2 or SDOUTS1. Both inter-
faces must be configured for the same sample rate, but
the interface format need not be the same. This allows
the IC to route audio data from one device to another,
converting the data format as needed. Figure 15 shows
the available digital signal routing options.
BCLKS1
LRCLKS1
SDOUTS1
SDINS1 DVDDS1
BCLKS2
LRCLKS2
SDOUTS2
SDINS2 DVDDS2
SEL1
DAI1
SEL2
DAI2
HIZOFF1
SDOEN1
HIZOFF2
SDOEN2
SDIEN1
SDIEN2
MAS1
MAS1
MAS2
MAS2
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
LBEN1
LBEN2 MUX
+
LTEN1
DAI1
DAI1
DAI2
RECORD PATH
PLAYBACK PATH
PLAYBACK PATH
Figure 15. Digital Audio Signal Routing
Table 9. Common Digital Audio Formats
MODE
Left Justified
I2S
WCI1/WCI2
BCI1/BCI2
DLY1/DLY2
TDM1/TDM2
SLOTL1/SLOTL2 SLOTR1/SLOTR2
1
0
X
X
0
0
1
1
0
1
X
X
0
0
1
1
X
X
0
X
X
0
PCM
TDM
Set as desired
���������������������������������������������������������������� Maxim Integrated Products 75
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 10. Digital Audio Interface Registers
REGISTER
BIT
NAME
DESCRIPTION
DAI1/DAI2 Master Mode
In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2
7
MAS1/MAS2
accept LRCLK and BCLK as inputs.
0 = Slave mode
1 = Master mode
DAI1/DAI2 Word Clock Invert
TDM1/TDM2 = 0:
0 = Left-channel data is transmitted while LRCLK is low.
1 = Right-channel data is transmitted while LRCLK is low.
TDM1/TDM2 = 1:
6
5
4
WCI1/WCI2
BCI1/BCI2
DLY1/DLY2
Always set WCI = 0.
DAI1/DAI2 Bit Clock Invert
BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1.
0 = SDIN is accepted on the rising edge of BCLK.
SDOUT is valid on the rising edge of BCLK.
1 = SDIN is accepted on the falling edge of BCLK.
SDOUT is valid on the falling edge of BCLK.
Master Mode:
0 = LRCLK transitions on the falling edge of BCLK.
1 = LRCLK transitions on the rising edge of BCLK.
0x14/0x1C
DAI1/DAI2 Data Delay
DLY1/DLY2 has no effect when TDM1/TDM2 = 1.
0 = The most significant data bit is clocked on the first active BCLK edge after an
LRCLK transition.
1 = The most significant data bit is clocked on the second active BCLK edge after an
LRCLK transition.
DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode)
Set TDM1/TDM2 when communicating with devices that use a frame synchronization
pulse on LRCLK instead of a square wave.
0 = Disabled
1 = Enabled (BCI1/BCI2 must be set to 1)
2
1
0
TDM1/TDM2
FSW1/FSW2
WS1/WS2
DAI1/DAI2 Wide Frame Sync Pulse
Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 =
1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0.
0 = Disabled
1 = Enabled
DAI1/DAI2 Audio Data Bit Depth
Determines the maximum bit depth of audio being transmitted and received. Data is
always 16 bit when TDM1/TMD2 = 0.
0 = 16 bits
1 = 24 bits
���������������������������������������������������������������� Maxim Integrated Products 76
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
ADC Oversampling Ratio
Use the higher setting for maximum performance. Use the lower setting for reduced
power consumption at the expense of performance.
7
OSR1
00 = 96x
01 = 64x
10 = Reserved
11 = Reserved
6
5
DAC Oversample Clock. Select PCLK/2 for higher performance. Select PCLK/4 for
lower consumption.
1 = DAC input clock = PCLK/2
DAC_OSR1/
DAC_OSR2
0 = DAC input clock = PCLK/4
0x15/0x1D
DAI1/DAI2 BCLK Output Frequency
When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When
operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK fre-
quency that clocks all data input to the DAC and output by the ADC.
000 = BCLK disabled
001 = 64 x LRCLK
010 = 48 x LRCLK
011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1)
100 = PCLK/2
101 = PCLK/4
110 = PCLK/8
2
1
0
BSEL1/
BSEL2
111 = PCLK/16
DAI1/DAI2 Audio Port Selector
Selects which port is used by DAI1/DAI2.
00 = None
01 = Port S1
10 = Port S2
7
6
SEL1/SEL2
LTEN1
11 = Reserved
DAI1 Digital Loopthrough
Connects the output of the record signal path to the input of the playback path. Data
input to DAI1 from an external device is mixed with the recorded audio signal.
0 = Disabled
1 = Enabled
5
4
0x16/0x1E
DAI1/DAI2 Digital Audio Interface Loopback
LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the digi-
tal audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC output
data.
LBEN1/
LBEN2
0 = Disabled
1 = Enabled
DAI1/DAI2 DAC Mono Mix
Mixes the left and right digital input to mono and routes the combined signal to the left
DMONO1/
DMONO2
and right playback paths. The left and right input data is attenuated by 6dB prior to the
mono mix.
3
0 = Disabled
1 = Enabled
���������������������������������������������������������������� Maxim Integrated Products 77
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
Disable DA1/DAI2 Output High-Impedance Mode
Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to
force a level on SDOUT at all times.
0 = Disabled
HIZOFF1/
HIZOFF2
2
1 = Enabled
DAI1/DAI2 Record Path Output Enable
DAI2 outputs data only if LBEN1 = 1.
0 = Disabled
0x16/0x1E
SDOEN1/
SDOEN2
1
1 = Enabled
DAI1/DAI2 Playback Path Input Enable
0 = Disabled
1 = Enabled
SDIEN1/
SDIEN2
0
7
TDM Left Time Slot
Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
SLOTL1/
SLOTL2
6
5
4
10 = Slot 3
11 = Slot 4
TDM Right Time Slot
Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
11 = Slot 4
SLOTR1/
SLOTR2
0x17/0x1F
TDM Slot Delay
Adds 1 BCLK cycle delay to the data in the specified TDM slot.
1xxx = Slot 4 delayed
x1xx = Slot 3 delayed
xx1x = Slot 2 delayed
3
2
1
0
SLOTDLY1/
SLOTDLY2
xxx1 = Slot 1 delayed
���������������������������������������������������������������� Maxim Integrated Products 78
MAX98088
Stereo Audio Codec
with FlexSound Technology
WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LRCLK
SDOUT
BCLK
RIGHT
LEFT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LEFT
LRCLK
SDOUT
BCLK
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LEFT
RIGHT
LRCLK
SDOUT
BCLK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 0, BCI_ = 0, DLY_ = 1, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LEFT
LRCLK
SDOUT
BCLK
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 16. Non-TDM Data Format Examples
���������������������������������������������������������������� Maxim Integrated Products 79
MAX98088
Stereo Audio Codec
with FlexSound Technology
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
BCLK
HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
BCLK
HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCLK
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 2, SLOTR_ = 3
LRCLK
SDOUT
HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
32 CYCLES
BCLK
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
HI-Z
HI-Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BCLK
SDIN
HI-Z
L
L
R
R
Figure 17. TDM Mode Data Format Examples
���������������������������������������������������������������� Maxim Integrated Products 80
MAX98088
Stereo Audio Codec
with FlexSound Technology
U Normal Mode: This mode uses a 15-bit clock divider
Clock Control
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequen-
cies and can be used in either master or slave mode.
The digital signal paths in the IC require a master clock
(MCLK) between 10MHz and 60MHz to function. The
MAX98088 requires an internal clock between 10MHz
and 20MHz. A prescaler divides MCLK by 1, 2, or 4 to
create the internal clock (PCLK). PCLK is used to clock
all portions of the IC.
U Exact Integer Mode (DAI1 only): In both master and
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
The MAX98088 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, four main clocking modes are
supported:
U DAC Low-Power Mode: This mode bypasses the
PLL for reduce power consumptions and uses fixed
counters to generate the clocks. The DAI__DAC_LP
bits override the other clock settings.
U PLL Mode: When operating in slave mode, enable the
PLL to lock onto any LRCLK input. This mode requires
the least configuration, but provides the lowest per-
formance. Use this mode to simplify initial setup or
when normal mode and exact integer mode cannot
be used.
Table 11. Clock Control Registers
REGISTER
BIT
NAME
DESCRIPTION
MCLK Prescaler
5
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
0x10
PSCLK
4
7
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
SAMPLE RATE
(kHz)
SAMPLE RATE
(kHz)
VALUE
VALUE
6
5
4
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Reserved
8
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
48
88.2
0x11/0x19
SR1/SR2
11.025
16
96
Reserved
Reserved
Reserved
Reserved
Reserved
22.05
24
32
44.1
���������������������������������������������������������������� Maxim Integrated Products 81
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 11. Clock Control Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
Exact Integer Mode
Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
3
VALUE
SAMPLE RATE
VALUE
SAMPLE RATE
PCLK = 12MHz,
LRCLK = 8kHz
0x0
Disabled
0x8
PCLK = 12MHz,
LRCLK = 16kHz
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x9
0xA
0xB
0xC
0xD
0xE
0xF
PCLK = 13MHz,
LRCLK = 8kHz
2
0x11
FREQ1
PCLK = 13MHz,
LRCLK = 16kHz
PCLK = 16MHz,
LRCLK = 8kHz
PCLK = 16MHz,
LRCLK = 16kHz
PCLK = 19.2MHz,
LRCLK = 8kHz
1
7
PCLK = 19.2MHz,
LRCLK = 16kHz
PLL Mode Enable (Slave Mode Only)
PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK
frequency and automatically sets the LRCLK divider (NI1/NI2).
PLL1/PLL2
0 = Disabled
1 = Enabled
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Normal Mode LRCLK Divider
When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12
for common NI values.
0x12/0x1A
SAMPLE RATE
DHF1/DHF2
NI1/NI2 FORMULA
8kHz P LRCLK P 48kHz
0
NI1/
NI2
48kHz <LRCLK P 96kHz
1
f
f
= LRCLK frequency
= Prescaled MCLK frequency (PCLK)
LRCLK
PCLK
0x13/0x1B
Rapid Lock Mode
Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1
to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically
adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is
much closer to the correct value, thus speeding up lock time. Wait one LRCLK period
after programming NI1/NI2 before setting PLL1/PLL2 = 1.
0
NI1[0]/NI2[0]
���������������������������������������������������������������� Maxim Integrated Products 82
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 11. Clock Control Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
DAI� DAC Low Power Select.
7
These bits setup the clocks to be generated from fixed counters that bypass the PLL
for DAC low power mode.
FILTER
SELECT
FILTER
SELECT
VALUE
SETTING
VALUE
SETTING
6
PCLK =
2304 x
LRCLK
DAI2_DAC_LP
PLL derived
clock
0x0
—
0x8
Voice
PCLK = 128
x LRCLK
Audio
96kHz
5
4
0x1
0x2
0x3
0x4
0x5
0x9
0xA
0xB
0xC
0xD
Reserved
Reserved
Reserved
Reserved
Reserved
—
—
—
—
—
PCLK = 192
x LRCLK
Audio
96kHz
0x4F
PCLK = 256
x LRCLK
Audio
48kHz
3
PCLK = 384
x LRCLK
Audio
48kHz
PCLK = 768
x LRCLK
2
1
Voice
DAI1_DAC_LP
PCLK =
1152 x
LRCLK
0x6
0x7
Voice
0xE
0xF
Reserved
Reserved
—
—
PCLK =
1536 x
LRCLK
0
3
Voice
DAI2 DAC Input Dither Enable
DAC2DITHEN is recommended to be set when DAI2_DAC_LP = 0000.
DAC2DITHEN
DAC1DITHEN
0 = Disabled
1 = Enabled
DAI1 DAC Input Dither 1 Enable
DAC1DITHEN is recommended to be set when DAI1_DAC_LP = 0000.
2
1
0 = Disabled
1 = Enabled
DAI2 Clock Gen Module Enable
CGM1_EN has to be set along with CGM2_EN to enable the clock generation for the
DAI2 DAC playback path.
0 = Disabled
0x50
CGM2_EN
CGM1_EN
1 = Enabled
DAI1/Device Clock Gen Module Enable
CGM1_EN enables the device clock generation, and needs to be set for DAC playback
or ADC record.
0 = Disabled
1 = Enabled
0
���������������������������������������������������������������� Maxim Integrated Products 83
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 12. Common NI1/NI2 Values
LRCLK (kHz)
PCLK (MHz)
DHF1/2 = 0
DHF1/2 = 1
88.2
8
11.025
1B18
18A2
1800
1694
160D
14D8
10EF
1000
0EB3
0D8C
12
16
22.05
3631
3144
3000
2D29
2C1A
29AF
21DE
2000
1D66
1B18
24
32
44.1
6C61
6287
6000
5A51
5833
535F
43BD
4000
3ACD
3631
48
64
96
10
11
13A9
11E0
116A
1062
1000
0F20
0C4A
0B9C
0AAB
09D5
1D7E
1ACF
1A1F
1893
1800
16AF
126F
116A
1000
0EBF
2752
23BF
22D4
20C5
2000
1E3F
1893
1738
1555
13A9
3AFB
359F
343F
3127
3000
2D5F
24DD
22D4
2000
1D7E
4EA5
477E
45A9
4189
4000
3C7F
3127
2E71
2AAB
2752
75F7
6B3E
687D
624E
6000
5ABE
49BA
45A9
4000
3AFB
4EA5
477E
45A9
4189
4000
3C7F
3127
2E71
2AAB
2752
6C61
6287
75F7
6B3E
687D
624E
6000
5ABE
49BA
45A9
4000
3AFB
11.2896
12
6000
5A51
5833
12.288
13
535F
16
43BD
4000
16.9344
18.432
20
3ACD
3631
Note: Values in bold are exact integers that provide maximum full-scale performance.
interfaces (SDIN1/SDIN2), and for the resulting mixed
audio to output on either audio interface through SDOUT1
or SDOUT2.
Sample Rate Converter
The sample rate conversion scheme enables the mix-
ing of asynchronous audio data from the digital audio
DV1G:
0/6/12/18dB
DVST:
0dB TO -60dB
SIDETONE
MIX
+
DSTS
MULTI BAND ALC
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
AUTOMATIC
GAIN
CONTROL
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
NOISE GATE
EQ1EN
EQ2EN
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
EXCURSION LIMITER
DACL
MIX
DALEN
AVLG: 0/6/
12/18dB
AVL:0dB
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
ADLEN
ADCL
MIXDAL
AUDIO/
FILTERS
DV2:
0dB TO -15dB
TO -15dB
DCB2
SAMPLE RATE
CONVERTER
SRMIX_
MODE
AUDIO/
VOICE
FILTERS
DV1:
0dB TO -15dB
MIX
DACR
ADCR
ADREN
MODE1
DVFLT
DAREN
MIXDAR
Figure 18. Sample Rate Converter
���������������������������������������������������������������� Maxim Integrated Products 84
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 13. Sample Rate Converter
REGISTER
BIT
NAME
DESCRIPTION
Sample Rate Mix Mode. Sets mixing configuration applied to the sample rate con-
verted channel(s).
0 = (DAI1 + DAI2)
1 = (DAI1 + DAI2)/2
4
SRMIX_MODE
Sample Rate Mix Enable. If enabled, mixes data on DAI1 and DAI2. If cleared, SCR
3
2
SRMIX_ENL
SRMIX_ENR
0x21
data source is DAI2 only.
0 = SRC mix disable
1 = SRC mix enable
Sample Rate Converter Enable. Select if the SRC is enabled on per channel basis.
0 = Sample rate converter disable
1 = Sample rate converter enable
1
0
SRC_ENL
SRC_ENR
Use music mode when processing high-fidelity audio
content. The music FIR filters reduce power consump-
tion and are linear phase to maintain stereo imaging.
An optional DC-blocking filter is available to eliminate
unwanted DC offset.
Passband Filtering
Each digital signal path in the IC includes options for
defining the path bandwidth (Figure 19). The playback
and record paths connected to DAI1 support both voice
and music filtering while the playback path connected to
DAI2 supports music filtering only.
In music mode, a second set of FIR filters are available to
support sample rates greater than 50kHz. The filters can
be independently selected for DAI1 and DAI2 and sup-
port both the playback and record audio paths.
The voice IIR filters provide greater than 70dB stopband
attenuation at frequencies above f /2 to reduce aliasing.
S
Three selectable highpass filters eliminate unwanted low-
frequency signals.
DV1G:
0/6/12/18dB
DVST:
0dB TO -60dB
SIDETONE
MIX
+
DSTS
MULTI BAND ALC
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
AUTOMATIC
GAIN
CONTROL
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
NOISE GATE
EQ1EN
EQ2EN
AUDIO/
VOICE
FILTERS
MODE1
AVFLT
EXCURSION LIMITER
DACL
MIX
DALEN
AVLG: 0/6/
12/18dB
AVL:0dB
AVRG: 0/6/
12/18dB
AVR:0dB
TO -15dB
ADLEN
ADCL
MIXDAL
AUDIO/
FILTERS
DV2:
0dB TO -15dB
TO -15dB
DCB2
SAMPLE RATE
CONVERTER
SRMIX_
MODE
AUDIO/
VOICE
FILTERS
ADCR
ADREN
DV1:
0dB TO -15dB
MIX
DACR
MODE1
DVFLT
DAREN
MIXDAR
Figure 19. Digital Passband Filtering Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 85
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 14. Passband Filtering Registers
REGISTER
BIT
NAME
DESCRIPTION
DAI1 Passband Filtering Mode
0 = Voice filters
7
MODE1
1 = Music filters (recommended for f > 24kHz)
S
6
5
DAI1 ADC Highpass Filter Mode
MODE1
AVFLT1
0
See Table 15
AVFLT1
DHF1
4
3
Select a nonzero value to enable
the DC-blocking filter.
1
0x18
DAI1 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz P LRCLK P 96kHz
2
1
DAI1 DAC Highpass Filter Mode
MODE1
DVFLT1
0
See Table 15
DVFLT1
Select a nonzero value to enable
the DC-blocking filter.
0
3
1
DAI2 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz <LRCLK P 96kHz
DHF2
DCB2
0x20
DAI2 DC Blocking Filter
Enables a DC-blocking filter on the DAI2 playback audio path.
0
0 = Disabled
1 = Enabled
���������������������������������������������������������������� Maxim Integrated Products 86
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 15. Voice Highpass Filters
AVFTL/DVFLT VALUE
INTENDED SAMPLE RATE
FILTER RESPONSE
000
N/A
Disabled
0
-10
-20
-30
-40
-50
-60
001/011
16kHz/8kHz
0
0
0
200
200
200
400
600
800
1000
1000
1000
FREQUENCY (Hz)
0
-10
-20
-30
-40
-50
-60
010/100
16kHz/8kHz
400
600
800
FREQUENCY (Hz)
0
-10
-20
-30
-40
-50
-60
101
8kHz to 48kHz
LRCLK = 48kHz
600 800
400
FREQUENCY (Hz)
110/111
N/A
Reserved
���������������������������������������������������������������� Maxim Integrated Products 87
MAX98088
Stereo Audio Codec
with FlexSound Technology
The ALC can optionally be configured in dual-band
mode. In this mode, the input signal is filtered into two
bands with a 5kHz center frequency. Each band is
routed through independent ALCs and then summed
together. In multiband mode, both bands use the same
parameters.
Playback Path Signal Processing
The IC playback signal path includes automatic level
control (ALC) and a 5-band parametric equalizer (EQ)
(Figure 20). The DAI1 and DAI2 playback paths include
separate ALCs controlled by a single set of registers.
Two completely separate parametric EQs are included
for the DAI1 and DAI2 playback paths.
OUTPUT SIGNAL
(dBFS)
Automatic Level Control
The automatic level control (ALC) circuit ensures maxi-
mum signal amplitude without producing audible clip-
ping. This is accomplished by a variable gain stage that
works on a sample by sample basis to increase the gain
up to 12dB. A look-ahead circuit determines if the next
sample exceeds full scale and reduces the gain so that
the sample is exactly full scale.
0
A programmable low signal threshold determines the
minimum signal amplitude that is amplified. Select a
threshold that prevents the amplification of background
noise. When the signal level drops below the low signal
threshold, the ALC reduces the gain to 0dB until the sig-
nal increases above the threshold. Figure 21 shows an
example of ALC input vs. output curves.
INPUT
SIGNAL
(dBFS)
LOW-LEVEL
THRESHOLD
-12
0
0
0
ALC WITH ALCTH ≠ 000
OUTPUT SIGNAL
(dBFS)
0
DV1G:
0/6/12/18dB
+
INPUT
SIGNAL
(dBFS)
MULTI BAND ALC
LOW-LEVEL
THRESHOLD
ALC WITH ALCTH = 000
-12
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
OUTPUT SIGNAL
(dBFS)
EQ1EN
EQ2EN
0
EXCURSION LIMITER
DACL
MIX
DALEN
AUDIO/
FILTERS
MIXDAL
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
INPUT
SIGNAL
(dBFS)
FILTERS
DV1:
MIX
0dB TO -15dB
DACR
MODE1
DVFLT
LOW-LEVEL
THRESHOLD
ALC DISABLED
-12
DAREN
MIXDAR
Figure 20. Playback Path Signal Processing Block Diagram
Figure 21. ALC Input vs. Output Examples
���������������������������������������������������������������� Maxim Integrated Products 88
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 16. Automatic Level Control Registers
REGISTER
BIT
NAME
DESCRIPTION
ALC Enable
Enables ALC on both the DAI1 and DAI2 playback paths.
0 = Disabled
1 = Enabled
7
ALCEN
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Excursion
Limiter section for Excursion Limiter release times. ALC release time is defined as the
6
time required to adjust the gain from 12dB to 0dB.
VALUE
000
ALC RELEASE TIME (s)
8
001
4
ALCRLS
5
4
010
2
1
011
100
0.5
101
0.25
0x43
110
Reserved
Reserved
111
Multiband Enable
Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be
configured properly to achieve the correct center frequency for each playback path.
0 = Single-band ALC
3
ALCMB
ALCTH
1 = Dual-band ALC
Low Signal Threshold
Selects the minimum signal level to be boosted by the ALC.
000 = -JdB (low-signal threshold disabled)
001 = -12dB
010 = -18dB
011 = -24dB
100 = -30dB
101 = -36dB
110 = -42dB
2
1
0
111 = -48dB
1000
Parametric Equalizer
The parametric EQ contains five independent biquad
filters with programmable gain, center frequency, and
bandwidth. Each biquad filter has a gain range of Q12dB
and a center frequency range from 20Hz to 20kHz. Use a
filter Q less than that shown in Figure 22 to achieve ideal
frequency responses. Setting a higher Q results in non-
ideal frequency response. The biquad filters are series
connected, allowing a total gain of Q60dB.
f = 8kHz
s
100
10
1
f = 48kHz
s
f = 96kHz
s
0.1
100
1000
10,000
100,000
CENTER FREQUENCY (Hz)
Figure 22. Maximum Recommended Filter Q vs. Frequency
���������������������������������������������������������������� Maxim Integrated Products 89
MAX98088
Stereo Audio Codec
with FlexSound Technology
Use the attenuator at the EQ’s input to avoid clipping
the signal. The attenuator can be programmed for fixed
attenuation or dynamic attenuation based on signal level.
If the dynamic EQ clip detection is enabled, the signal
level from the EQ is fed back to the attenuator circuit to
determine the amount of gain reduction necessary to
avoid clipping.
The MAX98088 EV kit software includes a graphical inter-
face for generating the EQ coefficients. The coefficients
are sample rate dependent and stored in registers 0x52
through 0xB5.
Table 17. EQ Registers
REGISTER
BIT
NAME
DESCRIPTION
DAI1/DAI2 EQ Clip Detection
Automatically controls the EQ attenuator to prevent clipping in the EQ.
0 = Enabled
1 = Disabled
EQCLP1/
EQCLP2
4
DAI1/DAI2 EQ Attenuator
Provides attenuation to prevent clipping in the EQ when full-scale signals are boost-
ed. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2
3
= 1.
VALUE
0x0
GAIN (dB)
VALUE
0x8
GAIN (dB)
0x30/0x32
2
1
0
0
-8
0x1
-1
-2
-3
-4
-5
-6
-7
0x9
-9
DVEQ1/DVEQ2
0x2
0xA
0xB
0xC
0xD
0xE
-10
-11
-12
-13
-14
-15
0x3
0x4
0x5
0x6
0x7
0xF
7
6
5
VS2EN
VSEN
ZDEN
See the Click-and-Pop Reduction section.
DAI2 EQ Enable
0 = Disabled
1 = Enabled
0x49
1
0
EQ2EN
EQ1EN
DAI1 EQ Enable
0 = Disabled
1 = Enabled
���������������������������������������������������������������� Maxim Integrated Products 90
MAX98088
Stereo Audio Codec
with FlexSound Technology
allows boost when MODE1 = 0 and attenuation in any
mode. The DAI2 signal path allows attenuation only.
Playback Level Control
The IC includes separate digital level control for the DAI1
and DAI2 playback audio paths. The DAI1 signal path
DV1G:
0/6/12/18dB
+
MULTI BAND ALC
DVEQ1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
EQ1EN
EQ2EN
EXCURSION LIMITER
DACL
MIX
DALEN
AUDIO/
MIXDAL
FILTERS
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
MIX
DACR
DV1:
0dB TO -15dB
MODE1
DVFLT
DAREN
MIXDAR
Figure 23. Playback Level Control Block Diagram
Table 18. DAC Playback Level Control Register
REGISTER
BIT
NAME
DESCRIPTION
DAI1/DAI2 Mute
0 = Disabled
1 = Enabled
7
DV1M/DV2M
DAI1 Voice Mode Gain
DV1G only applies when MODE1 = 0.
5
00 = 0dB
01 = 6dB
10 = 12dB
11 = 18dB
DV1G
4
3
2
DAI1/DAI2 Attenuation
0x2F/0x31
VALUE
0x0
GAIN (dB)
VALUE
0x8
GAIN (dB)
0
-8
0x1
-1
-2
-3
-4
-5
-6
-7
0x9
-9
0x2
0xA
0xB
0xC
0xD
0xE
-10
-11
-12
-13
-14
-15
DV1/DV2
0x3
1
0
0x4
0x5
0x6
0x7
0xF
���������������������������������������������������������������� Maxim Integrated Products 91
MAX98088
Stereo Audio Codec
with FlexSound Technology
DAC Input Mixers
The IC’s stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and
right DACs (Figure 24).
DV1G:
0/6/12/18dB
+
MULTI BAND ALC
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
EQ1EN
EQ2EN
EXCURSION LIMITER
DACL
MIX
DALEN
AUDIO/
FILTERS
MIXDAL
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
DV1:
MIX
DACR
0dB TO -15dB
MODE1
DVFLT
DAREN
MIXDAR
Figure 24. DAC Input Mixer Block Diagram
Table 19. DAC Input Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
7
Left DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
6
5
4
3
2
1
0
MIXDAL
0x22
Right DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
MIXDAR
���������������������������������������������������������������� Maxim Integrated Products 92
MAX98088
Stereo Audio Codec
with FlexSound Technology
Receiver Amplifier
The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive a 32I earpiece
speaker. In cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route
the receiver amplifier output to the left speaker outputs. The receiver amplifier can also be configured as stereo single-
ended line outputs using the I2C interface.
RECVOLL:
+8dB TO -62dB
RECP/
LOUTL/
RXINP
MIX
0dB
RECLEN
MIXRECL
RECBYP
RECVOLR:
RECN/
LOUTR/
RXINN
+8dB TO -62dB
MIX
0dB
RECREN
LINEMODE
SPKBYP
MIXRECR
SPKLP
SPKLN
+6dB
SPLEN
DACL
DALEN
DACR
DAREN
Figure 25. Receiver Amplifier Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 93
MAX98088
Stereo Audio Codec
with FlexSound Technology
Receiver Output Mixer
The IC’s receiver amplifier accepts input from the stereo DAC, the line inputs (single-ended or differential), and the MIC
inputs. Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the
mixed signal can be configured to attenuate 6dB, 9dB, or 12dB.
Table 20. Receiver Output Mixer Register
REGISTER
BIT
7
NAME
DESCRIPTION
Left Receiver Output Mixer
1xxxxxxx = Right DAC
x1xxxxxx = MIC2
6
5
xx1xxxxx = MIC1
4
0x28
MIXRECL
xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1)
xxxx1xxx = INB1
xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1)
xxxxxx1x = INA1
3
2
1
xxxxxxx1 = Left DAC
0
7
Right Receiver Output Mixer
1xxxxxxx = Left DAC
6
x1xxxxxx = MIC2
xx1xxxxx = MIC1
xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1)
xxxx1xxx = INB1
xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1)
xxxxxx1x = INA1
5
4
0x29
MIXRECR
3
2
1
xxxxxxx1 = Right DAC
0
Receiver Output Mode. Configures receive path output mode between BTL and ste-
reo line output.
0 = BTL
7
LINE_MODE
1 = Stereo line output
Right Receiver Mixer Gain Select
3
2
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
MIXRECR
_GAIN
0x2A
Left Receiver Mixer Gain Select
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
1
0
0
MIXRECL
_GAIN
���������������������������������������������������������������� Maxim Integrated Products 94
MAX98088
Stereo Audio Codec
with FlexSound Technology
Receiver Output Volume
Table 21. Receiver Output Level Register
REGISTER
BIT
NAME
DESCRIPTION
Receiver Output Mute
0 = Disabled
1 = Enabled
RECLM/
RECRM
7
Receiver Output Volume Level
4
3
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
VOLUME (dB)
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
VOLUME (dB)
-62
-58
-54
-50
-46
-42
-38
-35
-32
-29
-26
-23
-20
-17
-14
-12
-10
-8
-6
-4
-2
0
0x3B/0x3C
2
1
0
+1
+2
+3
+4
+5
+6
+6.5
+7
+7.5
+8
RECVOLL/
RECVOLR
���������������������������������������������������������������� Maxim Integrated Products 95
MAX98088
Stereo Audio Codec
with FlexSound Technology
The theoretical best efficiency of a linear amplifier is 78%,
however, that efficiency is only exhibited at peak output
power. Under normal operating levels (typical music
reproduction levels), efficiency falls below 30%, whereas
the IC’s Class D amplifier still exhibits 80% efficiency
under the same conditions.
Speaker Amplifiers
The IC integrates a stereo filterless Class D amplifier that
offers much higher efficiency than Class AB without the
typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current
steering switches and consume negligible additional
power. Any power loss associated with the Class D out-
put stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
Traditional Class D amplifiers require the use of exter-
nal LC filters or shielding to meet EN55022B and FCC
electromagnetic-interference (EMI) regulation standards.
Maxim’s patented active emissions limiting edge-rate
control circuitry reduces EMI emissions, allowing opera-
tion without any output filtering in typical applications.
SPKLVDD
SPKLP
SPVOLL:
+8dB TO -62dB
+6dB
SPLEN
SPKLN
MIX
DACL
SPKLGND
DALEN
POWER/
DISTORTION LIMITER
MIXSPL
SPKRVDD
SPKRP
+6dB
SPREN
MIX
SPKRN
DACR
DAREN
SPVOLR:
+8dB TO -62dB
SPKRGND
MIXSPR
Figure 26. Speaker Amplifier Path Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 96
MAX98088
Stereo Audio Codec
with FlexSound Technology
Speaker Output Mixers
The IC’s speaker amplifiers accept input from the stereo DAC, the line inputs (single-ended ore differential), and the MIC inputs.
Configure the mixer to mix any combination of the available sources. When more than one signal is selected, the mixer can
be configured to attenuate the signal by 6dB, 9dB or 12dB.
Table 22. Speaker Output Mixer Register
REGISTER
BIT
7
NAME
DESCRIPTION
Left Speaker Output Mixer
1xxxxxxx = Right DAC
x1xxxxxx = MIC2
6
5
xx1xxxxx = MIC1
4
0x2B
MIXSPL
xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1)
xxxx1xxx = INB1
xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1)
xxxxxx1x = INA1
3
2
1
xxxxxxx1 = Left DAC
0
7
Right Speaker Output Mixer
1xxxxxxx = Left DAC
6
x1xxxxxx = MIC2
xx1xxxxx = MIC1
xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1)
xxxx1xxx = INB1
xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1)
xxxxxx1x = INA1
5
4
0x2C
MIXSPR
3
2
1
xxxxxxx1 = Right DAC
0
Right Speaker Mixer Gain Select
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
3
2
1
MIXSPR
_GAIN
0x2D
Left Speaker Mixer Gain Select
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
MIXSPL
_GAIN
0
���������������������������������������������������������������� Maxim Integrated Products 97
MAX98088
Stereo Audio Codec
with FlexSound Technology
Speaker Output Volume
Table 23. Speaker Output Level Register
REGISTER
BIT
NAME
DESCRIPTION
Left/Right Speaker Output Mute
7
SPLM/SPRM
0 = Disabled
1 = Enabled
Left/Right Speaker Output Volume Level
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
VOLUME (dB)
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
VOLUME (dB)
4
3
-62
-58
-54
-50
-46
-42
-38
-35
-32
-29
-26
-23
-20
-17
-14
-12
-10
-8
-6
-4
-2
0
0x3D/0x3E
+1
+2
+3
+4
+5
+6
+6.5
+7
+7.5
+8
SPVOLL/SPVOLR
2
1
transitions between the high and low corner frequency to
prevent unwanted artifacts. The filter can operate in four
different modes:
Speaker Amplifier Signal Processing
The IC includes signal processing to improve the sound
quality of the speaker output and protect transducers
from damage. An excursion limiter dynamically adjusts
the highpass corner frequency, while a power limiter and
distortion limiter prevent the amplifier from outputting too
much distortion or power. The excursion limiter is located
in the DSP while the distortion limiter and power limiter
control the analog volume control (Figure 28). All three
limiters analyze the speaker amplifier’s output signal to
determine when to take action.
U Fixed-Frequency Preset Mode. The highpass corner
frequency is fixed at the upper corner frequency and
does not change with signal level.
U Fixed-Frequency Programmable Mode. The high-
pass corner frequency is fixed to that specified by the
programmable biquad filter.
U Preset Dynamic Mode. The highpass filter automati-
cally slides between a preset upper and lower corner
frequency based on output signal level.
Excursion Limiter
The excursion limiter is a dynamic highpass filter that
monitors the speaker outputs and increases the highpass
corner frequency when the speaker amplifier’s output
exceeds a predefined threshold. The filter smoothly
U User-Programmable Dynamic Mode. The highpass
filter slides between a user-programmed biquad filter
on the low side to a predefined corner frequency on
the high side.
���������������������������������������������������������������� Maxim Integrated Products 98
MAX98088
Stereo Audio Codec
with FlexSound Technology
The transfer function for the user-programmable biquad is:
The MAX98088 EV kit software includes a graphic interface
for generating the user-programmable biquad coefficients.
-1
-2
b
+ b z + b z
1 2
0
H(z) =
Note: Only change the excursion limiter settings when
the signal path is disabled to prevent undesired artifacts.
-1
-2
1+ a z + a z
1
2
The coefficients b , b , b , a , and a are sample
0
1
2
1
2
rate dependent and stored in registers 0xB4 through
0xC7. Store b , b , and b as positive numbers. Store
0
1
2
a
and a as negated two’s complement numbers.
1
2
Separate filters can be stored for the DAI1 and DAI2
playback paths.
DV1G:
0/6/12/18dB
+
MULTI BAND ALC
DVEQ1:
0dB TO -15dB
DVEQ2:
0dB TO -15dB
SPVOLL:
+8dB TO -62dB
SPKLVDD
SPKLP
5-BAND
PARAMETRIC
EQ
5-BAND
PARAMETRIC
EQ
+6dB
SPLEN
SPKLN
MIX
EQ1EN
EQ2EN
SPKLGND
SPKRVDD
MIXSPL
POWER/
DISTORTION LIMITER
EXCURSION LIMITER
DACL
MIX
DALEN
MIXDAL
AUDIO/
SPKRP
SPKRN
FILTERS
DV2:
0dB TO -15dB
+6dB
SPREN
DCB2
MIX
SPVOLR:
+8dB TO -62dB
SPKRGND
MIXSPR
AUDIO/
VOICE
FILTERS
DV1:
MIX
0dB TO -15dB
DACR
MODE1
DVFLT
DAREN
MIXDAR
Figure 27. Speaker Amplifier Signal Processing Block Diagram
���������������������������������������������������������������� Maxim Integrated Products 99
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 24. Excursion Limiter Registers
REGISTER
BIT
NAME
DESCRIPTION
Excursion Limiter Corner Frequency
6
The excursion limiter has limited sliding range and minimum corner frequencies. Listed
below are all the valid filter combinations.
LOWER CORNER UPPER CORNER
FREQUENCY FREQUENCY
Excursion limiter disabled
MINIMUM BIQUAD
CORNER FREQUENCY
DHPUCF DHPLCF
5
4
DHPUCF
—
—
—
—
—
100Hz
—
—
000
001
010
011
100
000
001
010
011
00
00
00
00
00
11
01
10
10
400Hz
600Hz
800Hz
1kHz
Programmable using biquad
0x41
200Hz
400Hz
400Hz
400Hz
600Hz
800Hz
1
0
—
Programmable
using biquad
400Hz
600Hz
800Hz
1kHz
200Hz
300Hz
400Hz
500Hz
001
010
011
100
11
11
11
11
DHPLCF
ALCRLS
DHPTH
Programmable
using biquad
Programmable
using biquad
Programmable
using biquad
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level
Control section for ALC release times. Excursion limiter release time is defined as the
time required to slide from the high corner frequency to the low corner frequency.
6
VALUE
000
001
010
011
100
101
110
111
EXCURSION LIMITER RELEASE TIME (s)
4
2
1
0x43
5
4
0.5
0.25
0.25
Reserved
Reserved
Excursion Limiter Threshold
Measured at the Class D speaker amplifier outputs. Signals above the threshold use
the upper corner frequency. Signals below the threshold use the lower corner fre-
3
2
1
0
quency. V
must correctly reflect the voltage of SPKLVDD to achieve accurate
BAT
thresholds.
000 = 0.34V
001 = 0.71V
010 = 1.30V
011 = 1.77V
100 = 2.33V
101 = 3.25V
110 = 4.25V
111 = 4.95V
P
P
P
P
P
P
P
P
0x42
��������������������������������������������������������������� Maxim Integrated Products 100
MAX98088
Stereo Audio Codec
with FlexSound Technology
Power Limiter
The IC’s power limiter includes user-programmable time
constants and power thresholds to match a wide range
of loudspeakers. Program the power limiter’s threshold to
match the loudspeaker’s rated power handling. This can
be determined through measurement or the loudspeak-
er’s specification. Program time constant 1 to match the
voice coil’s thermal time constant. Program time constant
2 to match the magnet’s thermal time constant. The time
constants can be determined by plotting the voice coil’s
resistance vs. time as power is applied to the speaker.
The IC’s power limiter tracks the continuous power deliv-
ered to the loudspeaker and briefly mutes the speaker
amplifier output if the speaker is at risk of sustaining
permanent damage.
Loudspeakers are typically damaged when the voice coil
overheats due to extended operation above the rated
power. During normal operation, heat generated in the
voice coil is transferred to the speaker’s magnet, which
transfers heat to the surrounding air. For the voice coil
to overheat, both the voice coil and the magnet must
overheat. The result is that a loudspeaker can operate
above its rated power for a significant time before it heats
sufficiently to cause damage.
Table 25. Power Limiter Registers
REGISTER
BIT
NAME
DESCRIPTION
Power Limiter Threshold
If the continuous output power from the speaker amplifiers exceeds this threshold,
the output is briefly muted to protect the speaker. The threshold is measured in watts
assuming an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/
SPKRVDD to achieve accurate thresholds.
7
THRESHOLD
(W)
THRESHOLD
(W)
VALUE
VALUE
6
5
Power limiter
disabled
0x0
0x8
0.27
PWRTH
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0.05
0.06
0.09
0.11
0.13
0.18
0.22
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0.35
0.48
0.72
1.00
1.43
1.57
1.80
0x44
4
2
Power Limiter Weighting Factor
Determines the balance between time constant 1 and 2 to match the dominance of
each time constant in the loudspeaker.
VALUE
000
T1 (%)
50
T2 (%)
50
1
0
001
62.5
75
37.5
25
PWRK
010
011
87.5
100
12.5
25
12.5
0
100
101
87.5
75
110
111
37.5
62.5
��������������������������������������������������������������� Maxim Integrated Products 101
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 25. Power Limiter Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
Power Limiter Time Constant 2
Select a value that matches the thermal time constant of the loudspeaker’s magnet.
7
TIME CONSTANT
(min)
TIME CONSTANT
(min)
VALUE
VALUE
6
5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Disabled
0.50
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
3.75
5.00
PWRT2
0.67
6.66
0.89
8.88
1.19
Reserved
Reserved
Reserved
Reserved
1.58
4
3
2.11
2.81
0x45
Power Limiter Time Constant 1
Select a value that matches the thermal time constant of the loudspeaker’s voice coil.
TIME CONSTANT
(s)
TIME CONSTANT
(s)
VALUE
VALUE
2
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Disabled
0.50
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
3.75
5.00
PWRT1
0.67
6.66
1
0
0.89
8.88
1.19
Reserved
Reserved
Reserved
Reserved
1.58
2.11
2.81
Distortion Limiter
The IC’s distortion limiter ensures that the speaker amplifier’s output does not exceed the programmed THD+N limit.
The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is
clipped. If the distortion exceeds the programmed threshold, the output gain is reduced.
��������������������������������������������������������������� Maxim Integrated Products 102
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 26. Distortion Limiter Registers
REGISTER
BIT
NAME
DESCRIPTION
Distortion Limit
Measured in % THD+N.
7
VALUE
THD+N LIMIT (%)
VALUE
THD+N LIMIT (%)
6
5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Limiter disabled
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
12
14
16
18
20
21
22
24
< 1
1
THDCLP
2
4
0x46
6
4
0
8
10
Distortion Limiter Release Time Constant
Duration of time required for the speaker amplifier’s output gain to adjust back to the
nominal level after a large signal has passed.
THDT1
0 = 1.4s
1 = 2.8s
When the input signal level is less than 10% of PVDD,
the switching frequency is reduced to a low rate. This
minimizes switching losses in the charge pump. When
the input signal exceeds 10% of PVDD, the switching fre-
quency increases to support the load current.
Headphone
DirectDrive Headphone Amplifier
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dis-
sipation and possible damage to both headphone and
headphone amplifier.
For input signals below 25% of PVDD, the charge pump
generates Q(PVDD/2) to minimize the voltage drop
across the amplifier’s power stage and thus improve
efficiency. Input signals that exceed 25% of PVDD cause
the charge pump to output QPVDD. The higher output
voltage allows for full output power from the headphone
amplifier.
Maxim’s second-generation DirectDrive architecture
uses a charge pump to create an internal negative sup-
ply voltage. This allows the headphone outputs of the ICs
to be biased at GND while operating from a single supply
(Figure 28). Without a DC component, there is no need
for the large DC-blocking capacitors. Instead of two large
(220µF typ) capacitors, the IC’s charge pump requires
3 small ceramic capacitors, conserving board space,
reducing cost, and improving the frequency response of
the headphone amplifier.
To prevent audible gliches when transitioning from the
Q(PVDD/2) output mode to the QPVDD output mode, the
charge pump transitions very quickly. This quick change
draws significant current from PVDD for the duration of
the transition. The bypass capacitor on PVDD supplies
the required current and prevents droop on PVDD.
The charge pump’s dynamic switching mode can be
2
turned off through the I C interface. The charge pump
can then be forced to output either Q(PVDD/2) or QPVDD
regardless of input signal level.
Charge Pump
The dual-mode charge pump generates both the positive
and negative power supply for the headphone amplifier.
To maximize efficiency, both the charge pump’s switching
frequency and output voltage change based on signal
level.
��������������������������������������������������������������� Maxim Integrated Products 103
MAX98088
Stereo Audio Codec
with FlexSound Technology
Class H Operation
A Class H amplifier uses a Class AB output stage with
power supplies that are modulated by the output signal.
In the case of the ICs, two nominal power-supply differ-
entials of 1.8V (+0.9V to -0.9V) and 3.6V (+1.8V to -1.8V)
V
DD
V
/2
DD
are available from the charge pump. Figure 29 shows the
operation of the output-voltage-dependent power supply
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
+V
DD
1.8V
32ms
HPVDD
0.9V
V
TH_H
OUTPUT
VOLTAGE
GND
V
TH_L
-0.9V
HPVSS
32ms
-1.8V
-V
DD
(V
)
SS
DirectDrive AMPLIFIER BIASING SCHEME
Figure 29. Class H Operation
Figure 28. Traditional Amplifier Output vs. DirectDrive Output
DACL
DALEN
DACR
DAREN
MIXHPL_
PATH SEL
HPVOLL:
MIX
+3dB TO -67dB
HPL
HPLEN
MIXHPL
HPSNS
HPR
MIXHPR_
PATH SEL
HPVOLR:
+3dB TO -67dB
MIX
HPREN
MIXHPR
Figure 30. Headphone Amplifier Block Diagram
��������������������������������������������������������������� Maxim Integrated Products 104
MAX98088
Stereo Audio Codec
with FlexSound Technology
Headphone Output Mixers
signal is selected, the mixer can be configured to attenu-
ate the signal by 6dB, 9dB, or 12dB. The stereo DAC
can bypass the headphone mixers, and be connected
directly to the headphone amplifiers to provide lower
power consumption.
The headphone amplifier mixer accepts input from the
stereo DAC, the line inputs (single-ended or differential),
and the MIC inputs. Configure the mixer to mix any com-
bination of the available sources. When more than one
Table 27. Headphone Output Mixer Register
REGISTER
BIT
7
NAME
DESCRIPTION
Left Headphone Output Mixer
1xxxxxxx = Right DAC
6
x1xxxxxx = MIC2
xx1xxxxx = MIC1
xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1)
xxxx1xxx = INB1
xxxxx1xx = INA2 (INADIFF = 0) or INA2-INB1 (INADIFF = 1)
xxxxxx1x = INA1
5
4
0x25
MIXHPL
3
2
1
xxxxxxx1 = Left DAC
0
Right Headphone Output Mixer
1xxxxxxx = Left DAC
x1xxxxxx = MIC2
xx1xxxxx = MIC1
xxx1xxxx = INB2 (INBDIFF = 0) or INB2-INB1 (INBDIFF = 1)
xxxx1xxx = INB1
7
6
5
4
0x26
MIXHPR
3
2
xxxxx1xx = INA2 (INADIFF = 0) or INA2-INA1 (INADIFF = 1)
xxxxxx1x = INA1
xxxxxxx1 = Right DAC
1
0
Right Headphone Mixer Path Select
0 = Directly connect to the right DAC (bypass right headphone output mixer)
1 = Right headphone output mixer
MIXHPR_ PATH
SEL
5
Left Headphone Mixer Path Select
0 = Directly connect to the left DAC (bypass left headphone output mixer)
1 = Left headphone output mixer
MIXHPL_ PATH
SEL
4
3
Right Headphone Mixer Gain Select
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
0x27
MIXHPR
_GAIN
2
1
Left Headphone Mixer Gain Select
00 = 0dB
01 = -6dB
10 = -9dB
11 = -12dB
MIXHPL
_GAIN
0
��������������������������������������������������������������� Maxim Integrated Products 105
MAX98088
Stereo Audio Codec
with FlexSound Technology
Headphone Output Volume
Table 28. Headphone Output Level Register
REGISTER
BIT
NAME
DESCRIPTION
Headphone Output Mute
0 = Disabled
7
HPLM/HPRM
1 = Enabled
Left/Right Headphone Output Volume Level
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
VOLUME (dB)
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
VOLUME (dB)
4
3
-67
-63
-59
-55
-51
-47
-43
-40
-37
-34
-31
-28
-25
-22
-19
-17
-15
-13
-11
-9
-7
-5
0x39/0x3A
-4
HPVOLL/HPVOLR
-3
2
1
0
-2
-1
0
+1
+1.5
+2
+2.5
+3
��������������������������������������������������������������� Maxim Integrated Products 106
MAX98088
Stereo Audio Codec
with FlexSound Technology
an external receiver amplifier is used, route its output to
the left speaker through RECP/RXINP and RECN/RXINN,
bypassing the Class D amplifier. In systems where an
external amplifier drives both the receiver and the IC’s
line input, one of the differential signals can be discon-
nected from the receiver when not needed by passing it
through the analog switch that connects RECP/RXINP to
RECN/RXINN.
Output Bypass Switches
The IC includes two output bypass switches that solve
common applications problems. When a single trans-
ducer is used for the loudspeaker and receiver, the need
exists for two amplifiers to power the same transducer.
Bypass switches connect the IC’s receiver amplifier
output to the speaker amplifier’s output, allowing either
amplifier to power the same transducer. In systems where
10I*
EXTERNAL
RECEIVER
AMP
RECP/RXINP
RECP/RXINP
RECN/RXINN
RECP/RXINP
RECN/RXINN
0dB
0dB
0dB
EXTERNAL
RECEIVER
AMP
RECLEN
RECLEN
RECLEN
10I*
RECN/RXINN
0dB
0dB
0dB
RECBYP
SPKBYP
RECBYP
SPKBYP
RECBYP
SPKBYP
RECREN
RECREN
RECREN
SPKLVDD
SPKLP
SPKLVDD
SPKLP
SPKLVDD
SPKLP
+6dB
+6dB
+6dB
SPKLN
SPKLN
SPKLN
SPKLGND
SPKLGND
SPKLGND
SPLEN
SPLEN
SPLEN
POWER/DISTORTION
LIMITER
POWER/DISTORTION
LIMITER
POWER/DISTORTION
LIMITER
*OPTIONAL 10I RESISTORS IMPROVE DISTORTION
THROUGH THE ANALOG SWITCH.
SPEAKER AMPLIFIER BYPASS USING AN
EXTERNAL RECEIVER AMPLIFIER
SPEAKER AMPLIFIER BYPASS USING THE
INTERNAL RECEIVER AMPLIFIER
CONTROLLING AN EXTERNAL RECEIVE
AMPLIFIER AND SPEAKER
Figure 31. Output Bypass Switch Block Diagrams
Table 29. Output Bypass Switches Register
REGISTER
BIT
NAME
INABYP
MIC2BYP
DESCRIPTION
7
See the Microphone Inputs section.
4
RXINP to RXINN Bypass Switch
Shorts RXINP to RXINN allowing a signal to pass through the ICs. Disable the receiver
1
0
RECBYP
SPKBYP
amplifier when RECBYP = 1.
0 = Disabled
1 = Enabled
0x4A
RXIN to SPKL Bypass Switch
Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external receiv-
er amplifier to power the left speaker. Disable the left speaker amplifier when SPKBYP
= 1.
0 = Disabled
1 = Enabled
��������������������������������������������������������������� Maxim Integrated Products 107
MAX98088
Stereo Audio Codec
with FlexSound Technology
enabled, volume slewing also occurs at device turn-on
and turn-off. During turn-on the volume is set to mute
before the output is enabled. Once the output is on, the
volume ramps to the desired level. At turn-off the volume
is ramped to mute before the outputs are disabled.
Click-and-Pop Reduction
The IC includes extensive click-and-pop reduction cir-
cuitry. The circuitry minimizes clicks and pops at turn-on,
turn-off, and during volume changes.
Zero-crossing detection is implemented on all analog
PGAs and volume controls to prevent large glitches when
volume changes are made. Instead of making a volume
change immediately, the change is made when the audio
signal crosses the midpoint. If no zero-crossing occurs
within the timeout window, the change is forced.
When there is no audio signal zero-crossing detection
can prevent volume slewing from occurring. Enable
enhanced volume slewing to prevent the volume control-
ler from requesting another volume level until the previ-
ous one has been set. Each step in the volume ramp then
occurs after a zero crossing has occurred in the audio
signal or the timeout window has expired. During turn-off,
enhance volume slewing is always disabled.
Volume slewing breaks up large volume changes into the
smallest available step size and the steps through each
step between the initial and final volume setting. When
Table 30. Click-and-Pop Reduction Register
REGISTER
BIT
NAME
DESCRIPTION
Enhanced Volume Smoothing
During volume slewing, the controller waits for each step in the ramp to be applied
before sending the next step. When zero-crossing detection is enabled this prevents
large steps in the output volume when no zero crossings are detected.
0 = Enabled
7
VS2EN
1 = Disabled
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
Volume Adjustment Smoothing
Volume changes are smoothed by stepping through intermediate steps. Also ramps
the volume from minimum to the programmed value at turn-on and back to minimum at
6
5
turn-off.
0 = Enabled
1 = Disabled
VSEN
ZDEN
0x47
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
Zero-Crossing Detection
Holds volume changes until there is a zero crossing in the audio signal. This reduces
click and pop during volume changes (zipper noise). If no zero crossing is detected
within 100ms, the volume change is forced.
0 = Enabled
1 = Disabled
Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC,
HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
1
0
EQ2EN
EQ1EN
See the 5-Band Parametric EQ section.
��������������������������������������������������������������� Maxim Integrated Products 108
MAX98088
Stereo Audio Codec
with FlexSound Technology
through JACKSNS. To detect a jack insertion and
removal, the ICs must be powered on and MICBIAS
enabled. Set JDETEN, MBEN, BIASEN, and VCMEN bits
to enable jack detection circuitry. JACKSNS is pulled up
by MICBIAS as long as no load is applied to JACKSNS.
Table 31 shows the change in JKSNS that occurs when
a jack is inserted and removed.
Jack Detection
The IC features jack detection that can detect the inser-
tion and removal of a jack. When a jack is detected, an
interrupt on IRQ can be triggered to alert the microcon-
troller of the event. Figure 32 shows the typical configura-
tion for jack detection.
Jack Detection and Removal
When the IC is in normal operation and the MICBIAS is
enabled, jack insertion and removal can be detected
HPL
MICBIAS
JACKSNS
HPR
MIC1P
Figure 32. Typical Configuration for Jack Detection
Table 31. Change in JKSNS Upon Jack Insertion
JACK TYPE
MBEN = 1, BIASEN = 1, VCMEN = 1
GND
GND
R
L
JKSNS: 1 è 0
MIC
GND
R
L
JKSNS: 1 è 0
Table 32. Change in JKSNS Upon Jack Removal
JACK TYPE
MBEN = 1, BIASEN = 1, VCMEN = 1
GND
GND
R
L
JKSNS: 0 è 1
JKSNS: 0 è 1
MIC
GND
R
L
��������������������������������������������������������������� Maxim Integrated Products 109
MAX98088
Stereo Audio Codec
with FlexSound Technology
Table 33. Jack Detection Registers
REGISTER
BIT
NAME
DESCRIPTION
JACKSNS State
Reports the status of JACKSNS when JDETEN = 1, MBEN = 1, BIASEN = 1, and
VCMEN = 1.
0 = JACKSNS low
1 = JACKSNS high
0x02
(Read Only)
6
JKSNS
Jack Detection Enable
0 = Disabled
1 = Enabled
7
1
0
JDETEN
JDEB
Jack Detection Debounce
Configures the debounce time for setting JDET.
00 = 25ms
01 = 50ms
10 = 100ms
11 = 200ms
0x4B
Battery Measurement
The IC measures the voltage applied to SPKLVDD (typically the battery voltage) and reports the value in register 0x03.
This value is also used by the speaker limiter circuitry to set accurate thresholds. When the battery measurement func-
tion is disabled, the battery voltage is user programmable.
Table 34. Battery Measurement Registers
REGISTER
BIT
NAME
DESCRIPTION
4
Battery Voltage
Read VBAT when V
3
= 1 to determine V . Program VBAT when V
SPKLVDD BATEN
BATEN
0x03
2
VBAT
= 0 to allow proper speaker amplifier signal processing. Calculate/program the battery
voltage using the following formula:
1
V
= 2.55V + [VBAT/10]
BATTERY
0
7
See the Power Management section.
SHDN
Battery Measurement Enable. Enables an internal ADC to measure V
0 = Disabled (register 0x03 readable and writeable)
1 = Enabled (register 0x03 read only)
.
SPKLVDD
6
VBATEN
0x51
3
2
1
0
PERFMODE
HPPLYBCK
PWRSV8K
PWRSV
See the Power Management section.
See the Power Management section.
See the Power Management section.
See the Power Management section.
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MAX98088
Stereo Audio Codec
with FlexSound Technology
either by poling register 0x00 or configuring the IRQ to
pull low when specific events occur. IRQ is an open-drain
output that requires a pullup resistor for proper operation.
Register 0x0F determines which bits in the status register
trigger IRQ to pull low.
Device Status
The IC uses register 0x00 and IRQ to report the status of
various device functions. The status register bits are set
when their respective events occur, and cleared upon
reading the register. Device status can be determined
Table 35. Status and Interrupt Registers
REGISTER
BIT
NAME
DESCRIPTION
Full Scale
0 = All digital signals are less than full scale.
1 = The DAC or ADC signal path has reached or exceeded full scale. This typically
indicates clipping.
7
CLD
Volume Slew Complete
SLD reports that any of the programmable-gain arrays or volume controllers has com-
pleted slewing from a previous setting to a new programmed setting. If multiple gain
arrays or volume controllers are changed at the same time, the SLD flag is set after the
last volume slew completes. SLD also reports when the digital audio interface soft-start
or soft-stop process has completed. MCLK is required for proper SLD operation.
0 = No volume slewing sequences have completed since the status register was last
read.
6
SLD
0x00
(Read Only)
1 = Volume slewing complete.
Digital Audio Interface Unlocked
5
1
ULK
0 = Both digital audio interfaces are operating normally.
1 = Either digital audio interface is configured incorrectly or receiving invalid clocks.
Jack Configuration Change
JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first
time power is applied to the IC. Read the status register following such an event to clear
JDET and allow for proper jack detection.
JDET
0 = No change in jack configuration.
1 = Jack configuration has changed.
Full-Scale Interrupt Enable
0 = Disabled
1 = Enabled
7
6
5
1
ICLD
ISLD
IULK
IJDET
Volume Slew Complete Interrupt Enable
0 = Disabled
1 = Enabled
0x0F
Digital Audio Interface Unlocked Interrupt Enable
0 = Disabled
1 = Enabled
Jack Configuration Change Interrupt Enable
0 = Disabled
1 = Enabled
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Device Revision
Table 36. Device Revision Register
REGISTER
BIT
7
NAME
DESCRIPTION
6
5
4
0xFF
(Read Only)
Device Revision Code
REV is always set to 0x40.
REV
3
2
1
0
I2C Serial Interface
protect the digital inputs of the IC from high voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
The IC features an I2C/SMBusK-compatible, 2-wire
serial interface comprising a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate com-
munication between the IC and the master at clock rates
up to 400kHz. Figure 5 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I, is
required on SDA. SCL operates only as an input. A pullup
resistor, typically greater than 500I, is required on SCL
if there are multiple masters on the bus, or if the single
master has an open-drain SCL output. Series resistors
in line with SDA and SCL are optional. Series resistors
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 33). A START condition
from the master signals the beginning of a transmission
to the IC. The master terminates transmission, and frees
the bus, by issuing a STOP condition. The bus remains
active if a REPEATED START condition is generated
instead of a STOP condition.
Early STOP Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the same
SCL high pulse as the START condition.
S
Sr
P
SCL
SDA
Figure 33. START, STOP, and REPEATED START Conditions
SMBus is a trademark of Intel Corp.
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Slave Address
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when the
IC is in read mode. An acknowledge is sent by the master
after each read byte to allow data transfer to continue. A
not acknowledge is sent when the master reads the final
byte of data from the IC, followed by a STOP condition.
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 0010000. Setting
the read/write bit to 1 (slave address = 0x21) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x20) configures the ICs for write mode. The
address is the first byte of information sent to the IC after
the START condition.
Write Data Format
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte
of data to configure the internal register address pointer,
one or more bytes of data, and a STOP condition. Figure 35
illustrates the proper frame format for writing one byte of
data to the IC. Figure 35 illustrates the frame format for
writing n-bytes of data to the IC.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 34). The IC pulls down SDA dur-
ing the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 34. Acknowledge
ACKNOWLEDGE FROM MAX98088
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX98088
ACKNOWLEDGE FROM MAX98088
REGISTER ADDRESS
A
A
DATA BYTE
1 BYTE
A
P
S
SLAVE ADDRESS
O
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 35. Writing One Byte of Data to the ICs
ACKNOWLEDGE FROM MAX98088
ACKNOWLEDGE FROM MAX98088
B5 B4 B3 B2 B1 B0
B6 B5 B4 B3 B2 B1 B0
B7
B6
B7
ACKNOWLEDGE FROM MAX98088
ACKNOWLEDGE FROM MAX98088
REGISTER ADDRESS
A
O
S
SLAVE ADDRESS
R/W
A
A
P
A
DATA BYTE n
1 BYTE
DATA BYTE 1
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 36. Writing n-Bytes of Data to the ICs
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MAX98088
Stereo Audio Codec
with FlexSound Technology
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the ICs. The ICs
acknowledge receipt of the address byte during the
master-generated 9th SCL pulse.
The first byte transmitted from the ICs is the content of
register 0x00. Transmitted data is valid on the rising
edge of SCL. The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continuous
frame. A STOP condition can be issued after any number
of read data bytes. If a STOP condition is issued followed
by another read operation, the first data byte to be read
is from register 0x00.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer tells
the IC where to write the next byte of data. An acknowl-
edge pulse is sent by the ICs upon receipt of the address
pointer data.
The address pointer can be preset to a specific register
before a read command is issued. The master pre-
sets the address pointer by first sending the IC’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/W bit set to 1. The
IC then transmits the contents of the specified register.
The address pointer autoincrements after transmitting the
first byte.
The third byte sent to the ICs contains the data that is
written to the chosen register. An acknowledge pulse
from the ICs signals receipt of the data byte. The address
pointer autoincrements to the next register address after
each received data byte. This autoincrement feature
allows a master to write to sequential registers within one
continuous frame. The master signals the end of trans-
mission by issuing a STOP condition. Register addresses
greater than 0xC7 are reserved. Do not write to these
addresses.
The master acknowledges receipt of each read byte during
the acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte. The
final byte must be followed by a not acknowledge from the
master and then a STOP condition. Figure 37 illustrates
the frame format for reading one byte from the IC.Figure 38
illustrates the frame format for reading multiple bytes
from the ICs.
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The IC acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read com-
mand resets the address pointer to register 0x00.
ACKNOWLEDGE FROM MAX98088
ACKNOWLEDGE FROM MAX98088
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX98088
NOT ACKNOWLEDGE FROM MASTER
S
SLAVE ADDRESS
R/W
O
A
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
A
P
REPEATED START
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 37. Reading One Byte of Data from the ICs
ACKNOWLEDGE FROM MAX98088
ACKNOWLEDGE FROM MAX98088
ACKNOWLEDGE FROM MAX98088
S
O
A
A
SLAVE ADDRESS
R/W
REGISTER ADDRESS
SLAVE ADDRESS
DATA BYTE
1 BYTE
Sr
1
A
A
REPEATED START
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 38. Reading n Bytes of Data from the ICs
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Applications Information
Typical Operating Circuits
Figures 39 and 40 provide example operating circuits for the ICs. sThe external components shown are the minimum
required for the ICs to operate. Additional components may be required by the application.
2.8V TO 5.5V
1.8V
10FF
1.8V TO 3.6V
1.8V TO 3.6V
1FF
1FF
1FF
1FF
1FF
1FF
1FF
1.8V TO
5.5V
DVDD
PVDD
AVDD
SPKLVDD SPKRVDD DVDDS2
DVDDS1
10kI
BCLKS2
TO MICROCONTROLLER
IRQ
DIGITAL
AUDIO
PORT 2
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
SDA
LRCLKS2
SDINS2
10MHz TO 60MHz CLOCK INPUT
SDOUTS2
DIGITAL AUDIO
PORT 1
JACKSNS
JACKSNS
BYPASS
SWITCH
INPUT
RECP/RXINP
RECN/RXINN
2
I C CONTROL
PORT
SCL
SPKLP
SPKLN
8I
8I
MICROPHONE
OUTPUT TO
BASEBAND
MIC1P/DIGMICDATA
MIC1N/DIGMICCLK
MAX98088
SPKRP
SPKRN
MICBIAS
MIC2P
JACKSNS
1kI
2.2kI
1FF
1FF
1FF
1FF
1FF
HPR
HPL
HEADSET
MICROPHONE
MIC2N
HPSNS
INA1/EXTMICP
INA2/EXTMICN
INB1
HANDSET
MICROPHONE
REF
REG
1kI
1FF
1FF
LINE INPUT
1FF
2.2FF
INB2
DGND AGND HPGND SPKRGND SPKLGND HPVDD
HPVSS
C1N
C1P
1FF
1FF
1FF
Figure 39. Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch
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MAX98088
Stereo Audio Codec
with FlexSound Technology
2.8V TO 5.5V
1.8V
10FF
1.8V TO 3.6V
1.8V TO 3.6V
1FF
1FF
1FF
1FF
1FF
1FF
1FF
1.8V TO
5.5V
DVDD
PVDD
AVDD
SPKLVDD SPKRVDD DVDDS2
DVDDS1
10kI
BCLKS2
TO MICROCONTROLLER
IRQ
10MHz TO 60MHz
CLOCK INPUT
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
SDA
LRCLKS2
SDINS2
DIGITAL
AUDIO
PORT 2
SDOUTS2
JACKSNS
DIGITAL AUDIO
PORT 1
JACKSNS
RECP/RXINP
RECN/RXINN
32I
2
I C CONTROL
PORT
SCL
DATA
SPKLP
SPKLN
DIGITAL
MIC 1
8I
8I
MIC1P/DIGMICDATA
MIC1N/DIGMICCLK
CLOCK
DATA
MAX98088
SPKRP
SPKRN
DIGITAL
MIC 2
CLOCK
MICBIAS
MIC2P
2.2kI
JACKSNS
1FF
1FF
1FF
1FF
1FF
HPR
HPL
HEADSET
MICROPHONE
MIC2N
HPSNS
INA1/EXTMICP
INA2/EXTMICN
INB1
REF
REG
LINE INPUT
LINE INPUT
1FF
1FF
1FF
2.2FF
INB2
DGND AGND HPGND SPKRGND SPKLGND HPVDD
HPVSS
C1N
C1P
1FF
1FF
1FF
Figure 40. Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier
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MAX98088
Stereo Audio Codec
with FlexSound Technology
In RF applications, improvements to both layout and com-
ponent selection decrease the IC’s susceptibility to RF
noise and prevent RF signals from being demodulated into
audible noise. Trace lengths should be kept below 1/4 of
the wavelength of the RF frequency of interest. Minimizing
the trace lengths prevents them from functioning as anten-
nas and coupling RF signals into the IC. The wavelength
(l) in meters is given by: l = c/f where c = 3 x 108 m/s, and
f = the RF frequency of interest.
Filterless Class D Operation
Traditional Class D amplifiers require an output filter to
recover the audio signal from the amplifier’s output. The
filters add cost, increase the solution size of the amplifier,
and can decrease efficiency and THD+N performance.
The traditional PWM scheme uses large differential output
swings (2 x V
peak to peak) and causes large ripple
DD
currents. Any parasitic resistance in the filter components
results in a loss of power, lowering the efficiency.
Route audio signals on middle layers of the PCB to allow
ground planes above and below to shield them from RF
interference. Ideally, the top and bottom layers of the
PCB should primarily be ground planes to create effec-
tive shielding.
The IC does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear
to recover the audio component of the square-wave out-
put. Eliminating the output filter results in a smaller, less
costly, more efficient solution.
Additional RF immunity can also be obtained by rely-
ing on the self-resonant frequency of capacitors as it
exhibits a frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capaci-
tors typically exhibit self resonance at the RF frequencies
of interest. These capacitors, when placed at the input
pins, can effectively shunt the RF noise to ground. For
these capacitors to be effective, they must have a low-
impedance, low-inductance path to the ground plane.
Avoid using microvias to connect to the ground plane
whenever possible as these vias do not conduct well at
RF frequencies.
Because the frequency of the IC’s output is well beyond
the bandwidth of most speakers, voice coil movement
due to the square-wave frequency is very small. Although
this movement is small, a speaker not designed to handle
the additional power can be damaged. For optimum
results, use a speaker with a series inductance > 10FH.
Typical 8I speakers exhibit series inductances in the
20FH to 100FH range.
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its har-
monics that is easily demodulated by audio amplifiers.
The IC is designed specifically to reject RF signals; how-
ever, PCB layout has a large impact on the susceptibility
of the end product.
Startup/Shutdown Sequencing
To ensure proper device initialization and minimal click-
and-pop, program the IC’s SHDN = 1 after configuring all
registers. Table 37 lists an example startup sequence for
the device. To shut down the IC, simply set SHDN = 0.
Table 37. Example Startup Sequence
SEQUENCE
DESCRIPTION
REGISTERS
0x51
1
2
Ensure SHDN = 0
Configure clocks
0x10 to 0x13, 0x19 to 0x1B
0x14 to 0x17, 0x1C to 0x1F
0x18, 0x20, 0x3F to 0x46
0x52 to 0xC9
3
Configure digital audio interface
Configure digital signal processing
Load coefficients
4
5
6
Configure mixers
0x22 to 0x2D
7
Configure gain and volume controls
Configure miscellaneous functions
Enable desired functions
Set SHDN = 1
0x2E to 0x3E
8
0x47 to 0x4B
9
0x4C, 0x50
10
0x51
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Many configuration options in the ICs can be made
while the devices are operating, however, some regis-
ters should only be adjusted when the corresponding
audio path is disabled. Table 38 lists the registers that
are sensitive during operation. Either disable the cor-
responding audio path or set SHDN = 0 while changing
these registers.
that removes the DC bias from an incoming analog
signal. The AC coupling capacitor allows the amplifier
to automatically bias the signal to an optimum DC level.
Assuming zero-source impedance, the -3dB point of the
highpass filter is given by:
1
f
=
-3dB
2πR C
IN IN
Component Selection
Choose C so that f
is well below the lowest fre-
IN
-3dB
Optional Ferrite Bead Filter
In applications where speaker leads exceed 20mm,
additional EMI suppression can be achieved by using a
filter constructed from a ferrite bead and a capacitor to
ground (Figure 41). Use a ferrite bead with low DC resis-
tance, high-frequency (> 600MHz) impedance between
100Iand 600I, and rated for at least 1A. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
quency of interest. For best audio quality use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with high-
voltage coefficients, such as ceramics, may result in
increased distortion at low frequencies.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mIfor optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surface-
mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
Input Capacitor
An input capacitor, C , in conjunction with the input
IN
impedance of the IC line inputs forms a highpass filter
Table 38. Registers That Are Sensitive to Changes During Operation
REGISTER
0x10 to 0x13, 0x19 to 0x1B
0x14 to 0x17, 0x1C to 0x1F
0x18, 0x20
DESCRIPTION
Clock Control Registers
Digital Audio Interface Configuration
Digital Passband Filters
0x25 to 0x2D
Analog Mixers
0x52 to 0xC9
Digital Signal Processing Coefficients
SPK_P
SPK_N
MAX98088
Figure 41. Optional Class D Ferrite Bead Filter
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Charge-Pump Flying Capacitor
Charge-Pump Holding Capacitor
The holding capacitor (bypassing HPVSS) value and ESR
directly affect the ripple at HPVSS. Increasing the capac-
itor’s value reduces output ripple. Likewise, decreasing
the ESR reduces both ripple and output resistance.
Lower capacitance values can be used in systems with
low maximum output power levels. See the Output Power
vs. Load Resistance graph in the Typical Operating
Characteristics section for more information
The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the charge
pump. A value that is too small degrades the device’s
ability to provide sufficient current drive, which leads to a
loss of output voltage. Increasing the value of the flying
capacitor reduces the charge-pump output resistance to
an extent. Above 1FF, the on-resistance of the internal
switches and the ESR of external charge- pump capaci-
tors dominate.
Unused Pins
Table 39 shows how to connect the IC’s pins when
unused.
Table 39. Unused Pins
NAME
CONNECTION
Unconnected
Always connect
Always connect
Unconnected
Unconnected
Unconnected
Unconnected
AGND
NAME
INB1
CONNECTION
Unconnected
Unconnected
Unconnected
Always connect
AGND
SPKRP
SPKRVDD
SPKLVDD
SPKLP
INA2/MICEXTN
LRCLKS2
MCLK
RECN/RXINN
HPVDD
C1P
SDINS2
Unconnected
Unconnected
Unconnected
Always connect
Unconnected
Always connect
Always connect
Always connect
Always connect
Unconnected
Unconnected
Unconnected
DVDD
IRQ
MIC1P/DIGMICDATA
INA1/MICEXTP
DGND
HPGND
SPKRN
Unconnected
Always connect
Always connect
Unconnected
Unconnected
Unconnected
Unconnected
Unconnected
AGND
SPKRGND
SPKLGND
SPKLN
BCLKS2
SDA
SCL
RECP/RXINP
C1N
REG
REF
HPL
MIC1N/DIGMICCLK
MIC2P
HPVSS
SDINS1
LRCLKS1
HPSNS
SDOUTS2
DVDDS2
DVDD
Unconnected
AGND
Always connect
Always connect
Always connect
Always connect
Unconnected
Unconnected
INB2
Unconnected
Unconnected
DVDD
AVDD
HPR
PVDD
DVDDS1
SDOUTS1
BCLKS1
JACKSNS
AGND
Unconnected
Unconnected
Unconnected
MICBIAS
MIC2N
��������������������������������������������������������������� Maxim Integrated Products 119
MAX98088
Stereo Audio Codec
with FlexSound Technology
Recommended PCB Routing
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the ICs, parti-
tion the circuitry so that the analog sections of the IC are
separated from the digital sections. This ensures that the
analog audio traces are not routed near digital traces.
The IC uses a 63-bump WLP package. Figure 42 provides
an example of how to connect to all active bumps using
3 layers of the PCB. To ensure uninterrupted ground
returns, use layer 2 as a connecting layer between layer
1 and layer 2 and flood the remaining area with ground.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect AGND,
DGND, HPGND, SPKLGND, and SPKRGND directly to
the ground plane using the shortest trace length possible.
Proper grounding improves audio performance, minimizes
crosstalk between channels, and prevents any digital
noise from coupling into the analog audio signals.
Ground the bypass capacitors on MICBIAS, REG, and
REF directly to the ground plane with minimum trace
length. Also be sure to minimize the path length to
AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD,
DVDDS1, and DVDDS2 directly to DGND.
LAYER 1
Place the capacitor between C1P and C1N as close as
possible to the ICs to minimize trace length from C1P to
C1N. Inductance and resistance added between C1P
and C1N reduce the output power of the headphone
amplifier. Bypass HPVDD and HPVSS with a capaci-
tor located close to HPVSS with a short trace length to
HPGND. Close decoupling of HPVSS minimizes supply
ripple and maximizes output power from the headphone
amplifier.
LAYER 2
HPSNS senses ground noise on the headphone jack and
adds the same noise to the output audio signal, thereby
making the output (headphone output minus ground)
noise free. Connect HPSNS to the headphone jack shield
to ensure accurate pickup of headphone ground noise.
Bypass SPKLVDD and SPKRVDD to SPKLGND and
SPKRGND, respectively, with as little trace length as
possible. Connect SPKLP, SPKLN, SPKRP, and SPKRN
to the stereo speakers using the shortest traces pos-
sible. Reducing trace length minimizes radiated EMI.
Route SPKLP/SPKLN and SPKRP/SPKRN as differential
pairs on the PCB to minimize loop area, thereby the
inductance of the circuit. If filter components are used
on the speaker outputs, be sure to locate them as close
as possible to the IC to ensure maximum effectiveness.
Minimize the trace length from any ground-connected
passive components to SPKLGND and SPKRGND to
further minimize radiated EMI.
LAYER 3
Figure 42. Suggested Routing for the MAX98088
��������������������������������������������������������������� Maxim Integrated Products 120
MAX98088
Stereo Audio Codec
with FlexSound Technology
Route microphone signals from the microphone to the ICs
as a differential pair, ensuring that the positive and nega-
tive signals follow the same path as closely as possible
with equal trace length. When using single-ended micro-
phones or other single-ended audio sources, ground the
negative microphone input as close as possible to the
audio source and then treat the positive and negative
traces as differential pairs.
0.24mm
An evaluation kit (EV kit) is available to provide an exam-
ple layout for the IC. The EV kit allows quick setup of the
IC and includes easy-to-use software allowing all internal
registers to be controlled.
0.21mm
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability test-
ing results, refer to the Application Note 1891: Wafer-
Level Packaging (WLP) and Its Applications. Figure 43
shows the dimensions of the WLP balls used on the
MAX98088.
Figure 43. WLP Ball Dimensions
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX98088EWY+
-40NC to +85NC
63 WLP
+Denotes lead(Pb)-free/RoHS-compliant package.
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0462
LAND PATTERN NO.
63 WLP
W633A3+1
Refer to Application Note 1891
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MAX98088
Stereo Audio Codec
with FlexSound Technology
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
6/10
Initial release
—
1, 5–27, 29,
30, 33, 35, 37,
39, 41, 43,
46, 54, 55, 56,
63–67, 69, 70,
70, 74, 75, 77,
80, 81, 83–86,
90, 94–99, 101,
103, 104, 105,
107, 109, 110,
111, 113, 114,
119, 120
1
6/11
Made various updates, replaced TOCs 56 and 68
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
123
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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