MAX98372ETJ+T [MAXIM]
Digital Input Class D Amplifier with DHT and Brownout Protection;
| 型号： | MAX98372ETJ+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Digital Input Class D Amplifier with DHT and Brownout Protection |
| 文件： | 总100页 (文件大小：3293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
General Description
Benefits and Features
● Wide Supply Range (5.5V to 18V)
The MAX98372 is a high-efficiency, mono Class D audio
amplifier featuring dynamic headroom tracking (DHT)
and brownout protection. DHT automatically optimizes
the headroom available to the Class D amplifier as the
power supply voltage varies, due to sudden transients
and declining battery life to maintain a consistent listening
experience. A wide 5.5V to 18V supply range allows the
device to reach 19W into an 8Ω load.
● Dynamic Headroom Tracking Maintains a Consistent
Listening Experience
● Integrated Thermal Foldback Allows Robust
Operation in a WLP Package
● Remote Output Sensing Allows Up to 20dB THD+N
Improvement When Ferrites Are Used
● Class D Edge Rate Control Enables Filterless
Operation
● 110dB A-Weighted Dynamic Range
● Output Power at 1% THD+N:
• 15.7W into 8Ω, V
• 13.2W into 4Ω, V
● Output Power at 10% THD+N
• 19W into 8Ω, V = 17V
• 15.8W into 4Ω, V
● Speaker Amplifier Efficiency
• 91% at 10W into 8Ω, V
• 81% at 15W into 4Ω, V
● ALC Provides Battery Brownout Protection
● Extensive Click-and-Pop Suppression
The MAX98372’s flexible digital audio interface (DAI)
supports I S, left-justified, and TDM formats. The digital
2
audio interface accepts 32kHz, 44.1kHz, 48kHz, 88.2kHz,
and 96kHz sample rates with 16-/24-/32-bit data sup-
ported for all data formats. In TDM mode, the device can
support up to 16 channels of audio data. A unique clocking
structure eliminates the need for an external MCLK signal
that is typically needed for PCM communication. This
reduces pin count and simplifies board layout.
= 17V
= 12V
PVDD
PVDD
PVDD
PVDD
= 12V
= 12V
= 12V
PVDD
PVDD
Active emissions limiting with edge rate control minimizes
EMI and eliminates the need for output filtering found in
traditional Class D devices.
An 8-bit PVDD supply voltage ADC enables the dynamic
headroom tracking circuit. DHT optimizes audio program
peak behavior as the supply voltage varies and provides
flexible user-defined parameters.
● 30-Bump, 0.4mm WLP and 32-Pin TQFN Packages
Simplified Block Diagram
Thermal foldback protection ensures robust behavior
when the thermal limits of the device are exercised. The
circuit can be enabled to automatically reduce the output
power above a user specified temperature. This allows for
uninterrupted music playback even at high ambient tem-
peratures. Traditional thermal protection is also available
in addition to robust overcurrent protection.
DVDD
PVDD
MAX98372
THERMAL
FOLDBACK
I2C
All MAX98372 control is performed using a standard
2-wire, I C interface. One of sixteen slave addresses can
DHT
2
ALC
be selected through two, four-level address pins. The IC is
available in a 0.4mm pitch, 30-bump WLP and 32-pin TQFN
packages. It is specified over the extended, -40°C to +85°C
temperature range.
D
V
O
L
P
G
A
DAC
CLASS D
Applications
● Tablets
● Notebook Computers
● Soundbars
Ordering Information appears at end of data sheet.
19-7734; Rev 4; 3/20
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Detailed Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bump/Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bump/Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Digital Audio Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Configuring the DAI Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Configuring the Digital Audio Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Digital Passband Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Biquad Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Signal Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
PVDD ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Digital Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Output Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Dynamic Headroom Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
DHT Ballistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Thermal ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Thermal Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Thermal Foldback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Automatic Level Control (ALC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
TABLE OF CONTENTS (continued)
DOUT Operation and Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Interchip Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Multiamplifier Grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Double Data Drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Class D Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Ultra-Low EMI Filterless Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
V
and V
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PVDD
DVDD
Click-and-Pop Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Amplifier Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Thermal Shutdown Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Output Sensing When Using Ferrites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Clocking Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Early Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
I2C Slave Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Layout and Grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Startup Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Shutdown Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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MAX98372
Digital Input Class D Amplifier
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LIST OF FIGURES
Figure 1. I2S Audio Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Left-Justified Audio Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3.TDM Audio Interface Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. I2C Interface Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. I2S Digital Audio Format Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6. Left-Justified Digital Audio Format Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 7. TDM Digital Audio Format Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 8. Example of Dynamic Headroom Tracking in Mode 1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 9. Example of Dynamic Headroom Tracking in Mode 2 Operation with a High RP. . . . . . . . . . . . . . . . . . . . . 56
Figure 10. Example of Dynamic Headroom Tracking in Mode 2 Operation with a Low RP . . . . . . . . . . . . . . . . . . . . 57
Figure 11. Example of Dynamic Headroom Tracking in Mode 3a Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 12. Example of Dynamic Headroom Tracking in Mode 3b Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 13. Example of Dynamic Headroom Tracking in Mode 3b with Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 14. Dynamic Headroom Tracking Attack Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 15. Thermal Foldback Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 16. ALC Example 1: Battery Drops Below Brownout Threshold and Quickly Recovers . . . . . . . . . . . . . . . . . 67
Figure 17. ALC Example 2: Battery Drops Below Brownout Threshold and Stays Low . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 18. ALC Example 3: Battery Drops Below Brownout Threshold and Stays Long Enough for the Amp to Mute
(Non-Infinite Hold Time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 19. ALC Example 4: Battery Drops Below Brownout Threshold and Stays Long Enough for the Amp to Mute
(Infinite Hold Time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 20. ALC Example 5: Immediate Attenuation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 21. DOUT Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 22. Single Data Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 23. Double Data Drive illustration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 24. EMI Plot 1: 12in, 8Ω, 16V, ½ Power, No Ferrite Bead, Edge Rate +15%. . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 25. EMI Plot 2: 12in, 4Ω, 16V, ½ Power, No Ferrite Bead, Edge Rate +15%. . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 26. EMI Plot 3: 12in, 8Ω, 16V, ½ Power, Ferrite Bead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 27. EMI Plot 4: 12in, 4Ω, 16V, ½ Power, Ferrite Bead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 28. Typical Application Circuit with Ferrites Beads Used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 29. THD Performance Improvement Enabled by Remote Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 30. START, STOP, and REPEATED START Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 31. Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 32. Writing One Byte of Data to the MAX98372 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 33. n-Bytes of Data to the MAX98372 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 34. Reading One Byte of Data from the MAX98372 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 35. Reading n-Bytes of Data from the MAX98372. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 36. MAX98372+ WLP Ball Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Maxim Integrated
│ 4
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
LIST OF TABLES
Table 1. MAX98372 Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 2. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 3. Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4. Supported Sample Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5. Supported BCLK Rates in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6. Configuration for Digital Audio Interface Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 7. PCM Receive Channel Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 8. TDM Channel Selection for Mono Replay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9. Digital Highpass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. Biquad Filter Coefficient Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Signal Path Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 12. PVDD Measurement ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. Digital Volume Ramping and Digital Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. Digital Gain Settings and Output Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 15. Speaker Gain Minimum Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 16. Dynamic Headroom Tracking Attack Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 17. Dynamic Headroom Tracking Release Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 18. Dynamic Gain Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 19. Limiter Threshold Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 20. Manual Limiter Threshold Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 21. Limiter Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 22. Limiter Attack and Release Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 23. Thermal ADC Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 24. Thermal Foldback Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 25. Thermal Foldback Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 26. ALC Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 27. ALC Attack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 28. ALC Attenuation and Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 29. ALC Infinite Hold Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 30. ALC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Table 31. DHT INFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 33. Thermal and DHT Link Enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 32. THERM INFO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 34. InterChip Communication Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 35. DOUT Double Data Drive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 36. DOUT DHT Receive Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 37. DOUT Thermal Foldback Receive Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
LIST OF TABLES (CONTINUED)
Table 38. DOUT Transmit Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 39. DOUT ALC Receive Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 40. Extra BCLK Cycle Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 41. Manual High-Impedance Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 42. Speaker Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 43. Spread-Spectrum Modulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 44. Clock Monitor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 45. Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 46. Global Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 47. ADDR I2C Address Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 48. Recommended External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Maxim Integrated
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Detailed Functional Diagram
PVDD
V
REFC
DVDD
IRQ
INTERRUPT
DISPATCHER
DVDD
UVLO
LINEAR
REGULATOR
PVDD
UVLO
ADDR1
MAX98372
ADDR0
2
I C
CONTROL
REGISTERS
SCL
DECIMATION
FILTER
PVDD
ADC
LPF
SDA
DSP
TEMPERATURE
CLOCK
MONITOR
MONITOR
RESET
DYNAMIC
THERMAL
FOLDBACK
HEADROOM
TRACKING
AUTOMATIC
LEVEL CONTROL
MDLL
DOUT
DIN
OUTP SNS
OUTP
BI-
QUAD
INTERPOLATION
FILTER
DIGITAL AUDIO
INTERFACE
MIXER
VOL
DAC
SPEAKER AMPLIFIER
LRCLK
BCLK
OUTN
OUTN SNS
DGND
AGND
PGND
Maxim Integrated
│ 7
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Absolute Maximum Ratings
PVDD to PGND.....................................................-0.3V to +20V
Short-Circuit Duration
OUT_ to PGND ....................................-0.3V to (V
+ 0.3V)
Between OUTP, OUTN and PGND or PVDD........Continuous
Between OUTP and OUTN ..................................Continuous
PVDD
V
to AGND...................................................-0.3V to +2.2V
REFC
DVDD to DGND....................................................-0.3V to +2.2V
SDA, SCL, ADDR_, IRQ to DGND.......................-0.3V to +2.2V
BCLK, LRCLK, DIN,
Continuous Power Dissipation (T = +70°C) for Multilayer Board
A
(derate 27mW/°C above +70°C for WLP) .....................2.16W
(derate 34.5mW/°C above +70°C for TQFN).................2.76W
Junction Temperature......................................................+150°C
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature (reflow).......................................+260°C
RESET to DGND ..............................-0.3V to (V
+ 0.3V)
AGND, DGND to PGND ......................................-0.1V to +0.1V
DVDD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
WLP
TQFN
Junction-to-Ambient Thermal Resistance (θ )..........+29°C/W
Junction-to-Ambient Thermal Resistance (θ ) ........+37°C/W
JA
JA
Junction-to-Board Thermal Resistance (θ ).........+33.4°C/W
Junction-to-Board Thermal Resistance (θ ).........+19.3°C/W
JB
JB
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, C
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITION
MIN
5.5
TYP
MAX
18
UNITS
V
Power-Supply Voltage
Range
PVDD
V
V
V
V
1.14
1.98
DVDD
V
Regulator Output
V
2.0
4.3
REFC
REFC
PVDD Undervoltage
Lockout
PVDD
UVLO
3.65
4.75
DVDD Undervoltage
Lockout
DVDD
UVLO
0.75
V
SPK_SWCLK = 0
SPK_SWCLK = 1
472kHz
330kHz
9
7
2
12
Quiescent Current
Quiescent Current
I _
mA
mA
µA
Q PVDD
I _
2.6
10
10
5
Q DVDD
I
Software Shutdown
Supply Current
All DAI pins pulled low,
PVDD
I
_
SHDN SW
T
= +25°C
I
A
DVDD
I
Hardware Shutdown
Supply Current
V
= 0V,
RESET
PVDD
I
_
µA
ms
SHDN HW
T
= +25°C
I
1
A
DVDD
Volume ramping
disabled
10
30
10
30
From SW_EN bit set to
full operation
Turn-On Time
t
ON
Volume ramping
enabled
Volume ramping
disabled
From SW_EN bit cleared
to shutdown
Turn-Off Time
t
ms
OFF
Volume ramping
enabled
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│ 8
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Electrical Characteristics (continued)
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, C
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
DIGITAL FILTER CHARACTERISICS (LRCLK < 50kHz) (Note 5)
Ripple limit cutoff
0.43 x f
0.47 x f
S
Passband Cutoff
f
f
-3dB cutoff
Hz
PLP
S
-6.02dB cutoff
0.5 x f
S
Passband Ripple
Stopband Cutoff
f < f
-0.1
+0.1
dB
Hz
dB
PLP
SLP
0.58 x f
SLP
S
Stopband Attenuation
f > f
60
DIGITAL FILTER CHARACTERISICS (LRCLK > 50kHz) (Note 5)
Ripple limit cutoff
0.24 x f
0.31 x f
-0.1
S
Passband Cutoff
f
Hz
PLP
-3dB cutoff
S
Passband Ripple
Stopband Cutoff
f < f
+0.1
dB
Hz
dB
PLP
f
0.417 x f
SLP
S
Stopband Attenuation
f > f
60
80
SLP
DIGITAL HIGHPASS FILTER CHARACTERISTICS
DC Attenuation (Note 5)
dB
Hz
DC Blocking Cutoff
Frequency (Note 5)
Across all sample rates
DACHPF = 0x1
2
DACHPF = 0x2
DACHPF = 0x3
DACHPF = 0x4
DACHPF = 0x5
DACHPF = 0x6
50
100
200
400
800
Highpass Cutoff
Frequency
Across all sample rates
Hz
SPEAKER AMPLIFIER ELECTRICAL CHARACTERISTICS
DIGITAL VOLUME CONTROL
Digital Volume (max)
Digital Volume (min)
Volume Control Step Size
Output Offset Voltage
DVOL[6:0] = 0x00
DVOL[6:0] = 0x7E
0
dB
dB
dB
mV
-63
0.5
±1
VOS
T
= +25°C
±5
A
Peak voltage,
= +25°C, A-weighted,
32 samples per second,
digital audio inputs have
zero-code input
Into shutdown
-66
-60
T
A
Click-and-Pop Level
K
dBV
CP
Out of shutdown
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│ 9
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Electrical Characteristics (continued)
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, C
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
V
= 17V, Z = 8Ω +
L
PVDD
33µH, measured using the
EIAJ method,
Dynamic Range
DR
A-weighted
110
dB
-60dBFS 1kHz output
signal, referenced to 1%
output power
A-weighted
Unweighted
35
72
Integrated Output Noise
e
Z = 8Ω + 33µH
µV
RMS
N
L
Z = 8Ω + 33µH
8.2
L
Z = 8Ω + 33µH,
L
THD+N ≤ 1%, f = 1kHz
15.7
V
= 17V
PVDD
Z = 4Ω + 33µH
13.2
10.2
L
Output Power
P
W
OUT
Z = 8Ω + 33µH
L
Z = 8Ω + 33µH,
L
THD+N ≤ 10%, f = 1kHz
19
15.8
91
V
= 17V
PVDD
Z = 4Ω + 33µH
L
P
= 10W,
OUT
Z = 8Ω + 33µH
L
Efficiency
f = 1kHz
%
%
ηSPK
P
= 15W,
OUT
81
0.02
0.03
0.1
Z = 4Ω + 33µH
L
P
= 4W,
OUT
Z = 8Ω + 33µH
L
f = 1kHz
P
= 8W,
OUT
Z = 4Ω + 33µH
L
Total Harmonic Distortion
+ Noise
THD+N
P
= 4W,
OUT
Z = 8Ω + 33µH
L
f = Up to 6kHz
P
= 8W,
OUT
0.2
Z = 4Ω + 33µH
L
Maximum Frequency
Response Deviation
Maximum deviation above and below 1kHz
reference
0.2
dB
dB
Gain Error
A
f = 1kHz, V = 2.828V
RMS
-0.5
+0.5
VERROR
O
Maximum Channel-to-
Channel Phase Error
(Note 3)
Output phase shift between multiple devices
from 20Hz to 20kHz, across all sample rates
and DAI operating modes
1
deg
dB
V
PVDD
= 5.5V to 18V
85
75
60
PVDD Power-Supply
Rejection Ratio
PSRR
f = 20Hz to 10kHz, V
= 100mV
RIPPLE P-P
f = 10kHz to 20kHz, V
= 100mV
P-P
RIPPLE
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│ 10
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Electrical Characteristics (continued)
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, C
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
DVDD Power-Supply
Rejection Ratio
PSRR
f = 1kHz, V
= 50mV
100
RIPPLE
P-P
472
330
SPK_SWCLK = 0
SPK_SWCLK = 1
kHz
kHz
Output Switching
Frequency
Constant across all
sample rates
f
S
Output Stage
On-Resistance
R
PMOS + NMOS
0.425
6.0
Ω
ON
Z = 8Ω + 33µH or Z = 4Ω + 33µH, TQFN
L
L
4.5
5.0
package
Current Limit
I
A
LIM
Z = 8Ω + 33µH or Z = 4Ω + 33µH, WLP
6.0
L
L
SPK_SWCLK = 0
SPK_SWCLK = 1
±32.4
±15.4
kHz
kHz
Spread-Spectrum
Bandwidth
SSM_MODINDEX=0x01
AUTOMATIC LEVEL CONTROL (ALC)
From PVDD minimum threshold event to
audio attenuation
Brownout Response Time
12
µs
V
2-cell mode (ALC_RANGE = 0)
3-cell mode (ALC_RANGE = 1)
All brownout voltage threshold settings
5.5
7.8
7.3
10.95
+2.5
Brownout Voltage
Threshold Range
V
Brownout Voltage
Threshold Accuracy
-2.5
±1
%
THERMAL FOLDBACK
Attack Time
10
0.5
1
µs
THRM_SLOPE[1:0] = 0x0
THRM_SLOPE[1:0] = 0x1
THRM_SLOPE[1:0] = 0x2
Attenuation Slope
dB/°C
2
Max Attenuation
Release Time
12
3
dB
THRM_REL[1:0] = 0x0
THRM_REL[1:0] = 0x3
ms/dB
300
THERMAL SHUTDOWN
Trigger Point
(Note 3)
140
150
20
160
°C
°C
Hysteresis
PVDD ADC ELECTRICAL CHARACTERISTICS
Resolution
8
Bits
LSB
V
Absolute Error
1.2
ADC Voltage Range
5.35
18.15
ADC Lowpass Filter
Cutoff Frequency
0.0875
x f
S
-3dB limit
Hz
Maxim Integrated
│ 11
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Electrical Characteristics (continued)
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, C
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
ADC Lowpass Filter
Stopband Frequency
0.167
-40dB limit
Hz
x f
S
PVDD_ADC_BW[1:0] = 0x1
PVDD_ADC_BW[1:0] = 0x2
PVDD_ADC_BW[1:0] = 0x3
2
ADC Programmable
Lowpass Filter
20
Hz
200
DIGITAL I/O CHARACTERISTICS
DIN, BCLK, LRCLK, ADDR_, RESET
0.7 x
Input Voltage High
V
V
V
IH
V
DVDD
0.3 x
Input Voltage Low
V
IL
V
DVDD
+1
Input Leakage Current
Input Capacitance
I
, I
-1
µA
pF
IH IL
C
3
IN
INPUT (SDA, SCL)
0.7 x
Input Voltage High
Input Voltage Low
V
V
V
IH
V
DVDD
0.3 x
V
IL
V
DVDD
Input Hysteresis
V
200
3
mV
pF
HYS
Input Capacitance
Input Leakage Current
OUTPUT (SDA, IRQ)
Output Low Voltage
Output Current
C
IN
I
, I
T
= +25°C, input high
-1
+1
µA
IH IL
A
V
I
= 3mA
0.4
V
OL
SINK
I
13
mA
OL
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS
GLOBAL
f
LRCLK Frequency Range
Word Length
All DAI operating modes
All DAI operating modes
32
45
96
55
kHz
bits
%
LRCLK
16
24
32
BCLK Duty Cycle
Maxim Integrated
│ 12
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Electrical Characteristics (continued)
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, C
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Maximum jitter with
minimal performance
degradation
RMS jitter below 40kHz
RMS jitter above 40kHz
0.5
Maximum BCLK/LRCLK
Input Jitter
ns
0.9
2
PCM MODE (I C, LEFT-JUSTIFIED)
LRCLK Duty Cycle
45
10
55
%
LRCLK to BCLK Active
Edge Setup Time
t
ns
SYNCSET
LRCLK to BCLK Active
Edge Hold Time
t
10
10
ns
ns
SYNCHOLD
DIN to BCLK Active Edge
Setup Time
t
SETUP
DIN to BCLK Active Edge
Hold Time
t
10
ns
ns
HOLD
BCLK Period (Note 3)
t
160
BCLK
6.25
f
f
f
x 32
BCLK Frequency
(Note 3)
S
S
S
f
MHz
BCLK
x 48
x 64
TDM MODE
LRCLK Pulse Width
PW
Measured in number of BCLK cycles
Measured in number of BCLK cycles
511
1
cycles
cycles
ns
LRCLK
DIN Frame Delay after
LRCLK Edge
0
BCLK Period (Note 3)
t
f
20
BCLK
BCLK
BCLK Frequency
(Note 3)
All TDM operating modes
50
MHz
Maxim Integrated
│ 13
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
tBCLK
tBCLKH
VIH
VIL
VIH
VIH
tBCLKL
BCLK (INPUT)
LRCLK (INPUT)
VIL
VIL
tSYNCHOLD
tSYNCSET
VIH
VIL
tSETUP tHOLD
VIHLEFT MSB
DIN (INPUT)
RIGHT MSB
VIL
2
Figure 1. I S Audio Interface Timing Diagram
tBCLK
tBCLKH
VIH
VIL
VIH
VIH
tBCLKL
BCLK (INPUT)
LRCLK (INPUT)
VIL
VIL
tSYNCHOLD
tSYNCSET
VIH
VIL
tSETUP tHOLD
VIH
DIN (INPUT)
LEFT MSB VIL
RIGHT MSB
Figure 2. Left-Justified Audio Interface Timing Diagram
tBCLK
tBCLKL
tBCLKH
VIH
VIH
BCLK (INPUT)
tSYNCSET
VIL
VIL
tSYNCHOLD
VIH
LRCLK (INPUT)
DIN (INPUT)
VIL
tSETUP tHOLD
VIH
MSB
VIL
Figure 3.TDM Audio Interface Timing Diagrams
Maxim Integrated
│ 14
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
2
I C Timing Characteristics
(V
= 12V, V
= V
= 1.8V, V
= 0V, C
= 1x 220µF, 2x 10µF, 2x 0.1µF, CV
= 1µF, C
= 1µF, Z
= open,
PVDD
DVDD
RESET
GND
PVDD
REFC
DVDD
SPK
AC measurement bandwidth 20Hz to 22kHz, f = 48kHz, 24-bit data, T = T
to T
, unless, otherwise noted. Typical values are at
MAX
S
A
MIN
T
= +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C TIMING CHARACTERISTICS
Serial Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
Hold Time (Repeated) START
Condition
t
t
0.6
µs
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Setup Time for a Repeated
START Condition
0.6
µs
SU,STA
HD,DAT
Data Hold Time
Data Setup Time
t
0
900
300
ns
ns
t
100
20 +
SU,DAT
SDA and SCL Receiving Rise
Time (Note 4)
t
ns
R
0.1C
B
SDA and SCL Receiving Fall
Time (Note 4)
20 +
t
t
300
250
ns
ns
µs
pF
ns
F
0.1C
B
SDA Transmitting Fall Time
20
F
Setup Time for STOP
Condition
t
0.6
0
SU,STO
Bus Capacitance
C
400
50
B
Pulse Width of Suppressed
Spike
t
SP
Note 2: 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 3: Minimums and/or maximum limits shown are design targets and not 100% production tested.
Note 4: C in pF.
B
Note 5: Digital filter performance is invariant over temperature and production tested at T = +25°C.
A
Maxim Integrated
│ 15
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
2
Figure 4. I C Interface Timing Diagram
Typical Operating Characteristics
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T , unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
PVDD QUIESCENT CURRENT
vs. PVDD VOLTAGE
DVDD QUIESCENT CURRENT
vs. DVDD VOLTAGE
toc02
toc01
3.0
10
ZSPK = ∞
ZSPK = ∞
9
fSPK_SW = 472kHz
2.5
2.0
1.5
1.0
0.5
0.0
8
7
fSPK_SW = 330kHz
6
5
4
3
2
1
0
1.0
1.5
2.0
5
10
15
DVDD VOLTAGE (V)
PVDD VOLTAGE (V)
DVDD SOFTWARE SHUTDOWN CURRENT
PVDD SOFTWARE SHUTDOWN CURRENT
vs. DVDD VOLTAGE
vs. PVDD VOLTAGE
toc03
toc04
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
ZSPK = ∞
DAI PINS = GND
ZSPK = ∞
1.0
1.5
2.0
5
10
15
DVDD VOLTAGE (V)
PVDD VOLTAGE (V)
Maxim Integrated
│ 16
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Operating Characteristics (continued)
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
DVDD HARDWARE SHUTDOWN CURRENT
PVDD HARDWARE SHUTDOWN CURRENT
THD+N RATIO
vs. OUTPUT POWER
vs. DVDD VOLTAGE
vs. PVDD VOLTAGE
toc07
toc05
toc06
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.8
0.7
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
ZSPK = 8Ω + 68µH
VPVDD = 5.5V
ZSPK = ∞
ZSPK = ∞
VRST = 0V
VRST = 0V
0.6
0.5
0.4
0.3
0.2
0.1
0
6kHz
1kHz
100Hz
1
0.0001
0.001
0.01
0.1
10
1.0
1.5
2.0
5
10
15
OUTPUT POWER (W)
DVDD VOLTAGE (V)
PVDD VOLTAGE (V)
THD+N RATIO vs.
OUTPUT POWER
THD+N RATIO vs.
OUTPUT POWER
THD+N RATIO vs.
OUTPUT POWER
toc08
toc09
toc10
0
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
VPVDD = 17V
ZSPK = 4Ω + 33µH
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
VPVDD = 12V
VPVDD = 5.5V
6kHz
1kHz
6kHz
6kHz
1kHz
1kHz
100Hz
100Hz
1
100Hz
0.0001 0.001
0.01
0.1
1
10
0.0001 0.001 0.01
0.1
10
100
0.0001
0.001
0.01
0.1
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
THD+N RATIO vs.
OUTPUT POWER
vs. FREQUENCY
vs. FREQUENCY
toc11
tocꢀ3
tocꢀ2
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
0
ZSPK = 4Ω + 33µH
VPVDD = 12V
VPVDD = 5.5V
ZSPK = 8Ω + 68µH
VPVDD = 12V
Zspk = 8Ω + 68µH
-10
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
6kHz
PꢀꢁT
PꢀꢁT = 0.1W
PꢀꢁT = 1W
= 4W
1kHz
100Hz
1
POUT = 1W
100
0.0001 0.001 0.01
0.1
10
100
10
100
1000
FREQUENCY (Hz)
10000
100000
10
1000
FREQUENCY (Hz)
10000
100000
OUTPUT POWER (W)
Maxim Integrated
│ 17
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Operating Characteristics (continued)
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
vs. FREQUENCY
vs. FREQUENCY
toc16
toc15
toc14
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
0
VPVDD = 17V
VPVDD = 5.5V
ZSPK = 4Ω + 33µH
VPVDD = 12V
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
ZSPK = 8Ω + 68µH
ZSPK = 4Ω + 33µH
POUT = 0.1W
POUT = 1W
POUT = 4W
POUT = 8W
POUT = 1W
100
POUT = 1W
100
-100
10
1000
FREQUENCY (Hz)
10000
100000
10
100
1000
FREQUENCY (Hz)
10000
100000
10
1000
FREQUENCY (Hz)
10000
100000
OUTPUT POWER
vs. LOAD RESISTANCE
OUTPUT POWER
vs. LOAD RESISTANCE
OUTPUT POWER
vs. LOAD RESISTANCE
toc17
toc18
toc19
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
20
18
16
14
12
10
8
25
20
15
10
5
VPVDD = 5.5V
VPVDD = 12V
VPVDD = 17V
THD+N = 10%
THD+N = 10%
THD+N = 1%
THD+N = 1%
THD+N = 10%
THD+N = 1%
6
4
2
0
0
1
10
100
1
10
100
1
10
100
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
OUTPUT POWER vs.
PVDD SUPPLY VOLTAGE
OUTPUT POWER vs.
PVDD SUPPLY VOLTAGE
NORMALIZED GAIN
vs. FREQUENCY
toc20
toc21
toc22
25
20
15
10
5
20
18
16
14
12
10
8
0.5
0.4
0.3
0.2
0.1
0
ZSPK = 8Ω + 68µH
ZSPK = 4Ω + 33µH
NORMALIZED TO 1kHz
ZSPK = 8Ω + 68µH
10% THD+N
fS = 32kHz
fS = 96kHz
10% THD+N
1% THD+N
1% THD+N
fS = 44.1kHz
fS = 48kHz
-0.1
-0.2
-0.3
-0.4
-0.5
6
4
2
0
0
5
10
15
20
5
7
9
11
13
20
200
2000
20000
PVDD SUPPLY VOLTAGE (V)
PVDD SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
Maxim Integrated
│ 18
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Operating Characteristics (continued)
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
EFFICIENCY vs.
OUTPUT POWER
POWER DISSIPATION
vs. OUTPUT POWER
EFFICIENCY vs.
OUTPUT POWER
toc24
toc23
toc25
90
80
90
80
70
60
50
40
30
20
10
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VPVDD = 12V
VPVDD = 12V
ZSPK = 4Ω + 33μH
fSPK = 330kHz
fSPK = 472kHz
ZSPK = 4Ω + 33μH
70
60
50
40
30
20
10
0
fSPK = 472kHz
fSPK = 330kHz
fSPK = 472kHz
VPVDD = 12V
ZSPK = 4Ω + 33μH
fSPK = 330kHz
10 100
0
5
10
OUTPUT POWER (W)
15
20
20
12
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
OUTPUT POWER (W)
OUTPUT POWER (W)
POWER DISSIPATION
vs. OUTPUT POWER
EFFICIENCY vs.
OUTPUT POWER
EFFICIENCY vs.
OUTPUT POWER
toc28
toc27
toc26
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2.5
2.0
1.5
1.0
0.5
0.0
VPVDD = 17V
VPVDD = 17V
fSPK = 330kHz
ZSPK = 8Ω + 68μH
ZSPK = 8Ω + 68μH
fSPK = 472kHz
fSPK = 472kHz
fSPK = 330kHz
fSPK = 472kHz
fSPK = 330kHz
VPVDD = 17V
ZSPK = 8Ω + 68μH
0
5
10
15
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
EFFICIENCY vs.
OUTPUT POWER
EFFICIENCY vs.
OUTPUT POWER
POWER DISSIPATION
vs. OUTPUT POWER
toc30
toc29
toc31
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VPVDD = 12V
VPVDD = 12V
ZSPK = 8Ω + 68μH
fSPK = 330kHz
ZSPK = 8Ω + 68μH
fSPK = 472kHz
fSPK = 472k
fSPK = 330kHz
fSPK = 472kHz
fSPK = 330kHz
VPVDD = 12V
ZSPK = 8Ω + 68μH
0
2
4
6
8
10
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
Maxim Integrated
│ 19
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Operating Characteristics (continued)
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
PVDD POWER-SUPPLY REJECTION RATIO
DVDD POWER-SUPPLY REJECTION RATIO
POWER-SUPPLY REJECTION RATIO vs.
PVDD SUPPLY VOLTAGE
vs. FREQUENCY
vs. FREQUENCY
toc32
toc3ꢀ
toc33
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
VRIPPLE = 100mVP-P
ZSPK = ∞
VRIPPLE = 100mVP-P
fs = 1kHz
VRIPPLE = 100mVP-P
60
40
20
0
10
100
1000
FREQUENCY (Hz)
10000
100000
5
10
15
20
10
100
1000
10000
100000
PVDD SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
SOFTWARE ENABLE
TURN-ON RESPONSE
VOLUME RAMPING ENABLED
SOFTWARE ENABLE
TURN-ON RESPONSE
VOLUME RAMPING DISABLED
POWER-SUPPLY REJECTION RATIO
vs. DVDD SUPPLY VOLTAGE
toc3ꢀ
toc37
toc3ꢀ
140
120
100
80
VRIPPLE = 100mVP-P
fs=1kHz
SCL
1V/div
SCL
1V/div
60
SPKOUT
5V/div
SPKOUT
5V/div
40
20
0
4ms/div
2ms/div
1.1
1.3
1.5
1.7
1.9
DVDD SUPPLY VOLTAGE (V)
SOFTWARE DISABLE
TURN-OFF RESPONSE
VOLUME RAMPING ENABLED
SOFTWARE DISABLE
TURN-OFF RESPONSE
VOLUME RAMPING DISABLED
HARDWARE RESET
TURN-OFF RESPONSE
toc38
toc39
toc40
SCL
1V/div
SCL
1V/div
RST
1V/div
SPKOUT
5V/div
SPKOUT
5V/div
SPKOUT
5V/div
4ms/div
2ms/div
800µs/div
Maxim Integrated
│ 20
www.maximintegrated.com
MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Operating Characteristics (continued)
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
BCLK REMOVAL
TURN-OFF RESPONSE
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
toc41
toc43
tocꢀ2
40
40
20
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
20
fS = 32kHz
fS = 32kHz
BCLK
2V/div
0
0
-20
-40
-20
-40
-60
-80
-100
-120
-140
LRCLK
1V/div
-60
-80
SPKOUT
5V/div
-100
-120
-140
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
0
0
5000
10000
FREQUENCY (Hz)
15000
20000
2ms
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
toc45
toc44
toc46
40
20
40
20
40
20
ZSPK = 8Ω + 68µH
S = 32kHz
ZSPK = 8Ω + 68µH
S = 44.1kHz
ZSPK = 8Ω + 68µH
S = 44.1kHz
f
f
f
0
0
0
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
5000
10000
15000
20000
0
5000
10000
15000
20000
5000
10000
15000
20000
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
toc47
toc49
toc48
40
20
40
20
40
20
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
fS = 44.1kHz
fS = 48kHz
fS = 48kHz
0
0
0
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
0
5000
10000
15000
20000
0
5000
10000
FREQUENCY (Hz)
15000
20000
5000
10000
15000
20000
FREQUENCY (Hz)
FREQUENCY (Hz)
Maxim Integrated
│
21
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Operating Characteristics (continued)
(V
= 12V, V
= 1.8V, V
= 0V, SPK_GAIN_MAX = 0x0B (20.5dB), f
= 3.072MHz, f
= 48kHz, speaker loads
PVDD
DVDD
GND
BCLK
LRCLK
(Z
) connected between OUTP and OUTN, T = T
to T
, unless otherwise noted. Typical values are at T = +25ºC.)
SPK
A
MIN
MAX A
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
toc50
toc51
toc52
40
20
40
20
40
20
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
fS = 48kHz
fS = 88.2kHz
fS = 88.2kHz
0
0
0
-20
-40
-60
-80
-20
-40
-60
-80
-100
-120
-140
-20
-40
-60
-80
-100
-120
-140
-100
-120
-140
0
5000
10000
15000
20000
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
15000
20000
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
toc53
toc54
40
20
40
ZSPK = 8Ω + 68µH
S = 88.2kHz
ZSPK = 8Ω + 68µH
S = 96kHz
20
0
f
f
0
-20
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
-140
-140
0
5000
10000
15000
20000
0
5000
10000
15000
20000
FREQUENCY (Hz)
FREQUENCY (Hz)
INBAND OUTPUT SPECTRUM
INBAND OUTPUT SPECTRUM
toc56
toc55
40
20
40
20
ZSPK = 8Ω + 68µH
ZSPK = 8Ω + 68µH
fS = 96kHz
fS = 96kHz
0
0
-20
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
-140
-140
0
5000
10000
FREQUENCY (Hz)
15000
20000
0
5000
10000
FREQUENCY (Hz)
15000
20000
Maxim Integrated
│ 22
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Bump/Pin Configurations
TOP VIEW (BUMP SIDE DOWN)
1
3
5
6
2
4
OUTN
SNS
PVDD
PVDD
DVDD
ADDR1
SCL
A
B
OUTN
OUTN
PGND
PGND
PGND
DGND
AGND
ADDR0
DOUT
SDA
C
PGND
OUTP
LRCLK
D
OUTP
PVDD
PGND
PVDD
AGND
DIN
IRQ
OUTP
SNS
RESET
BCLK
V
E
REFC
DIGITAL
ANALOG
HIGH POWER
WLP
(2.2mm x 2.7mm)
Maxim Integrated
│ 23
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Bump/Pin Configurations (continued)
TOP VIEW
24
23
22
21
20
19
18
17
25
26
27
28
29
30
31
32
RESET
VREFC
AGND
16
15
14
13
12
11
10
9
ADDR1
DVDD
DGND
AGND
PVDD
PVDD
MAX98372
PVDD
DIGITAL
ANALOG
PVDD
PVDD
OUTPSNS
OUTP
PVDD
HIGH
POWER
*EP
OUTNSNS
1
2
3
4
5
6
7
8
TQFN
5mm x 5mm
*EP = EXPOSED PAD
Maxim Integrated
│ 24
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Bump/Pin Description
PIN
SUPPLY
RAIL
NAME
FUNCTION
TQFN
WLP
A1
9
OUTNSNS
PVDD
PVDD
—
Negative Speaker Amplifier Output Sense. If not used, connect to OUTN.
10-12,
28-30
A2, A3
E2, E3
Speaker Amplifier Power Supply. Bypass each bump pair to PGND with a 10µF
and a 0.1µF, and a single 220µF per device.
2
Digital Core, Digital Audio Interface, and I C Control Power Supply. Bypass to
DGND with a 1µF.
A4
A5
15
16
DVDD
—
2
Four-Level I C Slave Address Select Input. See the Slave Address Selection sec-
ADDR1
DVDD
tion for additional information (Table 40).
2
A6
17
SCL
DVDD
PVDD
I C Control Clock Input
B1, B2
6-8
OUTN
Negative Speaker Amplifier Output
Speaker Amplifier Ground
Digital Ground
B3,
C1–C3, D3
3-5
14
18
PGND
DGND
ADDR0
—
—
B4
B5
2
Four-Level I C Slave Address Select Input. See the Slave Address Selection sec-
tion for additional information (Table 40).
DVDD
2
B6
C4, D4
C5
19
27, 13
20
SDA
AGND
DOUT
DVDD
—
I C Control Data Input/Output
Analog Ground
DVDD
Bidirectional ICC Link Data
DAI Left/Right Clock Input. LRCLK is the audio sample rate clock and determines
whether audio data is routed to the left or right channel. In TDM mode, LRCLK is a
frame sync pulse with programmable width.
C6
D1, D2
D5
21
1-2, 32
22
LRCLK
OUTP
IRQ
DVDD
PVDD
DVDD
Positive Speaker Amplifier Output
Hardware Interrupt Output. IRQ can be programmed to pull low when individual
bits in the flag registers change value. Connect a 10kΩ pullup resistor for full
output swing.
D6
E1
E4
23
31
26
DIN
DVDD
PVDD
PVDD
DAI Audio Data Input
OUTPSNS
Positive Speaker Amplifier Output Sense. If not used, connect to OUTP.
Internal Regulator Decoupling Point. Bypass to AGND with a 1µF.
V
REFC
Active-Low Hardware Reset. Drive low to place the device into low power reset
mode and reset the device registers to their power-on-reset (POR) states.
E5
25
RESET
DVDD
E6
—
24
—
BCLK
EP
DVDD
—
DAI Bit Clock Input
Exposed Pad. Connect exposed thermal pad to AGND.
Maxim Integrated
│ 25
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
2
be read back through I C, however, accurate readings
Detailed Description
only occur after the die temperature exceeds +100°C.
The MAX98372 is a high-efficiency mono Class D audio
amplifier that features thermal foldback protection and
ADCs for sensing battery supply voltage and onboard
temperature.
2
The DAI supports I S, left-justified, and TDM formatted
data at the following sample rates: 32kHz, 44.1kHz,
48kHz, 88.2kHz, and 96kHz. Audio bit depths of 16, 24,
and 32 bits are supported for input data. The DAI operates
from BCLK to allow the device to function without MCLK.
The MAX98372 can operate over a wide range of supply
voltage (PVDD), and has extensive on-board digital signal
processing to enable dynamic headroom tracking (DHT).
This feature automatically adjusts the output signal to fit
into the available supply voltage range. The DHT can be
completely bypassed for operation with fixed, regulated
supply voltages.
Thermal foldback allows the device to smoothly attenuate
the audio output in an effort to prevent destructive thermal
behavior. Above a set threshold, the gain of the replay path
reduces at a (user programmable) dB/°C rate to a 12dB
maximum attenuation. Thermal monitoring capabilities
alert the host when die temperature has triggered the
thermal foldback circuit, or is approaching the maximum
operating temperature. If maximum die temperature is
exceeded, the device shuts down to protect itself. Short-
circuit protection ensures that accidental shorts or high-
current events do not cause damage to the IC.
The MAX98372 provides automatic level control (ALC) for
battery brownout protection. This is achieved by reducing
amplifier gain when the battery voltage drops below the
selected threshold. ALC threshold, maximum attenuation,
and attack/release rates are programmable.
Active emissions limiting edge rate and overshoot control
circuitry, together with Class D modulation, minimize the
electromagnetic interference (EMI) traditionally associated
with Class D amplifiers. In systems that use less than 18in
of speaker cable, an output filter is unnecessary to meet
standard EMI limits.
Device status is communicated to the host through a
hardware interrupt (IRQ) and status registers accessible
2
through the I C interface.
2
The MAX98372 is fully programmable through the I C
interface. ADDR0, ADDR1 connections select one of
2
sixteen I C slave addresses. Shutdown mode is directly
Two ADCs monitor PVDD supply voltage and die
temperature. The PVDD supply voltage value can be
2
controlled through the I C interface, or a hardware
shutdown can be asserted through the RESET pin.
2
read using the I C interface. The temperature ADC can
Table 1. MAX98372 Control Register Map
REGISTER DESCRIPTION
REGISTER CONTENTS
POR
STATE
ADDR
NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT1
BIT 0
INTERRUPTS
THRM
WRN_
THRM
SHDN_
STATUS
INTERRUPT
THRMFB_
STATUS
0x01
0x02
0x03
0x04
0x05
R
R
—
—
—
—
—
—
—
—
—
0x00
0x01
STATUS 0
STATUS
INVAL
SLOT_
STATUS
SPK
PVDD
OVFL_
STATUS
PVDD
UVLO_
STATUS
INTERRUPT
STATUS 1
ICCOVC_ LMTRACT_
DHTACT_
STATUS
CURNT_
STATUS
STATUS
STATUS
THRMFB_
END_
THRMFB_
BGN_
THRM
THRM
THRM
THRM
INTERRUPT
STATE 0
R
—
WRN_END WRN_BGN SHDN_END SHDN_BGN 0x00
STATE
STATE
_STATE
_STATE
_STATE
_STATE
INVAL
SLOT_
STATE
SPK
PVDD
OVFL_
STATE
PVDD
UVLO_
STATE
INTERRUPT
STATE 1
ICCOVC_ LMTRACT_
DHTACT_
STATE
R
CURNT_
STATE
0x00
0x00
STATE
STATE
THRMFB_
BGN_
THRM
THRM
THRM
THRM
INTERRUPT
FLAG 0
THRMFB_
R/W
—
WRN_END_ WRN_BGN
FLAG _FLAG
SHDN_
SHDN_
END_ FLAG
FLAG
END_ FLAG BGN_ FLAG
Maxim Integrated
│
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 1. MAX98372 Control Register Map (continued)
REGISTER DESCRIPTION
REGISTER CONTENTS
POR
STATE
ADDR
NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT1
BIT 0
INVAL
SLOT_
FLAG
SPK
CURNT_
FLAG
PVDD
OVFL_
FLAG
INTERRUPT
FLAG 1
ICCOVC_ LMTRACT_
DHTACT_
FLAG
PVDD
0x06
R/W
—
0x00
0x00
0x00
0x00
FLAG
FLAG
UVLO_ FLAG
THRMFB_
END_
EN
THRMFB_
BGN_
EN
THRM
WRN_
THRM
WRN_
THRM
SHDN_
THRM
SHDN_
INTERRUPT
ENABLES 0
0x07
0x08
0x09
R/W
R/W
W
—
—
—
—
END_ EN
BGN_ EN
END_ EN
BGN_ EN
SPK
CURNT_
EN
INTERRUPT
ENABLES 1
ICCOVC_ LMTRACT_
INVAL
DHTACT_
EN
PVDD
PVDD
EN
EN
SLOT_ EN
OVFL_ EN UVLO_ EN
THRM
WRN_
THRM
WRN_
THRM
THRM
INTERRUPT
CLEARS 0
THRMFB_
END_CLR
THRMFB_
BGN_ CLR
—
SHDN_
SHDN_
END_ CLR BGN_ CLR
END_ CLR BGN_ CLR
INTERRUPT
CLEARS 1
ICCOVC_ LMTRACT_
INVAL
DHTACT_
CLR
SPK
PVDD
PVDD
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
W
R
—
—
—
—
—
—
0x00
0x00
0x00
0x00
0x00
0x00
CLR
CLR
SLOT_ CLR
CURNT_ CLR OVFL_CLR UVLO_ CLR
ALCINFH_
STATUS
ALCACT_
STATUS
ALCMUT_
STATUS
Live Status 1
State 1
—
—
—
—
—
—
—
—
—
—
—
—
ALCINFH_
STATE
ALCACT_
STATE
ALCMUT_
STATE
R
—
—
—
—
—
—
—
—
ALCINFH_
FLAG
ALCACT_
FLAG
ALCMUT_
FLAG
Flag 1
R
ALCINFH_
EN
IRQ Enable 1
IRQ Clear 1
R/W
W
ALCACT_EN ALCMUT_EN
ALCINFH_
CLR
ALCACT_
CLR
ALCMUT_
CLR
PCM CONFIGURATION
PCM CLOCK
0x10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
BSEL[3:0]
0x02
0x08
0x80
0x00
0x00
0x00
0x00
SETUP
PCM SAMPLE
0x11
SPK_SR[3:0]
RATE SETUP
PCM MODE
0X14
CHANSZ[1:0]
FORMAT[2:0]
BCLEDGE
CHANSEL
—
CONFIG
PCM RX
0x15
RX_
RX_
RX_
RX_
RX_
RX_
RX_
RX_
ENABLES A
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
PCM RX
0x16
RX_
RX_
RX_
RX_
RX_
RX_
RX_
RX_
ENABLES B
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
MONOMIX
0x18
DMONOMIX_CH1_SOURCE[3:0]
DMONOMIX_CH0_SOURCE[3:0]
CHANNEL SOURCE
MONOMIX
0x19
—
—
—
—
—
—
DMONOMIX_CFG[1:0]
CHANNEL SOURCE
Maxim Integrated
│ 27
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 1. MAX98372 Control Register Map (continued)
REGISTER DESCRIPTION
ADDR NAME R/W
DIGITAL FILTER PARAMETERS
REGISTER CONTENTS
POR
STATE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT1
BIT 0
PVDD_FILT PVDD_FILT
_TO_LMTR _TO_DHT
0x1C
DIGITAL FILTER
R/W
PVDD_ADC_BW[1:0]
—
DACHPF[2:0]
0x00
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DAC_BQ_B0[23:16]
DAC_BQ_B0[15:8]
DAC_BQ_B0[7:0]
DAC_BQ_B1[23:16]
DAC_BQ_B1[15:8]
DAC_BQ_B1[7:0]
DAC_BQ_B2[23:16]
DAC_BQ_B2[15:8]
DAC_BQ_B2[7:0]
DAC_BQ_A0[23:16]
DAC_BQ_A0[15:8]
DAC_BQ_A0[7:0]
DAC_BQ_A1[23:16]
DAC_BQ_A1[15:8]
DAC_BQ_A1[7:0]
0x10
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
DAC BQ B0
DAC BQ B1
DAC BQ B2
DAC BQ A0
DAC BQ A1
DIGITAL VOLUME
CONTROL
DVOL_
0x2D
0x2E
R/W
R/W
DVOL[6:0]
0x00
0x0B
RAMP_BYP
PATH GAIN
DPGA_CLIP[3:0]
SPK_GAIN_MAX[3:0]
DHT_VROT_PNT[3:0]
DYNAMIC GAIN PARAMETERS
DHT ROTATION
0x31
R/W
SPK_GAIN_MIN[3:0]
0x00
POINT
0x32
0x33
DHT ATTACK
DHT RELEASE
R/W
R/W
—
—
—
—
—
—
DHT_ATK_STEP[1:0]
DHT_REL_STEP[1:0]
DHT_ATK_RATE[2:0]
DHT_REL_RATE[2:0]
0x18
0x00
PVDD ADC
0x34
0x36
0x37
R
R/W
R
PVDD_ADC[7:0]
0x00
0xC0
0x00
MEASUREMENT
THERMAL
THRM_HOLD[1:0]
—
—
THRM_REL[1:0]
THRM_SLOPE[1:0]
FOLDBACK
THERMAL ADC
MEASUREMENT
—
—
—
—
THRM_ADC_MEAS[5:0]
THRM_MIN_TEMP[5:0]
THERMAL
FOLDBACK MIN
TEMP
0x38
0x39
R/W
R/W
0x00
0x03
THERMAL
FOLDBACK LOW
PASS FILTER
—
—
—
—
—
THRM_FILT_SEL[2:0]
Maxim Integrated
│ 28
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 1. MAX98372 Control Register Map (continued)
REGISTER DESCRIPTION
REGISTER CONTENTS
POR
STATE
ADDR
NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT1
BIT 0
PCM2 RXDHT
ENABLES A
RXDHT_
CH7_EN
RXDHT_
CH6_EN
RXDHT_
CH5_EN
RXDHT_
CH4_EN
RXDHT_
CH3_EN
RXDHT_
CH2_EN
RXDHT_
CH1_EN
RXDHT_
CH0_EN
0x3A
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PCM2 RXDHT
ENABLES B
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
RXDHT_
CH9_EN
RXDHT_
CH8_EN
0x3B
0x3C
0x3D
0x3E
0x3F
R/W
R/W
R/W
R/W
R/W
R/W
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
PCM2 RXTHM
ENABLES A
RXTHM_
CH7_EN
RXTHM_
CH6_EN
RXTHM_
CH5_EN
RXTHM_
CH4_EN
RXTHM_
CH3_EN
RXTHM_
CH2_EN
RXTHM_
CH1_EN
RXTHM_
CH0_EN
PCM2 RXTHM
ENABLES B
RXTHM_
CH15_EN
RXTHM_
CH14_EN
RXTHM_
CH13_EN
RXTHM_
CH12_EN
RXTHM_
CH11_EN
RXTHM_
CH10_EN
RXTHM_
CH9_EN
RXTHM_
CH8_EN
PCM2 TX \
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
ENABLES A
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
PCM2 TX
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
ENABLES A
CH15_EN
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
PCM2 DATA
DRIVE_
MODE
—
—
—
—
—
—
—
—
—
—
—
—
—
0x40
0x41
ORDER SELECT
TX_
EXTRA_
HIZ
PCM2 HiZ
R/W
—
0x00
MANUAL MODE
PCM2 TX HiZ
ENABLES A
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
0x42
0x43
R/W
R/W
0x00
0x00
CH7_HIZ
CH6_HIZ
CH5_HIZ
CH4_HIZ
CH3_HIZ
CH2_HIZ
CH1_HIZ
CH0_HIZ
PCM2 TX HiZ
ENABLES B
TX_
TX_
TX_
TX_
TX_
TX_
TX_
TX_
CH15_HIZ
CH14_HIZ
CH13_HIZ
CH12_HIZ
CH11_HIZ
CH10_HIZ
CH9_HIZ
CH8_HIZ
ENABLES
0x49
SSM_CFG
R/W
R/W
R/W
R/W
—
—
—
—
—
—
—
—
SSM_MODINDEX[2:0]
0x01
0x00
0x00
0x00
SPEAKER
ENABLE
SPK_
0x4A
SPK_SSM[1:0]
SPK_EDGE[1:0]
—
SPK_EN
SWCLK
DYNAMIC GAIN
ENABLES
0x4B
0x4C
—
—
—
—
—
—
—
—
PVADC_EN LMTR_EN
DHT_EN
THERMAL
THERM_
FB_EN
—
—
FOLDBACK ENABLE
CMON_
AUTO_
TSHDN_
AUTO_
CMON_
ENA
OVC_
SEL
0x4D RESTART BEHAVIOR R/W
—
—
—
—
—
—
—
—
0x00
0x00
RESTART
RESTART
ALC_LINK_
EN
THM_
DHT_
0x4E
ICC LINK ENABLE R/W
GLOBAL ENABLE R/W
—
LINK_EN
LINK_EN
0x50
0x51
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EN
0x00
0x00
SOFTWARE RESET
W
RST
LIMITER ATTACK
AND RELEASE
0x55
R/W
—
—
LMTR_REL_RATE[2:0]
LMTR_ATK_RATE[2:0]
0x30
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 1. MAX98372 Control Register Map (continued)
REGISTER DESCRIPTION
REGISTER CONTENTS
POR
STATE
ADDR
NAME
R/W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT1
BIT 0
Digital Filter Dither
Enable
AUTO_
DFILT_
R/W
—
—
—
—
—
—
0x03
0x00
0x00
0x00
0x57
DITHER_EN DITH_EN
LIMITER
THRESHOLD
SELECT
0x58
0x59
0x5C
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
—
LMTR_TH_SEL[1:0]
LIMITER MANUAL
THRESHOLD
LMTR_THC[4:0]
ICC_
DOUTEN_
EXTFF
ICC_
ICC PAD
ICC_OC_
ENA
DOUT_
EXTFF
ICC_PAD_CTRL[3:0]
CONTROL
PCM2 RXALC
Enables A
PCM2_RXAL_ PCM2_RXAL_ PCM2_RXAL_ PCM2_RXALC_ PCM2_RXALC_ PCM2_RXAL_ PCM2_RXAL_ PCM2_RXAL_
0x60
0x61
R/W
R/W
0x00
0x00
CH7_EN
CH6_EN
CH5_EN
CH4_EN
CH3_EN
CH2_EN
CH1_EN
CH0_EN
PCM2 RXALC
Enables B
PCM2_RXAL_ PCM2_RXAL_ PCM2_RXAL_ PCM2_RXALC_ PCM2_RXALC_ PCM2_RXAL_ PCM2_RXAL_ PCM2_RXAL_
CH15_EN
—
CH14_EN
CH13_EN
CH12_EN
CH11_EN
CH10_EN
CH9_EN
CH8_EN
0x62
0x63
THRESHOLD
ALC ATTACK
R/W
R/W
ALC_RANGE ALC_EN
ALC_ATK_STEP[3:0]
ALC_MAX_ATTEN[3:0]
ALC_TH[4:0]
0x06
0x00
0x80
—
—
ALC_ATK_RATE[2:0]
ALC_RLS_RATE[2:0]
0x64 ALC ATTEN and RLS R/W
ALC INFINITE HOLD
ALC_RLS_
TGR
0x65
R/W
ALC_RLS_CFG[1:0]
—
—
—
—
—
—
0x00
RELEASE
ALC
ALC_MUTE_
0x66
0xFF
R/W
R
ALC_MUTE_DLY[2:0]
ALC_RLS_DBT[2:0]
0x92
0x41
CONFIGURATION
EN
REV ID
REVID[7:0]
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Flag
Interrupts
Each interrupt source has a FLAG bit to indicate that a ris-
ing edge has occurred on the associated STATUS bit and
the associated ENABLE bit is set. This bit is read only.
The MAX98372 supports programmable interrupts for
sending feedback to the host about events that have
occurred on-chip. Table 2 lists the available interrupt
sources. Interrupts are output on IRQ, an active-low open-
drain output.
Enable
Each interrupt source has an ENABLE bit to indicate that
the associated FLAG bit is set whenever the STATE bit is
set. This bit is read/write.
Status
Each interrupt source has 1 bit to indicate the real-time
STATUS of the source. This bit is read only.
Clear
State
Each interrupt has a CLEAR bit that clears the associated
STATE and FLAG bits when a 1 is written. Writing a 0 has
no effect. This bit is write only.
Each interrupt source has a STATE bit that is set when-
ever a rising edge occurs on the associated STATUS bit
regardless of the state of the associated ENABLE bit. This
bit is read only.
Table 2. Interrupt Sources
NAME
DESCRIPTION
Overtemperature Begin Event
Overtemperature End Event
Thermal Warning Begin Event
Thermal Warning End Event
Speaker Current Event
Indicates when the die overtemperature threshold has been exceeded.
Indicates when the die overtemperature threshold is no longer exceeded including 20°C of
hysteresis.
Indicates when the thermal warning threshold has been exceeded.
Indicates that the die temperature was previously above the thermal warning threshold and has
now dropped below the threshold.
Indicates when the speaker amplifier current limit has been exceeded.
Indicates that a slot has been selected that is not available due to one or more of the following
reasons:
Invalid Slot Event
The (number of bits per channel) x (channels per frame) does not allow for the selected slot
(I S mode only).
2
The number of BCLK cycles per frame does not allow for the selected slot (TDM mode only).
Indicates that the thermal foldback limiter is operating in the attack or release phase.
Thermal Foldback Event
Indicates that the die temperature was previously above the thermal threshold and has now
dropped below the threshold.
Thermal Foldback End Event
V
Overflow Event
Indicates that the V
supply voltage has reached the V
ADC’s maximum input level.
PVDD
PVDD
PVDD
PVDD UVLO Event
DHT Active Event
Limiter Active Event
Indicates that PVDD has dropped below the minimum allowed voltage.
Indicates that the DHT circuit is applying compression to the signal.
Indicates that the limiter circuit is applying a hard limit (infinite compression) to the signal.
Indicates that an overcurrent event is in progress on DOUT.
Indicates that ALC is operating in attack, hold, or release phase.
Indicates that ALC has entered Mute.
ICC Overcurrent Event
ALC Active Event
ALC Mute Event
ALC Infinite Hold Event
Indicates that the ALC has entered infinite hold mode.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers
Interrupt Status 0
Interrupt Status bits reflect real-time fault conditions. If the fault condition is less than 3-4 LRCLK cycles, the Live Status bit holds
high for 3–4 LRCLK cycles.
ADDRESS
BIT
7
NAME
DESCRIPTION
0
0
Unused: Read back is 0.
Unused: Read back is 0.
6
Die Thermal Foldback Status
0: The die temperature is below the thermal warning threshold.
1: The die temperature is above the thermal warning threshold and the
signal is being dynamically attenuated.
5
THERMFB_STATUS
4
3
2
1
0
0
Unused: Read back is 0.
0x01
Die Overtemperature Warning Status
0: The die temperature is below the thermal warning threshold.
1: The die temperature is above the thermal warning threshold.
THERMWRN_STATUS
0
Unused: Read back is 0.
Die Overtemperature Status
0: The die temperature is below the maximum die temperature.
1: The die temperature exceeds the maximum die temperature.
THERMSHDN_STATUS
0
Unused: Read back is 0.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Status 1
Interrupt Status bits reflect real-time fault conditions. If the fault condition is less than 3–4 LRCLK cycles, the Live Status bit holds
high for 3–4 LRCLK cycles.
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back is 0.
ICC Overcurrent Status
6
5
ICCOVC_STATUS
0: No overcurrent event on the DOUT is in progress.
1: Overcurrent event on the DOUT is in progress.
Limiter Active Status
0: Limiter is not active.
1: Limiter is active.
LMTRACT_STATUS
Invalid Slot Status
0: Slot is valid.
1: Slot is invalid, one or more possible error conditions apply:
a. The (number of bits per channel) * (channels per frame)
does not allow for the selected slot. (I2S mode only)
b. The number of BCLK cycles per frame does not allow for the
selected slot.(TDM mode only).
4
INVALSLOT_STATUS
0x02
DHT Active Status
3
2
DHTACT_STATUS
0: Dynamic Headroom Tracking is not attacking or releasing.
1: Dynamic Headroom Tracking is active and is attacking or releasing.
Speaker Overcurrent Status
0: Speaker current is below the current limit.
1: Speaker current is above the current limit.
SPKCURNT_STATUS
PVDD Supply Voltage Monitor Overflow Status
0: The PVDD supply voltage is below the PVDD ADC’s maximum
input level.
1: The PVDD supply voltage has exceeded the PVDD ADC’s
maximum input level
1
0
PVDDOVFL_STATUS
PVDDUVLO_STATUS
PVDD Supply Voltage Undervoltage Status
0: The PVDD supply voltage is above the PVDD UVLO level.
1: The PVDD supply voltage is below the PVDD UVLO
threshold, and the part is shutdown.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 3. Interrupt Registers (continued)
Interrupt State 0
ADDRESS
BIT
7
NAME
DESCRIPTION
0
0
Unused: Read back is 0.
6
Unused: Read back is 0.
Die Thermal Foldback State End Event
0: No falling edge on thermal foldback status is detected.
1: A falling edge on thermal foldback status is detected.
Note: Write a 1 to THERMFB_END_CLR to reset.
5
4
3
2
1
0
THERMFB_END_STATE
THERMFB_BGN_STATE
THERMWRN_END_STATE
THERMWRN_BGN_STATE
THERMSHDN_END_STATE
THERMSHDN_BGN_STATE
Die Thermal Foldback State End Event
0: No rising edge on thermal foldback status is detected.
1: A rising edge on thermal foldback status is detected.
Note: Write a 1 to THERMFB_BGN_CLR to reset.
Thermal Warning Status End Event
0: No falling edge on THERMWRN_STATUS is detected.
1: A falling edge on THERMWRN_STATUS is detected.
Note: Write a 1 to THERMWRN_END_CLR to reset.
0x03
Thermal Warning Status Begin Event
0: No rising edge on THERMWRN_ STATUS is detected.
1: A rising edge on THERMWRN_STATUS is detected.
Note: Write a 1 to THERMWRN_BGN_CLR to reset.
Thermal Shutdown End Event
0: No falling edge on THERMSHDN_STATUS is detected.
1: A falling edge on THERMSHDN_STATUS is detected.
Note: Write a 1 to THERMSHDN_END_CLR to reset.
Thermal Shutdown Begin Event
0: No rising edge on THERMSHDN_STATUS is detected.
1: A rising edge on THERMSHDN_STATUS is detected.
Note: Write a 1 to THERMSHDN_BGN_CLR to reset.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt State 1
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back is 0.
ICC Overcurrent Event
0: No rising edge on ICCOVC_STATUS is detected.
1: A rising edge on ICCOVC_STATUS is detected.
Note: Write a 1 to ICCOVC_CLR to reset.
6
5
4
3
2
ICCOVC_STATE
LMTRACT_STATE
INVALSLOT_STATE
DHTACT_STATE
Limiter Active Event
0: No rising edge on LMTRACT_STATUS is detected.
1: A rising edge on LMTRACT_STATUS is detected.
Note: Write a 1 to LMTRACT_CLR to reset.
Invalid Slot Event
0: No rising edge on INVALSLOT_STATUS is detected.
1: A rising edge on INVALSLOT_STATUS is detected.
Note: Write a 1 to INVALSLOT_CLR to reset.
DHT Active Event
0x04
0: No rising edge on DHTACT_STATUS is detected.
1: A rising edge on DHTACT_STATUS is detected.
Note: Write a 1 to DHTACT_STATUS to reset.
Speaker Overcurrent Event
0: No rising edge on SPKCURNT_STATUS is detected.
1: A rising edge on SPKCURNT_STATUS is detected.
Note: Write a 1 to SPKCURNT_CLR to reset.
SPKCURNT_STATE
PVDD ADC Overflow Event
0: No rising edge on PVDDOVFL_STATUS is detected.
1: A rising edge on PVDDOVFL_STATUS is detected.
Note: Write a 1 to PVDDOVFL_CLR to reset.
1
0
PVDDOVFL_STATE
PVDDUVLO_STATE
PVDD Supply Voltage Undervoltage Lockout Event
0: No rising edge on PVDDUVLO_STATUS is detected.
1: A rising edge on PVDDUVLO_STATUS is detected.
Note: Write a 1 to PVDDOVFL_CLR to reset.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Flag 0
ADDRESS
BIT
7
NAME
DESCRIPTION
0
0
Unused: Read back is 0.
6
Unused: Read back is 0.
Die Thermal Foldback End Flag
5
4
3
2
1
0
THERMFB_END_FLAG
THERMFB_BGN_FLAG
THERMWRN_END_FLAG
THERMWRN_BGN_FLAG
THERMSHDN_END_FLAG
THERMSHDN_BGN_FLAG
0: No thermal foldback end interrupt is generated.
1: Thermal foldback end interrupt is generated.
Die Thermal Foldback Begin Flag
0: No thermal foldback begin interrupt is generated.
1: Thermal foldback begin interrupt is generated.
Thermal Warning End Flag
0: No thermal warning end is interrupt generated.
1: Thermal warning end interrupt is generated.
0x05
Thermal Warning Begin Flag
0: No thermal warning begin interrupt is generated.
1: Thermal warning begin interrupt is generated.
Thermal Shutdown End Flag
0: No thermal shutdown end interrupt is generated.
1: Thermal shutdown end interrupt is generated.
Thermal Shutdown Begin Flag
0: No thermal shutdown begin interrupt is generated.
1: Thermal shutdown begin interrupt is generated.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Flag 1
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back 0.
ICC Overcurrent Flag
6
5
4
3
2
1
0
ICCOVC_FLAG
LMTRACT_FLAG
INVALSLOT_FLAG
DHTACT_FLAG
0: No ICC overcurrent interrupt is generated.
1: ICC overcurrent interrupt is generated.
Limiter Active Flag
0: No limiter active interrupt is generated.
1: Limiter active interrupt is generated.
Invalid Slot Flag
0: No invalid slot interrupt is generated.
1: Invalid slot interrupt is generated.
DHT Active Flag
0: No dynamic headroom tracking active slot interrupt is generated.
1: dynamic headroom tracking active slot interrupt is generated.
0x06
Speaker Overcurrent Flag
0: No speaker overcurrent interrupt is generated.
1: Speaker overcurrent interrupt is generated.
SPKCURNT_FLAG
PVDDOVFL_FLAG
PVDDUVLO_FLAG
PVDD ADC Overflow Flag
0: No PVDD ADC overflow interrupt is generated.
1: PVDD ADC overflow interrupt is generated.
PVDD Supply Voltage Undervoltage Lockout Flag
0: No PVDD UVLO Interrupt is generated.
1: PVDD UVLO Interrupt is generated.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Enable 0
ADDRESS
BIT
7
NAME
DESCRIPTION
0
0
Unused: Read back is 0.
6
Unused: Read back is 0.
Die Thermal Foldback End Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMFB_END_FLAG
transitions from 0 to 1.
5
4
3
2
1
0
THERMFB_END_EN
THERMFB_BGN_EN
Die Thermal Foldback Begin Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMFB_END_FLAG
transitions from 0 to 1.
Thermal Warning End Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMWRN_END_
FLAG transitions from 0 to 1.
THERMWRN_END_ EN
THERMWRN_BGN_ EN
THERMSHDN_END_ EN
THERMSHDN_BGN_ EN
0x07
Thermal Warning Begin Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMWRN_BGN_
FLAG transitions from 0 to 1.
Thermal Shutdown End Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMSHDN_END_
FLAG transitions from 0 to 1.
Thermal Shutdown Begin Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when THERMSHDN_BGN_
FLAG transitions from 0 to 1.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Enable 1
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back is 0.
ICC Overcurrent Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when ICCOVC_FLAG
transitions from 0 to 1.
6
5
4
3
2
1
0
ICCOVC_EN
LMTRACT_EN
INVALSLOT_EN
DHTACT_EN
Limiter Active Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when LMTRACT_FLAG
transitions from 0 to 1.
Invalid Slot Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt enabled. IRQ is pulled low when INVALSLOT_FLAG
transitions from 0 to 1.
DHT Active Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when DHTACT_FLAG
transitions from 0 to 1.
0x08
Speaker Overcurrent Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when SPKCURNT_FLAG
transitions from 0 to 1.
SPKCURNT_EN
PVDDOVFL_EN
PVDDUVLO_EN
PVDD ADC Overflow Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when PVDDOVFL_FLAG
transitions from 0 to 1.
PVDD Supply Voltage Undervoltage Lockout Interrupt Enable
0: Interrupt is disabled (default).
1: Interrupt is enabled. IRQ is pulled low when PVDDUVLO_FLAG
transitions from 0 to 1.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Clear 0
ADDRESS
BIT
7
NAME
DESCRIPTION
0
0
Unused: Read back is 0.
6
Unused: Read back is 0.
Die Thermal Foldback End Interrupt Clear
0: No effect.
1: Clears the THERMFB_END_STATE and THERMFB_END_FLAG.
5
4
THERMFB_END_CLR
THERMFB_BGN_CLR
Die Thermal Foldback Begin Interrupt Clear
0: No effect.
1: Clears the THERMFB_BGN_STATE and THERMFB_BGN_FLAG.
Thermal Warning End Interrupt Clear
0: No effect.
1: Clears the THERMWRN_END_STATE and THERMWRN_END_FLAG.
3
2
THERMWRN_END_CLR
THERMWRN_BGN_CLR
0x09
Thermal Warning Begin Interrupt Clear
0: No effect.
1: Clears the THERMWRN_BGN_STATE and THERMWRN_BGN_FLAG.
Thermal Shutdown End Interrupt Clear
0: No effect.
1: Clears the THERMSHDN_END_STATE and THERMSHDN_END_FLAG.
1
0
THERMSHDN_END_CLR
THERMSHDN_BGN_CLR
Thermal Shutdown Begin Interrupt Clear
0: No effect.
1: Clears the THERMSHDN_BGN_STATE and THERMSHDN_BGN_FLAG.
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MAX98372
Digital Input Class D Amplifier
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Table 3. Interrupt Registers (continued)
Interrupt Clear 1
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back is 0.
ICC Overcurrent Clear
6
5
4
3
2
1
0
ICCOVC_CLR
LMTRACT_CLR
INVALSLOT_CLR
DHTACT_CLR
0: No effect.
1: Clears the ICCOVC_STATE and ICCOVC_FLAG.
Limiter Active Interrupt Clear
0: No effect.
1: Clears the LMTRACT_STATE and LMTRACT_FLAG.
Invalid Slot Interrupt Clear
0: No effect.
1: Clears the INVALSLOT_STATE and INVALSLOT_FLAG.
DHT Active Interrupt Clear
0: No effect.
1: Clears the DHTACT_STATE and DHTACT_FLAG.
0x0A
Speaker Overcurrent Interrupt Clear
0: No effect.
1: Clears the SPKCURNT_STATE and SPKCURNT_FLAG.
SPKCURNT_CLR
PVDDOVFL_CLR
PVDDUVLO_CLR
PVDD ADC Overflow Interrupt Clear
0: No effect.
1: Clears the PVDDOVFL_STATE and PVDDOVFL_FLAG.
PVDD Supply Voltage Undervoltage Lockout Interrupt Clear
0: No effect.
1: Clears the PVDDUVLO_STATE and PVDDUVLO_FLAG.
Live Status 1
ADDRESS
BIT
7
NAME
DESCRIPTION
Unused: Read back 0.
0
0
0
0
6
Unused: Read back 0.
5
Unused: Read back 0.
4
Unused: Read back 0.
ALC Infinite Hold Event
3
2
ALCINFH_STATUS
ALCACT_STATUS
0: ALC is not in infinite hold state
1: ALC is in infinite hold state
0x0B
ALC Active Status
0: ALC is not reducing the gain of the PGA
1: ALC is reducing the gain of the PGA due to low battery event
ALC Mute Status
1
0
ALCMUT_STATUS
0
0: ALC has not muted the audio path
1: ALC has muted the audio path
Unused: Read back 0.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 3. Interrupt Registers (continued)
State 1
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back is 0.
6
5
4
0
0
0
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
ALC Infinite Hold Event
3
2
ALCINFH_STATE
ALCACT_STATE
0: No rising edge on ALCINFH_STATUS is detected.
1: A rising edge on ALCINFH_STATUS is detected.
0x0C
ALC Activated Event
0: No rising edge on ALCACT_STATUS is detected.
1: A rising edge on ALCACT_STATUS is detected.
ALC Mute Event
1
0
ALCMUT_STATE
0
0: No rising edge on ALCMUT_STATUS is detected.
1: A rising edge on ALCMUT_STATUS is detected.
Unused: Read back is 0.
Flag 1
ADDRESS
BIT
7
NAME
DESCRIPTION
Unused: Read back is 0.
0
0
0
0
6
Unused: Read back is 0.
5
Unused: Read back is 0.
4
Unused: Read back is 0.
ALC Infinite Hold Flag
0: No interrupt generated.
1: Interrupt generated.
ALC Activated Flag
0: No interrupt generated.
1: Interrupt generated.
ALC Mute Flag
3
2
ALCINFH_FLAG
ALCACT_FLAG
0x0D
1
0
ALCMUT_FLAG
0
0: No interrupt generated.
1: Interrupt generated.
Unused: Read back is 0.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 3. Interrupt Registers (continued)
IRQ Enable 1
ADDRESS
BIT
NAME
DESCRIPTION
7
6
5
4
0
0
0
0
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
ALC Infinite Hold Interrupt Enable
0: Interrupt disabled (default)
1: Interrupt enabled. IRQ is pulled low when ALCINFH transitions from
0 to 1.
3
2
1
ALCINFH_EN
ALCACT_EN
ALCMUT_EN
0x0E
ALC Activated Interrupt Enable
0: Interrupt disabled (default)
1: Interrupt enabled. IRQ is pulled low when ALCACT transitions from
0 to 1.
ALC Mute Interrupt Enable
0: No interrupt generated (default)
1: Interrupt enabled. IRQ is pulled low when ALCMUT transitions from
0 to 1.
0
0
Unused: Read back is 0.
IRQ Clear 1
ADDRESS
BIT
NAME
DESCRIPTION
7
6
5
4
0
0
0
0
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Clear ALC Infinite Hold Interrupt
0: No effect
1: Clears ALCFINH_STATE and ALCINFH_FLAG
3
2
ALCINFH_CLR
ALCACT_CLR
0x0F
Clear ALC Activated Interrupt
0: No effect
1: Clears ALCACT_STATE and ALCACT_FLAG
Clear ALC Mute Interrupt
0: No effect
1: Clears ALCMUT_STATE and ALCMUT_FLAG
1
0
ALCMUT_CLR
0
Unused: Read back is 0.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Operating in slave mode only, the MAX98372 eliminates
the need for the external MCLK signal that is typically
used in I S applications by generating MCLK internally.
This reduces EMI and improves the RF immunity of the
IC. Table 5 lists the supported BCLK frequencies when
operating in this mode.
Digital Audio Interface
The digital audio interface (DAI) is highly flexible,
supporting common sample rates (Table 4) with 16/24/
2
2
32-bit depth for I S/left-justified data as well as up to 16
slots in a time division multiplexed (TDM) format.
Table 4. Supported Sample Rates
ADDRESS
BIT
NAME
DESCRIPTION
Speaker Path Sample Rate Select
0000–0101: Reserved
0110: 32kHz
0111: 44.1kHz
1000: 48kHz (default)
1001: Reserved
1010: 88.2kHz
1011: 96kHz
1100–1111: Reserved
3
2
1
0
0x11
SPK_SR[3:0]
Table 5. Supported BCLK Rates in Slave Mode
ADDRESS
BIT
NAME
DESCRIPTION
Selects the Number of BCLKs/LRCLK
0000: Not supported
0001: Not supported
0010: 32 BCLKs (default)
0011: 48 BCLKs
0100: 64 BCLKs
0101: 96 BCLKs
0110: 128 BCLKs
3
2
1
0x10
BSEL[3:0]
0111: 192 BCLKs
1000: 256 BCLKs
1001: 384 BCLKs
1010: 512 BCLKs
0
1011–1111: Not supported
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
TDM mode (Figure 7) uses a frame sync pulse instead
of a 50% duty cycle frame clock. The frame sync pulse
(applied to the LRCLK pin) is equal to one BCLK period
as a minimum, although the interface operates with longer
periods; the rising edge of LRCLK is used to indicate
the start of a new frame. The falling edge can occur at
any time as long as it does not violate the setup time
requirements of the LRCLK rising edge. In TDM, latch the
MSB of the first audio word on the first or second active
BCLK edge after an LRCLK rising edge.
Interface Format
2
The MAX98372 supports standard I S, left-justified, and
TDM data formats. I S and left-justified formats support
two audio channels of 16-, 24- or 32-bit depth. TDM
supports up to 16 audio channels of 16-, 24-, or 32-bit
depth. The IC supports slave operation only, and the
LRCLK and BCLK pins operate as inputs.
2
2
I S (Figure 5) and left-justified (Figure 6) modes configure
the LRCLK signal to transition before each channel. With
2
the default I S settings LRCLK low indicates left channel
Configuring the DAI Format
while LRCLK high indicates the right channel. The MSB
of the audio word is latched on the second active BCLK
edge after an LRCLK transition. In left-justified mode, the
MSB of the audio word is latched on the first active BCLK
edge after an LRCLK transition.
Specify the format by configuring the LRCLK invert, BCLK
active edge, data delay, and TDM mode configuration bits
(Table 6).
Table 6. Configuration for Digital Audio Interface Format
ADDRESS
BIT
NAME
DESCRIPTION
Configures Channel Word Length
7
CHANSZ[1:0]
00: 8 bits
01: 16 bits
10: 24 bits (default)
11: 32 bits
6
5
PCM Format Select
000: I S mode (default)
001: Left-justified
2
4
3
FORMAT[2:0]
BCLEDGE
010: Right-justified
011: TDM mode 1
100: TDM mode 2
101–111: Reserved
0x14
Active BCLK Edge Select
0: Data captured and valid on rising edge of BCLK (default)
1: Data captured and valid on the falling edge of BCLK
2
Non-TDM LRCLK Starting Edge
0: Falling LRCLK indicates the start of a stereo pair. Channel 0 when
LRCLK is low, channel 1 when LRCLK is high. (default)
1: Rising LRCLK indicates the start of a stereo pair. Channel 0 when
LRCLK is high, channel 1 when LRCLK is low.
1
0
CHANSEL
0
Unused: Read back is 0.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Route mono data directly to the speaker amplifier. If the
input is stereo, input the right channel to the device and
mix with the left channel if desired. Sum left and right
channels with the amplitude divided by 2 to reduce the
DAC input and avoid saturation. Stereo summing and L or
R choices are limited to 2 adjacent slots on the TDM bus.
Configuring the Digital Audio Input
The DAI may be configured to accept a mono PCM input,
placed from anywhere from slots 1 to 16 of digital audio in
2
TDM mode. In I S and left-justified modes, two channels
are available.
Table 7. PCM Receive Channel Enables
ADDRESS
BIT
NAME
DESCRIPTION
Receive Channel Enable
7
RX_CH7_EN
0: Receive channel 7 is disabled.
1: Receive channel 7 is enabled.
Receive Channel Enable
6
5
4
3
2
1
0
RX_CH6_EN
RX_CH5_EN
RX_CH4_EN
RX_CH3_EN
RX_CH2_EN
RX_CH1_EN
RX_CH0_EN
0: Receive channel 6 is disabled.
1: Receive channel 6 is enabled.
Receive Channel Enable
0: Receive channel 5 is disabled.
1: Receive channel 5 is enabled.
Receive Channel Enable
0: Receive channel 4 is disabled.
1: Receive channel 4 is enabled.
0x15
Receive Channel Enable
0: Receive channel 3 is disabled.
1: Receive channel 3 is enabled.
Receive Channel Enable
0: Receive channel 2 is disabled.
1: Receive channel 2 is enabled.
Receive Channel Enable
0: Receive channel 1 is disabled.
1: Receive channel 1 is enabled.
Receive Channel Enable
0: Receive channel 0 is disabled.
1: Receive channel 0 is enabled.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 7. PCM Receive Channel Enables (continued)
ADDRESS
BIT
NAME
DESCRIPTION
Receive Channel Enable
7
RX_CH15_EN
0: Receive channel 15 is disabled.
1: Receive channel 15 is enabled.
Receive Channel Enable
6
5
4
3
2
1
0
RX_CH14_EN
RX_CH13_EN
RX_CH12_EN
RX_CH11_EN
RX_CH10_EN
RX_CH9_EN
RX_CH8_EN
0: Receive channel 14 is disabled.
1: Receive channel 14 is enabled.
Receive Channel Enable
0: Receive channel 13 is disabled.
1: Receive channel 13 is enabled.
Receive Channel Enable
0: Receive channel 12 is disabled.
1: Receive channel 12 is enabled.
0x16
Receive Channel Enable
0: Receive channel 11 is disabled.
1: Receive channel 11 is enabled.
Receive Channel Enable
0: Receive channel 10 is disabled.
1: Receive channel 10 is enabled.
Receive Channel Enable
0: Receive channel 9 is disabled.
1: Receive channel 9 is enabled.
Receive Channel Enable
0: Receive channel 8 is disabled.
1: Receive channel 8 is enabled.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 8. TDM Channel Selection for Mono Replay
ADDRESS
BIT
NAME
DESCRIPTION
Digital Monomix Source Selection
7
0000: Channel 1 gets PCM RX channel 0.
0001: Channel 1 gets PCM RX channel 1.
0010: Channel 1 gets PCM RX channel 2.
0011: Channel 1 gets PCM RX channel 3.
…
6
5
4
3
2
1
0
DMONOMIX_CH1_SOURCE[3:0]
1111: Channel 1 gets PCM RX channel 15.
0x18
Digital Monomix Source Selection
0000: Channel 0 gets PCM RX channel 0.
0001: Channel 0 gets PCM RX channel 1.
0010: Channel 0 gets PCM RX channel 2.
0011: Channel 0 gets PCM RX channel 3.
…
DMONOMIX_CH0_SOURCE[3:0]
1111: Channel 0 gets PCM RX channel 15.
Monomix Configuration
1
0
00: Output of Monomix is channel 0.
01: Output of Monomix is channel 1.
10: Output of Monomix is (channel 0 + channel 1)/2.
11: Reserved
0x19
DMONOMIX_CFG[1:0]
2
Figure 5. I S Digital Audio Format Examples
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Figure 6. Left-Justified Digital Audio Format Examples
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
TDM MODE 1, 16 32-BIT CHANNELS LATCHED ON FALLING EDGE OF BCLK, PCM_BCLEDGE = 1,
PCM_FORMAT = 011
LRCLK
HI-Z
HI-Z
D31
D31
D30
D30
D1 D0 D31 D30
DOUT
BCLK
DIN
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D1 D0
D1 D0 D31 D30
TDM MODE 1, 16 32-BIT CHANNELS LATCHED ON RISING EDGE OF BCLK, PCM_BCLEDGE = 0,
PCM_FORMAT = 011
LRCLK
DOUT
BCLK
DIN
HI-Z
HI-Z
D31
D30
D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D31
D1 D0 D31 D30
D1 D0
TDM MODE 2, 16 32-BIT CHANNELS LATCHED ON FALLING EDGE OF BCLK, PCM_BCLEDGE = 1,
PCM_FORMAT = 100
LRCLK
HI-Z
HI-Z
DOUT
BCLK
DIN
D31
D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D31 D30
D1 D0 D31 D30
D1 D0
TDM MODE 2, 16 32-BIT CHANNELS LATCHED ON RISING EDGE OF BCLK, PCM_BCLEDGE = 0,
PCM_FORMAT = 100
LRCLK
HI-Z
HI-Z
D31
D30
D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0 D31 D30
D1 D0
D1 D0
DOUT
BCLK
D31
DIN
Figure 7. TDM Digital Audio Format Examples
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
through the biquad filter coefficients by setting the
Digital Passband Filtering
DACHPF[2:0] bits to 111. See the Biquad Filter section.
The MAX98372 features an optional highpass filter with
selectable corner frequency (50Hz, 100Hz, 200Hz, 400Hz,
and 800Hz), or a DC-blocking filter with a cutoff frequency
of 2Hz (80dB attenuation). The MAX98372 supports
5 sample rates: 32kHz, 44.1kHz, 48kHz, 88.2kHz, or
96KHz. For 32kHz, 44.1kHz, and 48kHz, a linear phase,
half-band filter effectively defines the response. For 96kHz
operation, a different filter characteristic is employed with
a smooth roll off above 20kHz. Set the digital highpass
filter corner frequency though the DACHPF bits in control
register 0x1C (Table 9). Create user-programmed filtering
The MAX98372 also features a configurable PVDD ADC
filter. This cutoff frequency of this filter can be adjusted by
setting the PVDD_ADC_BW bits in register 0x1C. These
filtered PVDD ADC measurements can be fed to the DHT
or limiter. Filtered or unfiltered PVDD ADC readings can
be sent to the DHT and limiter. To send filtered data to the
limiter or DHT, set the PVDD_FILT_TO_LMTR or PVDD_
FILT_TO_DHT bits, respectively. See Table 9.
Table 9. Digital Highpass Filter
ADDRESS
BIT
NAME
DESCRIPTION
0: Unfiltered PVDD ADC measurements are sent to the limiter.
1: Lowpass filtered PVDD ADC measurements are sent to limiter.
7
PVDD_FILT_TO_LMTR
0: Unfiltered PVDD ADC measurements are sent to DHT.
1: Lowpass filtered PVDD ADC measurements are sent to DHT.
6
5
PVDD_FILT_TO_DHT
PVDD ADC Lowpass Filter Selection
00: Pass through, filter off
01: 2Hz cutoff
10: 20Hz cutoff
11: 200Hz cutoff
PVDD_ADC_BW[1:0]
0
4
3
Unused: Read back is 0.
0x1C
Digital Highpass Filter
2
1
0
000: Pass through, filter off
001: DC blocker is enabled.
010: 50Hz HPF is enabled.
011: 100Hz HPF is enabled.
100: 200Hz HPF is enabled.
101: 400Hz HPF is enabled.
110: 800Hz HPF is enabled.
111: User programmable using DAC_BQ_B[0–2] and DAC_BQ_A[1–2]
registers
DACHPF[2:0]
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
The digital biquad coefficients are uninitialized at power-
up, and if the filter is going to be used, the coefficients
must be programmed before the device and biquad filter
are enabled. The transfer function is:
Biquad Filter
The digital biquad filter has five user-programmable
coefficients (B0, B1, B2, A1, and A2), and each individual
coefficient is 3 bytes (24 bits) long (A0 is fixed at 1). They
occupy 15 consecutive registers (Table 10) and each set
of three registers (per coefficient) must be programmed
consecutively for the settings to take effect. The coeffi-
cients are stored using a two’s complement format where
the first 4 bits are the integer portion and the last 20 bits
are the decimal portion that results in an approximate +8
to -8 range for each coefficient.
-1
-2
B
+ B * Z + B * Z
1 2
0
H(z) =
-1
-2
1+ A * Z + A * Z
1
2
Signal Path Delay
Delay through the signal path is minimized by use of
efficient signal processing and hardware DSP. Delay is
affected by the configuration of various blocks and filters
in the signal path. Typical delay, listed in number of audio
samples, is shown in Table 11.
Table 10. Biquad Filter Coefficient Registers
REG
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
REG NAME
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT NAME
B0[23:16]
B0[15:8]
B0[7:0]
VALUE
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Biquad
Coefficient B0
B1[23:16]
B1[15:8]
B1[7:0]
Biquad
Coefficient B1
B2[23:16]
B2[15:8]
B2[7:0]
Biquad
Coefficient B2
A1[23:16]
A1[15:8]
A1[7:0]
Biquad
Coefficient A1
A2[23:16]
A2[15:8]
A2[7:0]
Biquad
Coefficient A2
Table 11. Signal Path Delay
SAMPLE RATE (k)
DELAY (SAMPLES)
32
44.1
48
19
19
18
15
14
88.2
96
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
The PVDD ADC readback is real time and is dependant
on the PVDD_ADC_BW register setting in register 0x1C.
PVDD ADC
The PVDD ADC has an effective 8kHz sample rate, 8-bit
resolution and full scale input of 18V. The bandwidth
of the output is user programmable to reject both high
frequency and audio band noise from the supply, and to
tradeoff reaction time to follow the supply accurately. The
PVDD_ADC values are used to by the DHT and Limiter
Digital Volume Control
Auser-controlled digital volume control with an attenuation
range of 0dB to -63dB in 0.5dB steps, as well as a mute
setting is available. Volume ramping is available and
configurable with through the DVOL_RAMP_BYP bit in
the digital volume control register. See Table 13.
2
circuits. These values can be read back over I C through
the PVDD_ADC Register located at 0x34. See Table 12.
Table 12. PVDD Measurement ADC
ADDRESS
BIT
7
NAME
DESCRIPTION
0: 5.35V
1: 5.40V
2: 5.45V
3: 5.50V
…
6
5
4
0x34
PVDD_ADC[7:0]
3
253: 18.05V
254: 18.10V
255: 18.15V
2
1
0
Table 13. Digital Volume Ramping and Digital Volume
ADDRESS
BIT
NAME
DESCRIPTION
Digital Volume Ramp Bypass
7
DVOL_RAMP_BYP
0: Ramping is enabled at startup, shutdown and all volume changes.
1: All volume ramping is disabled.
Digital Volume Control
0: 0dB
1: -0.5dB
2: -1.0dB
3: -1.5dB
6
5
4
3
2
1
0
0x2D
DVOL[6:0]
…
125: -62.5dB
126: -63.0dB
127: Digital mute
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
The DPGA and SPK_GAIN_MAX register settings are
shown in Table 14.
Output Voltage Scaling
The MAX98372 operates over a large supply voltage
range. As a result, the part must be configured to scale
the output signals across possible PVDD supply range.
SPK_GAIN_MAX applies gain after the DAC to achieve
this voltage scaling.
Gain through the signal path is referenced to the full-scale
output of the DAC, which is 2.1dBV. The MAX98372 output
level can be calculated based on the digital input signal
level and selected amplifier gain.
Digital gain can be applied before the DAC by using the
DPGA_CLIPregister. InconjunctionwiththeSPK_GAIN_MAX
setting, the overall full-scale behavior of the device is set.
Output signal level (dBV) = input signal level (dBFS) +
2.1dBV + SPK_GAIN_MAX (dB)
where 0dBFS is referenced to 0dBV.
Table 14. Digital Gain Settings and Output Voltage Scaling
ADDRESS
BIT
NAME
DESCRIPTION
Digital Gain Settings (dB)
7
0000: 0
0110: 3.0
0111: 3.5
0001: 0.5
0010: 1.0
0011: 1.5
0100: 2.0
0101: 2.5
6
5
4
DPGA_CLIP[3:0]
1000: 4.0
1001: 5.0
1010: 6.0
1011–1111: 0
Speaker No-Load Output Voltage Maximum
Sets the output voltage level (V ) of 0dBFS.
3
2
1
P
0000: 5.37 (9.5dB)
0001: 6.03 (10.5dB)
0010: 6.77 (11.5dB)
0011: 7.59 (12.5dB)
0100: 8.52 (13.5dB)
0101: 9.56 (14.5dB)
0110: 10.72 (15.5dB)
0111: 12.03 (16.5dB)
1000: 13.5 (17.5dB)
1001: 15.15 (18.5dB)
1010: 16.99 (19.5dB)
1011: 19.07 (20.5dB)
1100–1111:
Guaranteed no clipping
Best near 5.5V (min) operating
0x2E
2-cell Li-ion operation
SPK_GAIN_MAX[3:0]
12V nominal
3-cell Li-ion operation
Optimum for 16.5V PVDD operation
Reserved
0
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Dynamic Headroom Tracking
The MAX98372 features dynamic headroom tracking
(DHT) to preserve consistant dynamic range in the pres-
ence of a varying supply. DHT maintains consistent vol-
ume and listening levels up to a predefined point, below
full scale. DHT maintains the headroom of the amplifier at
signal peaks that occur above this level (referred to as the
rotation point or RP) up to full scale to ensure consistent,
smooth compression of these signals in the presence of
supply variations.
PVDD > V
MPO
V
MPO
V
EXP_RP
A key element in tracking available headroom is the
PVDD ADC. The output of the ADC feeds the DHT cir-
cuitry with the necessary inputs to calculate the amount of
compression (if any) applied to signal peaks. Filtering can
be applied to the PVDD ADC readings used by the DHT
by using the PVDD_FILT_TO_DHT bit (Table 9).
ROTATION POINT (RP)
SET BY USER
The dynamic headroom tracking function relies heav-
ily on two parameters to be effective. The first is the
SPK_GAIN_MAX setting explained in the Output Voltage
Scaling section. This sets the maximum no-load peak
-6
0
INPUT SIGNAL LEVEL (dBFS)
output voltage (V
that the class D amplifier repro-
MPO)
duces when fed with a full-scale (0dBFS) signal. The
second parameter is the rotation point (RP). The rotation
point sets the level in dBFS above which compression
is applied to the output signal, if the PVDD voltage level
Figure 8. Example of Dynamic Headroom Tracking in Mode 1
Operation
The behavior of DHT has 3 modes, depending on the
drops below V
.
MPO
measured value of V
by the PVDD ADC:
PVDD
DHT uses a parameter called SPK_GAIN_MIN to control
the maximum compression ratio. This parameter can
enable the addition of a second inflection point on the
Transfer function.
MODE 1: PVDD voltage is greater than maximum peak
output voltage. If V is greater than V then there
is no action taken by the DHT block. There is sufficient
headroom for the amplifier to linearly represent any signal
up to and including 0dBFS; the signal transfer function is
unaffected.
PVDD
MPO
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Digital Input Class D Amplifier
with DHT and Brownout Protection
MODE 2: V
is less than V
, and greater than the
(in both Mode 2 and Mode 3) are set by the parameters
in Table 16 and Figure 21.
PVDD
MPO
output voltage as set by the Rotation Point register set-
ting (V ). For example, if the RP is set for -6dBFS,
EXP_RP
MODE 3a: PVDD voltage is less than the rotation points
then the peak voltage on the output (V
) would
EXP_RP
maximum output voltage, V
. When the rotation
EXP_RP
be V /2). If this is the case, the transfer function for
MPO
point is set to a high value (for example -6dBFS) this
mode applies. If V is less than V , then
signals below the RP is reproduced exactly as in Mode 1.
Any signals between RP and 0dBFS are now subject to
an audio compression function, acting in the DSP block
of the MAX98372. This acts with appropriate attenuation
for peaks over the RP in magnitude with programmable
attack and release times (see the DHT Ballistics section).
Figure 9 and Figure 10 show the effect on the transfer
function.
PVDD
EXP_RP
hard limiting is applied to peaks and the effective RP is
now set by the need to fit peak signals into the available
PVDD range. The MAX98372 automatically determines
a new RP based on the PVDD ADC. Normally, RP is set
so that this mode is never used, and the V
as
EXP_RP
set by the RP and SPK_GAIN_MAX combination should
reflect the lowest PVDD value expected. In this mode, the
SPK_GAIN_MIN parameter is set to be well below the
The compression ratios in Mode 2 are effectively defined
by the combination of: PVDD, RP, SPK_GAIN_MAX, and
SPK_GAIN_MIN settings. The ballistics of the compressor
V
.
EXP_RP
SPK_GAIN_MAX
V
MPO
PVDD < V
MPO
PEAK OUTPUT SCALED TO
FIT AVAILABLE PVDD
V
EXP_RP
COMPRESSION RATIO IS SCALED TO
FIT TRANSFER FUNCTION
AUTOMATICALLY BETWEEN
ROTATION POINT AND THEORETICAL
PEAK OUTPUT VOLTAGE (AS
DETERMINED BY PVDD ADC BLOCK)
INPUT SIGNAL LEVEL (dBFS)
-6
0
INPUT (dBFS)
Figure 9. Example of Dynamic Headroom Tracking in Mode 2 Operation with a High RP
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
SPK_GAIN_MAX
V
MPO
PVDD < V
MPO
PEAK OUTPUT SCALED TO
FIT AVAILABLE PVDD
SPK_GAIN_MIN
COMPRESSION RATIO IS SCALED TO
FIT TRANSFER FUNCTION
V
EXP_RP
AUTOMATICALLY BETWEEN
ROTATION POINT AND THEORETICAL
PEAK OUTPUT VOLTAGE (AS
DETERMINED BY PVDD ADC BLOCK)
-30
INPUT SIGNAL LEVEL (dBFS)
0
Figure 10. Example of Dynamic Headroom Tracking in Mode 2 Operation with a Low RP
Table 15. Speaker Gain Minimum Voltage
ADDRESS
BIT
NAME
DESCRIPTION
Speaker Gain Min (V ):
7
P
0000: 5.37 (9.5dB)
0001: 6.03 (10.5dB)
0010: 6.77 (11.5dB)
0011: 7.59 (12.5dB)
0100: 8.52 (13.5dB)
0101: 9.56 (14.5dB)
0110: 10.72 (15.5dB)
0111: 12.03 (16.5dB)
1000: 13.5 (17.5dB)
1001: 15.15 (18.5dB)
1010: 16.99 (19.5dB)
1011: 18.0 (20.0dB)
1100–1111: Reserved
6
5
4
3
2
1
0
SPK_GAIN_MIN[3:0]
0x31
DHT Rotation Point (dBFS)
0000: -0.5
0001: -1
0010: -2
0011: -3
0100: -4
0101: -5
0110: -6
0111: -8
1000: -10
1001: -12
1010: -15
1011: -18
1100: -20
1101: -22
1110: -25
1111: -30
DHT_VROT_PNT[3:0]
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Digital Input Class D Amplifier
with DHT and Brownout Protection
MODE 3b: PVDD voltage is less than the speaker gain
minimum output voltage. When the rotation point is set
to a low value (for example -30dBFS) this mode applies.
compress the signal any further. So the compression ratio
stays fixed, and as PVDD decreases below SPK_GAIN_
MIN, the output signal starts to clip. This clipping can be
eliminated if the limiter is enabled in addition to the DHT.
If V
is less than SPK_GAIN_MIN, the DHT cannot
PVDD
SPK_GAIN_MAX
V
MPO
PVDD < V
EXP_RP
V
EXP_RP
WHEN PVDD < V
A NEW
EXP_RP
ROTATION POINT IS
AUTOMATICALLY DETERMINED AND
INFINITE COMPRESSION IS APPLIED.
INPUT SIGNAL LEVEL (dBFS)
-6
0
Figure 11. Example of Dynamic Headroom Tracking in Mode 3a Operation
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Digital Input Class D Amplifier
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Figure 10 and Figure 12 show an additional param-
eter, SPK_GAIN_MIN, on the transfer function plots.
This parameter is useful when a lower RP is selected.
SPK_GAIN_MIN provides a means to create a maximum
compression ratio. When the input signal reaches the
maximum output voltage that PVDD can provide, the
output signal starts to clip (Figure 12). This behavior may
not be desirable, but the clipping can be eliminated by
enabling the limiter. See Figure 13.
SPK_GAIN_MAX
V
MPO
SPK_GAIN_MIN
PVDD < SPK_GAIN_MIN
CLIPPING
COMPRESSION
V
EXP_RP
-30
INPUT SIGNAL LEVEL (dBFS)
0
Figure 12. Example of Dynamic Headroom Tracking in Mode 3b Operation
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
The transfer function shown in Figure 13 is typically
preferable to the transfer function shown in Figure 12.
When DHT and the limiter are used together, it allows
for creation of a second inflection point on the transfer
function. This second inflection point reduces the transition
from compression to limiting and minimizes the audible
impact of signal manipulation by the DHT.
SPK_GAIN_MAX
V
MPO
SPK_GAIN_MIN
PVDD < SPK_GAIN_MIN
LIMITING
COMPRESSION
V
EXP_RP
THE PERFORMANCE SHOWN
IN THIS FIGURE IS THE
RESULT OF THE DHT AND THE
LIMITER WORKING IN
CONCERT
-30
INPUT SIGNAL LEVEL (dBFS)
0
Figure 13. Example of Dynamic Headroom Tracking in Mode 3b with Limiter
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Digital Input Class D Amplifier
with DHT and Brownout Protection
DHT Ballistics
Observing the output waveform, notice that the amount
of attenuation applied increases up to when VIN(dBFS)
= PVDD (dBFS). Once VIN(dBFS) is greater than
PVDD(dBFS) the amount of attenuation observed in the
output waveform appears to decrease. This is a result of
the output clipping against the PVDD voltage level. The
DHT still takes the same amount of time to apply the
compression as though it had the headroom to reproduce
the signal.
When an input signal exceeds the rotation point, DHT
applies attenuation to the signal over some amount of
time (this is configurable through the DHT_ATK_RATE
register 0x32). The instant that the large signal is input to
the MAX98372, the output tries to reproduce that signal
without any attenuation from the DHT. Over time, the
DHT applies compression to ensure that the signal can fit
within the available PVDD voltage. If a large enough input
signal is applied there can be hard clipping on the output
for a short time (Figure 14). However, after the full attack
time has completed, there should be no clipping. Hard
clipping can also be prevented by using the limiter. See
The amount of compression applied by DHT depends on
a few parameters: SPK_GAIN_MAX, PVDD, input signal
amplitude, and the rotation point.
To establish where PVDD is relative to speaker gain max,
use the following equation:
the Limiter section
.
SPK_GAIN_MAX
V
MPO
-3 dB
V
= 8.4V
PVDD
ATTACK
THE ATTACK ARROW
DEMOSTRATES THE TRANSISTION
FROM AN UNATTENUATED SIGNAL
TO THE COMPRESSED SIGNAL
THAT OCCURS OVER THE TOTAL
ATTACK TIME.
V
EXP_RP
-3
-10
INPUT SIGNAL LEVEL (dBFS)
0
INPUT (dBFS)
Figure 14. Dynamic Headroom Tracking Attack Functionality
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Digital Input Class D Amplifier
with DHT and Brownout Protection
A nontrivial case might be If V
rotation point = -10dBFS, and the input signal level is
-5dBFS. Next, we solve equation 3 with these values:
= 8.4V, V
= 12V,
Equation 1
PVDD
MPO
PVDD(V)
PVDD(dBFS) = 20log
V
MPO
Equation 3
where PVDD(V) is the voltage readback from the PVDD
ADC, and V is the maximum peak output voltage
-PVDD(dBFS)
= PVDD(dBFS) + Input(dBFS)×
MPO
V
(dBFS)
RP
(V
MPO
), see Figure 14. For example, if V
= 12V and
PVDD
3.098dBFS
-10dBFS
V
MPO
= 12V, then PVDD(dBFS) = 0dBFS. It should be
= -3.098dBFS + -5dBFS×
= -1.54dBFS
noted that 0dBFS is the maximum value for PVDD(dBFS).
If solving Equation 1 returns a value greater than 0 then
0dBFS should be used for further calculations. This is
important as DHT only ever applies attenuation and never
positive gain.
For this example, the total amount of compression applied
by DHT 1.54dB. DHT attack rate and DHT attack step can
be configured to apply the 1.54dB of attenuation of over a
programmable amount of time.
If V
= 8.4V and V
= 12V, then solving
PVDD
SPK_GAIN_MAX
Eq 1 gives -3.098dBFS. This is PVDD’s level relative to
SPK_GAIN_MAX in dB. To find the expected compressed
output voltage, use the following equation:
As a rule of thumb, attack times (product of attack rate,
attack step, and number of steps) faster than 600µs are
not achievable. This is independent of sample rate. Input
data is rectified, filtered and converted to the log domain.
The DSP compares the input data with filtered data from
the PVDD ADC then compression is applied within the
DSP. The compressed data must be converted back to lin-
ear scale and then output. The large number of complex
computations required in the DSP requires a fixed 600µs
to complete the compression algorithm. As a result, attack
times faster than 600µs are not possible. See Table 16.
Equation 2
-PVDD(dBFS)
ATTENUATION(dB) = PVDD(dBFS) + Input(dBFS)×
V
(dBFS)
RP
When PVDD(dBFS) = 0, the PVDD and the fraction term
drop out, which gives attenuation equal to zero. This
makes sense because when PVDD(dBFS) = 0, there is
sufficient headroom to playback any signal input into the
MAX98372 and no compression is applied.
Continuing the same example when the input signal size
decreases below the rotation point DHT releases the 1.54dB
of attenuation it applied to the signal. The release time for
DHT is configurable through Register 0x33. See Table 17.
Table 16. Dynamic Headroom Tracking Attack Settings
ADDRESS
BIT
NAME
DESCRIPTION
DHT Attack Step Size
00: 0.25dB
4
DHT_ATK_STEP[1:0]
01: 0.5 dB
10: 1.0dB
11: 2.0dB (default)
3
2
DHT Compressor Attack Rate
All attack times in µs/step
000: 17.5 (default)
001: 35
0x32
010: 70
011: 140
100: 280
101: 560
DHT_ATK_RATE[2:0]
1
0
110: 1120
111: 2240
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Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 17. Dynamic Headroom Tracking Release Settings
ADDRESS
BIT
NAME
DESCRIPTION
DHT Release Step Size
00: 0.25dB
4
DHT_REL_STEP[1:0]
01: 0.5dB
10: 1.0dB
11: 2.0dB (default)
3
2
1
DHT Compressor Release Rate
All release times in ms/step
000: 45 (default)
001: 225
010: 450
011: 1150
0x33
DHT_REL_RATE[2:0]
100: 2250
101: 3100
110: 4500
0
111: 6750
Table 18. Dynamic Gain Enables
ADDRESS
BIT
NAME
DESCRIPTION
0: PVDD ADC is disabled.
1: PVDD ADC is enabled.
2
PVADC_EN
0: Limiter is disabled.
1: Limiter is enabled.
0x4B
1
0
LMTR_EN
DHT_EN
0: Dynamic headroom tracking is disabled.
1: Dynamic headroom tracking is enabled.
Table 19. Limiter Threshold Select
ADDRESS
BIT
NAME
DESCRIPTION
Limiter Threshold Select
1
00: User-programmable threshold (contents of register 0x59).
01: Threshold is set by SPK_GAIN_MAX.
10–11: Threshold is set by PVDD level.
0x58
LMTR_TH_SEL[1:0]
0
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Digital Input Class D Amplifier
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Table 20. Manual Limiter Threshold Settings
ADDRESS
BIT
NAME
DESCRIPTION
4
Manual Limiter Threshold Setting (Input Referred)
00000: 0dBFS
00001: -1dBFS
00010: -2dBFS
00011: -3dBFS
…
11101: -29dBFS
11110: -30dBFS
11111: -31dBFS
3
2
1
0
0x59
LMTR_THC[4:0]
Limiter
Table 21. Limiter Threshold
The MAX98372 features a programmable limiter that is
used to compress large near full-scale signals. The input
signal level where the attenuation is applied varies based
on how the Limiter Threshold Select register is set.
SPK_GAIN_MAX SETTING
LMTR_THRESHOLD (dB)
0x0B
0x0A
0x09
0x08
…
0
-1
-2
When LMTR_TH_SEL is set to 00, the limiter threshold is
user configurable through register LMTR_THC. See Table 20.
-3
When LMTR_TH_SEL is set to 01, the threshold is
determined by SPK_GAIN_MAX. Table 21 provides the
threshold values.
…
-10
-11
0x01
0x00
When LMTR_TH_SEL is set to 10 or 11, the part looks
at the PVDD ADC and the SPK_GAIN_MAX setting and
determines the maximum output swing that the part can
deliver without clipping. Input signals that require more
voltage than is available on PVDD are limited to prevent
clipping. Filtering can be applied to the PVDD ADC read-
ings used by the limiter with the PVDD_FILT_TO_LMTR
bit (Table 9).
Thermal Protection
The MAX98372 continuously monitors die temperature to
ensure that the temperature does not exceed the maxi-
mum of +150°C (typ). The device can warn the host if die
temperature is approaching the limit and turns off the
speaker amplifier if the limit is exceeded. The interrupt
registers are maintained to ensure that host is alerted of
the overtemperature event. Thermal recovery behavior of
the device is determined by the state of TDHSN_AUTO_
RESTART bit in the Restart Behavior (0x4D) register.
If TSHDN_AUTO_RESTART is reset, a drop in the die
temperature below the thermal foldback threshold trig-
gers an interrupt to the host, indicating that it is safe to
turn on the speaker amplifier and resume audio playback.
If TSHDN_AUTO_RESTART is set, the device will turn
on the speaker amplifier when the die temperature drops
below the thermal foldback threshold setting.
The limiter attack and release rates are measured in abso-
lute time and are independent of sample rate. The limiter
has its own set of configurable ballistics (Figure 30).
Thermal ADC
The MAX98372 features a die temperature monitoring
ADC. This 6-bit ADC with a 100kHz sample rate reports
the die temperature from +100°C to +163°C. THRM_MIN_
TEMP sets the temperature at which the thermal foldback
circuit initially activates. The measurements from the
thermal ADC can be filtered before they are used by the
thermal foldback circuit, or the values can pass directly
without being filtered. THRM_FILT_SEL controls the filter
selection.
Thermal Foldback
To allow a smoother audio response to high temperature
events, the MAX98372 features a thermal foldback loop.
As the die temperature rises above a threshold of set
by THRM_MIN_TEMP register (+120°C by default), the
audio path is subjected to increasing attenuation, up to a
maximum of -12dB. See Table 23.
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Table 22. Limiter Attack and Release Settings
ADDRESS
BIT
NAME
DESCRIPTION
Limiter Release Time
Total time required for limiter to fully release
5
000: 15ms
001: 40ms
010: 70ms
011: 160ms
100: 300ms
101: 450ms
110: 600ms
111: 850ms
4
3
LMTR_REL_RATE[2:0]
0x55
Limiter Attack Time
Total time required for limiter to fully attack
000 - 100: 160µs
2
1
LMTR_ATK_RATE[2:0]
101: 320µs
110: 640µs
111: 1280µs
0
Table 23. Thermal ADC Measurements
ADDRESS
BIT
5
NAME
DESCRIPTION
0: 100°C
1: 101°C
…
62: 162°C
63: 163°C
4
3
0x37
THRM_ADC_MEAS[7:0]
2
1
0
0: 100°C
1: 101°C
…
20: 120°C (default)
…
5
4
3
0x38
THRM_MIN_TEMP[6:0]
2
1
39: 139°C
40-63: 140°C
0
000: THRM ADC LPF filter on f = 0.55kHz
C
2
1
001: THRM ADC LPF filter on f = 2.15kHz
C
010: THRM ADC LPF filter on f = 4.55kHz
C
011: Bypass filter (default)
0x39
THRM_FILT_SEL[2:0]
100: THRM ADC peak detect filter on f = 0.55kHz
C
101: THRM ADC peak detect filter on f = 2.15kHz
C
110: THRM ADC peak detect filter on f = 4.55kHz
111: Bypass filter
C
0
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Digital Input Class D Amplifier
with DHT and Brownout Protection
The thermal foldback feature can be turned on through the
THRM_FB_EN bit, default is off (Table 25). The release rate
of the attenuation and the slope of the effect can be set by
the user (Table 24), the attack time is fixed at 10µs/dB.
THRM_HOLD controls how long the temperature must
stay on one side of the hysteresis threshold. THRM_REL
controls the release rate of the attenuation applied by
the thermal foldback circuit. THRM_SLOPE controls the
amount of attenuation per °C. See Table 24.
Regardless of whether the thermal foldback feature is
enabled, the thermal warning bit in the interrupt registers
assert and generate an interrupt through the Interrupt
Mask register when thermal foldback threshold tempera-
ture is crossed.
Figure 15. Thermal Foldback Performance
Table 24. Thermal Foldback Settings
ADDRESS
BIT
NAME
DESCRIPTION
Thermal Foldback Hold Settings
00: 0ms
7
THRM_HOLD[1:0]
01: 20ms
10: 40ms
11: 80ms (default)
6
5
4
0
0
Unused: Read back is 0.
Unused: Read back is 0.
Thermal Foldback Release Times
00: 3ms/dB
01: 10ms/dB
10: 100ms/dB
11: 300ms/dB
3
2
1
0
0X36
THRM_REL[1:0]
Thermal Foldback Slope Settings
00: 0.5dB/°C
01: 1.0dB/°C
10: 2.0dB/°C
11: Reserved
THRM_SLOPE[1:0]
Table 25. Thermal Foldback Enable
ADDRESS
BIT
NAME
DESCRIPTION
Thermal Foldback Enable
0: Thermal foldback disabled
1: Thermal foldback enabled
0x4C
0
THRM_FB_EN
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MAX98372
Digital Input Class D Amplifier
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ALC_MUTE_DLY. The battery debounce time ALC_RLS_
DBT is the time the battery must be above the threshold
before moving to the RELEASE state either from the
MUTE state or the HOLD state. The transition to MUTE
can be disabled by resetting the ALC_MUTE_EN bit. If
ALC_RLS_DBT is set to infinite hold, the gain remains
either muted or at the programmed reduction level below
the nominal PGA gain setting until the ALS_RLS_TGR bit
is set. When ALC_MUTE_EN bit is set the gain remains
at programmed reduction value below the PGA gain
setting until PVDD rises above the brownout threshold.
ALC gain reductions are independent of the minimum
attenuation setting of the PGA. If enabled, gain ramping
has no effect on ALC attack, release or mute actions.
Figure 16–Figure 19 provide examples of how the ALC
behaves in four scenarios. If PVDD is held close to the
ALC threshold, ALC will be stuck in a state of intermedi-
ate attenuation. Intermediate Attenuation means that ALC
started to reduce gain but never reaches the programmed
maximum attenuation. Gain is constant in this state, in-
between original gain and maximum attenuation as ALC
is neither attacking of releasing. Figure 20 shows an
example of ALC Intermediate attenuation.
Automatic Level Control (ALC)
The MAX98372 automatic level control feature (ALC)
reduces the amplifier gain at the PGA if the battery volt-
age drops below a programmable brownout threshold
preventing battery collapse. ALC compares PVDD to the
programmable brownout threshold set by ALC_TH and
ALC_RANGE. When PVDD drops below the brownout
threshold the ALC reduces amplifier gain at a program-
mable attack rate and step size set by ALC_ATK_RATE
and ALC_ATK_STEP. The gain change occurs immedi-
ately even when zero-cross detection is enabled. PGA
gain reduction is programmable from 1dB to 9dB in 1dB
steps below the nominal setting of the GAIN register (reg-
ister 0x64, ALC_MAX_ATTEN). If gain reductions cause
the battery voltage to rise above the brownout threshold,
the gain reduction stops to a level where PVDD again
drops below the brownout threshold after a programmable
debounce time set by ALC_RLS_DBT. The rate at which
the gain is restored is set by ALC_RLS_RATE and ALC_
RLS_CFG. If the battery supply voltage remains below
the brownout threshold after the amplifier gain has been
reduced by programmed setting, the speaker amplifier is,
by default, muted after a programmable delay time set by
V
PVDD
PROGRAMMABLE
THRESHOLD
ALCTH
VPVDD DROPS BELOW
THRESHOLD
t
SPEAKER GAIN
ATTACK RATE
PER
ATTACK STEP
14dB
5dB
RELEASE
RATE
MAX ATTENUATION
(0dB to 9dB)
RELEASE DE-BOUNCE
TIME
MUTE
t
Figure 16. ALC Example 1: Battery Drops Below Brownout Threshold and Quickly Recovers
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MAX98372
Digital Input Class D Amplifier
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V
PVDD
PROGRAMMABLE
THRESHOLD
ALCTH
VPVDD DROPS BELOW
THRESHOLD
t
ATTACK RATE
PER
SPEAKER GAIN
ATTACK STEP
14dB
5dB
MAX ATTENUATION
(0dB to 9dB)
MUTE DELAY
MUTE
t
MUTE ENABLED
Figure 17. ALC Example 2: Battery Drops Below Brownout Threshold and Stays Low
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
V
PVDD
PROGRAMMABLE
THRESHOLD
ALCTH
VPVDD DROPS BELOW
THRESHOLD
t
ATTACK RATE
PER
SPEAKER GAIN
ATTACK STEP
14dB
RELEASE DE-BOUNCE
TIME
5dB
MAX ATTENUATION
(0dB to 9dB)
RELEASE RATE
MUTE
t
MUTE ENABLED, NON-INFINITE HOLD
Figure 18. ALC Example 3: Battery Drops Below Brownout Threshold and Stays Long Enough for the Amp to Mute (Non-Infinite Hold Time)
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
V
PVDD
PROGRAMMABLE
THRESHOLD
ALCTH
VPVDD DROPS BELOW
THRESHOLD
t
ATTACK RATE
PER
SPEAKER GAIN
ATTACK STEP
14dB
HOST TRIGGERS
RELEASE
5dB
MAX ATTENUATION
(0dB to 9dB)
RELEASE RATE
MUTE
t
MUTE ENABLED, INFINITE HOLD
Figure 19. ALC Example 4: Battery Drops Below Brownout Threshold and Stays Long Enough for the Amp to Mute (Infinite Hold Time)
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
V
VPVDD DROPS BELOW
THRESHOLD
PVDD
PROGRAMMABLE
THRESHOLD
ALCTH
t
SPEAKER GAIN
ATTACK RATE
PER
ATTACK STEP
14dB
5dB
RELEASE
RATE
MAX ATTENUATION
(0dB to 9dB)
RELEASE
DE-BOUNCE TIME
MUTE
t
Figure 20. ALC Example 5: Immediate Attenuation
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Digital Input Class D Amplifier
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Table 26. ALC Threshold
ADDRESS
BIT
NAME
DESCRIPTION
7
0
Unused: Read back is 0.
0: 2-cell operation (default)
1: 3-cell operation
6
5
ALC_RANGE
ALC_EN
0: ALC is not enabled (default)
1: ALC is enabled.
Value (Hex)
ALC_RANGE = 0
ALC_RANGE = 1
7.80
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
—
—
7.95
4
—
8.10
5.5
8.25
5.6
8.40
5.7
8.55
5.8
8.70
3
2
5.9
8.85
0x62
6.0
9.00
6.1
9.15
ALC_TH[4:0]
6.2 (default)
6.3
9.30 (default)
9.45
6.4
9.60
6.5
9.75
6.6
9.90
6.7
10.05
10.20
10.35
10.50
10.65
10.80
10.95
1
0
6.8
6.9
12
13
14
15
7.0
7.1
7.2
7.3
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 27. ALC Attack
ADDRESS
BIT
NAME
DESCRIPTION
ALC Attack step
7
0: -1 dB step (default)
1: -2 dB Step
2: -3 dB Step
3: -4 dB Step
4: -5 dB Step
5: -6 dB Step
6: -7 dB Step
7: -8 dB Step
8: -9 dB Step
…
6
5
ALC_ATK_STEP[3:0]
4
F: -9 dB Step
0x63
3
2
0
Unused: Read back is 0.
ALC Attack rate
000: 10ms/step (default)
001: 20ms/step
010: 40ms/step
011: 80ms/step
100: 160ms/step
101: 320ms/step
110: 640ms/step
111: 1280ms/step
1
0
ATK_RATE
Table 28. ALC Attenuation and Release
ADDRESS
BIT
NAME
DESCRIPTION
ALC Maximum Gain Reduction Setting (dB)
0000: -1
7
0001: -2
6
5
0010: -3
0011: -4
0100: -5
0101: -6
ALC_MAX_ATTEN[3:0]
0110: -7
0111: -8
1000: -9 (default)
4
3
2
0x64
0
Unused: Read back is 0.
ALC Release rates (ms/dB)
000: 10 (default)
001: 50
010: 100
1
0
ATK_RLS_RATE[2:0]
011: 250
100: 500
101: 750
110: 1000
111: 1500
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 29. ALC Infinite Hold Release
ADDRESS
BIT
NAME
DESCRIPTION
00: Uses ALC_RLS_RATE[2:0] as defined
7
01: 8x faster release rate
10: 64x faster release rate
11: 512x faster release rate
ALC_RLS_CFG[1:0]
6
5
4
3
2
1
0
0
0
0
0
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
0x65
0: Register is self-clearing and always read back as ‘0’
1: If Infinite HOLD is enabled, write a ‘1’ to unlock the release phase. If
infinite HOLD is enabled and a ‘1’ is written while a battery low event is
occurring, the gain is NOT released
0
ALC_RLS_TGR
Table 30. ALC Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: ALC cannot mute the channel path
1: ALC can mute the channel path (default)
7
ALC_MUTE_EN
Delay Before Onset of Mute
000: 0.3ms
001: 0.6ms (default)
010: 1ms
6
5
ALC_MUTE_DLY[2:0]
011: 3ms
100: 4.5ms
101: 6ms
110: 15ms
111: 30ms
4
3
2
0x66
0
Unused: Read back is 0.
Battery Debounce Time (ms)
000: 10
001: 100
010: 250 (default)
011: 500
100: 0.01
101: 0.1
1
0
ALC_RLS_DBT[2:0]
110: 1
111: Infinite hold
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
bit. At all other times, the pin is an input (to allow other
devices to drive the DOUT signal).
DOUT Operation and Data format
The MAX98372 features a bidirectional DOUT pin to
provide feedback data to the applications processor and
other MAX98372s. The data output from DOUT shares
the status of amplifier DHT, thermal foldback adjustments,
and ALC status. The data format used to frame the data
carried on DOUT is the same as the data format of the
input data on the DIN pin. The DOUT pin only drives out
during the slot assigned to the amplifier by TX_CH#_EN
The data output on the DOUT pin is structured as shown
in Figure 21.
Where DHT_INFO[7:0] contains the DHT attenuation (in
dB), THERM_INFO [5:0] contains the thermal foldback
attenuation, and ALC[0] contains transmitter devices’ ALC
comparator status broadcast out to other amplifiers on the
same bus. It is decoded as shown in Figure 21.
Table 31. DHT INFO
Table 32. THERM INFO
VALUE
DECODE (°C)
VALUE
DECODE (dB)
-95.625
-95.25
0
1
No thermal adjustment needed
0
+1
+2
1
2
2
-94.875
0.375 (steps)
-0.750
…
61
62
63
1 (steps)
+61
…
253
254
255
+62
-0.375
+63
0
Note: X are padding bits and zeros that make up the remaining bits in the rest of the frame.
SLOT 1
SLOT 2
SLOT 3
SLOT 4
DHT_INFO[7:0]
THERM_INFO[5:0] ALC
X
Figure 21. DOUT Data Structure
Table 33. Thermal and DHT Link Enables
ADDRESS
BIT
NAME
DESCRIPTION
0: Disable ALC link.
1: Enable ALC link.
2
ALC_LINK_EN
0: Disable THRM link.
1: Enable THRM link.
1
0
THRM_LINK_EN
DHT_LINK_EN
0x4E
0: Disable DHT link.
1: Enable DHT link.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
The THRM_LINK_EN, DHT_LINK_EN, and ALC_LINK_
EN are intended to be used as the global enables of
receive data function of the ICC. It should also be noted
that for the ICC to function properly ICC_OC_ENA bit in
register 0x5C must be set to 1 so that the overcurrent
protection on DOUT is enabled.
4 belong to another. Assign amplifier 1 to broadcast on
slot 0 through the TX_CH0_EN bit enable and amplifier 3
to broadcast on slot 2 through the TX_CH2_EN bit. Then
configure both amplifiers to enable RX enable to listen to
both slots 0 and 2, so both amplifiers would have RX_
DHT_CH0_EN and RX_DHT_CH2_EN enabled. While
this configuration groups the amplifier in the same DHT
group, there is another set of grouping registers for ther-
mal foldback. These registers can be configured identi-
cally or differently to accommodate the desired behavior.
To configure the second group, set amplifier 2 to broad-
cast on slot 1 through TX_CH1_EN and set amplifier 4 to
broadcast on slot 3 through TX_CH3_EN. Then configure
both amplifiers to enable RX enable to listen to both slots
1 and 3, so both amps would have RX_DHT_CH1_EN
and RX_DHT_CH3_EN enabled.
Interchip Communication
The MAX98372 features an interchip communication
(ICC) bus that facilitates synchronized gain adjustments
between groups of MAX98372 amplifiers.
Multiamplifier Grouping
By setting registers 0x3A through register 0x3F, registers
0x60 and 0x61, it is possible to group MAX98372 ampli-
fiers so that any gain adjustments due to DHT and/or
thermal foldback and/or ALC status are synchronized.
By definition, the minimum size of a group is two ampli-
fiers, so the maximum number of groups that is supported
is eight. A group can contain as many as 16 amplifiers, but
then only one group is supported.
Each amplifier is configured by a register setting to moni-
tor DOUT during certain slots. The slots selected define
to which group each amplifier belongs. Therefore, each
amplifier in a group must have the same settings for RX
enables. Each individual amplifier must also have only
one TX_CH# enable set as well as the corresponding
RX_CH# enable.
It is a requirement of the host processor to ensure that
the RX register bits are set to the same values across all
amplifiers intended to be used in a group. Devices in the
same DHT group must also be configured with the same
DHT parameters (SPK_GAIN_MAX, RP, and ballistics)
to achieve a balanced response across the group. The
same is true of the THERM group and ALC group.
For example, if there are four amplifiers and two groups
are needed, then one configuration may be that amplifiers
1 and 3 would belong to one group and amplifiers 2 and
Table 34. InterChip Communication Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: Disable overcurrent protection on DOUT.
1: Enable overcurrent protection on DOUT.
6
ICC_OC_ENA
0: Disable faster drive enable of the DOUT.
1: Enable faster drive enable of the DOUT for the ICC with BCLK rate
greater than 12.288MHz.
5
4
ICC_DOUTEN_EXTFF
ICC_DOUT_EXTFF
0: Disable faster drive of the DOUT.
1: Enable faster drive of the DOUT for the ICC with BCLK rate greater
than 12.288MHz.
DOUT Drive Strength Control
0000: 1 (default)
0001 and 0010: 7/8
0011 and 0100: 3/4
0101 and 0110: 5/8
0111 and 1000: 1/2
1001 and 1010: 3/8
1011 and 1100: 1/4
0x5C
3
2
1
ICC_PAD_CTRL[3:0]
1101: 1/8
1110: 1/8 with Miller slew rate reduction (improves EMI)
1111: off
0
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
In this way, the DOUT data transfer rate is effectively
half of the BCLK speed. This is accomplished by setting
DRIVE_MODE = 1.
Double Data Drive
If the shared DOUT trace has a high capacitance that
needs to be driven at high speed then the double-data
drive feature can be used. This gives a longer drive time
for each device.
This has implications for the supported slot lengths. When
double-data drive is enabled, only 32-bit slot lengths are
permitted.
When the BCLK is less than or equal to 25MHz, DOUT
can be clocked with standard clocking: data changes on
the falling edge and is valid on the rising edge of each
BCLK (Table 35).
Additional MAX98372 devices correctly interpret the
double-data drive format (if enabled). Any other attached
hardware, such as an applications processor, which is
expecting standard timing, needs to ensure that it omits
away the information captured on the nonvalid rising edge
each time and reconstruct the samples accordingly.
When the BCLK is greater than 25MHz, DOUT should be
clocked using a double-data drive method: data changes
on the falling edge and is valid on the second rising edge.
Table 35. DOUT Double Data Drive Mode
ADDRESS
BIT
NAME
DESCRIPTION
0: Single data drive (default)
1: Double data drive
0x40
3
DRIVE_MODE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DHT
[7]
DHT
[6]
DHT
[5]
DHT
[4]
DHT
[3]
DHT
[2]
DHT
[1]
DHT
[0]
THM THM THM THM THM THM
[5] [4] [3] [1] [0]
[2]
ALC
[0]
THREE-STATE DATA AT
END OF SLOT
DRIVE DATA ON
FALLING EDGE
RECEIVE DATA ON
RISING EDGE
Figure 22. Single Data Drive
31
30
29
28
27
26
25
24
DHT [7]
DRIVE
DHT [6]
DHT [5]
DHT [4]
t
Figure 23. Double Data Drive illustration
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 36. DOUT DHT Receive Channel Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: DHT receive channel 7 is disabled.
1: DHT receive channel 7 is enabled.
7
RXDHT_CH7_EN
0: DHT receive channel 6 is disabled.
1: DHT receive channel 6 is enabled.
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RXDHT_CH6_EN
RXDHT_CH5_EN
RXDHT_CH4_EN
RXDHT_CH3_EN
RXDHT_CH2_EN
RXDHT_CH1_EN
RXDHT_CH0_EN
RXDHT_CH15_EN
RXDHT_CH14_EN
RXDHT_CH13_EN
RXDHT_CH12_EN
RXDHT_CH11_EN
RXDHT_CH10_EN
RXDHT_CH9_EN
RXDHT_CH8_EN
0: DHT receive channel 5 is disabled.
1: DHT receive channel 5 is enabled.
0: DHT receive channel 4 is disabled.
1: DHT receive channel 4 is enabled.
0x3A
0: DHT receive channel 3 is disabled.
1: DHT receive channel 3 is enabled.
0: DHT receive channel 2 is disabled.
1: DHT receive channel 2 is enabled.
0: DHT receive channel 1 is disabled.
1: DHT receive channel 1 is enabled.
0: DHT receive channel 0 is disabled.
1: DHT receive channel 0 is enabled.
0: DHT receive channel 15 is disabled.
1: DHT receive channel 15 is enabled.
0: DHT receive channel 14 is disabled.
1: DHT receive channel 14 is enabled.
0: DHT receive channel 13 is disabled.
1: DHT receive channel 13 is enabled.
0: DHT receive channel 12 is disabled.
1: DHT receive channel 12 is enabled.
0x3B
0: DHT receive channel 11 is disabled.
1: DHT receive channel 11 is enabled.
0: DHT receive channel 10 is disabled.
1: DHT receive channel 10 is enabled.
0: DHT receive channel 9 is disabled.
1: DHT receive channel 9 is enabled.
0: DHT receive channel 8 is disabled.
1: DHT receive channel 8 is enabled.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 37. DOUT Thermal Foldback Receive Channel Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: THRM FB receive channel 7 is disabled.
1: THRM FB receive channel 7 is enabled.
7
RXTHM_CH7_EN
0: THRM FB receive channel 6 is disabled.
1: THRM FB receive channel 6 is enabled.
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RXTHM_CH6_EN
RXTHM_CH5_EN
RXTHM_CH4_EN
RXTHM_CH3_EN
RXTHM_CH2_EN
RXTHM_CH1_EN
RXTHM_CH0_EN
RXTHM_CH15_EN
RXTHM_CH14_EN
RXTHM_CH13_EN
RXTHM_CH12_EN
RXTHM_CH11_EN
RXTHM_CH10_EN
RXTHM_CH9_EN
RXTHM_CH8_EN
0: THRM FB receive channel 5 is disabled.
1: THRM FB receive channel 5 is enabled.
0: THRM FB receive channel 4 is disabled.
1: THRM FB receive channel 4 is enabled.
0x3C
0: THRM FB receive channel 3 is disabled.
1: THRM FB receive channel 3 is enabled.
0: THRM FB receive channel 2 is disabled.
1: THRM FB receive channel 2 is enabled.
0: THRM FB receive channel 1 is disabled.
1: THRM FB receive channel 1 is enabled.
0: THRM FB receive channel 0 is disabled.
1: THRM FB receive channel 0 is enabled.
0: THRM FB receive channel 15 is disabled.
1: THRM FB receive channel 15 is enabled.
0: THRM FB receive channel 14 is disabled.
1: THRM FB receive channel 14 is enabled.
0: THRM FB receive channel 13 is disabled.
1: THRM FB receive channel 13 is enabled.
0: THRM FB receive channel 12 is disabled.
1: THRM FB receive channel 12 is enabled.
0x3D
0: THRM FB receive channel 11 is disabled.
1: THRM FB receive channel 11 is enabled.
0: THRM FB receive channel 10 is disabled.
1: THRM FB receive channel 10 is enabled.
0: THRM FB receive channel 9 is disabled.
1: THRM FB receive channel 9 is enabled.
0: THRM FB receive channel 8 is disabled.
1: THRM FB receive channel 8 is enabled.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 38. DOUT Transmit Channel Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: Transmit channel 7 is disabled.
1: Transmit channel 7 is enabled.
7
TX_CH7_EN
0: Transmit channel 6 is disabled.
1: Transmit channel 6 is enabled.
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TX_CH6_EN
TX_CH5_EN
TX_CH4_EN
TX_CH3_EN
TX_CH2_EN
TX_CH1_EN
TX_CH0_EN
TX_CH15_EN
TX_CH14_EN
TX_CH13_EN
TX_CH12_EN
TX_CH11_EN
TX_CH10_EN
TX_CH9_EN
TX_CH8_EN
0: Transmit channel 5 is disabled.
1: Transmit channel 5 is enabled.
0: Transmit channel 4 is disabled.
1: Transmit channel 4 is enabled.
0x3E
0: Transmit channel 3 is disabled.
1: Transmit channel 3 is enabled.
0: Transmit channel 2 is disabled.
1: Transmit channel 2 is enabled.
0: Transmit channel 1 is disabled.
1: Transmit channel 1 is enabled.
0: Transmit channel 0 is disabled.
1: Transmit channel 0 is enabled.
0: Transmit channel 15 is disabled.
1: Transmit channel 15 is enabled.
0: Transmit channel 14 is disabled.
1: Transmit channel 14 is enabled.
0: Transmit channel 13 is disabled.
1: Transmit channel 13 is enabled.
0: Transmit channel 12 is disabled.
1: Transmit channel 12 is enabled.
0x3F
0: Transmit channel 11 is disabled.
1: Transmit channel 11 is enabled.
0: Transmit channel 10 is disabled.
1: Transmit channel 10 is enabled.
0: Transmit channel 9 is disabled.
1: Transmit channel 9 is enabled.
0: Transmit channel 8 is disabled.
1: Transmit channel 8 is enabled.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 39. DOUT ALC Receive Channel Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: ALC FB receive channel 7 is disabled.
1: ALC FB receive channel 7 is enabled.
7
RXALC_CH7_EN
0: ALC FB receive channel 6 is disabled.
1: ALC FB receive channel 6 is enabled.
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RXALC_CH6_EN
RXALC_CH5_EN
RXALC_CH4_EN
RXALC_CH3_EN
RXALC_CH2_EN
RXALC_CH1_EN
RXALC_CH0_EN
RXALC_CH15_EN
RXALC_CH14_EN
RXALC_CH13_EN
RXALC_CH12_EN
RXALC_CH11_EN
RXALC_CH10_EN
RXALC_CH9_EN
RXALC_CH8_EN
0: ALC FB receive channel 5 is disabled.
1: ALC FB receive channel 5 is enabled.
0: ALC FB receive channel 4 is disabled.
1: ALC FB receive channel 4 is enabled.
0x60
0: ALC FB receive channel 3 is disabled.
1: ALC FB receive channel 3 is enabled.
0: ALC FB receive channel 2 is disabled.
1: ALC FB receive channel 2 is enabled.
0: ALC FB receive channel 1 is disabled.
1: ALC FB receive channel 1 is enabled.
0: ALC FB receive channel 0 is disabled.
1: ALC FB receive channel 0 is enabled.
0: ALC FB receive channel 15 is disabled.
1: ALC FB receive channel 15 is enabled.
0: ALC FB receive channel 14 is disabled.
1: ALC FB receive channel 14 is enabled.
0: ALC FB receive channel 13 is disabled.
1: ALC FB receive channel 13 is enabled.
0: ALC FB receive channel 12 is disabled.
1: ALC FB receive channel 12 is enabled.
0x61
0: ALC FB receive channel 11 is disabled.
1: ALC FB receive channel 11 is enabled.
0: ALC FB receive channel 10 is disabled.
1: ALC FB receive channel 10 is enabled.
0: ALC FB receive channel 9 is disabled.
1: ALC FB receive channel 9 is enabled.
0: ALC FB receive channel 8 is disabled.
1: ALC FB receive channel 8 is enabled.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 40. Extra BCLK Cycle Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: Extra BCLK cycles are driven to zero.
1: Extra BCLK cycles are driven to high impedance.
0x41
1
TX_EXTRA_HIZ
Table 41. Manual High-Impedance Mode Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: Transmit Channel 7 outputs data/zeros.
1: Transmit Channel 7 outputs high impedance.
7
TX_CH7_HIZ
0: Transmit Channel 6 outputs data/zeros.
1: Transmit Channel 6 outputs high impedance.
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TX_CH6_HIZ
TX_CH5_HIZ
TX_CH4_HIZ
TX_CH3_HIZ
TX_CH2_HIZ
TX_CH1_HIZ
TX_CH0_HIZ
TX_CH15_HIZ
TX_CH14_HIZ
TX_CH13_HIZ
TX_CH12_HIZ
TX_CH11_HIZ
TX_CH10_HIZ
TX_CH9_HIZ
TX_CH8_HIZ
0: Transmit Channel 5 outputs data/zeros.
1: Transmit Channel 5 outputs high impedance.
0: Transmit Channel 4 outputs data/zeros.
1: Transmit Channel 4 is enabled.
0X42
0: Transmit Channel 3 outputs data/zeros.
1: Transmit Channel 3 outputs high impedance.
0: Transmit Channel 2 outputs data/zeros.
1: Transmit Channel 2 outputs high impedance.
0: Transmit Channel 1 outputs data/zeros.
1: Transmit Channel 1 outputs high impedance.
0: Transmit Channel 0 outputs data/zeros.
1: Transmit Channel 0 outputs high impedance.
0: Transmit Channel 15 outputs data/zeros.
1: Transmit Channel 15 outputs high impedance.
0: Transmit Channel 14 outputs data/zeros.
1: Transmit Channel 14 outputs high impedance.
0: Transmit Channel 13 outputs data/zeros.
1: Transmit Channel 13 outputs high impedance.
0: Transmit Channel 12 outputs data/zeros.
1: Transmit Channel 12 outputs high impedance.
0x43
0: Transmit Channel 11 outputs data/zeros.
1: Transmit Channel 11 outputs high impedance.
0: Transmit Channel 10 outputs data/zeros.
1: Transmit Channel 10 outputs high impedance.
0: Transmit Channel 9 outputs data/zeros.
1: Transmit Channel 9 outputs high impedance.
0: Transmit Channel 8 outputs data/zeros.
1: Transmit Channel 8 outputs high impedance.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
rate slows the efficiency goes down. Set the speaker
edge rate with bits SPK_EDGE bits in register 0x4A.
Class D Output Stage
The MAX98372 Class D output stage with active emis-
sions limiting and spread spectrum provides optimum
suppression and control of output switching harmonics
that most directly contribute to EMI and radiated emis-
sions. Programmable speaker edge rate control is avail-
able to help tweak EMI performance. As the edge rate
increases the efficiency goes up slightly, and as the edge
The default Class D output switching frequency is 472kHz
for the best THD performance. To trade off THD perfor-
mance for higher efficiency the output switching frequency
can be set to 330kHz by setting SPK_SWCLK to 1.
Chnages to the SPK_EN bit should only be made when
Global Enable (EN) is set low. See Table 42 for speaker
configuration.
Table 42. Speaker Configuration
ADDRESS
BIT
NAME
DESCRIPTION
Class D output Switching Frequency Select
0: Speaker switching frequency is set to 472kHz (default).
1: Speaker switching frequency is set to 330kHz.
7
SPK_SWCLK
6
5
0
Unused: Read back is 0.
Speaker Spread Spectrum Modulation Control
00: SSM is disabled (default)
SPK_SSM[1:0]
4
3
10: SSM is enabled
Programmable Speaker Edge Rate Control
00: Nominal edge rate (default)
01: +15% faster edge rate
0x4A
SPK_EDGE[1:0]
2
1
10: -40% slower edge rate
11: -20% slower edge rate
0
Unused: Read back is 0.
Speaker Amplifier Enable
0
SPK_EN
0: Speaker amplifier is disabled (default).
1: Speaker amplifier is enabled
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Maxim’s spread-spectrum modulation mode flattens
wideband spectral components while proprietary
techniques ensure that the cycle-to-cycle variation of the
switching period does not degrade audio reproduction or
efficiency. The ICs’ spread-spectrum modulator randomly
varies the switching frequency by as much as ±18.6kHz
around 330kHz center frequency, or by ±39.4kHz around
478.75kHz center frequency. Above 10MHz, the wideband
spectrum looks like noise for EMI purposes.
Ultra-Low EMI Filterless Output Stage
Traditional Class D amplifiers require the use of external
LC filters, or shielding, to meet electromagnetic-interfer-
ence (EMI) regulation standards. The active emissions
limiting edge-rate control circuitry reduce EMI emissions
so that with 12in of speaker cable the MAX98372 passes
the EN55022B standard without the need for external
filtering components.
Figure 24. EMI Plot 1: 12in, 8Ω, 16V, ½ Power, No Ferrite Bead, Edge Rate +15%
Figure 25. EMI Plot 2: 12in, 4Ω, 16V, ½ Power, No Ferrite Bead, Edge Rate +15%
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Figure 26. EMI Plot 3: 12in, 8Ω, 16V, ½ Power, Ferrite Bead
Figure 27. EMI Plot 4: 12in, 4Ω, 16V, ½ Power, Ferrite Bead
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 43. Spread-Spectrum Modulation Configuration
ADDRESS
BIT
7
NAME
DESCRIPTION
0
0
0
0
0
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
Unused: Read back is 0.
6
5
4
3
Spread Spectrum Modulation Index Selection
0x49
SSM_MODINDEX
Modulation
2
0x0
0x1 (Default)
0x2
±7.7% & ±3.8%
±6.4% & ±3.8%
±5.1% & ±2.6%
±3.8% & ±2.6%
±2.6% & ±1.3%
±1.3% & ±1.3%
SSM_MODINDEX
1
0
0x3
0x4
0x5
During normal operation, any requested gain changes are
ramped from the old value to the new value at a value
determined by the ballistics within the volume control block.
V
and V
UVLO
DVDD
PVDD
The MAX98372 monitors both DVDD and PVDD for low
voltage conditions that would prevent the speaker amplifier
from operating normally. If the voltage on DVDD drops below
the DVDD-UVLO threshold (V
placed in hardware shutdown. All the I C internal registers
reset to their default values. The device can be commanded
Amplifier Current Limit
), the device is
DVDD-UVLO
The MAX98372 features current limit protection that pro-
tects the device against shorts. If the output current of
the speaker amplifier exceeds the current limit (6A typ)
the IC disables the outputs for approximately 100µs. After
100ms, the outputs are reenabled. If the fault condition
still exists, the IC continues to disable and reenable the
outputs until the fault condition is removed. Set OVC_SEL
low to disable this behavior (Table 44). The current limit
protects against both high-current and short-circuit events.
2
2
to leave this state through the I C command if the voltage
on DVDD later exceeds the V
threshold.
DVDD-UVLO
If the voltage PVDD drops below the PVDD-UVLO thresh-
old, the audio output is muted to prevent the PVDD supply
from being used by the amplifier. If the voltage on PVDD
later exceeds the V
be commanded to unmute through the I C command.
threshold, the device can
2
PVDD-UVLO
Thermal Shutdown Recovery
Click-and-Pop Suppression
When the temperate of the die exceeds +150°C, the
part enters thermal shutdown. However, the MAX98372
features a configurable thermal shutdown autorecov-
ery mode. When the die temperate has decreased by
30°C from the thermal shutdown event, the MAX98372
attempts to resume the previous operating state. Set
TSHDN_AUTO_RESTART high to enable autorecovery
mode (Table 44).
The MAX98372 speaker amplifier features Maxim’s com-
prehensive click-and-pop suppression. During power-up
and power-down, the click-and-pop suppression circuitry
reduces any audible transient sources internal to the device.
At startup, the PGA gain is automatically ramped from
mute to the desired setting at a rate of 200µs/dB.
Similarly, the gain is ramped down to mute at shutdown
at the same rate. For faster startup and shutdown, disable
gain ramping.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Output Sensing When Using Ferrites
The MAX98372 features two remote sensing pins OUTN_
SNS and OUTP_SNS. Remotely sensing the voltage
at the load provides a THD+N advantage over sens-
ing at the DUT output when ferrite beads are used
(Figure 29).The remote sense lines connect the output
signal at the load to the inverting terminal of the internal
error amplifier of the Class D (Figure 28). Ferrites are
highly nonlinear so sensing at the load versus at the out-
put pins ensures that any signal degradation caused by
the filtering components is appropriately compensated.
MAX98372
OUTP SNS
OUTP
FB
SPEAKER AMPLIFIER
OUTN
FB
However, in many applications, there may not be a need
to filter the output with a ferrite bead.
OUTN SNS
Clocking Architecture
The MAX98372 includes a flexible clocking architecture
and operation with no MCLK input.
A configurable internal clock monitor circuit monitors the
internal clock source (BCLK) and automatically places
the device in software shutdown if the clock source is
removed. Set CMON_ENA high to enable the clock
monitor. This prevents unwanted signals from being
applied to the speaker during a fault condition. When
CMON_AUTO_RESTART is high, the device automati-
cally returns to normal operation when the clock source
is subsequently reapplied (Table 44).
Figure 28. Typical Application Circuit with Ferrites Beads Used
Reset
The MAX98372 features an active-low hardware reset.
When the voltage-on reset is pulled low, the part enters
global shutdown. To reenable the part, the reset pin must
2
be pulled high and a global enable I C command must
be issued.
Hardware Reset
When the reset pin is pulled low, the device is in its lowest
2
power-down state and communication over I C is not
possible. After exiting reset mode, all registers are set to
their default POR values.
Also, if DVDD is removed while PVDD is still applied,
the device goes into a hardware shutdown mode and
2
communication through I C is not possible.
Figure 29. THD Performance Improvement Enabled by Remote
Sensing
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Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 44. Clock Monitor Configuration
ADDRESS
BIT
NAME
DESCRIPTION
0: Device does not restart after a clock monitor event (default).
1: Device restarts automatically when BCLK is restarted.
3
CMON_AUTO_RESTART
0: Clock monitor is disabled (default).
1: Clock monitor is enabled.
2
1
0
CMON_ENA
OVC_SEL
0x4D
0: Current limit recovery is in manual mode (default).
1: Current limit recovery is in autorecovery mode.
0: Thermal-protection recovery is in manual mode (default).
1: Thermal-protection recovery is in autorecovery mode.
TSDHN_AUTO_RESTART
Table 45. Reset Register
ADDRESS
BIT
NAME
DESCRIPTION
Reset
0x51
0
RST
0: No action is taken.
1: Reset. All registers return to their POR (default) values.
Table 46. Global Enable Register
ADDRESS
BIT
NAME
DESCRIPTION
Global Enable:
0: Disabled
0x50
0
EN
1: Enabled
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
generated SCL pulses. The master acknowledges receipt
of each byte of data. Each read sequence is framed by
a START (S) or REPEATED START (Sr) condition, a
not acknowledge, and a STOP (P) condition. SDA oper-
ates as both an input and an open-drain output. A pullup
resistor, typically greater than 500Ω, is required on SDA.
SCL operates only as an input. A pullup resistor, typically
greater than 500Ω, is required on SCL if there are mul-
tiple masters on the bus, or if the single master has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the IC from high voltage spikes on the bus lines,
and minimize crosstalk and undershoot of the bus signals.
Software Reset
Write 1 to bit 0 of register 0x51 to trigger a software reset.
Software reset is used to return most registers to their
default (POR) states. Biquad equalizer coefficients are not
reset.
The software reset register is a write only register. As a
result, a read of this register always returns 0x00. Writing
logic-high to RST triggers a software register reset, while
writing a logic-low to RST has no effect.
Also if PVDD is removed while DVDD is still applied the
device goes into software shutdown mode where all
blocks are disabled except I C control block.
2
2
I C Serial Interface
Bit Transfer
2
The MAX98372 features an I C 2-wire serial interface
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals. See the START and STOP Conditions section.
consisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate communication between the
IC and the master at clock rates up to 400kHz. Figure 30
shows the 2-wire interface timing diagram. The master
generates SCL and initiates data transfer on the bus. The
master device writes data to the IC by transmitting the
proper slave address followed by the register address and
then the data word. Each transmit sequence is framed by
a START (S) or REPEATED START (Sr) condition and a
STOP (P) condition. Each word transmitted to the IC is 8
bits long and is followed by an acknowledge clock pulse.
A master reading data from the IC transmits the proper
slave address followed by a series of nine SCL pulses.
The IC transmits data on SDA in sync with the master-
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A mas-
ter initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
CL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 30). A START condition
from the master signals the beginning of a transmission to
the IC. The master terminates transmission, and frees the
bus, by issuing a STOP condition. The bus remains active
if a REPEATED START condition is generated instead of
a STOP condition.
Figure 30. START, STOP, and REPEATED START Conditions
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Digital Input Class D Amplifier
with DHT and Brownout Protection
address is the first byte of information sent to the IC after
the START condition.
Early Stop Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the same
SCL high pulse as the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when in
write mode Figure 31. The IC pulls down SDA during the
entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful
data transfer, the bus master reattempts communication.
The master pulls down SDA during the 9th clock cycle to
acknowledge receipt of data when the IC is in read mode.
An acknowledge is sent by the master after each read
byte to allow data transfer to continue. A not-acknowledge
is sent when the master reads the final byte of data from
the IC, followed by a STOP condition.
Slave Address
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the IC,
the seven most significant bits are programmable through
the ADDR1 and ADDR0 bumps. Setting the read/write bit
to 1 configures the IC for read mode. Setting the read/
write bit to 0 configures the IC for write mode. The slave
Write Data Format
A write to the IC includes transmission of a START con-
dition, the slave address with the R/W bit set to 0, one
byte of data to configure the internal register address
pointer, one or more bytes of data, and a STOP condition.
Figure 32 illustrates the proper frame format for writing
one byte of data to the IC. Figure 33 illustrates the frame
format for writing n-bytes of data to the IC.
Figure 31. Acknowledge
ACKNOWLEDGE FROM SLAVE
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM
ACKNOWLEDGE FROM SLAVE
SLAVE
S
SLAVE ADDRESS
0
A
DATA BYTE
1 BYTE
A
REGISTER ADDRESS
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 32. Writing One Byte of Data to the MAX98372
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM SLAVE
SLAVE ADDRESS
R/W
REGISTER ADDRESS
S
0
A
A
DATA BYTE 1
1 BYTE
A
DATA BYTE n
1 BYTE
A
P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 33. n-Bytes of Data to the MAX98372
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated 9th SCL pulse.
The first byte transmitted from the IC is the content of
register 0x00. Transmitted data is valid on the rising edge
of SCL. The address pointer autoincrements after each
read data byte. This autoincrement feature allows all
registers to be read sequentially within one continuous
frame. A STOP condition can be issued after any number
of read data bytes. If a STOP condition is issued followed
by another read operation, the first data byte to be read is
from register 0x00.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer tells
the IC where to write the next byte of data. An acknowl-
edge pulse is sent by the IC upon receipt of the address
pointer data.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the IC’s slave address
with the R/W bit set to 0 followed by the register address. A
REPEATED START condition is then sent followed by the
slave address with the R/W bit set to 1. The IC then trans-
mits the contents of the specified register. The address
pointer autoincrements after transmitting the first byte.
The third byte sent to the IC contains the data that is writ-
ten to the chosen register. An acknowledge pulse from the
IC signals receipt of the data byte. The address pointer
autoincrements to the next register address after each
received data byte. This autoincrement feature allows a
master to write to sequential registers within one continu-
ous frame. The master signals the end of transmission by
issuing a STOP condition.
The master acknowledges receipt of each read byte during
the acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP condition. Figure 34
illustrates the frame format for reading one byte from
the IC. Figure 35 illustrates the frame format for reading
multiple bytes from the IC.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The IC acknowledges receipt of its slave
address by pulling SDA low during the 9th SCL clock
pulse. A START command followed by a read command
resets the address pointer to register 0x00.
ACKNOWLEDGE FROM
SLAVE
ACKNOWLEDGE FROM
SLAVE
ACKNOWLEDGE FROM
SLAVE
S
SLAVE ADDRESS
REGISTER ADDRESS
A
Sr
SLAVE ADDRESS
R/W
1
A
A
P
DATA BYTE
1 BYTE
0
REPEATED
START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 34. Reading One Byte of Data from the MAX98372
ACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE FROM SLAVE
REGISTER ADDRESS
ACKNOWLEDGE FROM SLAVE
1
A
DATA BYTE
1 BYTE
A P
S
SLAVE ADDRESS
R/W
A
Sr
SLAVE ADDRESS
R/W
0
REPEATED
START
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 35. Reading n-Bytes of Data from the MAX98372
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
2
Use wide, low-resistance output, supply and ground
traces. As load impedance decreases, the current drawn
from the device outputs increase. At higher current, the
resistance of the output traces decreases the power
delivered to the load. For example, if 2W is delivered
from the speaker output to a 4Ω load through a 100mΩ
trace, 49mW is consumed in the trace. If power is deliv-
ered through a 10mΩ trace, only 5mW is consumed in
the trace. Wide output, supply, and ground traces also
improve the power dissipation of the device.
I C Slave Addresses
2
The MAX98372 is configured using the I C control bus.
The addresses effectively allow unique audio endpoint des-
tinations in systems that use multiples of the device. The IC
uses hardware select slave addresses determined by the
configuration of ADDR0, ADDR1 as shown in Table 47. See
2
the I C Serial Interface section for a complete interface
description.
Applications Information
The MAX98372 is inherently designed for excellent RF
immunity. For best performance, add ground fills around
all signal traces on the top and bottom PCB planes.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Use at least 4 PCB layers, and add thermal
vias to the ground/power plane close to the MAX98372
to ensure good thermal performance and high-end out-
put power. Good grounding improves audio performance
and prevents switching noise from coupling into the
audio signal. Ground the power signals and the analog
signals of the IC separately at the system ground plane,
to prevent switching interference from corrupting sensi-
tive analog signals.
The MAX98372 TQFN package features an exposed ther-
mal pad on its underside. Connect the exposed thermal
pad to AGND.
It is generally advisable to follow the layout of the
MAX98372 evaluation kit as closely as is practical in the
application.
Thermal and performance measurements shown in this
data sheet were measured with a 6-layer board with 2
signal layers and 4 ground layers. As a result, the EV kit
performance is likely better than what can be achieved
with a JEDEC standard board.
Place the recommended supply decoupling capacitors as
close as possible to the IC. The PVDD-to-PGND connection
must be kept short and should have minimum trace length
and loop area to ensure optimumal performance.
2
Table 47. ADDR I C Address Select
2
ADDR1
ADDR0
ADDR0 connected to DGND
I C WRITE ADDRESS SELECT
ADDR1 connected to DVDD
ADDR1 connected to DGND
ADDR1 connected to SDA
ADDR1 connected to SCL
ADDR1 connected to DVDD
ADDR1 connected to DGND
ADDR1 connected to SDA
ADDR1 connected to SCL
ADDR1 connected to DVDD
ADDR1 connected to DGND
ADDR1 connected to SDA
ADDR1 connected to SCL
ADDR1 connected to DVDD
ADDR1 connected to DGND
ADDR1 connected to SDA
ADDR1 connected to SCL
0x62
0x64
0x66
0x68
0x6A
0x6C
0x6E
0x70
0x72
0x74
0x76
0x78
0x7A
0x7C
0x7E
0x80
ADDR0 connected to DGND
ADDR0 connected to DGND
ADDR0 connected to DGND
ADDR0 connected to SDA
ADDR0 connected to SDA
ADDR0 connected to SDA
ADDR0 connected to SDA
ADDR0 connected to DVDD
ADDR0 connected to DVDD
ADDR0 connected to DVDD
ADDR0 connected to DVDD
ADDR0 connected to SCL
ADDR0 connected to SCL
ADDR0 connected to SCL
ADDR0 connected to SCL
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Table 48. Recommended External Components
VOLTAGE RATING
DIELECTRIC
(V)
BUMP
VALUE (µF)
SIZE
PVDD
PVDD
PVDD
PVDD
PVDD
10
10
0.1
0.1
220
1
0603
0603
0402
0402
—
50
50
25
25
35
6.3
6.3
—
X5R
X5R
X5R
X5R
Alum-Elec
X5R
V
0201
0201
0201
REFC
DVDD
1
X5R
IRQ
10
—
Shutdown Sequence
1) Set global enable (EN) low.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow temperature
profile, as well as the latest information on reliability test-
ing results, refer to the Application Note 1891: Wafer-Level
Packaging (WLP) and Its Applications. The recommended
PCB pad size is 0.23mm.
2) Remove digital audio (PCM) clocks.
3) Apply logic-low signal to RESET pin.
4) Remove power from PVDD and DVDD pins.
Startup Sequence
1) Apply the nominal voltage to the DVDD and PVDD pins.
2) Apply logic-high to the RESET pin and wait at least
2
500µs for I C communication to become available.
3) Program the device to the desired mode of operation.
• Program the digital audio interface inputs and outputs.
• Program the speaker output amplifier gain and set
SPK_EN (this bit must only be toggled when EN is low).
• Program the PVDD and thermal ADC.
• Program the DHT and thermal foldback.
• Set global enable (EN) high.
Figure 36. MAX98372+ WLP Ball Dimensions
4) Digital audio data (PCM) can be applied to the IC
before or after the global enable is set high.
• When applying an audio signal to an active IC, the
signal should be ramped.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Typical Application Circuit
1.14V TO 1.98V
5.5V TO 18V
1μF
1μF
0.1μF
10μF
10μF
0.1μF
220μF
10kΩ 10kΩ 10kΩ
PVDD
V
REFC
DVDD
SDA
SCL
CONTROL
OUTP SNS
OUTP
INTERFACE
IRQ
ADDR1
REFER TO
APPLICATION
ADDR2
INFORMATION
MAX98372
RESET
OUTN
BCLK
LRCLK
OUTN SNS
DIGITAL
AUDIO
DIN
INTERFACE
DOUT
AGND
DGND
PGND
Ordering Information
PART
MAX98372EWV+
MAX98372EWV+T
MAX98372ETJ+
MAX98372ETJ+T
TEMP RANGE PIN-PACKAGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
30 WLP
30 WLP
32 TQFN
32 TQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
LAND
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
PATTERN NO.
Refer to Application Note 1891
90-0012
30 WLP
W302G2+1
T3255+4C
21-100002
21-0140
32 TQFN
Pin 1
Indicator
see Note 7
Marking
E
COMMON DIMENSIONS
1
A
0.05
0.03
0.64
0.19
A
A1
A2
0.45 REF
AAAA
D
A3
b
BASIC
0.040
0.27
0.03
0.025
0.025
BASIC
BASIC
D
2.207
2.797
E
TOP VIEW
SIDE VIEW
D1
E1
1.60
2.00
A3
e
0.40 BASIC
0.00 BASIC
0.20 BASIC
SD
SE
A1
A
A2
DEPOPULATED BUMPS:
NONE
0.05
S
S
FRONT VIEW
E1
SE
e
NOTES:
1. Terminal pitch is defined by terminal center to center value.
2. Outer dimension is defined by center lines between scribe lines.
3. All dimensions in millimeter.
E
D
C
B
B
SD
4. Marking shown is for package orientation reference only.
5. Tolerance is ± 0.02 unless specified otherwise.
D1
M
6. All dimensions apply to PbFree (+) package codes only.
7. Front - side finish can be either Black or Clear.
A
1
2
3 4 5 6
maxim
b
0.05
TM
integrated
S
A
AB
TITLE
PACKAGE OUTLINE 30 BUMPS
BOTTOM VIEW
WLP PKG. 0.4 mm PITCH, W302G2+1
REV.
APPROVAL
DOCUMENT CO2NT1RO-L1N0O.0002
1
- DRAWING NOT TO SCALE -
A
1
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
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MAX98372
Digital Input Class D Amplifier
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Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”,
or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
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MAX98372
Digital Input Class D Amplifier
with DHT and Brownout Protection
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
9/15
Initial release
—
Updated Electrical Characteristics table DIN Frame Delay after LRCLK Edge parameter,
replaced Figure 7
1
2
1/16
2/17
12, 48
Added TQFN package information to Absolute Maximum Ratings and Package
Information sections (including package outline drawings), updated Tables 1, 3─6,
9, 24, 26─30, 33, 42─44, added four new figures (Figure 24─Figure 27), added
Startup Sequence and Shutdown Sequence sections, added MAX98372ETJ+ and
MAX98372ETJ+T in Ordering Information table
8, 29,
43─45, 51,
66, 72─75,
83─86, 88,
93─99
3
4
8/17
3/20
Updated Electrical Characteristics table with current limit specs for different packages
11
Updated Bump/Pin Configurations diagram, Bump/Pin Description table, Layout and
Grounding section
24, 25, 92
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shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
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