MAX9850_V01 [MAXIM]
Stereo Audio DAC with DirectDrive Headphone Amplifier;
| 型号： | MAX9850_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Stereo Audio DAC with DirectDrive Headphone Amplifier |
| 文件： | 总36页 (文件大小：3658K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
General Description
Features
● 1.8V to 3.6V Single-Supply Operation
The MAX9850 is a low-power, high-performance stereo
audio DAC with an integrated DirectDrive headphone
amplifier. The MAX9850 is designed to meet the board
space and performance requirements of portable devices
such as cell phones and MP3 and portable DVD players.
● 30mW Stereo Headphone Output Power with
1.8V Supply
● DirectDrive Outputs Eliminate DC-Blocking
Capacitors
The MAX9850 uses Maxim’s DirectDrive headphone
technology that produces a ground-biased analog audio
output from a single supply, which allows for driving the
headphones directly from the amplifier outputs without large
DC-blocking capacitors. This feature saves board space,
provides higher click/pop suppression, and improves
low-frequency (bass) response. The architecture does not
require the headphone jack to be biased to a DC voltage
and thus allows for a conventional, grounded chassis
design.
● 91dB PSRR at 1kHz
● Any Master Clock Up to 40MHz
2
● Flexible I S-Compatible Digital Audio Interface
2
● I C Headphone Volume and Mute Control
● Stereo Line Inputs and Outputs
● Clickless/Popless Operation
2
● 2-Wire (I C)-Compatible Control Interface
● Available in 28-Pin Thin QFN Package
The MAX9850’s flexible clocking circuitry utilizes any available
system clock up to 40MHz, eliminating the need for an
external PLL and multiple crystal oscillators. The DAC
supports a wide range of sample rates from 8kHz to 48kHz
in both master and slave modes, making the MAX9850 the
easiest to use and most versatile audio DAC available. It
can also be operated like traditional synchronous DACs, at
any integer-oversampling ratio.
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
MAX9850ETI+ -40°C to +85°C 28 TQFN-EP** T2855+
**EP = Exposed pad.
+Denotes lead-free package.
The audio DAC receives input data over a flexible
3-wire interface that supports left-justified, right-
justified audio data, or I S-compatible audio data. Stereo
Pin Configuration appears at end of data sheet.
2
audio line inputs are provided to either mix analog audio
with the digital input stream, or to drive the headphone
outputs directly. Mode settings, headphone amplifier
volume controls, and shutdown for both the headphone
and line outputs are programmed through a 2-wire,
Block Diagram
MCLK
1.8V TO 3.6V
INR
2
I C-compatible interface.
DIGITAL
PLL
OUTR
HPR
LINE
OUT
MAX9850
The MAX9850 is fully specified over the -40°C to +85°C
extended temperature range and is available in a low-
profile, 28-pin thin QFN package (5mm x 5mm x 0.8mm).
DAC
SDIN
BCLK
LRCLK
DIGITAL
AUDIO
HPL
Applications
DAC
●ꢀ MP3/Portable Multimedia Players
●ꢀ Cell Phones/Smart Phones
●ꢀ Portable DVD Players
SDA
SCL
ADD
GPIO
OUTL
LINE
OUT
2
I C
INL
19-3454; Rev 4; 8/19
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Absolute Maximum Ratings
(Voltages with respect to AGND.)
OUTL, OUTR..........................(NREG - 0.3V) to (PREG + 0.3V)
DV , AV , PV
................................................-0.3V to +4V
C1N ......................................... (PV - 0.3V) to (PGND + 0.3V)
DD
DD
DD
DD
SS
AV
Referenced to PV ..................................-0.3V to +0.3V
C1P..........................................(PGND - 0.3V) to (PV
+ 0.3V)
DD
DD
SV , PV ............................................................-4V to +0.3V
Current Into/Out of Any Pin..............................................100mA
Duration of HPL, HPR, OUTL,
SS
SS
SV Referenced to PV ...................................-0.3V to +0.3V
SS
SS
DGND, PGND ......................................................-0.3V to +0.3V
OUTR Short Circuit to AGND................................Continuous
BCLK, LRCLK, HPS, SDIN ....................-0.3V to (DV + 0.3V)
Continuous Power Dissipation (T = +70°C)
DD
A
GPIO, MCLK ...........................................................-0.3V to +4V
28-Pin Thin QFN (derate 35.7mW/°C above +70°C)...2857mW
Junction Temperature......................................................+150°C
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
REF, PREG ............................................-0.3V to (AV + 0.3V)
DD
NREG .....................................................+0.3V to (SV - 0.3V)
SS
SDA, SCL, ADD.......................................................-0.3V to +4V
INL, INR......................................................................-2V to +2V
HPR, HPL................................. (SV - 0.3V) to (AV
+ 0.3V)
SS
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μFꢀtoꢀAGND,ꢀ
DD
DD
DD
NREG
PREG
REF
R
ꢀ=ꢀ32ΩꢀtoꢀAGND,ꢀR
ꢀ=ꢀ10kΩꢀtoꢀAGND,ꢀf
= 48kHz, f
= 12.288MHz, volume set to -9.5dB, T = T
to
MIN
LOAD_HP
LOAD_OUT
LRCLK
MCLK
A
T
, unless otherwise noted. Typical specifications at T = +25°C, unless otherwise noted.) (Note 1)
A
MAX
PARAMETER
SYMBOL
AV
CONDITIONS
MIN
1.8
TYP
MAX
UNITS
,
DD
Analog Supply Voltage
Digital Supply Voltage
AV
= PV
3.6
V
V
DD
DD
PV
DD
DV
1.8
3.6
7.7
DD
AV
AV
AV
AV
= 1.8V
= 3.0V
= 1.8V
= 3.0V
= 1.8V
= 3.0V
5.5
5.9
3.5
3.75
2.1
3.8
1.5
0.3
Full operation (Note 2), no
headphone or line output load
DD
DD
DD
DD
Analog Supply Current
AI
DI
mA
DD
5.3
2.9
Full operation (Note 2),
headphones disabled
DV
DV
Full operation (Note 2),
no line output load
DD
DD
Digital Supply Current
mA
DD
Analog Shutdown Current
Digital Shutdown Current
AI
DI
I
+ I
, A
= P = 1.8V
VDD
10
5
µA
µA
SHDN
AVDD
PVDD VDD
Static digital interface, D
= 1.8V
SHDN
VDD
Shutdown to Full Operation
(Note 2)
t
1.3
1.4
ms
ms
ON
Power-On to Full Operation
(Note 2)
t
PON
DAC PERFORMANCE/LINE OUTPUTS (Note 3)
0dBFS Output Voltage
V
1.85
82
1.95
87.5
87.5
88
2.05
V
P-P
OUT_FS
AV
AV
= 3.0V
= 1.8V
DD
Dynamic Range (Note 4)
DR
dB
DD
Unweighted
A-weighted
91
Signal-to-Noise Ratio
(Note 5)
SNR
dB
AV
= 1.8V, unweighted
88
DD
DD
AV
= 1.8V, A-weighted
91
Maxim Integrated
│ 2
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Electrical Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μFꢀtoꢀAGND,ꢀ
DD
DD
DD
NREG
PREG
REF
R
ꢀ=ꢀ32ΩꢀtoꢀAGND,ꢀR
ꢀ=ꢀ10kΩꢀtoꢀAGND,ꢀf
= 48kHz, f
= 12.288MHz, volume set to -9.5dB, T = T
to
MIN
LOAD_HP
LOAD_OUT
LRCLK
MCLK
A
T
, unless otherwise noted. Typical specifications at T = +25°C, unless otherwise noted.) (Note 1)
A
MAX
PARAMETER
SYMBOL
CONDITIONS
0dBFS
-60dBFS
AV = 1.8V,
MIN
TYP
87
MAX
UNITS
27.5
Total Harmonic Distortion Plus
Noise
DD
THD+N
f
= 984.375Hz
dB
IN
-81
0dBFS
AV = 1.8V,
-60dBFS
DD
-27.5
0
-22
Line Output Offset Voltage
V
-15
+15
mV
dB
OS_LINE
Channel-to-Channel Gain
Matching
ΔAV/AV
OUTL to OUTR, OUTR to OUTL
= 100mV , f = 1kHz,
±0.04
V
RIPPLE
P-P IN
87
67
applied to AV
and PV
DD
DD
Power-Supply Rejection Ratio
PSRR
dB
dB
V
= 100mV , f = 20kHz,
P-P IN
RIPPLE
applied to AV
and PV
DD
DD
f
= 1kHz, V
= 2V
OUT
OUT P-P
Crosstalk
XTALK
-105
(OUTL to OUTR) or (OUTR to OUTL)
Sampling Frequency Range
MCLK Frequency
f
8
48
40
kHz
S
f
8.448
MHz
MCLK
DAC 8x INTERPOLATION FILTER
Passband Frequency
Frequency Response
Stopband Attenuation
Stopband Frequency
LINE INPUTS (INL, INR)
Line Input Voltage
PB
FR
To -1dB corner
10Hz to 20kHz
0
-0.1
0.48 x f
+0.1
kHz
dB
S
SBA
SB
58
dB
Attenuation greater than SBA
0.58 x f
7.42 x f
kHz
S
S
V
-1
-1.05
-15
+1
V
IN_LINE
IN_ to OUT_ Gain
A
-1
0
-0.95
+15
V/V
mV
kΩ
V_LINE
Line Input Bias Voltage
V
BIAS_LINE
INL and INR Input Resistance
R
10
22
IN_LINE
INTERNAL REGULATORS (NREG, PREG)
PREG Output Voltage
NREG Output Voltage
REF Output Voltage
V
V
1.60
-1.15
1.23
V
V
V
PREG
NREG
V
REF
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│ 3
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Electrical Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μFꢀtoꢀAGND,ꢀ
DD
DD
DD
NREG
PREG
REF
R
ꢀ=ꢀ32ΩꢀtoꢀAGND,ꢀR
ꢀ=ꢀ10kΩꢀtoꢀAGND,ꢀf
= 48kHz, f
= 12.288MHz, volume set to -9.5dB, T = T
to
MIN
LOAD_HP
LOAD_OUT
LRCLK
MCLK
A
T
, unless otherwise noted. Typical specifications at T = +25°C, unless otherwise noted.) (Note 1)
A
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HEADPHONE OUTPUTS (HPL, HPR)
R =ꢀ16Ω
L
95
65
AV
= 3.0V
DD
R =ꢀ32Ω
L
40
THD+N = 1%
= 1kHz, headphone
volume = +6dB
AV
= 3.0V
DD
Output Power
OUT
f
mW
IN
R =ꢀ16Ω
L
30
AV
= 1.8V
DD
R =ꢀ32Ω
L
15
25
AV
= 1.8V
DD
Full-Scale Headphone Amplifier
Output Voltage
V
Volume = +5dB, HP unloaded
Volume = +3dB, HP unloaded
1.16
1.34
1.23
1.41
1.30
1.48
V
RMS
OUT_FS
Line In to HP Output Voltage
Gain
A
V/V
dB
V_HP
R =ꢀ32Ω,ꢀP
= 60mW, f = 1kHz
-94
-90
88
90
88
91
L
OUT
IN
Total Harmonic Distortion Plus
Noise
THD+N
SNR
R =ꢀ16Ω,ꢀP
= 60mW, f = 1kHz
IN
L
OUT
Unweighted
A-weighted
Signal-to-Noise Ratio (Note 6)
Power-Supply Rejection Ratio
dB
AV
AV
= 1.8V, unweighted
= 1.8V, A-weighted
DD
DD
V
= 100mV , frequency = 1kHz,
P-P
RIPPLE
91
72
applied to AV
and PV
DD
DD
PSRR
dB
V
= 100mV , frequency = 20kHz,
P-P
RIPPLE
applied to AV
and PV
DD
DD
T = +25°C
-15
-25
+15
+25
A
Headphone Output Offset
Voltage
V
Volume = -11.5dB
mV
OS_HP
SR
T = T
to T
MAX
A
MIN
Slew Rate
0.47
150
V/µs
pF
Maximum Capacitive Load
C
No sustained oscillations
ꢀ=ꢀ32Ω,ꢀP = 3.5mW, f = 1kHz
L
R
HP
OUT IN
Crosstalk
XTALK
-85
±0.05
667
dB
dB
(HPL to HPR) or (HPR to HPL)
Channel-to-Channel Gain
Matching
ΔA /A
V
V
Internal Charge-Pump
Oscillator Frequency
f
550
775
kHz
CP
Charge-Pump Operating
Frequency Range
Charge-pump clock derived from MCLK
550
775
kHz
dB
Volume Control Range
-73.5
+6.0
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Electrical Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μFꢀtoꢀAGND,ꢀ
DD
DD
DD
NREG
PREG
REF
R
ꢀ=ꢀ32ΩꢀtoꢀAGND,ꢀR
ꢀ=ꢀ10kΩꢀtoꢀAGND,ꢀf
= 48kHz, f
= 12.288MHz, volume set to -9.5dB, T = T
to
MIN
LOAD_HP
LOAD_OUT
LRCLK
MCLK
A
T
, unless otherwise noted. Typical specifications at T = +25°C, unless otherwise noted.) (Note 1)
A
MAX
PARAMETER
Mute Attenuation
DIGITAL INPUTS (GPIO, SCL, SDA, BCLK, LRCLK, SDIN, ADD, MCLK)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
100
dB
0.8 x
Input High Voltage
V
V
IH
DV
DD
0.2 x
Input Low Voltage
Input Leakage Current
Input Hysteresis
V
V
µA
V
IL
DV
DD
I
, I
V
= DV , V = DGND
-10
+10
IH IL
IH
DD IL
0.09 x
DV
DD
Input Capacitance
C
10
pF
IN
OPEN-DRAIN DIGITAL OUTPUTS (GPIO, SDA)
Output-High Leakage Current
I
V
= DV (Note 7)
DD
1
µA
V
OH
OH
DV
DV
> 2V
< 2V
0.4
DD
DD
Output Low Voltage
V
I
= 3mA
OL
OL
0.2 x
DV
DD
CMOS DIGITAL OUTPUTS (BCLK, LRCLK)
DV
0.4
-
DD
Output High Voltage
V
I
I
= 1mA
= 1mA
V
V
OH
OH
OL
Output Low Voltage
V
0.4
OL
HEADPHONE SENSE INPUT (HPS)
0.7 x
DV
Input High Voltage
Input Low Voltage
V
V
V
IH
DD
0.25 x
DV
V
IL
DD
Full shutdown, V = DV
400
IH
DD
Input-High Leakage Current
I
µA
IH
Normal operation, V = DV
1
1
IH
DD
Full shutdown, V = DGND
IL
Input-Low Leakage Current
Input Hysteresis
I
µA
V
IL
Normal operation, V = DGND
100
IL
0.05 x
DV
DD
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Electrical Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μFꢀtoꢀAGND,ꢀ
DD
DD
DD
NREG
PREG
REF
R
ꢀ=ꢀ32ΩꢀtoꢀAGND,ꢀR
ꢀ=ꢀ10kΩꢀtoꢀAGND,ꢀf
= 48kHz, f
= 12.288MHz, volume set to -9.5dB, T = T
to
MIN
LOAD_HP
LOAD_OUT
LRCLK
MCLK
A
T
, unless otherwise noted. Typical specifications at T = +25°C, unless otherwise noted.) (Note 1)
A
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C TIMING
Serial Clock Frequency
f
0
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
Hold Time (Repeated) START
Condition
t
t
0.6
µs
HD, STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Repeated START Condition
Setup Time
0.6
µs
SU, STA
Data Hold Time
Data Setup Time
Bus Capacitance
t
0
900
ns
ns
pF
HD, DAT
t
100
SU, DAT
C
400
300
B
SDA and SCL Receiving Rise
Time (Note 8)
t
20 + 0.1C
20 + 0.1C
ns
ns
R
B
SDA and SCL Receiving Fall
Time (Note 8)
t
300
F
B
DV
DV
= 1.8V, T = +25°C
20 + 0.1C
20 + 0.5C
0.6
250
250
DD
DD
A
B
SDA Transmitting Fall Time
(Note 8)
t
ns
F
= 3.6V, T = +25°C
A
B
Setup Time for STOP Condition
Pulse Width of Suppressed Spike
DIGITAL AUDIO TIMING
t
µs
ns
SU, STO
t
0
50
SP
BCLK Period (Note 9)
t
3 x 1/f
ns
ns
ns
ns
BCLK
ICLK
Low or High BCLK Pulse Width
BCLK and LRCLK Rise Time
BCLK and LRCLK Fall Time
t
0.35 x t
BCLK
BCLK_PW
t
Master mode, C
Master mode, C
= 15pF
= 15pF
1
1
R
LOAD
LOAD
t
F
SDIN or LRCLK to BCLK Rising
Setup Time
t
t
,
DBSU
30
ns
ns
BWSU
DV
DV
= 1.8V
= 3.6V
0
5
DD
DD
SDIN or LRCLK to BCLK Rising
Hold Time
t
,
DBH
t
BWBH
Note 1: The MAX9850 is 100% production tested at T = +25°C and is guaranteed by design for T = T
to T
.
MAX
A
A
MIN
Note 2: Full operation is defined as clocking all zeros into the DAC while the DAC, headphone outputs, and line outputs are all
enabled.
Note 3: DAC performance specifications measured using the line outputs, OUTL and OUTR.
Note 4: Dynamic range is defined as the SNR of a 1kHz, -60dBFS input signal measured with an A-weighted filter, then normalized
to full scale (+60dB).
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│ 6
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Note 5: DAC SNR measured from DAC inputs to OUTL and OUTR.
Note 6: Headphone amplifier SNR measured from line inputs to headphone outputs.
Note 7: GPIOꢀisꢀ100kΩꢀtoꢀgroundꢀwhenꢀDV < V < 3.6V.
DD
OH
Note 8:
Note 9:
C is in pF.
B
f
derived by dividing f
by 1, 2, 3, or 4. See the Registers and Bit Descriptions section.
MCLK
ICLK
Typical Power Dissipation at AV
= 1.8V (No Headphone/Line Output Load)
DD
MODE
AV
POWER
DV
POWER
PV POWER
DD
TOTAL POWER
13.70mW
DD
DD
Full Operation (Note 1)
4.93mW
3.11mW
3.76mW
3.76mW
5.00mW
3.22mW
DAC to Line Outputs, Headphones Disabled
10.10mW
Line Inputs to Line Outputs and Headphone
Outputs, DAC Disabled
3.22mW
0.085mW
3.40mW
6.71mW
Line Inputs to Line Outputs, DAC and
Headphones Disabled
1.39mW
2.7µW
0.085mW
0.5µW
1.61mW
<0.1µW
3.08mW
3.2µW
Full Shutdown
Typical Operating Characteristics
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μF,ꢀf = 48kHz,
REF S
DD
DD
DD
NREG
PREG
f
= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, T = +25°C, unless otherwise
MCLK
A
noted. f = 984.375Hz, A-weighted THD+N.)
IN
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
(LINE IN TO HP) vs. POWER OUT
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. POWER OUT
(DAC TO HP) vs. POWER OUT
10
10
10
AV = 1.8V
DD
AV = 1.8V
DD
AV = 1.8V
DD
R = 16Ω
L
R = 16Ω
L
R = 32Ω
L
f
= 1kHz
IN
f
= 1kHz
IN
1
1
0.1
1
f
= 1kHz
IN
f
= 10kHz
IN
0.1
0.01
0.1
f
= 10kHz
IN
f
= 20Hz
IN
0.01
0.001
0.01
0.001
f
= 20Hz
IN
f
= 10kHz
20
IN
f
= 20Hz
20
IN
0.001
0
10
30
40
50
60
0
10
20
30
40
50
60
0
10
30
40
50
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
Maxim Integrated
│ 7
www.maximintegrated.com
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Typical Operating Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μF,ꢀf = 48kHz,
REF S
DD
DD
DD
NREG
PREG
f
= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, T = +25°C, unless otherwise
MCLK
A
noted. f = 984.375Hz, A-weighted THD+N.)
IN
TOTAL HARMONIC DISTORTION PLUS NOISE
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. POWER OUT
TOTAL HARMONIC DISTORTION PLUS NOISE
(LINE IN TO HP) vs. POWER OUT
(LINE IN TO HP) vs. POWER OUT
10
10
10
AV = 1.8V
DD
AV = 3.0V
DD
AV = 3.0V
DD
R = 32Ω
L
R = 16Ω
L
R = 16Ω
L
f
= 1kHz
IN
1
1
0.1
1
f
= 1kHz
IN
f
= 1kHz
f = 20Hz
IN
IN
0.1
0.1
f
= 10kHz
IN
f
= 10kHz
IN
f
= 10kHz
IN
0.01
0.001
0.01
0.01
f
IN
= 20Hz
60
f
IN
= 20Hz
40
0.001
0.001
0
10
20
30
50
0
20
40
80
100
0
20
40
60
80
100
POWER OUT (mW)
POWER OUT (mW)
POWER OUT (mW)
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. POWER OUT
TOTAL HARMONIC DISTORTION PLUS NOISE
(LINE IN TO HP) vs. POWER OUT
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. FREQUENCY
10
10
10
AV = 3.0V
DD
AV = 3.0V
DD
AV = 1.8V
DD
R
L
= 32Ω
R = 32Ω
L
R
L
= 16Ω
1
1
1
f
= 1kHz
IN
f
= 10kHz
IN
P
OUT
= 5mW
0.1
0.1
0.1
f
= 1kHz
IN
f
= 10kHz
IN
f
= 20Hz
IN
0.01
0.001
0.01
0.01
P
OUT
= 21mW
f
= 20Hz
IN
0.001
0.001
0
20
40
60
80
100
0
20
40
60
80
100
10
100
1k
10k
100k
POWER OUT (mW)
POWER OUT (mW)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO LINE OUT) vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. FREQUENCY
10
10
10
AV = 1.8V
DD
AV = 1.8V TO 3.0V
DD
AV = 3.0V
DD
R = 32Ω
L
R = 10kΩ
L
R = 16Ω
L
1
1
1
P
= 10mW
OUT
P
= 3mW
OUT
0.1
0.1
0.1
0.01
V
= 2V
0.01
0.01
OUT
P-P
1k
P
= 60mW
1k
OUT
P
= 15mW
1k
OUT
0.001
0.001
0.001
10
100
10k
100k
10
100
10k
100k
10
100
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Maxim Integrated
│ 8
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Typical Operating Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μF,ꢀf = 48kHz,
REF S
DD
DD
DD
NREG
PREG
f
= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, T = +25°C, unless otherwise
MCLK
A
noted. f = 984.375Hz, A-weighted THD+N.)
IN
POWER DISSIPATION
vs. POWER OUT
POWER DISSIPATION
vs. POWER OUT
TOTAL HARMONIC DISTORTION PLUS NOISE
(DAC TO HP) vs. FREQUENCY
10
160
140
120
100
80
350
300
250
200
150
100
50
AV = PV = DV = 1.8V
AV = PV = DV = 3.0V
DD DD DD
AV = 3.0V
DD
R = 32Ω
L
DD
DD
DD
P
OUT
= P
+ P
P
OUT
= P
+ P
HPR HPL
HPR
HPL
1
R
LOAD
= 16Ω
R
LOAD
= 16Ω
P
OUT
= 6mW
0.1
60
40
0.01
R
LOAD
= 32Ω
R
LOAD
= 32Ω
P
OUT
= 50mW
10k
20
0.001
0
0
10
100
1k
100k
0
10
20
30
40
0
50
100
150
FREQUENCY (Hz)
POWER OUT (mW)
POWER OUT (mW)
POWER OUT
POWER OUT
POWER OUT
vs. HEADPHONE LOAD
vs. HEADPHONE LOAD
vs. SUPPLY VOLTAGE
50
140
120
100
80
180
160
140
120
100
80
AV = 3.0V
DD
LINE IN TO HP OUT
R = 16Ω
L
LINE IN TO HP OUT
f = 1kHz
IN
AV = 1.8V
DD
45
40
35
30
25
20
15
10
5
LINE IN TO HP OUT
= 1kHz
f
IN
= 1kHz
f
IN
THD+N = 10%
THD+N = 10%
THD+N = 10%
60
THD+N = 1%
THD+N = 1%
60
THD+N = 1%
40
40
20
20
0
0
0
10
100
1000
10
100
1000
1.0
1.5
2.0
2.5
3.0
3.5
4.0
R
LOAD
(Ω)
R
LOAD
(Ω)
SUPPLY VOLTAGE (V)
POWER OUT
vs. SUPPLY VOLTAGE
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HP)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO LINE OUT)
0
-10
0
-10
100
90
80
70
60
50
40
30
20
10
0
R
= 10kΩ
APPLIED TO
R
= 32Ω
LOAD
L
R
= 10kΩ
APPLIED TO
LOAD
V
LINE IN TO HP OUT
= 1kHz
RIPPLE
V
RIPPLE
-20
-20
AV AND PV = 100mV
CLOCKING ZEROS INTO DAC
VOLUME SET AT -9.5dB
f
DD
DD
P-P
IN
AV AND PV = 100mV
CLOCKING ZEROS INTO DAC
DD
DD
P-P
-30
-30
-40
-40
THD+N = 10%
-50
-50
-60
-60
THD+N = 1%
-70
-70
AV = 1.8VDC
DD
AV = 3.0VDC
DD
-80
-80
-90
-90
AV = 3.0VDC
DD
-100
-110
-120
-100
-110
-120
AV = 1.8VDC
DD
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10
100
1k
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
Maxim Integrated
│ 9
www.maximintegrated.com
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Typical Operating Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μF,ꢀf = 48kHz,
REF S
DD
DD
DD
NREG
PREG
f
= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, T = +25°C, unless otherwise
MCLK
A
noted. f = 984.375Hz, A-weighted THD+N.)
IN
CROSSTALK vs. FREQUENCY
(DAC IN TO HP OUT)
CROSSTALK vs. FREQUENCY
(LINE IN TO HP OUT)
CROSSTALK vs. FREQUENCY
(DAC IN TO LINE OUT)
-40
-40
-50
-40
-50
VOLUME SET TO -9.5dB
DAC IN = 0dBFS
VOLUME SET TO -9.5dB
DAC IN = 0dBFS
VOLUME SET TO -9.5dB
-50
-60
LINE IN = 1V
RMS
R
LOAD
= 32Ω
R
LOAD
= 32Ω
-60
-60
L TO R
L TO R
-70
-70
-70
-80
-80
-80
-90
-90
-90
L TO R
R TO L
R TO L
-100
-110
-120
-100
-110
-120
-100
-110
-120
R TO L
10
100
1k
10k
100k
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, SLAVE NONINTEGER MODE
(DAC IN = 0dBFS)
FFT, SLAVE NONINTEGER MODE
(DAC IN = -60dBFS)
FFT, SLAVE NONINTEGER MODE
(DAC IN = IDLE)
0
0
0
LINE OUT
LINE OUT
LINE OUT
f
= 1kHz
IN
f
f
= 1kHz
= 12MHz
IN
MCLK
-20
-40
-20
-40
-20
-40
f
= 12MHz
MCLK
f
= 12MHz
MCLK
-60
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-140
-100
-120
-140
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (kHz)
15
20
0
5
10
FREQUENCY (Hz)
15
20
FFT, MASTER INTEGER MODE
(DAC IN = 0dBFS)
FFT, MASTER INTEGER MODE
(DAC IN = -60dBFS)
FFT, MASTER INTEGER MODE
(DAC IN = IDLE)
0
-20
0
-20
0
-20
LINE OUT
= 12.288MHz
LINE OUT
LINE OUT
f
MCLK
f
f
= 1kHz
= 12.288MHz
f
f
= 1kHz
= 12.288MHz
IN
MCLK
IN
MCLK
-40
-40
-40
-60
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-140
-100
-120
-140
0
5
10
15
20
0
5
10
FREQUENCY (Hz)
15
20
0
5
10
FREQUENCY (Hz)
15
20
FREQUENCY (Hz)
Maxim Integrated
│ 10
www.maximintegrated.com
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Typical Operating Characteristics (continued)
(DV
= AV
= PV ꢀ=ꢀ3.0V,ꢀAGNDꢀ=ꢀDGNDꢀ=ꢀPGNDꢀ=ꢀ0V,ꢀC1ꢀ=ꢀ0.47μF,ꢀC2ꢀ=ꢀ2.2μF,ꢀC
= C
= C
ꢀ=ꢀ1μF,ꢀf = 48kHz,
REF S
DD
DD
DD
NREG
PREG
f
= 12.288MHz, master integer mode, headphone volume set to +6dB, both channels driven in-phase, T = +25°C, unless otherwise
MCLK
A
noted. f = 984.375Hz, A-weighted THD+N.)
IN
GAIN FLATNESS
SNR vs. MCLK FREQUENCY
vs. FREQUENCY
WIDEBAND FFT
1.0
20
0
100
DAC IN = 0dBFS
DAC IN TO LINE OUT
= 1kHz
R
= 32Ω
f
= f
/ 3
f
= f
/ 1
LOAD
ICLK MCLK
ICLK MCLK
0.8
0.6
0.4
0.2
0
DAC IN TO HP
DAC IN = 0dBFS
95
90
85
80
75
70
65
60
f
IN
-20
-40
f
/ 2
ICLK MCLK
= f
/ 4
f
= f
ICLK MCLK
-60
-0.2
-0.4
-0.6
-0.8
-1.0
-80
SLAVE NONINTEGER MODE
DAC IN = -60dBFS
-100
-120
-140
f
= 32kHz, 44.1kHz, 48kHz
LRCLK
AV = 3.0V
DD
10
100
1k
10k
100k
10
100
1k
10k
100k
5
10
15
20
25
30
35
40
FREQUENCY (Hz)
MCLK FREQUENCY (MHz)
FREQUENCY (Hz)
OUTPUT POWER
vs. TEMPERATURE
GROUP DELAY
WIDEBAND FFT
20
0
60
55
50
45
40
35
30
25
20
15
10
5
40
DAC IN = -60dBFS
DAC IN TO LINE OUT
= 1kHz
AV = 1.8V
DD
THD+N = 1%
LRCLK = 48kHz
MCLK = 7.68MHz
INTEGER MODE,
HEADPHONE STEREO MODE
35
30
25
20
15
10
f
IN
R
LOAD
= 16Ω
-20
-40
R
LOAD
= 32Ω
-60
-80
-100
-120
-140
0
10
100
1k
10k
100k
10
100
1000
10000
-40
-15
10
35
60
85
FREQUENCY (Hz)
FREQUENCY (Hz)
TEMPERATURE (°C)
AV AND PV SUPPLY CURRENT
DIGITAL SUPPLY CURRENT
vs. DV
DD
DD
vs. AV AND PV SUPPLY VOLTAGE
DD
DD
DD
10
9
10
9
8
7
6
5
4
3
2
1
0
8
T
= +85°C
A
7
6
T
A
= +85°C, +25°C, -40°C
5
4
T
A
= +25°C
T
A
= -40°C
3
2
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
AV AND PV (V)
1.0
1.5
2.0
2.5
DV (V)
3.0
3.5
4.0
DD
DD
DD
Maxim Integrated
│ 11
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Pin Description
PIN
NAME
FUNCTION
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clock and determines
whether the audio data on SDIN is routed to the left or right channel. LRCLK is an input when the
MAX9850 is in slave mode and an output when in master mode.
1
LRCLK
Digital Audio Bit Clock Input/Output. BCLK is an input when the MAX9850 is in slave mode
and an output when in master mode.
2
BCLK
SDIN
3
4
5
6
Digital Audio Serial Data Input
DV
Digital Power-Supply Input. Bypass to DGND with a 1µF ceramic capacitor.
Master Clock Input. All internal digital clocks are derived from MCLK.
DD
MCLK
DGND
Digital Ground
2
I C Address-Select Input. Connect to AGND, AV , or SDA to select one of the three possible
DD
7
8
ADD
2
I C addresses.
General-Purpose Input/Output. Configure GPIO as an input or an output through the GPIO register.
GPIO can perform the function of an interrupt when configured as an output. See the GPIO section.
GPIO
9
INR
INL
Right-Channel Line Input. INR is mixed with the right DAC output.
Left-Channel Line Input. INL is mixed with the left DAC output.
Line Level Right-Channel Output. OUTR is biased at AGND.
Line Level Left-Channel Output. OUTL is biased at AGND.
10
11
12
13
14
15
16
17
18
19
20
OUTR
OUTL
REF
Reference Output. Bypass to AGND with a 1µF ceramic capacitor.
Analog Ground
AGND
NREG
PREG
Line Output Negative Regulator Output. Bypass to AGND with a 1µF capacitor.
Line Output Positive Regulator Output. Bypass to AGND with a 1µF capacitor.
Analog Power Supply. Bypass to AGND with a 1µF ceramic capacitor.
Right-Channel Headphone Output. HPR is a DirectDrive output biased at AGND.
Left-Channel Headphone Output. HPL is a DirectDrive output biased at AGND.
AV
DD
HPR
HPL
SV
Headphone Amplifier Negative Power-Supply Input. Connect to PV
.
SS
SS
Headphone Sense Input. Connect to the control pin of a headphone jack for automatic headphone
sensing. Float HPS if unused. See the Headphone Sense Input (HPS) section.
21
22
HPS
PV
Inverting Charge-Pump Output. Bypass to PGND with a 2.2µF ceramic capacitor and connect to
SV to provide the headphone amplifiers with a negative supply.
SS
SS
Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.47µF ceramic capacitor between
C1N and C1P.
23
24
25
C1N
PGND
C1P
Charge-Pump Ground
Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.47µF ceramic capacitor
between C1P and C1N.
Charge-Pump and Headphone Amplifier Positive Power-Supply Input. Bypass to PGND
26
PV
DD
with a 1µF ceramic capacitor. Connect to AV
for normal operation.
DD
2
27
28
—
SCL
SDA
EP
I C-Compatible Serial Clock Input
2
I C-Compatible Serial Data Input/Output
Exposed Thermal Pad. Connect EP to AGND.
Maxim Integrated
│ 12
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Functional Diagram/Typical Operating Circuit
Maxim Integrated
│ 13
www.maximintegrated.com
MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
samples. The resulting oversampled digital signal is then
converted using a multibit sigma-delta modulator followed
by an analog smoothing filter that greatly attenuates high-
frequency quantization noise typical with oversampling
converters. Flexible clocking modes allow the MAX9850
to be used effectively in applications normally not well
suited for oversampling converters all without the need for
expensive sample rate converters.
Detailed Description
The MAX9850 audio digital-to-analog converter (DAC)
with a stereo DirectDrive headphone amplifier is a complete
digital audio playback solution. The sigma-delta DAC
has 90dB of dynamic range and accepts stereo audio
data at sampling frequencies ranging from 8kHz to
48kHz. Headphone output volume level, muting, and
device configuration are programmed through the
2
2
Set DACEN = 0 in the enable register (register 0x5, bit B0)
to disable the DAC. Set DACEN = 1 to enable the DAC.
I C-compatible interface. Three selectable I C device IDs
are available. Both basic modes of operation, integer and
noninteger, provide full dynamic range performance and
allow maximum flexibility when choosing the MAX9850’s
master clock (MCLK) frequency. Integer mode operation
requires that MCLK is an integer multiple of 16 times
the sample rate, and provides maximum full-scale SNR
performance. Noninteger mode allows maximum flexibility
when choosing an MCLK frequency, as the MCLK may be
any frequency in the acceptable range.
Line Outputs/Inputs
The MAX9850 features line inputs (INR, INL) and line
outputs (OUTR, OUTL). The line inputs allow a line
level signal to be mixed with the DAC output, see the
Functional Diagram/Typical Operating Circuit. Set LNIEN
= 1 in the enable register (register 0x5, bit B1) to enable
the line inputs. The line inputs are biased at AGND and
can be directly coupled or AC-coupled to INR and INL,
depending on the signal source.
Audio data is sent to the MAX9850 through a 3-wire
digital audio data bus that supports numerous input
formats. LRCLK and BCLK signals are generated by the
MAX9850 when configured in master mode. The MAX9850
can also be configured as a slave device, accepting
LRCLK and BCLK signals from an external digital audio
master. External LRCLK and BCLK signals may be either
synchronous or asynchronous with MCLK when the
MAX9850 is configured as a slave device.
Stereo DirectDrive line outputs (OUTR and OUTL) can be
used to drive line-level loads. Line outputs internally drive
the inputs of the headphone amplifier. Set LNOEN = 1 in
the enable register (register 0x5, bit B2) to enable the line
outputs. Disabling the line outputs will also disable the
headphone outputs.
The internal charge pump must be enabled to operate
the line outputs. Enable the charge pump by configuring
CPEN(1:0) = 11 in the enable register (register 0x5, bit B5
and B4). See the Charge Pump section.
Maxim’s DirectDrive architecture employs an internal
charge pump to create a negative voltage supply to power
the headphone amplifier outputs. The internal negative
supply allows the analog output signals to be biased
at ground, eliminating the need for an output-coupling
capacitor, reducing system cost and size.
DirectDrive Headphone and
Line Amplifiers
Unlike the MAX9850, traditional single-supply headphone
amplifiers have their outputs biased about a nominal DC
voltage, typically half the supply, for maximum dynamic
range. Large coupling capacitors are typically needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to the
headphone, resulting in unnecessary power dissipation
and possible damage to both headphone and headphone
amplifier.
The MAX9850’s stereo line inputs allow mixing of analog
audio with digital audio. The summed audio signal is
sent directly to the line and headphone outputs. The line
inputs/outputs can be activated even when the DAC is
disabled and MCLK is not present.
The headphone sense input (HPS) detects when a head-
phone is connected to the MAX9850. The HPS circuit
shuts down the headphone amplifier outputs when no
headphones are connected. The headphone amplifiers
can be automatically enabled when HPS detects the
presence of headphones.
Maxim’s DirectDrive architecture uses a charge pump to
create an internal negative supply voltage. This allows
the MAX9850 headphone and line outputs to be biased
about ground, almost doubling the dynamic range while
operating from a single supply. With no DC component,
there is no need for the large DC-blocking capacitors.
Instead of two large (33µF to 330µF) capacitors, the
MAX9850 charge pump requires only two small ceramic
Sigma-Delta DAC
The MAX9850 uses a sigma-delta DAC to achieve up to
91dB of SNR. The DAC receives a stereo digital input
signal sampled at f
, interpolates the signal data
LRCLK
to an 8 times f
frequency, and digitally filters the
LRCLK
Maxim Integrated
│ 14
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Table 1. Slew-Rate Settings
10
0
TYPICAL VOLUME SLEW RATE
FROM FULL
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
SR1
SR0
FROM FULL
VOLUME TO
VMN = 1 (ms)
VOLUME TO MUTE
0
0
1
1
0
1
0
1
63µs
125ms
63ms
42ms
0.1
200
100
67
Set MUTE = 1 in the volume register (register 0x2, bit
B7) to mute the headphone amplifiers. The mute function
is independent of the volume control. The programmed
volume settings are not reset when mute is enabled. With
the zero-crossing detection and volume slew enabled,
the Mute command mutes the output after the first zero
crossing or after a 200ms timeout (SR = 01).
0
8
16 24 32 40 48 56 64
VOL(5:0) CODE
Figure 1. Headphone Amplifier Attenuation Profile
capacitors (0.47µF and 2.2µF), conserving board space,
reducing cost, improving the frequency response, and
THD of the headphone amplifier. In addition to the cost
and size disadvantages, the DC-blocking capacitors
required by conventional headphone amplifiers limit low-
frequency response and decrease PSRR performance.
Some dielectrics can significantly distort the audio signal.
Mono Mode
Set MONO = 1 in the general-purpose register (register
0x3, bit B2) to enable mono mode. In mono mode, HPR
is disabled, the left and right audio channels are summed
and output on HPL. The 6dB attenuation ensures that the
summed signal amplitude does not overdrive headphone
amplifiers. SMONO in the status B register (register 0x1,
bit B4) sets to 1 when the MAX9850 is in mono mode.
Volume Control
Program VOL(5:0) in the volume register (register 0x2, bits
B5–B0) to set the volume attenuation of the headphone
amplifiers. Program VOL(5:0) to 0x00 for full volume.
Minimum volume occurs at VOL(5:0) greater than or equal
to 0x28. VMN in the status A register (register 0x0, bit B3)
sets to 1 when the MAX9850 output is programmed to and
reaches volume step 0x3F. Figure 1 shows the attenuation
profile for each VOL(5:0) value.
Configuring the Headphone and Line Outputs
Set HPEN and LNOEN in the enable register (register
0x5, bits B3 and B2) equal to 1 to enable the headphone
outputs (HPR and HPL). Set HPEN or LNOEN = 0 to
disable the headphone outputs.
The headphone amplifier inputs are driven from the out-
puts of the line amplifier. Disabling the line out by setting
LNOEN = 0 in the enable register (register 0x5, bit B2),
deprives the headphone amplifiers of an input signal and
disables the headphone outputs (HPR and HPL).
Volume Slew, Zero-Crossing Detect, and Mute
Set SLEW = 1 in the volume register (register 0x2, bit
B6) to enable the volume slew circuit. When SLEW
= 1 headphone amplifier volume changes will slew
between programmed levels smoothly. Set the volume
slew rate with SR(1:0) in the charge-pump register
(register 0x7, bits B7 and B6). Table 1 lists the volume
slew-rate settings for each value of SR(1:0).
The internal charge pump must be enabled to operate
the headphone and line outputs. Enable the charge pump
by programming CPEN(1:0) = 11 in the enable register
(register 0x5, bits B5 and B4). See the Charge Pump
section for more details.
Set ZDEN = 1 in the general-purpose register (register
0x3, bit B0) to force volume changes and headphone
amplifier muting to occur when the audio signal is at its
zero crossing. For optimal performance, set SR(1:0) to
01. This zero-crossing detection reduces audible clicks/
pops caused when transitioning or slewing between
volume levels.
Headphone Sense Input (HPS)
The headphone sense input (HPS) monitors the head-
phone jack, and automatically disables the headphone
amplifiers based upon the voltage applied at HPS. For
automatic headphone detection, connect HPS to the
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Stereo Audio DAC with DirectDrive
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Table 2. HPS Debounce Times
DV
DD
DEBOUNCE
TIME
DEBOUNCE TIME
BASED ON
DBDEL(0) DBDEL(0)
(ms)
f
= 667kHz (ms)
0 (Disabled)
Approx 200
Approx 400
Approx 800
CP
SHDN*
0
0
1
1
0
1
0
1
0
17
2
2
2
x 1/f
x 1/f
x 1/f
CP
CP
CP
100kΩ
MAX9850
18
19
HPS
GPIO
Configure GPIO as an input or an output with the GPD
bit in the general-purpose register (register 0x3, bit B5).
GPD = 1 configures GPIO as an open-drain output while
GPD = 0 makes GPIO an input. Connect an external
*SHDN = 1 FOR THIS DIAGRAM
pullup resistor from GPIO to DV
configured as an output.
when GPIO is
DD
Figure 2. Headphone Sense (HPS) Input
GPIO as an output allows the MAX9850 to drive an LED
or other state indicator. It also can be used to provide an
interrupt signal to alert a µC when an event has occurred.
Potential events include changes in internal PLL lock
state, connecting headphones to HPS, headphone
outputs reaching the minimum volume, or an overcurrent
on the headphone outputs. Any of these events can be
programmed to pulse GPIO’s output state when GPIO is
configured as an open-drain output.
control pin of a 3-wire headphone jack as shown in
Figure 2. With no headphone present, the output
impedance of the headphone amplifier pulls HPS to less
than 0.3 x DV . When a headphone is inserted into the
DD
jack, the control pin is disconnected from the tip contact
and HPS is pulled to DV ꢀthroughꢀtheꢀinternalꢀ100kΩꢀ
DD
pullup. No external resistor is required. Leave HPS float-
ing if automatic headphone sensing is not used. HPS
must be high and HPEN (register 0x5, bit B3) must be
set to 1 for the headphone amplifiers (HPR and HPL) to
output an audio signal.
Using GPIO as an input allows the MAX9850 to receive a
signal from a µC’s digital I/O or other device. The status
of GPIO is read through SGPIO in the status A register
(register 0x0, bit B6).
The MAX9850 includes an HPS debounce circuit that
ignores short duration changes on HPS. The debounce
circuit ensures that a headphone is properly connected
before powering up and enabling the headphone amplifi-
ers. Program DBDEL(1:0) in the general-purpose register
(register 0x3, bits B4 and B3) to set the HPS debounce
delay time. The delay time is based on a division of the
GPIO as an Output
Set GPD = 1 (register 0x3, bit B5) to configure GPIO as
an output. Program the output operating mode of GPIO
with GM(1:0) in the general-purpose register (register
0x3, bits B7 and B6). GPIO can be programmed to output
logic-high, a logic-low, or it can be programmed to output
an interrupt signal by changing state when the ALERT bit
in the status A register (register 0x0, bit B7) sets. Table 3
lists GPIO’s modes of operation.
charge-pump frequency, f . See the Charge Pump
CP
section for details on programming the charge-pump
frequency. Table 2 lists the available delay times of the
debounce circuit.
Table 3. GPIO Output Operating Modes
(GPD = 1)
There is no delay on removal of a headphone when using
automatic headphone sense. The headphone amplifiers
are immediately placed into shutdown when HPS goes
high.
GM(1) GM(0)
MODE DESCRIPTION
0
0
1
0
1
0
GPIO = 0
SHPS in the status a register (register 0x0, bit B4) reports
the status of HPS. SHPS = 0 when HPS is low and SHPS
= 1 when HPS is high.
GPIO = High impedance
GPIO = 0, ALERT output pulse enabled
GPIO = High impedance,
ALERT output pulse enabled
1
1
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Table 4. Interrupt Enable Register (0x4) Events
EVENT
BIT NUMBER IN REGISTER 0x4
LCK (register 0x0, bit B5) sets when the internal PLL acquires or loses frequency lock
B5
SHPS (register 0x0, bit B4) sets after the headphone is inserted and the debounce time
has elapsed when the headphone amplifier is powered up and ready
B4
VMN (register 0x0, bit B3) sets when the headphone amplifier minimum volume is reached
IOHL or IOHR (register 0x0, bits B1 or B0) sets after an overcurrent at either HPL or HPR
B3
B0
The interrupt enable register programs the MAX9850 to
set ALERT = 1 when an event occurs. GPIO pulses when
ALERT sets if GM(1:0) is programmed with 10 or 11.
Table 4 contains a list of events that can set ALERT and
their corresponding bit positions in the interrupt enable
register. Enable the interrupt for each event by setting its
bit to 1.
Higher ICLK frequencies provide higher SNR. Always
use the highest acceptable ICLK. Sample rates other
than those listed in Table 5 can be used. The MAX9850
defaults to IC(1:0) = 0x0 at power-up.
DAC Operating Modes
Four DAC operating modes: master integer, slave
integer, master noninteger, and slave noninteger allow
flexibility for operating with various applications and
virtually any available MCLK frequency within the system.
The operating modes are set with MAS in the digital audio
register (register 0xA, bit B7) and INT in the LRCLK MSB
register (register 0x8, bit B7). Table 6 shows the four
modes of operation and the equations needed to program
the MAX9850 to use the DAC modes.
GPIO as an Input
The state of the GPIO input is read through SGPIO in the
status A register (register 0x0, bit B6). Set ISGPIO = 1 to
allow ALERT to set when SGPIO changes state.
Internal Timing
The internal clock (ICLK) and sample rate clock (LRCLK in
master mode) are derived from MCLK. The MAX9850’s flexible
operating modes allow any desired LRCLK sample rate to
operate over a wide range of MCLK input frequencies.
The master and slave integer modes are the modes in
which DACs commonly operate. In these modes, LRCLK
is ICLK divided by an integer value. A typical application
would set MCLK equal to 256 x LRCLK. The MAX9850
requires that ICLK be an integer multiple of 16 x LRCLK
where the integer multiple is at least 10 when in master
or slave integer modes. Integer mode always provides the
maximum full-scale signal level performance compared to
other modes of operation. Choose integer mode over any
other mode of operation when possible.
Figure 3 shows a flowchart detailing how the internal clocks
are derived from MCLK. The MAX9850 generates ICLK
by dividing the MCLK frequency. Higher ICLK frequencies
allow for greater DAC oversampling and SNR performance.
Dynamic range of 90dB (typ) is possible when f
is
ICLK
greater than or equal to 12MHz. Lower ICLK frequencies
may require slightly less supply current but sacrifice
dynamic range. See the SNR vs. MCLK Frequency graph
in the Typical Operating Characteristics.
The master noninteger mode allows for a condition where
LRCLK and ICLK may not be related by an integer value.
In these modes, the MAX9850 can operate from any
available MCLK in the system.
ICLK is a frequency-scaled version of MCLK that is used
by the MAX9850 to clock the internal DAC circuitry and
generate LRCLK and BCLK when in master mode. The
charge-pump clock is derived from ICLK when the internal
charge-pump oscillator is not used.
IC(1:0) INTERNAL CLOCK
Connect an available system clock to MCLK, see the DAC
Operating Modes section. MCLK can be supplied from
any synchronous or available asynchronous system clock
whose frequency falls within the 8.448MHz to 13MHz,
or 16.896MHz to 40MHz range. Any MCLK within these
ranges allow the MAX9850 to operate at any sample rate
between 8kHz to 48kHz in either a master or slave mode
of operation. Other MCLK frequencies can still be used,
but will limit the sample rate ranges that the MAX9850
operates with as illustrated in Table 5.
0x0 = 1/1
0x1 = 1/2
0x2 = 1/3
0x3 = 1/4
(ICLK)
MASTER CLOCK
(MCLK)
CHARGE-PUMP
CLOCK
CP(4:0)
LRCLK DIVIDER
LRCLK*
*LRCLK IS GENERATED WHEN IN MASTER
MODE ONLY. THE DIVIDER IS SET WITH THE
LRCLK MSB AND LRCLK LSB REGISTERS.
Figure 3. Internally Generated Clock Signals Derived from MCLK
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Table 5. Acceptable MCLK Frequency Ranges
MINIMUM ICLK
(MHz)
MAXIMUM ICLK
(MHz)
ACCEPTABLE MCLK FREQUENCIES*
(MHz)
LRCLK
(kHz)
INTEGER MODE NONINTEGER MODE
IC(1:0) = 0x0
SF = 1
IC(1:0) = 0x1
SF = 2
IC(1:0) = 0x2
SF = 3
IC(1:0) = 0x3
SF = 4
ANY MODE
13.0
(160 x f
LRCLK
)
(176 x f )
LRCLK
1.280 and
2.560 and
3.840 and
5.120 and
8
11.025
12
1.280
1.4080
1.4080 to 13.0
2.8160 to 26.0
4.2240 to 39.0
5.6320 to 40.0
1.764 and
3.528 and
5.292 and
7.056 and
1.764
1.920
2.560
3.528
3.840
5.120
7.056
7.680
1.9404
2.1120
2.8160
3.8808
4.2240
5.6320
7.7616
8.4480
13.0
1.9404 to 13.0
3.8808 to 26.0
5.8212 to 39.0
7.7616 to 40.0
1.920 and
3.840 and
5.760 and
7.680 and
13.0
2.1120 to 13.0
4.2240 to 26.0
6.3360 to 39.0
8.4480 to 40.0
2.560 and
5.120 and
7.680 and
10.240 and
16
13.0
2.8160 to 13.0
5.6320 to 26.0
8.4480 to 39.0 11.2640 to 40.0
3.528 and
7.056 and
10.584 and 14.112 and
22.05
24
13.0
3.8808 to 13.0
7.7616 to 26.0 11.6424 to 39.0 15.5232 to 40.0
7.680 and 11.520 and 15.360 and
8.4480 to 26.0 12.6720 to 39.0 16.8960 to 40.0
10.240 and 15.360 and 20.480 and
3.840 and
13.0
4.2240 to 13.0
5.120 and
32
13.0
5.6320 to 13.0 11.2640 to 26.0 16.8960 to 39.0 22.5280 to 40.0
7.056 and 14.112 and 21.168 and 28.224 and
7.7616 to 13.0 15.5232 to 26.0 23.2848 to 39.0 31.0464 to 40.0
7.680 and 15.360 and 23.040 and 30.720 and
8.4480 to 13.0 16.8960 to 26.0 25.3440 to 39.0 33.7920 to 40.0
44.1
48
13.0
13.0
*The first frequency listed is the minimum MCLK frequency required to operate in integer mode. The range of frequencies indicates
the MCLK frequencies the MAX9850 needs to operate in any mode.
Table 6. DAC Operating Modes
SLAVE MODE
(MAS = 0)
MASTER MODE
(MAS = 1)
MODE
LRCLK and BCLK signals supplied LRCLK and BCLK signals supplied
from external source
by MAX9850
Asynchronous
22
Asynchronous
LRCLK may be any
frequency within an
acceptable range
NONINTEGER
MODE (INT = 0)
2
× f
LRCLK
N
= 0
N
=
MSB,LSB
MSB,LSB
f
ICLK
Synchronous
ICLK and LRCLK must be
synchronous and exact
integer ratio related
INTEGER MODE
(INT = 1)
f
ICLK
N
=
, N
= 0
MSB
LSB
16 × f
LRCLK
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Slave modes of operation allow the MAX9850 to operate
in any audio system where the LRCLK and BCLK must
be supplied from an external source. When operating in
slave mode, the MCLK supplied to the MAX9850 may be
either synchronous or asynchronous with LRCLK. Use
the slave integer mode if ICLK is synchronous and has an
integer multiple of 16 x LRCLK. Integer mode ensures that
the highest levels of full-scale-input signal performance can
be achieved. Slave noninteger mode offers the highest
degree of clock flexibility. ICLK does not need to be
synchronous or an integer multiple of LRCLK when
operating in slave noninteger mode.
Slave Integer Mode (MAS = 0, IM = 1)
The MAX9850 accepts LRCLK and BCLK from an external
digital audio source when in slave integer mode. LRCLK
must be an exact integer multiple of ICLK to ensure
proper operation. Program LSB(7:0) (register 0x9, bits
B7–B0) with the LRCLK division ratio. Use the following
equation to find the value that needs to be programmed
to LSB(7:0):
f
ICLK
N
=
LSB
16 × f
LRCLK
where:
= ICLK frequency. f
Master modes of operation allow the MAX9850 to generate
and supply an LRCLK and BCLK to other elements in the
system. Use master integer mode if the provided ICLK is
an integer multiple of 16 x LRCLK. Integer mode ensures
that the highest levels of full-scale input signal performance
can be achieved. Master noninteger mode allows the
MAX9850 to supply virtually any frequency LRCLK with
an accuracy better than ±0.5%.
f
must be 160 x f
for
ICLK
ICLK
LRCLK
proper DAC operation.
f
= supplied LRCLK frequency.
LRCLK
N
= decimal value of the data contained in LSB(7:0)
LSB
(register 0x9, bits B7–B0).
For example:
f
= 11.2896MHz and f
= 44.1kHz, N
= 16
ICLK
LRCLK
LSB
The slave noninteger mode provides maximum flexibility
for ICLK and LRCLK frequencies. The ICLK and LRCLK
can be asynchronous and noninteger related. Connect
any available system clock that is listed on Table 5 in the
Internal Timing section. In slave noninteger mode, the
acceptable MCLK frequency range is the same as master
mode.
(0x10).
Solve the above equation for N
mode if N
. Use slave integer
is an integer. Use slave noninteger mode if
LSB
LSB
N
is not an integer.
LSB
Slave Noninteger (MAS = 0, IM = 0)
In slave noninteger mode, the MAX9850 accepts an
external LRCLK and converts the digital audio signal
using any asynchronous ICLK within the acceptable
operating range. The MAX9850 uses internal clock
recovery circuitry to generate all required internal clocks.
This allows the MAX9850 to operate in systems that do
not have dedicated clock sources or crystal oscillators.
Master Integer Mode (MAS = 1, IM = 1)
The MAX9850 generates the LRCLK and BCLK in master
mode. LRCLK is an integer factor of ICLK by the following
equation:
f
ICLK
f
=
Virtually any existing system clock will work. f
be at least 176 x f
must
ICLK
LRCLK
16 ×N
LSB
for proper operation.
LRCLK
where:
Master Noninteger Mode (MAS = 1, IM = 0)
The ICLK frequency in some applications may not be
an integer multiple of the desired LRCLK frequency. The
MAX9850, operating in master noninteger mode, can
generate and output any LRCLK frequency between
8kHz to 48kHz (±0.5%) with any ICLK frequency within the
acceptable operating range. In this mode, the MAX9850
generates LRCLK by dividing MCLK by the ratio
programmed into MSB(14:8) and LSB(7:0) (register 0x8,
bits B7–B0 and register 0x9, bits B6–B0). The LRCLK
sample frequency can have any noninteger relationship
with respect to MCLK. Calculate the values for MSB(14:8)
and LSB(7:0) with the following equation:
f
f
= ICLK frequency. f
must be at least 160 x
ICLK
ICLK
for proper DAC operation.
LRCLK
N
= decimal value of the data contained in LSB(7:0)
LSB
(register 0x9, bits B7–B0).
f
= LRCLK frequency.
LRCLK
For example:
f
= 12.228MHz and N
= 16 (0x10), f
=
ICLK
LSB
LRCLK
48kHz.
Solve the above equation for N
mode if N
if N
. Use master integer
LSB
is an integer. Use master noninteger mode
LSB
is not an integer.
LSB
22
22 × f
LRCLK
N
= ROUND
MSB,LSB
f
ICLK
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Stereo Audio DAC with DirectDrive
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where:
The state of CP(4:0), in the charge-pump register (register
0x7, bits B4–B0), determines whether the charge-pump
oscillator is derived from the internal 667kHz oscillator or
from MCLK. Set CPEN(1:0) = 11 and set CP(4:0) = 0x00
to enable the internal oscillator. The charge pump runs
independent from MCLK when the internal oscillator is
enabled allowing the charge pump to operate when the
DAC is disabled or when only the line inputs are used. No
MCLK is required when only the line inputs are used.
f
f
= ICLK frequency. f
must be at least 176 x
for proper DAC operation.
ICLK
ICLK
LRCLK
f
= LRCLK frequency.
LRCLK
N
= decimal value of MSB(14:8) and LSB(7:0)
MSB,LSB
(register 0x8, bits B6–B0 and register 0x9, bits B7–B0).
Round the results of the equation to the nearest integer
value.
The switching frequency of the charge pump is well
beyond the audio range and does not interfere with
audio signals. The switch drivers utilize techniques that
minimize noise generated by turn-on and turn-off
transients. Although not typically required, additional high-
frequency noise attenuation can be achieved by increasing
For example:
f
= 44.1kHz, f
= 12.288MHz.
15052.8.
LRCLK
ICLK
1) Solve for N
MSB,LSB,
2) Round result to nearest integer value. 15053.
3) Convert to hex, 0x3CD.
the size of C2 and the PV
bypass capacitor (see the
DD
4) Program MSB(14:8) with the MSB 0x3A and program
LSB(7:0) with the LSB 0xCD).
Functional Diagram/Typical Operating Circuit).
Derive the charge-pump clock from MCLK by programming
CP(4:0) to a non-zero value based on the following equation:
Table 7 provides examples of using master noninteger
mode with various MCLK frequencies to generate useful
LRCLK frequencies.
f
MCLK
N
=
CP( 4:0 )
2× f
× SF
CP
Charge Pump
where:
The DirectDrive line and headphone outputs of
the MAX9850 require a charge pump to create the
internal negative power supply. Set CPEN(1:0) = 11 in
the enable register (register 0x5, bits B5 and B4) to turn
on the charge pump. The negative charge-pump voltage
is established and the audio outputs are ready for use
approximately 1.4ms after CPEN is set to 11.
f
= MCLK frequency.
MCLK
f
= charge-pump clock frequency. Ensure f = 667kHz
CP
CP
±20% for proper operation.
SF = MCLK scale factor. SF is the decimal value of
IC(1:0) + 1.
N
= rounded decimal value of CP(4:0) (register
CP(4:0)
0x7, bits B4–B0). N
must be greater than 1 when
CP(4:0)
deriving the charge-pump clock from I
.
CLK
Table 7. Master Noninteger N
Examples
MSB,LSB
N (15-BIT hex VALUE)
MCLK
(MHz)
ICLK
(MHz)
SF
LRCLK OUTPUT FREQUENCY (kHz)
48
44.1
4E66
5555
5833
39CE
3ACD
3C36
4000
4E66
5555
5587
32
24
22.05
2733
2AAB
2C1A
1CE7
1D66
1E1B
2000
2733
2AAB
2AC3
16
12
11.03
139A
1555
160D
0E73
0EB3
0F0E
1000
139A
1555
1562
8
18.4320
16.9344
16.3840
12.5000
12.2880
12.0000
11.2896
9.2160
2
2
2
1
1
1
1
1
1
1
9.2160
8.4672
8.1920
12.5000
12.2880
12.0000
11.2896
9.2160
8.4672
8.4480
5555
5CE1
38E4
3DEB
4000
29F1
2AAB
2BB1
2E71
38E4
3DEB
3E10
2AAB
2E71
3000
1F75
2000
20C5
22D4
2AAB
2E71
2E8C
1C72
1EF6
2000
14F9
1555
15D8
1738
1C72
1EF6
1F08
1555
1738
1800
0FBB
1000
1062
116A
1555
1738
1746
0E39
0F7B
1000
0A7C
0AAB
0AEC
0B9C
0E39
0F7B
0F84
3EEA
4000
4189
45A9
5555
5CE1
5D17
8.4672
8.4480
Note: The N values represent the combined MSB(14:8) and LSB(7:0) values.
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For example:
Table 8. Recommended CP(4:0) Values
for Typical MCLK Frequencies
f
= 12MHz, SF = 1, and f
= 666.7kHz,
CP
MCLK
N
= 9.
CP(4:0)
f
f
CP
MCLK
Table 8 shows recommended CP(4:0) values for typical
MCLK frequencies.
CP(4:0)
IC(1:0)
SF
(MHz)
(kHz)
705.6
666.7
682.7
650.0
666.7
642.9
11.2896
12.0000
12.2880
13.0000
24.0000
27.0000
0x08
0x09
0x09
0x0A
0x09
0x07
0x0
0x0
0x0
0x0
0x1
0x2
1
1
1
1
2
3
Registers and Bit Descriptions
Eleven internal registers program and report the status
of the MAX9850. Table 9 lists all of the registers, their
addresses, and power-on-reset state. Registers 0x0 and
0x1 are read-only while all of the other registers are read/
write. Register 0xB is reserved for factory testing.
Table 9. Register Map
REGISTER
ADDRESS
POWER-ON
RESET STATE
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
Status A
Status B
Volume
ALERT
X
SGPIO
X
LCK
X
SHPS
VMN
SHP
1
IOHL
SLI
IOHR
0x0
—
—
SMONO
SLO
SDAC
0x1
MUTE
SLEW
VOL(5:0)
0x2
0x0C
General
Purpose
GM(1:0)
GPD
ILCK
DBDEL(1:0)
MONO
0
0
0
ZDEN
IIOH
0x3
0x4
0x00
0x00
Interrupt
Enable
0
ISGPIO
ISHPS
0
IVMN
Enable
Clock
SHDN MCLKEN
CPEN(1:0)
HPEN LNOEN LNIEN DACEN
IC(1:0)
0x5
0x6
0x00
0x00
0
0
0
0
0
0
Charge
Pump
SR(1:0)
CP(4:0)
0x7
0x00
LRCLK MSB
LRCLK LSB
Digital Audio
INT
MSB(14:8)
DLY
0x8
0x9
0xA
0xB
0x00
0x00
0x00
—
LSB(7:0)
MAS
INV
BCINV
LSF
RTJ
WS(1:0)
RESERVED
X = Don’t Care.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
PLL Lock Status (LCK)
Status Registers (0x0, 0x1)
1 = The internal PLL is locked with LRCLK.
0 = The internal PLL is not locked with LRCLK.
Table 10. Status A (0x0) Read-Only,
Bit Descriptions
LCK reports the lock status of the internal PLL at the time
that STATUS A is read. The DAC is disabled when the
PLL is not locked. When the PLL is locked with LRCLK,
the DAC will become operational if DACEN is equal to 1
(register 0x5, bit B0). ALERT sets to 1 when LCK changes
state if ILCK = 1 in the interrupt enable register (register
0x4, bit B5).
B7
B6
B5
B4
B3
B2
B1
B0
ALERT SGPIO LCK SHPS VMN
1
IOHL IOHR
Alert Flag (ALERT)
1 = An interrupt event has occurred.
0 = No interrupt event has occurred.
HPS Status (SHPS)
ALERT is an alert flag that sets when an interrupt event
has occurred. The events that can be programmed to set
ALERT are as follows:
1 = HPS is high, indicating that headphones are
connected.
0 = HPS is low, indicating no headphone is connected.
● A change in state on SGPIO indicating a change in
levels at GPIO when GPIO is configured as an input.
Configure GPIO as an input and set ISGPIO = 1 in the
interrupt enable register (register 0x4, bit B6).
SHPS reports the debounced status of HPS at the time
STATUS A is read. SHPS = 0 indicates that no headphone
is connected and HPS is low. SHPS sets to 1 when HPS
is high, indicating headphones are connected. ALERT
sets to 1 when SHPS changes state, if ISHPS = 1 in the
interrupt enable register (register 0x4, bit B4).
● The internal PLL locks or unlocks with LRCLK. Set
ILCK = 1 in the interrupt enable register (register 0x4,
bit B5).
Volume at Minimum (VMN)
● A change in state on SHPS indicating headphones
have been connected or disconnected. Set ISHPS =
1 in the interrupt enable register (register 0x4, bit B4).
1 = Headphone volume has reached its minimum volume.
0 = Headphone volume is not at its minimum.
VMN sets to 1 when the minimum headphone amplifier
volume has been reached. ALERT sets to 1 when IVMN
= 1 in the interrupt enable register (register 0x4, bit B3).
● The headphone amplifier reaches its minimum
volume. Set IVMN = 1 in the interrupt enable register
(register 0x4, bit B3).
● An overload on either right or left headphone outputs
(HPR, HPL). Set IIOH = 1 in the interrupt enable
register (register 0x4, bit B0).
Headphone Overcurrent Left (IOHL)
1 = The left headphone output (HPL) has experienced an
overcurrent condition.
ALERT sets to 1 after an event occurs and remains set
until the status A register is read. GPIO configured as an
output can interrupt a µC on an ALERT event. GM(1:0) in
the GPIO register (register 0x3, bits B7 and B6) control
the output mode of GPIO. See the GPIO section for more
information on programming GPIO as an output.
0 = The left headphone output (HPL) is operating normally.
IOHL sets to 1, when an overcurrent occurs on the left
headphone output HPL and remains set until status a is
read. ALERT sets to 1 when an overcurrent on the right
or left headphone output occurs if IIOH = 1 in the interrupt
enable register (register 0x4, bit B0).
GPIO Status (SGPIO)
1 = GPIO is high.
0 = GPIO is low.
Headphone Overcurrent Right (IOHR)
1 = The right headphone output (HPR) has experienced
an overcurrent condition.
SGPIO reports the status of GPIO at the time that status
A is read, regardless of whether GPIO is programmed as
an input or output. A change in state on SGPIO causes
ALERT to set to 1 when GPIO is configured as an input
and ISGPIO = 1 in the interrupt enable register (register
0x4, bit B6).
0 = The right headphone output (HPR) is operating normally.
IOHR sets to 1 and remains set until STATUS A is read.
ALERT sets to 1 when an overcurrent on the right or
left headphone output occurs if IIOH = 1 in the interrupt
enable register (register 0x4, bit B0).
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Line Output Status (SLO)
Table 11. Status B (0x1) Read-Only,
Bit Descriptions
0 = The line outputs are enabled.
1 = The line outputs are disabled.
B7
B6
B5
B4
B3
B2
B1
B0
SLO indicates whether the line outputs are enabled or
disabled. Set LNOEN = 1 in the enable register (register
0x5, bit B2) to enable the line outputs.
X
X
X
SMONO SHP
SLO
SLI
SDAC
Mono Status (SMONO)
Line Input Status (SLI)
1 = The headphone amplifier outputs are in mono mode.
0 = The headphone amplifier outputs are in stereo mode.
0 = The line inputs are enabled.
1 = The line inputs are disabled.
SMONO indicates whether the headphone outputs are in
mono or stereo mode. In mono mode, the left and right
audio signals are mixed and output to the left headphone
output. Set MONO = 1 in the general-purpose register
(register 0x3, bit B2) to enter mono mode.
SLI indicates whether the line inputs are enabled or
disabled. Set LNIEN = 1 in the enable register (register
0x5, bit B1) to enable the line inputs.
DAC Status (SDAC)
0 = The DAC is operating and has completed a soft-start
sequence.
Headphone Amplifier Status (SHP)
0 = The headphone amplifiers are operating.
1 = The headphone amplifiers are not operating.
1 = The DAC is not operating and has completed a soft-
stop sequence.
SHP indicates whether the headphone amplifiers are
operating or not operating.
SDAC indicates whether the DAC is operational and
receiving valid clock signals, or not operating.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Slew-Rate Control Enable (SLEW)
1 = Enable slew-rate control.
Volume Register (0x2)
Table 12. Volume (0x2) Read/Write,
Bit Descriptions
0 = Disable slew-rate control.
The slew-rate control allows the headphone amplifiers to
smoothly slew between volume settings after a volume
change is made. Volume changes occur immediately
when the slew-rate control is disabled.
B7
B6
B5
B4
B3
B2
B1
B0
MUTE SLEW
VOL(5:0)
Volume Control (VOL(5:0))
Mute Enable (MUTE)
1 = Mute headphone outputs.
0 = Unmute headphone outputs.
VOL(5:0) controls the headphone amplifier volume attenuation.
Code 0x00 is full volume while 0x28 to 0x3F is full attenuation.
VMN sets to 1 when code 0x3F is programmed and the
minimum volume is reached. Table 13 lists the volume
attenuation settings for each code.
Set MUTE = 1 to mute the headphone outputs (HPR,
HPL). The headphone output is muted on the first zero
crossing of the audio signal if zero-crossing detect is
enabled.
Table 13. Volume Control Settings
VOL(5:0)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
SETTING (dB)
+6.0
VOL(5:0)
0x0E
0x0F
0x10
0x11
SETTING (dB)
-7.5
VOL(5:0)
0x1C
0x1D
0x1E
0x1F
SETTING (dB)
-35.5
-37.5
-39.5
-41.5
-45.5
-49.5
-53.5
-57.5
-61.5
-65.5
-69.5
-73.5
Mute
+5.5
-9.5
+5.0
-11.5
+4.5
-13.5
-15.5
-17.5
-19.5
-21.5
-23.5
-25.5
-27.5
-29.5
-31.5
-33.5
+4.0
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x20
+3.5
0x21
+3.0
0x22
+2.5
0x23
+1.5
0x24
+0.5
0x25
-0.5
0x26
-1.5
0x27
-3.5
0x28-0x3F
—
-5.5
—
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Volume changes, headphone output muting, and entering/
exiting shutdown occur only on the zero crossing of the
audio signal when ZDEN = 1. For optimum performance,
set SR(1:0) to 01.
General-Purpose Register
Table 14. General Purpose (0x3)
Read/Write, Bit Descriptions
Interrupt Enable Register
B7
B6
B5
B4
B3
B2
B1
B0
Table 15. Interrupt Enable (0x4)
Read/Write, Bit Descriptions
GM(1:0)
GPD DBDEL(1:0) MONO
0
ZDEN
GPIO Output Mode Control (GM(1:0))
00 = GPIO outputs low.
B7
B6
B5
B4
B3
B2
B1
B0
01 = GPIO is high impedance.
0
ISGPIO ILCK ISHPS IVMN
0
0
IIOH
10 = GPIO outputs low and the ALERT output pulse
function is enabled.
Note: Any of the below interrupts can be configured to
trigger a hardware interrupt through GPIO. Program GPD
and GM(1:0) in the general-purpose register to enable the
ALERT output pulse function.
11 = GPIO is high impedance and the ALERT output pulse
function is enabled.
GM(1:0) programs the GPIO output state and enables or
disables the ALERT output pulse function. The open-drain
GPIO output can be programmed to output static high
or a low. GPIO can also be programmed to pulse to the
opposite output level than the programmed output state
when an alert occurs. An alert occurs when ALERT sets
to 1 in the status A register. GM(1:0) has no function when
GPIO is configured as an input.
SGPIO Interrupt Enable (ISGPIO)
1 = A state change on SGPIO, when GPIO is an input,
will cause ALERT to set to 1.
0 = A state change on SGPIO, when GPIO is an input,
will not cause ALERT to set.
ISGPIO = 1 configures the MAX9850 to set ALERT = 1
when SGPIO changes state. The interrupt may only be
enabled when GPIO is an input.
GPIO Direction (GPD)
1 = Configure GPIO as an open-drain output.
0 = Configure GPIO as an input.
PLL Lock Interrupt Enable (ILCK)
The state of GPD determines whether GPIO is an input
or an output.
1 = A state change on LCK will cause ALERT to set to 1.
0 = A state change on LCK will not cause ALERT to set.
Debounce Delay Control (DBDEL(1:0))
00 = HPS debounce delay disabled.
ILCK = 1 configures the MAX9850 to set ALERT = 1 when
the DAC’s internal PLL loses or achieves frequency lock
with LRCLK. Program GM(1:0), while GPD = 1, to configure
GPIO as a hardware interrupt to alert a µC when LCK
changes state.
01 = HPS debounce delay is a nominal 200ms.
10 = HPS debounce delay is a nominal 400ms.
11 = HPS debounce delay is a nominal 800ms.
SHPS Interrupt Enable (ISHPS)
DBDEL(1:0) controls the length of HPS debounce time.
The debounce time is derived from the charge-pump
clock.
1 = A state change on SHPS will cause ALERT to set to 1.
0 = A state change on SHPS will not cause ALERT to set.
Mono Mode Enable (MONO)
ISHPS = 1 configures the MAX9850 to set ALERT = 1
when SHPS changes state.
1 = Enable mono mode.
0 = Disable mono mode, headphone outputs in stereo
mode.
Volume at Minimum Interrupt Enable (IVMN)
1 = A state change on VMN will cause ALERT to set to 1.
0 = A state change on VMN will not cause ALERT to set.
Set MONO = 1 to force the headphone outputs to
mono mode. The stereo input signal is summed to one
channel. The summed signal is output on the left
headphone output (HPL).
IVMN = 1 configures the MAX9850 to set ALERT = 1
when the headphone amplifier is programmed to and
reaches its minimum output volume. Program GM(1:0),
while GPD = 1, to configure GPIO as a hardware interrupt
to alert a µC when the headphone output volume is
programmed to and reaches its minimum volume.
Zero-Detect Enable (ZDEN)
1 = Enables the zero-detect function.
0 = Disables the zero-detect function.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Headphone Overcurrent Interrupt Enable (IIOH)
1 = ALERT sets to 1 when either IOHL or IOHR set to 1.
0 = ALERT will not set when IOHL or IOHR set to 1.
Line Output Enable (LNOEN)
1 = Enable the line outputs.
0 = Disable the line outputs.
IIOH = 1 configures the MAX9850 to set ALERT = 1
when one or both of the headphone amplifier outputs
(HPL, HPR) has experienced an overcurrent condition.
Program GM(1:0), while GPD = 1, to configure GPIO as a
hardware interrupt to alert a µC to an overcurrent
condition on the headphone outputs.
LNOEN = 0 forces the line outputs and the headphone
outputs to high impedance. Set LNOEN = 1 to enable
the line outputs. The line outputs must be enabled for the
headphone amplifiers to operate properly.
Line Input Enable (LNIEN)
1 = Enable the line inputs.
0 = Disable the line inputs.
Enable Register
Table 16. Enable (0x5) Read/Write,
Bit Descriptions
LNIEN = 1 enables the line inputs. LNIEN = 0 disconnects
the line inputs.
DAC Enable (DACEN)
1 = Enable the audio DAC.
0 = Disable the audio DAC.
B7
B6
B5
B4
B3
B2
B1
B0
SHDN MCLKEN CPEN (1:0) HPEN LNOEN LNIEN DACEN
DACEN = 1 enables the DAC and all supporting circuitry
including the digital audio interface and interpolating FIR
filter. DACEN = 0 places the DAC and support circuitry
into low-power shutdown mode.
Shutdown (SHDN)
1 = The MAX9850 is powered on.
0 = The MAX9850 is in low-power shutdown mode. The
2
I C interface remains active.
Clock Register
Set SHDN = 1 to power on the MAX9850. The headphone
amplifier, master clock, line inputs/outputs, DAC, charge
pump, and charge-pump clock all have their own enable
bits. The individual components of the MAX9850 can only
be enabled after SHDN = 1.
Table 17. Clock (0x6) Read/Write,
Bit Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
MCLK Enable (MCLKEN)
0
0
0
0
IC(1:0)
0
0
1 = MCLK is connected to the MAX9850.
0 = MCLK is disconnected from the MAX9850.
Internal Clock Divide (IC(1:0))
00 = Internal clock divider is transparent (f
= f
).
ICLK
MCLK
MCLKEN must be set to 1 for the DAC to operate
properly. The line inputs/outputs and headphone
amplifiers will work if MCLKEN = 0, but the charge-pump
clock must be derived from the internal oscillator.
01 = (f
10 = (f
11 = (f
= f
/ 2).
/ 3).
/ 4).
ICLK
ICLK
ICLK
MCLK
MCLK
MCLK
= f
= f
Charge-Pump Enable (CPEN(1:0))
11 = Enable the internal charge pump.
00 = Disable the internal charge pump.
10 and 01 = Invalid.
IC(1:0) controls the internal clock divider that determines
the internal clock frequency from the master clock.
Charge-Pump Register
Table 18. Charge Pump (0x7) Read/Write,
Bit Descriptions
Set CPEN(1:0) to 11 to enable the internal charge pump
when the line outputs and headphone amplifiers are used.
Headphone Output Enable (HPEN)
1 = Enable the headphone outputs.
0 = Disable the headphone outputs.
B7
B6
B5
B4
B3
B2
B1
B0
SR(1:0)
0
CP(4:0)
Set HPEN = 1 to enable the headphone outputs. HPEN
= 0 places the headphone outputs in high impedance.
The line outputs must be enabled for the headphone
amplifiers to operate properly.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Slew-Rate Control (SR(1:0))
Integer Mode (INT)
00 = Headphone volume slews from code 0x00 to 0x28 in
63µs. Not recommended when ZDEN = 1.
1 = Configure the MAX9850 to integer mode.
0 = Configure the MAX9850 to noninteger mode.
Integer mode operation requires that ICLK is an integer
01 = Headphone volume slews from code 0x00 to 0x28
in 125ms.
multiple of 16 times the sample rate (f
). See the
LRCLK
DAC Operating Modes section. When in integer mode,
= f / (16 x LSB(7:0)).
10 = Headphone volume slews from code 0x00 to 0x28
in 63ms.
f
LRCLK
ICLK
LRCLK MSB Divider (MSB(14:8))
11 = Headphone volume slews from code 0x00 to 0x28
in 42ms.
MSB(14:8) and LSB(7:0) are used to determine f
LRCLK
when in noninteger mode only (see the DAC Operating
Modes section). For nonintegger mode:
Program SR(1:0) to set the rate that the MAX9850 uses to
slew between two volume settings. The slew-rate control
also controls the amount of time the headphone outputs
take to mute or shut down after the command is given.
22
2
× f
LRCLK
N
=
MSB,LSB
f
ICLK
Charge-Pump Clock Divider (CP(4:0))
LRCLK LSB Divider (LSB(7:0))
CP(4:0) controls the charge-pump clock divider. The
LSB(7:0) combined with MSB(14:8) sets the LRCLK
divider when the MAX9850 is configured in noninteger
charge-pump clock frequency (f
either ICLK or from the internal oscillator.
) is derived from
CPCLK
mode. Only LSB(7:0) is used to determine f
the MAX9850 is configured in integer mode. See the DAC
Operating Modes section.
when
LRCLK
Program CP(4:0) = 0x00 to enable the 667kHz internal
oscillator. This allows the headphone amplifiers and line
outputs to operate when the DAC is disabled.
Digital Audio Register
Programming CP(4:0) to any value other than 0x00
disables the internal oscillator and derives the charge-
pump clock from ICLK. Program CP(4:0) with a value that
creates a 667kHz ±20% charge-pump clock from ICLK by
the following equation:
Table 20. Digital Audio (0xA) Read/Write,
Bit Descriptions
B7
B6
B5
B4
B3
B2
B1
B0
f
MCLK
MAS INV BCINV
LSF
DLY
RTJ
WS(1:0)
f
=
CP
2×
×SF
NCP( 4:0 )
Master Mode (MAS)
where:
1 = Configure the MAX9850 to master mode.
0 = Configure the MAX9850 to slave mode.
f
= MCLK frequency.
MCLK
Set MAS = 1 to configure the MAX9850 to master mode.
The LRCLK and BCLK are generated by the MAX9850
when in master mode. Set MAS = 0 to configure the
MAX9850 as a digital audio slave that accepts LRCLK
and BCLK from an external digital audio source.
N
= decimal value of CP(4:0). N
must be
CP(4:0)
CP(4:0)
greater than 1 when deriving the charge-pump clock from
I
.
CLK
f
= charge-pump clock frequency. Program f
=
CP
CP
667kHz ±20% for proper operation.
LRCLK Invert (INV)
SF = MCLK scale factor. SF is the decimal value of
IC(1:0) + 1.
1 = Left audio data is clocked in when LRCLK is high and
right data is clocked in when LRCLK is low.
LRCLK MSB and LRCLK LSB Registers
0 = Left audio data is clocked in when LRCLK is low and
right data is clocked in when LRCLK is high.
Table 19. LRCLK MSB (0x8) and LRCLK
LSB (0x9) Read/Write, Bit Descriptions
2
Set INV = 0 to conform to the I S standard.
Bit Clock Invert (BCINV)
B7
B6
B5
B4
B3
B2
B1
B0
1 = Digital data at SDIN latches in on the falling edge of
BCLK.
INT
MSB(14:8)
0 = Digital data at SDIN latches in on the rising edge of
BCLK.
LSB(7:0)
2
Set BCINV = 0 to conform to the I S standard.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
The MAX9850 can accept right- or left-justified data when
operating in slave mode with extra BCLK pulses beyond
what is programmed by the WS(1:0) bits. When using the
Least Significant Bit First (LSF)
1 = Accepts audio data LSB first.
0 = Accepts audio data MSB first.
2
I S standard, audio data MSBit must latch into SDIN on
2
Set LSF = 0 to conform to the I S standard.
the second BCLK rising edge following an LRCLK transition.
See Figure 4 for the various relationships between clock
and data that are supported by the MAX9850.
SDIN Delay (DLY)
1 = Audio data is latched into the MAX9850 on the second
rising BCLK edge after LRCLK transitions.
0 = Audio data is latched into the MAX9850 on the first
rising BCLK edge after LRCLK transitions
The MAX9850 can be configured to accept 16, 18, 20,
or 24-bit data. The MAX9850 generates exactly the
programmed number of BCLK cycles when in master
mode. Program the audio data word size with WS(1:0)
(register 0xA, bit B0 and B1) according to Table 22 to
ensure that the MAX9850 outputs the correct number of
BCLK cycles to accommodate the input word.
2
Set DLY = 1 to conform to the I S standard.
Right-Justified Data (RTJ)
1 = Audio data is right justified.
0 = Audio data is left justified.
2
2
I S data is left justified. Set RTJ = 0 to conform to the I S
standard.
Table 22. Audio Data Word Size
WS(1:0)
0x0
DATA WORD SIZE (BITS)
Word Length Select (WS(1:0))
16
18
20
24
00 = Audio data word length is 16 bits.
01 = Audio data word length is 18 bits.
10 = Audio data word length is 20 bits.
11 = Audio data word length is 24 bits.
0x1
0x2
0x3
Program WS(1:0) to select the input data word length.
Programming the audio data word length ensures
that the correct number of BCLK cycles are output to
accommodate the incoming data word.
The internal digital processing resolution is 18 bits wide.
Data words longer than 18 bits will be truncated. Zeros
are internally programmed into the missing bit positions
when the data word is shorter than the programmed word
size.
Digital Audio Interface
The MAX9850 receives serial digital audio data through
a 3-wire interface. The data can be right or left justified,
MSB or LSB first, or I S compatible. The 3-wire serial
2
I C-Compatible Serial Interface
2
2
The MAX9850 features an I C/SMBus™-compatible,
2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate
communication between the MAX9850 and the master
at clock rates up to 400kHz. Figure 5 shows the 2-wire
interface timing diagram. The master generates SCL and
initiates data transfer on the bus.
bus carries two time-multiplexed audio data channels
(SDIN), a channel-select line (LRCLK), and a bit clock
line (BCLK). The configuration of the audio interface is
controlled with the digital audio register, see Table 20.
Typical digital audio formats, and the required digital
audio register code, are listed in Table 21. Figure 4
illustrates the difference between right justified, left
A master device writes data to the MAX9850 by transmitting the
proper slave address followed by the register address and
then the data word. Each transmit sequence is framed
by a START (S) or REPEATED START (Sr) condition
and a STOP (P) condition. Each word transmitted to the
MAX9850 is 8 bits long and is followed by an acknowledge
clock pulse.
2
justified, and I S compatible audio data.
Table 21. Typical Digital Audio Formats
DIGITAL AUDIO REGISTER
FORMAT
CODE (0xA)
Left-Justified Audio Data
Right-Justified Audio Data
X0000000
X0000100
X0001000
2
I S-Compatible Audio Data
The MAX9850 generates the BCLK and the LRCLK from
ICLK when in master mode, see the Internal Timing
section. In slave mode, the MAX9850 accepts an LRCLK
and BCLK from an external digital audio source.
SMBus is a trademark of Intel Corp.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
2
I S
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00001000
LEFT
8
RIGHT
LRCLK
SDIN
X
15 14 13 12 11 10
9
7
6
5
4
3
2
1
0
X 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCLK
LEFT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000000
LEFT
7
RIGHT
LRCLK
SDIN
15 14 13 12 11 10
9
8
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6 5 4 3 2 1 0
BCLK
RIGHT-JUSTIFIED
DIGITAL AUDIO REGISTER (0xA)
CONTENTS = 00000100
LEFT
RIGHT
LRCLK
SDIN
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BCLK
Figure 4. Right-Justified, and Left-Justified Audio Data Formats (Slave Mode, 16-Bit Data)
SDA
t
BUF
t
t
HD, STA
SU, DAT
t
t
SP
HD, STA
t
SU, STO
t
t
HD, DAT
LOW
SCL
t
HIGH
t
HD, STA
t
R
t
F
START
CONDITION
REPEATED
START
STOP
START
CONDITION CONDITION
CONDITION
Figure 5. 2-Wire Interface Timing Diagram
A master reading data from the MAX9850 transmits the
proper slave address followed by a series of nine SCL
pulses. The MAX9850 transmits data on SDA in sync with
the master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START or REPEATED START condition, a
not acknowledge, and a STOP condition.
in a single-master system has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX9850
from high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high are
control signals (see the START and STOP Conditions sec-
SDA operates as both an input and an open-drain output.
Aꢀpullupꢀresistor,ꢀtypicallyꢀgreaterꢀthanꢀ500Ω,ꢀisꢀrequiredꢀ
on the SDA bus. SCL operates as an input only. A pullup
resistor,ꢀtypicallyꢀgreaterꢀthanꢀ500Ω,ꢀisꢀrequiredꢀonꢀSCLꢀ
if there are multiple masters on the bus, or if the master
2
tion). SDA and SCL idle high when the I C bus is not busy.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Table 23. MAX9850 Address Map
S
Sr
P
MAX9850 SLAVE ADDRESS
ADD
A6
A5
A4
A3
A2
A1
A0 R/W
SCL
GND
AV
0
0
1
0
0
0
0
1
1
X
X
X
0
0
1
0
0
0
DD
SDA
0
0
1
0
0
1
SDA
X = Don’t Care.
Slave Address
The MAX9850 is programmable to one of three slave
addresses (see Table 23). These slave addresses are
Figure 6. START, STOP, and REPEATED START Conditions
unique device IDs. Connect ADD to GND, AV , or SDA
DD
2
to set the I C slave address. The address is defined as
CLOCK PULSE FOR
ACKNOWLEDGMENT
the seven most significant bits (MSBs) followed by the
Read/Write bit. Set the Read/Write bit to 1 to configure
the MAX9850 to read mode. Set the Read/Write bit to 0
to configure the MAX9850 to write mode. The address is
the first byte of information sent to the MAX9850 after the
START condition.
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
Acknowledge
ACKNOWLEDGE
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9850 uses to handshake receipt of each byte of
data when in write mode (see Figure 7). The MAX9850
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master
may retry communication.
Figure 7. Acknowledge
Start and Stop Conditions
SDA and SCL idle high when the bus is not in use. A master
initiates communication by issuing a START condition. A
START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition on
SDA while SCL is high (Figure 6). A START condition from
the master signals the beginning of a transmission to the
MAX9850. The master terminates transmission, and frees
the bus, by issuing a STOP condition. The bus remains
active if a REPEATED START condition is generated
instead of a STOP condition.
The master pulls down SDA during the 9th clock cycle
to acknowledge receipt of data when the MAX9850 is in
read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not-
acknowledge is sent when the master reads the final byte
of data from the MAX9850, followed by a STOP condition.
Early STOP Conditions
The MAX9850 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
within one continuous frame. Figure 9 illustrates how to
write to multiple registers with one frame. The master signals
the end of transmission by issuing a STOP condition.
Write Data Format
A write to the MAX9850 includes transmission of a START
condition, the slave address with the R/W bit set to 0
(see Table 23), one byte of data to configure the internal
register address pointer, one or more bytes of data, and
a STOP condition. Figure 8 illustrates the proper frame
format for writing one byte of data to the MAX9850. Figure
9 illustrates the frame format for writing n-bytes of data to
the MAX9850.
Register addresses greater than 0xA are reserved. Do not
write to these addresses.
Read Data Format
Send the slave address with the R/W bit set to 1 to initiate
a read operation. The MAX9850 acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read command
resets the address pointer to register 0x0. The first byte
transmitted from the MAX9850 will be the contents of
register 0x0. Transmitted data is valid on the rising edge
of the master-generated serial clock (SCL). The address
pointer autoincrements after each read data byte. This
autoincrement feature allows all registers to be read
sequentially within one continuous frame.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9850.
The MAX9850 acknowledges receipt of the address byte
during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the MAX9850’s internal register address pointer. The
pointer tells the MAX9850 where to write the next byte
of data. An acknowledge pulse is sent by the MAX9850
upon receipt of the address pointer data.
A STOP condition can be issued after any number of
read data bytes. If a STOP condition is issued followed by
another read operation, the first data byte to be read will
be from register 0x0 and subsequent reads will autoincrement
the address pointer until the next STOP condition.
The third byte sent to the MAX9850 contains the data that
will be written to the chosen register. An acknowledge
pulse from the MAX9850 signals receipt of the data byte.
The address pointer autoincrements to the next register
address after each received data byte. This autoincrement
feature allows a master to write to sequential registers
ACKNOWLEDGE FROM MAX9850
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9850
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9850
REGISTER ADDRESS
A
P
S
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 8. Writing One Byte of Data to the MAX9850
ACKNOWLEDGE FROM MAX9850
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9850
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9850
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9850
REGISTER ADDRESS
A
A
P
S
0
A
A
1st DATA BYTE
1 BYTE
Nth DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 9. Writing n-Bytes of Data to the MAX9850
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
NOT ACKNOWLEDGE FROM MASTER
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9850
ACKNOWLEDGE FROM MAX9850
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9850
REGISTER ADDRESS
A
P
S
0
A
A
Sr SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Reading One Byte of Data from MAX9850
NOT ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE FROM MASTER
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9850
ACKNOWLEDGE FROM MAX9850
ACKNOWLEDGE FROM MAX9850
REGISTER ADDRESS
A
A
P
S
0
A
A
Sr
1
A
SLAVE ADDRESS
SLAVE ADDRESS
FIRST DATA BYTE
Nth DATA WORD
1 BYTE
R/W
REPEATED START
R/W
1 BYTE
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 11. Reading n-Bytes from MAX9850
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9850’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent
followed by the slave address with the R/W bit set to
1. The MAX9850 transmits the contents of the specified
register. The address pointer autoincrements after trans-
mitting the first byte. Attempting to read from register
addresses higher than 0xB results in repeated reads of
0xB. Note that 0xB is a reserved register.
desired circuit functions on the MAX9850. Finally, the
global shutdown bit, SHDN needs to be set to 1 (register
0x5, bit B7). The enable bits can all be set with a single
2
I C write operation.
2
It is good practice for an application to configure the I C
registers before taking the MAX9850 out of shutdown.
This may include setting initial volume levels, DAC
mode of operation, stereo or mono operation, and audio
interface settings. Powering on the MAX9850 with all the
registers set ensures that the audio output will not be
interrupted.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not-acknowledge
from the master and then a STOP condition. Figure 10
illustrates the frame format for reading one byte from the
MAX9850. Figure 11 illustrates the frame format for
reading multiple bytes from the MAX9850.
The charge pump starts and establishes the internal
supply voltages once the appropriate byte is written to
the enable register. The MAX9850 is ready for operation
approximately 10ms after the charge pump is enabled.
If selected, the headphone outputs will also complete a
clickless/popless power-up sequence during this time.
The headphone amplifier status bit (SHP) (register 0x1,
bit B3) sets to 1 once the headphones are ready to
operate. The line inputs and outputs will also turn on
during this 10ms startup period if enabled.
Applications Information
Powering On/Off the MAX9850
Let AC-coupling capacitors settle before enabling the line
input amplifiers. The input-coupling capacitor charges to
the output bias voltage of the driving device even while
the MAX9850 is in shutdown. The input AC coupling
capacitors are charged and ready for use immediately
after power is applied to the system in most applications.
The MAX9850 powers on in low-power shutdown mode
with the DAC, headphones, line inputs, and outputs all
disabled. For useful circuit operation to be available, the
charge pump needs to be activated using CPEN(1:0) in
the enable register (register 0x5, bits B5 and B4). Setting
the appropriate bits in the enable register will enable the
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
1.8V TO 3.6V
1µF
1µF
1µF
3.3V TO 5.5V
0.47µF
V
DD
DV
DD
PV
DD
AV
DD
SCL
OUTL
INL+
INL-
OUTR+
OUTR-
µC
SDA
REF
0.47µF
MAX9701*
1µF
MAX9850
0.47µF
INR+
INR-
OUTL+
OUTL-
C1P
OUTR
GPIO
DV
DD
0.47µF
C1N
0.47µF
SHDN
PGND
MCLK
10kΩ
DIGITAL
AUDIO
SOURCE
SDIN
BCLK
LRCLK
HPL
HPS
HPR
PV
SS
SV
SS
PGND DGND AGND
2.2µF
*FUTURE PRODUCT—CONTACT FACTORY FOR AVAILABILITY.
Figure 12. Stereo Speakerphone
The DAC begins its soft-start routine after being enabled
and after receiving 32 LRCLK cycles. All internal filters are
initialized and the DAC gain gradually ramps to maximum.
The MAX9850’s headphone output level is determined by
the headphone amplifier volume setting.
Stereo Speakerphone
The MAX9850 can be combined with a stereo speaker
amplifier to create a complete speakerphone playback
solution. The MAX9701, or another Maxim stereo speaker
amplifier, can be used to drive the speakers while the
MAX9850’s integrated DirectDrive headphone amplifier
drives the headphones (see Figure 12).
Mute the audio outputs before powering down the
MAX9850 by setting MUTE to 1 (register 0x2, bit B7).
Ramping the volume to its maximum attenuation is an
alternative to muting the output. VMN in the status A
register (register 0x0, bit B3) notifies the µC when the
outputs are at maximum attenuation. Disable the head-
phone and line outputs once the audio is fully attenuated.
Headphone and line outputs can be disabled within 50’s
without any audible clicks or pops, once the audio is fully
attenuated. Place the MAX9850 in shutdown after the
outputs are disabled.
Configure GPIO to output high when a headphone is not
connected and low when the headphone is connected.
Connect GPIO to the SHDN control of the MAX9701.
Configure the interrupt enable register to set ALERT
(register 0x0, bit B7) when HPS changes state. The µC
polls the status A register and waits for ALERT to set
when HPS changes state. The µC changes the state of
GPIO when ALERT is set, either turning off the speaker
amp because a headphone is connected or enabling the
speaker amp when the headphone is disconnected.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
1.8V TO 3.6V
1µF
3.3V TO 5.5V
0.47µF
0.47µF
V
DD
1µF
1µF
INL+
INL-
OUTR+
OUTR-
0.47µF
0.47µF
0.47µF
DV
PV
DD
AV
DD
DD
MAX9701*
INL
OUTL
OUTR
BASEBAND
IC
INR+
INR-
OUTL+
OUTL-
DV
DD
INR
REF
C1P
1µF
0.47µF
MAX9850
SHDN
PGND
0.47µF
10kΩ
SCL
SDA
C1N
GPIO
HPL
HPS
HPR
APPLICATIONS
PROCESSOR
MCLK
SDIN
BCLK
LRCLK
PV
SV
SS
PGND DGND AGND
SS
*FUTURE PRODUCT—CONTACT FACTORY FOR AVAILABILITY.
2.2µF
Figure 13. Cell Phone Audio
Cell Phone Audio
PC Board Layout and Bypassing
The MAX9850 is a complete cell-phone audio playback
solution. In a typical application, ringtones are created
and output through the application’s processor on the
digital audio bus. Connect the baseband IC to the line
inputs of the MAX9850, INR and INL. The headphone
amplifier outputs a summed version of the digital audio
input and the line input (see Figure 13).
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply inputs
and amplifier outputs to minimize losses due to parasitic
trace resistance. Large traces also aid in moving heat
away from the package. Proper grounding improves audio
performance, minimizes crosstalk between channels, and
prevents any switching noise from coupling into the audio
signal. Connect PGND, DGND, and AGND together at a
single point on the PC board. Route DGND, PGND, and
all traces that carry switching transients or digital signals
away from AGND and traces or components in the analog
audio-signal path.
Headphone Short Circuit
The headphone amplifiers can provide almost ±300mA
per channel during a short-circuit event. The MAX9850
has been designed to withstand this current continuously.
To avoid unnecessarily draining a battery, it is advised
to enable the IOHR and IOHL hardware interrupt. The
µC can service the interrupt by disabling the headphone
amplifiers and waiting for a timeout period.
Connect all components associated with the charge
pump to PGND. Connect PV
and SV
together at
SS
SS
the device. Place the charge-pump capacitors as close
to PV as possible. Ensure C2 is connected to PGND.
SS
A headphone short-circuit event on the right channel
only may also indicate that a mono headphone has been
inserted into the stereo socket. The µC can then automati-
cally disable the right channel by placing the MAX9850 in
mono mode. This resolves a mono jack-induced, short-
circuit condition.
Bypass PV
capacitors as close to the device as possible.
with 1µF to PGND. Place the bypass
DD
The MAX9850 thin QFN package features an exposed
thermal pad on its underside. This pad lowers the
package’s thermal resistance by providing a direct heat
conduction path from the die to the printed circuit board.
If possible, connect the exposed thermal pad to an
electrically isolated, large pad of copper. If it cannot be left
floating, connect it to AGND.
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Pin Configuration
Chip Information
TRANSISTOR COUNT: 104,069
PROCESS: BiCMOS
TOP VIEW
21 20
19
18 17 16 15
PV
AGND
REF
22
14
13
12
SS
C1N 23
PGND 24
C1P 25
OUTL
MAX9850
11 OUTR
26
27
10
9
PV
INL
DD
SCL
INR
SDA 28
8
GPIO
+
1
2
3
4
5
6
7
TQFN
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 QFN
T2855+6
21-0140
90-0026
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MAX9850
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
Updated Typical Operating Characteristics
NUMBER
DATE
4
8/19
11
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2019 Maxim Integrated Products, Inc.
│ 36
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