MAX9879_V01 [MAXIM]
Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier;
| 型号： | MAX9879_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier |
| 文件： | 总32页 (文件大小：575K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
General Description
Features
The MAX9879 combines a high-efficiency stereo Class D
audio power amplifier with a stereo capacitor-less
DirectDrive® headphone amplifier. Maxim’s filterless class
D amplifiers with active emissions limiting technology pro-
vide Class AB performance with Class D efficiency.
o Better than 9dB Margin Under EN 55022 Class B
Limits with No Filter Components
o Low RF Susceptibility Design Rejects TDMA
Noise from GSM Radios
o Input Mixer with User Defined Input Mode
The Class D power amplifier delivers up to 715mW from
a 3.7V supply into an 8Ω load with 88% efficiency to
extend battery life. The filterless modulation scheme
combined with active emission limiting circuitry and
spread-spectrum modulation greatly reduces EMI while
eliminating the need for output filtering used in tradition-
al Class D devices.
The headphone amplifier delivers up to 58mW from
a 3.7V supply into a 16Ω load. Maxim’s DirectDrive
architecture produces a ground-referenced output from
a single supply, eliminating the need for large DC-
blocking capacitors, saving cost, space and compo-
nent height.
The device utilizes a user-defined input architecture,
three preamplifier gain settings, an input mixer, volume
control, comprehensive click-and-pop suppression, and
I2C control. A bypass mode feature disables the integrat-
ed Class D amplifier and utilizes an internal DPST switch
to allow an external amplifier to drive the speaker that is
connected at the outputs of the MAX9879.
o Stereo 715mW Speaker Output (R = 8Ω,
L
V
DD
= 3.7V)
o Stereo 58mW Headphone Output (16Ω,
V
= 3.7V)
DD
o Low 0.04% THD+N at 1kHz (Class D Power
Amplifier)
o Low 0.018% THD+N at 1kHz (Headphone
Amplifier)
o 88% Efficiency (R = 8Ω, P
= 750mW)
L
OUT
o 1.6Ω Analog Switch for Speaker Amplifier Bypass
o High Speaker Amplifier PSRR (72dB at 217Hz)
o High Headphone Amplifier PSRR (84dB at 217Hz)
o I2C Control
o Hardware and Software Shutdown Mode
o Ultra-Low Click and Pop
o Robust Design with Current and Thermal
Protection
o Available in Space-Saving Package
5x6 UCSP (2.5mm x 3mm)
The MAX9879 is available in a thermally efficient,
space-saving 30-bump UCSP™ package.
Ordering Information
Applications
Portable Multimedia Players
PART
TEMP RANGE
PIN-PACKAGE
Cell Phones
MAX9879ERV+
-40°C to +85°C
30 UCSP (5x6)
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
+Denotes a lead(Pb)-free/RoHS-compliant package.
UCSP is a trademark of Maxim Integrated Products, Inc.
Pin Configuration
Simplified Block Diagram
TOP VIEW
(BUMP SIDE DOWN)
SINGLE SUPPLY
2.7V TO 5.5V
2
3
4
1
5
6
A
VOLUME
PREAMPLIFIER
CONTROL
C1P
C1N
OUTL- PVDDL
OUTL+
RXIN+
PGNDR OUTR-
PGNDR PVDDR
MIXER
B
RXIN-
PGNDL
VOLUME
2
I C
CONTROL
INTERFACE
C
D
E
V
GND
BIAS
GND
INB1
INB2
GND
INA1
INA2
GND
SCL
OUTR+
SDA
SS
HPL
HPR
BYPASS
V
SHDN
V
DD
CCIO
MAX9879
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-4436; Rev 1; 4/13
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ABSOLUTE MAXIMUM RATINGS
V
V
V
V
, PVDDL, PVDDR to GND ..................................-0.3V to +6V
, PVDDL to PVDDR .........................................-0.3V to +0.3V
to PVDDL .......................................................-0.3V to +0.3V
Continuous Current In/Out of HPR and HPL.....................140mA
Continuous Current In/Out of RXIN+ and RXIN-...............150mA
DD
DD
DD
Continuous Input Current V ...........................................100mA
SS
to GND...........................................................-0.3V to +4V
Continuous Input Current (All Other Pins) ........................ 20mA
Duration of OUT_ Short Circuit
CCIO
PGNDL, PGNDR, to GND......................................-0.3V to +0.3V
PGNDL to PGNDR.................................................-0.3V to +0.3V
to PGND_ or PVDD_...............................................Continuous
Duration of Short Circuit
V
SS
to GND...............................................................-6V to +0.3V
C1N to GND................................................(V - 0.3V) to +0.3V
C1P to GND...........................................-0.3V to (PVDD_ + 0.3V)
Between OUT_+ and OUT_- ..................................Continuous
Duration of HP_ Short Circuit to GND or PVDDL........Continuous
SS
HPL, HPR to V (Note 1).............................-0.3V to the lower of
Continuous Power Dissipation (T = +70°C)
5x6 UCSP Multilayer Board
SS
A
(V
- V + 0.3V) or +9V
DD
SS
HPL, HPR to V
(Note 2) .........................+0.3V to the higher of
(derate 16.5mW/°C above +70°C).............................1250mW
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
(V - PVDD_ - 0.3V) or -9V
SS
INA1, INA2, INB1, INB2, BIAS..................................-0.3V to +4V
SDA, SCL, SHDN......................................................-0.3V to +4V
All Other Pins to GND............................-0.3V to (PVDD_ + 0.3V)
Continuous Current In/Out of PVDD_, PGND_, OUT_ .... 800mA
Note 1: HPR and HPL should be limited to no more than 9V above V , or above PV + 0.3V, whichever limits first.
SS
DD
Note 2: HPR and HPL should be limited to no more than 9V below PV , or below V - 0.3V, whichever limits first.
DD
SS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0, volume controls =
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
PGNDR
0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to
GND. R
(Notes 3, 4)
= ∞, R = ∞. C1 = C2 = C
= 1µF. T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SPK
HP
BIAS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
Guaranteed by PSRR Test
MIN
2.7
TYP
MAX
UNITS
V
,
DD
Analog Supply Voltage Range
Digital Supply Voltage Range
5.5
V
V
PVDDR
PVDDL
V
1.7
3.6
9.0
18
10
24
10
CCIO
HP mode, R = ∞
5.6
9.8
6.6
13.2
5
HP
Stereo SPK mode, R
= ∞
SPK
Quiescent Current
Shutdown Current
I
mA
µA
DD
Mono SPK mode, R
= ∞
SPK
Stereo SPK + HP mode, R = R
= ∞
HP
SPK
I
= I
+ I
PVDDR
;
CC
Software shutdown
SHDN
DD
+ I
I
+ I
T
SHDN
PVDDL
= +25°C
Hardware shutdown
0.1
10
1
A
Time from shutdown or power-on to full
operation
Turn-On Time
t
ms
ON
T
= +25°C, preamp = 0dB or +5.5dB
= +25°C, preamp = +20dB
Preamp = 0dB
11
3
21
5.5
31
8
A
A
Input Resistance
R
kΩ
IN
T
2.3
Headphone amplifier
path
Preamp = +5.5dB
Preamp = +20dB
Preamp = 0dB
1.2
0.23
1.2
Maximum Input Signal Swing
V
P-P
Speaker amplifier path
Preamp = +5.5dB
Preamp = +20dB
0.64
0.12
2
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0, volume controls =
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
PGNDR
0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to
GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = T to T , unless otherwise noted. Typical values are at T = +25°C.)
SPK
HP
BIAS
A
MIN
MAX
A
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
58
MAX
UNITS
Preamp = 0
f
= 1kHz (differential
IN
Common-Mode Rejection Ratio
CMRR
dB
Preamp = 5.5dB
Preamp = 20dB
55
input mode)
43
Input DC Voltage
Bias Voltage
IN__ inputs
1.22
1.13
1.3
1.2
1.38
V
V
V
1.272
BIAS
SPEAKER AMPLIFIER
T
T
= +25°C (volume at mute)
0.5
4.5
4
mV
mV
A
Output Offset Voltage
Click-and-Pop Level
V
OS
= +25°C (volume at 0dB, ENA = 1 and
A
ENB = 0 or ENB = 1 and ENA = 0, ΔIN_ = 0)
Peak voltage,
Into shutdown
-70
-70
76
72
68
55
T
A
= +25°C
K
A-weighted, 32 samples
per second, volume at
mute (Note 5)
dBV
CP
Out of shutdown
PVDD_ = V
DD
50
= 2.7V to 5.5V
f = 217Hz,
100mV
ripple
ripple
ripple
P-P
Power-Supply Rejection Ratio
(Note 5)
PSRR
T
A
= +25°C
dB
f = 1kHz,
100mV
P-P
f = 20kHz,
100mV
P-P
V
V
V
= 3.7V
= 3.3V
= 3.0V
715
565
470
DD
DD
DD
THD+N ≤ 1%, R
8Ω
=
SPK
Output Power
P
mW
%
OUT
f = 1kHz, P
= 350mW, T = +25°C,
A
OUT
Total Harmonic Distortion + Noise
THD+N
0.04
92
0.2
R
SPK
= 8Ω
ΔIN_ = 0
(single-ended)
A-weighted, ENA = 1
and ENB = 0 or ENB = 1
and ENA = 0
ΔIN_ = 1
(differential)
94
Signal-to-Noise Ratio
SNR
dB
ΔIN_ = 0
(single-ended)
88
A-weighted ENA =
ENB = 1
ΔIN_ = 1
(differential)
92
700
40
Output Frequency
Maxim Integrated
kHz
3
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0, volume controls =
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
PGNDR
0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to
GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = T to T , unless otherwise noted. Typical values are at T = +25°C.)
SPK
HP
BIAS
A
MIN
MAX
A
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1.5
88
MAX
UNITS
A
Current Limit
Efficiency
η
P
= 600mW, f = 1kHz
%
OUT
Speaker Gain
A
V
17.4
18
18.4
dB
A-weighted, (ENA = 1 and ENB = 0
or ENA = 0 and ENB = 1), ΔIN_ = 0
Output Noise
63
75
µV
RMS
OUTL to OUTR, OUTR to OUTL,
f = 20Hz to 20kHz
Crosstalk
dB
HEADPHONE AMPLIFIERS
T
T
= +25°C (volume at mute)
0.22
1.5
0.85
mV
mV
A
Output Offset Voltage
V
OS
= +25°C (Volume at 0dB, ENA = 1 and
A
ENB = 0 or ENA = 0 and ENB = 1, ΔIN_ = 0)
Peak voltage, T = 25°C Into shutdown
A
A-weighted, 32 samples
-75
-75
Click-and-Pop Level
K
dBV
CP
per second, volume at
mute (Note 5)
Out of shutdown
PVDD_ = V
= 2.7V to 5.5V
f = 217Hz,
DD
70
85
84
V
RIPPLE
= 100mV
f = 1kHz,
P-P
Power-Supply Rejection Ratio
(Note 5)
PSRR
T
A
= +25°C
dB
80
62
V
RIPPLE
= 100mV
P-P
f = 20kHz,
V
RIPPLE
= 100mV
P-P
R
= 16Ω
= 32Ω
58
54
3
HP
HP
Output Power
P
THD+N = 1%
mW
dB
OUT
R
Headphone Gain
A
2.6
3.4
2.5
V
T
A
= +25°C, HPL to HPR, volume at 0dB,
ENA=1 and ENB = 0 or ENA = 1 and ENB
Channel-to-Channel Gain
Tracking
0.3
%
= 0, ΔIN_ = 0
R
(P
= 32Ω
HP
0.018
0.037
= 10mW, f = 1kHz)
OUT
Total Harmonic Distortion + Noise
THD+N
%
R
HP
= 16Ω
0.08
(P
= 10mW, f = 1kHz)
OUT
4
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0, volume controls =
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
PGNDR
0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to
GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = T to T , unless otherwise noted. Typical values are at T = +25°C.)
SPK
HP
BIAS
A
MIN
MAX
A
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ENA = 1 and
ENB = 0 or
ENA = 1 and
ENB = 0
ΔIN_ = 0
ΔIN_ = 1
98
A-weighted,
= 16Ω
98
Signal-to-Noise Ratio
SNR
dB
R
HP
ΔIN_ = 0
ΔIN_ = 1
96
96
ENA = 1 and
ENB = 1
Slew Rate
SR
0.35
100
67
V/µs
pF
Capacitive Drive
Crosstalk
C
L
HPL to HPR, HPR to HPL, f = 20Hz to 20kHz
dB
350
20
Charge-Pump Frequency
kHz
VOLUME CONTROL
Minimum Setting
_VOL = 1
-75
0
dB
dB
Maximum Setting
_VOL = 31
PGAIN_ = 00
0
Input Gain
Input A or B
PGAIN_ = 01
PGAIN_ = 10
Speaker
5.5
20
100
110
dB
Mute Attenuation
f = 1kHz, _VOL = 0
ZCD = 1
dB
ms
Headphone
Zero-Crossing Detection Time
Out
60
ANALOG SWITCH
I
= 20mA,
RXIN__
T
T
= +25°C
2.4
4
A
On-Resistance
R
ON
RXIN_ = 0 and V
BYPASS = 1
Ω
DD,
= T
to T
5.2
A
MIN
MAX
Series resistance is
10Ω per switch
V
V
= 2V
= V /2,
DD
,
DIFRXIN
CMRXIN
P-P
0.3
0.3
0.25
%
Total Harmonic Distortion + Noise
Off-Isolation
f = 1kHz, BYPASS = 1
No series resistors
BYPASS = 0, RXIN+ and RXIN- to GND =
50Ω, R = 8Ω, f = 10kHz, referred to
speaker output signal
88
dB
V
SPK
DIGITAL INPUTS (SDA, SCL, SHDN)
0.7 x
Input Voltage High (SDA, SCL)
V
IH
V
CCIO
0.3 x
Input Voltage Low (SDA, SCL)
Input Hysteresis (SDA, SCL)
V
V
IL
V
CCIO
V
200
mV
HYS
Maxim Integrated
5
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0, volume controls =
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
PGNDR
0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to
GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = T to T , unless otherwise noted. Typical values are at T = +25°C.)
SPK
HP
BIAS
A
MIN
MAX
A
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage High (SHDN)
Input Voltage Low (SHDN)
Input Hysteresis (SHDN)
V
1.4
V
V
IH
V
0.4
IL
V
100
10
mV
HYS
SDA, SCL, SHDN Input
Capacitance
C
pF
IN
Input Leakage Current
I
I
SDA, SCL, SHDN, T = +25°C
1.0
1.0
µA
µA
IN
IN
A
Input Leakage Current
V
= 0, T = +25°C
CCIO A
DIGITAL OUTPUTS (SDA open drain)
Output Low-Voltage SDA
V
I
I
= 3mA
= 3mA
0.4
V
V
OL
SINK
V
-
CCIO
0.4
Output High-Voltage SDA
V
OH
SINK
V
to V
bus capacitance
L(MAX)
H(MIN)
Output Fall Time SDA
t
250
ns
OF
= 10pF to 400pF, I
= 3mA
SINK
2-WIRE INTERFACE TIMING
External Pullup Voltage Range
(SDA and SCL)
1.7
DC
1.3
3.6
V
Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
BUF
START Condition Hold
START Condition Setup Time
Clock Low Period
t
0.6
0.6
1.3
0.6
100
0
µs
µs
µs
µs
ns
ns
HD:STA
t
SU:STA
t
LOW
Clock High Period
Data Setup Time
t
HIGH
t
SU:DAT
HD:DAT
Data Hold Time
t
900
300
20 +
0.1 x C
SCL/SDA Receiving Rise Time
SCL/SDA Receiving Fall Time
t
(Note 6)
ns
ns
R
B
20 +
0.1 x C
t
300
F
F
B
B
20 +
0.1 x C
V
V
=1.8V (Note 6)
250
250
CCIO
CCIO
SDA Transmitting Fall Time
t
ns
20 +
0.05 x C
= 3.6V (Note 6)
B
6
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume controls =
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
PGNDR
0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL or HPR to
GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = T to T , unless otherwise noted. Typical values are at T = +25°C.)
SPK
HP
BIAS
A
MIN
MAX
A
(Notes 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
0.6
0
TYP
MAX
UNITS
µs
Set-Up Time for STOP Condition
Pulse Width of Spike Suppressed
t
SU:STO
t
50
ns
SP
Capacitive Load for Each Bus
Line
C
400
pF
B
Note 3: All devices are 100% production tested at T = +25°C. All temperature limits are guaranteed by design.
A
Note 4: Class D amplifier testing performed with a resistive load in series with an inductor to simulate an actual speaker load. For
= 8Ω, L = 68mH.
R
SPKR
Note 5: Amplifier inputs are AC-coupled to GND.
Note 6: C is in pF.
B
Maxim Integrated
7
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R
= ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS A
GENERAL
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
10
8
16
14
12
10
8
20
18
16
14
12
10
8
STEREO-SPEAKER MODE
HEADPHONE + STEREO-SPEAKER MODE
HEADPHONE MODE
6
4
6
4
2
2
6
0
0
4
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
VOLUME LEVEL vs. VOLUME STEP
16
14
12
10
8
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
SOFTWARE-SHUTDOWN MODE
f
IN
= 1kHz
HARDWARE-SHUTDOWN MODE
6
4
2
0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
0
4
8
12 16 20 24 28 32
VOLUME STEP
8
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS
A
SPEAKER AMPLIFIERS (Headphone Disabled)
THD+N vs. FREQUENCY SPEAKER
THD+N vs. FREQUENCY SPEAKER
THD+N vs. OUTPUT POWER
10
1
10
1
10
PVDD_= 3.7V
R = 8Ω
L
PVDD_= 3.0V
R = 8Ω
L
PVDD_ = 3.7V
R = 8Ω
L
1
0.1
OUTPUT POWER = 200mW
OUTPUT POWER = 100mW
f
IN
= 6kHz
0.1
0.01
0.1
0.01
f
IN
= 20Hz
f
IN
= 1kHz
800
OUTPUT POWER = 600mW
OUTPUT POWER = 400mW
0.01
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0
200
400
600
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
OUTPUT POWER (mW)
THD+N vs. OUTPUT POWER
THD+N vs. OUTPUT POWER
10
10
1
PVDD_ = 3.0V
R = 8Ω
PVDD_ = 3.7V
R = 8Ω
L
L
LEFT SPEAKER ONLY
1
0.1
f
IN
= 6kHz
f
= 6kHz
IN
0.1
f
IN
= 20Hz
f
= 1kHz
IN
f
IN
= 1kHz
800
f
IN
= 20Hz
400
0.01
0.01
0
100 200 300 400 500 600 700
OUTPUT POWER (mW)
0
200
600
1000
OUTPUT POWER (mW)
OUTPUT POWER vs. SUPPLY VOLTAGE
EFFICIENCY vs. OUTPUT POWER
2000
1800
1600
1400
1200
1000
800
100
90
80
70
60
50
40
30
20
10
0
R = 8Ω
IN
L
f
= 1kHz
THD+N = 10%
600
THD+N = 1%
400
200
f
IN
= 1kHz, R = 8Ω
L
0
2.7
3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOTAGE (V)
0
100 200 300 400 500 600 700 800 900
OUTPUT POWER (mW)
Maxim Integrated
9
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS
A
SPEAKER AMPLIFIERS (Headphone Disabled)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (SPEAKER MODE)
OUTPUT POWER vs. LOAD
CROSSTALK vs. FREQUENCY
1000
800
600
400
200
0
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
R = 8Ω
= 1
VP-P
f = 1kHz
L
R = 8Ω
L
V
IN
V
= 100mV
RIPPLE
P-P
-20
-40
INPUTS AC GROUNDED
THD+N = 10%
RIGHT
-60
RIGHT TO LEFT
THD+N = 1%
-80
LEFT
-100
-120
LEFT TO RIGHT
10 100
1
10
100
0.01
0.1
1
FREQUENCY (kHz)
0.01
0.1
1
10
100
LOAD (Ω)
FREQUENCY (kHz)
OUTPUT FREQUENCY SPECTRUM
SPEAKER MODE
WIDEBAND FREQUENCY SPECTRUM
(SPEAKER MODE)
0
-20
0
-10
V
= -60dBV
OUT
RBW = 1kHz
INPUT AC GROUNDED
f = 1kHz
R = 8Ω
L
-20
UNWEIGHTED
-30
-40
-40
-60
-50
-60
-80
-70
-80
-100
-120
-90
-100
-110
-120
-140
0
5
10
15
20
0
1
10
100
FREQUENCY (kHz)
FREQUENCY (MHz)
MAX9879 toc19
MAX9879 toc20
SDA
2V/div
SHDN
1V/div
SCL
2V/div
OUT+ - OUT-
1V/div
400μs/div
2ms/div
10
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS
A
HEADPHONE AMPLIFIERS (Speaker Disabled)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (HEADPHONE NOISE)
MAX9879 toc21
10
1
10
1
V
= 3.7V
DD
V
= 3.7V
DD
SDA
2V/div
R = 32Ω
L
R = 16Ω
L
SCL
2V/div
OUTPUT POWER = 10mW
0.1
0.1
0.01
OUTPUT POWER = 20mW
OUT+ - OUT-
1V/div
0.01
0.001
OUTPUT POWER = 40mW
OUTPUT POWER = 45mW
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
2ms/div
FREQUENCY (kHz)
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION + NOISE
vs. FREQUENCY (HEADPHONE MODE)
10
1
10
1
10
1
V
= 3.0V
V
= 3.0V
V
DD
= 3.7V
DD
DD
R = 32Ω
L
R = 16Ω
L
R = 32Ω
L
OUTPUT POWER = 7mW
f
IN
= 1kHz
OUTPUT POWER = 30mW
0.1
0.1
0.1
0.01
0.001
0.01
0.001
0.01
0.001
OUTPUT POWER = 22mW
f
= 100Hz
IN
OUTPUT POWER = 10mW
f
= 6kHz
IN
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION + NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION + NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
TOTAL HARMONIC DISTORTION + NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
10
1
100
10
100
10
V
= 3.7V
V
= 3.0V
V
DD
= 3.0V
DD
DD
R = 16Ω
L
R = 32Ω
L
R = 16Ω
L
f
IN
= 100Hz
f
IN
= 100Hz
f
IN
= 100Hz
0.1
0.1
0.1
f
IN
= 1kHz
0.01
0.001
0.01
0.001
0.01
0.001
f
IN
= 6kHz
f
IN
= 6kHz
f = 1kHz
IN
f
= 6kHz
60
f
IN
= 1kHz
20
IN
0
40
60
80
100
0
10
20
30
40
50
70
0
10
20
30
40
50
60
OUTPUT POWER (mW)
OUTPUT POWER (mW)
OUTPUT POWER (mW)
Maxim Integrated
11
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS
A
HEADPHONE AMPLIFIERS (Speaker Disabled)
TOTAL HARMONIC DISTORTION + NOISE
vs. OUTPUT POWER (HEADPHONE MODE)
POWER DISSIPATION vs. OUTPUT POWER
(HEADPHONE MODE)
OUTPUT POWER vs. SUPPLY VOLTAGE
100
10
250
225
200
175
150
125
100
75
80
75
60
50
40
30
V
= 3.7V
V
= 3.0V
DD
DD
THD+N = 10%
THD+N = 10%
0.1
R = 16Ω
L
R = 16Ω
L
0.01
0.001
20
R = 32Ω
L
50
R = 32Ω
L
R = 32Ω
L
10
0
25
f
= 1kHz
IN
0
0.1
1
10
100
0
1
10
100
2.7
3.1 3.5 3.9 4.3 4.7 5.1
SUPPLY VOLTAGE (V)
5.5
OUTPUT POWER (mW)
TOTAL OUTPUT POWER (mW)
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)
OUTPUT POWER vs. LOAD RESISTANCE
(HEADPHONE MODE)
OUTPUT POWER vs. SUPPLY VOLTAGE
160
140
120
100
80
100
90
80
70
50
30
20
100
90
80
70
60
50
40
30
20
10
0
f = 1kHz
THD+N = 1%
V
DD
= 3.3V
THD+N = 10%
f = 1kHz
THD+N = 10%
C1 = C2 = 0.47μF
THD+N = 1%
THD+N = 1%
C1 = C2 = 1μF
60
C1 = C2 = 2.2μF
40
R = 16Ω
L
20
0
10
0
f
IN
= 1kHz
2.7
3.1 3.5 3.9
4.3 4.7 5.1 5.5
10
100
10
100
SUPPLY VOTAGE (V)
LOAD RESISTANCE (Ω)
LOAD RESISTANCE (Ω)
POWER SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
CROSSTALK vs. FREQUENCY
(HEADPHONE MODE)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-20
0
-10
-20
-30
-40
-50
-60
-70
-80
V
= 100mV
P-P
V
= -60dB
RIPPLE
R = 16Ω
f = 1kHz
V = 1V
IN P-P
OUT
L
INPUTS AC GROUNDED
f =1kHz
R = 32Ω
L
-40
-60
RIGHT TO LEFT
-80
LEFT TO RIGHT
LEFT
-100
-120
-140
RIGHT
0.01
0.1
1
10
100
0
5
10
15
20
0.01
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (Hz)
12
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R = ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS
A
HEADPHONE AMPLIFIERS (Speaker Disabled)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (HEADPHONE MODE)
MAX9879 toc40
0
-10
-20
-30
-40
-50
-60
-70
-80
SHDN
1V/div
A
= +20dB
V
HP_
1V/div
A
= 0dB
0.1
A
= +5.5dB
10
V
V
0.01
1
FREQUENCY (kHz)
100
20μs/div
Maxim Integrated
13
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Operating Characteristics (continued)
(V
= V
= V
= 3.7V, V
= 1.8V, V
= V
= V
= 0. Single-ended inputs, preamp = 0dB, volume con-
PGNDR
DD
PVDDL
PVDDR
CCIO
GND
PGNDL
trols = 0dB, BYPASS = 0, SHDN = 1. Speaker loads connected between OUT_+ and OUT_-. Headphone loads connected from HPL
or HPR to GND. R
= ∞, R = ∞. C1 = C2 = C = 1µF. T = +25°C, unless otherwise noted.)
SPK
HP
BIAS A
ANALOG SWITCH
MAX9879 toc41
MAX9879 toc42
SDA
SDA
2V/div
2V/div
SCL
SCL
2V/div
2V/div
HP_
HP_
1V/div
1V/div
2ms/div
2ms/div
THD+N vs. OUTPUT POWER
BYPASS SWITCH
THD+N vs. OUTPUT POWER
BYPASS SWITCH
100
10
PVDD_ = 3.7V
R = 8Ω
NO SERIES RESISTORS
PVDD_ = 3.7V
R = 8Ω
NO SERIES RESISTORS
L
L
10
1
f
IN
= 100Hz
f
= 1kHz
IN
f
IN
= 1kHz
f
IN
= 100Hz
1
0.1
0.1
f
IN
= 6kHz
f
= 6kHz
800
IN
0.01
0.01
0
200
400
600
1000
0
30
60
90
120
150
OUTPUT POWER (mW)
OUTPUT POWER (mW)
14
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Pin Description
BUMP
A1
NAME
C1P
FUNCTION
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor between C1P and C1N.
Left-Speaker Negative Output
A2
OUTL-
PVDDL
OUTL+
PGNDR
OUTR-
C1N
A3
Left-Channel Class D Power Supply. Bypass with a 1µF capacitor to PGNDL.
Left-Speaker Positive Output
A4
A5, B5
A6
Right-Channel Class D Power Ground
Right-Speaker Negative Output
B1
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor between C1P and C1N.
Receiver Bypass Negative Input
B2
RXIN-
B3
PGNDL
RXIN+
PVDDR
Left-Channel Class D Power Ground
B4
Receiver Bypass Positive Input
B6
Right-Channel Class D Power Supply. Bypass with a 1µF capacitor to PGNDL.
Headphone Amplifier Negative Power Supply. Bypass with a 1µF capacitor to PGND.
C1
V
SS
C2, C3, C4,
C5
GND
Analog Ground
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
OUTR+
HPL
Right-Speaker Positive Output
Headphone Amplifier Right Output
BIAS
INB1
INA1
SCL
Common-Mode Bias. Bypass to GND with a 1µF capacitor.
Input B1. Left input or negative input.
Input A1. Left input or negative input.
Serial-Clock Input. Connect a pullup resistor from SDA to V
.
CCIO
SDA
Serial-Data Input/Output. Connect a pullup resistor from SDA to V
.
CCIO
HPR
Headphone Amplifier Left Output
V
Analog Supply. Connect to PVDDL and PVDDR. Bypass with a 1µF capacitor to GND.
Input B2. Right input or positive input.
DD
INB2
INA2
Input A2. Right input or positive input.
SHDN
Active-Low Shutdown Input Signal
2
V
I C Power Supply
CCIO
When an input is configured as mono differential, it can
Detailed Description
be routed to both speakers or to both headphones.
When an input is stereo, it is routed to either the stereo
headphones or the stereo speakers. Simultaneous oper-
ation is also possible. If the right speaker amplifier is dis-
abled then the left and right audio signals are summed
into the left speaker amplifier and vice-versa.
Signal Path
The MAX9879 signal path consists of flexible inputs,
signal mixing, volume control, and output amplifiers
(Figures 1a, 1b, 1c).
The inputs can be configured for single-ended or differ-
ential signals (Figure 2). The internal preamplifiers fea-
ture three programmable gain settings of 0dB, +5.5dB,
and +20dB. Following preamplification, the input sig-
nals are mixed, volume adjusted, and routed to the
headphone and speaker amplifiers based on the out-
put mode configuration (see Table 6). The volume con-
trol stages provide up to 75dB attenuation. The
headphone amplifiers provide +3dB of gain while the
speaker amplifier provides +18dB of additional gain.
When the application does not require the use of both
INA_ and INB_, the SNR of the MAX9879 is improved
2
by deselecting the unused input through the I C output
mode register and AC-coupling the unused inputs to
ground with a 330pF capacitor. The 330pF capacitor
and the input resistance to the MAX9879 form a high-
pass filter preventing audible noise from coupling into
the outputs.
Maxim Integrated
15
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
STEREO MODE
1μF
INA1
HPL
HPR
L
L
CLASS AB
INPUT A
1μF
INA2
R
R
L
+
CLASS AB
R
+
OUTL+
OUTL-
OUTR+
1μF
1μF
CLASS D
CLASS D
INB1
INB2
L
L
INPUT B
+
R
R
OUTR-
NOTE: STEREO SPEAKER OUTPUTS MAY
BE SUMMED FOR MONO OUTPUT.
Figure 1a. Stereo-Mode Signal Path
MONO MODE
1μF
INA1
+
HPL
HPR
CLASS AB
CLASS AB
INPUT A
1μF
INA2
-
+
OUTL+
OUTL-
OUTR+
1μF
1μF
CLASS D
CLASS D
INB1
INB2
+
-
INPUT B
OUTR-
Figure 1b. Mono-Mode Signal Path
16
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
MONO IN, STEREO IN, OUTPUT IN STEREO MODE
1μF
1μF
INA1
INA2
HPL
L
L
CLASS AB
INPUT A
R
R
L
HPR
CLASS AB
+
R
+
OUTL+
OUTL-
OUTR+
1μF
1μF
CLASS D
CLASS D
INB1
INB2
+
-
INPUT B
+
OUTR-
NOTE: STEREO SPEAKER OUTPUTS MAY
BE SUMMED FOR MONO OUTPUT.
Figure 1c. Mono INB, Stereo INA, Output in Stereo-Mode Signal Path
Maxim Integrated
17
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
STEREO SINGLE-ENDED
IN_2 (R)
R
TO MIXER
IN_1 (L)
L
DIFFERENTIAL
IN_2 (+)
IN_1 (-)
TO MIXER
Figure 2. Differential and Stereo Single-Ended Input Configurations
18
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
interference (EMI) regulation standards. Limiting the
dV/dt normally results in decreased efficiency. Maxim’s
active emissions limiting circuitry actively limits the
dV/dt of the rising and falling edge transitions, provid-
ing reduced EMI emissions, while maintaining up to
88% efficiency.
Volume Control and Mute
The MAX9879 features three Volume Control registers
(see Table 4), allowing independent volume control of
speaker and headphone amplifier outputs. There is one
Speaker Volume Control register that evenly controls both
speaker outputs. Two Headphone Volume Control regis-
ters provide independent control of each headphone out-
put. Each volume control register provides 31 attenuation
steps providing 0dB to -75dB (typ) of total attenuation
and a mute function.
In addition to active emission limiting, the MAX9879 fea-
tures a spread-spectrum modulation mode that flattens
the wideband spectral components. Proprietary tech-
niques ensure that the cycle-to-cycle variation of the
switching period does not degrade audio reproduction
or efficiency (see the Typical Operating Characteristics).
With spread-spectrum modulation, the switching fre-
quency varies randomly by 40kHz around the center
frequency (700kHz). The effect is to reduce the peak
energy at harmonics of the switching frequency. Above
10MHz, the wideband spectrum looks like white noise for
EMI purposes (see Figure 4).
Class D Speaker Amplifier
The MAX9879 integrates a filterless Class D amplifier
that offers much higher efficiency than Class AB with-
out the typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current-
steering switches and consume negligible additional
power. Any power loss associated with the Class D out-
Speaker Current Limit
Most applications do not enter current limit unless the
output is short circuited or connected incorrectly.
2
put stage is mostly due to the I R loss of the MOSFET
on-resistance, and quiescent current overhead.
When the output current of the speaker amplifier
exceeds the current limit (1.5A, typ) the MAX9879 dis-
ables the outputs for approximately 250µs. At the end of
250µs, the outputs are re-enabled, and if the fault condi-
tion still exists, the MAX9879 continues to disable and re-
enable the outputs until the fault condition is removed.
The theoretical best efficiency of a linear amplifier is
78%, however, that efficiency is only exhibited at peak
output power. Under normal operating levels (typical
music reproduction levels), efficiency falls below 30%,
whereas the MAX9879 still exhibits 88% efficiency
under the same conditions (Figure 3).
Bypass Mode
The integrated DPST analog audio switch allows the
MAX9879’s Class D amplifier to be bypassed. In bypass
mode, the Class D amplifier is automatically disabled
allowing an external amplifier to drive the speaker con-
nected between OUTL+ and OUTL- through RXIN+ and
RXIN- (see the Typical Application Circuit).
Ultra-Low EMI Filterless Output Stage
In traditional Class D amplifiers, the high dV/dt of the
rising and falling edge transitions results in increased
EMI emissions, which requires the use of external LC
filters or shielding to meet EN55022 electromagnetic-
MAX9877 EFFICIENCY
vs. IDEAL CLASS EFFICIENCY
100
The bypass switch is enabled at startup. The switch can
be opened or closed even when the MAX9879 is in soft-
2
ware shutdown (see the I C Register Description section).
90
80
Unlike discrete solutions, the switch design reduces
coupling of Class D switching noise to the RXIN_
inputs. This eliminates the need for a costly T-switch.
70
MAX9879
60
The bypass switch is typically used with two 10Ω resis-
tors connected to each input. These resistors, in combi-
nation with the switch on-resistance and an 8Ω load,
approximate the 32Ω load expected by the external
amplifier. Although not required, using the resistors
optimizes THD+N.
50
IDEAL CLASS AB
40
30
20
V
V
= PVDD_ = 3.7V (MAX9879)
DD
SUPPLY
10
0
= 3.7V (IDEAL CLASS AB)
Drive RXIN+ and RXIN- with a low-impedance source
to minimize noise on the pins. In applications that do
not require the bypass mode, leave RXIN+ and RXIN-
unconnected.
0
0.25
0.50
0.75
1.00
OUTPUT POWER (W)
Figure 3. MAX9879 Efficiency vs. Class AB Efficiency
Maxim Integrated
19
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
40
TEST LIMIT
35
30
25
20
15
10
5
MAX9879 OUTPUT
180 200 220 240 260 280 300
100 120 140 160
FREQUENCY (MHz)
30
60
80
TEST LIMIT
40
35
25
20
15
MAX9879 OUTPUT
10
650
FREQUENCY (MHz)
750
850 900
300 350 400 450 500 550 600
700
800
950 1000
Figure 4. EMI with 152mm of Speaker Cable
ing board space, reducing cost, and improving the fre-
quency response of the headphone amplifier. See the
Output Power vs. Load Resistance graph in the Typical
Operating Characteristics for details of the possible
capacitor sizes. There is a low DC voltage on the ampli-
fier outputs due to amplifier offset. However, the offset of
the MAX9879 is typically 1.5mV, which, when com-
bined with a 32Ω load, results in less than 47µA of DC
current flow to the headphones.
DirectDrive Headphone Amplifier
Traditional single-supply headphone amplifiers have
outputs biased at a nominal DC voltage (typically half
the supply). Large coupling capacitors are needed to
block this DC bias from the headphone. Without these
capacitors, a significant amount of DC current flows to
the headphone, resulting in unnecessary power dissi-
pation and possible damage to both the headphone
and headphone amplifier.
Maxim’s DirectDrive® architecture uses a charge pump
to create an internal negative supply voltage. This
allows the headphone outputs of the MAX9879 to be
biased at GND while operating from a single supply
(Figure 5). Without a DC component, there is no need
for the large DC-blocking capacitors. Instead of two
large (220µF, typ) capacitors, the MAX9879 charge
pump requires two small ceramic capacitors, conserv-
In addition to the cost and size disadvantages of the
DC-blocking capacitors required by conventional head-
phone amplifiers, these capacitors limit the amplifier’s
low-frequency response and can distort the audio sig-
nal. Previous attempts at eliminating the output-cou-
pling capacitors involved biasing the headphone return
(sleeve) to the DC bias voltage of the headphone
amplifiers. This method raises some issues:
DirectDrive is a registered trademark of Maxim Integrated
Products, Inc.
20
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
1) The sleeve is typically grounded to the chassis.
caused by the parasitic trace inductance is minimized.
Although not typically required, additional high-frequen-
cy noise attenuation can be achieved by increasing the
size of C2 (see the Typical Application Circuit). The
charge pump is active only in headphone modes.
Using the midrail biasing approach, the sleeve
must be isolated from system ground, complicating
product design.
2) During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the
amplifier must be able to withstand the full energy
from an ESD strike.
Headphone Current Limit
The headphone amplifier current is limited to 140mA (typ).
The current limit clamps the output current, which appears
as clipping when the maximum current is exceeded.
3) When using the headphone jack as a line out to
other equipment, the bias voltage on the sleeve
may conflict with the ground potential from other
equipment, resulting in possible damage to the
amplifiers.
Shutdown Mode
The MAX9879 features two ways of entering low-power
shutdown:
• The device can be placed in shutdown mode by writ-
The MAX9879 features a low-noise charge pump. The
1
ing to the SHDN bit in the Output Control Register.
switching frequency of the charge pump is / of the
2
Class D switching frequency, regardless of the operating
mode. Since the Class D amplifiers are operated in
spread-spectrum mode, the charge pump also switches
with a spread-spectrum pattern. The nominal switching
frequency is well beyond the audio range, and thus does
not interfere with audio signals. The switch drivers fea-
ture a controlled switching speed that minimizes noise
generated by turn-on and turn-off transients. By limiting
the switching speed of the charge pump, the di/dt noise
• The device can be placed in an ultra-low power shut-
down mode by setting the SHDN pin to 0V. This com-
pletely disables the MAX9879 including the I2C
interface.
Click-and-Pop Suppression
The MAX9879 features click-and-pop suppression that
eliminates audible transients from occurring at startup
and shutdown.
Use the following procedure to start up the MAX9879:
1) Configure the desired output mode and pream-
plifier gain.
V
DD
2) Set the SHDN bit to 1 to start up the amplifier.
3) Wait 10ms for the startup time to pass.
V
OUT
V /2
DD
4) Increase the output volume to the desired level.
To disable the device simply set SHDN to 0.
During the startup period, the MAX9879 precharges the
input capacitors to prevent clicks and pops. If the output
amplifiers have been programmed to be active they are
held in shutdown until the precharge period is complete.
GND
CONVENTIONAL DRIVER BIASING SCHEME
+V
DD
When power is initially applied to the MAX9879, the
power-on-reset state of all three volume control registers
is mute. For most applications, the volume can be set to
the desired level once the device is active. If the click-
and-pop is too high, step through intermediate volume
settings with zero-crossing detection disabled. Stepping
through higher volume settings has a greater impact on
click-and-pop than lower volume settings.
V
OUT
GND
For the lowest possible click and pop, start up the device
at minimum volume and then step through each volume
setting until the desired setting is reached. Disable zero-
crossing detection if no input signal is expected.
-V
DD
DirectDrive BIASING SCHEME
Figure 5. Traditional Amplifier Output vs. MAX9879 DirectDrive
Output
Maxim Integrated
21
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
2
I C Interface
I2C Address
The slave address of the MAX9879 is 1001101R/(W)
(write: 0x9A, read: 0x9B).
Table 1. Register Map
REGISTER
ADDRESS
REGISTER
POR STATE
B7
B6
B5
B4
B3
B2
B1
B0
Input Mode
Control
0x00
0x40
0
ZCD
ΔINA
ΔINB
PGAINA
PGAINB
Speaker
Volume
Control
0x01
0x02
0x00
0x00
0
0
0
0
0
0
SPKVOL
HPLVOL
Left
Headphone
Volume
Control
Right
Headphone
Volume
Control
0x03
0x04
0x00
0x49
0
0
0
0
HPRVOL
Output Mode
Control
LSPK
EN
RSPK
EN
SHDN BYPASS
ENB
ENA
HPEN
Table 2. Input Mode Control Register
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0
ZCD
ΔINA
ΔINB
PGAINA
PGAINB
2
1 = IN_ is configured as a mono differential input with
IN_2 as the positive and IN_1 as the negative input.
I C Register Description
Zero-Crossing Detection (ZCD)
0 = IN_ is configured as a stereo single-ended input
with IN_2 as the right and IN_1 as the left input.
Zero-crossing detection limits distortion in the output
signal during volume transitions by delaying the transi-
tion until the mixer output crosses the internal bias volt-
age. A timeout period (typically 60ms) forces the
volume transition if the mixer output signal does not
cross the bias voltage.
Preamplifier Gain (PGAIN_)
The preamplifier gain of INA_ and INB_ can be pro-
grammed by writing to PGAIN_.
00 = 0dB
1 = Zero-crossing detection is enabled.
0 = Zero-crossing detection is disabled.
01 = +5.5dB
10 = +20dB
11 = Reserved
Differential Input Configuration (ΔIN_)
The inputs INA_ and INB_ can be configured for mono
differential or stereo single-ended operation.
22
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Table 3. Speaker/Left Headphone/Right Headphone Volume Control
REGISTER
0x01
B7
0
B6
0
B5
0
B4
B3
B2
B1
B0
SVOL (Table 4)
HPLVOL (Table 4)
HPRVOL (Table 4)
0x02
0
0
0
0x03
0
0
0
Volume Control
The device has a separate volume control for left head-
phone, right headphone, and speaker amplifiers. The
total system gain is a combination of the input gain, the
volume control, and the output amplifier gain. Table 4
shows the volume settings for each volume control.
Table 4. Volume Control Settings
_VOL
_VOL
CODE
GAIN (dB)
CODE
GAIN (dB)
B4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
B4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
-23
-21
-19
-17
-15
-13
-11
-9
0
1
MUTE
-75
-71
-67
-63
-59
-55
-51
-47
-44
-41
-38
-35
-32
-29
-26
2
3
4
5
6
7
-7
8
-6
9
-5
10
11
12
13
14
15
-4
-3
-2
-1
0
Table 5. Output Mode Control
REGISTER
B7
B6
B5
B4
ENB
B3
B2
B1
B0
LSPK
EN
RSPK
EN
0x04
SHDN
BYPASS
0
ENA
HPEN
Shutdown (SHDN)
SHDN is an active-low shutdown bit that overrides all
1 = MAX9879 operational.
settings and places the entire device in low-power shut-
2
down mode. The I C interface is fully active in this shut-
0 = MAX9879 in low-power shutdown mode.
down mode and bypass mode remains operational.
Maxim Integrated
23
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Bypass Mode (BYPASS)
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9879 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9879 transmits the proper slave address fol-
lowed by a series of nine SCL pulses. The MAX9879
transmits data on SDA in sync with the master-generat-
ed SCL pulses. The master acknowledges receipt of
each byte of data. Each read sequence is framed by a
START (S) or REPEATED START (Sr) condition, a not
acknowledge, and a STOP (P) condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically greater than 500Ω, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there
are multiple masters on the bus, or if the single master
has an open-drain SCL output. Series resistors in line
with SDA and SCL are optional. Series resistors protect
the digital inputs of the MAX9879 from high voltage
spikes on the bus lines, and minimize crosstalk and
undershoot of the bus signals.
1 = MAX9879 bypass switches are closed and the
Class D amplifier is disabled.
0 = Bypass mode disabled.
This mode does not control headphone operation.
Output Mode Control Register
Speaker/Headphone Output Mode
(_SPKEN/HPEN)
The MAX9879 features independent enables and input
selection for each speaker amplifier and the headphone
amplifier. See Table 6 for a detailed description of the
available modes. If the right speaker amplifier is disabled,
the stereo signals are automatically summed to mono for
the left output and vice-versa.
Table 6. Speaker/Headphone Modes
BIT
LSPKEN
RSPKEN
HPEN
ENA
DESCRIPTION
Enable bit for left speaker
Enable bit for right speaker
Enable bit for headphone amplifier
Enable bit for input A
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section).
ENB
Enable bit for input B
2
I C Interface Specification
2
The MAX9879 features an I C/SMBus™-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facil-
itate communication between the MAX9879 and the
master at clock rates up to 400kHz. Figure 6 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9879 by transmitting the
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START (S) condition is a high-to-low transition
on SDA with SCL high. A STOP (P) condition is a low-to-
high transition on SDA while SCL is high (Figure 7).
SDA
t
BUF
t
t
SU:STA
SU:DAT
t
SU:STA
t
t
SU:STO
t
HD:DAT
LOW
SCL
t
HIGH
t
HD:STA
t
R
t
F
REPEATED
START CONDITION
STOP
CONDITION
START
CONDITION
START
CONDITION
Figure 6. 2-Wire Interface Timing Diagram
SMBus is a trademark of Intel Corp.
24
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
A START (S) condition from the master signals the
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9879 uses to handshake receipt each byte of data
when in write mode (see Figure 8). The MAX9879 pulls
down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.
beginning of a transmission to the MAX9879. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START (Sr) condition is generated instead of
a STOP condition.
Early STOP Conditions
The MAX9879 recognizes a STOP (P) condition at any
point during data transmission except if the STOP (P)
condition occurs in the same high pulse as a START (S)
condition. For proper operation, do not send a STOP
(P) condition during the same SCL high pulse as the
START (S) condition.
The master pulls down SDA during the ninth clock
cycle to acknowledge receipt of data when the
MAX9879 is in read mode. An acknowledge is sent by
the master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the MAX9879, followed
by a STOP (P) condition.
Slave Address
The MAX9879 is preprogrammed with a slave address
of 1001101R/(W). The address is defined as the seven
most significant bits (MSBs) followed by the Read/Write
bit. Setting the Read/Write bit to 1 configures the
MAX9879 for read mode. Setting the Read/Write bit to 0
configures the MAX9879 for write mode. The address is
the first byte of information sent to the MAX9879 after
the START (S) condition.
Write Data Format
A write to the MAX9879 includes transmission of a
START (S) condition, the slave address with the R/W bit
set to 0, one byte of data to configure the internal regis-
ter address pointer, one or more bytes of data, and a
STOP (P) condition. Figure 9 illustrates the proper
frame format for writing one byte of data to the
S
Sr
P
SCL
SDA
Figure 7. START (S), STOP (P), and REPEATED START (Sr) Conditions
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 8. Acknowledge
Maxim Integrated
25
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
MAX9879. Figure 10 illustrates the frame format for writ-
ing n bytes of data to the MAX9879.
The third byte sent to the MAX9879 contains the data
that is written to the chosen register. An acknowledge
pulse from the MAX9879 signals receipt of the data
byte. The address pointer autoincrements to the next
register address after each received data byte. This
autoincrement feature allows a master to write to
sequential registers within one continuous frame. Figure
10 illustrates how to write to multiple registers with one
frame. The master signals the end of transmission by
issuing a STOP (P) condition.
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the MAX9879.
The MAX9879 acknowledges receipt of the address
byte during the master-generated 9th SCL pulse.
The second byte transmitted from the master config-
ures the MAX9879’s internal register address pointer.
The pointer tells the MAX9879 where to write the next
byte of data. An acknowledge pulse is sent by the
MAX9879 upon receipt of the address pointer data.
Register addresses greater than 0x04 are reserved. Do
not write to these addresses.
ACKNOWLEDGE FROM MAX9879
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9877
ACKNOWLEDGE FROM MAX9877
REGISTER ADDRESS
A
P
S
SLAVE ADDRESS
0
A
A
DATA BYTE
1 BYTE
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 9. Writing One Byte of Data to the MAX9879
ACKNOWLEDGE FROM MAX9879
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9879
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9879
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9879
S
0
A
A
A
REGISTER ADDRESS
DATA BYTE 1
1 BYTE
DATA BYTE n
1 BYTE
A
P
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 10. Writing n Bytes of Data to the MAX9879
NOT ACKNOWLEDGE FROM MASTER
ACKNOWLEDGE FROM MAX9879
REGISTER ADDRESS
REPEATED START
ACKNOWLEDGE FROM MAX9879
Sr SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9879
SLAVE ADDRESS
A
P
S
0
A
A
1
A
DATA BYTE
1 BYTE
R/W
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 11. Reading One Indexed Byte of Data from the MAX9879
26
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
ACKNOWLEDGE FROM MAX9879
Sr SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9879
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9879
SLAVE ADDRESS
A
P
S
0
A
A
1
A
DATA BYTE
1 BYTE
R/W
REPEATED START
R/W
AUTOINCREMENT INTERNAL
REGISTER ADDRESS POINTER
Figure 12. Reading n Bytes of Indexed Data from the MAX9879
OUT+
OUT-
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The MAX9879 acknowledges
receipt of its slave address by pulling SDA low during
the 9th SCL clock pulse. A START (S) command fol-
lowed by a read command resets the address pointer
to register 0x00. The first byte transmitted from the
MAX9879 is the contents of register 0x00. Transmitted
data is valid on the rising edge of SCL. The address
pointer autoincrements after each read data byte. This
autoincrement feature allows all registers to be read
sequentially within one continuous frame. A STOP (P)
condition can be issued after any number of read data
bytes. If a STOP (P) condition is issued followed by
another read operation, the first data byte to be read
will be from register 0x00.
MAX9879
Figure 13. Optional Ferrite Bead Filter
filters add cost, increase the solution size of the amplifier,
and can decrease efficiency and THD+N performance.
The traditional PWM scheme uses large differential out-
put swings (2 x V
) and causes large ripple cur-
DD(P-P)
rents. Any parasitic resistance in the filter components
results in a loss of power, lowering the efficiency.
The MAX9879 does not require an output filter. The
device relies on the inherent inductance of the speaker
coil and the natural filtering of both the speaker and the
human ear to recover the audio component of the
square-wave output. Eliminating the output filter results
in a smaller, less costly, more efficient solution.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9879‘s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START (Sr) condition is
then sent followed by the slave address with the R/W
bit set to 1. The MAX9879 then transmits the contents
of the specified register. The address pointer autoincre-
ments after transmitting the first byte. The master
acknowledges receipt of each read byte during the
acknowledge clock pulse. The master must acknowl-
edge all correctly received bytes except the last byte.
The final byte must be followed by a not acknowledge
from the master and then a STOP (P) condition. Figure
11 illustrates the frame format for reading one byte from
the MAX9879. Figure 12 illustrates the frame format for
reading multiple bytes from the MAX9879.
Because the frequency of the MAX9879 output is well
beyond the bandwidth of most speakers, voice coil
movement due to the square-wave frequency is very
small. Although this movement is small, a speaker not
designed to handle the additional power can be dam-
aged. For optimum results, use a speaker with a series
inductance > 10µH. Typical 8Ω speakers exhibit series
inductances in the 20µH to 100µH range.
Component Selection
Optional Ferrite Bead Filter
In applications where speaker leads exceed 20mm,
additional EMI suppression can be achieved by using a
filter constructed from a ferrite bead and a capacitor to
ground. A ferrite bead with low DC resistance, high-
frequency (> 1.176MHz) impedance of 100Ω to 600Ω,
and rated for at least 1A should be used. The capacitor
value varies based on the ferrite bead chosen and the
Applications Information
Filterless Class D Operation
Traditional Class D amplifiers require an output filter to
recover the audio signal from the amplifier’s output. The
Maxim Integrated
27
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
RF SUSCEPTIBILITY
Input Capacitor
-10
-30
An input capacitor, C , in conjunction with the input
IN
impedance of the MAX9879 forms a highpass filter that
removes the DC bias from an incoming signal. The AC-
coupling capacitor allows the amplifier to automatically
bias the signal to an optimum DC level. Assuming zero
source impedance, the -3dB point of the highpass filter
is given by:
-50
THRESHOLD OF HEARING
-70
MAX9879
-90
1
-110
-130
f
=
−3dB
2πR C
IN IN
NOISE FLOOR
10k
Choose C so that f
is well below the lowest fre-
IN
-3dB
-150
10
100
1k
100k
quency of interest. Use capacitors whose dielectrics
have low-voltage coefficients, such as tantalum or alu-
minum electrolytic. Capacitors with high-voltage coeffi-
cients, such as ceramics, may result in increased
distortion at low frequencies.
FREQUENCY (Hz)
Figure 14. MAX9879 Susceptibility to a GSM Cell Phone Radio
BIAS Capacitor
PVDD Bulk Capacitor (C3)
In addition to the recommended PVDD bypass capaci-
tance, bulk capacitance equal to C3 should be used.
Place the bulk capacitor as close as possible to the device.
BIAS is the output of the internally generated DC bias volt-
age. The BIAS bypass capacitor, C
, reduces power
BIAS
supply and other noise sources at the common-mode
bias node. Bypass BIAS with a 1µF capacitor to GND.
Supply Bypassing,
Layout, and Grounding
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mΩ for optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surface-
mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
Proper layout and grounding are essential for optimum
performance. Use wide traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Wide traces also aid in mov-
ing heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Flying Capacitor (C1)
The value of the flying capacitor (C1) affects the output
resistance of the charge pump. A C1 value that is too
small degrades the device’s ability to provide sufficient
current drive, which leads to a loss of output voltage.
Increasing the value of C1 reduces the charge-pump out-
put resistance to an extent. Above 1µF, the on-resistance
of the switches and the ESR of C1 and C2 dominate.
Connect the PVDD_ pins to a 2.7V to 5.5V source.
Bypass PVDD_ to PGND pin with a 1µF ceramic capac-
itor. Additional bulk capacitance should be used to pre-
vent power supply pumping. Bypass PVDD_ to the
PGND pin with a 1µF ceramic capacitor. Additional
bulk capacitance should be used to prevent power-
supply pumping. Place the bypass capacitors as close
as possible to the MAX9879.
Output Holding Capacitor (C2)
The output capacitor value and ESR directly affect the
ripple at V . Increasing the value of C2 reduces output
SS
ripple. Likewise, decreasing the ESR of C2 reduces both
ripple and output resistance. Lower capacitance values
can be used in systems with low maximum output power
levels. See the Output Power vs. Load Resistance graph
in the Typical Operating Characteristics.
Connect V
to PVDD_. Bypass V
to GND with a
DD
DD
1µF capacitor. Place the bypass capacitors as close as
possible to the MAX9879.
28
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz that is easily
demodulated by audio amplifiers. Figure 14 shows the
susceptibility of the MAX9879 to a transmitting GSM
radio placed in close proximity. Although there is mea-
surable noise at 217Hz and its harmonics, the noise is
well below the threshold of hearing using typical head-
phones.
In RF applications, improvements to both layout and
component selection decreases the MAX9879’s sus-
ceptibility to RF noise and prevent RF signals from
being demodulated into audible noise. Trace lengths
1
should be kept below / the wavelength of the RF fre-
4
quency of interest. Minimizing the trace lengths pre-
vents them from functioning as antennas and coupling
RF signals into the MAX9879. The wavelength λ in
meters is given by:
45 5μm
250μm
λ = c/f
where c = 3 x 108 m/s, and f = the RF frequency of
interest.
Figure 15. PCB Footprint Recommendation Diagram
Route audio signals on middle layers of the PCB to
allow ground planes above and below shield them from
RF interference. Ideally the top and bottom layers of the
PCB should primarily be ground planes to create effec-
tive shielding.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profile, as well as the latest information on reliability
testing results, refer to the Application Note 1891:
Understanding the Basics of the Wafer-Level Chip-
Scale Package (WL-CSP) on Maxim’s website at
www.maxim-ic.com/ucsp. See Figure 15 for the rec-
ommended PCB footprint for the MAX9879.
Additional RF immunity can also be obtained from rely-
ing on the self-resonant frequency of capacitors as it
exhibits the frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capaci-
tors typically exhibit self resonance at RF frequencies.
These capacitors, when placed at the input pins, can
effectively shunt the RF noise at the inputs of the
MAX9879. For these capacitors to be effective, they
must have a low-impedance, low-inductance path to
the ground plane. Do not use microvias to connect to
the ground plane as these vias do not conduct well at
RF frequencies.
Maxim Integrated
29
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Typical Application Circuit
2.7V TO 5.5V
1.7V TO 3.6V
C
1μF
C
1μF
C
3
1μF
2
3
1μF
0.1μF
V
V
V
DD
PVDDL
A3
PVDDR
SS
CCIO
C1
E6
E2
B6
C1N B1
C1P A1
INA2 E4
MAX9879
C
1μF
CHARGE
PUMP
1
-75dB TO 0dB
E1 HPR
D1 HPL
+3dB
1μF
INPUT A
0dB/+5.5dB/+20dB
+3dB
INA1 D4
INB2 E3
1μF
1μF
-75dB TO 0dB
INPUT B
0dB/+5.5dB/+20dB
C6 OUTR+
A6 OUTR-
CLASS D
MODULATOR
+12dB
INB1 D3
CONNECT TO V
NORMAL OPERATION
FOR
CCIO
1μF
-75dB TO 0dB
-75dB TO 0dB
+6dB
SHDN
BIAS
E5
A4 OUTL+
A2 OUTL-
CLASS D
MODULATOR
+12dB
D2
D6
1μF
2
SDA
SCL
I C
CONTROL
D5
BYPASS
10Ω
10Ω
RXIN+ B4
RXIN- B2
BASEBAND
RECEIVER
AMPLIFIER
C2, C3, C4, C5
GND
B3
A5, B5
PGNDL
PGNDR
Chip Information
PROCESS: BiCMOS
30
Maxim Integrated
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0058
—
30 NCSP
R302A3+1
Maxim Integrated
31
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
1
2/09
4/13
Initial release
—
Updated maximum input signal swing and Typical Application Circuit
2, 30
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
32 ________________________________Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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