MAX9888_V01 [MAXIM]
Stereo Audio CODEC with FlexSound Technology;
| 型号： | MAX9888_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Stereo Audio CODEC with FlexSound Technology |
| 文件： | 总115页 (文件大小：11070K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5235; Rev 1; 2/11
Stereo Audio CODEC
with FlexSound Technology
General Description
The MAX9888 is a full-featured audio CODEC whose
high performance and low power consumption make it
ideal for portable applications.
Features
S 100dB DR Stereo DAC (8kHz < f < 96kHz)
S
S 91dB DR Stereo ADC (8kHz < f < 96kHz)
S
S Stereo Low EMI Class D Amplifiers
950mW/Channel (8I, V
= 4.2V)
SPKVDD_
Class D speaker amplifiers provide efficient amplification
for two speakers. Low radiated emissions enable com-
pletely filterless operation. Integrated bypass switches
optionally connect an external amplifier to the transducer
when the Class D amplifiers are disabled.
S Stereo DirectDrive Headphone Amplifiers
S Differential Receiver Amplifier
S 2 Stereo Single-Ended/Mono Differential Line
Inputs
S 3 Differential Microphone Inputs
®
DirectDrive headphone amplifiers provide a true
S FlexSound Technology
5-Band Parametric EQ
ground-referenced output, eliminating the need for
large DC-blocking capacitors. 1.8V headphone opera-
tion ensures low power consumption. The device also
includes a differential receiver amplifier.
Automatic Level Control (ALC)
Excursion Limiter
Speaker Power Limiter
Speaker Distortion Limiter
Microphone Automatic Gain Control
and Noise Gate
Three differential analog microphone inputs are available
as well as support for two PDM digital microphones.
Integrated switches allow microphone signals to be
routed out to external devices. Two flexible single-ended
or differential line inputs may be connected to an FM
radio or other sources.
S Dual I2S/PCM/TDM Digital Audio Interfaces
S Asynchronous Digital Mixing
S Supports Master Clock Frequencies from 10MHz
to 60MHz
Integrated FlexSoundK technology improves loud-
speaker performance by optimizing the signal level and
frequency response while limiting the maximum distor-
tion and power at the output to prevent speaker damage.
Automatic gain control (AGC) and a noise gate optimize
the signal level of microphone input signals to make best
use of the ADC dynamic range.
S RF Immune Analog Inputs and Outputs
S Extensive Click-and-Pop Reduction Circuitry
S I2C Control Interface
S 63 WLP Package (3.80mm x 3.30mm, 0.4mm Pitch)
Ordering Information
The device is fully specified over the -40NC to +85NC
extended temperature range.
PART
TEMP RANGE
PIN-PACKAGE
MAX9888EWY+
-40NC to +85NC
63 WLP
DirectDrive is a registered trademark and FlexSound is a
trademark of Maxim Integrated Products, Inc.
+Denotes lead(Pb)-free/RoHS-compliant package.
Simplified Block Diagram
2
I
2
2
I S/PCM
C
I
S/PCM
RECEIVER AMP
DIGITAL
AUDIO
DIGITAL
AUDIO
CONTROL
INTERFACE
INTERFACE
DIGITAL MICROPHONE
SPEAKER AMP
INPUT
FlexSound TECHNOLOGY
• 5-BAND PARAMETRIC EQ
• AUTOMATIC LEVEL CONTROL
• LOUDSPEAKER PROCESSING
• EXCURSION LIMITER
• THD LIMITER
ADC
DAC
SPEAKER AMP
MIX
MIX
• POWER LIMITER
LINEIN A1
• MICROPHONE PROCESSING
• AUTOMATIC GAIN CONTROL
• NOISE GATE
• ASYNCHRONOUS DIGITAL
MIXING
HEADPHONE AMP
ADC
DAC
LINEIN A2
+
LINEIN B1
MAX9888
HEADPHONE AMP
LINEIN B2
+
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Stereo Audio CODEC
with FlexSound Technology
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Digital Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Audio Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Digital Microphone Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2
I C Timing Characterstics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Microphone to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Line to ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Digital Loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Analog Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DAC to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Line to Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DAC to Speaker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Line to Speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
DAC to Headphone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Line to Headphone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Speaker Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Detailed Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2
I C Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Microphone Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Line Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
ADC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Record Path Signal Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Microphone AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Noise Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
2
Stereo Audio CODEC
with FlexSound Technology
TABLE OF CONTENTS (continued)
ADC Record Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Sidetone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Digital Audio Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Passband Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Playback Path Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Automatic Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Parametric Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Playback Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
DAC Input Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Preoutput Signal Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Preoutput Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Preoutput PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Receiver Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Receiver Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Speaker Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Speaker Output Volume. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Speaker Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Speaker Amplifier Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Excursion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Power Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Distortion Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Headphone Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Headphone Output Mixers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Headphone Output Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Output Bypass Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Click-and-Pop Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Jack Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Jack Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Accessory Button Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Jack Removal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3
Stereo Audio CODEC
with FlexSound Technology
TABLE OF CONTENTS (continued)
Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Device Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
START and STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Early STOP Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Write Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Read Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Typical Operating Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Analog Microphones and Bypass Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Digital Microphones and Receiver Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Filterless Class D Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
RF Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Startup/Shutdown Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Optional Ferrite Bead Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Charge-Pump Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Charge-Pump Flying Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Charge-Pump Holding Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Recommended PCB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Supply Bypassing, Layout, and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
WLP Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
4
Stereo Audio CODEC
with FlexSound Technology
Functional Diagram
S D I N 2
S D O U T 2
L R C L K 2
B C L K 2
S D I N 1
S D O U T 1
L R C L K 1
B C L K 1
5
Stereo Audio CODEC
with FlexSound Technology
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND.)
REG, INA1, INA2, INB1, INB2, MIC1P/DIGMICDATA,
DVDD, AVDD, HPVDD .........................................-0.3V to +2.2V
SPKLVDD, SPKRVDD, DVDDS1, DVDDS2..........-0.3V to +6.0V
DGND, HPGND, SPKLGND, SPKRGND..............-0.1V to +0.1V
HPVSS ...............................(HPGND - 2.2V) to (HPGND + 0.3V)
C1N .................................... (HPVSS - 0.3V) to (HPGND + 0.3V)
C1P.....................................(HPGND - 0.3V) to (HPVDD + 0.3V)
PREG..................................................... -0.3V to (AVDD + 0.3V)
REF, MICBIAS .................................-0.3V to (SPKLVDD + 0.3V)
MCLK, SDINS1, SDINS2, JACKSNS,
MIC1N/DIGMICCLK, MIC2P, MIC2N ...............-0.3V to +2.2V
HPSNS...............................(HPGND - 0.3V) to (HPGND + 0.3V)
HPL, HPR ............................(HPVSS - 0.3V) to (HPVDD + 0.3V)
RECP, RECN ..............(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKLP, SPKLN...........(SPKLGND - 0.3V) to (SPKLVDD + 0.3V)
SPKRP, SPKRN .........(SPKRGND - 0.3V) to (SPKRVDD + 0.3V)
Continuous Power Dissipation (T = +70NC)
A
63-Bump WLP (derate 25.6mW/NC above +70NC)........2.05W
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
SDA, SCL, IRQ .................................................-0.3V to +6.0V
LRCLKS1, BCLKS1, SDOUTS1.........-0.3V to (DVDDS1 + 0.3V)
LRCLKS2, BCLKS2, SDOUTS2.........-0.3V to (DVDDS2 + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
V
V
,
SPKLVDD
2.8
5.5
SPKRVDD
V
, V
,
DVDD AVDD
Supply Voltage Range
Guaranteed by PSRR
1.65
1.65
1.8
2.0
3.6
V
V
HPVDD
V
V
,
DVDDS1
DVDDS2
Analog
Speaker
Digital
6.37
1.98
1.49
2.71
1.65
2.93
1.85
8.22
2.94
10
3.5
3
Full-duplex 8kHz mono,
receiver output (Note 3)
Analog
Speaker
Digital
4
DAC playback 48kHz stereo,
headphone outputs (Note 3)
2.5
4.5
3
Analog
Speaker
Digital
DAC playback 48kHz stereo,
speaker outputs (Note 3)
18
5
Total Supply Current (Note 2)
I
mA
VDD
Analog
Speaker
Digital
12.75
1.7
18
3
Full-duplex 48kHz stereo,
microphone inputs,
headphone outputs (Note 3)
3.75
5.5
Analog
Speaker
Digital
5.11
0.58
0.03
7
1
Stereo line playback,
IN_DIF = 0, INA1 to HPL,
INA2 to HPR, V
= 0V
MCLK
0.06
6
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
Analog
MIN
TYP
0.2
0.1
1
MAX UNITS
2
Shutdown Supply Current
(Note 2)
T
A
= +25NC
Speaker
Digital
1
5
FA
REF Voltage
PREG Voltage
REG Voltage
2.5
1.6
0.7
30
V
V
V
SLEW = 0
SLEW = 1
Shutdown to Full Operation
MICROPHONE TO ADC PATH
Dynamic Range (Note 4)
ms
17
f = 8kHz, MODE = 0 (IIR voice),
S
DR
75
88
dB
AV
= 0dB
MICPRE_
V
= 0.1V , MCLK = 12.288MHz,
P-P
IN
-77
-82
-71
65
-65
f = 8kHz, f = 1kHz
S
Total Harmonic Distortion +
Noise
THD+N
CMRR
AV
= 0dB, V = 1V , f = 1kHz
dB
dB
MICPRE_
IN
P-P
AV
f = 1kHz
= +30dB, V = 32mV
,
MICPRE_
IN
P-P
Common-Mode Rejection Ratio
V
V
= 100mV , f = 217Hz
P-P
IN
= 1.65V to 2.0V, input referred, MIC
AVDD
60
100
inputs floating
f = 217Hz, V
input referred
= 100mV , AV = 0dB,
ADC
RIPPLE
P-P
100
91
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
= 100mV , AV = 0dB,
ADC
RIPPLE
P-P
input referred
f = 10kHz, V
input referred
= 100mV , AV = 0dB,
ADC
RIPPLE
P-P
70
MODE = 0 (IIR voice)
8kHz
2.2
1.1
4.5
0.76
1kHz, 0dB input,
highpass filter
MODE = 0 (IIR voice)
16kHz
Path Phase Delay
disabled measured
from analog input to
digital output
ms
MODE = 1 (FIR audio)
8kHz
MODE = 1 (FIR audio)
48kHz
7
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
= 0dB
MIN
TYP
MAX UNITS
MICROPHONE PREAMP
Full-Scale Input
AV
1.05
0
V
P-P
MICPRE_
PA1EN/PA2EN = 01
PA1EN/PA2EN = 10
PA1EN/PA2EN = 11
PGAM1/PGAM2 = 0x00
PGAM1/PGAM2 = 0x14
Preamplifier Gain
AV
(Note 5)
19.5
29.4
19.5
20
30
20
0
20.5
30.5
20.5
dB
MICPRE_
PGA Gain
AV
(Note 5)
dB
MICPGA_
All gain settings, measured at MIC1P/MIC1N/
MIC2P/MIC2N
MIC Input Resistance
R
30
50
kI
IN_MIC
MICROPHONE BIAS
MICBIAS Output Voltage
Load Regulation
V
I
I
= 1mA
2.14
2.2
0.5
100
92
2.25
11
V
MICBIAS
LOAD
= 1mA to 2mA
mV
FV
LOAD
Line Regulation
V
= 2.8V to 5.5V
SPKLVDD
f = 217Hz, V
f = 10kHz, V
= 100mV
RIPPLE (SPKLVDD)
RIPPLE (SPKLVDD)
P-P
Ripple Rejection
dB
= 100mV
83
P-P
A-weighted, f = 20Hz to 20kHz
P-weighted, f = 20Hz to 4kHz
f = 1kHz
3.8
2.1
33
FV
RMS
Noise Voltage
nV/√Hz
MICROPHONE BYPASS SWITCH
I
V
= 100mA, INABYP = MIC2BYP = 1,
MIC1_
On-Resistance
R
3.5
-80
60
20
I
ON
= V
= (0V, V
)
MIC2_
INA_
AVDD
Total Harmonic Distortion +
Noise
V
= 2V , V
= 0.9V, R = 10kI,
IN
P-P CM L
THD+N
dB
dB
FA
f = 1kHz, INABYP = MIC2BYP = 1
V
= 2V , V = 0.9V, R = 10kI,
IN
P-P CM
L
Off-Isolation
f = 1kHz
V
V
= (0V, V ),
AVDD
MIC1_
Off-Leakage Current
-2.5
+2.5
/V
= (V , 0V)
AVDD
MIC2_ INA_
LINE INPUT TO ADC PATH
Dynamic Range (Note 4)
f = 48kHz, MCLK = 12.288MHz, MODE = 1
S
(FIR audio)
DR
91
dB
Total Harmonic Distortion +
Noise
THD+N
V
= 1V , f = 1kHz
-77
1
dB
%
IN
P-P
Gain Error
DC accuracy
5
8
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
LINE INPUT PREAMP
AV
AV
= 0dB
1
PGAIN_
Full-Scale Input
V
V
P-P
IN
= -6dB
1.4
20
PGAIN_
PGAINA/PGAINB = 0x0
PGAINA/PGAINB = 0x1
19
13
21
15
14
3
PGAINA/PGAINB = 0x2
(Note 5)
= +25NC
2
4
Level Adjust Gain
AV
dB
PGAIN_
PGAINA/PGAINB = 0x3
T
0
A
PGAINA/PGAINB = 0x4
-4
-3
-6
-2
PGAINA/PGAINB = 0x5, 0x6, 0x7
-7
-5
AV
AV
AV
AV
AV
AV
= +20dB
= +14dB
= +3dB
= 0dB
14.6
21
20
20
10
20
20
20
27.4
PGAIN_
PGAIN_
PGAIN_
PGAIN_
PGAIN_
PGAIN_
Input Resistance
R
kI
kI
IN
7.3
13.7
= -3dB
= -6dB
T
T
= +25NC
18.5
17.5
21.5
23
A
Feedback Resistance
R
INAEXT/INBEXT = 1
IN_FB
= T
to T
MAX
A
MIN
ADC LEVEL CONTROL
ADC Level Adjust Range
ADC Level Adjust Step Size
ADC Gain Adjust Range
ADC Gain Adjust Step Size
ADC DIGITAL FILTERS
AV
AVL/AVR = 0xF to 0x0 (Note 5)
-12
0
+3
18
dB
dB
dB
dB
ADCLVL
1
6
AV
AVLG/AVRG = 00 to 11 (Note 5)
ADCGAIN
VOICE MODE IIR LOWPASS FILTER (MODE1 = 0)
0.441
Ripple limit cutoff
-3dB cutoff
x f
s
Passband Cutoff
f
Hz
PLP
SLP
0.449
x f
s
Passband Ripple
f < f
-0.1
+0.1
0.47
dB
Hz
dB
PLP
Stopband Cutoff
f
x f
s
Stopband Attenuation (Note 6)
f > f
74
SLP
9
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
AVFLT = 0x1 (elliptical tuned for
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
0.0161
f = 16kHz + 217Hz notch)
s
x f
s
AVFLT = 0x2 (500Hz Butterworth tuned for
f = 16kHz)
s
0.0319
x f
s
Passband Cutoff
(-3dB from Peak)
AVFLT = 0x3 (elliptical tuned for
f = 8kHz + 217Hz notch)
s
0.0321
x f
f
Hz
AHPPB
s
AVFLT = 0x4 (500Hz Butterworth tuned for
f = 8kHz)
s
0.0632
x f
s
0.0043
x f
AVFLT = 0x5 (f /240 Butterworth)
s
s
AVFLT = 0x1 (elliptical tuned for
0.0139
f = 16kHz + 217Hz notch)
s
x f
s
AVFLT = 0x2 (500Hz Butterworth tuned for
f = 16kHz)
s
0.0156
x f
s
Stopband Cutoff
(-30dB from Peak)
AVFLT = 0x3 (elliptical tuned for
f = 8kHz + 217Hz notch)
s
0.0279
x f
f
Hz
AHPSB
s
AVFLT = 0x4 (500Hz Butterworth tuned for f = 0.0312
s
8kHz)
x f
s
0.002
x f
AVFLT = 0x5 (f /240 Butterworth)
s
s
DC Attenuation
DC
AVFLT ≠ 000
90
dB
Hz
ATTEN
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 0, LRCLK < 50kHz)
0.43
x f
Ripple limit cutoff
s
0.48
x f
Passband Cutoff
f
-3dB cutoff
PLP
SLP
s
0.5
x f
-6.02dB cutoff
s
Passband Ripple
f < f
-0.1
+0.1
0.58
dB
Hz
dB
PLP
Stopband Cutoff
f
x f
s
Stopband Attenuation (Note 6)
f < f
60
SLP
ADC STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1 = 1, LRCLK > 50kHz)
0.208
x f
Ripple limit cutoff
-3dB cutoff
s
Passband Cutoff
f
Hz
PLP
0.28
x f
s
10
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Passband Ripple
f < f
f < f
-0.1
+0.1
dB
Hz
dB
PLP
0.417
Stopband Cutoff
f
SLP
x f
s
Stopband Attenuation
60
SLP
ADC STEREO AUDIO MODE DC-BLOCKING HIGHPASS FILTER (MODE1 = 1)
Passband Cutoff
(-3dB from Peak)
0.000125
x fs
f
AVFLT ≠ 000
AVFLT ≠ 000
Hz
dB
AHPPB
DC Attenuation
DC
90
Atten
MICROPHONE AUTOMATIC GAIN CONTROL
AGCHLD = 01
50
400
2
AGC Hold Duration
AGC Attack Time
AGC Release Time
ms
ms
s
AGCHLD = 11
AGCATK = 00
AGCATK = 11
123
0.078
10
AGCRLS = 000
AGCRLS = 111
AGCTH = 0x0 to 0xF
AGC Threshold Level
AGC Threshold Step Size
AGC Gain
-3
0
+18
20
dB
dB
dB
1
(Note 5)
ADC NOISE GATE
NG Threshold Level
NG Attenuation
ANTH = 0x3 to 0xF, referred to 0dBFS
(Note 5)
-64
0
-16
12
dB
dB
ADC-TO-DAC DIGITAL SIDETONE (MODE = 0)
DVST = 0x01
DVST = 0x1F
-0.5
-60.5
2
Sidetone Gain Adjust Range
Sidetone Gain Adjust Step Size
Sidetone Path Phase Delay
AV
dB
dB
ms
STGA
8kHz
2.2
1.1
1kHz, 0dB input, highpass
filter disabled
16kHz
ADC-TO-DAC DIGITAL LOOP-THROUGH PATH
f = 48kHz, MCLK = 12.288MHz, MODE = 1
S
(FIR audio)
Dynamic Range (Note 4)
Total Harmonic Distortion
DR
89
dB
dB
f = 1kHz, f = 48kHz, MCLK = 12.288MHz,
S
MODE = 1 (FIR audio)
THD
-71
-66
DAC LEVEL CONTROL
DAC Attenuation Range
DAC Attenuation Step Size
DAC Gain Adjust Range
DAC Gain Adjust Step Size
AV
AV
DV1DV2 = 0xF to 0x0 (Note 5)
DV1G = 00 to 11 (Note 5)
-15
0
0
dB
dB
dB
dB
DACATTN
1
6
18
DACGAIN
11
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
DAC DIGITAL FILTERS
VOICE MODE IIR LOWPASS FILTER (MODE1 = 0)
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
0.448
Ripple limit cutoff
-3dB cutoff
x f
s
Passband Cutoff
f
Hz
PLP
0.451
x f
s
Passband Ripple
f < f
-0.1
+0.1
dB
Hz
dB
PLP
0.476
Stopband Cutoff
f
SLP
x f
s
Stopband Attenuation (Note 6)
f > f
75
SLP
VOICE MODE IIR HIGHPASS FILTER (MODE1 = 0)
DVFLT = 0x1 (elliptical tuned for
f = 16kHz + 217Hz notch)
s
0.0161
x f
s
DVFLT = 0x2 (500Hz Butterworth tuned for
f = 16kHz)
s
0.0312
x f
s
Passband Cutoff
(-3dB from Peak)
DVFLT = 0x3 (elliptical tuned for
f = 8kHz + 217Hz notch)
s
0.0321
x f
f
Hz
DHPPB
s
DVFLT = 0x4 (500Hz Butterworth tuned for
f = 8kHz)
s
0.0625
x f
s
0.0042
x f
DVFLT = 0x5 (f /240 Butterworth)
s
s
DVFLT = 0x1 (elliptical tuned for
0.0139
f = 16kHz + 217Hz notch)
s
x f
s
DVFLT = 0x2 (500Hz Butterworth tuned for
f = 16kHz)
s
0.0156
x f
s
Stopband Cutoff
(-30dB from Peak)
DVFLT = 0x3 (elliptical tuned for
f = 8kHz + 217Hz notch)
s
0.0279
x f
f
Hz
dB
DHPSB
s
DVFLT = 0x4 (500Hz Butterworth tuned for
f = 8kHz)
s
0.0312
x f
s
0.002
x f
DVFLT = 0x5 (f /240 Butterworth)
s
s
DC Attenuation
DC
DVFLT ≠ 000
85
ATTEN
12
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 0, LRCLK < 50kHz)
0.43
x f
Ripple limit cutoff
-3dB cutoff
s
0.47
x f
Passband Cutoff
f
Hz
PLP
SLP
s
0.5
x f
-6.02dB cutoff
s
Passband Ripple
f < f
-0.1
+0.1
0.58
dB
Hz
dB
PLP
Stopband Cutoff
f
x f
s
Stopband Attenuation (Note 6)
f > f
60
SLP
STEREO AUDIO MODE FIR LOWPASS FILTER (MODE1 = 1, DHF1/DHF2 = 1 for LRCLK > 50kHz)
0.24
Ripple limit cutoff
x f
s
Passband Cutoff
f
f
Hz
PLP
0.31
x f
-3dB cutoff
s
Passband Ripple
f < f
-0.1
+0.1
dB
Hz
dB
PLP
0.477
Stopband Cutoff
SLP
x f
s
Stopband Attenuation (Note 6)
f < f
60
SLP
STEREO AUDIO MODE DC-BLOCKING HIGHPASS FILTER
Passband Cutoff (-3dB from
Peak)
0.000104
x f
f
DVFLT ≠ 000 (DAI1), DCB2 = 1 (DAI2)
DVFLT ≠ 000 (DAI1), DCB2 = 1 (DAI2)
Hz
dB
DHPPB
s
DC Attenuation
DC
90
ATTEN
AUTOMATIC LEVEL CONTROL
Dual Band Lowpass Corner
Frequency
ALCMB = 1
ALCMB = 1
5
5
kHz
kHz
Dual Band Highpass Corner
Frequency
Gain Range
0
12
dB
Low Signal Threshold
ALCTH = 111 to 001
ALCRLS = 101
-48
-12
dBFS
0.25
8
Release Time
s
ALCRLS = 000
PARAMETRIC EQUALIZER
Number of Bands
5
1
Bands
dB
Per Band Gain Range
Preattenuator Gain Range
Preattenuator Step Size
-12
-15
+12
0
(Note 5)
dB
dB
13
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
f = 48kHz, MCLK = 12.288MHz, f = 1kHz
MIN
TYP
MAX UNITS
DAC-TO-RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
96
dB
S
Total Harmonic Distortion +
Noise
THD+N
f = 1kHz, P
= 25mW, R
= 32I
-70
-63
dB
OUT
REC
Into shutdown
-70
-73
Peak voltage, A-weighted, 32
Click and Pop Level
K
samples per second, AV
= 0dB
dBV
CP
REC
Out of shutdown
PREOUTPUT MIXERS
PGAOUTA/PGAOUTB/
PGAOUTC = 0x0
PGAOUTA/PGAOUTB/
PGAOUTC = 0xC
0
Level Adjust Gain
AV
(Note 5)
f = 1kHz
dB
PGAOUT_
-25
-23.4
-22
Level Adjust Step Size
Mute Attenuation
2
dB
dB
85
LINE INPUT-TO-RECEIVER AMPLIFIER PATH
Dynamic Range (Note 4)
DR
Referenced to full-scale output level
92
dB
dB
Total Harmonic Distortion +
Noise
THD+N
-70
V
= 2.8V to 5.5V
54
89
SPKLVDD
f = 217Hz, V
= 100mV
-63
-63
-65
-57
RIPPLE
P-P
Power-Supply Rejection Ratio
PSRR
dB
f = 1kHz, V
= 100mV
RIPPLE
P-P
f = 10kHz, V
= 100mV
RIPPLE
P-P
Into shutdown
Out of shutdown
Peak voltage, A-weighted, 32
samples per second, AV
= 0dB
Click-and-Pop Level
K
CP
dBV
mW
REC
-55
RECEIVER AMPLIFIER
Output Power
P
R
REC
= 32I, f = 1kHz, THD = 1%
100
1
OUT
Full-Scale Output
(Note 7)
V
RMS
RECVOL = 0x00
RECVOL = 0x1F
-65
-62
+8
0.5
1
-58
Volume Control
AV
REC
(Note 5)
dB
+7.5
+8.5
+8dB to +6dB
+6dB to +0dB
0dB to -14dB
-14dB to -38dB
-38dB to -62dB
f = 1kHz
Volume Control Step Size
2
dB
3
4
Mute Attenuation
95
dB
Output Offset Voltage
V
AV
= -62dB
T = +25NC
A
mV
OS
REC
±0.13
500
±1
R
REC
R
REC
= 32I
= J
Capacitive Drive Capability
No sustained oscillations
pF
100
14
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DAC-TO-SPEAKER AMPLIFIER PATH
Total Harmonic Distortion +
Noise
THD+N
f = 1kHz, P
= 250mW, Z
= 8I+ 68FH
-71
-75
dB
dB
OUT
SPK
SPKL to SPKR and SPKR to SPKL,
= 640mW, f = 1kHz
Crosstalk
Output Noise
P
OUT
A-weighted
43
FV
RMS
Into shutdown
-65
Peak voltage, A-weighted,
32 samples per second,
Click-and-Pop Level
K
dBV
CP
Out of shutdown
-65
AV
= 0dB
SPK_
LINE INPUT-TO-SPEAKER AMPLIFIER PATH
Total Harmonic Distortion +
Noise
THD+N
PSRR
f = 1kHz, P
= 200mW, Z
= 8I+ 68FH
-66
dB
OUT
SPK
Output Noise
A-weighted
= V
56
60
75
73
50
-48
FV
RMS
V
= 2.8V to 5.5V
RIPPLE
43
SPKLVDD
f = 217Hz, V
= 100mV
RIPPLE
Power-Supply Rejection Ratio
dB
f = 1kHz, V
= 100mV
RIPPLE
f = 10kHz, V
= 100mV
RIPPLE
Into shutdown
Peak voltage, A-weighted,
32 samples per second,
Click-and-Pop Level
K
dBV
mW
CP
Out of shutdown
-50
AV
= 0dB
SPK_
SPEAKER AMPLIFIER
V
V
=
SPKLVDD
1370
954
733
544
= 5.0V
SPKRVDD
V
V
=
SPKLVDD
= 4.2V
SPKRVDD
f = 1kHz, THD = 1%,
= 8I+ 68FH
Output Power
P
OUT
Z
SPK
V
V
=
SPKLVDD
= 3.7V
SPKRVDD
V
V
=
SPKLVDD
= 3.2V
SPKRVDD
Full-Scale Output
(Note 7)
2
-64
+8
0.5
1
V
RMS
SPVOLL/SPVOLR = 0x00
SPVOLL/SPVOLR = 0x1F
+8dB to +6dB
-69
-59
Volume Control (Note 5)
AV
SPK_
dB
+7.5
+8.5
+6dB to +0dB
Volume Control Step Size
0dB to -14dB
2
dB
-14dB to -38dB
-38dB to -64dB
3
4
15
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Mute Attenuation
f = 1kHz
AV = -64dB, T = +25NC
86
dB
Output Offset Voltage
EXCURSION LIMITER
Upper-Corner Frequency Range
Lower-Corner Frequency
V
OS
mV
SPK_
A
±0.25
±1.25
DHPUCF = 001 to 100
DHPLCF = 01 to 10
DHPUCF = 000 (fixed mode)
DHPUCF = 001
400
1000
Hz
Hz
400
100
200
300
400
500
Biquad Minimum Corner
Frequency
DHPUCF = 010
Hz
DHPUCF = 011
DHPUCF = 100
Z
V
= 8I+ 68FH,
SPK
DHPTH = 000
DHPTH = 111
0.34
4.95
Threshold Voltage
Release Time
= V
=
=
V
P
SPKLVDD
SPKRVDD
5.5V, AV
= +8dB
SPK_
ALCRLS = 101
ALCRLS = 000
0.25
4
s
POWER LIMITER
Attenuation
-64
dB
W
Z
V
= 8I+ 68FH,
SPK
PWRTH = 0x1
PWRTH = 0xF
0.05
Threshold
= V
SPKRVDD
SPKLVDD
1.80
5.5V, AV
= +8dB
SPK_
PWRT1 = 0x1
PWRT1 = 0xF
0.5
8.7
0.5
8.7
Time Constant 1
Time Constant 2
t
t
s
PWR1
PWR2
PWRT2 = 0x1 to 0xF
PWRT2 = 0xF
min
%
Weighting Factor
k
PWRK = 000 to 111
12.5
100
PWR
DISTORTION LIMITER
THDCLP = 0x1
THDCLP = 0xF
THDT1 = 000
THDT1 = 111
< 1
24
Distortion Limit
%
s
0.76
6.2
Release Time Constant
DAC-TO-HEADPHONE AMPLIFIER PATH
Master or slave mode
Slave mode
100
f = 48kHz, MCLK =
S
12.288MHz
Dynamic Range (Note 4)
DR
dB
dB
94
R
= 16I
= 32I
-71
-75
-64
HP
HP
f = 48kHz, MCLK = 12.288MHz,
S
f = 1kHz, P
= 20mW
OUT
R
Total Harmonic Distortion +
Noise
THD+N
f = 48kHz, MCLK = 12.288MHz,
S
-79
f = 1kHz, V
= 1
, R = 10kI
VRMS HP
OUT
16
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
f = 1kHz, Input = -1dBFS, R = 10kI
-82
dB
HP
Crosstalk
HPL to HPR and HPR to HPL,
-82
dB
dB
P
OUT
= 5mW, f = 1kHz, R = 32I
HP
V
AVDD
= V
= 1.65V to 2.0V
60
84
92
91
57
HPVDD
f = 217Hz, V
= 100mV, AV
= 0dB
RIPPLE
VOL
Power-Supply Rejection Ratio
PSRR
f = 1kHz, V
= 100mV, AV
= 0dB
RIPPLE
VOL
f = 10kHz, V
= 100mV, AV
= 0dB
RIPPLE
VOL
MODE = 0 (voice) 8kHz
2.2
1.1
1kHz, 0dB input,
highpass filter
MODE = 0 (voice)
16kHz
DAC Path Phase Delay
disabled measured
from digital input to
analog output
ms
MODE = 1 (music)
8kHz
4.5
MODE = 1 (music)
48kHz
0.76
Gain Error
1
%
%
Channel Gain Mismatch
0.5
-66
Into shutdown
Peak voltage, A-weighted,
32 samples per second,
Click-and-Pop Level
K
CP
dBV
Out of
shutdown
-67
AV
= 0dB
HP_
LINE INPUT-TO-HEADPHONE AMPLIFIER PATH
Total Harmonic Distortion +
Noise
THD+N
DR
V
= 1V , f =1kHz, R = 32I
-70
dB
dB
IN
P-P
HP
Dynamic Range (Note 4)
91
66
62
57
41
-62
V
= V
= 1.65V to 2.0V
42
AVDD
HPVDD
f = 217Hz, V
= 100mV
RIPPLE
P-P
Power-Supply Rejection Ratio
PSRR
dB
dBV
mW
f = 1kHz, V
= 100mV
RIPPLE
P-P
f = 10kHz, V
= 100mV
RIPPLE
P-P
Into shutdown
Peak voltage, A-weighted,
32 samples per second,
AV
Click and Pop Level
K
CP
Out of
shutdown
-60
= 0dB
HP_
HEADPHONE AMPLIFIER
Output Power
R
= 32I
= 16I
32
40
1
HP
HP
P
f = 1kHz, THD = 1%
(Note 7)
OUT
R
Full-Scale Output
Volume Control
V
RMS
HPVOL_ = 0x00
HPVOL_ = 0x1F
-71
2.4
-67
3
-66
3.5
AV
T = +25NC (Note 5)
A
dB
HP_
17
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.5
1
MAX UNITS
+3dB to +1dB
+1dB to -5dB
-5dB to -19dB
-19dB to -43dB
-43dB to -67dB
f = 1kHz
Volume Control Step Size
2
dB
3
4
Mute Attenuation
82
dB
T
T
= +25NC
A
±0.2
±1
Output Offset Voltage
V
OS
AV
= -67dB
mV
HP_
= T
to T
MAX
A
MIN
±2
R
HP
R
HP
= 32I
= J
500
100
667
74
No sustained
oscillations
Capacitive Drive Capability
pF
300
900
kHz
Charge Pump Oscillator
Frequency
f
CP
Slow mode
SPEAKER BYPASS SWITCH
I
V
= 100mA, SPKBYP = 1,
= [0V, V
SPKLVDD]
SPKL_
On-Resistance
R
2.8
4.5
I
ON
RXIN_
V
Z
= 2V , V
= V
/2,
IN
P-P CM
SPKLVDD
R = 10I
-77
-60
S
Total Harmonic Distortion +
Noise
THD+N
= 8I+ 68FH, f = 1kHz,
dB
SPK
R = 0I
S
SPKBYP = 1
V
= 2V , V
= V
SPKLVDD
/2,
IN
P-P CM
Off-Isolation
96
dB
Z = 8I+ 68FH, f = 1kHz
L
V
V
= [0V, V
],
, 0V]
RXIN_
SPKL_
SPKLVDD
Off-Leakage Current
RECEIVER BYPASS SWITCH
On-Resistance
-1
+1
2
FA
= [V
SPKLVDD
I
= 100mA, RECBYP = 1,
RECP
R
1.2
-66
80
I
%
ON
V
= [0V, V
]
RECN
SPKLVDD
Total Harmonic Distortion +
Noise
V
= 2V , V
= V
/2,
IN
P-P CM
SPKLVDD
THD+N
R = 32I, f = 1kHz, RECBYP = 1
L
V
= 2V , V
= V
/2,
IN
P-P CM
SPKLVDD
Off-Isolation
dB
FA
R = 32I, f = 1kHz
L
V
V
= [0V, V
],
, 0V]
RECP
SPKLVDD
Off-Leakage Current
-15
+15
= [V
RECN
SPKLVDD
18
Stereo Audio CODEC
with FlexSound Technology
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
ADCGAIN
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS = 1.
SPK_
PGAIN_
PGAOUT_
HP_
REC
T
A
= T
to T , unless otherwise noted. Typical values are at T = +25NC.) (Note 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
JACK DETECTION
0.92 x
0.95 x
0.98 x
MICBIAS enabled
V
V
V
MICBIAS MICBIAS MICBIAS
JACKSNS High Threshold
V
V
V
TH1
TH2
0.92 x
SPKLVD
0.95 x
V V
D SPKLVDD SPKLVDD
0.98 x
MICBIAS disabled
MICBIAS enabled
MICBIAS disabled
V
0.06 x
0.10 x
0.17 x
V
V
V
MICBIAS MICBIAS MICBIAS
JACKSNS Low Threshold
V
0.06 x
SPKLVD
0.10 x
SPKLVDD SPKLVD
0.17 x
V
V
V
V
D
D
JACKSNS Sense Voltage
V
R
MICBIAS disabled
MICBIAS disabled, JDWK = 0
MICBIAS disabled, JDWK = 1
JDEB = 00
V
SENSE
SPKLVDD
JACKSNS Sense Resistance
JACKSNS Weak Pullup Current
1.7
2
2.4
5
2.9
9.5
kI
FA
SENSE
I
WPU
25
200
JACKSNS Deglitch Period
t
ms
GLITCH
JDEB = 11
BATTERY ADC
Input Voltage Range
LSB Size
2.8
5.5
V
V
0.1
DIGITAL INPUT/OUTPUT CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= 1.65V to 2.0V, V
= V
= 3.7V, T = T
to T , unless
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
A
MIN
otherwise noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
1.2
-1
TYP
MAX
UNITS
MCLK
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
V
IH
V
V
V
IL
0.6
+1
I , I
IH IL
V
= 2.0V, V = 0V, 5.5V, T = +25°C
FA
pF
DVDD
IN
A
10
SDINS1, BCLKS1, LRCLKS1—INPUT
0.7 x
DVDDS1
Input High Voltage
Input Low Voltage
V
V
V
IH
0.29 x
DVDDS1
V
IL
Input Hysteresis
200
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I , I
IH IL
V
= 3.6V, V = 0V, 3.6V; T = +25°C
-1
+1
DVDDS1
IN
A
19
Stereo Audio CODEC
with FlexSound Technology
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= 1.65V to 2.0V, V
= V
= 3.7V, T = T
to T , unless
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
A
MIN
otherwise noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
BCLKS1, LRCLKS1, SDOUTS1—OUTPUT
Output Low Voltage
Output High Voltage
V
V
V
V
= 1.65V, I = 3mA
0.4
V
V
OL
DVDDS1
OL
DVDDS1
- 0.4
V
OH
= 1.65V, I
= 3mA
DVDDS1
OH
= 2.0V, V = 0V, 5.5V; T = +25°C,
DVDD
IN
A
Input Leakage Current
I
, I
-1
+1
FA
IH IL
high-impedance state
SDINS2, BCLKS2, LRCLKS2—INPUT
0.7 x
DVDDS2
Input High Voltage
Input Low Voltage
V
V
V
IH
0.29 x
DVDDS2
V
IL
Input Hysteresis
200
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I , I
IH IL
V
= 3.6V, V = 0V, 3.6V; T = +25°C
-1
+1
DVDDS2
IN
A
BCLKS2, LRCLKS2, SDOUTS2—OUTPUT
Output Low Voltage
V
V
V
V
= 1.65V, I = 3mA
0.4
+1
V
V
OL
DVDDS2
OL
DVDDS2
- 0.4
Output High Voltage
V
OH
= 1.65V, I
= 3mA
DVDDS2
OH
= 2.0V, V = 0V, 5.5V; T = +25NC,
DVDD
IN
A
Input Leakage Current
SDA, SCL—INPUT
Input High Voltage
I
, I
-1
FA
IH IL
high-impedance state
0.7 x
DVDD
V
V
V
IH
0.3 x
DVDD
Input Low Voltage
V
IL
Input Hysteresis
210
10
mV
FA
pF
Input Leakage Current
Input Capacitance
SDA, IRQ—OUTPUT
Output High Current
I
, I
V
= 2.0V, V = 0V, 5.5V, T = +25NC
-1
+1
IH IL
DVDD
IN
A
I
V
V
= 5.5V, T = +25°C
1
mA
V
OH
OUT
A
0.2 x
DVDD
Output Low Voltage
DIGMICDATA—INPUT
Input High Voltage
V
= 1.65V, I = 3mA
DVDD OL
OL
0.65 x
DVDD
V
IH
V
V
0.35 x
DVDD
Input Low Voltage
V
IL
Input Hysteresis
125
10
mV
FA
pF
Input Leakage Current
Input Capacitance
I , I
IH IL
V
= 2.0V, V = 0V, 2.0V; T = +25°C
-25
+25
DVDD
IN
A
20
Stereo Audio CODEC
with FlexSound Technology
DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued)
(V
AVDD
= V
= V
= V
= V
= 1.65V to 2.0V, V
= V
= 3.7V, T = T
to T , unless
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
A
MIN
otherwise noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
DIGMICCLK—OUTPUT
Output Low Voltage
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
OL
V
V
= 1.65V, I = 1mA
0.4
V
V
DVDD
OL
DVDD -
0.4
Output High Voltage
V
OH
= 1.65V, I
= 1mA
DVDD
OH
INPUT CLOCK CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V, T = T
A
to T , unless otherwise
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
MIN
noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
50
MAX
60
UNITS
MCLK Input Frequency
f
MHz
MCLK
PSCLK = 01
40
60
MCLK Input Duty Cycle
%
PSCLK = 10 or 11
30
70
Maximum MCLK Input Jitter
LRCLK Sample Rate (Note 8)
100
ps
RMS
DHF_ = 0
8
48
48
96
kHz
DHF_ = 1
FREQ1 = 0x8 to 0xF
FREQ1 = 0x0
0
0
DAI1 LRCLK Average Frequency
Error (Note 9)
%
%
-0.025
+0.025
DAI2 LRCLK Average Frequency
Error (Note 9)
-0.025
+0.025
Rapid lock mode
2
7
PLL Lock Time
ms
Nonrapid lock mode
12
25
Maximum LRCLK Jitter to Maintain
PLL Lock
100
ns
Soft-Start/Stop Time
10
ms
21
Stereo Audio CODEC
with FlexSound Technology
AUDIO INTERFACE TIMING CHARACTERISTICS
(V
AVDD
= V
= V
= V
= V
= 1.65V, V
= V
= 2.8V, T = T
A
to T
, unless otherwise
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
MIN
noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
BCLK Cycle Time
SYMBOL
CONDITIONS
MIN
90
TYP
MAX
UNITS
ns
t
Slave mode
Slave mode
Slave mode
BCLK
BCLK High Time
t
20
ns
BCLKH
BCLK Low Time
t
20
ns
BCLKL
BCLK or LRCLK Rise and Fall Time
SDIN to BCLK Setup Time
LRCLK to BCLK Setup Time
SDIN to BCLK Hold Time
LRCLK to BCLK Hold Time
t , t
Master mode, C = 15pF
L
ns
R
F
t
20
20
20
20
ns
SETUP
t
Slave mode
ns
SYNCSET
t
ns
HOLD
SYNCHOLD
t
Slave mode
ns
Minimum Delay Time from LSB
BCLK Falling Edge to
t
Master mode, TDM_ = 1
42
ns
HIZOUT
High-Impedance State
LRCLK Rising Edge to SDOUT
MSB Delay
t
C = 30pF, TDM_ = 1, FSW_ = 1
50
ns
ns
SYNCTX
L
TDM_ = 1, BCLK rising edge
50
50
BCLK to SDOUT Delay
t
C = 30pF
L
CLKTX
TDM_ = 0
TDM_ = 1
-15
20
+15
Master
mode
Delay Time from BCLK to LRCLK
t
ns
ns
CLKSYNC
ENDSYNC
0.8 x
BCLKL
TDM_ = 0
t
Delay Time from LRCLK to BCLK
After LSB
Master
mode
t
TDM_ = 1, FSW_ = 1
t
BCLK
t
F
t
R
t
t
BCLKL
BCLKH
BCLK
BCLK
(OUTPUT)
(INPUT)
t
t
CLKSYNC
SYNCSET
HI-Z
LRCLK
(OUTPUT)
LRCLK
(INPUT)
t
t
CLKTX
t
t
HIZOUT
CLKTX
HIZOUT
SDOUT
(OUTPUT)
SDOUT
LSB
LSB
LSB
HI-Z
MSB
MSB
t
HOLD
(OUTPUT)
t
t
t
SETUP
HOLD
SETUP
SDIN
(INPUT)
SDIN
LSB
MSB
MSB
(INPUT)
MASTER MODE
SLAVE MODE
Figure 1. Non-TDM Audio Interface Timing Diagrams (TDM_ = 0)
22
Stereo Audio CODEC
with FlexSound Technology
t
BCLK
t
F
t
R
t
t
BCLKL
BCLKH
BCLK (OUTPUT)
BCLK (INPUT)
t
t
t
CLKSYNC
SYNCSET
CLKSYNC
t
SYNCHOLD
LRCLK (OUTPUT)
t
LRCLK (INPUT)
t
t
t
CLKTX
CLKTX
HIZOUT
HIZOUT
SDOUT (OUTPUT)
SDOUT (OUTPUT)
LSB
LSB
HI-Z
MSB
LSB
HI-Z
MSB
MSB
t
t
t
t
SETUP HOLD
SETUP HOLD
SDIN (INPUT)
SDIN (INPUT)
MSB
MASTER MODE
LSB
SLAVE MODE
Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 0)
t
BCLK
t
F
t
R
t
t
BCLKL
BCLKH
BCLK (OUTPUT)
BCLK (INPUT)
LRCLK (INPUT)
t
t
CLKSYNC
ENDSYNC
LRCLK (OUTPUT)
t
t
t
t
CLKTX
CLKTX
SYNCTX
SYNCTX
t
t
HIZOUT
HIZOUT
SDOUT (OUTPUT)
LSB
HI-Z
MSB
SDOUT (OUTPUT)
SDIN (INPUT)
LSB
HI-Z
MSB
t
t
t
t
SETUP HOLD
SETUP HOLD
SDIN (INPUT)
LSB
MSB
SLAVE MODE
LSB
MSB
MASTER MODE
Figure 3. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = 1)
DIGITAL MICROPHONE TIMING CHARACTERSTICS
(V
AVDD
= V
= V
= V
= V
= 2.0V, V
= V
= 2.8V, T = T
to T , unless otherwise
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
A
MIN
noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MICCLK = 00
MICCLK = 01
MCLK/8
MCLK/6
DIGMICCLK Frequency
f
MHz
MICCLK
DIGMICDATA to DIGMICCLK
Setup Time
t
Either clock edge
Either clock edge
20
0
ns
ns
SU,MIC
HD,MIC
DIGMICDATA to DIGMICCLK
Hold Time
t
23
Stereo Audio CODEC
with FlexSound Technology
1/f
MICCLK
t
t
HD,MIC SU,MIC
t
t
HD,MIC SU,MIC
LEFT
RIGHT
LEFT
RIGHT
Figure 4. Digital Microphone Timing Diagram
2
I C TIMING CHARACTERSTICS
(V
AVDD
= V
= V
= V
= V
= 1.65V to 2.0V, V
= V
= 3.7V, T = T
to T , unless
MAX
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
A
MIN
otherwise noted. Typical values are at T = +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Guaranteed by SCL pulse-width low and
high
Serial-Clock Frequency
f
0
400
kHz
SCL
Bus Free Time Between STOP and
START Conditions
t
1.3
0.6
Fs
Fs
BUF
Hold Time (Repeated) START
Condition
t
t
HD,STA
SCL Pulse-Width Low
SCL Pulse-Width High
t
1.3
0.6
Fs
Fs
LOW
t
HIGH
Setup Time for a Repeated START
Condition
0.6
Fs
SU,STA
Data Hold Time
Data Setup Time
t
R
= 475I, CB = 100pF, 400pF
0
900
ns
ns
HD,DAT
PU
t
100
SU,DAT
20 +
SDA and SCL Receiving Rise Time
SDA and SCL Receiving Fall Time
SDA Transmitting Fall Time
t
(Note 10)
(Note 10)
300
300
250
ns
ns
ns
R
0.1C
B
20 +
0.1C
t
F
F
B
20 +
0.05C
t
R
= 475I, C = 100pF, 400pF (Note 10)
B
PU
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
0
Fs
pF
ns
SU,STO
C
B
Guaranteed by SDA transmitting fall time
400
50
Pulse Width of Suppressed Spike
t
SP
24
Stereo Audio CODEC
with FlexSound Technology
SDA
SCL
t
BUF
t
SU,STA
t
SU,DAT
t
HD,STA
t
SP
t
LOW
t
SU,STO
t
HD,DAT
t
HIGH
t
HD,STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 5. I C Interface Timing Diagram
Note 1: The IC is 100% production tested at T = +25NC. Specifications over temperature limits are guaranteed by design.
A
Note 2: Analog supply current = I
+ I
. Speaker supply current = I
+ I . Digital supply current = I
SPKRVDD DVDD
AVDD
HPVDD
SPKLVDD
+ I
+ I
.
DVDDS1
DVDDS2
Note 3: Clocking all zeros into the DAC. Slave mode.
Note 4: Dynamic range measured using the EIAJ method. -60dBFS, 1kHz output signal, A-weighted and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 5: Gain measured relative to the 0dB setting.
Note 6: The filter specification is accurate only for synchronous clocking modes, where NI is a multiple of 0x1000.
Note 7: 0dBFS for DAC input. 1V
for INA/INB inputs.
P-P
Note 8: LRCLK may be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios may exhibit some full-
scale performance degradation compared to synchronous integer related MCLK/LRCLK ratios.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
Power Consumption
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V)
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
I
+
SPKLVDD
I
I
I
I
+ I
DVDDS2
(mA)
POWER
(mW)
AVDD
HPVDD
(mA)
DVDD
DVDDS1
MODE
I
SPKRVDD
(mA)
(mA)
(mA)
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters
1.35
1.37
1.65
2.91
0.02
16.25
21.55
16.36
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, 0.1mW/channel,
1.35
1.35
4.19
1.37
1.65
1.65
3.02
2.96
0.02
0.02
R
HP
= 32I
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, ALC enabled
25
Stereo Audio CODEC
with FlexSound Technology
Power Consumption (continued)
SPKRVDD
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V)
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
I
+
SPKLVDD
I
I
I
I
+ I
DVDDS2
(mA)
POWER
(mW)
AVDD
HPVDD
(mA)
DVDD
DVDDS1
MODE
I
SPKRVDD
(mA)
(mA)
(mA)
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, EQ enabled
1.35
1.36
1.65
3.27
0.02
16.90
16.27
16.29
13.65
9.27
DAC Playback 48kHz Stereo HP
DAC à HP
24-bit, music filters, digital mixing
1.34
1.35
1.35
1.00
1.83
1.25
9.91
1.36
1.37
1.37
0.71
0.02
0.02
0.02
1.65
1.69
1.65
1.01
8.22
4.31
0.39
2.91
2.85
1.46
1.36
2.92
2.82
1.62
0.02
0.02
0.01
0.01
0.02
0.02
0.11
DAC Playback 44.1kHz Stereo HP
DAC à HP
24-bit, music filters
DAC Playback 8kHz Stereo HP
DAC à HP
16-bit, voice filters
DAC Playback 8kHz Mono HP
DAC à HP
16-bit, voice filters
DAC Playback 48kHz Stereo SPK
DAC à SPK
24-bit, music filters
39.09
23.32
22.48
DAC Playback 48kHz Mono SPK
DAC à SPK
24-bit, music filters
Line Stereo Record 48kHz
INA à ADC
16-bit, music filters
Line Stereo Record 48kHz, Stereo HP
INA à ADC
INA à HP
10.64
10.97
10.49
2.65
0.03
0.02
0.66
7.15
0.39
1.63
1.63
1.63
0.11
0.12
0.16
29.51
49.50
23.58
16-bit, music filters
Line Stereo Record 48kHz, Stereo SPK
INA à ADC
INA à SPK
16-bit, music filters
Differential Line Record 48kHz
INA à ADCL
INB à ADCR
Differential input
Microphone Stereo Record 48kHz
MIC1/2 à ADC
16-bit, music filters
10.88
10.77
0.03
0.02
0.69
0.64
1.62
1.03
0.17
0.06
25.43
23.78
Microphone Stereo Record 8kHz
MIC1/2 à ADC
16-bit, voice filters
26
Stereo Audio CODEC
with FlexSound Technology
Power Consumption (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V)
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
I
+
SPKLVDD
I
I
I
I
+ I
DVDDS2
(mA)
POWER
(mW)
AVDD
HPVDD
(mA)
DVDD
DVDDS1
MODE
I
SPKRVDD
(mA)
(mA)
(mA)
Microphone Mono Record 48kHz
MIC1/2 à ADC
16-bit, music filters
6.01
0.02
0.66
1.37
0.10
15.97
14.94
15.00
14.98
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters
5.95
5.95
5.96
0.02
0.02
0.02
0.64
0.64
0.64
0.98
0.98
0.98
0.04
0.04
0.04
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters, AGC
Microphone Mono Record 8kHz
MIC1/2 à ADC
16-bit, voice filters, AGC, noise gate
Full-Duplex 48kHz Stereo HP
MIC1/2 à ADC
DAC à HP
11.38
6.35
1.37
0.02
0.71
1.37
1.70
1.98
1.01
1.09
3.56
1.47
1.46
1.51
0.19
0.03
0.03
0.05
36.06
21.47
18.72
28.95
24-bit, music filters
Full-Duplex 8kHz Mono RCV
MIC1 à ADC
DAC à REC
16-bit, voice filters
Full-Duplex 8kHz Mono HP
MIC1 à ADC
DAC à HP
6.09
16-bit, voice filters
Full-Duplex 8kHz Stereo HP
MIC1/2 à ADC
DAC à HP
10.92
16-bit, voice filters
Line Playback Stereo HP
INA à HP
Single-ended inputs
1.89
2.21
1.68
2.65
0.02
0.02
0.58
7.05
3.70
0.03
0.04
0.03
0.01
0.02
0.02
10.41
30.19
16.90
Line Playback Stereo SPK
INA à SPK
Single-ended inputs
Line Playback Mono SPK
INA à SPK
Single-ended inputs
Differential Line Playback Stereo HP
INA à HPL
INB à HPR
2.46
2.65
0.58
0.03
0.01
11.42
Differential input
27
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
Microphone to ADC
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
MCLK = 13MHz
LRCLK = 8kHz
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
FREQ MODE
= 1V
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
V
= 1V
MICPRE_
V
= 1V
MICPRE_
IN
AV
P-P
MICPRE_
IN
AV
P-P
IN
AV
P-P
= 0dB
= 0dB
= 0dB
10
100
1000
10,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (MIC TO ADC)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
V
= 1V
MICPRE_
V
= 0.1V
MICPRE_
V
IN
AV
= 0.032V
IN
AV
P-P
IN
AV
P-P
= +20dB
P-P
= 0dB
= +30dB
MICPRE_
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
10
100
1000
10,000
FREQUENCY (Hz)
FREQUENCY (Hz)
28
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
COMMON-MODE REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
POWER-SUPPLY REJECTION
RATIO vs. FREQUENCY (MIC TO ADC)
GAIN vs. FREQUENCY (MIC TO ADC)
5
90
80
70
60
50
40
30
20
10
0
0
-20
V
= 200mV
P-P
RIPPLE
INPUTS AC GROUNDED
-5
MODE = 1
AV
MICPRE_
= +30dB
-15
-25
-35
-40
AV
MICPRE_
= +20dB
-60
RIPPLE ON AVDD,
DVDD, HPVDD
-45
MODE = 0
AV
MICPRE_
= 0dB
MCLK = 13MHz
-55
-80
LRCLK = 8kHz
FREQ MODE
= 1V
-65
-75
-85
-100
-120
V
IN
AV
P-P
MICPRE_
RIPPLE ON
SPKLVDD, SPKRVDD
= 0dB
V
= 0dBFS
OUT, DIFF
100
10
100
1000
10,000
10
1000
10,000
100,000
10
100
1000 10,000
FREQUENCY (Hz)
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, 0dBFS (MIC TO ADC)
FFT, -60dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
0
0
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
-20
-40
-20
-40
-20
-40
AV
= 0dB
AV
MICPRE_
= 0dB
AV = 0dB
MICPRE_
MICPRE_
-60
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-140
-100
-120
-140
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
0
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
29
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
PGAIN_
PGAOUT_
HP_
REC
1. T = +25NC, unless otherwise noted.)
A
FFT, -60dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
0
-20
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-40
AV
MICPRE_
= 0dB
AV = 0dB
MICPRE_
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
FFT, -60dBFS (MIC TO ADC)
FFT, 0dBFS (MIC TO ADC)
0
-20
0
-20
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
AV
MICPRE_
= 0dB
AV = 0dB
MICPRE_
-40
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
30
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
PGAIN_
PGAOUT_
HP_
REC
1. T = +25NC, unless otherwise noted.)
A
FFT, -60dBFS (MIC TO ADC)
ADC ENABLE/DISABLE RESPONSE
0
-20
(MIC TO ADC)
MAX9888 toc18
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
SCL
2V/div
AV
MICPRE_
= 0dB
-40
-60
ADC
OUTPUT
0.5V/div
-80
-100
-120
-140
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
10ms/div
SOFTWARE TURN-ON/OFF RESPONSE
(MIC TO ADC)
MAX9888 toc19
SCL
2V/div
ADC
OUTPUT
0.5V/div
10ms/div
31
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
Line to ADC
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
IN
= 1.4V
V
IN
= 1V
V
IN
= 0.1V
P-P
P-P
P-P
AV
PGAIN_
= -6dB
C
= 1µF
AV
PGAIN_
= +20dB
IN
C
IN
= 1µF
AV
= 0dB
PGAIN_
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY (LINE TO ADC)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO ADC)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-20
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
= 200mV
P-P
RIPPLE
INPUTS AC GROUNDED
V
= 1V
IN
EXTERNAL GAIN MODE
RMS
-40
R
= 56kI, C = 1µF
IN
IN
-60
RIPPLE ON AVDD,
DVDD, HPVDD
-80
-100
-120
RIPPLE ON
SPKLVDD, SPKRVDD
10
100
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
32
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
PGAIN_
PGAOUT_
HP_
REC
1. T = +25NC, unless otherwise noted.)
A
Digital Loopback
FFT, 0dBFS
(SDINS1 TO SDOUTS2 DIGITAL LOOPBACK)
FFT, -60dBFS
(SDINS1 TO SDOUTS2 DIGITAL LOOPBACK)
0
-20
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-180
-100
-120
-140
-160
-180
0
5000
10,000
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
FREQUENCY (Hz)
33
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
Analog Loopback
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO ADC TO DAC TO HEADPHONE )
FFT, 0dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-20
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I, C = 1µF
R
= 32I, C = 1µF
R
= 32I
HP
IN
HP
IN
HP
-40
-60
P
= 0.025W
P
= 0.025W
OUT
OUT
-80
-100
-120
-140
P
= 0.01W
100
OUT
P
= 0.01W
100
OUT
10
1000
10,000
100,000
10
1000
10,000
100,000
0
5000
10,000
15,000
20,000
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
FFT, -60dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
FFT, 0dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
FFT, -60dBFS
(LINE TO ADC TO DAC TO HEADPHONE)
0
-20
0
-20
0
-20
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
R
= 32I
R
= 32I
R = 32I
HP
HP
HP
-40
-40
-40
-60
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-140
-100
-120
-140
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
34
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
DAC to Receiver
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER (DAC TO RECEIVER)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY (DAC TO RECEIVER)
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO RECEIVER)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
140
130
120
110
100
90
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-10
THD+N = 10%
THD+N = 1%
-20
R
= 32I
R
= 32I
REC
REC
AV
REC
= +8dB
-30
-40
-50
-60
-70
-80
-90
P
= 0.05W
OUT
f = 3000Hz
f = 1000Hz
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
80
R
REC
= 32I
70
AV
REC
= +8dB
f = 100Hz
P
= 0.025W
OUT
60
0
0.02 0.04 0.06 0.08 0.10 0.12
OUTPUT POWER (W)
10
100
1000
10,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
GAIN vs. FREQUENCY
(DAC TO RECEIVER)
POWER CONSUMPTION vs. OUTPUT
POWER (DAC TO RECEIVER)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO RECEIVER)
5
4
0.25
0.20
0.15
0.10
0.05
0
0
-20
V
= 200mV
P-P
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
RIPPLE
ALL ZEROS AT INPUT
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
3
R
= 32I
REC
R
= 32I
REC
AV
2
= +8dB
REC
1
-40
RIPPLE ON SPKLVDD,
SPKRVDD
0
-1
-2
-3
-4
-5
-60
-80
RIPPLE ON AVDD,
DVDD, HPVDD
-100
10
100
1000
10,000
0
0.02 0.04 0.06 0.08 0.10 0.12
OUTPUT POWER (W)
10
100
1000
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
35
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
SOFTWARE TURN-ON/OFF RESPONSE
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO RECEIVER, VSEN = 0)
(DAC TO RECEIVER, VSEN = 1)
FFT, 0dBFS (DAC TO RECEIVER)
MAX9888 toc39
MAX9888 toc40
0
-20
SCL
2V/div
SCL
2V/div
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
R
= 32I
REC
-40
-60
RECEIVER
OUTPUT
1V/div
RECEIVER
OUTPUT
1V/div
-80
-100
-120
-140
10ms/div
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
10ms/div
WIDEBAND FFT, 0dBFS
(DAC TO RECEIVER)
WIDEBAND FFT, -60dBFS
(DAC TO RECEIVER)
FFT, -60dBFS (DAC TO RECEIVER)
0
0
-20
0
-20
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 8kHz
PLL MODE
MCLK = 13MHz
LRCLK = 8kHz
PLL MODE
-20
R
= 32I
R
REC
= 32I
R
REC
= 32I
REC
-40
-60
-40
-40
-60
-60
-80
-80
-80
-100
-120
-140
-100
-120
-100
-120
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
1
10
100
1000 10,000
0
1
10
100
1000 10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
36
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
PGAIN_
PGAOUT_
HP_
REC
1. T = +25NC, unless otherwise noted.)
A
Line to Receiver
TOTAL HARMONIC DISTORTION PLUS
NOISE vs. OUTPUT POWER
(LINE TO RECEIVER)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
(LINE TO RECEIVER)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
R
= 32I
REC
= 1µF
R
= 32I
REC
AV
-10
-20
-30
-40
-50
-60
-70
-80
-90
C
= +8dB
IN
AV
REC
= +8dB
REC
f = 6000Hz
P
= 0.05W
OUT
P
= 0.025W
OUT
f = 1000Hz
0.06 0.08
f = 100Hz
0
0.02
0.04
0.10
10
100
1000
FREQUENCY (Hz)
10,000
100,000
OUTPUT POWER (W)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO RECEIVER)
GAIN vs. FREQUENCY (LINE TO RECEIVER)
5
4
0
-20
R
= 32I
REC
= 1µF
V
= 200mV
P-P
RIPPLE
C
IN
INPUT AC GROUNDED
3
2
1
-40
RIPPLE ON SPKLVDD,
SPKRVDD
0
-1
-2
-3
-4
-5
-60
-80
RIPPLE ON AVDD,
DVDD, HPVDD
-100
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
37
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
DAC to Speaker
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
0
-10
-20
-30
-40
-50
-60
-70
-80
V
= 4.2V
V
= 3.7V
V
= 3.V
SPK_VDD
SPK_VDD
SPK_VDD
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
Z
= 8I+ 68µH
= +8dB
Z
= 8I+ 68µH
= +8dB
Z
= 8I+ 68µH
= +8dB
SPK_
SPK
SPK
SPK
AV
AV
AV
SPK_
SPK_
f = 6000Hz
-40
-50
f = 6000Hz
f = 6000Hz
f = 1000Hz
f = 1000Hz
f = 1000Hz
-60
-70
-80
f = 100Hz
0.6
f = 100Hz
f = 100Hz
0.1
0
0.2
0.4
0.8
1.0
1.2
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.3
0.4
0.5
0.6
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
= 4.2V
V
= 3.7V
V
= 3V
SPK_VDD
SPK_VDD
SPK_VDD
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz, LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
Z
SPK
= 4I+ 33µH
= +8dB
Z
= 4I+ 33µH
= +8dB
SPK
AV
AV
Z
= 4I + 33µH
SPK_
SPK_
SPK
AV
= +8dB
SPK_
f = 6000Hz
f = 6000Hz
f = 6000Hz
f = 1000Hz
f = 1000Hz
f = 1000Hz
f = 100Hz
0.5
f = 100Hz
f = 100Hz
0
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4
OUTPUT POWER (W)
OUTPUT POWER (W)
OUTPUT POWER (W)
38
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
V
= 4.2V
V
= 3.7V
V
= 4.2V
SPK_VDD
SPK_VDD
SPK_VDD
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
Z
SPK
= 8I+ 68µH
= +8dB
Z
SPK
= 8I+ 68µH
= +8dB
Z
SPK
= 4I+ 33µH
AV
AV
SPK_
SPK_
P
= 1.0W
OUT
P
= 0.25W
P
= 0.25W
OUT
OUT
OUT
OUT
P
= 0.5W
OUT
P
= 0.55W
100
P
= 0.55W
100
10
1000
10,000
100,000
10
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO SPEAKER)
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
OUTPUT POWER vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
2200
2000
1800
1600
1400
1200
1000
800
3500
3000
2500
2000
1500
1000
500
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
V
= 3.7V
SPK_VDD
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
Z
SPK
= 8I+ 68µH
Z
SPK
= 4I+ 33µH
Z
SPK
= 4I+ 33µH
THD+N = 10%
P
= 1.0W
OUT
THD+N = 1%
THD+N = 10%
P
= 0.5W
OUT
THD+N = 1%
600
400
0
10
100
1000
FREQUENCY (Hz)
10,000
100,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
39
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
GAIN vs. FREQUENCY
(DAC TO SPEAKER)
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
EFFICIENCY vs. OUTPUT POWER
(DAC TO SPEAKER)
5
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
4
3
2
Z
= 8I+ 68µH
SPK
1
= 4I+ 33µH
Z
SPK
Z
SPK
= 4I+ 33µH
0
Z
= 8I+ 68µH
Z
SPK
= 8I+ 68µH
SPK
-1
-2
-3
-4
-5
V
= 4.2V
V
= 3.7V
SPK_VDD
SPK_VDD
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
AV
SPK_
= +8dB
AV
SPK_
= +8dB
10
100
1000
FREQUENCY (Hz)
10,000
100,000
0
0.5
1.0
1.5
2.0
2.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
OUTPUT POWER PER CHANNEL (W)
OUTPUT POWER PER CHANNEL (W)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DAC TO SPEAKER)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO SPEAKER)
POWER-SUPPLY REJECTION RATIO
vs. SUPPLY VOLTAGE (DAC TO SPEAKER)
30
0
-20
0
-20
RIPPLE ON SPKLVDD, SPKRVDD
MCLK = 12.288MHz,
LRCLK = 48kHz
V
= 200mV
P-P
RIPPLE
V
= 200mV
RIPPLE
P-P
25
20
15
10
5
f = 1kHz
Z
SPK
= 8I+ 68µH
NI MODE
AV = +8dB
SPK_
-40
RIPPLE ON SPKLVDD,
SPKRVDD
-40
ALL ZEROS AT INPUT
-60
-60
-80
-80
RIPPLE ON AVDD,
DVDD, HPVDD
0
-100
-100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10
100
1000
10,000
100,000
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SPK_VDD SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
40
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
SOFTWARE TURN-ON/OFF RESPONSE
SOFTWARE TURN-ON/OFF RESPONSE
CROSSTALK vs. FREQUENCY
(DAC TO SPEAKER)
(DAC TO SPEAKER, VSEN = 0)
(DAC TO SPEAKER, VSEN = 1)
MAX9888 toc68
MAX9888 toc69
0
SCL
2V/div
SCL
2V/div
MCLK = 12.288MHz,
LRCLK = 48kHz
-10
NI MODE
-20
Z
SPK
= 8I+ 68µH
-30
-40
-50
-60
-70
-80
-90
SPEAKER
OUTPUT
1V/div
SPEAKER
OUTPUT
1V/div
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10ms/div
10ms/div
WIDEBAND FFT
(DAC TO SPEAKER)
FFT, -60dBFS (DAC TO SPEAKER)
FFT, -60dBFS (DAC TO SPEAKER)
0
0
-20
20
10
MCLK = 12.288MHz,
LRCLK = 48kHz
NI MODE
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
-20
-40
0
Z
SPK
= 8I+ 68µH
Z
SPK
= 8I+ 68µH
Z
SPK
= 8I+ 68µH
-40
-10
-20
-30
-40
-50
-60
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
1
10
FREQUENCY (MHz)
100
41
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
Line to Speaker
GAIN vs. FREQUENCY
(LINE TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO SPEAKER)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO SPEAKER)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
5
4
Z
AV
= 8I+ 68µH
Z
C
AV
= 8I+ 68µH
= 1µF
Z = 8I+ 68µH
SPK
C = 1µF
IN
SPK
SPK
IN
= +8dB
SPK_
3
= +8dB
SPK_
2
1
P
= 0.55W
OUT
0
f = 6000Hz
-1
-2
-3
-4
-5
P
= 0.25W
OUT
f = 100Hz
0.6
f = 1000Hz
0.2
0
0.4
0.8
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
OUTPUT POWER (W)
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO SPEAKER)
CROSSTALK vs. FREQUENCY
(LINE TO SPEAKER)
0
-20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
Z
= 8I+ 68µH
SPK
V
= 200mV
RMS
RIPPLE
INPUT AC GROUNDED
RIPPLE ON AVDD,
DVDD, HPVDD
-40
-60
-80
RIPPLE ON SPKLVDD,
SPKRVDD
-100
10
100
1000
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
FREQUENCY (Hz)
42
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
DAC to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
0
0
0
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
R
= 32I
R
= 32I
HP
HP
HP
AV
HP_
= +3dB
AV
HP_
= +3dB
AV
HP_
= +3dB
f = 6000Hz
f = 1000Hz
f = 3000Hz
f = 1000Hz
f = 6000Hz
f = 1000Hz
f = 100Hz
0.03 0.04
OUTPUT POWER (W)
f = 100Hz
0.03 0.04
OUTPUT POWER (W)
f = 100Hz
0.03 0.04
OUTPUT POWER (W)
0
0.01
0.02
0.05
0
0.01
0.02
0.05
0
0.01
0.02
0.05
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO SPEAKER)
0
0
0
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 13MHz
LRCLK = 8kHz
FREQ MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
R
= 16I
R
= 32I
HP
HP
HP
AV
HP_
= +3dB
AV
HP_
= +3dB
AV
HP_
= +3dB
f = 6000Hz
f = 1000Hz
f = 6000Hz
f = 1000Hz
P
= 0.01W
OUT
f = 100Hz
P
= 0.02W
OUT
f = 100Hz
0.03 0.04
OUTPUT POWER (W)
0
0.01
0.02
0.05
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
OUTPUT POWER (W)
10
100
1000
10,000
FREQUENCY (Hz)
43
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
0
0
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
R
= 32I
R
= 32I
HP
HP
HP
AV
HP_
= +3dB
AV
HP_
= +3dB
AV
HP_
= +3dB
P
= 0.025W
= 0.01W
P
= 0.025W
= 0.01W
OUT
OUT
P
= 0.025W
OUT
P
P
OUT
OUT
P
= 0.1W
OUT
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (DAC TO HEADPHONE)
GAIN vs. FREQUENCY
(DAC TO HEADPHONE)
HPVDD INPUT CURRENT vs. OUTPUT
POWER (DAC TO HEADPHONE)
0
10
0
120
100
80
60
40
20
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-10
-20
-30
-40
-50
-60
-70
-80
-90
MODE = 1
-10
-20
-30
-40
-50
-60
-70
R
= 16I
HP
P
= 0.01W
OUT
P
MODE = 0
R
= 16I
HP
MCLK = 13MHz
LRCLK = 8kHz
NI MODE
R
= 32I
HP
= 0.0.25W
R
= 32I
OUT
HP
10
100
1000
10,000
100,000
10
100
1000
10,000
100,000
0.01
0.1
1
10
100
FREQUENCY (Hz)
FREQUENCY (Hz)
OUTPUT POWER PER CHANNEL (mW)
44
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (DAC TO HEADPHONE)
CROSSTALK vs. FREQUENCY
(DAC TO HEADPHONE)
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 0)
MAX9888 toc92
0
-40
-50
SCL
2V/div
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
V
= 200mV
P-P
RIPPLE
INPUT ALL ZEROS
-20
-40
R
= 32I
HP
-60
HEADPHONE
OUTPUT
-70
RIPPLE ON SPKLVDD,
SPKRVDD
0.5V/div
-60
-80
-80
-90
RIPPLE ON AVDD,
DVDD, HPVDD
-100
-100
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
10ms/div
FREQUENCY (Hz)
SOFTWARE TURN-ON/OFF RESPONSE
(DAC TO HEADPHONE, VSEN = 1)
FFT, 0dBFS (DAC TO HEADPHONE)
FFT, -60dBFS (DAC TO HEADPHONE)
MAX9888 toc93
0
0
-20
SCL
2V/div
MCLK = 13MHz,
LRCLK = 8kHz
FREQ MODE
MCLK = 13MHz,
LRCLK = 8kHz
FREQ MODE
-20
-40
-40
R
= 32I
R
= 32I
HP
HP
-60
-60
HEADPHONE
OUTPUT
-80
-80
0.5V/div
-100
-120
-140
-160
-100
-120
-140
10ms/div
0
5000
10,000
15,000
20,000
0
5000
10,000
15,000
20,000
FREQUENCY (Hz)
FREQUENCY (Hz)
45
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV = 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
SPK_
PGAIN_
PGAOUT_
HP_
REC
1. T = +25NC, unless otherwise noted.)
A
FFT, -60dBFS (DAC TO HEADPHONE)
FFT, 0dBFS (DAC TO HEADPHONE)
0
0
-20
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
MCLK = 13MHz,
LRCLK = 44.1kHz
PLL MODE
-20
-40
-60
R = 32I
HP
R
= 32I
HP
-40
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
0
5000
10,000
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
FREQUENCY (Hz)
FFT, 0dBFS (DAC TO HEADPHONE)
0
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
-20
-40
R
= 32I
HP
-60
-80
-100
-120
-140
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
46
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
FFT, -60dBFS (DAC TO HEADPHONE)
FFT, 0dBFS (DAC TO HEADPHONE)
FFT, -60dBFS (DAC TO HEADPHONE)
0
0
-20
0
-20
MCLK = 12.288MHz
LRCLK = 48kHz
NI MODE
MCLK = 12.288MHz
LRCLK = 96kHz
NI MODE
MCLK = 2.288MHz
LRCLK = 96kHz
NI MODE
-20
-40
-40
R
= 32I
R
= 32I
R
= 32I
HP
HP
HP
-40
-60
-80
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
-100
-120
-140
0
5000
10,000
15,000
20,000
0
5000
10,000
FREQUENCY (Hz)
15,000
20,000
0
5000
10,000
15,000
20,000
FREQUENCY (Hz)
FREQUENCY (Hz)
WIDEBAND FFT, -60dBFS
(DAC TO HEADPHONE)
WIDEBAND FFT, 0dBFS
(DAC TO HEADPHONE)
20
0
20
0
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
MCLK = 13MHz
LRCLK = 44.1kHz
PLL MODE
A
R
= -3dB
= 32I
A
R
= -3dB
= 32I
VHP_
HP
VHP_
HP
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
1
10
100
1000 10,000
0
1
10
100
1000 10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
47
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
Line to Headphone
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER (LINE TO HEADPHONE)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY (LINE TO HEADPHONE)
GAIN vs. FREQUENCY
(LINE TO HEADPHONE)
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
5
4
R
HP
A
VHP_
= 32I
= +3dB
R
C
= 32I
= 1µF
R
= 32I
HP
IN
HP
IN
C = 1µF
3
2
1
0
f = 6000Hz
-1
-2
-3
-4
-5
P
= 0.01W
OUT
f = 1000Hz
f = 100Hz
P
= 0.025W
OUT
0
0.01
0.02
0.03
0.04
0.05
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
OUTPUT POWER (W)
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
COMMON-MODE REJECTION RATIO
vs. FREQUENCY (LINE TO HEADPHONE)
CROSSTALK vs. FREQUENCY
(LINE TO HEADPHONE)
0
-20
70
60
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
R
= 32I
HP
V
= 200mV
V
C
R
= -6dBV
OUT
RIPPLE
P-P
= 1µF
IN
= 32I
HP
RIPPLE ON AVDD,
DVDD, HPVDD
AV
= 0dB
PGAIN_
-40
AV
= 20dB
PGAIN_
-60
RIPPLE ON SPKLVDD,
SPKRVDD
-80
-100
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
48
Stereo Audio CODEC
with FlexSound Technology
Typical Operating Characteristics (continued)
(V
AVDD
= V
= V
= V
= V
= +1.8V, V
= V
= 3.7V. Speaker loads (Z
) connected
SPK
HPVDD
DVDD
DVDDS1
DVDDS2
SPKLVDD
SPKRVDD
between SPK_P and SPK_N. Receiver load (R
) connected between RECP and RECN. Headphone loads (R ) connected from
REC
HP
= 1FF, C
C1N-C1P HPVSS
HPL or HPR to GND. R
= J, R
= J, Z
= J, C
= 2.2FF, C
= C
= C
= 1FF, C
HP
REC
SPK
REF
MICBIAS
PREG
REG
= 1FF. AV
= +20dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB,
ADCGAIN
MICPRE_
MICPGA_
DACATTN
DACGAIN
ADCLVL
AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, AV
= 0dB, MCLK = 12.288MHz, LRCLK = 48kHz, MAS =
PGAIN_
PGAOUT_
HP_
REC
SPK_
1. T = +25NC, unless otherwise noted.)
A
Speaker Bypass Switch
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
(SPEAKER BYPASS SWITCH)
ON RESISTANCE vs. V
(SPEAKER BYPASS SWITCH)
COM
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
-10
-20
-30
-40
-50
-60
-70
-80
I
= 20mA
SW
RECEIVER AMPLIFIER DRIVING
LOUDSPEAKER
Z
= 8I+ 68µH
SPK
V
= 3.0V
SPK_VDD
V
= 3.7V
SPK_VDD
V
f = 6000Hz
= 4.2V
SPK_VDD
V
= 5.0V
5
SPK_VDD
f = 1000Hz
f = 100Hz
0
1
2
3
4
6
0
0.05
0.10
0.15
0.20
V
(V)
OUTPUT POWER (W)
COM
OFF-ISOLATION vs. FREQUENCY
(SPEAKER BYPASS SWITCH)
0
-20
-40
-60
-80
SPEAKER AMP DRIVING LOUDSPEAKER
SPEAKER BYPASS SWITCH OPEN
MEASURED AT RXIN_
50I LOAD ON RXIN_
RECEIVER AMP DRIVING RXIN_
-100
-120
10
100
1000
10,000
100,000
FREQUENCY (Hz)
49
Stereo Audio CODEC
with FlexSound Technology
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
1
2
3
4
5
6
7
8
9
RECP/
RXINP
SPKRN
SPKRGND
SPKLVDD
SPKLP
SPKLN
HPVDD
HPGND
HPVSS
A
B
C
D
E
RECN/
RXINN
SPKRN
SPKRP
SPKRGND
SPKRP
SPKLVDD
SPKRVDD
SPKLP
SPKLN
C1P
N.C.
C1N
HPL
HPR
SPKLGND
SPKLGND
HPSNS
INB2
MAX9888
INA2/
EXTMICN
BCLKS1
LRCLKS1
SPKRVDD
SDINS1
N.C.
JACKSNS
N.C.
INB1
INA1/
EXTMICP
MIC1P/
DIGMICDATA
DVDDS1
DGND
MCLK
N.C.
SDOUTS1
IRQ
SCL
N.C.
REG
N.C.
REF
MIC1N/
DIGMICCLK
BCLKS2
DVDDS2
LRCLKS2
SDINS2
SDA
MIC2P
MIC2N
F
SDOUTS2
DVDD
AVDD
PREG
AGND
MICBIAS
G
50
Stereo Audio CODEC
with FlexSound Technology
Pin Description
PIN
NAME
FUNCTION
A1, B1
A2, B2
SPKRN
Negative Right-Channel Class D Speaker Output
SPKRGND Right-Speaker Ground
Left-Speaker, REF, Receiver Amplifier Power Supply. Bypass to SPKLGND with a 1FF and a 10FF
capacitor.
A3, B3
SPKLVDD
A4, B4
A5, B5
SPKLP
SPKLN
Positive Left-Channel Class D Speaker Output
Negative Left-Channel Class D Speaker Output
Positive Receiver Amplifier Output. Can be positive bypass switch input when receiver amp is shut
down.
A6
RECP/RXINP
A7
A8
A9
HPVDD
HPGND
HPVSS
Headphone Power Supply. Bypass to HPGND with a 1FF capacitor.
Headphone Ground
Inverting Charge-Pump Output. Bypass to HPGND with a 1FF ceramic capacitor.
Negative Receiver Amplifier Output. Can be negative bypass switch input when receiver amp is shut
down.
B6
B7
B8
RECN/RXINN
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1FF ceramic capacitor between C1N
and C1P.
C1N
B9
HPL
Left-Channel Headphone Output
C1, C2
C3, D3
C4, C5
SPKRP
Positive Right-Channel Class D Speaker Output
SPKRVDD Right-Speaker Power Supply. Bypass to SPKRGND with a 1FF capacitor.
SPKLGND Left-Speaker Ground
Headphone Amplifier Ground Sense. Connect to the headphone jack ground terminal or connect to
C6
HPSNS
ground.
C7, D5, D7,
E3, E6, E7
N.C.
No Connection
C8
C9
INB2
HPR
Single-Ended Line Input B2. Also positive differential line input B.
Right-Channel Headphone Output
S1 Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9888 is in slave mode and
an output when in master mode. The input/output voltage is referenced to DVDDS1.
D1
BCLKS1
S1 Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and
determines whether S1 audio data is routed to the left or right channel. In TDM mode, LRCLKS1 is a
frame sync pulse. LRCLKS1 is an input when the MAX9888 is in slave mode and an output when in
master mode. The input/output voltage is referenced to DVDDS1.
D2
LRCLKS1
SDINS1
D4
D6
D8
S1 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS1.
JACKSNS Jack Sense. Detects the insertion of a jack. See the Headset Detection section.
INB1
Single-Ended Line Input B1. Also negative differential line input B.
INA2/
Single-Ended Line Input A2. Also positive differential line input A or negative differential external
D9
EXTMICN microphone input.
51
Stereo Audio CODEC
with FlexSound Technology
Pin Description (continued)
PIN
E1
NAME
DVDDS1
MCLK
FUNCTION
S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
E2
Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz.
E4
SDOUTS1 S1 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS1.
Hardware Interrupt Output. IRQ can be programmed to pull low when bits in status register 0x00
change state. Read status register 0x00 to clear IRQ once set. Repeat faults have no effect on IRQ
E5
E8
IRQ
until it is cleared by reading the I2C status register 0x00. Connect a 10kIpullup resistor to DVDD for
full output swing.
MIC1P/
Positive Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
DIGMICDATA be retasked as a digital microphone data input.
INA1/ Single-Ended Line Input A1. Also negative differential line input A or positive differential external
EXTMICP microphone input.
E9
F1
F2
DGND
Digital Ground
S2 Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the IC is in slave mode and an
output when in master mode. The input/output voltage is referenced to DVDDS2.
BCLKS2
S2 Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and
determines whether audio data on S2 is routed to the left or right channel. In TDM mode, LRCLKS2 is
a frame sync pulse. LRCLKS2 is an input when the IC is in slave mode and an output when in master
mode. The input/output voltage is referenced to DVDDS2.
F3
LRCLKS2
F4
F5
F6
F7
SDA
SCL
I2C Serial-Data Input/Output. Connect a pullup resistor to DVDD for full output swing.
I2C Serial-Clock Input
REG
Common-Mode Voltage Reference. Bypass to AGND with a 1FF capacitor.
Converter Reference. Bypass to AGND with a 2.2FF capacitor.
Negative Differential Microphone 1 Input. AC-couple a microphone with a series 1FF capacitor. Can
REF
MIC1N/
F8
DIGMICCLK be retasked as a digital microphone clock output.
MIC2P Positive Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
SDOUTS2 S2 Digital Audio Serial-Data ADC Output. The output voltage is referenced to DVDDS2.
F9
G1
G2
G3
DVDDS2
SDINS2
S2 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor.
S2 Digital Audio Serial-Data DAC Input. The input voltage is referenced to DVDDS2.
Digital Power Supply. Supply for the digital core and I2C interface. Bypass to DGND with a 1FF
capacitor.
G4
DVDD
G5
G6
G7
AVDD
PREG
AGND
Analog Power Supply. Bypass to AGND with a 1FF capacitor.
Positive Internal Regulated Supply. Bypass to AGND with a 1FF capacitor.
Analog Ground
Low-Noise Bias Voltage. Outputs a 2.2V microphone bias. An external resistor in the 2.2kI to 1kI
range should be used to set the microphone current.
G8
G9
MICBIAS
MIC2N
Negative Differential Microphone 2 Input. AC-couple a microphone with a series 1FF capacitor.
52
Stereo Audio CODEC
with FlexSound Technology
When the receiver amplifier is disabled, analog switches
Detailed Description
The MAX9888 is a fully integrated stereo audio codec
with FlexSound technology and integrated amplifiers.
allow RECP/RXINP and RECN/RXINN to be reused for
signal routing. In systems where a single transducer is
used for both the loudspeaker and receiver, an exter-
nal receiver amplifier can be routed to the left speaker
through RECP/RXINP and RECN/RXINN, bypassing the
Class D amplifier, to connect to the loudspeaker. If the
internal receiver amplifier is used, then leave RECP/
RXINP and RECN/RXINN unconnected. In systems
where an external amplifier drives both the receiver and
the MAX9888’s input, one of the differential signals can
be disconnected from the receiver when not needed
by passing it through the analog switch that connects
RECP/RXINP to RECN/RXINN.
Two differential microphone amplifiers can accept sig-
nals from three analog inputs. One input can be retasked
to support two digital microphones. Any combination of
two microphones (analog or digital) can be recorded
simultaneously. The analog signals are amplified up
to 50dB and recorded by the stereo ADC. The digital
record path supports voice filtering with selectable
preset highpass filters and high stopband attenuation
at f /2. An automatic gain control (AGC) circuit moni-
S
tors the digitized signal and automatically adjusts the
analog microphone gain to make best use of the ADC’s
dynamic range. A noise gate attenuates signals below
the user-defined threshold to minimize the noise output
by the ADC.
The stereo Class D amplifier provides efficient amplifi-
cation for two speakers. The amplifier includes active
emissions limiting to minimize the radiated emissions
(EMI) traditionally associated with Class D. In most
systems, no output filtering is required to meet standard
EMI limits.
The IC includes two analog line inputs. One of the line
inputs can be optionally retasked as a third analog micro-
phone input. Both line inputs support either stereo single-
ended input signals or mono differential signals. The line
inputs are preamplified and then routed either to the ADC
for recording or to the output amplifiers for playback.
To optimize speaker sound quality, the IC includes an
excursion limiter, a distortion limiter, and a power limiter.
The excursion limiter is a dynamic highpass filter with
variable corner frequency that increases in response
to high signal levels. Low-frequency energy typically
causes more distortion than useful sound at high sig-
nal levels, so attenuating low frequencies allows the
speaker to play louder without distortion or damage. At
lower signal levels, the filter corner frequency reduces
to pass more low frequency energy when the speaker
can handle it. The distortion limiter reduces the volume
when the output signal exceeds a preset distortion level.
This ensures that regardless of input signal and battery
voltage, excessive distortion is never heard by the user.
The power limiter monitors the continuous power into the
loudspeaker and lowers the signal level if the speaker is
at risk of overheating.
Integrated analog switches allow two differential micro-
phone signals to be routed out the third microphone
input to an external device. This eliminates the need
for an external analog switch in systems that have two
devices recording signals from the same microphone.
Through two digital audio interfaces, the device can
transmit one stereo audio signal and receive two stereo
audio signals in a wide range of formats including I2S,
PCM, and up to four mono slots in TDM. Each interface
can be connected to either of two audio ports (S1 and
S2) for communication with external devices. Both audio
interfaces support 8kHz to 96kHz sample rates. Each
input signal is independently equalized using 5-band
parametric equalizers. A multiband automatic level
control (ALC) boosts signals by up to 12dB. One signal
path additionally supports the same voiceband filtering
as the ADC path.
The stereo DirectDrive headphone amplifier uses an
inverting charge pump to generate a ground-referenced
output signal. This eliminates the need for DC-blocking
capacitors or a midrail bias for the headphone jack
ground return. Ground sense reduces output noise
caused by ground return current.
The IC includes a differential receiver amplifier, stereo
Class D speaker amplifiers, and DirectDrive true ground
stereo headphone amplifiers.
The IC integrates jack detection allowing the detection
of insertion and removal of accessories as well as button
presses.
53
Stereo Audio CODEC
with FlexSound Technology
2
I C Slave Address
Registers
Configure the MAX9888 using the I2C control bus. The
IC uses a slave address of 0x20 or 00100000 for write
operations and 0x21 or 00100001 for read operations.
See the I2C Serial Interface section for a complete inter-
face description.
Table 1 lists all of the registers, their addresses, and
power-on-reset states. Registers 0x00 to 0x03 and 0xFF
are read-only while all of the other registers are read/
write. Write zeros to all unused bits in the register table
when updating the register, unless otherwise noted.
Table 1. Register Map
REGISTER
STATUS
Status
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
CLD
SLD
NG
ULK
—
—
—
AGC
—
JDET
—
0x00
0x01
0x02
0x03
—
—
—
—
R
R
R
103
65
Microphone
AGC/NG
Jack Status
JKSNS
—
—
—
0
—
—
—
101
Battery
Voltage
—
—
VBAT
R/W 102
R/W 103
Interrupt
Enable
ICLD
ISLD
IULK
0
0
0
0
IJDET
0
0
0
0x0F
0x10
0x00
0x00
MASTER CLOCK CONTROL
Master Clock
0
0
PSCLK
R/W
76
DAI1 CLOCK CONTROL
Clock Mode
SR1
FREQ1
0x11
0x12
0x13
0x00
0x00
0x00
R/W
R/W
R/W
76
77
77
PLL1
NI1[14:8]
Any Clock
Control
NI1[7:1]
NI1[0]
WS1
DAI1 CONFIGURATION
Format
Clock
MAS1
WCI1
BCI1
0
DLY1
0
0
0
TDM1
FSW1
0x14
0x15
0x00
0x00
R/W
R/W
71
72
OSR1
BSEL1
I/O
SEL1
LTEN1
LBEN1 DMONO1 HIZOFF1 SDOEN1 SDIEN1
SLOTDLY1
DVFLT1
0x16
0x00
R/W
72
Configuration
Time-Division
Multiplex
SLOTL1
SLOTR1
0x17
0x18
0x00
0x00
R/W
R/W
73
79
Filters
MODE1
AVFLT1
DHF1
DAI2 CLOCK CONTROL
Clock Mode
SR2
0
0
0
0
0x19
0x1A
0x1B
0x00
0x00
0x00
R/W
R/W
R/W
76
77
77
PLL2
NI2[14:8]
Any Clock
Control
NI2[7:1]
NI2[0]
DAI2 CONFIGURATION
Format
Clock
MAS2
0
WCI2
0
BCI2
DLY2
0
0
0
TDM2
FSW2
WS2
0x1C
0x1D
0x1E
0x00
0x00
0x00
R/W
R/W
R/W
71
72
72
0
0
BSEL2
I/O
SEL2
LBEN2 DMONO2 HIZOFF2 SDOEN2 SDIEN2
Configuration
54
Stereo Audio CODEC
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
Time-Division
Multiplex
SLOTL2
SLOTR2
SLOTDLY2
0x1F
0x20
0x00
0x00
R/W
R/W
73
79
Filters
0
0
0
0
DHF2
0
0
DCB2
MIXERS
DAC Mixer
MIXDAL
MIXDAR
0x21
0x22
0x00
0x00
R/W
R/W
85
64
Left ADC
Mixer
MIXADL
MIXADR
Right ADC
Mixer
0x23
0x24
0x25
0x26
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
64
86
86
86
Preoutput 1
Mixer
0
0
0
0
0
0
0
0
0
0
0
0
MIXOUT1
MIXOUT2
MIXOUT3
Preoutput 2
Mixer
Preoutput 3
Mixer
Headphone
Amplifier
Mixer
MIXHPL
MIXHPR
MIXREC
MIXSPR
0x27
0x28
0x29
0x00
0x00
0x00
R/W
R/W
R/W
97
88
90
Receiver
Amplifier
Mixer
0
0
0
0
0
Speaker
Amplifier
Mixer
MIXSPL
LEVEL CONTROL
Sidetone
DSTS
DVST
0x2A
0x2B
0x00
0x00
R/W
R/W
69
84
DAI1
Playback
Level
DV1M
0
0
0
0
DV1G
DV1
DVEQ1
DV2
DAI1
Playback
Level
0
0
0
0
0x2C
0x2D
0x2E
0x00
0x00
0x00
R/W
R/W
R/W
83
84
83
EQCLP1
DAI2
Playback
Level
DV2M
0
0
DAI2
Playback
Level
DVEQ2
EQCLP2
Left ADC
Level
0
0
0
0
0
AVLG
AVRG
AVL
AVR
0x2F
0x30
0x31
0x00
0x00
0x00
R/W
R/W
R/W
68
68
61
Right ADC
Level
Microphone
1 Input Level
PA1EN
PGAM1
55
Stereo Audio CODEC
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
Microphone
2 Input Level
0
PA2EN
PGAM2
0x32
0x33
0x34
0x35
0x36
0x37
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
61
63
63
87
87
87
INA Input
Level
0
0
0
0
0
INAEXT
0
0
0
0
0
0
0
0
0
0
0
0
PGAINA
PGAINB
INB Input
Level
INBEXT
Preoutput 1
Level
0
0
0
PGAOUT1
Preoutput 2
Level
PGAOUT2
PGAOUT3
Preoutput 3
Level
Left
Headphone
Amplifier
Volume
Control
HPLM
HPRM
0
0
0
0
HPVOLL
0x38
0x39
0x00
0x00
R/W
R/W
97
97
Right
Headphone
Amplifier
Volume
Control
HPVOLR
Receiver
Amplifier
Volume
Control
RECM
SPLM
0
0
0
0
RECVOL
SPVOLL
0x3A
0x3B
0x00
0x00
R/W
R/W
88
90
Left Speaker
Amplifier
Volume
Control
Right
Speaker
Amplifier
Volume
Control
SPRM
0
0
SPVOLR
0x3C
0x00
R/W
90
MICROPHONE AGC
Configuration AGCSRC
Threshold
AGCRLS
AGCATK
AGCHLD
0x3D
0x3E
0x00
0x00
R/W
R/W
65
66
ANTH
AGCTH
SPEAKER SIGNAL PROCESSING
Excursion
Limiter Filter
0
DHPUCF
0
0
DHPLCF
0x3F
0x00
R/W
92
Excursion
Limiter
Threshold
0
0
0
0
0
DHPTH
ALCTH
0x40
0x41
0x00
0x00
R/W
R/W
92
82
ALC
ALCEN
ALCRLS
ALCMB
56
Stereo Audio CODEC
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
Power Limiter
Power Limiter
B7
B6
PWRTH
PWRT2
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
0
PWRK
0x42
0x43
0x00
0x00
R/W
R/W
93
94
PWRT1
Distortion
Limiter
THDCLP
0
THDT1
0x44
0x00
R/W
95
CONFIGURATION
Audio Input INADIFF INBDIFF
0
0
0
0
0
0
0
0
0
0
0x45
0x46
0x47
0x00
0x00
0x00
R/W
R/W
63
61
Microphone
MICCLK
DIGMICL DIGMICR
EXTMIC
Level Control
0
EQ2EN EQ1EN
R/W 99, 83
VS2EN
VSEN
ZDEN
Bypass
Switches
INABYP
JDETEN
0
0
MIC2BYP
0
0
0
0
RECBYP SPKBYP
0x48
0x49
0x00
0x00
R/W 62, 98
Jack
Detection
0
0
0
0
0
JDEB
R/W 101
POWER MANAGEMENT
Input Enable INAEN INBEN
MBEN
0
0
ADLEN ADREN
DALEN DAREN
0x4A
0x4B
0x00
0x00
R/W
R/W
59
59
Output Enable HPLEN HPREN SPLEN SPREN RECEN
System
Enable
VBATEN
0
0
0
0
JDWK
0
0x4C
0x00
R/W
59
SHDN
DSP COEFFICIENTS
K_1[15:8]
K_1[7:0]
0x50/0x82
0x51/0x83
0x52/0x84
0x53/0x85
0x54/0x86
0x55/0x87
0x56/0x88
0x57/0x89
0x58/0x8A
0x59/0x8B
0x5A/0x8C
0x5B/0x8D
0x5C/0x8E
0x5D/0x8F
0x5E/0x90
0x5F/0x91
0x60/0x92
0x61/0x93
0x62/0x94
0x63/0x95
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
K1_1[15:8]
K1_1[7:0]
K2_1[15:8]
K2_1[7:0]
c1_1[15:8]
c1_1[7:0]
c2_1[15:8]
c2_1[7:0]
K_2[15:8]
K_2[7:0]
EQ Band 1
(DAI1/DAI2)
K1_2[15:8]
K1_2[7:0]
K2_2[15:8]
K2_2[7:0]
c1_2[15:8]
c1_2[7:0]
c2_2[15:8]
c2_2[7:0]
EQ Band 2
(DAI1/DAI2)
57
Stereo Audio CODEC
with FlexSound Technology
Table 1. Register Map (continued)
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
ADDRESS DEFAULT R/W PAGE
K_3[15:8]
0x64/0x96
0x65/0x97
0x66/0x98
0x67/0x99
0x68/0x9A
0x69/0x9B
0x6A/0x9C
0x6B/0x9D
0x6C/0x9E
0x6D/0x9F
0x6E/0xA0
0x6F/0xA1
0x70/0xA2
0x71/0xA3
0x72/0xA4
0x73/0xA5
0x74/0xA6
0x75/0xA7
0x76/0xA8
0x77/0xA9
0x78/0xAA
0x79/0xAB
0x7A/0xAC
0x7B/0xAD
0x7C/0xAE
0x7D/0xAF
0x7E/0xB0
0x7F/0xB1
0x80/0xB2
0x81/0xB3
0xB4/0xBE
0xB5/0xBF
0xB6/0xC0
0xB7/0xC1
0xB8/0xC2
0xB9/0xC3
0xBA/0xC4
0xBB/0xC5
0xBC/0xC6
0xBD/0xC7
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
0xXX
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
82
91
91
91
91
91
91
91
91
91
91
K_3[7:0]
K1_3[15:8]
K1_3[7:0]
K2_3[15:8]
K2_3[7:0]
c1_3[15:8]
c1_3[7:0]
c2_3[15:8]
c2_3[7:0]
K_4[15:8]
K_4[7:0]
EQ Band 3
(DAI1/DAI2)
K1_4[15:8]
K1_4[7:0]
K2_4[15:8]
K2_4[7:0]
c1_4[15:8]
c1_4[7:0]
c2_4[15:8]
c2_4[7:0]
K_5[15:8]
K_5[7:0]
EQ Band 4
(DAI1/DAI2)
K1_5[15:8]
K1_5[7:0]
K2_5[15:8]
K2_5[7:0]
c1_5[15:8]
c1_5[7:0]
c2_5[15:8]
c2_5[7:0]
a1[15:8]
EQ Band 5
(DAI1/DAI2)
a1[7:0]
a2[15:8]
a2[7:0]
Excursion
Limiter
Biquad
b0[15:8]
b0[7:0]
(DAI1/DAI2)
b1[15:8]
b1[7:0]
b2[15:8]
b2[7:0]
REVISION ID
Rev ID
REV
0xFF
0x43
R
104
58
Stereo Audio CODEC
with FlexSound Technology
Power Management
The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply
current.
Table 2. Power Management Registers
REGISTER
BIT
NAME
DESCRIPTION
Global Shutdown
Disables everything except the headset detection circuitry, which is controlled
7
separately.
SHDN
0 = Device shutdown
1 = Device enabled
0x4C
6
1
VBATEN
JDWK
See the Battery Measurement section.
See the Headset Detection section.
Line Input A Enable
0 = Disabled
1 = Enabled
Line Input B Enable
0 = Disabled
1 = Enabled
Microphone Bias Enable
0 = Disabled
1 = Enabled
Left ADC Enable
0 = Disabled
1 = Enabled
Right ADC Enable
0 = Disabled
1 = Enabled
Left Headphone Enable
0 = Disabled
1 = Enabled
Right Headphone Enable
0 = Disabled
1 = Enabled
Left Speaker Enable
0 = Disabled
1 = Enabled
Right Speaker Enable
0 = Disabled
1 = Enabled
Receiver Enable
0 = Disabled
1 = Enabled
Left DAC Enable
0 = Disabled
1 = Enabled
Right DAC Enable
0 = Disabled
7
6
3
1
0
7
6
5
4
3
1
0
INAEN
INBEN
MBEN
0x4A
ADLEN
ADREN
HPLEN
HPREN
SPLEN
SPREN
RECEN
DALEN
DAREN
0x4B
1 = Enabled
59
Stereo Audio CODEC
with FlexSound Technology
MIC2P/MIC2N and EXTMICP/EXTMICN. MIC1P/MIC1N
Microphone Inputs
The device includes three differential microphone inputs
and a low-noise microphone bias for powering the micro-
phones (Figure 6). One microphone input can also be con-
figured as a digital microphone input accepting signals
from up to two digital microphones. Two microphones,
analog or digital, can be recorded simultaneously.
then become outputs that route the microphone signals
to an external device as needed. Two devices can then
record microphone signals without needing external
analog switches.
Analog microphone signals are amplified by two stages
of gain and then routed to the ADCs. The first stage offers
selectable 0dB, 20dB, or 30dB settings. The second
stage is a programmable-gain amplifier (PGA) adjustable
from 0dB to 20dB in 1dB steps. To maximize the signal-
to-noise ratio, use the gain in the first stage whenever
possible. Zero-crossing detection is included on the PGA
to minimize zipper noise while making gain changes.
In the typical application, one microphone input is used
for the handset microphone and the other is used as an
accessory microphone. In systems using a background
noise microphone, INA can be retasked as another
microphone input.
In systems where the codec is not the only device
recording microphone signals, connect microphones to
MCLK
MICBIAS
PSCLK
REG
CLOCK
MBEN
CONTROL
MIC1P/
PGAM1:
+20dB TO 0dB
DIGMICDATA
MIC1N/
DIGMICCLK
EXTMIC
PA1EN:
0/20/30dB
MIC2BYP
ADLEN
MIC2P
MIX
ADCL
MIC2N
PGAM1:
+20dB TO 0dB
MIXADL
EXTMIC
PA2EN:
0/20/30dB
PGAINA:
+20dB TO -6dB
INABYP
MIX
ADCR
ADREN
INA1/EXTMICP
INA2/EXTMICN
INADIFF
MIXADR
PGAINA:
+20dB TO -6dB
Figure 6. Microphone Input Block Diagram
60
Stereo Audio CODEC
with FlexSound Technology
Table 3. Microphone Input Registers
REGISTER
BIT
NAME
DESCRIPTION
MIC1/MIC2 Preamplifier Gain
6
Course microphone gain adjustment.
00 = Preamplifier disabled
01 = 0dB
PA1EN/PA2EN
10 = 20dB
11 = 30dB
5
4
MIC1/MIC2 PGA
Fine microphone gain adjustment.
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
VALUE
0x0B
GAIN (dB)
3
2
1
0
7
6
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
0x31/0x32
+19
0x0C
+18
0x0D
+17
0x0E
PGAM1/PGAM2
+16
0x0F
+15
0x10
+14
0x11
+13
0x12
+12
0x13
+11
0x14 to 0x1F
+10
Digital Microphone Clock Frequency
Select a frequency that is within the digital microphone’s clock frequency range.
Set OSR1 = 1 when using a digital microphone.
00 = PCLK/8
01 = PCLK/6
MICCLK
10 = 64 x LRCLK
11 = Reserved
Left Digital Microphone Enable
Set PAL1EN = 00 for proper operation.
0 = Disabled
5
4
DIGMICL
DIGMICR
1 = Enabled
0x46
Right Digital Microphone Enable
Set PAR1EN = 00 for proper operation.
0 = Disabled
1 = Enabled
External Microphone Connection
Routes INA_/EXTMIC_ to the microphone preamplifiers. Set INAEN = 0 when using
INA_/EXTMIC_ as a microphone input.
00 = Disabled
01 = MIC1 input
10 = MIC2 input
1
0
EXTMIC
11 = Reserved
61
Stereo Audio CODEC
with FlexSound Technology
Table 3. Microphone Input Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
INA_/EXTMIC_ to MIC1_ Bypass Switch
7
INABYP
0 = Disabled
1 = Enabled
MIC1_ to MIC2_ Bypass Switch
0 = Disabled
1 = Enabled
4
1
0
MIC2BYP
RECBYP
SPKBYP
0x48
See the Output Bypass Switches section.
by choosing the appropriate input resistor and using the
following formula:
AV
Line Inputs
The device includes two sets of line inputs (Figure 7).
Each set can be configured as a stereo single-ended
input or as a mono differential input. Each input includes
adjustable gain to match a wide range of input signal
levels. If a custom gain is needed, the external gain
mode provides a trimmed feedback resistor. Set the gain
= 20 x log (20K/RIN)
PGAIN
The external gain mode also allows summing multiple
signals into a single input, by connecting multiple input
resistors as show in Figure 8, and inputting signals larger
than 1V
.
P-P
INABYP
PGAINA:
+20dB TO -6dB
INA1/
EXTMICP
INADIFF
LEFT
INPUT 1
PGAINA:
+20dB TO -6dB
20kI
20kI
MIX
INA2/
EXTMICN
LEFT
INPUT 2
INA1/EXTMICP
INA2/EXTMICN
MIXOUT1
VCM
VCM
RIGHT
INPUT 1
PGAINB:
+20dB TO -6dB
MIX
RIGHT
INPUT 2
INB1
INB2
INBDIFF
MIXOUT2
PGAINB:
+20dB TO -6dB
MIX
MIXOUT3
Figure 7. Line Input Block Diagram
Figure 8. Summing Multiple Input Signals into INA/INB
62
Stereo Audio CODEC
with FlexSound Technology
Table 4. Line Input Registers
REGISTER
BIT
NAME
DESCRIPTION
Line Input A/B External Gain
Switches out the internal input resistor and selects a trimmed 20kIfeedback resistor.
6
INAEXT/INBEXT
Use an external input resistor to set the gain of the line input.
0 = Disabled
1 = Enabled
Line Input A/B Internal Gain Settings
000 = +20dB
001 = +14dB
2
1
0
0x33/0x34
010 = +3dB
PGAINA/PGAINB 011 = 0dB
100 = -3dB
101 = -6dB
110 = -6dB
111 = -6dB
Line Input A Differential Enable
7
6
INADIFF
INBDIFF
0 = Stereo single-ended input
1 = Mono differential input
0x45
Line Input B Differential Enable
0 = Stereo single-ended input
1 = Mono differential input
ADC Input Mixers
PGAM1:
+20dB TO 0dB
The device’s stereo ADC accepts input from the micro-
phone amplifiers and line inputs. The ADC mixer routes
any combination of the six audio inputs to the left and
right ADCs (Figure 9).
PA1EN:
0/20/30dB
ADLEN
ADCL
MIX
PGAM2:
+20dB TO 0dB
MIXADL
PA2EN:
0/20/30dB
ADCR
ADREN
MIX
PGAINA:
+20dB TO -6dB
MIXADR
INADIFF
PGAINA:
+20dB TO -6dB
+
+
PGAINB:
+20dB TO -6dB
INBDIFF
PGAINB:
+20dB TO -6dB
Figure 9. ADC Input Mixer Block Diagram
63
Stereo Audio CODEC
with FlexSound Technology
Table 5. ADC Input Mixer Register
REGISTER
BIT
7
NAME
DESCRIPTION
Left/Right ADC Input Mixer
Selects which analog inputs are recorded by the left/right ADC.
1xxxxxxx = MIC1
x1xxxxxx = MIC2
xx1xxxxx = Reserved
xxx1xxxx = Reserved
xxxx1xxx = INA1
xxxxx1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xxxxxx1x = INB1
6
5
4
0x22/0x23
MIXADL/MIXADR
3
2
1
xxxxxxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
0
Noise Gate
Since the AGC increases the levels of all signals below
a user-defined threshold, the noise floor is effectively
increased by 20dB. To counteract this, the noise gate
reduces the gain at low signal levels. Unlike typical noise
gates that completely silence the output below a defined
level, the noise gate in the IC applies downward expan-
sion. The noise gate attenuates the output at a rate of
1dB for each 2dB the signal is below the threshold.
Record Path Signal Processing
The device’s record signal path includes both automatic
gain control (AGC) for the microphone inputs and a digi-
tal noise gate at the output of the ADC (Figure 10).
Microphone AGC
The IC’s AGC monitors the signal level at the output of
the ADC and then adjusts the MIC1 and MIC2 analog
PGA settings automatically. When the signal level is
below the predefined threshold, the gain is increased up
to its maximum (20dB). If the signal exceeds the thresh-
old, the gain is reduced to prevent the output signal level
exceeding the threshold. When AGC is enabled, the
microphone PGA is not user programmable. The AGC
provides a more constant signal level and improves the
available ADC dynamic range.
The noise gate can be used in conjunction with the AGC
or on its own. When the AGC is enabled, the noise gate
reduces the output level only when the AGC has set the
gain to the maximum setting. Figure 11 shows the gain
response resulting from using the AGC and noise gate.
AGC AND NOISE GATE
AMPLITUDE RESPONSE
PGAM1:
+20dB TO -6dB
0
NOISE GATE
AGC ONLY
AUTOMATIC
AUDIO/
-20
GAIN
VOICE
PA1EN:
CONTROL
FILTERS
MODE1
AVFLT
AGC AND NOISE GATE
-40
0/20/30dB
ADLEN
ADCL
PGAM2:
+20dB TO 0dB
MIX
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
-60
MIXADL
AGC AND NOISE
GATE DISABLED
PA2EN:
0/20/30dB
-80
NOISE GATE ONLY
ADCR
ADREN
MIX
-100
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
MIXADR
-120
-120
-100
-80
-60
-40
-20
0
INPUT AMPLITUDE (dBFS)
Figure 10. Record Path Signal Processing Block Diagram
Figure 11. AGC and Noise Gate Input vs. Output Gain
64
Stereo Audio CODEC
with FlexSound Technology
Table 6. Record Path Signal Processing Registers
REGISTER
BIT
NAME
DESCRIPTION
Noise Gate Attenuation
Reports the current noise gate attenuation.
000 = 0dB
7
001 = 1dB
010 = 2dB
6
5
4
NG
011 = 3dB to 5dB
100 = 6dB to 7dB
101 = 8dB to 9dB
110 = 10dB to 11dB
111 = 12dB
AGC Gain
Reports the current AGC gain setting.
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN (dB)
+20
VALUE
0x0B
GAIN (dB)
0x01
+9
+8
+7
+6
+5
+4
+3
+2
+1
0
3
2
+19
0x0C
+18
0x0D
+17
0x0E
AGC
+16
0x0F
+15
0x10
+14
0x11
1
0
+13
0x12
+12
0x13
+11
0x14 to 0x1F
+10
AGC/Noise Gate Signal Source
Determines which ADC channel the AGC and noise gates analyze. Gain is adjusted on
both channels regardless of the AGCSRC setting.
0 = Left ADC output
7
AGCSRC
1 = Maximum of either the left or right ADC output
AGC Release Time
Defined as the duration from start to finish of gain increase in the region shown in Figure
12. Release times are longer for low AGC threshold levels.
6
5
4
0x3D
000 = 78ms
001 = 156ms
010 = 312ms
011 = 625ms
100 = 1.25s
101 = 2.5s
110 = 5s
AGCRLS
111 = 10s
65
Stereo Audio CODEC
with FlexSound Technology
Table 6. Record Path Signal Processing Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
AGC Attack Time
Defined as the time required to reduce gain by 63% of the total gain reduction (one time
constant of the exponential response). Attack times are longer for low AGC threshold
3
levels. See Figure 12 for details.
00 = 2ms
AGCATK
01 = 7.2ms
10 = 31ms
11 = 123ms
2
1
0x3D
AGC Hold Time
The delay before the AGC release begins. The hold time counter starts whenever the
signal drops below the AGC threshold and is reset by any signal that exceeds the
AGCHLD
threshold. Set AGCHLD to enable the AGC circuit. See Figure 12 for details.
00 = AGC disabled
01 = 50ms
10 = 100ms
0
7
11 = 400ms
Noise Gate Threshold
Gain is reduced for signals below the threshold to quiet noise. The thresholds are relative
to the ADC’s full-scale output voltage.
THRESHOLD
(dBFS)
THRESHOLD
(dBFS)
VALUE
VALUE
6
5
0x0
Noise gate disabled
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
-45
-41
-38
-34
-30
-27
-22
-16
0x1
Reserved
Reserved
-64
ANTH
0x2
0x3
0x4
-62
0x5
0x6
-58
4
3
-53
0x7
-50
0x3E
AGC Threshold
Gain is reduced when signals exceed the threshold to prevent clipping. The thresholds
are relative to the ADC’s full-scale voltage.
THRESHOLD
(dBFS)
THRESHOLD
(dBFS)
VALUE
VALUE
2
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-3
-4
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
-11
-12
-13
-14
-15
-16
-17
-18
AGCTH
-5
1
0
-6
-7
-8
-9
-10
66
Stereo Audio CODEC
with FlexSound Technology
ATTACK TIME
HOLD TIME
RELEASE TIME
Figure 12. AGC Timing
range, use analog gain to adjust the signal level and set
the digital level control to 0dB whenever possible. Digital
level control is primarily used when adjusting the record
level for digital microphones.
ADC Record Level Control
The IC includes separate digital level control for the left
and right ADC outputs (Figure 13). To optimize dynamic
NOISE GATE
AUDIO/
VOICE
FILTERS
AUTOMATIC
GAIN CONTROL
MODE1
AVFLT1
ADLEN
ADCL
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
ADCR
ADREN
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
Figure 13. ADC Record Level Control Block Diagram
67
Stereo Audio CODEC
with FlexSound Technology
Table 7. ADC Record Level Control Register
REGISTER
BIT
NAME
DESCRIPTION
Left/Right ADC Gain
00 = 0dB
5
AVLG/AVRG
01 = 6dB
10 = 12dB
11 = 18dB
4
Left/Right ADC Level
3
2
VALUE
0x0
GAIN (dB)
VALUE
0x8
GAIN (dB)
+3
+2
+1
0
-5
-6
0x2F/0x30
0x1
0x9
0x2
0xA
0xB
0xC
0xD
0xE
-7
AVL/AVR
1
0
0x3
-8
0x4
-1
-2
-3
-4
-9
0x5
-10
-11
-12
0x6
0x7
0xF
used in telephony to allow the speaker to hear himself
speak, providing a more natural user experience. The
IC implements sidetone digitally. Doing so helps prevent
unwanted feedback into the playback signal path and
better matches the playback audio signal.
Sidetone
Enable sidetone during full-duplex operation to add a
low-level copy of the recorded audio signal to the play-
back audio signal (Figure 14). Sidetone is commonly
DV1G:
0/6/12/18dB
DVST:
0dB TO -60dB
SIDETONE
DSTS
MIX
+
MULTIBAND ALC
NOISE GATE
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
AUTOMATIC
GAIN
CONTROL
AUDIO/
VOICE
FILTERS
5-BAND
5-BAND
PARAMETRIC
EQ
PARAMETRIC
EQ
MODE1
AVFLT
ADLEN
ADCL
EQ1EN
EQ2EN
MIXDAL
MIX
EXCURSION LIMITER
AVLG: 0/6/12/18dB
AVL: 3dB TO -12dB
DACL
DALEN
AUDIO/
FILTERS
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
MIXDAR
MIX
ADCR
ADREN
DV1:
0dB TO -15dB
DACR
MODE1
DVFLT
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
DAREN
Figure 14. Sidetone Block Diagram
68
Stereo Audio CODEC
with FlexSound Technology
Table 8. Sidetone Register
REGISTER
BIT
NAME
DESCRIPTION
Sidetone Source
Selects which ADC output is fed back as sidetone. When mixing the left and right ADC
outputs, each is attenuated by 6dB to prevent full-scale signals from clipping.
7
DSTS
00 = Sidetone disabled
01 = Left ADC
6
4
10 = Right ADC
11 = Left + Right ADC
Sidetone Level
Adjusts the sidetone signal level. All levels are referenced to the ADC’s full-scale output.
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
LEVEL (dB)
Sidetone disabled
-0.5
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
LEVEL (dB)
-30.5
-32.5
-34.5
-36.5
-38.5
-40.5
-42.5
-44.5
-46.5
-48.5
-50.5
-52.5
-54.5
-56.6
-58.5
-60.5
3
2
1
0
-2.5
0x2A
-4.5
-6.5
-8.5
DVST
-10.5
-12.5
-14.5
-16.5
-18.5
-20.5
-22.5
-24.5
-26.5
-28.5
2 mono slots per interface, leaving the remaining two
slots available for another device. Table 9 shows how to
configure the device for common digital audio formats.
Figures 16 and 17 show examples of common audio
formats. By default, SDOUTS1 and SDOUTS2 are set
high impedance when the IC is not outputting data to
facilitate sharing the bus. Configure the interface in TDM
mode using only slot 1 to transmit and receive mono
PCM voice data.
Digital Audio Interfaces
The IC includes two separate playback signal paths and
one record signal path. Digital audio interface 1 (DAI1)
is used to transmit the recorded stereo audio signal and
receive a stereo audio signal for playback. Digital audio
interface 2 (DAI2) is used to receive a second stereo
audio signal. Use DAI1 for all full-duplex operations and
for all voice signals. Use DAI2 for music and to mix two
playback audio signals. The digital audio interfaces are
separate from the audio ports to enable either interface
to communicate with any external device connected to
the audio ports.
The IC’s digital audio interfaces support both ADC to
DAC loop-through and digital loopback. Loop-through
allows the signal converted by the ADC to be routed
to the DAC for playback. The signal is routed from the
record path to the playback path in the digital audio
interface to allow the IC’s full complement of digital
signal processing to be used. Loopback allows digital
Each audio interface can be configured in a variety of
formats including left justified, I2S, PCM, and time divi-
sion multiplexed (TDM). TDM mode supports up to 4
mono audio slots in each frame. The IC can use up to
69
Stereo Audio CODEC
with FlexSound Technology
data input to either SDINS1 or SDINS2 to be routed
from one interface to the other for output on SDOUTS2
or SDOUTS1. Both interfaces must be configured for
the same sample rate, but the interface format need
not be the same. This allows the IC to route audio data
from one device to another, converting the data format
as needed. Figure 15 shows the available digital signal
routing options.
BCLKS1
LRCLKS1
SDOUTS1
PORT S1
SDINS1 DVDDS1 BCLKS2
LRCLKS2
SDOUTS2
PORT S1
SDINS2 DVDDS2
SEL1
DAI1
SEL2
DAI2
HIZOFF1
HIZOFF2
MAS1
MAS1
DATA
MAS2
MAS2
BIT
CLOCK
FRAME
CLOCK
DATA
INPUT
BIT
CLOCK
FRAME
CLOCK
DATA
OUTPUT
DATA
INPUT
OUTPUT
LBEN1
MUX
LBEN2
+
LTEN1
DAI1
DAI1
DAI2
RECORD PATH
PLAYBACK PATH
PLAYBACK PATH
Figure 15. Digital Audio Signal Routing
Table 9. Common Digital Audio Formats
MODE
Left Justified
I2S
WCI1/WCI2
BCI1/BCI2
DLY1/DLY2
TDM1/TDM2
SLOTL1/SLOTL2 SLOTR1/SLOTR2
Set as desired
Set as desired
0
1
X
X
0
0
1
1
X
X
0
X
X
0
1
X
X
0
1
1
PCM
TDM
Set as desired
X = Don’t care.
70
Stereo Audio CODEC
with FlexSound Technology
Table 10. Digital Audio Interface Registers
REGISTER
BIT
NAME
DESCRIPTION
DAI1/DAI2 Master Mode
In master mode, DAI1/DAI2 outputs LRCLK and BCLK. In slave mode, DAI1/DAI2
7
MAS1/MAS2
accept LRCLK and BCLK as inputs.
0 = Slave mode
1 = Master mode
DAI1/DAI2 Word Clock Invert
TDM1/TDM2 = 0:
0 = Left-channel data is transmitted while LRCLK is low.
1 = Right-channel data is transmitted while LRCLK is low.
TDM1/TDM2 = 1:
6
5
4
WCI1/WCI2
BCI1/BCI2
DLY1/DLY2
Always set WCI = 0.
DAI1/DAI2 Bit Clock Invert
BCI1/BCI2 must be set to 1 when TDM1/TDM2 = 1.
0 = SDIN is accepted on the rising edge of BCLK.
SDOUT is valid on the rising edge of BCLK.
1 = SDIN is accepted on the falling edge of BCLK.
SDOUT is valid on the falling edge of BCLK.
Master Mode:
0 = LRCLK transitions on the falling edge of BCLK.
1 = LRCLK transitions on the rising edge of BCLK.
0x14/0x1C
DAI1/DAI2 Data Delay
DLY1/DLY2 has no effect when TDM1/TDM2 = 1.
0 = The most significant data bit is clocked on the first active BCLK edge after an
LRCLK transition.
1 = The most significant data bit is clocked on the second active BCLK edge after an
LRCLK transition.
DAI1/DAI2 Time-Division Multiplex Mode (TDM Mode)
Set TDM1/TDM2 when communicating with devices that use a frame synchronization
pulse on LRCLK instead of a square wave.
0 = Disabled
1 = Enabled (BCI1/BCI2 must be set to 1)
2
1
0
TDM1/TDM2
FSW1/FSW2
WS1/WS2
DAI1/DAI2 Wide Frame Sync Pulse
Increases the width of the frame sync pulse to the full data width when TDM1/TDM2 =
1. FSW1/FSW2 has no effect when TDM1/TDM2 = 0.
0 = Disabled
1 = Enabled
DAI1/DAI2 Audio Data Bit Depth
Determines the maximum bit depth of audio being transmitted and received. Data is
always 16 bit when TDM1/TMD2 = 0.
0 = 16 bits
1 = 24 bits
71
Stereo Audio CODEC
with FlexSound Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
ADC Oversampling Ratio
Use the higher setting for maximum performance. Use the lower setting for reduced
power consumption at the expense of performance.
7
OSR1
00 = 96x
01 = 64x
10 = Reserved
11 = Reserved
6
2
DAI1/DAI2 BCLK Output Frequency
When operating in master mode, BSEL1/BSEL2 set the frequency of BCLK. When
operating in slave mode, BSEL1/BSEL2 have no effect. Select the lowest BCLK
0x15/0x1D
frequency that clocks all data input to the DAC and output by the ADC.
000 = BCLK disabled
001 = 64 x LRCLK
010 = 48 x LRCLK
011 = 128 x LRCLK (invalid for DHF1/DHF2 = 1)
100 = PCLK/2
101 = PCLK/4
BSEL1/
BSEL2
1
0
110 = PCLK/8
111 = PCLK/16
DAI1/DAI2 Audio Port Selector
Selects which port is used by DAI1/DAI2.
00 = None
01 = Port S1
10 = Port S2
7
6
SEL1/SEL2
LTEN1
11 = Reserved
DAI1 Digital Loopthrough
Connects the output of the record signal path to the input of the playback path. Data
input to DAI1 from an external device is mixed with the recorded audio signal.
0 = Disabled
1 = Enabled
5
4
0x16/0x1E
DAI1/DAI2 Digital Audio Interface Loopback
LBEN1 routes the digital audio input to DAI1 back out on DAI2. LBEN2 routes the
digital audio input to DAI2 back out on DAI1. Selecting LBEN2 disables the ADC
output data.
0 = Disabled
1 = Enabled
LBEN1/
LBEN2
DAI1/DAI2 DAC Mono Mix
Mixes the left and right digital input to mono and routes the combined signal to the left
DMONO1/
DMONO2
and right playback paths. The left and right input data is attenuated by 6dB prior to the
mono mix.
3
0 = Disabled
1 = Enabled
72
Stereo Audio CODEC
with FlexSound Technology
Table 10. Digital Audio Interface Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
Disable DA1/DAI2 Output High-Impedance Mode
Normally SDOUT is set high impedance between data words. Set HIZOFF1/HIZOFF2 to
force a level on SDOUT at all times.
0 = Disabled
HIZOFF1/
HIZOFF2
2
1 = Enabled
DAI1/DAI2 Record Path Output Enable
DAI2 outputs data only if LBEN1 = 1.
0 = Disabled
0x16/0x1E
SDOEN1/
SDOEN2
1
1 = Enabled
DAI1/DAI2 Playback Path Input Enable
0 = Disabled
1 = Enabled
SDIEN1/
SDIEN2
0
7
TDM Left Time Slot
Selects which of the four slots is used for left data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
SLOTL1/
SLOTL2
6
5
4
10 = Slot 3
11 = Slot 4
TDM Right Time Slot
Selects which of the four slots is used for right data on DAI1/DAI2. If the same slot is
selected for left and right audio, left audio is placed in the slot.
00 = Slot 1
01 = Slot 2
10 = Slot 3
0x17/0x1F
SLOTR1/
SLOTR2
11 = Slot 4
TDM Slot Delay
Adds 1 BCLK cycle delay to the data in the specified TDM slot.
1xxx = Slot 4 delayed
x1xx = Slot 3 delayed
xx1x = Slot 2 delayed
3
2
SLOTDLY1/
SLOTDLY2
1
0
xxx1 = Slot 1 delayed
73
Stereo Audio CODEC
with FlexSound Technology
WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LRCLK
SDOUT
BCLK
RIGHT
LEFT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 1, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LEFT
LRCLK
SDOUT
BCLK
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LEFT
RIGHT
LRCLK
SDOUT
BCLK
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WCI_ = 0, BCI_ = 0, DLY_ = 1, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0
LEFT
LRCLK
SDOUT
BCLK
RIGHT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 16. Non-TDM Data Format Examples
74
Stereo Audio CODEC
with FlexSound Technology
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
BCLK
HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 1, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
BCLK
HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
BCLK
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 2, SLOTR_ = 3
LRCLK
SDOUT
HI-Z
HI-Z
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
32 CYCLES
BCLK
SDIN
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1
LRCLK
SDOUT
16 CYCLES
16 CYCLES
16 CYCLES
16 CYCLES
HI-Z
HI-Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
R
1
R
1
R
1
R
R
R
R
R
R
R
R
BCLK
SDIN
HI-Z
L
L
1
R
Figure 17. TDM Mode Data Format Examples
75
Stereo Audio CODEC
with FlexSound Technology
requires the least configuration, but provides the
Clock Control
The digital signal paths in the IC require a master
clock (MCLK) between 10MHz and 60MHz to func-
tion. Internally, the MAX9888 requires a clock between
10MHz and 20MHz. A prescaler divides MCLK by 1, 2,
or 4 to create the internal clock (PCLK). PCLK is used to
clock all portions of the IC.
lowest performance. Use this mode to simplify initial
setup or when normal mode and exact integer mode
cannot be used.
U Normal Mode: This mode uses a 15-bit clock divider
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequen-
cies and can be used in either master or slave mode.
The MAX9888 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, three main clocking modes are
supported:
U Exact Integer Mode (DAI1 only): In both master and
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
U PLL Mode: When operating in slave mode, enable
the PLL to lock onto any LRCLK input. This mode
Table 11. Clock Control Registers
REGISTER
BIT
NAME
DESCRIPTION
MCLK Prescaler
5
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz PMCLK P20MHz (PCLK = MCLK)
10 = 20MHz PMCLK P40MHz (PCLK = MCLK/2)
11 = 40MHz PMCLK P60MHz (PCLK = MCLK/4)
0x10
PSCLK
4
7
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
SAMPLE RATE
(kHz)
SAMPLE RATE
(kHz)
VALUE
VALUE
6
5
4
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Reserved
8
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
48
88.2
0x11/0x19
SR1/SR2
11.025
16
96
Reserved
Reserved
Reserved
Reserved
Reserved
22.05
24
32
44.1
76
Stereo Audio CODEC
with FlexSound Technology
Table 11. Clock Control Registers (continued)
REGISTER
BIT
NAME
DESCRIPTION
Exact Integer Mode
Overrides PLL1 and NI1 and configures a specific PCLK to LRCLK ratio.
3
VALUE
SAMPLE RATE
VALUE
SAMPLE RATE
PCLK = 12MHz,
LRCLK = 8kHz
0x0
Disabled
0x8
PCLK = 12MHz,
LRCLK = 16kHz
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x9
0xA
0xB
0xC
0xD
0xE
0xF
PCLK = 13MHz,
LRCLK = 8kHz
2
0x11
FREQ1
PCLK = 13MHz,
LRCLK = 16kHz
PCLK = 16MHz,
LRCLK = 8kHz
PCLK = 16MHz,
LRCLK = 16kHz
PCLK = 19.2MHz,
LRCLK = 8kHz
1
7
PCLK = 19.2MHz,
LRCLK = 16kHz
PLL Mode Enable (Slave Mode Only)
PLL1/PLL2 enables a digital PLL that locks on to the externally supplied LRCLK
frequency and automatically sets the LRCLK divider (NI1/NI2).
PLL1/PLL2
0 = Disabled
1 = Enabled
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Normal Mode LRCLK Divider
When PLL1/PLL2 = 0, the frequency of LRCLK is determined by NI1/NI2. See Table 12
for common NI values.
0x12/0x1A
SAMPLE RATE
DHF1/DHF2
NI1/NI2 FORMULA
65536× 96× f
LRCLK
NI =
8kHz PLRCLK P48kHz
0
f
PCLK
NI1/
NI2
65536× 48× f
LRCLK
NI =
48kHz <LRCLK P96kHz
1
f
PCLK
f
f
= LRCLK frequency
= Prescaled MCLK frequency (PCLK)
LRCLK
PCLK
0x13/0x1B
Rapid Lock Mode
Program NI1/NI2 to the nearest valid ratio and set NI1[0]/NI2[0] when PLL1/PLL2 = 1
to enable rapid lock mode. Normally, the PLL automatically calculates and dynamically
adjusts NI1/NI2. When rapid lock mode is properly configured, the PLL starting point is
much closer to the correct value, thus speeding up lock time. Wait one LRCLK period
after programming NI1/NI2 before setting PLL1/PLL2 = 1.
0
NI1[0]/NI2[0]
77
Stereo Audio CODEC
with FlexSound Technology
Table 12. Common NI1/NI2 Values
LRCLK (kHz)
PCLK (MHz)
DHF1/2 = 0
22.05
3631
DHF1/2 = 1
88.2
8
11.025
1B18
18A2
1800
1694
160D
14D8
10EF
1000
0EB3
0D8C
12
16
24
32
44.1
6C61
6287
6000
5A51
5833
535F
43BD
4000
3ACD
3631
48
64
96
10
11
13A9
11E0
116A
1062
1000
0F20
0C4A
0B9C
0AAB
09D5
1D7E
1ACF
1A1F
1893
1800
16AF
126F
116A
1000
0EBF
2752
23BF
22D4
20C5
2000
1E3F
1893
1738
1555
13A9
3AFB
359F
343F
3127
3000
2D5F
24DD
22D4
2000
1D7E
4EA5
477E
45A9
4189
4000
3C7F
3127
2E71
2AAB
2752
75F7
6B3E
687D
624E
6000
5ABE
49BA
45A9
4000
3AFB
4EA5
477E
45A9
4189
4000
3C7F
3127
2E71
2AAB
2752
6C61
6287
75F7
6B3E
687D
624E
6000
5ABE
49BA
45A9
4000
3AFB
3144
11.2896
12
3000
6000
2D29
2C1A
29AF
5A51
5833
12.288
13
535F
16
21DE
2000
43BD
4000
16.9344
18.432
20
1D66
1B18
3ACD
3631
Note: Values in bold are exact integers that provide maximum full-scale performance.
Use music mode when processing high-fidelity audio
content. The music FIR filters reduce power consump-
tion and are linear phase to maintain stereo imaging.
An optional DC-blocking filter is available to eliminate
unwanted DC offset.
Passband Filtering
Each digital signal path in the IC includes options for
defining the path bandwidth (Figure 18). The playback
and record paths connected to DAI1 support both voice
and music filtering while the playback path connected to
DAI2 supports music filtering only.
In music mode, a second set of FIR filters are available
to support sample rates greater than 50kHz. The filters
can be independently selected for DAI1 and DAI2 and
support both the playback and record audio paths.
The voice IIR filters provide greater than 70dB stopband
attenuation at frequencies above f /2 to reduce aliasing.
S
Three selectable highpass filters eliminate unwanted
low-frequency signals.
DV1G:
0/6/12/18dB
DVST:
0dB TO -60dB
SIDETONE
DSTS
MIX
+
MULTIBAND ALC
NOISE GATE
DVEQ1:
DVEQ2:
AUTOMATIC
GAIN
CONTROL
0dB TO -15dB
0dB TO -15dB
AUDIO/
VOICE
FILTERS
5-BAND
5-BAND
PARAMETRIC
EQ
PARAMETRIC
EQ
MODE1
AVFLT
ADLEN
ADCL
MIXDAL
MIX
EQ1EN
EQ2EN
EXCURSION LIMITER
DACL
AVLG: 0/6/12/18dB
DALEN
AVL: 3dB TO -12dB
AUDIO/
FILTERS
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
MIXDAR
MIX
ADCR
ADREN
DV1:
0dB TO -15dB
DACR
AVRG: 0/6/12/18dB
AVR: 3dB TO -2dB
MODE1
DVFLT
DAREN
Figure 18. Digital Passband Filtering Block Diagram
78
Stereo Audio CODEC
with FlexSound Technology
Table 13. Passband Filtering Registers
REGISTER
BIT
NAME
DESCRIPTION
DAI1 Passband Filtering Mode
7
MODE1
0 = Voice filters
1 = Music filters (recommended for f > 24kHz)
S
6
5
DAI1 ADC Highpass Filter Mode
MODE1
AVFLT1
AVFLT1
DHF1
0
1
See Table 14
Select a nonzero value to enable the DC-blocking filter
4
DAI1 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz P LRCLK <96kHz
0x18
3
2
1
DAI1 DAC Highpass Filter Mode
MODE1
DVFLT1
DVFLT1
0
1
See Table 14
Select a nonzero value to enable the DC-blocking filter
0
DAI2 High Sample Rate Mode
Selects the sample rate range.
0 = 8kHz P LRCLK P 48kHz
1 = 48kHz <LRCLK P 96kHz
3
DHF2
DCB2
0x20
DAI2 DC Blocking Filter
Enables a DC-blocking filter on the DAI2 playback audio path.
0 = Disabled
1 = Enabled
0
79
Stereo Audio CODEC
with FlexSound Technology
Table 14. Voice Highpass Filters
AVFTL/DVFLT VALUE
INTENDED SAMPLE RATE
FILTER RESPONSE
000
N/A
Disabled
0
-10
-20
-30
-40
-50
-60
001/011
16kHz/8kHz
0
0
0
200
200
200
400
600
800
1000
1000
1000
FREQUENCY (Hz)
0
-10
-20
-30
-40
-50
-60
010/100
16kHz/8kHz
400
600
800
FREQUENCY (Hz)
0
-10
-20
-30
-40
-50
-60
101
8kHz to 48kHz
LRCLK = 48kHz
600 800
400
FREQUENCY (Hz)
110/111
N/A
Reserved
80
Stereo Audio CODEC
with FlexSound Technology
The ALC can optionally be configured in dual-band
mode. In this mode, the input signal is filtered into two
bands with a 5kHz center frequency. Each band is
routed through independent ALCs and then summed
together. In multiband mode, both bands use the same
parameters.
Playback Path Signal Processing
The IC playback signal path includes automatic level
control (ALC) and a 5-band parametric equalizer (EQ)
(Figure 19). The DAI1 and DAI2 playback paths include
separate ALCs controlled by a single set of registers.
Two completely separate parametric EQs are included
for the DAI1 and DAI2 playback paths.
OUTPUT SIGNAL
(dBFS)
Automatic Level Control
The automatic level control (ALC) circuit ensures maxi-
mum signal amplitude without producing audible clip-
ping. This is accomplished by a variable gain stage that
works on a sample by sample basis to increase the gain
up to 12dB. A look-ahead circuit determines if the next
sample exceeds full scale and reduces the gain so that
the sample is exactly full scale.
0
A programmable low signal threshold determines the
minimum signal amplitude that is amplified. Select a
threshold that prevents the amplification of background
noise. When the signal level drops below the low signal
threshold, the ALC reduces the gain to 0dB until the sig-
nal increases above the threshold. Figure 20 shows an
example of ALC input vs. output curves.
INPUT
SIGNAL
(dBFS)
LOW-LEVEL
THRESHOLD
-12
0
0
0
ALC WITH ALCTH ≠ 000
OUTPUT SIGNAL
(dBFS)
0
DV1G:
0/6/12/18dB
+
INPUT
SIGNAL
(dBFS)
MULTIBAND ALC
LOW-LEVEL
THRESHOLD
ALC WITH ALCTH = 000
-12
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
OUTPUT SIGNAL
(dBFS)
5-BAND
5-BAND
PARAMETRIC
EQ
PARAMETRIC
EQ
0
EQ1EN
EQ2EN
MIXDAL
MIX
EXCURSION LIMITER
DACL
DALEN
AUDIO/
FILTERS
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
MIXDAR
MIX
INPUT
SIGNAL
(dBFS)
DV1:
DACR
0dB TO -15dB
MODE1
DVFLT
LOW-LEVEL
THRESHOLD
ALC DISABLED
-12
DAREN
Figure 19. Playback Path Signal Processing Block Diagram
Figure 20. ALC Input vs. Output Examples
81
Stereo Audio CODEC
with FlexSound Technology
Table 15. Automatic Level Control Registers
REGISTER
BIT
NAME
DESCRIPTION
ALC Enable
Enables ALC on both the DAI1 and DAI2 playback paths.
0 = Disabled
1 = Enabled
7
ALCEN
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Excursion
Limiter section for Excursion Limiter release times. ALC release time is defined as the
6
time required to adjust the gain from 12dB to 0dB.
VALUE
000
ALC RELEASE TIME (s)
8
001
4
ALCRLS
5
4
010
2
1
011
100
0.5
101
0.25
0x41
110
Reserved
Reserved
111
Multiband Enable
Enables dual-band processing with a 5kHz center frequency. SR1 and SR2 must be
configured properly to achieve the correct center frequency for each playback path.
0 = Single-band ALC
3
ALCMB
ALCTH
1 = Dual-band ALC
Low Signal Threshold
Selects the minimum signal level to be boosted by the ALC.
000 = -JdB (low-signal threshold disabled)
001 = -12dB
010 = -18dB
011 = -24dB
100 = -30dB
101 = -36dB
110 = -42dB
2
1
0
111 = -48dB
Parametric Equalizer
1000
The parametric EQ contains five independent biquad
filters with programmable gain, center frequency, and
bandwidth. Each biquad filter has a gain range of Q12dB
and a center frequency range from 20Hz to 20kHz. Use a
filter Q less than that shown in Figure 21 to achieve ideal
frequency responses. Setting a higher Q results in non-
ideal frequency response. The biquad filters are series
connected, allowing a total gain of Q60dB.
f = 8kHz
s
100
10
1
f = 48kHz
s
f = 96kHz
s
0.1
100
1000
10,000
100,000
CENTER FREQUENCY (Hz)
Figure 21. Maximum Recommended Filter Q vs. Frequency
82
Stereo Audio CODEC
with FlexSound Technology
Use the attenuator at the EQ’s input to avoid clipping
The MAX9888 EV kit software includes a graphic inter-
face for generating the EQ coefficients. The coefficients
are sample rate dependent and stored in registers 0x50
through 0xB3.
the signal. The attenuator can be programmed for fixed
attenuation or dynamic attenuation based on signal level.
If the dynamic EQ clip detection is enabled, the signal
level from the EQ is fed back to the attenuator circuit to
determine the amount of gain reduction necessary to
avoid clipping.
Table 16. EQ Registers
REGISTER
BIT
NAME
DESCRIPTION
DAI1/DAI2 EQ Clip Detection
Automatically controls the EQ attenuator to prevent clipping in the EQ.
0 = Enabled
1 = Disabled
EQCLP1/
EQCLP2
4
DAI1/DAI2 EQ Attenuator
Provides attenuation to prevent clipping in the EQ when full-scale signals are boost-
ed. DVEQ1/DVEQ2 operates only when EQ1EN/EQ2EN = 1 and EQCLP1/EQCLP2
3
= 1.
VALUE
0x0
GAIN (dB)
VALUE
0x8
GAIN (dB)
0x2C/0x2E
2
1
0
0
-8
0x1
-1
-2
-3
-4
-5
-6
-7
0x9
-9
DVEQ1/DVEQ2
0x2
0xA
0xB
0xC
0xD
0xE
-10
-11
-12
-13
-14
-15
0x3
0x4
0x5
0x6
0x7
0xF
7
6
VS2EN
VSEN
See the Click-and-Pop Reduction section.
5
1
0
ZDEN
EQ2EN
EQ1EN
0x47
DAI2 EQ Enable
0 = Disabled
1 = Enabled
DAI1 EQ Enable
0 = Disabled
1 = Enabled
83
Stereo Audio CODEC
with FlexSound Technology
allows boost when MODE1 = 0 and attenuation in any
mode. The DAI2 signal path allows attenuation only.
Playback Level Control
The IC includes separate digital level control for the DAI1
and DAI2 playback audio paths. The DAI1 signal path
DV1G:
0/6/12/18dB
+
MULTIBAND ALC
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
5-BAND
5-BAND
PARAMETRIC
EQ
PARAMETRIC
EQ
MIXDAL
EQ1EN
EQ2EN
EXCURSION LIMITER
DACL
MIX
DALEN
AUDIO/
FILTERS
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
MIXDAR
MIX
DV1:
DACR
0dB TO -15dB
MODE1
DVFLT
DAREN
Figure 22. Playback Level Control Block Diagram
Table 17. DAC Playback Level Control Register
REGISTER
BIT
NAME
DESCRIPTION
DAI1/DAI2 Mute
0 = Disabled
1 = Enabled
7
DV1M/DV2M
DAI1 Voice Mode Gain
DV1G only applies when MODE1 = 0.
5
00 = 0dB
01 = 6dB
10 = 12dB
11 = 18dB
DV1G
4
3
2
DAI1/DAI2 Attenuation
0x2B/0x2D
VALUE
0x0
GAIN (dB)
VALUE
0x8
GAIN (dB)
0
-8
0x1
-1
-2
-3
-4
-5
-6
-7
0x9
-9
0x2
0xA
0xB
0xC
0xD
0xE
-10
-11
-12
-13
-14
-15
DV1/DV2
0x3
1
0
0x4
0x5
0x6
0x7
0xF
84
Stereo Audio CODEC
with FlexSound Technology
DAC Input Mixers
The IC’s stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and
right DACs (Figure 23).
DV1G:
0/6/12/18dB
+
MULTIBAND ALC
DVEQ1:
DVEQ2:
0dB TO -15dB
0dB TO -15dB
5-BAND
5-BAND
PARAMETRIC
EQ
PARAMETRIC
EQ
EQ1EN
EXCURSION LIMITER
EQ2EN
MIXDAL
MIX
DACL
DALEN
AUDIO/
FILTERS
DV2:
0dB TO -15dB
DCB2
AUDIO/
VOICE
FILTERS
MIXDAR
MIX
DV1:
DACR
0dB TO -15dB
MODE1
DVFLT
DAREN
Figure 23. DAC Input Mixer Block Diagram
Table 18. DAC Input Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
7
Left DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
6
5
4
3
2
1
0
MIXDAL
0x21
Right DAC Input Mixer
1xxx = DAI1 left channel
x1xx = DAI1 right channel
xx1x = DAI2 left channel
xxx1 = DAI2 right channel
MIXDAR
85
Stereo Audio CODEC
with FlexSound Technology
Preoutput Signal Path
The IC’s preoutput mixer stage provides mixing and level adjustment for line input signals routed to the output ampli-
fiers. Figure 24 shows a block diagram of the preoutput signal path. 9dB is added between the line input amplifiers
and the output amplifiers to boost the 1V
maximum line input signal level to the 1V
maximum DAC signal level.
P-P
RMS
RECP/
RXINP
RECVOL:
+8dB TO -62dB
0dB
MIX
RECN/
RXINN
MIXREC
RECBYP
SPKBYP
RECEN
SPKLVDD
SPKLP
BATTERY ADC
SPVOLL:
+8dB TO -62dB
MIX
+6dB
SPKLN
MIXSPL
SPLEN
SPKLGND
SPKRVDD
SPKRP
POWER/
DISTORTION LIMITER
+6dB
MIX
SPKRN
MIXSPR
SPVOLR:
+8dB TO -62dB
SPREN
HPVOLL:
+3dB TO -67dB
SPKRPGND
PGAINA:
+20dB TO -6dB
HPL
PGAOUT1:
0dB TO -23dB
INADIFF
MIX
HPLEN
PREOUT1
MIXHPL
MIX
+9dB
PGAINA:
+20dB TO -6dB
HPSNS
HPR
MIXOUT1
+
HPVOLR:
+3dB TO -67dB
PGAOUT2:
0dB TO -23dB
MIX
PREOUT2
MIX
+9dB
+9dB
HPREN
MIXHPR
PGAINB:
+20dB TO -6dB
MIXOUT2
PGAOUT3:
0dB TO -23dB
INBDIFF
PREOUT3
MIX
PGAINB:
+20dB TO -6dB
MIXOUT3
+
Figure 24. Preoutput Signal Path Block Diagram
Preoutput Mixer
The IC’s output amplifiers each accept input from one of the three preoutput mixers. Configure each pre-
output mixer to mix any combination of the four line input signals.
Table 19. Preoutput Mixer Registers
REGISTER
BIT
NAME
DESCRIPTION
3
Preoutput Mixer 1
MIXOUT1/
MIXOUT2/
MIXOUT3
1xxx = INA1
2
1
0
0x24/0x25/
0x26
x1xx = INA2 (INADIFF = 0) or INA2 - INA1 (INADIFF = 1)
xx1x = INB1
xxx1 = INB2 (INBDIFF = 0) or INB2 - INB1 (INBDIFF = 1)
86
Stereo Audio CODEC
with FlexSound Technology
Preoutput PGA
The IC’s preoutput PGAs allow line input signals to be attenuated to match DAC output signal levels. Use the 0dB
setting for maximum performance.
Table 20. Preoutput PGA Registers
REGISTER
BIT
NAME
DESCRIPTION
GAIN (dB)
Preoutput PGA Level
3
VALUE
0x0
VALUE
0x8
GAIN (dB)
-15
0
-1
2
1
0x1
0x9
-17
PGAOUT1/
PGAOUT2/
PGAOUT3
0x2
-3
0xA
0xB
0xC
0xD
0xE
-19
0x35/0x36/
0x37
0x3
-5
-21
0x4
-7
-23
0x5
-9
Mute
Mute
Mute
0
0x6
-11
-13
0x7
0xF
Receiver Amplifier
The IC includes a single differential receiver amplifier. The receiver amplifier is designed to drive 32I receivers. In
cases where a single transducer is used for the loudspeaker and receiver, use the SPKBYP switch to route the receiver
amplifier output to the left speaker outputs.
RECP/
RXINP
RECVOL:
+8dB TO -62dB
0dB
MIX
RECN/
RXINN
MIXREC
RECBYP
SPKBYP
RECEN
DACL
DALEN
DACR
DAREN
PGAOUT1:
0dB TO -23dB
PREOUT1
+9dB
+9dB
PGAOUT2:
0dB TO -23dB
PREOUT2
Figure 25. Receiver Amplifier Block Diagram
87
Stereo Audio CODEC
with FlexSound Technology
Receiver Output Mixer
The IC’s receiver amplifier accepts input from the stereo DAC and the line inputs. Configure the mixer to mix any combina-
tion of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals,
9.5dB for 3 signals, or 12dB for 4 signals.
Table 21. Receiver Output Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
3
Receiver Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Preoutput mixer 1
xxx1 = Preoutput mixer 2
2
1
0
0x28
MIXREC
Receiver Output Volume
Table 22. Receiver Output Level Register
REGISTER
BIT
NAME
DESCRIPTION
Receiver Output Mute
0 = Disabled
7
RECM
1 = Enabled
Receiver Output Volume Level
4
3
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
VOLUME (dB)
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
VOLUME (dB)
-62
-58
-54
-50
-46
-42
-38
-35
-32
-29
-26
-23
-20
-17
-14
-12
-10
-8
-6
-4
-2
0
0x3A
2
1
0
+1
+2
+3
+4
+5
+6
+6.5
+7
+7.5
+8
RECVOL
88
Stereo Audio CODEC
with FlexSound Technology
The theoretical best efficiency of a linear amplifier is
78%, however, that efficiency is only exhibited at peak
output power. Under normal operating levels (typical
music reproduction levels), efficiency falls below 30%,
whereas the IC’s Class D amplifier still exhibits 80% effi-
ciency under the same conditions.
Speaker Amplifiers
The IC integrates a stereo filterless Class D amplifier that
offers much higher efficiency than Class AB without the
typical disadvantages.
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as current
steering switches and consume negligible additional
power. Any power loss associated with the Class D out-
put stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
Traditional Class D amplifiers require the use of exter-
nal LC filters or shielding to meet EN55022B and FCC
electromagnetic-interference (EMI) regulation standards.
Maxim’s patented active emissions limiting edge-rate
control circuitry reduces EMI emissions (Figure 26).
40
30
20
10
0
40
30
20
10
0
-10
-10
30
60 80 100 120 140 160 180 200 220 240 260 280 300
FREQUENCY (MHz)
300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
FREQUENCY (MHz)
Figure 26. EMI with 15cm of Speaker Cable
SPKLVDD
BATTERY ADC
SPVOLL:
+8dB TO -62dB
SPKLP
MIX
+6dB
SPKLN
MIXSPL
SPLEN
SPKLGND
DACL
POWER/DISTORTION LIMITER
SPKRVDD
SPKRP
DALEN
MIX
+6dB
SPKRN
DACR
MIXSPR
SPVOLR:
+8dB TO -62dB
SPREN
SPKRPGND
DAREN
PGAOUT2:
0dB TO -23dB
PREOUT2
+9dB
+9dB
PGAOUT3:
0dB TO -23dB
PREOUT3
Figure 27. Speaker Amplifier Path Block Diagram
89
Stereo Audio CODEC
with FlexSound Technology
Speaker Output Mixers
The IC’s speaker amplifiers accept input from the stereo DAC and the line inputs. Configure the mixer to mix any combina-
tion of the available sources. When more than one signal is selected, the mixed signal is attenuated by 6dB for 2 signals,
9.5dB for 3 signals, or 12dB for four signals.
Table 23. Speaker Output Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
7
Left Speaker Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 3
6
5
4
3
2
1
0
MIXSPL
0x29
Right Speaker Output Mixer
1xxx = Left DAC
x1xx = Right DAC
xx1x = Reserved
xxx1 = Preoutput mixer 2
MIXSPR
Speaker Output Volume
Table 24. Speaker Output Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
Left/Right Speaker Output Mute
7
SPLM/SPRM
0 = Disabled
1 = Enabled
Left/Right Speaker Output Volume Level
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
VOLUME (dB)
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
VOLUME (dB)
4
-64
-59
-55
-50
-46
-42
-38
-35
-32
-29
-26
-23
-20
-17
-14
-12
-10
-8
-6
3
2
-4
-2
0
0x3B/0x3C
+1
+2
+3
+4
+5
+6
+6.5
+7
+7.5
+8
SPVOLL/SPVOLR
1
0
90
Stereo Audio CODEC
with FlexSound Technology
U Preset Dynamic Mode. The highpass filter automati-
cally slides between a preset upper and lower corner
frequency based on output signal level.
Speaker Amplifier Signal Processing
The IC includes signal processing to improve the sound
quality of the speaker output and protect transducers
from damage. An excursion limiter dynamically adjusts
the highpass corner frequency, while a power limiter and
distortion limiter prevent the amplifier from outputting too
much distortion or power. The excursion limiter is located
in the DSP while the distortion limiter and power limiter
control the analog volume control (Figure 28). All three
limiters analyze the speaker amplifier’s output signal to
determine when to take action.
U User Programmable Dynamic Mode. The highpass
filter slides between a user-programmed biquad filter
on the low side to a predefined corner frequency on
the high side.
The transfer function for the user-programmable biquad is:
-1
-2
b
+ b z + b z
1 2
0
H(z) =
-1
-2
1+ a z + a z
1
2
Excursion Limiter
The excursion limiter is a dynamic highpass filter that
monitors the speaker outputs and increases the high-
pass corner frequency when the speaker amplifier’s out-
put exceeds a predefined threshold. The filter smoothly
transitions between the high and low corner frequency to
prevent unwanted artifacts. The filter can operate in four
different modes:
The coefficients b , b , b , a , and a are sample rate
0
1
2
1
2
dependent and stored in registers 0xB4 through 0xC7.
Store b , b , and b as positive numbers. Store a and
0
1
2
1
a as negated two’s complement numbers. Separate fil-
2
ters can be stored for the DAI1 and DAI2 playback paths.
The MAX9888 EV kit software includes a graphic interface
for generating the user-programmable biquad coefficients.
Note: Only change the excursion limiter settings when
the signal path is disabled to prevent undesired artifacts.
U Fixed Frequency Preset Mode. The highpass corner
frequency is fixed at the upper corner frequency and
does not change with signal level.
U Fixed Frequency Programmable Mode. The high-
pass corner frequency is fixed to that specified by the
programmable biquad filter.
DV1G:
0/6/12/18dB
+
MULTIBAND ALC
SPKLVDD
BATTERY ADC
DVEQ1:
DVEQ2:
SPVOLL:
+8dB TO -62dB
0dB TO -15dB
0dB TO -15dB
SPKLP
5-BAND
5-BAND
PARAMETRIC
EQ
PARAMETRIC
EQ
MIX
+6dB
SPKLN
MIXSPL
EQ1EN
EQ2EN
SPLEN
SPKLGND
SPKRVDD
SPKRP
EXCURSION LIMITER
DACL
POWER/
DISTORTION LIMITER
MIX
DALEN
AUDIO/
FILTERS
MIXDAL
DV2:
0dB TO -15dB
DCB2
MIX
+6dB
AUDIO/
VOICE
FILTERS
SPKRN
MIXSPR
SPVOLR:
+8dB TO -62dB
DV1:
0dB TO -15dB
SPREN
SPKRPGND
MIX
DACR
MODE1
DVFLT
DAREN
MIXDAR
Figure 28. Speaker Amplifier Signal Processing Block Diagram
91
Stereo Audio CODEC
with FlexSound Technology
Table 25. Excursion Limiter Registers
REGISTER BIT
NAME
DESCRIPTION
Excursion Limiter Corner Frequency
6
The excursion limiter has limited sliding range and minimum corner frequencies. Listed below
are all the valid filter combinations.
LOWER CORNER
FREQUENCY
UPPER CORNER
FREQUENCY
MINIMUM BIQUAD
CORNER FREQUENCY
DHPUCF DHPLCF
5
4
DHPUCF
Excursion limiter disabled
—
—
000
001
010
011
100
000
001
010
011
00
00
00
00
00
11
01
10
10
400Hz
600Hz
—
800Hz
1kHz
—
—
Programmable using biquad
100Hz
—
0x3F
200Hz
400Hz
400Hz
400Hz
600Hz
800Hz
—
1
—
Programmable
using biquad
Programmable
using biquad
Programmable
using biquad
Programmable
using biquad
400Hz
600Hz
800Hz
1kHz
200Hz
300Hz
400Hz
500Hz
001
010
011
100
11
11
11
11
DHPLCF
0
6
ALC and Excursion Limiter Release Time
Sets the release time for both the ALC and Excursion Limiter. See the Automatic Level Control
section for ALC release times. Excursion limiter release time is defined as the time required to
slide from the high corner frequency to the low corner frequency.
VALUE
000
EXCURSION LIMITER RELEASE TIME (s)
4
2
001
0x41
5
ALCRLS
010
1
011
0.5
100
0.25
101
0.25
4
110
Reserved
Reserved
111
Excursion Limiter Threshold
Measured at the Class D speaker amplifier outputs. Signals above the threshold use the upper
3
2
corner frequency. Signals below the threshold use the lower corner frequency. V
must
BAT
correctly reflect the voltage of SPKLVDD to achieve accurate thresholds.
000 = 0.34V
001 = 0.71V
010 = 1.30V
011 = 1.77V
100 = 2.33V
101 = 3.25V
110 = 4.25V
111 = 4.95V
P
P
P
P
P
P
P
P
0x40
DHPTH
1
0
92
Stereo Audio CODEC
with FlexSound Technology
Power Limiter
The IC’s power limiter includes user-programmable time
constants and power thresholds to match a wide range
of loudspeakers. Program the power limiter’s threshold to
match the loudspeaker’s rated power handling. This can
be determined through measurement or the loudspeak-
er’s specification. Program time constant 1 to match the
voice coil’s thermal time constant. Program time constant
2 to match the magnet’s thermal time constant. The time
constants can be determined by plotting the voice coil’s
resistance vs. time as power is applied to the speaker.
The IC’s power limiter tracks the RMS power delivered to
the loudspeaker and briefly mutes the speaker amplifier
output if the speaker is at risk of sustaining permanent
damage.
Loudspeakers are typically damaged when the voice coil
overheats due to extended operation above the rated
power. During normal operation, heat generated in the
voice coil is transferred to the speaker’s magnet, which
transfers heat to the surrounding air. For the voice coil to
overheat, both the voice coil and the magnet must over-
heat. The result is that a loudspeaker can operate above
its rated power for a significant time before it heats suf-
ficiently to cause damage.
Table 26. Power Limiter Registers
REGISTER
BIT
NAME
DESCRIPTION
Power Limiter Threshold
If the RMS output power from the speaker amplifiers exceeds this threshold, the out-
put is briefly muted to protect the speaker. The threshold is measured in watts assum-
ing an 8I load. VBAT must correctly reflect the voltage of SPKLVDD/SPKRVDD to
achieve accurate thresholds.
7
THRESHOLD
(W)
THRESHOLD
(W)
VALUE
VALUE
6
5
Power limiter
disabled
0x0
0x8
0.27
PWRTH
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0.05
0.06
0.09
0.11
0.13
0.18
0.22
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0.35
0.48
0.72
1.00
1.43
1.57
1.80
0x42
4
2
Power Limiter Weighting Factor
Determines the balance between time constant 1 and 2 to match the dominance of
each time constant in the loudspeaker.
VALUE
000
T1 (%)
T2 (%)
50
50
1
001
62.5
37.5
25
PWRK
010
75
011
87.5
12.5
0
100
100
101
12.5
25
87.5
75
0
110
111
37.5
62.5
REGISTER
BIT
NAME
DESCRIPTION
93
Stereo Audio CODEC
with FlexSound Technology
Table 26. Power Limiter Registers (continued)
Power Limiter Time Constant 2
Select a value that matches the thermal time constant of the loudspeaker’s magnet.
7
TIME CONSTANT
TIME CONSTANT
(min)
VALUE
VALUE
(min)
Disabled
0.50
6
5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
3.75
5.00
PWRT2
0.67
6.66
0.89
8.88
1.19
Reserved
Reserved
Reserved
Reserved
1.58
4
3
2.11
2.81
0x43
Power Limiter Time Constant 1
Select a value that matches the thermal time constant of the loudspeaker’s voice coil.
TIME CONSTANT
(s)
TIME CONSTANT
(s)
VALUE
VALUE
2
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Disabled
0.50
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
3.75
5.00
PWRT1
0.67
6.66
1
0
0.89
8.88
1.19
Reserved
Reserved
Reserved
Reserved
1.58
2.11
2.81
Distortion Limiter
The IC’s distortion limiter ensures that the speaker amplifier’s output does not exceed the programmed THD+N limit.
The distortion limiter analyzes the Class D output duty cycle to determine the percentage of the waveform that is
clipped. If the distortion exceeds the programmed threshold, the output gain is reduced.
94
Stereo Audio CODEC
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Table 27. Distortion Limiter Registers
REGISTER
BIT
NAME
DESCRIPTION
Distortion Limit
Measured in % THD+N.
7
VALUE
THD+N LIMIT (%)
VALUE
THD+N LIMIT (%)
6
5
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Limiter disabled
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
12
14
16
18
20
21
22
24
< 1
1
THDCLP
2
4
6
4
8
0x44
10
Distortion Limiter Release Time Constant
Duration of time required for the speaker amplifier’s output gain to adjust back to the
nominal level after a large signal has passed.
000 = 6.2s
001 = 3.1s
2
1
0
THDT1
010 = 1.6s
011 = 815ms
100 = 419ms
101 = 223ms
110 = 116ms
111 = 76ms
improving the frequency response of the headphone
amplifier. There is a low DC voltage on the amplifier out-
puts due to amplifier offset. However, the offset of the IC
is typically Q0.2mV, which, when combined with a 32I
load, results in less than 6FA of DC current flow to the
headphones.
Headphone Amplifier
The IC’s headphone amplifier integrates Maxim’s
DirectDrive architecture to eliminate the need for large
DC-blocking capacitors. Traditional single-supply head-
phone amplifiers have outputs biased at a nominal
DC voltage (typically half the supply). Large coupling
capacitors are needed to block this DC bias from the
headphone. Without these capacitors, a significant
amount of DC current flows to the headphone, resulting
in unnecessary power dissipation and possible damage
to both the headphone and headphone amplifier.
In addition to the cost and size disadvantages of
the DC-blocking capacitors required by conventional
headphone amplifiers, these capacitors limit the ampli-
fier’s low-frequency response and can distort the audio
signal. The DC-blocking capacitor not only blocks DC,
but also low-frequency audio. Improving the low-fre-
quency response of a conventional headphone amplifier
requires increasing the capacitor size, further adding
to the cost and size of the solution. Due to the voltage
coefficient of the capacitors used for DC blocking, they
introduce significant distortion near the corner frequency
of the highpass filter they create. This distortion further
degrades the low-frequency audio quality.
The DirectDrive architecture uses a charge pump to
create an internal negative supply voltage. This allows
the IC’s headphone outputs to be biased at GND while
operating from a single supply (Figure 29). Without a DC
component, there is no need for the large DC-blocking
capacitors. Instead of two large (220FF, typ) capaci-
tors, the IC charge pump requires two small ceramic
capacitors, conserving board space, reducing cost, and
95
Stereo Audio CODEC
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Alternative approaches to eliminating the output-cou-
pling capacitors involve biasing the headphone return
(sleeve) to the DC bias voltage of the headphone ampli-
fiers. This method raises some issues:
The switch drivers feature a controlled switching speed
that minimizes noise generated by turn-on and turn-off
transients. By limiting the switching speed of the charge
pump, the di/dt noise caused by the parasitic trace
inductance is minimized. The charge pump is active only
in headphone modes.
U The sleeve is typically grounded to the chassis. Using
the midrail biasing approach, the sleeve must be
isolated from system ground, complicating product
design.
To reduce audible noise at the outputs, the IC’s head-
phone amplifier includes headphone ground sensing.
Connect the sense line (HPSNS) to the ground terminal
of the device’s headphone jack. Any noise present at
the headphone ground is then added to the headphone
output. The result is elimination of this noise from the
audible output. If ground sensing is not required, con-
nect HPSNS directly to ground. Figure 30 shows a block
diagram of the headphone output section including the
headphone sense function.
U During an ESD strike, the amplifier’s ESD structures
are the only path to system ground. Thus, the ampli-
fier must be able to withstand the full energy from an
ESD strike.
U When using the headphone jack as a line out to other
equipment, the bias voltage on the sleeve may con-
flict with the ground potential from other equipment,
resulting in possible damage to the amplifiers.
Headphone Output Mixers
The IC’s headphone amplifier accepts input from the
stereo DAC and the line inputs. The output of the left and
right DAC cannot be mixed at the headphone mixer. Use
MIXDAL/MIXDAR to mix the left and right audio channels
before conversion.
The IC features a low-noise charge pump to generate
a negative supply for the headphone amplifier. The
nominal switching frequency is well beyond the audio
range, and thus does not interfere with audio signals.
V
DD
V
/2
DD
DACL
DALEN
GND
CONVENTIONAL AMPLIFIER BIASING SCHEME
+V
DD
DACR
HPVOLL:
+3dB TO -67dB
DAREN
PGAOUT1:
0dB TO -23dB
HPL
MIX
PREOUT1
HPLEN
HPSNS
+9dB
MIXHPL
GND
HPVOLR:
+3dB TO -67dB
MIX
HPR
PREOUT2
+9dB
MIXHPR
-V
DD
)
HPREN
PGAOUT2:
0dB TO -23dB
(V
SS
DirectDrive AMPLIFIER BIASING SCHEME
Figure 30. Headphone Amplifier Block Diagram
Figure 29. Traditional Amplifier Output vs. DirectDrive Output
96
Stereo Audio CODEC
with FlexSound Technology
Table 28. Headphone Output Mixer Register
REGISTER
BIT
NAME
DESCRIPTION
Left Headphone Output Mixer
10xx = Left DAC
7
6
5
4
3
2
1
0
01xx = Right DAC (requires DALEN = 0 for proper operation)
11xx = Left DAC
xx1x = Reserved
MIXHPL
xxx1 = Preoutput mixer 1
0x27
Right Headphone Output Mixer
10xx = Left DAC (requires DAREN = 0 for proper operation)
01xx = Right DAC
11xx = Right DAC
xx1x = Reserved
MIXHPR
xxx1 = Preoutput mixer 2
Headphone Output Volume
Table 29. Headphone Output Level Register
REGISTER
BIT
NAME
DESCRIPTION
Headphone Output Mute
0 = Disabled
7
HPLM/HPRM
1 = Enabled
Left/Right Headphone Output Volume Level
VALUE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
VOLUME (dB)
VALUE
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
VOLUME (dB)
4
3
-67
-63
-59
-55
-51
-47
-43
-40
-37
-34
-31
-28
-25
-22
-19
-17
-15
-13
-11
-9
-7
-5
0x38/0x39
-4
HPVOLL/HPVOLR
-3
2
1
0
-2
-1
0
+1
+1.5
+2
+2.5
+3
97
Stereo Audio CODEC
with FlexSound Technology
an external receiver amplifier is used, route its output to
Output Bypass Switches
The IC includes two output bypass switches that solve
common applications problems. When a single trans-
ducer is used for the loudspeaker and receiver, the need
exists for two amplifiers to power the same transducer.
Bypass switches connect the IC’s receiver amplifier
output to the speaker amplifier’s output, allowing either
amplifier to power the same transducer. In systems where
the left speaker through RECP/RXINP and RECN/RXINN,
bypassing the Class D amplifier. In systems where an
external amplifier drives both the receiver and the IC’s
line input, one of the differential signals can be discon-
nected from the receiver when not needed by passing it
through the analog switch that connects RECP/RXINP to
RECN/RXINN.
EXTERNAL
RECEIVER AMP
10I*
RECP/RXINP
RECP/RXINP
RECN/RXINN
RECN/RXINN
EXTERNAL
RECEIVER
AMP
0dB
0dB
10I*
0dB
RECN/RXINN
RECN/RXINN
RECEN
RECEN
RECBYP
SPKBYP
RECBYP
SPKBYP
RECEN
RECBYP
SPKBYP
SPKLVDD
SPKLP
SPKLVDD
SPKLP
SPKLVDD
SPKLP
+6dB
SPKLN
+6dB
SPKLN
+6dB
SPKLGND
SPKLN
SPLEN
SPKLGND
SPLEN
POWER/DISTORTION
LIMITER
SPKLGND
SPLEN
POWER/DISTORTION
LIMITER
POWER/DISTORTION
LIMITER
*OPTIONAL 10I RESISTORS IMPROVE DISTORTION
THROUGH THE ANALOG SWITCH.
SPEAKER AMPLIFIER BYPASS USING AN
EXTERNAL RECEIVER AMPLIFIER
SPEAKER AMPLIFIER BYPASS USING THE
INTERNAL RECEIVER AMPLIFIER
CONTROLLING AN EXTERNAL RECEIVE
AMPLIFIER AND SPEAKER
Figure 31. Output Bypass Switch Block Diagrams
Table 30. Output Bypass Switches Register
REGISTER
BIT
7
NAME
INABYP
MIC2BYP
DESCRIPTION
See the Microphone Inputs section.
4
RXINP to RXINN Bypass Switch
Shorts RXINP to RXINN allowing a signal to pass through the MAX9888. Disable the
1
0
RECBYP
SPKBYP
receiver amplifier when RECBYP = 1.
0 = Disabled
1 = Enabled
0x48
RXIN to SPKL Bypass Switch
Shorts RXINP/RXINN to SPKLP/SPKLN allowing either the internal or an external
receiver amplifier to power the left speaker. Disable the left speaker amplifier when
SPKBYP = 1.
0 = Disabled
1 = Enabled
98
Stereo Audio CODEC
with FlexSound Technology
enabled, volume slewing also occurs at device turn-on
and turn-off. During turn-on the volume is set to mute
before the output is enabled. Once the output is on, the
volume ramps to the desired level. At turn-off the volume
is ramped to mute before the outputs are disabled.
Click-and-Pop Reduction
The IC includes extensive click-and-pop reduction cir-
cuitry. The circuitry minimizes clicks and pops at turn-on,
turn-off, and during volume changes.
Zero-crossing detection is implemented on all analog
PGAs and volume controls to prevent large glitches
when volume changes are made. Instead of making a
volume change immediately, the change is made when
the audio signal crosses the midpoint. If no zero-crossing
occurs within the timeout window, the change is forced.
When there is no audio signal zero-crossing detection
can prevent volume slewing from occurring. Enable
enhanced volume slewing to prevent the volume control-
ler from requesting another volume level until the previ-
ous one has been set. Each step in the volume ramp
then occurs after a zero crossing has occurred in the
audio signal or the timeout window has expired. During
turn-off, enhance volume slewing is always disabled.
Volume slewing breaks up large volume changes into the
smallest available step size and the steps through each
step between the initial and final volume setting. When
Table 31. Click-and-Pop Reduction Register
REGISTER
BIT
NAME
DESCRIPTION
Enhanced Volume Smoothing
During volume slewing, the controller waits for each step in the ramp to be applied
before sending the next step. When zero-crossing detection is enabled this prevents
large steps in the output volume when no zero crossings are detected.
0 = Enabled
7
VS2EN
1 = Disabled
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
Volume Adjustment Smoothing
Volume changes are smoothed by stepping through intermediate steps. Also ramps
the volume from minimum to the programmed value at turn-on and back to minimum at
6
5
VSEN
ZDEN
turn-off.
0 = Enabled
1 = Disabled
0x49
Applies to volume changes in HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
Zero-Crossing Detection
Holds volume changes until there is a zero crossing in the audio signal. This reduces
click and pop during volume changes (zipper noise). If no zero crossing is detected
within 100ms, the volume change is forced.
0 = Enabled
1 = Disabled
Applies to volume changes in PGAM1, PGAM2, PGAOUTA, PGAOUTB, PGAOUTC,
HPVOLL, HPVOLR, RECVOL, SPVOLL, and SPVOLR.
1
0
EQ2EN
EQ1EN
See the 5-Band Parametric EQ section.
99
Stereo Audio CODEC
with FlexSound Technology
load is applied to JACKSNS. Table 32 shows the change
in JKSNS that occurs when a jack is inserted.
Jack Detection
The IC features jack detection that can detect the inser-
tion and removal of a jack as well as the load type. When
a jack is detected, an interrupt on IRQ can be triggered
to alert the microcontroller of the event. Figure 32 shows
the typical configuration for jack detection.
Accessory Button Detection
After jack insertion, the MAX9888 can detect button
presses on accessories that include a microphone and
a switch that shorts the microphone signal to ground.
Set JDETEN to enable jack detection circuitry. A pullup
current is automatically applied to JACKSNS if MICBIAS
is disabled. Clear JDWK to allow differentiation between
the microphone load and a short to ground. Button
presses can be detected both when MICBIAS is enabled
and disabled. Table 33 shows the change in JKSNS that
occurs when the accessory button is pressed.
Jack Insertion
To detect a jack insertion, the IC must have a power
supply and MICBIAS should be disabled. Set JDETEN
to enable jack detection circuitry and apply a pullup cur-
rent to JACKSNS. Set JDWK to minimize supply current.
Clear JDWK to differentiate between headsets with a
microphone and headphones without a microphone. The
voltage on JACKSNS is equal to SPKLVDD as long as no
HPL
MICBIAS
JACKSNS
HPR
MIC1P
Figure 32. Typical Configuration for Jack Detection
Table 32. Change in JKSNS Upon Jack Insertion
JACK TYPE
JDWK = 1
JDWK = 0
GND
GND
R
L
JKSNS: 11 è 00
JKSNS: 11 è 00
MIC
GND
R
L
JKSNS: 11 è 00
JKSNS: 11 è 01
Table 33. Change in JKSNS Upon Button Press
JACK TYPE
MICBIAS ENABLED OR DISABLED
MIC
GND
R
L
JKSNS: 01 è 00
100
Stereo Audio CODEC
with FlexSound Technology
Jack Removal
applied to JACKSNS if MICBIAS is disabled. Set JDWK
to minimize supply current if button detection is not
required. Table 34 shows the change in JKSNS that
occurs when a jack is removed.
The IC detects jack removal by monitoring JACKSNS
for transitions to the 11 state. Set JDETEN to enable
jack detection circuitry. A pullup current is automatically
Table 34. Change in JKSNS Upon Jack Removal
JACK TYPE
JDWK = 1 AND MICBIAS DISABLED
JDWK = 0 OR MICBIAS ENABLED
GND
GND
R
L
JKSNS: 00 è 11
JKSNS: 00 è 11
JKSNS: 00 è 11
MIC
GND
R
L
JKSNS: 01 è 11
Table 35. Jack Detection Registers
REGISTER
BIT
NAME
DESCRIPTION
JACKSNS State
Reports the status of JACKSNS when JDETEN = 1.
VALUE
MODE
DESCRIPTION
7
MBEN = 1
MBEN = 0
MBEN = 1
MBEN = 0
MBEN = 1
MBEN = 0
MBEN = 1
MBEN = 0
V
V
< 0.1 x V
JACKSNS
JACKSNS
MICBIAS
SPKLVDD
< 0.95 x V
JACKSNS MICBIAS
00
< 0.1 x V
0x02
(Read Only)
JKSNS
0.1 x V
0.1 x V
< V
MICBIAS
01
10
11
< V
< 0.95 x V
SPKLVDD
SPKLVDD
JACKSNS
Reserved
Reserved
6
0.95 x V
0.95 x V
< V
JACKSNS
MICBIAS
< V
SPKLVDD
JACKSNS
Jack Detection Enable
0 = Disabled
1 = Enabled
7
1
0
JDETEN
JDEB
Jack Detection Debounce
Configures the debounce time for setting JDET.
00 = 25ms
01 = 50ms
10 = 100ms
11 = 200ms
0x49
7
6
See the Power Management section.
See the Battery Measurement section.
JACKSNS Pullup
SHDN
VBATEN
When JDWK = 1 JACKSNS is slow to increase in voltage. Set JDWK = 0 before setting
JDETEN = 1 to prevent false detection.
Valid when MBIAS = 0 or SHDN = 0.
0x4C
1
JDWK
0 = 2.4kIto SPKLVDD (allows microphone detection)
1 = 5FA to SPKLVDD (minimizes supply current)
101
Stereo Audio CODEC
with FlexSound Technology
circuitry to set accurate thresholds. When the battery
measurement function is disabled, the battery voltage is
user programmable.
Battery Measurement
The IC measures the voltage applied to SPKLVDD (typi-
cally the battery voltage) and reports the value in regis-
ter 0x03. This value is also used by the speaker limiter
Table 36. Battery Measurement Registers
REGISTER
BIT
4
NAME
DESCRIPTION
Battery Voltage
Read VBAT when V
3
= 1 to determine V
. Program VBAT when V
BATEN
SPKLVDD BATEN
0x03
2
VBAT
= 0 to allow proper speaker amplifier signal processing. Calculate the battery voltage
using the following formula:
1
V
= 2.55V + [VBAT/10]
BATTERY
0
7
SHDN
VBATEN
JDWK
See the Power Management section.
Battery Measurement Enable
Enables an internal ADC to measure V
0 = Disabled (register 0x03 readable and writeable)
1 = Enabled (register 0x03 read only)
.
SPKLVDD
0x4C
6
1
See the Headset Detection section.
102
Stereo Audio CODEC
with FlexSound Technology
either by poling register 0x00 or configuring the IRQ to
pull low when specific events occur. IRQ is an open-
drain output that requires a pullup resistor for proper
operation. Register 0x0F determines which bits in the
status register trigger IRQ to pull low.
Device Status
The IC uses register 0x00 and IRQ to report the status of
various device functions. The status register bits are set
when their respective events occur, and cleared upon
reading the register. Device status can be determined
Table 37. Status and Interrupt Registers
REGISTER
BIT
NAME
DESCRIPTION
Full Scale
0 = All digital signals are less than full scale.
1 = The DAC or ADC signal path has reached or exceeded full scale. This typically
indicates clipping.
7
CLD
Volume Slew Complete
SLD reports that any of the programmable-gain arrays or volume controllers has
completed slewing from a previous setting to a new programmed setting. If multiple
gain arrays or volume controllers are changed at the same time, the SLD flag is set
after the last volume slew completes. SLD also reports when the digital audio interface
soft-start or soft-stop process has completed. MCLK is required for proper SLD
operation.
6
SLD
0 = No volume slewing sequences have completed since the status register was last
read.
1 = Volume slewing complete.
0x00
(Read Only)
Digital Audio Interface Unlocked
5
1
ULK
0 = Both digital audio interfaces are operating normally.
1 = Either digital audio interface is configured incorrectly or receiving invalid data.
Jack Configuration Change
JDET reports changes to any bit in the Jack Status register (0x02). Changes to the Jack
Status bits are debounced before setting JDET. The debounce period is programmable
using the JDEB bits. JDET is always set the first time JDETEN or SHDN is set the first
time power is applied to the IC. Read the status register following such an event to clear
JDET and allow for proper jack detection.
JDET
0 = No change in jack configuration.
1 = Jack configuration has changed.
Full-Scale Interrupt Enable
0 = Disabled
1 = Enabled
7
6
5
1
ICLD
ISLD
IULK
IJDET
Volume Slew Complete Interrupt Enable
0 = Disabled
1 = Enabled
0x0F
Digital Audio Interface Unlocked Interrupt Enable
0 = Disabled
1 = Enabled
Jack Configuration Change Interrupt Enable
0 = Disabled
1 = Enabled
103
Stereo Audio CODEC
with FlexSound Technology
Device Revision
Table 38. Device Revision Register
REGISTER
BIT
NAME
DESCRIPTION
7
6
5
4
0xFF
(Read Only)
Device Revision Code
REV is always set to 0x43.
REV
3
2
1
0
I2C Serial Interface
resistors protect the digital inputs of the IC from high
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
The IC features an I2C/SMBusK-compatible, 2-wire
serial interface comprising a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate com-
munication between the IC and the master at clock rates
up to 400kHz. Figure 5 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I,
is required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if
the single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 33). A
START condition from the master signals the beginning
of a transmission to the IC. The master terminates trans-
mission, and frees the bus, by issuing a STOP condition.
The bus remains active if a REPEATED START condition
is generated instead of a STOP condition.
Early STOP Conditions
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the
same SCL high pulse as the START condition.
S
Sr
P
SCL
SDA
Figure 33. START, STOP, and REPEATED START Conditions
SMBus is a trademark of Intel Corp.
104
Stereo Audio CODEC
with FlexSound Technology
Slave Address
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when
the IC is in read mode. An acknowledge is sent by the
master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the IC, followed by a
STOP condition.
The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 0010000. Setting
the read/write bit to 1 (slave address = 0x21) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x20) configures the IC for write mode. The
address is the first byte of information sent to the IC after
the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 34). The IC pulls down SDA dur-
ing the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
Write Data Format
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte
of data to configure the internal register address pointer,
one or more bytes of data, and a STOP condition. Figure
35 illustrates the proper frame format for writing one byte
of data to the IC. Figure 35 illustrates the frame format for
writing n-bytes of data to the IC.
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 34. Acknowledge
ACKNOWLEDGE FROM MAX9888
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9888
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9888
A
A
DATA BYTE
1 BYTE
A
P
S
SLAVE ADDRESS
O
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 35. Writing One Byte of Data to the IC
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
B5 B4 B3 B2 B1 B0
B6 B5 B4 B3 B2 B1 B0
B7
B6
B7
ACKNOWLEDGE FROM MAX9888
SLAVE ADDRESS
R/W
ACKNOWLEDGE FROM MAX9888
REGISTER ADDRESS
A
O
S
A
A
P
A
DATA BYTE n
1 BYTE
DATA BYTE 1
1 BYTE
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 36. Writing n-Bytes of Data to the IC
105
Stereo Audio CODEC
with FlexSound Technology
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated 9th SCL pulse.
The first byte transmitted from the IC is the content of
register 0x00. Transmitted data is valid on the rising
edge of SCL. The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continu-
ous frame. A STOP condition can be issued after any
number of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte to
be read is from register 0x00.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer
tells the IC where to write the next byte of data. An
acknowledge pulse is sent by the IC upon receipt of the
address pointer data.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the IC’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/W bit set to 1. The
IC then transmits the contents of the specified register.
The address pointer autoincrements after transmitting
the first byte.
The third byte sent to the IC contains the data that is
written to the chosen register. An acknowledge pulse
from the IC signals receipt of the data byte. The address
pointer autoincrements to the next register address after
each received data byte. This autoincrement feature
allows a master to write to sequential registers within
one continuous frame. The master signals the end of
transmission by issuing a STOP condition. Register
addresses greater than 0xC7 are reserved. Do not write
to these addresses.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowl-
edge from the master and then a STOP condition. Figure
37 illustrates the frame format for reading one byte from
the IC. Figure 38 illustrates the frame format for reading
multiple bytes from the IC.
Read Data Format
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The IC acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read com-
mand resets the address pointer to register 0x00.
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
REGISTER ADDRESS
ACKNOWLEDGE FROM MAX9888
NOT ACKNOWLEDGE FROM MASTER
S
SLAVE ADDRESS
R/W
O
A
A
Sr
SLAVE ADDRESS
1
A
DATA BYTE
1 BYTE
A
P
REPEATED START
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 37. Reading One Byte of Data from the IC
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
S
O
A
A
SLAVE ADDRESS
R/W
REGISTER ADDRESS
SLAVE ADDRESS
DATA BYTE
1 BYTE
Sr
1
A
A
REPEATED START
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 38. Reading n Bytes of Data from the IC
106
Stereo Audio CODEC
with FlexSound Technology
required for the IC to operate. Additional components
Applications Information
may be required by the application.
Typical Operating Circuits
Figures 39 and 40 provide example operating circuits for
the IC. The external components shown are the minimum
Analog Microphones and Bypass Switch
2.8V TO 5.5V
1.8V
10FF
1.8V TO 3.6V
1.8V TO 3.6V
1FF
1FF
1FF
1FF
1FF
1FF
1FF
1.8V TO
5.5V
DVDD
HPVDD
AVDD
SPKLVDD SPKRVDD DVDDS2
DVDDS1
10kI
BCLKS2
TO MICROCONTROLLER
IRQ
DIGITAL
AUDIO
PORT 2
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
SDA
LRCLKS2
SDINS2
10MHz TO 60MHz CLOCK INPUT
SDOUTS2
DIGITAL AUDIO
PORT 1
JACKSNS
JACKSNS
BYPASS
SWITCH
INPUT
RECP/RXINP
RECN/RXINN
2
I C CONTROL
PORT
SCL
SPKLP
SPKLN
8I
8I
MICROPHONE
OUTPUT TO
BASEBAND
MIC1P/DIGMICDATA
MIC1N/DIGMICCLK
MAX9888
SPKRP
SPKRN
MICBIAS
MIC2P
JACKSNS
1kI
2.2kI
1FF
1FF
1FF
1FF
1FF
HPR
HPL
HEADSET
MICROPHONE
MIC2N
HPSNS
REF
INA1/EXTMICP
INA2/EXTMICN
INB1
HANDSET
MICROPHONE
PREG
REG
1kI
1FF
1FF
LINE INPUT
INB2
1FF
1FF
2.2FF
DGND
AGND
HPGND SPKRGND SPKLGND HPVSS
C1N
C1P
1FF
1FF
Figure 39. Typical Application Circuit Using Analog Microphone Inputs and the Bypass Switch
107
Stereo Audio CODEC
with FlexSound Technology
Digital Microphones and Receiver Amplifier
2.8V TO 5.5V
1.8V
10FF
1.8V TO 3.6V
1.8V TO 3.6V
1FF
1FF
1FF
1FF
1FF
1FF
1FF
1.8V TO
5.5V
DVDD
HPVDD
AVDD
SPKLVDD SPKRVDD DVDDS2
DVDDS1
10kI
BCLKS2
TO MICROCONTROLLER
IRQ
10MHz TO 60MHz
CLOCK INPUT
MCLK
BCLKS1
LRCLKS1
SDINS1
SDOUTS1
SDA
LRCLKS2
SDINS2
DIGITAL
AUDIO
PORT 2
SDOUTS2
JACKSNS
DIGITAL AUDIO
PORT 1
JACKSNS
RECP/RXINP
RECN/RXINN
32I
2
I C CONTROL
PORT
SCL
DATA
SPKLP
SPKLN
DIGITAL
MIC 1
8I
8I
MIC1P/DIGMICDATA
MIC1N/DIGMICCLK
CLOCK
DATA
MAX9888
SPKRP
SPKRN
DIGITAL
MIC 2
CLOCK
MICBIAS
MIC2P
2.2kI
JACKSNS
1FF
1FF
1FF
1FF
1FF
HPR
HPL
HEADSET
MICROPHONE
MIC2N
HPSNS
REF
INA1/EXTMICP
INA2/EXTMICN
INB1
LINE INPUT
LINE INPUT
PREG
REG
1FF
1FF
1FF
1FF
2.2FF
INB2
DGND
AGND
HPGND SPKRGND SPKLGND HPVSS
C1N
C1P
1FF
1FF
Figure 40. Typical Application Circuit Using the Digital Microphone Input and Receiver Amplifier
108
Stereo Audio CODEC
with FlexSound Technology
In RF applications, improvements to both layout and com-
ponent selection decrease the IC’s susceptibility to RF
noise and prevent RF signals from being demodulated into
audible noise. Trace lengths should be kept below 1/4 of
the wavelength of the RF frequency of interest. Minimizing
the trace lengths prevents them from functioning as anten-
nas and coupling RF signals into the IC. The wavelength
(l) in meters is given by: l = c/f where c = 3 x 108 m/s, and
f = the RF frequency of interest.
Filterless Class D Operation
Traditional Class D amplifiers require an output filter
to recover the audio signal from the amplifier’s output.
The filters add cost, increase the solution size of the
amplifier, and can decrease efficiency and THD+N
performance. The traditional PWM scheme uses large
differential output swings (2 x V
peak to peak) and
DD
causes large ripple currents. Any parasitic resistance in
the filter components results in a loss of power, lowering
the efficiency.
Route audio signals on middle layers of the PCB to allow
ground planes above and below to shield them from RF
interference. Ideally, the top and bottom layers of the
PCB should primarily be ground planes to create effec-
tive shielding.
The IC does not require an output filter. The device relies
on the inherent inductance of the speaker coil and the
natural filtering of both the speaker and the human ear
to recover the audio component of the square-wave out-
put. Eliminating the output filter results in a smaller, less
costly, more efficient solution.
Additional RF immunity can also be obtained by rely-
ing on the self-resonant frequency of capacitors as it
exhibits a frequency response similar to a notch filter.
Depending on the manufacturer, 10pF to 20pF capaci-
tors typically exhibit self resonance at the RF frequencies
of interest. These capacitors, when placed at the input
pins, can effectively shunt the RF noise to ground. For
these capacitors to be effective, they must have a low-
impedance, low-inductance path to the ground plane.
Avoid using microvias to connect to the ground plane
whenever possible as these vias do not conduct well at
RF frequencies.
Because the frequency of the IC output is well beyond
the bandwidth of most speakers, voice coil move-
ment due to the square-wave frequency is very small.
Although this movement is small, a speaker not designed
to handle the additional power can be damaged. For
optimum results, use a speaker with a series inductance
> 10FH. Typical 8I speakers exhibit series inductances
in the 20FH to 100FH range.
RF Susceptibility
GSM radios transmit using time-division multiple access
(TDMA) with 217Hz intervals. The result is an RF signal
with strong amplitude modulation at 217Hz and its har-
monics that is easily demodulated by audio amplifiers.
The IC is designed specifically to reject RF signals; how-
ever, PCB layout has a large impact on the susceptibility
of the end product.
Startup/Shutdown Sequencing
To ensure proper device initialization and minimal click-
and-pop, program the IC’s SHDN = 1 after configuring all
registers. Table 39 lists an example startup sequence for
the device. To shut down the IC, simply set SHDN = 0.
Table 39. Example Startup Sequence
SEQUENCE
DESCRIPTION
REGISTERS
0x4C
1
2
Ensure SHDN = 0
Configure clocks
0x10 to 0x13, 0x19 to 0x1B
0x14 to 0x17, 0x1C to 0x1F
0x18, 0x20, 0x3D to 0x44
0x50 to 0xC7
3
Configure digital audio interface
Configure digital signal processing
Load coefficients
4
5
6
Configure mixers
0x21 to 0x29
7
Configure gain and volume controls
Configure miscellaneous functions
Enable desired functions
Set SHDN = 1
0x2A to 0x3C
8
0x45 to 0x49
9
0x4A, 0x4B
10
0x4C
109
Stereo Audio CODEC
with FlexSound Technology
While many configuration options in the IC can be made
while the device is operating, some registers should
only be adjusted when the corresponding audio path is
disabled. Table 40 lists the registers that are sensitive
during operation. Either disable the corresponding audio
path or set SHDN = 0 while changing these registers.
signal. The AC coupling capacitor allows the amplifier
to automatically bias the signal to an optimum DC level.
Assuming zero-source impedance, the -3dB point of the
highpass filter is given by:
1
f
=
-3dB
2πR C
IN IN
Component Selection
Choose C so that f
is well below the lowest fre-
IN
-3dB
Optional Ferrite Bead Filter
In applications where speaker leads exceed 20mm,
additional EMI suppression can be achieved by using a
filter constructed from a ferrite bead and a capacitor to
ground (Figure 41). Use a ferrite bead with low DC resis-
tance, high-frequency (> 600MHz) impedance between
100Iand 600I, and rated for at least 1A. The capacitor
value varies based on the ferrite bead chosen and the
actual speaker lead length. Select a capacitor less than
1nF based on EMI performance.
quency of interest. For best audio quality use capacitors
whose dielectrics have low-voltage coefficients, such as
tantalum or aluminum electrolytic. Capacitors with high-
voltage coefficients, such as ceramics, may result in
increased distortion at low frequencies.
Charge-Pump Capacitor Selection
Use capacitors with an ESR less than 100mIfor optimum
performance. Low-ESR ceramic capacitors minimize the
output resistance of the charge pump. Most surface-
mount ceramic capacitors satisfy the ESR requirement.
For best performance over the extended temperature
range, select capacitors with an X7R dielectric.
Input Capacitor
An input capacitor, C , in conjunction with the input
IN
impedance of the IC line inputs forms a highpass filter
that removes the DC bias from an incoming analog
Table 40. Registers That Are Sensitive to Changes During Operation
REGISTER
0x10 to 0x13, 0x19 to 0x1B
0x14 to 0x17, 0x1C to 0x1F
0x18, 0x20
DESCRIPTION
Clock Control Registers
Digital Audio Interface Configuration
Digital Passband Filters
0x24 to 0x29
Analog Mixers
0x50 to 0xC7
Digital Signal Processing Coefficients
SPK_P
SPK_N
MAX9888
Figure 41. Optional Class D Ferrite Bead Filter
110
Stereo Audio CODEC
with FlexSound Technology
Charge-Pump Flying Capacitor
Charge-Pump Holding Capacitor
The holding capacitor (bypassing HPVSS) value and
ESR directly affect the ripple at HPVSS. Increasing
the capacitor’s value reduces output ripple. Likewise,
decreasing the ESR reduces both ripple and output
resistance. Lower capacitance values can be used in
systems with low maximum output power levels. See the
Output Power vs. Load Resistance graph in the Typical
Operating Characteristics section for more information
The value of the flying capacitor (connected between
C1N and C1P) affects the output resistance of the
charge pump. A value that is too small degrades the
device’s ability to provide sufficient current drive, which
leads to a loss of output voltage. Increasing the value
of the flying capacitor reduces the charge-pump output
resistance to an extent. Above 1FF, the on-resistance
of the internal switches and the ESR of external charge-
pump capacitors dominate.
Unused Pins
Table 41 shows how to connect the IC’s pins when
unused.
Table 41. Unused Pins
NAME
CONNECTION
Unconnected
Always connected
Always connect
Unconnected
Unconnected
Always connect
Unconnected
AGND
NAME
INB1
CONNECTION
Unconnected
Unconnected
Unconnected
Always connect
AGND
SPKRP
SPKRVDD
SPKLVDD
SPKLP
INA2/MICEXTN
LRCLKS2
MCLK
RECN/RXINN
HPVDD
C1P
SDINS2
Unconnected
Unconnected
Unconnected
Always connect
Unconnected
Always connect
Always connect
Always connect
Always connect
Unconnected
Unconnected
Unconnected
DVDD
IRQ
MIC1P/DIGMICDATA
INA1/MICEXTP
DGND
HPGND
SPKRN
Unconnected
Always connect
Always connect
Unconnected
Unconnected
Unconnected
Unconnected
Unconnected
AGND
SPKRGND
SPKLGND
SPKLN
BCLKS2
SDA
SCL
RECP/RXINP
C1N
REG
REF
HPL
MIC1N/DIGMICCLK
MIC2P
HPVSS
SDINS1
LRCLKS1
HPSNS
SDOUTS2
DVDDS2
DVDD
Unconnected
AGND
Always connect
Always connect
Always connect
Always connect
Unconnected
Unconnected
INB2
Unconnected
Unconnected
DVDD
AVDD
HPR
PREG
DVDDS1
SDOUTS1
BCLKS1
JACKSNS
AGND
Unconnected
Unconnected
Unconnected
MICBIAS
MIC2N
111
Stereo Audio CODEC
with FlexSound Technology
Recommended PCB Routing
The IC uses a 63-bump WLP package. Figure 42
provides an example of how to connect to all active
bumps using 3 layers of the PCB. To ensure uninter-
rupted ground returns, use layer 2 as a connecting layer
between layer 1 and layer 2 and flood the remaining area
with ground.
Supply Bypassing, Layout, and Grounding
Proper layout and grounding are essential for optimum
performance. When designing a PCB for the IC, parti-
tion the circuitry so that the analog sections of the IC are
separated from the digital sections. This ensures that the
analog audio traces are not routed near digital traces.
Use a large continuous ground plane on a dedicated
layer of the PCB to minimize loop areas. Connect AGND,
DGND, HPGND, SPKLGND, and SPKRGND directly to
the ground plane using the shortest trace length pos-
sible. Proper grounding improves audio performance,
minimizes crosstalk between channels, and prevents
any digital noise from coupling into the analog audio
signals.
Ground the bypass capacitors on MICBIAS, REG, PREG,
and REF directly to the ground plane with minimum
trace length. Also be sure to minimize the path length to
AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground plane
with minimum path length to DGND. Bypass DVDD,
DVDDS1, and DVDDS2 directly to DGND.
LAYER 1
Place the capacitor between C1P and C1N as close as
possible to the IC to minimize trace length from C1P to
C1N. Inductance and resistance added between C1P
and C1N reduce the output power of the headphone
amplifier. Bypass HPVSS with a capacitor located close
to HPVSS with a short trace length to HPGND. Close
decoupling of HPVSS minimizes supply ripple and maxi-
mizes output power from the headphone amplifier.
HPSNS senses ground noise on the headphone jack and
adds the same noise to the output audio signal, thereby
making the output (headphone output minus ground)
noise free. Connect HPSNS to the headphone jack shield
to ensure accurate pickup of headphone ground noise.
LAYER 2
Bypass SPKLVDD and SPKRVDD to SPKLGND and
SPKRGND, respectively, with as little trace length as
possible. Connect SPKLP, SPKLN, SPKRP, and SPKRN
to the stereo speakers using the shortest traces pos-
sible. Reducing trace length minimizes radiated EMI.
Route SPKLP/SPKLN and SPKRP/SPKRN as differential
pairs on the PCB to minimize loop area, thereby the
inductance of the circuit. If filter components are used
on the speaker outputs, be sure to locate them as close
as possible to the IC to ensure maximum effectiveness.
Minimize the trace length from any ground-connected
passive components to SPKLGND and SPKRGND to
further minimize radiated EMI.
LAYER 3
Figure 42. Suggested Routing
112
Stereo Audio CODEC
with FlexSound Technology
Route microphone signals from the microphone to the IC
as a differential pair, ensuring that the positive and nega-
tive signals follow the same path as closely as possible
with equal trace length. When using single-ended micro-
phones or other single-ended audio sources, ground the
negative microphone input as close as possible to the
audio source and then treat the positive and negative
traces as differential pairs.
0.24mm
An evaluation kit (EV kit) is available to provide an exam-
ple layout for the IC. The EV kit allows quick setup of the
IC and includes easy-to-use software allowing all internal
registers to be controlled.
WLP Applications Information
For the latest application details on WLP construction,
dimensions, tape carrier information, PCB techniques,
bump-pad layout, and recommended reflow tempera-
ture profile, as well as the latest information on reliability
testing results, refer to the Application Note 1891: Wafer-
Level Packaging (WLP) and Its Applications. Figure 43
shows the dimensions of the WLP balls used on the IC.
0.21mm
Figure 43. WLP Ball Dimensions
113
Stereo Audio CODEC
with FlexSound Technology
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0462
LAND PATTERN NO.
Refer to
Application Note 1891
63 WLP
W633A3+1
114
Stereo Audio CODEC
with FlexSound Technology
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
1
6/10
Initial release
Updated DAC playback 48kHz stereo, speaker outputs, speaker maximum value
—
2/11
6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
115
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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