MAX9895AEWX+ [MAXIM]
Active Noise-Cancelling Solution for Stereo Headsets;
| 型号： | MAX9895AEWX+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Active Noise-Cancelling Solution for Stereo Headsets |
| 文件： | 总22页 (文件大小：1209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4478; Rev 0; 10/09
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
General Description
Features
o 2.7V to 4.5V Operation
o Low Headphone Amplifier Noise
The MAX9895A is a complete audio subsystem for
active noise-cancelling (ANC) stereo headsets. The
device features three stages for each right and left
channel. A microphone preamplifier, an analog sound
processing block, and a headphone amplifier combine
to create a simple and very flexible active noise-cancel-
ing system.
o Low-Noise Microphone Preamplifiers with 2.2V
Bias
o Stereo 33mW into 16Ω Capacitorless Headphone
Amplifiers
o Microphone Output Path Available for Speech
The MAX9895A features a feed-forward architecture,
where outside microphones sense the ambient noise
and on-board analog sound processing generates the
compensation signal needed for noise reduction. This
further supports the mechanical isolation of the headset
by attenuating sound that leaks through the mechanics
of the headphone.
Transmission
o Adjustable Microphone Gain by I2C Interface or
External Resistors
o Low External Component Count
Ordering Information
The microphone preamplifiers feature programmable
gain, allowing alignment of the microphone and driver
tolerances and left-right channel matching. The head-
phone amplifiers are output capacitorless and can
deliver 33mW into a 16Ω transducer.
The MAX9895A has three modes of operation: ANC on,
PTL, and ANC off. The ANC-on mode demonstrates the
noise-canceling performance of the device. PTL (push-
to-listen) mode sends the microphone signals directly
to the headphones to temporarily listen to the surround-
ings. ANC off disables noise-canceling, but allows use
of the headphone amplifiers during music playback.
PIN-
GAIN
(V/V)
PART
TEMP RANGE
PACKAGE
MAX9895AEWX+ -40°C to +85°C
MAX9895AETL+ -40°C to +85°C
36 WLP
1
1
40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Simplified Block Diagram
The MAX9895A is available in a space-saving WLP or
TQFN package and is specified over the -40°C to
+85°C extended temperature range.
MAX9895A
HEADPHONE
LEFT
ANALOG
SIGNAL PROCESSING
Applications
Noise-Cancelling Headphones/Headsets
Headsets for Mobile Communication
Mobile Phones
MICROPHONE
INPUT LEFT
MIC
PREAMP
HEADPHONE
AMP
LINE
IN LEFT
HEADPHONE
RIGHT
Portable Gaming Devices
ANALOG
SIGNAL PROCESSING
E-Books
MICROPHONE
INPUT RIGHT
MIC
PREAMP
HEADPHONE
AMP
LINE
IN RIGHT
Pin Configurations appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Active Noise-Cancelling Solution
for Stereo Headsets
ABSOLUTE MAXIMUM RATINGS
DD
PVDD to PGND.........................................................-0.3V to +6V
V
to GND..............................................................-0.3V to +6V
Continuous Current into HPOUT_ .....................................200mA
Continuous Input Current (all other pins) ......................... 20mA
PVDD to V .........................................................-0.1V to +0.1V
Continuous Power Dissipation (T = +70°C)
36-Bump, 0.4mm-Pitch WLP Single-Layer Board
DD
A
CPVDD to PVDD...............................................Internally shorted
PGND to GND .......................................................-0.1V to +0.1V
SDA, SCL..................................................................-0.3V to +6V
LINEIN_ ....................................................................-0.3V to +6V
(derate 17mW/°C above +70°C)..............................1360mW
Maximum Current per Bump (10k hrs at +120°C)................1.7A
TQFN Package (derate 22mW/°C above +70°C) ......1777mW
ESD Protection, Human Body Model................................... 2kV
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Any Other Pin .............................................-0.3V to (V
Duration of Short Circuit Between HPOUT_
+ 0.3V)
DD
and GND ................................................................Continuous
Duration of Short Circuit Between MICBIAS
MX895A
and V , GND .......................................................Continuous
DD
Duration of Short Circuit Between V
MID
and V , GND .......................................................Continuous
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= V
= V
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
DD
PVDD
CPVDD
L
VDD
DD
BIAS BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and PGND, R
= 10kΩ,
PREIN_
FLY
HOLD
MID
R
= 50kΩ, R
GAIN
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, V
= +1V/V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note1)
MAX
A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
GENERAL
V
DD
Supply Voltage Range
PVDD
Inferred by PSRR test
2.7
3.3
4.5
CPVDD
ANC = on
3.4
2.5
3.4
4.6
3.4
4.6
12
Quiescent Supply Current
I
mA
ANC = off, PTL = off
DD
PTL = on
2
Shutdown Supply Current
Internal Reference
I
I C mode, T = +25°C
µA
V
SHDN
A
V
Voltage on V
1.25
1.3
37
1.35
BIAS
BIAS
Input from LINEIN_
Input from MICIN_
Falling threshold
Startup Time
t
ms
V
ON
390
Undervoltage Lockout
HEADPHONE OUTPUTS
Line Input Resistance
Output Offset Voltage
UVLO
2.27
7
2.65
R
MAX9895A
10
14
3
kΩ
IN
V
T
A
= +25°C
0.3
mV
OS
R = 32Ω, P
f = 1kHz from LINEIN_
= 10mW,
OUT
L
0.002
0.002
Total Harmonic Distortion plus
Noise
THD+N
PSRR
%
R = 16Ω, P = 10mW,
L
OUT
f = 1kHz from LINEIN_
V
= 2.5V to 4.5V, T = +25°C
60
70
65
55
DD
A
Power-Supply Rejection Ratio
(Note 2)
dB
f ≤ 1kHz, V = 200mV
IN
P-P
f = 10kHz, V = 200mV
IN
P-P
2
_______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
DD
PVDD
CPVDD
L
VDD
DD
BIAS BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and PGND, R
= 10kΩ,
PREIN_
FLY
HOLD
MID
R
= 50kΩ, R
GAIN
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, V
= +1V/V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note1)
MAX
A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
38
26
9
MAX
UNITS
R = 16Ω, THD+N = 1%, T = +25°C
L
A
20
(Note 3)
Output Power
P
mW
OUT
R = 32Ω, THD+N = 1%, T = +25°C
L
A
ANC = off, PTL = off
BW = 20Hz to 20kHz
Output Noise Voltage
V
µV
RMS
ON
ANC = off, PTL = off
A-weighted
6
ANC = on, A-weighted
6.5
0.2
Slew Rate
SR
V/µs
No sustained oscillations
(capacitance between HPOUT_ and V
Maximum Capacitive Load
C
100
pF
dBV
dB
MAXLOAD
)
MID
R = 32Ω, peak voltage,
A-weighted, 32 samples/sec,
Turn on
Turn off
-73
-72
L
Click-and-Pop Level
KCP
T
A
= +25°C (Note 4)
f = 1kHz, R = 32Ω, P
= 10mW, TQFN
57
70
L
OUT
Crosstalk
WLP
MICROPHONE INPUTS
Preamplifier Feedback
Resistance
R
External
External
10
1
100
kΩ
PREFB
Preamplifier Input Resistance
Input Bias Current
R
10
10
kΩ
PREIN
I
Measured at MICIN, T = +25°C
A
1
6
nA
BIAS
BW = 20Hz to 20kHz
measured at MICOUT_
Microphone Input Noise Voltage
e
µV
N
Minimum ANC Gain
Maximum ANC Gain
Minimum PTL Gain
Maximum PTL Gain
ANC/PTL Gain Stepsize
ANCG_MIN
ANCG_MAX
PTLG_MIN
PTLG_MAX
-18.0
-6.0
-12.0
0
-17.5
-5.5
-11.5
0.5
-17.0
-5.0
-11.0
1
dB
dB
dB
dB
dB
MICOUT_ to HPOUT_, measured at DC
AG_STEP MICOUT_ to HPOUT_, measured at DC
Measured at SPR1 and SPR2 with respect
to V
0.5
OPA Offset
-30
+30
mV
BIAS
Allowed capacitance to GND on MICOUT_
and all signal processing filter I/O except
SPC3
Maximum Capacitive Load
C
15
1
pF
MAXLOAD
Swing of all internal and external nodes of
preamplifier, signal processing, and filter
Dynamic Range
MICDYN
V
with respect to V
BIAS
_______________________________________________________________________________________
3
Active Noise-Cancelling Solution
for Stereo Headsets
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
DD
PVDD
CPVDD
L
VDD
DD
BIAS BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and PGND, R
= 10kΩ,
PREIN_
FLY
HOLD
MID
R
= 50kΩ, R
GAIN
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, V
= +1V/V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note1)
MAX
A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Current capability of preamplifier, signal
processing, and filter output
Maximum Output Current
PTL Attenuation
I
500
µA
OUT
Attenuation from LINEIN_ to HPOUT_ in
PTL mode
MX895A
40
dB
MICROPHONE BIAS (MICBIAS Pin)
MIC Bias Voltage
V
V
= 3.3V; 100µA < I
< 1mA
MICBIAS
2.1
55
2.2
35
100
62
60
6
2.3
V
MICBIAS
DD
MIC Bias Current Limit
I
mA
pF
MICLM
Maximum Capacitive Load
C
MAXLOAD
V
from 2.7V to 4.5V
DD
MICBIAS PSRR
MB_PSRR
dB
µV
f = 20kHz
MICBIAS Noise
MB_N
CHARGE PUMP
Charge-Pump Frequency
f
225
250
4
275
kHz
OSC
V
Output Resistance
R
Ω
MID
VMID
2
DIGITAL INPUT SDA (SCL Tied to GND: I C Interface Disabled)
V
= 0V to 3.3V
= +25°C
SDA
Input Leakage
I
16
µA
L
T
A
Input Voltage High
Input Voltage Low
V
1.8
1.4
V
V
IH
V
0.8
IL
2
SCL/SDA (I C Interface Enabled)
Input Voltage High
V
1.8V CMOS compatibility
1.8V CMOS compatibility
V
V
IH
Input Voltage Low
V
0.4
IL
Input Hysteresis
V
0.2
10
V
IHIST
Input High Leakage Current
Input Low Leakage Current
Input Capacitance
I
V
V
= 3V; T = +25°C
1
1
µA
µA
pF
V
IH
IN
IN
A
I
= 0; T = +25°C
A
IL
C
IN
Output Voltage Low
V
I
= 3mA; T = +25°C
0.4
OL
OL
A
2
I C INTERFACE
Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
0.6
BUF
Hold Time (REPEATED) START
Condition
t
µs
µs
HD:STA
Setup Time for a REPEATED
START Condition
t
SU:STA
4
_______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
DD
PVDD
CPVDD
L
VDD
DD
BIAS BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and PGND, R
= 10kΩ,
PREIN_
FLY
HOLD
MID
R
= 50kΩ, R
GAIN
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, V
= +1V/V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note1)
MAX
A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.3
0.6
100
0
TYP
MAX
UNITS
µs
SCL Pulse-Width Low
SCL Pulse-Width High
Data Setup Time
t
LOW
t
µs
HIGH
t
ns
SU:DAT
HD:DAT
Data Hold Time
t
900
300
ns
SDA and SCL Receiving Rise
Time
20 +
t
R
(Note 5)
(Note 5)
(Note 5)
ns
ns
ns
0.1C
B
SDA and SCL Receiving Fall
Time
20 +
0.1C
t
F
t
F
300
250
B
20 +
SDA Transmitting Fall Time
0.1C
B
Setup Time for STOP Condition
Bus Capacitance
t
0.6
µs
pF
ns
SU,STO
C
400
50
B
Pulse Width of Suppressed Spike
t
0
SP
Note 1: All devices are 100% production tested at T = +25°C. Specifications over temperature limits are guaranteed by design.
A
Note 2: PSRR at any frequency is limited by resistor matching (common-mode sense architecture used to reject the modulation on
VMID).
Note 3: Output power is guaranteed by measuring the RDSON of all power MOSFETs (headphone driver and charge pump).
Note 4: Line inputs AC-coupled to GND.
Note 5: C is in pF.
B
_______________________________________________________________________________________
5
Active Noise-Cancelling Solution
for Stereo Headsets
Typical Operating Characteristics
(V
= V
= V
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
BIAS
DD
PVDD
CPVDD
L
VDD
DD
BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and GND, R
= 10kΩ,
FLY
HOLD
MID
PREIN_
R
= 10kΩ, R
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, both outputs driven in phase, GAIN = +1V/V (MAX9895AA)).
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
5
4
3
2
1
0
5
4
3
2
1
0
20
15
10
5
2
I C SHUTDOWN
MX895A
ANC_ON
ANC_ON
ANC_OFF
ANC_OFF
0
2.7
3.3
3.9
4.5
-40
-15
10
35
60
85
2.7
3.3
3.9
4.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SHUTDOWN CURRENT
vs. TEMPERATURE
SOFTWARE TURN-ON
HARDWARE TURN-ON
MAX9895A toc06
MAX9895A toc05
7.00
6.95
6.90
6.85
6.80
6.75
I2C SHUTDOWN
SDA
2V/div
V
CC
SCL
2V/div
2V/div
HPOUT
500mV/div
500mV/div
6.70
6.65
6.60
200ms/div
-40
-15
10
35
60
85
200ms/div
TEMPERATURE (°C)
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. OUTPUT POWER
100
100
10
R = 16
BOTH CHANNELS
DRIVEN IN PHASE
I
R = 32
BOTH CHANNELS
DRIVEN IN PHASE
I
L
L
10
1
1
0.1
0.1
6kHz
6kHz
1kHz
1kHz
0.01
0.001
0.01
0.001
100Hz
100Hz
0
10
20
30
40
50
60
0
5
10 15 20 25 30 35 40
OUTPUT POWER (mW)
OUTPUT POWER (mW)
6
_______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Typical Operating Characteristics (continued)
(V
= V
= V
FLY
= 10kΩ, R
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
BIAS
DD
PVDD
CPVDD
L
VDD
DD
BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and GND, R
= 10kΩ,
HOLD
MID
PREIN_
R
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, both outputs driven in phase, GAIN = +1V/V (MAX9895AA)).
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
1
0.1
1
R = 16I
R = 32I
L
L
BOTH CHANNELS
DRIVEN IN PHASE
BOTH CHANNELS
DRIVEN IN PHASE
0.1
0.01
0.01
0.001
15mW
30mW
5mW
15mW
0.001
10
100
1000
FREQUENCY (Hz)
10,000
100,000
10
100
1000
10,000
100,000
FREQUENCY (Hz)
POWER-SUPPLY REJECTION RATIO
POWER-SUPPLY REJECTION RATIO
0
-10
-20
-30
-40
-50
-60
0
-10
-20
-30
-40
-50
-60
-70
V
= 3.3V 100mV
P-P
V
= -3.3V 100mV
P-P
CC
CC
ANC_OFF
ANC_ON
PTL
-70
-80
-80
-90
10
100
1k
10k
100k
10
100
100k
1k
FREQUENCY (Hz)
10k
FREQUENCY (Hz)
CROSSTALK vs. FREQUENCY
OUTPUT SPECTRUM vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
0
-20
-40
-60
-80
V
= -60dBV
OUT
R = 32I,
L
P
= 10mW
OUT
-100
-120
-140
10
100
1000
FREQUENCY (Hz)
10,000
100,000
0
2k 4k
20k
6k 8k 10k 12k 14k 16k 18k
FREQUENCY (Hz)
_______________________________________________________________________________________
7
Active Noise-Cancelling Solution
for Stereo Headsets
Typical Operating Characteristics (continued)
(V
= V
= V
FLY
= 10kΩ, R
= 3.3V, R = ∞, C
= 10µF connected between V
and PGND, C
= 1µF connected between V
BIAS
DD
PVDD
CPVDD
L
VDD
DD
BIAS
and GND, C
= 1µF connected between C1P and C1N. C
= 1µF connected between V
and GND, R
= 10kΩ,
HOLD
MID
PREIN_
R
= 3.3kΩ, MIC signal gain in ANC mode ANC_GAIN = -11.5dB, MIC signal gain in PTL mode PTL_GAIN =
PREFB_
MICBIAS
-5.5dB, both outputs driven in phase, GAIN = +1V/V (MAX9895A)).
POWER DISSIPATION
vs. OUTPUT POWER
OUTPUT POWER
vs. LOAD RESISTANCE
80
100
90
80
70
60
50
40
30
20
10
0
70
R = 16
I
L
MX895A
60
50
40
30
20
10
0
10% THD + N
1% THD + N
R = 32
I
L
BOTH CHANNELS
DRIVEN IN PHASE,
SIGNAL APPLIED ON
LINEIN
BOTH CHANNELS
DRIVEN IN PHASE
0
10 20 30 40 50 60 70 80 90 100
OUTPUT POWER (mW)
0
10 20 30 40 50 60 70 80 90 100
LOAD RESISTANCE (Ω)
OUTPUT POWER
vs. SUPPLY VOLTAGE
TOTAL OUTPUT POWER vs.
SUPPLY VOLTAGE
160
140
120
100
80
80
70
60
50
40
30
20
10
0
10% THD + N
1% THD + N
10% THD + N
1% THD + N
60
40
R = 16I,
BOTH CHANNELS
DRIVEN IN PHASE
R = 32I,
BOTH CHANNELS
DRIVEN IN PHASE
L
L
20
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
SUPPLY VOLTAGE (V)
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5
SUPPLY VOLTAGE (V)
MICBIAS POWER-SUPPLY
REJECTION RATIO
MICIN INPUT HEADROOM
vs. SUPPLY VOLTAGE
0
-10
-20
-30
-40
-50
-60
-70
-80
600
500
400
300
200
100
0
V
= 3.3V ±100mV
P-P
CC
PTL MODE
ALL BYPASS CAPS
REMOVED
1%THD, 5V/V EXTERNAL GAIN
10
100
1000
10,000
100,000
2.7
3.3
3.9
4.5
FREQUENCY (Hz)
SUPPLY VOLTAGE (V)
8
_______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Pin Description
PIN
NAME
SPR1_L
FUNCTION
TQFN
WLP
1
A6
Left-Channel Signal Processing
Left-Channel Microphone Preamplifier Output. Apply feedback resistor to set input
gain. See the Microphone Output section for more details.
2
C5
MICOUT_L
3
4
B6
C6
C4
D4
D6
E6
MICIN_L
MICBIAS
LINEIN_L
LINEIN_R
GND
Left-Channel Microphone Input
Microphone Supply Voltage. Use separate left/right MICBIAS resistors.
Left-Channel Audio Line Input
5
6
Right-Channel Audio Line Input
Signal Ground (Reference for V
, MICBIAS, and LINEIN)
BIAS
7, 8
9
MICIN_R
Right-Channel Microphone Input
Right-Channel Microphone Preamplifier Output. Apply feedback resistor to set input
gain.
10
D5
MICOUT_R
11
12
13
14
15
16
F6
E5
F5
E4
F4
E3
SPR1_R
SPC1_R
SPC2_R
SPC3_R
SPC4_R
SPR2_R
Right-Channel Signal Processing
Right-Channel Signal Processing
Right-Channel Signal Processing
Right-Channel Signal Processing
Right-Channel Signal Processing
Right-Channel Signal Processing
Internal Reference. Bypass V
LINEIN.
to GND with a 1µF capacitor. Used for MICIN and
BIAS
17
F3
V
BIAS
18
19
20
21
22
23
24
25
26
E2
F2
D2
F1
SPFC2_R
SPFC1_R
SPFO_R
Right-Channel Signal Processing
Right-Channel Signal Processing
Right-Channel Signal Processing
Right-Channel Headphone Output
HPOUT_R
V
DD
E1
Positive Supply Voltage
PVDD
CPVDD
C1P
D1
C1
Charge-Pump Flying Capacitor Positive
Charge-Pump Flying Capacitor Negative
C1N
Charge-Pump Output Voltage. Connect to common return of headphone. Bypass
27
B1
V
MID
V
with a 1µF capacitor to PGND.
MID
28
29
—
N.C.
No Connection
Power Ground
A1
PGND
2
I C Interface Data Line. Also used as MODE select in hardware mode (SCL = GND).
30
D3
SDA/NC-MODE
See Table 1.
2
31
32
C3
A2
SCL
I C Interface Clock Line. Connect to GND for hardware mode.
HPOUT_L
Left-Channel Headphone Output
_______________________________________________________________________________________
9
Active Noise-Cancelling Solution
for Stereo Headsets
Pin Description
PIN
NAME
FUNCTION
TQFN
33
WLP
C2
B2
A3
B3
A4
B4
A5
B5
—
SPFO_L
SPFC1_L
SPFC2_L
SPR2_L
SPC4_L
SPC3_L
SPC2_L
SPC1_L
EP
Left-Channel Signal Processing
Left-Channel Signal Processing
Left-Channel Signal Processing
Left-Channel Signal Processing
Left-Channel Signal Processing
Left-Channel Signal Processing
Left-Channel Signal Processing
Left-Channel Signal Processing
Exposed Pad. Must be connected to PGND.
34
35
36
37
MX895A
38
39
40
—
The PTL mode connects the microphone preamplifier
directly to the headphone amplifier, bypassing the
noise cancellation, and attenuates the line-input signal.
PTL mode gives the user the option of listening to the
surroundings without removing the headphones. See
Table 1 for hardware mode settings.
Detailed Description
The MAX9895A is a complete audio subsystem for
active noise-cancelling stereo headsets. The device
features a microphone preamplifier, an analog sound
processing block, and a headphone amplifier combin-
ing to create a simple and very flexible active noise-
canceling system. The MAX9895A uses feed-forward
architecture, creating a headphone signal that has the
same amplitude, but opposite phase as outside noise
that leaks through the mechanical isolation of the ear-
phones. These two signals cancel each other and pro-
vide noise suppression at the ear. The device consists
of an ultra-low noise microphone preamplifier to set
input impedance and gain, followed by an analog sig-
nal processing block, and a capacitorless headphone
amplifier. The headphone amplifier does not require the
large output-coupling capacitors used by conventional
single-supply headphone amplifiers, and can output
33mW into a 16Ω headphone. The product also fea-
tures undervoltage lockout and comprehensive click-
and-pop suppression circuitry. See the Functional
Diagram/Typical Applications Circuit for further details.
Microphone Preamplifier
The MAX9895A features an ultra-low noise microphone
input preamplifier. Using an inverting op amp design with
external input and feedback resistors allows flexibility in
setting input impedance and gain. The microphone gain
can be adjusted in two ways: adjust the feedback resis-
tor in the preamplifier stage by use of a potentiometer or
setting I2C registers using a microcontroller to adjust the
gain after the analog processing stage.
Microphone Bias Supply
The MAX9895A provides a low-noise voltage bias
designed for biasing electret condenser microphones
(ECM). The bias output is regulated to 2.5V.
Table 1. Mode Selection (in Hardware
Mode)
Modes of Operation
The MAX9895A features three modes of operation;
active noise canceling (ANC) on or off, and push-to-lis-
ten (PTL). The ANC-on mode provides full noise cancel-
ing and provides line-input mixing to the headphones.
This allows music to be played while noise canceling is
operational. The ANC-off mode disables the micro-
phone preamplifiers and noise processing blocks, but
allows the line inputs to operate normally. This gives
flexibility to the design such that music can still be
played through the headphones while noise canceling
is inactive.
SDA LEVEL
CONFIGURATION
(PTL Mode) LINEIN_ is attenuated,
MICOUT_ signal is passed directly to the
headphone driver without filtering and phase
reversal.
GND
Hi-Z
ANC on
V
ANC off (only HP amps are active)
DD
10 ______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Microphone Output
The outputs of the microphone preamplifiers are provid-
ed to allow for external adjustment of the gain of the
preamplifier and to provide a path for voice transmis-
sion (headset) applications.
Unlike conventional single-supply, single-ended ampli-
fiers, the MAX9895A headphone amplifier does not
need large DC-blocking caps, as the outputs are
referred to V /2, which is the bias output voltage of
CC
the amplifier. Conventional single-supply headphone
amplifiers require large coupling capacitors to block
the output DC bias from the headphone. The
MAX9895A architecture uses a high-efficiency charge
pump to create an internal midbias supply voltage
Programmable Gain
The second gain stage can be programmed in 0.5dB
steps to compensate for microphone and headphone
sensitivity. This requires a microcontroller connected to
the I2C bus, which operates in slave mode. An alternate
solution for gain setting is to add a trim-pot to the feed-
back resistor of the microphone preamplifier. See the
Typical Application Circuit.
(V
). This keeps supply current low and allows the
MID
amplifier outputs to be connected directly to the head-
phones without the need for these large coupling
capacitors.
Serial Interface
Analog Signal Processing
This block creates the noise cancellation signal. The
signal processing block uses the output of the micro-
phone preamp and external components to create a
headphone signal that has the same amplitude, but
opposite phase as outside noise that leaks through the
mechanical isolation of the earphones, so both waves
cancel each other. Note: The choice of external com-
ponents depends on the headset characteristics.
Please contact your local Maxim sales office for more
information on determining the proper component val-
ues for the Analog Signal Processing section.
The MAX9895A features an I2C, 2-wire serial interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate communication
between the MAX9895A and the master at clock rates
up to 400kHz. Figure 1 shows the 2-wire interface tim-
ing diagram. The MAX9895A is a receive-only slave
device relying on the master to generate the SCL sig-
nal. The MAX9895A cannot write to the SDA bus except
to acknowledge the receipt of data from the master.
The master, typically a microcontroller, generates SCL
and initiates data transfer on the bus. If the serial inter-
face is not used, the SCL pin must be tied to GND to
disable this feature and allow the device to be used in
hardware mode (no microcontroller).
Headphone Amplifier
The stereo headphone amplifier is capable of delivering
33mW into 16Ω loads and has a gain (line in to head-
phone out) of 1V/V for the MAX9895AA. The input to the
headphone amplifier is a linear sum of three signals:
line in (external input), mic gain (output of analog signal
processing block) and PTL gain (ANC bypass).
A master device communicates to the MAX9895A by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or REPEATED START (Sr) condition and a STOP (P) con-
SDA
t
BUF
t
t
SU, STA
SU, DAT
t
t
SP
HD, STA
t
SU, STO
t
t
HD, DAT
LOW
SCL
t
HIGH
t
HD, STA
t
R
t
F
START
CONDITION
REPEATED
START
STOP
CONDITION
START
CONDITION
CONDITION
Figure 1. 2-Wire Serial-Interface Timing Diagram
______________________________________________________________________________________ 11
Active Noise-Cancelling Solution
for Stereo Headsets
S
Sr
P
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
SDA
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
MX895A
Figure 2. START, STOP, and REPEATED START Conditions
Figure 3. Acknowledge
dition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
Slave Address
The MAX9895A is available with 0x40 preset slave
addresses. The address is defined as the seven most
significant bits (MSBs) followed by the read/write (R/W)
bit. The address is the first byte of information sent to
the MAX9895A after the START condition. The
MAX9895A is a slave device only capable of being writ-
ten to. The sent R/W bit must always be a zero when
configuring the MAX9895A.
The MAX9895A SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9895A SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple mas-
ters on the bus, or if the master in a single-master sys-
tem has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. Series resistors
protect the digital inputs of the MAX9895A from high-
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
The MAX9895A acknowledges the receipt of its
address even if R/W is set to 1. However, the
MAX9895A does not drive SDA. Addressing the
MAX9895A with R/W set to 1 causes the master to
receive all 1s regardless of the contents of the com-
mand register.
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9895A uses to handshake receipt of each byte of
data (see Figure 3). The MAX9895A pulls down SDA
during the master-generated 9th clock pulse. The SDA
line must remain stable and low during the high period
of the acknowledge clock pulse. Monitoring ACK allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master can reat-
tempt communication.
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master device initiates communication by issuing a
START (S) condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP (P) condition is
a low-to-high transition on SDA while SCL is high (Figure
2). A START condition from the master signals the begin-
ning of transmission to the MAX9895A. The master termi-
nates transmission and frees the bus by issuing a STOP
condition. The bus remains active if a REPEATED START
(Sr) condition is generated instead of a STOP condition.
Write Data Format
A write to the MAX9895A includes transmission of a
START (S) condition, the slave address with the R/W bit
reset to 0, one byte of data to configure the command
register, and a STOP (P) condition. Figure 4 illustrates
the proper format for one frame.
Early STOP Conditions
The MAX9895A recognizes a STOP condition at any
point during data transmission except if the STOP condi-
tion occurs in the same high pulse as a START condition.
The MAX9895A only accepts write data, but it acknowl-
edges the receipt of its address byte with the R/W bit
set high. The MAX9895A does not write to the SDA bus
12 ______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
device’s low-frequency response. Use capacitors
whose dielectrics have low-voltage coefficients, such
as tantalum or aluminum electrolytic. Capacitors with
high-voltage coefficients, such as ceramics, can result
in increased distortion at low frequencies.
COMMAND BYTE IS STORED ON
RECEIPT OF STOP CONDITION
B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9895
S
SLAVE ADDRESS
0
ACK COMMAND BYTE
ACKNOWLEDGE
ACK P
Apply same method for microphone input-coupling capac-
R/W
FROM MAX9895
itor (C
). The R for microphone input is R
.
PREIN_
IN
PREIN_
Setting the Gains
Figure 4. Write Data Format Example
The gains of the microphone input preamplifiers are set
through the feedback using the following equation:
in the event that the R/W bit is set high. Subsequently,
the master reads all 1s from the MAX9895A. Always
reset the R/W bit to 0 to avoid this situation.
A (V/V) = -(R /R )
V
F
IN
In stand-alone control mode, the internal gain stage for
MIC GAIN is fixed at 11.5dB and the PTL GAIN stage is
I2C-Enabled Software Mode
The MAX9895A can operate with or without an external
microcontroller (µC). When a µC is present, commands
are sent through the I2C protocol (SCL, SDA).
2
fixed at -5.5dB. In software control mode (I C mode),
the internal gain stage stages, MIC GAIN and PTL
2
GAIN, are programmable through the I C registers. See
the Serial Interface section for more information.
I2C-Disabled Hardware Mode
By tying SCL to ground, the I2C interface is disabled
and the device operates in hardware mode. In this
case, the SDA pin operates as a MODE select. Table 1
shows different configurations with the SDA level.
The LINE IN and HEADPHONE AMP stages each have
fixed voltage gain of 0dB.
Charge-Pump Capacitor Selection
Use ceramic capacitors with a low ESR for optimum
performance. For optimal performance over the extend-
ed temperature range, select capacitors with an X7R
dielectric. Table 2 lists suggested manufacturers.
Application Information
Input-Coupling Capacitor
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Connect PGND and GND together at a sin-
gle point on the PCB. Place the power-supply bypass
capacitor and the charge-pump hold capacitor as close
as possible to the MAX9895A. Route PGND and all traces
that carry switching transients away from GND and the
audio signal path. The thin QFN package features an
exposed pad that improves thermal efficiency. Ensure
that the exposed pad is electrically connected to PGND
The input capacitor (C ), in conjunction with the input
IN
resistor (R ), forms a highpass filter that removes the
IN
DC bias from an incoming signal (see the Functional
Diagram/Typical Applications Circuit). The AC-coupling
capacitor allows the device to bias the signal to an opti-
mum DC level. Assuming zero-source impedance, the
-3dB point of the highpass filter is given by:
1
f
=
−3dB
2πR C
IN IN
and is isolated from V , PVDD, and CPVDD.
DD
Choose the CIN so that f
is well below the lowest
-3dB
-3dB
frequency of interest. Setting f
too high affects the
Table 2. Suggest Capacitor Manufacturers
SUPPLIER
Taiyo Yuden
TDK
PHONE
FAX
WEBSITE
800-348-2496
847-803-6100
770-436-1300
847-925-0899
847-390-4405
770-436-3030
www.t-yuden.com
www.component.tdk.com
www.murata.com
Murata
______________________________________________________________________________________ 13
Active Noise-Cancelling Solution
for Stereo Headsets
2
Table 3. I C Register Table
ADDRESS
0x00
TYPE
R/W
R/W
R/W
R/W
R/W
POR
0x0B
0x0B
0x0B
0x0B
0x00
NAME
7
X
X
X
X
6
X
X
X
X
5
X
X
X
X
4
3
2
1
0
ANC_GAIN_LEFT
ANC_GAIN_RIGHT
PTL_GAIN_LEFT
PTL_GAIN_RIGHT
MODE
ANC GAIN setting for LEFT CHANNEL
ANC GAIN setting for RIGHT CHANNEL
PTL GAIN setting for LEFT CHANNEL
PTL GAIN setting for RIGHT CHANNEL
0x01
0x02
0x03
0x04
X
0
PTL
ANC
SHDN
MX895A
Table 4. Gain Setting Register 0x00, 0x01, 0x02, 0x03
0x00, 0x01
ANC GAIN [dB]
0x00, 0x01
ANC GAIN [dB]
0x00, 0x01
ANC GAIN [dB]
HEX
HEX
HEX
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
-6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
0x08
0x09
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
-14.0
-14.5
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
0x0A
0x0B (POR)
0x0C
0x0D
0x0E
0x0F
0x02, 0x03
PTL GAIN [dB]
0x02, 0x03
PTL GAIN [dB]
0x02, 0x03
PTL GAIN [dB]
HEX
HEX
HEX
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
-0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
0x08
0x09
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
-8.0
-8.5
0x0A
-9.0
0x0B (POR)
0x0C
-9.5
-10.0
-10.5
-11.0
-11.5
0x0D
0x0E
0x0F
Table 5. Mode Register 0x04
BIT
NAME
POR
FUNCTION
0: Shut down
1: Play
0
SHDN
0
0: Noise cancelling on
1: Noise cancelling off (microphone muted)
1
2
ANC
PTL
0
0
0: LINEIN routed to HPOUT
1: LINEIN attenuated; MICOUT routed to HPOUT
14 ______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Table 6. Source Select
MODE
INPUT
ANC ON
ANC OFF
Muted
Noninverting, 0dB Attenuated
PTL
NC mode, inverting, gain defined by
I C REG 01 and 02
2
Microphone In
Line In
Noninverting, gain defined by I C REG 03 and 04
2
Noninverting, 0db
Functional Diagram/Typical Applications Circuit
LINE IN L
C
IN
40
1
39
38
36
37
34
33
35
5
(B5) (A6) (A5) (B4) (B3) (A4) (B2)
(C2) (A3)
(C4)
MIC_L
R
IN
3
C
PREIN
R
PREINL
HEADPHONE L
(B6) MICIN_L
32
ANC GAIN
ANALOG
HP
HPOUT_L (A2)
SIGNAL PROCESSING
AMP
22
R
V
PREFBL
DD
23
2
PVDD
PVDD, V
DD
(C5) MICOUT_L
31
(C3) SCL
24
R
MICBIAS
CPVDD (E1)
PTL GAIN
SCL
SDA/NC_MODE
C
30 (D3) SDA
4
(C6)
VDD
2
I C CONTROL
27
MICBIAS
V
MIC_BIAS
VBIAS
MID
VMID (B1)
17
CHARGE
PUMP
(F3)
V
BIAS
C
HOLD
7, 8
(D6) GND
28, 29
PGND (A1)
C
BIAS
MAX9895
GND
PGND
CIN
PTL GAIN
R
MICOUT_R
26
MICBIAS
C
CIP (C1)
FLY
10
(D5)
25
(D1)
R
PREFBR
ANALOG
SIGNAL PROCESSING
MIC_R
HPOUT_R
HP
AMP
C
PREIN
R
PREINR
MICIN_R
21
(F1)
ANC GAIN
9
(E6)
HEADPHONE R
R
IN
( ) WLPP PACKAGE
11
18
12
13
14
16
15
19
20
6
(F6)
(E2)
(E5)
(F5) (E4) (E3) (F4) (F2)
(D2)
(D4)
C
IN
LINE IN R
______________________________________________________________________________________ 15
Active Noise-Cancelling Solution
for Stereo Headsets
Typical Applications Circuit (Hardware Mode)
3.3V
LITHIUM
BATT
STEREO
MUSIC
SOURCE
MX895A
40
1
39 38 36 37 34 33 35
5
7, 8 6
(B5)
(A6) (A5) (B4) (B3) (A4) (B2) (C2) (A3)
(C4) (D6) (D4)
3
(B5)
1µF
10Ik
HPOUT_L
MICIN_L
V
DD
PVDD
100Ik
24 (E1)
3.3Ik
CPVDD
2
10µF
1µF
(C5)
MICOUT_L
MICBIAS
4 (C6)
17 (F3)
27 (B1)
29 (A1)
V
MID
V
BIAS
MAX9895
7, 8 (B6)
1µF
GND
PGND
1µF
10 (D5)
MICOUT_R
3.3Ik
26 (C1)
25 (D1)
21 (F1)
C1N
C1P
100Ik
HPOUT_R
9
(E6)
MICIN_R
10Ik
1µF
31 30
(C3) (D3)
12 11 13 14 16 15 19 20 18
(E5) (F6) (F5) (E4) (E3) (F4) (F2) (D2) (E2)
PTL
STEREO NOISE-CANCELLING
HEADPHONES
16 ______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Typical Applications Circuit (Software Mode)
3.3V
LITHIUM
BATT
STEREO
MUSIC
SOURCE
MICROCONTROLLER
40
1
39 38 36 37 34 33 35
5
7, 8
6
(B5)
(A6) (A5) (B4) (B3) (A4) (B2) (C2) (A3)
(C4) (D6) (D4)
3
(B5)
1µF
10kI
HPOUT_L
MICIN_L
V
DD
PVDD
20kI
24 (E1)
2
(C5)
3.3kI
CPVDD
MICOUT_L
MICBIAS
10µF
1µF
4 (C6)
17 (F3)
27 (B1)
29 (A1)
V
MID
V
MAX9895
BIAS
7, 8 (B6)
1µF
GND
PGND
1µF
10
(D5)
26 (C1)
25 (D1)
21 (F1)
3.3kI
C1N
C1P
MICOUT_R
20kI
HPOUT_R
9
(E6)
MICIN_R
10kI
1µF
31 30
(C3) (D3)
12 11 13 14 16 15 19 20 18
(E5) (F6) (F5) (E4) (E3) (F4) (F2) (D2) (E2)
STEREO NOISE-CANCELLING
HEADPHONES
______________________________________________________________________________________ 17
Active Noise-Cancelling Solution
for Stereo Headsets
Typical Applications Circuit (AAA Battery, Hardware Mode)
1.5V
3.3V
ALKALINE
BATT
LX
POUT
MAX1760
REF
OUT
ISET
GND PGND FB
MX895A
STEREO
MUSIC
SOURCE
40
1
39 38 36 37 34 33 35
5
7, 8 6
(B5)
(A6) (A5) (B4) (B3) (A4) (B2) (C2) (A3)
(C4) (D6) (D4)
3
(B5)
1F
10kI
HPOUT_L
MICIN_L
V
DD
PVDD
100kI
24 (E1)
3.3kI
CPVDD
2
10µF
1µF
(C5)
MICOUT_L
MICBIAS
4 (C6)
17 (F3)
27 (B1)
29 (A1)
V
MID
V
MAX9895
BIAS
7, 8 (B6)
1µF
GND
PGND
1µF
10 (D5)
MICOUT_R
3.3kI
26 (C1)
25 (D1)
21 (F1)
C1P
C1N
100kI
HPOUT_R
9
(E6)
MICIN_R
10kI
1µF
31 30
(C3) (D3)
12 11 13 14 16 15 19 20 18
(E5) (F6) (F5) (E4) (E3) (F4) (F2) (D2) (E2)
PTL
STEREO NOISE-CANCELLING
HEADSET
18 ______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Pin Configurations
TOP VIEW
(BUMPS ON BOTTOM)
TOP VIEW
1
2
3
4
5
6
MAX9895
40 39 38 37 36 35 34 33 32 31
PGND
HPOUT_L
SPFC1_L
SPFO_L
SPFC2_L
SPR2_L
SCL
SPC4_L
SPC3_L
LINEIN_L
LINEIN_R
SPC3_R
SPC2_L
SPC1_L
SPR1_L
MICIN_L
MICBIAS
GND
A
B
A
B
30 SDA
SPR1_L
MICOUT_L
MICIN_L
MICBIAS
LINEIN_L
LINEIN_R
GND
1
2
3
4
29 PGND
+
V
28
27
N.C.
MID
V
MID
26 C1N
5
6
C
C1N
C1P
MICOUT_L
MICOUT_R
SPC1_R
C
MAX9895
25 C1P
7
24 CPVDD
23 PVDD
8
GND
*EP
D
E
F
SPFO_R
SPFC2_R
SDA
D
E
F
9
22
21
V
MICIN_R
MICOUT_R
DD
10
HPOUT_R
11 12 13 14 15 16 17 18 19 20
V
DD
SPR2_R
MICIN_R
HPOUT_R
1
SPFC1_R
2
V
SPC4_R
4
SPC2_R
5
SPR1_R
6
BIAS
3
TQFN-EP
5mm x 5mm
WLP (0.4mm pitch)
2.54mm x 2.54mm
*EP = EXPOSED PAD; CONNECT TO PGND.
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________ 19
Active Noise-Cancelling Solution
for Stereo Headsets
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
36 WLP
PACKAGE CODE
W362A2+2
DOCUMENT NO.
21-0301
40 TQFN
T4055+1
21-0140
MX895A
20 ______________________________________________________________________________________
Active Noise-Cancelling Solution
for Stereo Headsets
MX895A
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
______________________________________________________________________________________ 21
Active Noise-Cancelling Solution
for Stereo Headsets
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
MX895A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX989EUA+
Comparator, 2 Func, 7000uV Offset-Max, 300ns Response Time, CMOS, PDSO8, MICRO, SOP-8
MAXIM
©2020 ICPDF网 联系我们和版权申明