MAX9965BGCCQ-TD [MAXIM]
Comparator, 4 Func, 100000uV Offset-Max, 1.2ns Response Time, BIPolar, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, TQFP-100;
| 型号： | MAX9965BGCCQ-TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Comparator, 4 Func, 100000uV Offset-Max, 1.2ns Response Time, BIPolar, PQFP100, 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, TQFP-100 放大器 |
| 文件： | 总26页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3016; Rev 2; 5/06
Quad Low-Power, 500Mbps
ATE Driver/Comparator
General Description
Features
The MAX9965/MAX9966 four-channel, low-power, high-
speed pin electronics driver and comparator ICs
include for each channel a three-level pin driver, com-
parator, and variable clamps. The MAX9965/MAX9966
are similar to the MAX9963/MAX9964, but with even
lower window comparator dispersion for enhanced
accuracy. The driver features a wide voltage range and
high-speed operation, includes high-Z and active termi-
nation (3rd-level drive) modes, and is highly linear even
at low-voltage swings. The dual bipolar-input compara-
tor provides very low dispersion (timing variation) over a
wide variety of input conditions. The clamps provide
damping of high-speed DUT waveforms when the
device is configured as a high-impedance receiver.
High-speed, differential control inputs compatible with
ECL, LVPECL, LVDS, and GTL levels are provided for
each channel. ECL/LVPECL or flexible open-collector
outputs are available for the comparators.
♦ Small Footprint: Four Channels in 0.4in2
♦ Low Power Dissipation: 975mW/Channel (typ)
♦ High Speed: 500Mbps at 3V
P-P
♦ Very Low Timing Dispersion
♦ Wide Operating Range: -1.5V to +6.5V
♦ Active Termination (3rd-Level Drive)
♦ Low-Leakage Mode: 15nA Maximum
♦ Integrated Clamps
♦ Interface Easily with Most Logic Families
♦ Digitally Programmable Slew Rate
♦ Internal Logic Termination Resistors
♦ Low Gain and Offset Error
The A-grade version provides tight matching of gain
and offset for the driver and comparator, allowing refer-
ence levels to be shared across multiple channels in
cost-sensitive systems. For system designs that incor-
porate independent reference levels for each channel,
the B-grade version is available at reduced cost.
Ordering Information
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EPR***
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
100 TQFP-EP**
MAX9965ADCCQ*
MAX9965AKCCQ*
MAX9965AGCCQ*
MAX9965AHCCQ*
MAX9965AJCCQ*
MAX9965BDCCQ*
MAX9965BKCCQ*
MAX9965BGCCQ
MAX9965BHCCQ*
MAX9965BJCCQ
MAX9966ADCCQ*
MAX9966AKCCQ*
MAX9966AGCCQ*
MAX9966AHCCQ*
MAX9966AJCCQ*
MAX9966BDCCQ*
MAX9966BKCCQ*
MAX9966BGCCQ
MAX9966BHCCQ*
MAX9966BJCCQ*
Optional internal resistors at the high-speed inputs pro-
vide differential termination of LVDS inputs, while
optional internal resistors provide the pullup voltage
and source termination for open-collector comparator
outputs. These features significantly reduce the dis-
crete component count on the circuit board.
The MAX9965/MAX9966 operating range is -1.5V to
+6.5V, with powerdissipation of only 975mW per channel.
These devices are available in a 100-pin, 14mm x
14mm body, 0.5mm pitch TQFP with an exposed 8mm
x 8mm die pad on the top (MAX9965) or bottom
(MAX9966) of the package for efficient heat removal.
The MAX9965/MAX9966 are specified to operate with
an internal die temperature of +60°C to +100°C, and
feature a die temperature monitor output.
Applications
Memory Testers
Low-Cost Mixed-Signal/System-on-Chip Testers
Structural Testers
Pattern/Data Generators
*Future product—contact factory for availability.
**EP = Exposed pad.
***EPR = Exposed pad reversed.
Pin Configurations and Selector Guide appear at end of data
sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ABSOLUTE MAXIMUM RATINGS
V
V
to GND.........................................................-0.3V to +11.5V
to GND............................................................-7.0V to +0.3V
DLV_ to DTV_ ........................................................………… 10V
CHV_ or CLV_ to DUT_..........................................………… 10V
CH_, NCH_, CL_, NCL_ to GND...............................-2.5V to +5V
Current into DHV_, DLV_, DTV_,
CC
EE
All Other Pins ...................................(V - 0.3V) to (V
+ 0.3V)
EE
CC
V
- V ................................................................-0.3V to +18V
CC
EE
DUT_ to GND.........................................................-2.5V to +7.5V
DATA_, NDATA_, RCV_, NRCV_ to GND ................-2.5 to +5.0V
DATA_ to NDATA_ ................................................….…….. 1.5V
RCV_ to NRCV_....................................................………… 1.5V
CHV_, CLV_, CPHV_, CPLV_........................................ 10mA
Current into TEMP............................................-0.5mA to +20mA
DUT_ Short Circuit to -1.5V to +6.5V.....................….Continuous
Power Dissipation (T = +70°C)
A
V
to GND....................................................…-0.3V to +5V
MAX9965__CCQ (derate 167mW/°C
CCO_ _
SCLK, DIN, CS, RST to GND ...............................…-1.0V to +5V
DHV_, DLV_, DTV_, CHV_, CLV_ to GND .............-2.5V to +7.5V
CPHV_ to GND ......................................................-2.5V to +8.5V
CPLV_ to GND.......................................................-3.5V to +7.5V
DHV_ to DLV_........................................................………… 10V
DHV_ to DTV_........................................................………… 10V
above +70°C) ...............................................................13.3W*
MAX9966__CCQ (derate 47.6mW/°C
above +70°C) .................................................................3.8W*
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .........................................….……+125°C
Lead Temperature (soldering, 10s) .....................……….+300°C
*Dissipation wattage values are based on still air with no heat sink for the MAX9965 and slug soldered to board copper for the MAX9966.
Actual maximum power dissipation is a function of users’ heat extraction technique and may be substantially higher.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V
= -2.2V, T = +85°C, unless otherwise noted.
CPLV_ J
CC
EE
CCO_ _
CPHV_
All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
POWER SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply
V
9.5
9.75
-5.25
200
10.5
-4.5
225
-425
4.5
V
V
CC
Negative Supply
V
-6.5
EE
Positive Supply
I
(Note 2)
mA
mA
W
CC
Negative Supply
I
(Note 2)
-370
3.9
EE
Power Dissipation
P
(Notes 2, 3)
D
DUT_ CHARACTERISTICS
Operating Voltage Range Max
V
(Note 4)
-1.5
+6.5
2
V
DUT
LLEAK = 0, 0 ≤ V
≤ 3V
DUT_
Leakage Current in High-Z Mode
I
µA
DUT
LLEAK = 0, V
= -1.5V, 6.5V
5
DUT_
LLEAK = 1, 0 ≤ V
≤ 3V, T < +90°C
15
30
30
DUT_
J
Leakage Current in Low-Leakage
Mode
I
nA
LLEAK = 1, V
DUT_
= -1.5V,T < +90°C
J
DUT
LLEAK = 1, V
= 6.5V, T < +90°C
J
DUT_
Driver in term mode (DUT_ = DTV_)
Driver in high-Z mode
(Notes 5, 7)
3
5
Combined Capacitance
C
DUT
pF
Low-Leakage Enable Time
Low-Leakage Disable Time
20
20
µs
µs
(Notes 6, 7)
Time to return to the specified maximum
leakage after a 3V, 4V/ns step at DUT_
(Note 7)
Low-Leakage Recovery
10
µs
2
_______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V
= -2.2V, T = +85°C, unless otherwise noted.
CPLV_ J
CC
EE
CCO_ _
CPHV_
All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_)
Input Bias Current
Settling Time
I
25
µA
µs
BIAS
To 5mV
1
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_)
Input High Voltage
Input Low Voltage
V
-1.6
-2.0
0.15
+3.5
+3.1
1.0
V
V
V
IH
V
IL
Differential Input Voltage
V
DIFF
MAX996_ _GCCQ, MAX996_ _JCCQ,
between signal and complement
Input Resistor
96
104
Ω
SINGLE-ENDED CONTROL INPUTS (CS, RST, SCLK, DIN)
Input High Voltage
Input Low Voltage
V
1.6
3.5
V
V
IH
V
-0.1
+0.9
IL
SERIAL INTERFACE TIMING (Figure 5)
SCLK Frequency
f
50
MHz
ns
SCLK
SCLK Pulse Width High
SCLK Pulse Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
CS Pulse Width High
t
8
CH
t
8
ns
CL
t
t
3.5
3.5
3.5
3.5
3.5
20
ns
CSS0
CSS1
CSH1
ns
t
ns
t
ns
DS
DH
t
ns
t
ns
CSWH
TEMPERATURE MONITOR (TEMP)
Nominal Voltage
T = +70°C, R ≥ 10MΩ
3.43
+10
15
V
J
L
Temperature Coefficient
Output Resistance
mV/°C
kΩ
DRIVERS (Note 8)
DC OUTPUT CHARACTERISTICS (R ≥ 10MΩ )
L
DHV_, DLV_, DTV_, Output Offset
Voltage
At DUT_ with V
= 3V,
= 0
DHV_
V
MAX996_B
MAX996_B
100
mV
V/V
OS
V
= 1.5V, V
DLV_
DTV_
Measured with V
, V
,
DHV_ DLV_
DHV_, DLV_, DTV_, Gain
A
0.96
1.001
V
V
at 0 and 4.5V
DTV_
DHV_, DLV_, DTV_, Output
Voltage Temperature Coefficient
Includes both gain and offset temperature
effects
75
µV/°C
mV
0V ≤ V
≤ 3V (Note 9)
5
DUT_
Linearity Error
Full range (Notes 9, 10)
15
_______________________________________________________________________________________
3
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V
= -2.2V, T = +85°C, unless otherwise noted.
CPLV_ J
CC
EE
CCO_ _
CPHV_
All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
DHV_ to DLV_ Crosstalk
DLV_ to DHV_ Crosstalk
SYMBOL
CONDITIONS
= 200mV, 6.5V
DHV_
MIN
TYP
MAX
UNITS
mV
V
V
= 0, V
2
2
DLV_
DHV_
= 5V, V
= -1.5V, 4.8V
mV
DLV_
DTV_ to DLV_ and DHV_
Crosstalk
V
V
= 3V, V
= -1.5V, +6.5V
= 0,
DHV_
DTV_
DLV_
2
mV
DHV_ to DTV_ Crosstalk
DLV_ to DTV_ Crosstalk
V
V
V
= 1.5V, V
= 1.5V, V
= 0, V =1.6V, 3V
DHV_
3
3
mV
mV
DTV_
DTV_
DLV_
DHV_
= 3V, V
= 0, 1.4V
DLV_
DHV_, DLV_, DTV_
DC Power-Supply Rejection Ratio
and V independently set to their
EE
CC
PSRR
40
dB
min/max values
Maximum DC Drive Current
DC Output Resistance
I
60
49
120
51
mA
Ω
DUT_
R
I
I
=
=
30mA (Note 11)
1.0mA to 40mA
50
1
DUT_
DUT_
DC Output Resistance Variation
ΔR
2.5
Ω
DUT_
DUT_
DYNAMIC OUTPUT CHARACTERISTICS (Z = 50Ω)
L
V
V
V
= 0, V
= 0.1V
= 1V
30
40
50
0
DLV_
DLV_
DLV_
DHV_
DHV_
DHV_
Drive Mode Overshoot
mV
= 0, V
= 0, V
= 3V
Term Mode Overshoot
(Note 12)
mV
ns
Settling Time to Within 25mV
Settling Time to Within 5mV
3V step (Note 13)
3V step (Note 13)
10
20
ns
TIMING CHARACTERISTICS (Z = 50Ω) (Note 14)
L
Prop Delay, Data to Output
Prop Delay Match, T vs. T
t
2
2.75
ns
ps
PDD
3V
P-P
50
LH
HL
Prop Delay Match, Drivers Within
Package
(Note 15)
40
+3
60
ps
ps/°C
ps
Prop Delay Temperature
Coefficient
Prop Delay Change vs.
Pulse Width
3V , 40MHz, 2.5ns to 22.5ns pulse width,
P-P
relative to 12.5ns pulse width
Prop Delay Change vs.
Common-Mode Voltage
V
V
V
- V
= 1V, V = 0 to 6V
DHV_
85
2.9
2.9
ps
ns
ns
DHV_
DHV_
DHV_
DLV_
Prop Delay, Drive to High-Z
t
t
= 1.0V, V
= 1.0V, V
= -1.0V, V
= -1.0V, V
= 0
= 0
PDDZ
PDZD
DLV_
DLV_
DTV_
DTV_
Prop Delay, High-Z to Drive
Prop Delay, Drive to Term
Prop Delay, Term to Drive
t
t
V
V
= 3V, V
= 3V, V
= 0, V
= 1.5V
= 1.5V
2.3
2.0
ns
ns
PDDT
PDTD
DHV_
DHV_
DLV_
DLV_
DTV_
= 0, V
DTV_
DYNAMIC PERFORMANCE (Z = 50Ω)
L
0.2 V , 20% to 80%
330
670
1.2
2.0
P-P
ps
ns
1 V , 10% to 90%
450
1.1
750
1.4
P-P
Rise and Fall Time
t , t
R F
3 V , 10% to 90%
P-P
5 V , 10% to 90%
P-P
4
_______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V
= -2.2V, T = +85°C, unless otherwise noted.
CPLV_ J
CC
EE
CCO_ _
CPHV_
All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
SC1 = 0, SC0 = 1 Slew Rate
75
%
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
SC1 = 1, SC0 = 0 Slew Rate
SC1 = 1, SC0 = 1 Slew Rate
50
25
%
%
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
0.2V , V
= 0.2V, V
_ = 0
DLV
0.65
1.0
P-P DHV_
1V , V
P-P DHV_
= 1V, V
_ = 0
_ = 0
_ = 0
DLV
DLV
DLV
Minimum Pulse Width (Note 16)
Data Rate (Note 17)
ns
3V , V
P-P DHV_
= 3V, V
= 5V, V
2.0
5V , V
P-P DHV_
2.9
0.2V , V
= 0.2V, V
_ = 0
1700
1000
500
350
20
P-P DHV_
DLV
1V , V
P-P DHV_
= 1V, V
_ = 0
_ = 0
_ = 0
DLV
DLV
DLV
Mbps
3V , V
P-P DHV_
= 3V, V
= 5V, V
5V , V
P-P DHV_
Dynamic Crosstalk
(Note 18)
mV
P-P
V
= 3V, V
= 0, V
= 1.5V,
= 1.5V,
DHV_
DLV_
DTV_
Rise and Fall Time, Drive to Term
t
t
, t
1.6
0.7
ns
DTR DTF
10% to 90% (Note 19)
V
= 3V, V = 0, V
DHV_
DLV_
DTV_
Rise and Fall Time, Term to Drive
, t
ns
TDR TDF
10% to 90% (Note 19)
(Note 4)
COMPARATORS
DC CHARACTERISTICS
Input Voltage Range
Differential Input Voltage
Hysteresis
V
-1.5
8
+6.5
100
V
IN
V
V
DIFF
V
0
mV
mV
HYST
Input Offset Voltage
V
V
= 1.5V
MAX996_B
OS
DUT_
Input Offset Voltage Temperature
Coefficient
50
µV/°C
dB
Common-Mode Rejection Ratio
CMRR
PSRR
V
V
V
= -1.5V, 6.5V (Note 20)
= 1.5V (Note 9)
50
50
55
1
DUT_
DUT_
DUT_
5
Linearity Error
mV
= -1.5V and 6.5V (Note 9)
1
10
Power-Supply Rejection Ratio
V
= -1.5V, 6.5V (Note 21)
66
dB
DUT_
AC CHARACTERISTICS (Note 22)
MAX996_ _GCCQ
0.6
0.9
1.2
2.6
Minimum Pulse Width
t
(Note 23)
ns
PW(MIN)
MAX996_ _HCCQ,
MAX996_ _JCCQ
Prop Delay
t
2.0
ns
PDL
Prop Delay Temperature
Coefficient
ps/°C
_______________________________________________________________________________________
5
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V
= -2.2V, T = +85°C, unless otherwise noted.
CPLV_ J
CC
EE
CCO_ _
CPHV_
All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Prop Delay Match, High/Low vs.
Low/High
40
ps
Prop Delay Match, Comparators
Within Package
(Note 15)
40
20
ps
ps
ps
Prop Delay Dispersion vs.
Common-Mode Input
V
V
= -1.4, 6.4V (Note 24)
CHV_ = CLV_
Prop Delay Dispersion vs.
Overdrive
50mV to 500mV
60
25
45
MAX996_ _GCCQ
2.0ns to 23ns pulse
width, relative to 12.5ns
pulse width
Prop Delay Dispersion vs. Pulse
Width
ps
ps
MAX996_ _HCCQ,
MAX996_ _JCCQ
Prop Delay Dispersion vs. Slew
Rate
0.5V/ns to 6.5V/ns slew rate, peak-to-peak
variation
50
50
V
= 1.0V , t = t
P-P R F
DUT_
Term mode
= 1.0ns 10% to 90%,
relative to timing at 50%
point
Waveform Tracking 10% to 90%
ps
High-Z mode
250
OPEN-COLLECTOR LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX996_ _GCCQ)
Voltage Range
V
V
0
3.5
V
V
CCO_ _
VCCO_ _
Output Low Voltage Compliance
Output High Voltage
Set by I
, R
, and V
-0.5
OUT TERM
CCO_ _
V
V
CCO_ _ CCO_ _
- 0.1
V
I
I
= I
= I
= I
= I
= I
= I
= 0
= 0
V
OH
CH_
NCH_
CL_
NCL_
- 0.02
V
CCO_ _
- 0.4
Output Low Voltage
Output Voltage Swing
Termination Resistor
V
V
V
OL
CH_
NCH_
CL_
NCL_
0.350
48
0.380
0.442
52
Single-ended measurement from V
CH_, NCH_, CL_, NCL_
to
CCO_ _
R
TERM
Ω
Differential Rise Time
Differential Fall Time
t
20% to 80%
20% to- 80%
200
200
ps
ps
R
t
F
OPEN-EMITTER LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_: MAX996_ _JCCQ)
V
Voltage Range
V
-0.1
3.5
V
CCO_ _
CCO_ _
All outputs 50Ω to
V
Supply Current
I
330
mA
CCO_ _
VCCO_ _
(V
VCCO_ _
- 2V)
V
V
CCO_ _ CCO_ _
- 1
Output High Voltage
V
50Ω to (V
- 2V)
V
OH
VCCO_ _
- 0.88
V
V
CCO_ _ CCO_ _
Output Low Voltage
V
50Ω to (V
50Ω to (V
- 2V)
- 2V)
V
OL
VCCO_ _
VCCO_ _
- 1.73
- 1.5
Output Voltage Swing
800
850
950
mV
6
_______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -5.25V, V
= 2.5V, SC1 = SC0 = 0, V
= 7.2V, V
= -2.2V, T = +85°C, unless otherwise noted.
CPLV_ J
CC
EE
CCO_ _
CPHV_
All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
Differential Rise Time
SYMBOL
CONDITIONS
MIN
TYP
500
500
MAX
UNITS
ps
t
R
20% to 80%
20% to 80%
Differential Fall Time
t
F
ps
CLAMPS
High Clamp Input Voltage Range
Low Clamp Input Voltage Range
V
-0.3
-2.5
+7.5
+5.3
100
V
V
CPH_
V
CPL_
At DUT_ with I
At DUT_ with I
= 1mA, V
= 1.5V
= 1.5V
DUT_
CPHV_
Clamp Offset Voltage
V
mV
OS
= -1mA, V
100
DUT_
CPLV_
Offset Voltage Temperature
Coefficient
0.5
mV/°C
V
and V independently set to their min
EE
CC
40
and max values, I
= 1mA, V
= 0
CPHV_
DUT_
Clamp Power-Supply Rejection
Voltage Gain
PSRR
dB
V
and V independently set to their min
EE
CC
40
and max values, I
= -1mA, V
= 0
DUT_
CPLV_
A
0.96
1.00
V/V
V
Voltage Gain Temperature
Coefficient
-100
10
ppm/°C
I
V
= 1mA, V
= -1.5V,
CPLV_
DUT_
= -0.3V to 6.5V
CPHV_
Clamp Linearity
mV
mA
Ω
I
= -1mA, V
= 6.5V,
DUT_
CPHV_
10
V
= -1.5V to 5.3V
CPLV_
V
V
= 0, V
= -1.5V, V = 6.5V
DUT_
50
95
CPHV_
CPLV_
CPLV_
Short-Circuit Output Current
Clamp DC Impedance
I
DUT
= 5V, V
= 6.5V, V
= -1.5V
DUT_
-95
-50
CPHV_
V
= 3V, V
= 0,
CPHV_
CPLV_
50
50
55
55
I
= -5mA and -15mA
DUT
R
OUT
V
= 3V, V
= 0,
CPLV_
CPHV_
I
= 5mA and 15mA
DUT
Note 1: All min and max limits are 100% tested in production. Tests are performed at worst-case supply voltages where applicable.
Note 2: Total for quad device at worst-case setting. R ≥ 10MΩ. The applicable supply currents are measured with typical supply
L
voltages.
Note 3: Does not include internal dissipation of the comparator outputs. With output loads of 50Ω to (V
- 2V), this adds
VCCO_ _
240mW typical to the total chip power (MAX996_ _HCCQ, MAX996_ _JCCQ).
Note 4: Provided that the Absolute Maximum Ratings are not exceeded, externally forced voltages may exceed this range.
Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 6: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 7: Based on simulation results only.
Note 8: With the exception of Offset and Gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 9: Relative to straight line between 0 and 3V.
Note 10: Full ranges are -1.3V ≤ V
≤ 6.5V, -1.5V ≤ V
≤ 6.5V, -1.5V ≤ V
≤ 6.3V.
DHV_
DTV_
DLV_
Note 11: Nominal target value is 50Ω. Contact factory for alternate trim selections within the 40Ω to 50Ω range.
Note 12: V = 1.5V, R = 50Ω. External signal driven into T-line is a 0 to 3V edge with 1.2ns rise time (10% to 90%).
DTV_
S
Measurement is made using the comparator.
Note 13: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
_______________________________________________________________________________________
7
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Note 14: Prop delays are measured from the crossing point of the differential input signals to the 50% point of expected output
swing. Rise time of the differential inputs DATA_ and RCV_ is 250ps (10% to 90%).
Note 15: Rising edge to rising edge or falling edge to falling edge.
Note 16: Specified amplitude is programmed. At this pulse width, the output reaches at least 95% of its nominal (DC) amplitude.
The pulse width is measured at DATA_.
Note 17: Specified amplitude is programmed. Maximum data rate specified in transitions per second. A square wave that reaches
at least 95% of its programmed amplitude may be generated at one-half of this frequency.
Note 18: Crosstalk from any driver to the other three channels. Aggressor channel is driving 3V
into a 50Ω load. Victim channels
P-P
are in term mode with V
= 1.5V.
DTV_
Note 19: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when V
< V
< V
. If
DHV_
DLV_
DTV_
V
< V
or V
> V
, switching speed is degraded by approximately a factor of 3.
DTV_
DLV_
DTV_
DHV_
Note 20: Change in Offset Voltage over input range.
Note 21: Change in Offset Voltage with power supplies independently set to their minimum and maximum values.
Note 22: Unless otherwise noted, all Prop Delays are measured at 40MHz, V = 0 to 2V, V = V = 1V, slew rate = 2V/ns,
DUT_
CHV_
CLV_
Z = 50Ω, driver in Term Mode with V
= 0V. Comparator outputs are terminated with 50Ω to GND at scope input with
S
DTV_
V
= 2V. Open-collector outputs are also terminated (internally or externally) with R
= 50Ω to V
. Measured
CCO_ _
CCO_ _
TERM
from V
crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs.
DUT_
Note 23: V
= 0 to 1V, V
= V
= 0.5V. At this pulse width, the output reaches at least 90% of its DC Voltage swing. The
DUT_
CHV_
CLV_
pulse width is measured at the crossing points of the differential outputs.
Note 24: Relative to propagation delay at V = V = 1.5V. V = 200mV . Overdrive = 100mV.
CHV_
CLV_
DUT_
P-P
8
_______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics
DRIVER SMALL-SIGNAL RESPONSE
DRIVE TO TERM TRANSITION
DRIVER LARGE-SIGNAL RESPONSE
DLV_ = 0V
R = 50Ω
L
DLV_ = 0V
R = 50Ω
L
DHV_ = 5V
DHV_ = 500mV
DHV_ = 200mV
DHV_ TO DTV_
DHV_ = 3V
DLV_ TO DTV_
0
0
0
DHV_ = 100mV
t = 2.5ns/div
DHV_ = 1V
R = 50Ω
L
t = 5.0ns/div
t = 2.5ns/div
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
DRIVER TRAILING-EDGE TIMING ERROR
vs. PULSE WIDTH
HIGH-Z TO DRIVE TRANSITION
40
20
65
55
45
35
25
15
5
NORMALIZED TO V = 1.5V
CM
HIGH-Z TO DHV_
0
-20
-40
-60
-80
-100
RISING EDGE
0
LOW PULSE
HIGH PULSE
FALLING EDGE
-5
HIGH-Z TO DLV_
-15
-25
-35
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns, DHV_ = 3V, DLV_ = 0V
R = 50Ω
L
0
5
10
15
20
25
0
1
2
3
4
5
6
t = 5.0ns/div
PULSE WIDTH (ns)
COMMON-MODE VOLTAGE (V)
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
6
5
6
5
6
5
DUT_ = DHV_
DUT_ = DLV_
DUT_ = DTV_
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
-1
-2
-3
-4
-5
-6
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
DUT_
V
DUT_
DUT_
_______________________________________________________________________________________
9
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
CROSSTALK TO DUT_ FROM DLV_
WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM DTV_
WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM DHV_
WITH DUT_ = DLV_
2.0
1.6
0.5
0.4
2.0
1.6
DHV_ = 5V
DTV_ = 1.5V
DHV_ = 3V
DLV_ = 0
DLV_ = 0
DTV_ = 1.5V
1.2
0.3
1.2
0.8
0.2
0.8
0.4
0.1
0.4
0
0
0
-0.4
-0.8
-1.2
-1.6
-2.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.4
-0.8
-1.2
-1.6
-2.0
NORMALIZED AT DLV_ = 0V
NORMALIZED AT DTV_ = 1.5V
NORMALIZED AT DHV_ = 5V
-1.5
0
1.5
3.0
4.5
6.0
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DTV_ VOLTAGE (V)
-0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DHV_ VOLTAGE (V)
DLV_ VOLTAGE (V)
CROSSTALK TO DUT_ FROM DTV_
WITH DUT_ = DLV_
CROSSTALK TO DUT_ FROM DLV_
WITH DUT_ = DTV_
CROSSTALK TO DUT_ FROM DHV_
WITH DUT_ = DTV_
0.5
0.4
2.0
1.5
1.0
0.5
0
1.0
0.5
DLV_ = 0
DHV_ = 3V
DTV_ = 1.5V
DHV_ = 6.5V
DTV_ = 1.5V
DLV_ = -1.5V
0.3
0.2
0
0.1
0
-0.5
-1.0
-1.5
-2.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
-1.0
NORMALIZED AT DTV_ = 1.5V
NORMALIZED AT DLV_ = 0
NORMALIZED AT DHV_ = 3V
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DTV_ VOLTAGE (V)
-1.5
0
1.5
3.0
4.5
6.0
-0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DHV_ VOLTAGE (V)
DLV_ VOLTAGE (V)
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
DRIVER GAIN vs. TEMPERATURE
DRIVER OFFSET vs. TEMPERATURE
1.0008
1.0006
1.0004
1.0002
1.0000
0.9998
0.9996
0.9994
0.25
0.20
0.15
0.10
0.05
0
2.0
1.5
NORMALIZED AT T = +85°C
J
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-0.05
-0.10
NORMALIZED AT T = +85°C
J
NORMALIZED AT V = 1.5V
CM
60
70
80
90
100
60
70
80
90
100
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
10 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
COMPARATOR FALLING EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
COMPARATOR RISING EDGE TIMING
VARIATION vs. COMMON-MODE VOLTAGE
COMPARATOR TIMING VARIATION
vs. OVERDRIVE
100
75
100
75
150
130
110
90
50
50
FALLING EDGE
25
25
70
0
0
50
30
-25
-50
-75
-100
-25
-50
-75
-100
10
-10
-30
-50
RISING EDGE
NORMALIZED TO ZERO AT V = 1.5V
CM
NORMALIZED TO ZERO AT V = 1.5V
CM
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
0
0.1
0.2
0.3
0.4
0.5
0.6
OVERDRIVE (V)
COMPARATOR TRAILING EDGE TIMING
ERROR vs. PULSE WIDTH, MAX996_ _JCCQ
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE, DUT_ RISING
COMPARATOR TRAILING EDGE TIMING
ERROR vs. PULSE WIDTH, MAX996_ _GCCQ
40
60
50
40
30
20
10
0
30
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns
20
0
20
10
-20
-40
-60
-80
-100
-120
-140
HIGH PULSE
LOW PULSE
0
-10
-20
-30
-40
HIGH PULSE
LOW PULSE
NORMALIZED TO PW = 12.5ns
PERIOD = 25ns
NORMALIZED TO SR = 2V/ns
-10
0
5
10
15
20
25
0.5
1.5
2.5
3.5
4.5
5.5
6.5
0
5
10
15
20
25
PULSE WIDTH (ns)
SLEW RATE (V/ns)
PULSE WIDTH (ns)
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE (MAX996_ _GCCQ)
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE, DUT_ FALLING
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE (MAX996_ _JCCQ)
60
50
40
30
20
10
0
0
0
NORMALIZED TO SR = 2V/ns
-10
t = 2.50ns/div
0.5
1.5
2.5
3.5
4.5
5.5
6.5
t = 2.50ns/div
V
= 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V,
DUT
SLEW RATE (V/ns)
V
= 0 TO 3V PULSE, CHV_ = CLV_ = 1.5V,
DUT
EXTERNAL LOAD = 50Ω
EXTERNAL LOAD = 50Ω
______________________________________________________________________________________ 11
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
COMPARATOR RESPONSE
vs. HIGH SLEW-RATE OVERDRIVE
COMPARATOR OFFSET
vs. TEMPERATURE
CLAMP RESPONSE
0.6
0.4
TERM MODE
RISING
0.2
0
DIGITIZED
OUTPUT
INPUT
-0.2
-0.4
-0.6
-0.8
FALLING
0
0
INPUT SLEW-RATE = 17V/ns
t = 2.50ns/div
NORMALIZED TO T = +85°C
J
t = 5.0ns/div
= 0V TO 3V SQUARE WAVE, R = 25Ω
CPLV_ = -0.1V, CPHV_ = +3.1V
75
79
83
87
91
95
V
DUT
S
TEMPERATURE (°C)
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
HIGH-Z LEAKAGE CURRENT
vs. DUT_ VOLTAGE
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
1.2
1.0
100
0
V
= 3V
DUT_
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1100
-1200
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
V
= 0
DUT_
-100
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
CPHV_ VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DUT_ VOLTAGE (V)
-1.50 -1.25 -1.00 -0.75 -0.50 -0.25
CPLV_VOLTAGE (V)
0
COMPARATOR REFERENCE
INPUT CURRENT vs. INPUT VOLTAGE
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
DRIVER REFERENCE CURRENT
vs. INPUT VOLTAGE
1.00
0.75
0.50
0.25
0
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
DHV_
DTV_
CHV_
-0.25
-0.50
-0.75
-1.00
DLV_
CLV_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
INPUT VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
DUT_ VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
INPUT VOLTAGE (V)
12 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Typical Operating Characteristics (continued)
INPUT CURRENT
vs. INPUT VOLTAGE, CPHV_
INPUT CURRENT
vs. INPUT VOLTAGE, CPLV_
SUPPLY CURRENT I vs. V
CC
CC
185
170
155
140
125
110
95
600
500
400
300
200
-500
-600
-700
-800
-900
-1000
CPLV_ = -2.2V
A
B
C
80
65
50
35
CPHV_ = 7.2V
20
9.50
9.75
10.00
(V)
10.25
10.50
-0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
CPHV_ VOLTAGE (V)
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
CPLV_ VOLTAGE (V)
V
CC
A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0,
CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V
B: SAME AS A EXCEPT DUT_ = HIGH-Z
C: SAME AS B EXCEPT DUT_ = LOW LEAK
SUPPLY CURRENT I vs. V
EE
I
CC
vs. TEMPERATURE
EE
I
EE
vs. TEMPERATURE
-220
168.0
167.5
167.0
166.5
166.0
165.5
165.0
164.5
164.0
163.5
-329.0
-329.2
-329.4
-329.6
-329.8
-330.0
-330.2
-330.4
-240
-260
-280
-300
-320
-340
-360
-380
-400
C
B
A
-6.50 -6.25 -6.00 -5.75 -5.50 -5.25 -5.00 -4.75 -4.50
(V)
60
70
80
90
100
110
60
70
80
TEMPERATURE (°C)
DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0,
CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV = -2.2V,
= 9.75V, V = -5.25V
90
100
110
V
TEMPERATURE (°C)
EE
A: DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0,
CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV_ = -2.2V
B: SAME AS A EXCEPT DUT_ = HIGH-Z
DUT_ = DTV_ = 1.5V, DHV_ = 3V, DLV_ = 0,
CHV_ = CLV_ = 0, CPHV_ = 7.2V, CPLV = -2.2V,
V
= 9.75V, V = -5.25V
CC
EE
V
CC
EE
C: SAME AS B EXCEPT DUT_ = LOW LEAK
______________________________________________________________________________________ 13
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Pin Description
PIN
NAME
FUNCTION
MAX9965
MAX9966
Channel 3/4 Collector Voltage Input. For open-collector outputs, this is the pullup
voltage for the internal termination resistors. For open-emitter outputs, this is the
34 collector voltage of the output transistors. Not internally connected on open-collector
1
25
V
CCO
versions without internal termination resistors. V
channel 4.
34 services both channel 3 and
CCO
Channel 4 Multiplexer Control Inputs. Differential controls DATA4 and NDATA4 select
driver 4’s input from DHV4 or DLV4. Drive DATA4 above NDATA4 to select DHV4. Drive
NDATA4 above DATA4 to select DLV4.
2
3
24
23
DATA4
NDATA4
Channel 4 Multiplexer Control Inputs. Differential controls RCV4 and NRCV4 place
channel 4 into receive mode. Drive RCV4 above NRCV4 to place channel 4 into
receive mode. Drive NRCV4 above RCV4 to place channel 4 into drive mode.
Channel 3 Multiplexer Control Inputs. Differential controls DATA3 and NDATA3 select
driver 3’s input from DHV3 or DLV3. Drive DATA3 above NDATA3 to select DHV3.
Drive NDATA3 above DATA3 to select DLV3.
Channel 3 Multiplexer Control Inputs. Differential controls RCV3 and NRCV3 place
channel 3 into receive mode. Drive RCV3 above NRCV3 to place channel 3 into
receive mode. Drive NRCV3 above RCV3 to place channel 3 into drive mode.
4
5
6
7
8
9
22
21
20
19
18
17
RCV4
NRCV4
DATA3
NDATA3
RCV3
NRCV3
10, 27, 54, 55, 16, 27, 54, 55,
60, 61, 65, 66, 60, 61, 65, 66,
V
Negative Power-Supply Input
EE
71, 72, 99
71, 72, 99
11, 28, 51, 56, 15, 28, 51, 56,
62, 64, 70, 75, 62, 64, 70, 75,
GND
Ground Connection
98
98
Reset Input. Asynchronous reset input for the serial register. RST is active low
12
14
RST
and asserts low-leakage mode. At power-up, hold RST low until V and V
CC
EE
have stabilized.
13
14
15
13
12
11
CS
SCLK
DIN
Chip Select Input. Serial port activation input. CS is active low.
Serial Clock Input. Clock for serial port.
Data Input. Serial port data input.
16, 26, 52, 58, 10, 26, 52, 58,
V
Positive Power-Supply Input
CC
68, 74, 100
68, 74, 100
Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place
channel 2 into receive mode. Drive RCV2 above NRCV2 to place channel 2 into
receive mode. Drive NRCV2 above RCV2 to place channel 2 into drive mode.
Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select
driver 2’s input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2.
Drive NDATA2 above DATA2 to select DLV2.
Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place
channel 1 into receive mode. Drive RCV1 above NRCV1 to place channel 1 into
receive mode. Drive NRCV1 above RCV1 to place channel 1 into drive mode.
17
18
19
20
21
22
9
8
7
6
5
4
NRCV2
RCV2
NDATA2
DATA2
NRCV1
RCV1
Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select
driver 1’s input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1.
Drive NDATA1 above DATA1 to select DLV1.
23
24
3
2
NDATA1
DATA1
14 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9965
MAX9966
Channel 1/2 Collector Voltage Input. For open-collector outputs, this is the pullup
voltage for the internal termination resistors. For open-emitter outputs, this is the
25
1
V
12 collector voltage of the output transistors. Not internally connected on open-collector
CCO
versions without internal termination resistors. V
channel 2.
12 services both channel 1 and
CCO
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
NCL2
CL2
Channel 2 Low Comparator Output. Differential output of channel 2 low comparator.
Channel 2 High Comparator Output. Differential output of channel 2 high comparator.
Channel 1 Low Comparator Output. Differential output of channel 1 low comparator.
Channel 1 High Comparator Output. Differential output of channel 1 high comparator.
NCH2
CH2
NCL1
CL1
NCH1
CH1
CPHV2 Channel 2 High Clamp Reference Input
CPLV2 Channel 2 Low Clamp Reference Input
DHV2
DLV2
DTV2
CHV2
CLV2
Channel 2 Driver High Reference Input
Channel 2 Driver Low Reference Input
Channel 2 Driver Termination Reference Input
Channel 2 High Comparator Reference Input
Channel 2 Low Comparator Reference Input
CPHV1 Channel 1 High Clamp Reference Input
CPLV1 Channel 1 Low Clamp Reference Input
DHV1
DLV1
DTV1
CHV1
CLV1
Channel 1 Driver High Reference Input
Channel 1 Driver Low Reference Input
Channel 1 Driver Termination Reference Input
Channel 1 High Comparator Reference Input
Channel 1 Low Comparator Reference Input
Channel 1 Device Under Test Input/Output. Combined I/O for driver, comparator, and
clamp.
53
57, 69
59
73
57, 69
67
DUT1
N.C.
No Connect. Leave open.
Channel 2 Device Under Test Input/Output. Combined I/O for driver, comparator, and
clamp.
DUT2
TEMP
63
63
Temperature Monitor Output
______________________________________________________________________________________ 15
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Pin Description (continued)
PIN
NAME
FUNCTION
MAX9965
MAX9966
Channel 3 Device Under Test Input/Output. Combined I/O for driver, comparator, and
clamp.
67
59
DUT3
DUT4
Channel 4 Device Under Test Input/Output. Combined I/O for driver, comparator, and
clamp.
73
53
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLV4
CHV4
DTV4
DLV4
DHV4
Channel 4 Low Comparator Reference Input
Channel 4 High Comparator Reference Input
Channel 4 Driver Termination Reference Input
Channel 4 Driver Low Reference Input
Channel 4 Driver High Reference Input
CPLV4 Channel 4 Low Clamp Reference Input
CPHV4 Channel 4 High Clamp Reference Input
CLV3
CHV3
DTV3
DLV3
DHV3
Channel 3 Low Comparator Reference Input
Channel 3 High Comparator Reference Input
Channel 3 Driver Termination Reference Input
Channel 3 Driver Low Reference Input
Channel 3 Driver High Reference Input
CPLV3 Channel 3 Low Clamp Reference Input
CPHV3 Channel 3 High Clamp Reference Input
CH4
Channel 4 High Comparator Output. Differential outputs of channel 4 high comparator.
NCH4
CL4
Channel 4 Low Comparator Output. Differential outputs of channel 4 low comparator.
NCL4
CH3
Channel 3 High Comparator Output. Differential outputs of channel 3 high comparator.
NCH3
CL3
Channel 3 Low Comparator Output. Differential outputs of channel 3 low comparator.
NCL3
16 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
ONE OF FOUR IDENTICAL CHANNELS SHOWN
MULTIPLEXER
DLV_
DHV_
DTV_
SLEW-
RATE
CONTROL
BUFFER
50Ω
DUT_
SC0
SC1
LLEAK
OPTIONAL
100Ω
MAX9965
MAX9966
DATA_
NDATA_
RCV_
HIGH-Z
NRCV_
OPTIONAL
100Ω
TMSEL
CLAMPS
CPHV_
CPLV_
CHV_
CH_
NCH_
2Ω
2Ω
COMPARATORS
4 x 48Ω
OPTIONAL
V
CCO_ _
CL_
NCL_
CLV_
TEMP
CS
SERIAL INTERFACE IS COMMON TO ALL FOUR CHANNELS.
MODE BITS ARE INDEPENTENTLY
CH_ MODE BITS
V
CC
EE
LLEAK
LATCHED FOR EACH CHANNEL.
SCLK
DIN
SC0
V
SERIAL
INTERFACE
SC1
GND
RST
TMSEL
Figure 1. MAX9965/MAX9966 Block Diagram
______________________________________________________________________________________ 17
Quad Low-Power, 500Mbps
ATE Driver/Comparator
The MAX9965/MAX9966 modal operation is pro-
grammed through a 3-wire, low-voltage, CMOS-com-
patible serial interface.
Detailed Description
The MAX9965/MAX9966 four-channel, high-speed pin
electronics driver and comparator ICs for automatic test
equipment include, for each channel, a three-level pin
driver, a dual comparator, and variable clamps (Figure
1). The driver features a -1.5V to +6.5V operating range
and high-speed operation, including high-Z and active
termination (3rd-level drive) modes, which is highly lin-
ear even at low-voltage swings. The devices are similar
to the MAX9963/MAX9964 but with a comparator that
provides even lower timing dispersion, due to changes
in input slew rate and pulse width. The clamps provide
damping of high-speed DUT_ waveforms when the
device is configured as a high-impedance receiver.
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_
and RCV_, and mode control bit TMSEL. A slew-rate
circuit controls the slew rate of the buffer input. One of
four possible slew rates can be selected (Table 1); the
speed of the internal multiplexer sets the 100% driver
slew rate (see the Driver Large-Signal Response in the
Typical Operating Characteristics).
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
in low-leakage mode (Figure 2, Table 2). In high-imped-
ance mode, the clamps are connected. This switching
is controlled by the high-speed input RCV_ and the
mode control bits TMSEL and LLEAK. In high-imped-
ance mode, the bias current at DUT_ is less than 2µA
over the 0 to 3V range, while the node maintains its
ability to track high-speed signals. In low-leakage
mode, the bias current at DUT_ is further reduced to
less than 15nA. See the Low-Leakage Mode section for
more detailed information.
Each of the four channels has high-speed, differential
inputs compatible with ECL, LVPECL, LVDS, and GTL
signal levels, with optional 100Ω differential input termi-
nations. Optional internal resistors at DATA_ and RCV_
provide differential termination of LVDS inputs. Optional
internal resistors at CH_ and CL_ provide the pullup
voltage and source termination for open-collector com-
parator outputs. These options significantly reduce the
discrete component count on the circuit board.
The MAX9965/MAX9966 are available in two grade
options. An A-grade version provides tighter matching of
gain and offset of the drivers, and tighter offset matching
of the comparators. This allows reference levels to be
shared across multiple channels in cost-sensitive sys-
tems. A B-grade version provides lower cost for system
designs that incorporate independent reference levels for
each channel.
The nominal driver output resistance is 50Ω. Contact the
factory for different values within the 40Ω to 50Ω range.
REFERENCE
INPUTS
HIGH-
SPEED
INPUTS
0
1
DLV_
0
1
0
DHV_
DTV_
SLEW RATE
BUFFER
0
50Ω
DUT_
1
DATA_
RCV_
HIGH-Z
CPHV_
CPLV_
CLAMPS
COMPARATORS
4
MODE
Figure 2. Simplified Driver Channel
18 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Table 1. Slew Rate Logic
Table 3. Comparator Logic
SC1
SC0
DRIVER SLEW RATE (%)
DUT_ > CHV_
DUT_ > CLV_
CH_
CL_
0
0
0
1
1
0
1
0
1
100
75
0
0
1
1
0
1
0
1
0
0
1
1
1
50
0
25
1
Table 2. Driver Logic
CH_
DUT_
CHV_
EXTERNAL
CONNECTIONS
INTERNAL CONTROL
REGISTER
8mA
DRIVER OUTPUT
DATA_ RCV_
TMSEL
LLEAK
V
EE
NCH_
1
0
0
0
X
X
0
0
Drive to DHV_
Drive to DLV_
Drive to DTV_
(term mode)
High-impedance
mode (high-z)
2Ω
2Ω
X
1
1
0
4 x 48Ω
OPTIONAL
V
CCO_ _
X
X
1
X
0
X
0
1
Low-leakage mode
Clamps
CL_
8mA
A pair of voltage clamps (high and low) can be config-
ured to limit the voltage at DUT_, and to suppress
reflections when the channel is configured as a high-
impedance receiver. The clamps behave as diodes
connected to the outputs of high-current buffers.
Internal circuitry compensates for the diode drop at
1mA clamp current. Set the clamp voltages using exter-
nal connections CPHV_ and CPLV_. The clamps are
enabled only when the driver is in the high-impedance
mode (Figure 2). For transient suppression, set the
clamp voltages to approximately the minimum and
maximum expected DUT_ voltage range and must be
empirically determined. The optimal clamp voltages are
application specific. If clamping is not desired, set the
clamp voltages at least 0.7V outside the expected
DUT_ voltage range; overvoltage protection remains
active without loading DUT_.
CLV_
V
EE
NCL_
Figure 3. Open-Collector Comparator Outputs
CH_
106Ω
DUT_
CHV_
106Ω
NCH_
V
CCO_ _
Comparators
The MAX9965/MAX9966 have two independent high-
speed comparators for each channel. Each comparator
has one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (Figure 1).
Comparator outputs are a logical result of the input con-
ditions, as indicated in Table 3.
CL_
106Ω
CLV_
106Ω
The MAX9965/MAX9966s’ comparators feature BJT
inputs for improved comparator dispersion in contrast
to the MAX9963/MAX9964s’ JFET comparators.
NCL_
Figure 4. Open-Emitter Comparator Outputs
______________________________________________________________________________________ 19
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Three configurations are available for the comparator
Table 4. Shift Register Functions
differential outputs to ease interfacing with a wide vari-
ety of logic families. An open-collector configuration
switches an 8mA current source between two outputs.
This configuration is available with and without internal
BIT
NAME
FUNCTION
Channel 1 Write Enable. Set to 1 to
D7
1E
update the control byte for channel 1. Set
to zero to make no change to channel 1.
termination resistors connected to V
(Figure 3).
CCO_
unconnected and
For external termination, leave V
CCO_
add the required external resistors. These resistors are
typically 50Ω to the pullup voltage at the receiving end
of the output trace. Alternate configurations may be
used, provided that the Absolute Maximum Ratings are
Channel 2 Write Enable. Set to 1 to
update the control byte for channel 2. Set
to zero to make no change to channel 2.
D6
D5
D4
D3
2E
3E
4E
Channel 3 Write Enable. Set to 1 to
update the control byte for channel 3. Set
to zero to make no change to channel 3.
not exceeded. For internal termination, connect V
CCO_
to the desired VOH voltage. Each output provides a
nominal 400mV swing and 50Ω source termination.
P-P
An open-emitter configuration is also available (Figure
4). Connect an external collector voltage to V and
Channel 4 Write Enable. Set to 1 to
update the control byte for channel 4. Set
to zero to make no change to channel 4.
CCO_
add external pulldown resistors. These are typically
-2V at the receiving end of the output
50Ω to V
CCO_
Low-Leakage Select. Set to 1 to put
LLEAK driver and clamps into low-leakage
mode. Set to zero for normal operation.
trace. Alternate configurations may be used, provided
that the Absolute Maximum Ratings are not exceeded.
Low-Leakage Mode, LLEAK
Asserting LLEAK through the serial port or with RST
places the MAX9965/MAX9966 into a very-low-leakage
state in which the DUT_ input current is less than 15nA
over the 0 to 3V range. In this mode, the driver, compara-
tors, and clamps are disabled. This mode is convenient
for making IDDQ and PMU measurements without the
need for an output disconnect relay. LLEAK is pro-
grammed independently for each channel. If DUT_ is dri-
ven with a high-speed signal while LLEAK is asserted,
leakage current momentarily increases beyond the limits
specified for normal operation. The Low-Leakage
Recovery specification in the Electrical Characteristics
table indicates device behavior under this condition.
D2
D1
SC1
SC0
Driver Slew Rate Select. SC1 and SC0
set the driver slew rate. See Table 1.
Driver Termination Select. Set to 1 to
force the driver output to the DTV_
voltage (term mode) when RCV_ = 1. Set
to zero to place the driver into a high
impedance state (high-z mode) when
RCV_ = 1. See Table 2.
D0
TMSEL
t
CH
SCLK
t
t
t
CL
CSS0
CSS1
t
CSH1
CS
t
CSWH
t
DH
t
DS
DIN
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Serial Interface Timing
20 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
SHIFT REGISTER
SCLK
0
1
2
3
4
5
6
7
DIN
CS
ENABLE
F/F
F/F
F/F
F/F
3
7
3
6
3
5
3
4
D
Q
D
Q
D
Q
D
Q
ENABLE
RST
ENABLE
RST
ENABLE
RST
ENABLE
RST
RST
F/F
D
F/F
D
F/F
D
F/F
D
0-2
7
0-2
6
0-2
5
0-2
4
Q
Q
Q
Q
3
1
3
1
3
1
3
1
ENABLE
ENABLE
ENABLE
ENABLE
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 1
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 2
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 3
TMSEL, SC0, SC1 LLEAK
MODE BITS CHANNEL 4
Figure 6. Serial Interface
and RCV_, manage the features of each channel, as
shown in Tables 1 and 2. RST sets LLEAK = 1 for all
channels, forcing them into low-leakage mode. All other
bits are unaffected. At power-up, hold RST low until
Temperature Monitor
Each device supplies a single temperature output sig-
nal, TEMP, that asserts a nominal output voltage of
3.43V at a die temperature of +70°C (343K). The output
voltage increases proportionately with temperature at a
rate of 10mV/°C. The temperature sensor output imped-
ance is 15kΩ (typ).
V
and V have stabilized.
EE
CC
Heat Removal
These devices require heat removal under normal cir-
cumstances through the exposed pad, either by solder-
ing to circuit board copper (MAX9966) or by use of an
external heat sink (MAX9965). The exposed pad is
Serial Interface and Device Control
A CMOS-compatible serial interface controls the
MAX9965/MAX9966 modes (Figure 6). Control data
flow into a bit shift register (MSB first) and are latched
when CS is taken high, as shown in the serial timing
diagram, Figure 5. Data from the shift register are then
loaded into any or all of a group of four quad latches,
determined by bits D4 through D7, as indicated in
Figure 6 and Table 4. The quad latches contain the four
mode bits for each channel of the quad pin driver. The
mode bits, in conjunction with external inputs DATA_
electrically at V potential for both package types, and
EE
must be either connected to V or isolated.
EE
Chip Information
TRANSISTOR COUNT: 7293
PROCESS: Bipolar
______________________________________________________________________________________ 21
Quad Low-Power, 500Mbps
ATE Driver/Comparator
Selector Guide
COMPARATOR
OUTPUT
TERMINATION
HIGH-SPEED
DIGITAL INPUT
TERMINATION
ACCURACY
GRADE
COMPARATOR
OUTPUT TYPE
HEAT
EXTRACTION
PIN-
PACKAGE
PART
MAX9965ADCCQ*
MAX9965AKCCQ*
MAX9965AGCCQ*
MAX9965AHCCQ*
MAX9965AJCCQ*
MAX9965BDCCQ*
MAX9965BKCCQ*
MAX9965BGCCQ
MAX9965BHCCQ*
MAX9965BJCCQ
MAX9966ADCCQ*
MAX9966AKCCQ*
MAX9966AGCCQ*
MAX9966AHCCQ*
MAX9966AJCCQ*
MAX9966BDCCQ*
MAX9966BKCCQ*
MAX9966BGCCQ
MAX9966BHCCQ*
MAX9966BJCCQ*
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
B
B
B
B
B
Open collector
Open collector
Open collector
Open emitter
Open emitter
Open collector
Open collector
Open collector
Open emitter
Open emitter
Open collector
Open collector
Open collector
Open emitter
Open emitter
Open collector
Open collector
Open collector
Open emitter
Open emitter
None
None
None
Top
Top
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EPR
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100 TQFP-EP
100Ω LVDS
100Ω LVDS
None
50Ω to V
Top
CCO__
None
Top
None
None
None
100Ω LVDS
None
Top
Top
100Ω LVDS
100Ω LVDS
None
Top
50Ω to V
Top
CCO__
None
None
None
None
Top
100Ω LVDS
None
Top
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
100Ω LVDS
100Ω LVDS
None
50Ω to V
CCO__
None
None
None
None
100Ω LVDS
None
100Ω LVDS
100Ω LVDS
None
50Ω to V
CCO__
None
None
100Ω LVDS
*Future product—contact factory for availability.
22 ______________________________________________________________________________________
Quad Low-Power, 500Mbps
ATE Driver/Comparator
MAX9965 Pin Configuration
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
V
34
1
2
75 GND
74
73 DUT4
CCO
DATA4
NDATA4
RCV4
V
CC
3
4
72
71
V
V
EE
EE
MAX9965
NRCV4
DATA3
NDATA3
RCV3
5
6
70 GND
69 N.C.
7
8
68
V
CC
NRCV3
9
67 DUT3
V
10
66
65
V
V
EE
EE
EE
GND 11
RST 12
CS 13
64 GND
63 TEMP
62 GND
SCLK 14
DIN 15
61
60
V
V
EE
EE
V
CC
16
NRCV2 17
RCV2 18
59 DUT2
58
V
CC
NDATA2 19
DATA2 20
NRCV1 21
RCV1 22
57 N.C.
56 GND
55
54
V
V
EE
EE
NDATA1 23
DATA1 24
53 DUT1
52
51 GND
V
CC
V
CCO
12 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TQFP-EPR
______________________________________________________________________________________ 23
Quad Low-Power, 500Mbps
ATE Driver/Comparator
MAX9966 Pin Configuration
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
V
12
1
2
75 GND
74
73 DUT1
CCO
DATA1
NDATA1
RCV1
V
CC
3
4
72
71
V
V
EE
EE
MAX9966
NRCV1
DATA2
NDATA2
RCV2
5
6
70 GND
69 N.C.
7
8
68
V
CC
NRCV2
9
67 DUT2
V
10
66
65
V
V
CC
EE
EE
DIN 11
12
64 GND
63 TEMP
62 GND
SCLK
CS 13
14
RST
GND 15
16
61
60
V
V
EE
EE
V
EE
NRCV3 17
RCV3 18
59 DUT3
58
V
CC
NDATA3 19
DATA3 20
NRCV4 21
RCV4 22
57 N.C.
56 GND
55
54
V
V
EE
EE
NDATA4 23
DATA4 24
53 DUT4
52
51 GND
V
CC
V
CCO
34 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TQFP-EP
Package Information
For the latest package outline information, go to
www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
ENGL ISH • ? ? ? ? • ? ? ? • ? ? ?
WH AT 'S NEW
PR OD UC TS
SO LUTI ONS
D ES IG N
A PPNOTES
SU PPORT
B U Y
COM PA N Y
M EMB ERS
M A X 9 9 6 5
Pa rt Nu m ber T abl e
N
o
t
e
s
:
1 . S e e t h e M A X 9 9 6 5 Q u i c k V i e w D a t a S h e e t f o r f u r t h e r i n f o r m a t i o n o n t h i s p r o d u c t f a m i l y o r d o w n l o a d t h e
M A X 9 9 6 5 f u l l d a t a s h e e t ( P D F , 4 8 4 k B ) .
2 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
3 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n
o
n
e
b
u
s
i
n
e
s
s
d
a
y
.
4 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e f u l l
d a t a s h e e t o r P a r t N a m i n g C o n v e n t i o n s .
5 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e p r o d u c t
u s e s .
P
a
r
t
N
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b
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F r e e
S a m p l e
B u y
D i r e c t
T
e
m
p
R o H S / L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : T Y P E P I N S S I Z E
D R A W I N G C O D E / V A R *
M
A
X
9
9
6
5
B
G
C
C
Q
-
T
D
0 C t o + 7 0 C R o H S / L e a d - F r e e : N o
0 C t o + 7 0 C R o H S / L e a d - F r e e : N o
0 C t o + 7 0 C R o H S / L e a d - F r e e : Y e s
0 C t o + 7 0 C R o H S / L e a d - F r e e : Y e s
0 C t o + 7 0 C R o H S / L e a d - F r e e : Y e s
M A X 9 9 6 5 B J C C Q - T D
M A X 9 9 6 5 B G C C Q + T D
M A X 9 9 6 5 B J C C Q + D
M A X 9 9 6 5 B J C C Q + T D
M A X 9 9 6 5 B G C C Q - D
M A X 9 9 6 5 B J C C Q - D
T Q F P ; 1 0 0 p i n ; 1 4 x 1 4 x 1 m m
D w g : 2 1 - 0 1 4 8 A ( P D F )
U s e p k g c o d e / v a r i a t i o n : C 1 0 0 E - 8 R *
0 C t o + 7 0 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
T Q F P ; 1 0 0 p i n ; 1 4 x 1 4 x 1 m m
D w g : 2 1 - 0 1 4 8 A ( P D F )
0 C t o + 7 0 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U
s
e
p
k
g
c
o
d
e
/
v
a
r
i
a
t
i
o
n
:
C
1
0
0
E
-
8
R
*
M A X 9 9 6 5 B G C C Q + D
T Q F P ; 1 0 0 p i n ; 1 4 x 1 4 x 1 . 0 m m
D w g : 2 1 - 0 1 4 8 A ( P D F )
0 C t o + 7 0 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : C 1 0 0 E + 8 R *
D i d n ' t F i n d W h a t Y o u N e e d ?
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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