MAX9969BRCCQ+TD [MAXIM]
Analog Circuit, 1 Func, PQFP100, 14 X 14 MM, 1 MM HEIGHT, LEAD FREE, TQFP-100;
| 型号： | MAX9969BRCCQ+TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PQFP100, 14 X 14 MM, 1 MM HEIGHT, LEAD FREE, TQFP-100 |
| 文件： | 总31页 (文件大小：889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3389; Rev 0; 8/04
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
General Description
Features
ꢀ Low-Power Dissipation: 1.4W/Channel (typ)
The MAX9969 dual, low-power, high-speed, pin elec-
tronics driver/comparator with 35mA load IC includes,
for each channel, a three-level pin driver, a dual com-
parator, variable clamps, and an active load. An addi-
tional differential comparator allows comparisons
between the two channels. The driver features a wide
voltage range and high-speed operation, includes high-
impedance and active-termination (3rd-level drive)
modes, and is highly linear even at low voltage swings.
The dual comparator provides low dispersion (timing
variation) over a wide variety of input conditions, and
differential outputs. The clamps provide damping of
high-speed device-under-test (DUT) waveforms when
the device is configured as a high-impedance receiver.
The programmable load supplies up to 35mA of source
and sink current. The load facilitates contact/continuity
testing, at-speed parametric testing of IOH and IOL,
and pullup of high-output-impedance devices. The
MAX9969A features tighter matching of offset for the
drivers and the comparators.
ꢀ Greatly Reduced Power Penalty when Load
Commutated
ꢀ High Speed: 1200Mbps at 3V
and 1800Mbps
P-P
at 1V
P-P
ꢀ Programmable 35mA Active-Load Current
ꢀ Low Timing Dispersion
ꢀ Wide -1.5V to +6.5V Operating Range
ꢀ Active Termination (3rd-Level Drive)
ꢀ Low-Leakage Mode: 15nA
ꢀ Integrated Clamps
ꢀ Integrated Differential Comparator
ꢀ Interfaces Easily with Most Logic Families
ꢀ Digitally Programmable Slew Rate
ꢀ Internal Termination Resistors
ꢀ Low Offset Error
The MAX9969 provides high-speed, differential control
inputs with optional internal termination resistors that
are compatible with LVPECL, LVDS, and GTL. Flexible
open-collector outputs with optional internal pullup
resistors are available for the comparators. These fea-
tures significantly reduce the discrete component count
on the circuit board.
ꢀ Pin Compatible with the MAX9967
Ordering Information
PART
TEMP RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
100 TQFP-EPR**
100 TQFP-EPR**
100 TQFP-EPR**
100 TQFP-EPR**
100 TQFP-EPR**
100 TQFP-EPR**
100 TQFP-EPR**
100 TQFP-EPR**
MAX9969ADCCQ
MAX9969AGCCQ*
MAX9969ALCCQ
MAX9969ARCCQ*
MAX9969BDCCQ
MAX9969BGCCQ*
MAX9969BLCCQ
MAX9969BRCCQ
A 3-wire, low-voltage, CMOS-compatible serial inter-
face programs the low-leakage, slew-rate limit, and tri-
state/terminate operational configurations of the
MAX9969.
The MAX9969’s operating range is -1.5V to +6.5V with
power dissipation of only 1.4W per channel. The device
is available in a 100-pin, 14mm x 14mm body, and
0.5mm pitch TQFP. An exposed 8mm x 8mm die pad
on the top of the package facilitates efficient heat
removal. The device is specified to operate with an
internal die temperature of +60°C to +100°C, and fea-
tures a die temperature monitor output.
*Future product—contact factory for availability.
**EPR = Exposed pad reversed (TOP).
Applications
High-Performance Mixed-Signal/
System-on-Chip ATE
High-Performance Memory ATE
Pin Configuration and Selector Guide appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ABSOLUTE MAXIMUM RATINGS
V
V
V
to GND............................................................-0.3V to +11V
to GND..........................................................-5.75V to +0.3V
DHV_, DLV_, DTV_, CHV_, CLV_,
CC
EE
CC
COM_ to GND ...................................................-2.5V to +7.5V
CPHV_ to GND .........................................................-1V to +8.5V
CPLV_ to GND..........................................................-3.5V to +6V
DHV_ to DLV_ ...................................................................... 10V
DHV_ to DTV_ ...................................................................... 10V
DLV_ to DTV_....................................................................... 10V
CHV_ or CLV_ to DUT_........................................................ 10V
CH_, NCH_, CL_, NCL_ to GND..................................-1V to +5V
- V ...........................................................-0.3V to +16.75V
EE
GS to GND............................................................................. 1V
DUT_ to GND.......................................................-2.75V to +7.5V
LDH_, LDL_ to GND .................................................-0.3V to +6V
DATA_, NDATA_, RCV_, NRCV_, LDEN_,
NLDEN_ to GND...................................................-2.5V to +5V
DATA_ to NDATA_, RCV_ to NRCV_,
LDEN_ to NLDEN_.......................................................... 1.5V
TDATA_, TRCV_, TLDEN_ to GND ...........................-2.5V to +5V
DATA_, NDATA_, to TDATA_................................................. 2V
RCV_, NRCV_, to TRCV_ ....................................................... 2V
LDEN_, NLDEN_ to TLDEN_.................................................. 2V
All Other Pins to GND ......................(V - 0.3V) to (V
TEMP Current...................................................-0.5mA to +20mA
DUT_ Short Circuit to -1.5V to +6.5V..........................Continuous
+ 0.3V)
EE
CC
Continuous Power Dissipation (T = +70°C)
A
MAX9969_ _CCQ (derate 167mW/°C above +70°C) ...13.3W*
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature .....................................................+125°C
V
to GND..........................................................-0.3V to +5V
SCLK, DIN, CS, RST to GND ......................................-1V to +5V
CCO_
*Dissipation wattage values are based on still air with no heat sink. Actual maximum power dissipation is a function of heat extraction
technique and may be substantially higher.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
POWER SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Positive Supply
Negative Supply
V
9.5
9.75
-4.75
165
10.5
-4.50
185
V
V
CC
V
-5.25
EE
V
_ = V
_ = V
_ = 0, R ≥ 10MΩ
L
LDH
LDL
V
V
_ = 3.5V, R = 0,
L
LDH
LDL
Positive Supply Current (Note 2)
Negative Supply Current (Note 2)
Power Dissipation (Notes 2, 3)
I
mA
mA
W
CC
_ = 1.5V, load enabled,
COM
245
-235
-315
2.8
275
-260
-350
3.2
driver = high impedance
V
_ = V
_ = 0, R ≥ 10MΩ
L
LDH
LDL
V
V
_ = V
_ = 3.5V, R = 0,
L
LDH
LDL
I
EE
_ = -1V, load enabled,
COM
driver = high impedance
V
_ = V
_ = 0
LDH
LDL
V
V
_ = V
_ = 3.5V, R = 0,
L
LDH
LDL
P
D
_ = 1.5V, load enabled,
COM
3.3
3.7
driver = high impedance
DUT_ CHARACTERISTICS
Operating Voltage Range
V
(Note 4)
-1.5
+6.5
3
V
DUT
Leakage Current in
High-Impedance Mode
I
LLEAK = 0; V
LLEAK = 1; V
_ = -1.5V, 0, +3V, +6.5V
_ = -1.5V, 0, +3V, +6.5V
µA
DUT
DUT
Leakage Current in
Low-Leakage Mode
15
nA
DUT
2
_______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
Driver in term mode (DUT_ = DTV_)
Driver in high-impedance mode
(Notes 5, 6)
MIN
TYP
3
MAX
UNITS
5
6
Combined Capacitance
C
pF
DUT
5
Low-Leakage Enable Time
Low-Leakage Disable Time
20
0.1
µs
µs
(Notes 6, 7)
Time to return to the specified maximum
leakage after a 3V, 4V/ns step at DUT_
(Note 7)
Low-Leakage Recovery
4
µs
LEVEL PROGRAMMING INPUTS (DHV_, DLV_, DTV_, CHV_, CLV_, CPHV_, CPLV_, COM_, LDH_, LDL_)
Input Bias Current
Settling Time
I
MAX9969_RCCQ
25
µA
µs
BIAS
To 0.1% of full scale change (Note 7)
1
DIFFERENTIAL CONTROL INPUTS (DATA_, NDATA_, RCV_, NRCV_, LDEN_, NLDEN_)
Input High Voltage
Input Low Voltage
V
0
3.5
V
V
IH
V
-0.2
0.15
+3.1
1.00
IL
Between differential inputs
Differential Input Voltage
Input Bias Current
V
V
µA
V
DIFF
Between a differential input and its
termination voltage (Note 7)
1.9
25
MAX9969_DCCQ, MAX9969_RCCQ
V
V
_
_
TDATA
MAX9969_GCCQ, MAX9969_LCCQ and
MAX9969_RCCQ
Input Termination Voltage
V
_
0
+3.5
52.5
1.45
TRCV
TLDEN
MAX9969_GCCQ, MAX9969_LCCQ, and
MAX9969_RCCQ between signal and
corresponding termination voltage input
Input Termination Resistor
47.5
1.05
0.43
Ω
SINGLE-ENDED CONTROL INPUTS (CS, SCLK, DIN, RST)
Internal Threshold Reference
V
1.25
20
V
kΩ
V
THRINT
Internal Reference Output
Resistance
R
O
External Threshold Reference
V
1.73
3.5
THR
V
+
THR
0.2
Input High Voltage
V
V
IH
V
-
THR
0.2
Input Low Voltage
Input Bias Current
V
-0.1
V
IL
I
25
µA
B
SERIAL INTERFACE TIMING (Figure 5)
SCLK Frequency
f
50
MHz
ns
SCLK
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
t
8
CH
t
8
ns
CL
t
t
3.5
3.5
ns
CSS0
CSS1
ns
_______________________________________________________________________________________
3
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
CS Pulse Width High
SYMBOL
CONDITIONS
MIN
3.5
3.5
3.5
20
TYP
MAX
UNITS
ns
t
CSH1
t
ns
DS
t
ns
DH
t
ns
CSWH
TEMPERATURE MONITOR (TEMP)
Nominal Voltage
T = +70°C, R ≥ 10MΩ
3.33
+10
20
V
J
L
Temperature Coefficient
Output Resistance
mV/°C
kΩ
DRIVERS (Note 8)
DC OUTPUT CHARACTERISTICS (R ≥ 10MΩ)
L
At DUT_ with V
_,
DHV
MAX9969A
MAX9969B
15
V
_, V _
DTV DLV
DHV_, DLV_, DTV_,
Output Offset Voltage
V
mV
OS
independently tested
at +1.5V
100
DHV_, DLV_, DTV_, Output Offset
Temperature Coefficient
+200
-50
µV/°C
V/V
Measured with V
_, V
_,
DHV
DLV
DHV_, DLV_, DTV_, Gain
A
0.960
1.001
V
and V
_ at 0 and 4.5V
DTV
DHV_, DLV_, DTV_, Gain
Temperature Coefficient
ppm/°C
mV
V
_ = 1.5V, 3V (Note 9)
DUT
5
15
2
Linearity Error
Full range (Notes 9, 10)
DHV_ to DLV_ Crosstalk
DLV_ to DHV_ Crosstalk
V
V
_ = 0; V
_ = 200mV, 6.5V
DHV
mV
mV
DLV
DHV
_ = 5V; V
_ = -1.5V, +4.8V
2
DLV
DTV_ to DLV_ and DHV_
Crosstalk
V
V
_ = 3V; V
_ = -1.5V, +6.5V
_ = 0;
DHV
DLV
2
mV
DTV
DHV_ to DTV_ Crosstalk
DLV_ to DTV_ Crosstalk
V
V
_ = 1.5V; V
_ = 1.5V; V
_ = 0; V _ = 1.6V, 3V
DHV
2
2
mV
mV
DTV
DLV
_ = 3V; V _ = 0, 1.4V
DHV DLV
DTV
DHV_, DTV_, DLV_ DC
Power-Supply Rejection Ratio
PSRR
(Note 11)
18
mV/V
Maximum DC Drive Current
DC Output Resistance
I
_
40
49
80
51
1
mA
DUT
R
_
DUT
I
I
I
_ = 30mA (Note 12)
_ = 1mA, 8mA
50
0.5
Ω
DUT
DUT
DUT
DC Output Resistance Variation
_R
_
DUT
Ω
_ = 1mA, 8mA, 15mA, 40mA
0.75
1.5
DYNAMIC OUTPUT CHARACTERISTICS (Z = 50Ω)
L
AC Drive Current
80
mA
mV
V
V
V
_ = 0, V
_ = 0, V
_ = 0, V
_ = 0.1V
_ = 1V
_ = 3V
15
22
DLV
DLV
DLV
DHV
DHV
DHV
Drive-Mode Overshoot
110
210
130
370
4
_______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
4
MAX
11
UNITS
V
V
V
_ = 0, V
_ = 0, V
_ = 0, V
_ = 0.1V
_ = 1V
_ = 3V
DLV
DLV
DLV
DHV
DHV
DHV
Drive-Mode Undershoot
mV
20
30
65
185
V
= 1.0V
= t = 250ps
F
,
,
DUT_
P-P
t
R
60
0
150
10% to 90%
Term-Mode Overshoot
(Note 13)
mV
V
= 3.0V
DUT_
P-P
t
R
= t = 500ps
F
10% to 90%
_ = 1V, V _ = 0
DLV
V
V
V
V
_ = V
180
180
100
100
4
250
250
DHV
DTV
Term-Mode Spike
mV
mV
_ = V
_ = 0, V
_ = 1V
DHV
DLV
DLV
DLV
DTV
_ = -1.0V, V _ = 0
DHV
High-Impedance Mode Spike
_ = 0, V
_ = 1V
DHV
Settling Time to within 25mV
Settling Time to within 5mV
3V step (Note 14)
3V step (Note 14)
ns
ns
40
TIMING CHARACTERISTICS (Z = 50Ω) (Note 15)
L
Prop Delay, Data to Output
Prop Delay Match, t vs. t
t
1.5
1.7
40
2.0
80
ns
ps
PDD
3V
P-P
LH
HL
Prop Delay Match, Drivers within
Package
(Note 16)
40
ps
Prop Delay Temperature
Coefficient
+1.6
70
ps/°C
MAX9969_DCCQ
0.2V , 40MHz,
P-P
0.6ns to 24.4ns pulse
width, relative to
12.5ns pulse width
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
25
70
50
50
60
MAX9969_DCCQ
1V , 40MHz, 0.6ns
P-P
to 24.4ns pulse width,
relative to 12.5ns
pulse width
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
25
Prop Delay Change vs.
Pulse Width
ps
MAX9969_DCCQ
80
3V , 40MHz, 0.9ns
P-P
to 24.1ns pulse width,
relative to 12.5ns
pulse width
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
35
MAX9969_DCCQ
100
5V , Z = 500Ω,
P-P
L
40MHz, 1.4ns to
23.6ns pulse width,
relative to 12.5ns
pulse width
MAX9969_GCCQ
MAX9969_LCCQ
MAX9969_RCCQ
100
_______________________________________________________________________________________
5
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
_ = 1V, V _ = 0 to 6V
MIN
TYP
MAX
UNITS
Prop Delay Change vs.
Common-Mode Voltage
V
V
V
_ - V
50
75
ps
DHV
DHV
DHV
DLV
DHV
Prop Delay,
Drive to High Impedance
t
t
_ = 1.0V, V
_ = 1.0V, V
_ = -1.0V, V
_ = -1.0V, V
_ = 0
_ = 0
2.0
3.0
2.3
3.4
2.6
3.9
ns
ns
ns
PDDZ
PDZD
DLV
DTV
Prop Delay,
High Impedance to Drive
DLV
DTV
Prop Delay Match,
-1.3
-1.1
-0.9
t
vs. t
PDZD
PDDZ
Prop Delay Match, t
vs. t
0.4
1.7
2.0
0.5
0.1
0.6
2.0
2.3
0.3
0.3
0.8
2.3
2.7
0.1
0.5
ns
ns
ns
ns
ns
PDDZ
LH
Prop Delay, Drive to Term
Prop Delay, Term to Drive
t
t
V
V
_ = 3V, V
_ = 3V, V
_ = 0, V
_ = 0, V
_ = 1.5V
_ = 1.5V
PDDT
PDTD
DHV
DLV
DTV
DHV
DLV
DTV
Prop Delay Match, t
vs. t
PDTD
PDDT
Prop Delay Match, t
vs. t
LH
PDDT
DYNAMIC PERFORMANCE (Z = 50Ω)
L
0.2V , 10% to 90%
300
330
500
800
350
390
650
1000
50
400
450
P-P
1V , 10% to 90%
P-P
Rise and Fall Time
t , t
ps
R
F
3V , 10% to 90%
P-P
750
5V , Z = 500Ω, 10% to 90%
1200
P-P
L
Rise and Fall Time Match
t
R
vs. t
3V , 10% to 90%
P-P
ps
%
F
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
SC1 = 0, SC0 = 1 Slew Rate
63
40
18
70
47
25
77
55
32
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
SC1 = 1, SC0 = 0 Slew Rate
SC1 = 1, SC0 = 1 Slew Rate
%
%
Percent of full speed (SC0 = SC1 = 0),
3V , 20% to 80%
P-P
0.2V
550
550
P-P
1V
3V
630
P-P
P-P
Minimum Pulse Width
Data Rate
(Note 17)
ps
850
1000
5V , Z = 500Ω
1300
1800
1800
1200
800
P-P
L
0.2V
P-P
1V
3V
P-P
P-P
(Note 18)
(Note 19)
Mbps
5V , Z = 500Ω
P-P
L
Dynamic Crosstalk
12
mV
P-P
V
_ = 3V, V
_ = 0, V _ = 1.5V,
DTV
DHV
DLV
Rise and Fall Time, Drive to Term
t
t
, t
0.6
0.6
1.0
1.0
1.3
1.3
ns
DTR DTF
10% to 90%, Figure 1a (Note 20)
V
_ = 3V, V _ = 0, V _ = 1.5V,
DHV
DLV
DTV
Rise and Fall Time, Term to Drive
, t
ns
TDR TDF
10% to 90%, Figure 1b (Note 20)
6
_______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
COMPARATORS (Note 8)
DC CHARACTERISTICS
Input Voltage Range
Differential Input Voltage
Hysteresis
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
(Note 4)
-1.5
8
+6.5
V
V
IN
V
DIFF
V
0
mV
HYST
MAX9969A
MAX9969B
20
Input Offset Voltage
V
V
V
_ = 1.5V
mV
OS
DUT
100
Input Offset Voltage Temperature
Coefficient
10
µV/°C
mV/V
mV
Common-Mode Rejection Ratio
CMRR
PSRR
_ = -1.5V, +6.5V (Note 21)
0.25
2
3
DUT
V
V
_ = 1.5V, 3V
DUT
DUT
Linearity Error
(Note 10)
_ = -1.5V, +6.5V
10
2
Power-Supply Rejection Ratio
V
_ = 1.5V (Note 11)
0.035
mV/V
DUT
AC CHARACTERISTICS (Note 22)
Term mode, t = t = 150ps
2
3
R
F
Bandwidth
GHz
ps
High-impedance mode
0.65
0.75
MAX9969_LCCQ
500
650
1.6
50
and MAX9969_RCCQ
Minimum Pulse Width
Prop Delay
t
(Note 23)
PW(MIN)
MAX9969_DCCQ
600
1.3
and MAX9969_GCCQ
t
1.0
ns
PDL
Prop Delay Temperature
Coefficient
+1.7
ps/°C
Prop Delay Match, High/Low vs.
Low/High
10
50
80
40
ps
ps
ps
ps
Prop Delay Match High vs. Low
Comparator
Prop Delay Match, Comparators
within Package
(Note 16)
= V
Prop Delay Dispersion vs.
Common-Mode Input
V
= -1.4V to +6.4V
CHV_
CLV_
CLV_
60
60
(Note 24)
V
V
= V
= 0.1V to 0.9V,
CHV_
_ = 1V , t = t = 250ps,
40
DUT
P-P
R
F
10% to 90% relative to timing at 50% point
Prop Delay Dispersion vs.
Overdrive
ps
V
V
= V
= 40mV to 160mV,
CLV_
CHV_
_ = 0.2V , t = t = 150ps,
40
30
60
50
DUT
P-P
R
F
10% to 90% relative to timing at 50% point
Prop Delay Dispersion vs.
Pulse Width
0.6ns to 24.4ns pulse width, relative to
12.5ns pulse width
ps
_______________________________________________________________________________________
7
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Prop Delay Dispersion vs.
Slew Rate
0.5V/ns to 6V/ns slew rate,
relative to 4V/ns slew rate
30
60
ps
V
_ = 1.0V , t = t = 250ps,
DUT P-P R F
10% to 90% relative to timing at 50% point,
term mode
40
60
V
_ = 1.0V , t = t = 250ps,
DUT P-P R F
Waveform Tracking 10% to 90%
10% to 90% relative to timing at 50% point,
high-impedance mode
ps
190
150
250
200
V
_ = 3V , t = t = 500ps,
DUT P-P R F
10% to 90% relative to timing at 50% point,
high-impedance mode
Term mode
6
5
DUT_ Slew-Rate Tracking
V/ns
High-impedance mode
LOGIC OUTPUTS (CH_, NCH_, CL_, NCL_)
V
V
_ Voltage Range
_ Current
V
_
VCCO
0
3.5
V
CCO
CCO
I
_
32
mA
V
VCCO
Output Low Voltage Compliance
Output High Current
Set by I , R
, and V
_
CCO
-0.5
OL TERM
I
MAX9969_DCCQ, MAX9969_GCCQ
MAX9969_DCCQ, MAX9969_GCCQ
MAX9969_DCCQ, MAX9969_GCCQ
-0.1
7.6
+0.3
8.4
mA
mA
mA
OH
Output Low Current
I
8
OL
Output Current Swing
I
_ = I
_ = I _ = I
_ = 0,
V
V
V
CCO_
CH
NCH
CL
NCL
CCO_
CCO_
Output High Voltage
Output Low Voltage
Output Voltage Swing
V
V
V
OH
MAX9969_LCCQ, MAX9969_RCCQ
- 0.05 - 0.005 + 0.01
I
_ = I _ = I _ = I _ = 0,
V
CCO_
- 0.4
CH
NCH
CL
NCL
V
OL
MAX9969_LCCQ, MAX9969_RCCQ
I
_ = I _ = I _ = I _ = 0,
CH
NCH
CL
NCL
380
48
400
420
52
mV
MAX9969_LCCQ, MAX9969_RCCQ
Single-ended measurement from V
CH_, NCH_, CL_, NCL_, MAX9969_LCCQ,
MAX9969_RCCQ
_ to
CCO
Output Termination Resistor
R
Ω
TERM
MAX9969_DCCQ,
MAX9969_GCCQ,
240
190
R
TERM
= 50Ω at end of line
Differential Rise and Fall Times
t , t
20% to 80%
ps
R
F
MAX9969_LCCQ,
MAX9969_RCCQ
230
CLAMPS
High Clamp Input Voltage Range
Low Clamp Input Voltage Range
V
_
0
+7.5
+5.0
100
V
V
CPH
V
_
-2.5
CPL
At DUT_ with I
At DUT_ with I
_ = 1mA, V
_ = 0
DUT
CPHV
Clamp Offset Voltage
V
mV
OS
_ = -1mA, V
DUT
_ = 0
100
CPLV
8
_______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Offset-Voltage Temperature
Coefficient
250
µV/°C
I
V
_ = 1mA,
DUT
10
10
_ = 0
CPHV
Clamp Power-Supply
Rejection Ratio
PSRR
(Note 11)
mV/V
I
_ = -1mA,
DUT
V
_ = 0
CPLV
Voltage Gain
A
0.960
1.005
V/V
V
Voltage-Gain Temperature
Coefficient
-30
10
ppm/°C
I
V
_ = 1mA, V
_ = -1.5V,
DUT
CPLV
_ = 0 to 6.5V
CPHV
Clamp Linearity
mV
I
_ = -1mA, V
_ = 6.5V,
CPHV
DUT
10
V
_ = -1.5V to +5V
CPLV
V
V
_ = 0, V
_ = 6.5V
_ = -1.5V,
CPLV
CPHV
40
-80
50
80
-40
55
DUT
Short-Circuit Output Current
Clamp DC Impedance
I
_
mA
Ω
SCDUT
V
V
_ = 6.5V, V
_ = -1.5V
_ = 5V,
CPHV
CPLV
DUT
V
_ = 3V, V
_ = 5mA and 15mA
_ = 0,
CPHV
CPLV
R
OUT
I
DUT
V
= 2.5V; V
= 10mA, 20mA, 30mA
= -1.5V;
CPLV_
CPHV_
1.5
1.5
I
DUT_
Clamp DC Impedance Variation
Ω
V
= 6.5V; V
= -10mA, -20mA, -30mA
= 2.5V;
CPLV_
CPHV_
I
DUT_
ACTIVE LOAD (V
_ = 1.5V, R > 1MΩ, driver in high-impedance mode unless otherwise noted)
COM L
COM_ Voltage Range
Differential Voltage Range
COM_ Offset Voltage
V
_
-1
+6
+7.5
100
V
V
COM
V
- V
-7.5
DUT_
COM_
Vos
I
= I
= 20mA
mV
SOURCE
SINK
Offset-Voltage Temperature
Coefficient
+100
µV/°C
V/V
COM_ Voltage Gain
A
V
_ = 0, 4.5V; I
= I = 20mA
SINK
0.98
1.00
V
COM
SOURCE
Voltage-Gain Temperature
Coefficient
-10
3
ppm/°C
V
_ = -1V, +6V;
COM
COM_ Linearity Error
15
10
mV
I
= I
= 20mA
SOURCE
SINK
COM_ Output Voltage
Power-Supply Rejection Ratio
V
_ = 2.5V,
COM
PSRR
mV/V
I
= I
= 20mA
SOURCE SINK
_______________________________________________________________________________________
9
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
=
SOURCE
V
V
V
_ = 3V, 6.5V with
DUT
30
= 35mA
SINK
Output Resistance,
Sink or Source
_ = -1V and
COM
Ro
kΩ
_ = -1.5V, +2V
DUT
I
I
=
SOURCE
500
with V
_ = 6V
COM
= 1mA
SINK
I
I
V
_ = 33.25mA,
DUT
Output Resistance,
Linear Region
= I
= 35mA,
Ro
11
15
Ω
SOURCE
SINK
_ = 2.5V verfied by deadband test
COM
Deadband
V
_ = 2.5V, 95% I
COM
to 95% I
700
800
mV
SOURCE
SINK
SOURCE CURRENT (V _ = 4.5V)
DUT
Maximum Source Current
Source Programming Gain
V
V
_ = 3.8V
36
40
mA
LDL
LDL
A
TC
_ = 0.2V, 3V; V
= 0.1V
9.75
10
10.25
mA/V
LDH_
Source Current Offset (Combined
Offset of LDL_ and GS)
I
V
_ = 200mV
-1000
0
µA
OS
LDL
Source-Current Temperature
Coefficient
I
= 35mA
-15
µA/°C
µA/V
SOURCE
I
I
= 25mA
= 35mA
60
84
SOURCE
Source-Current Power-Supply
Rejection Ratio
PSRR
SOURCE
V
_ = 100mV,
LDL
60
1V, 2.25V
Source Current Linearity
(Note 25)
µA
V
_ = 3V
130
LDL
SINK CURRENT (V _ = -1.5V)
DUT
Maximum Sink Current
Sink Programming Gain
V
V
_ = 3.8V
-40
-36
mA
LDH
A
_ = 0.2V, 3V; V
LDH
_ = 0.1V
LDL
-10.25
-10
+8
-9.75
mA/V
TC
Sink-Current Offset (Combined
Offset of LDH_ and GS)
I
V
_ = 200mV
LDH
0
1000
µA
OS
Sink-Current Temperature
Coefficient
I
= 35mA
µA/°C
µA/V
SINK
I
I
= 25mA
= 35mA
60
84
SINK
Sink-Current Power-Supply
Rejection Ratio
PSRR
SINK
V
_ = 100mV,
LDH
60
1V, 2.25V
Sink-Current Linearity
(Note 25)
µA
V
_ = 3V
LDH
130
GROUND SENSE
GS Voltage Range
V
Verified by GS common-mode error test
250
mV
µA
µA
GS
V
V
_ = -1.5V, V
=
250mV,
DUT
LDH
GS
20
_ - V = 0.2V
GS
GS Common-Mode Error
GS Input Bias Current
V
V
_ = +4.5V, V
=
GS
250mV,
DUT
20
25
_ - V = 0.2V
LDL
GS
V
= 0
GS
10 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (Z = 50Ω to GND)
L
I
V
= 10mA,
_ = -1V
SOURCE
3
3.5
3.5
2
4
COM
Enable Time
Disable Time
t
(Note 26)
(Note 26)
ns
EN
I
= 10mA,
_ = 1V
SINK
3
4
V
COM
I
= 10mA,
_ = 1V
SOURCE
1.7
1.7
2.3
2.3
V
COM
t
ns
DIS
I
= 10mA,
_ = -1V
SINK
2
V
COM
To 10%
To 1.5%
To 10%
To 1.5%
15
50
3
I
= I
=
=
SOURCE
SINK
1mA (Note 27)
Current Settling Time on
Commutation
ns
5
I
= I
SOURCE
SINK
20mA (Note 27)
15
Spike During Enable/Disable
Transition
I
= I
= 35mA, V _ = 0
COM
200
300
mV
SOURCE
SINK
Note 1: All minimum and maximum DC and driver 3V rise- and fall-time test limits are 100% production tested. All other test limits
are guaranteed by design. Tests are performed at nominal supply voltages, unless otherwise noted.
Note 2: Total for dual device at worst-case setting.
Note 3: Does not include above ground internal dissipation of the comparator outputs. Additional power dissipation is typically
(32mA x V
)
VCCO_
Note 4: Externally forced voltages may exceed this range provided that the Absolute Maximum Ratings are not exceeded.
Note 5: Transition time from LLEAK being asserted to leakage current dropping below specified limits.
Note 6: Based on simulation results only.
Note 7: Transition time from LLEAK being deasserted to output returning to normal operating mode.
Note 8: With the exception of offset and gain/CMRR tests, reference input values are calibrated for offset and gain.
Note 9: Specifications measured at the endpoints of the full range. Full range is -1.3V ≤ V
≤ +6.5V, -1.5V ≤ V
≤ +6.3V,
DLV_
DHV_
-1.5V ≤ V
≤ +6.5V.
DTV_
Note 10: Relative to straight line between 0 and 4.5V.
Note 11: Change in offset voltage with power supplies independently set to their minimum and maximum values.
Note 12: Nominal target value is 50Ω. Contact factory for alternate trim selections within the 45Ω to 51Ω range.
Note 13: V
= midpoint of voltage swing, R = 50Ω. Measurement is made using the comparator.
S
DTV_
Note 14: Measured from the crossing point of DATA_ inputs to the settling of the driver output.
Note 15: Prop delays are measured from the crossing point of the differential input signals to the 50% point of the expected output
swing. Rise time of the differential inputs DATA_ and RCV_ are 250ps (10% to 90%).
Note 16: Rising edge to rising edge or falling edge to falling edge.
Note 17: Specified amplitude is programmed. At this pulse width, the output reaches at least 90% of its nominal (DC) amplitude. The
pulse width is measured at DATA_.
Note 18: Specified amplitude is programmed. Maximum data rate is specified in transitions per second. A square wave that reaches
at least 90% of its programmed amplitude may be generated at one-half of this frequency.
Note 19: Crosstalk from either driver to the other. Aggressor channel is driving 3V
into a 50Ω load. Victim channel is in term mode
P-P
with V
= +1.5V.
DTV_
Note 20: Indicative of switching speed from DHV_ or DLV_ to DTV_ and DTV_ to DHV_ or DLV_ when V
< V
< V
. If
DHV_
DLV_
DTV_
V
< V
or V
> V
, switching speed is degraded by a factor of approximately 3.
DHV_
DTV_
DLV_
DTV_
Note 21: Change in offset voltage over the input range.
______________________________________________________________________________________ 11
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
ELECTRICAL CHARACTERISTICS (continued)
(V
= +9.75V, V = -4.75V, V
= +2.5V, SC1 = SC0 = 0, V
= +7.2V, V
= -2.2V, V _ = V _ = 0, V = 0, T =
LDH LDL GS J
CC
EE
CCO_
CPHV_
CPLV_
+85°C, unless otherwise noted. All temperature coefficients are measured at T = +60°C to +100°C, unless otherwise noted.) (Note 1)
J
Note 22: Unless otherwise noted, all propagation delays are measured at 40MHz, V
= 0 to +1V, V
= V
= +0.5V, t = t
CLV_ R F
DUT_
CHV_
= 250ps, Z = 50Ω, driver in term mode with V
= +0.5V. Comparator outputs are terminated with 50Ω to 1.25V and
S
DTV_
V
_ = 2.5V. Measured from V
crossing calibrated CHV_/CLV_ threshold to crossing point of differential outputs.
CCO
DUT_
Note 23: At this pulse width, the output reaches at least 90% of its DC voltage swing. The pulse width is measured at the crossing
points of the differential outputs.
Note 24: V
= 200mV . Overdrive = 100mV.
DUT_
P-P
Note 25: Relative to segmented interpolations between 200mV, 2V, 2.5V, and 3.5V.
Note 26: Measured from crossing of LDEN_ inputs to the 50% point of the output current change.
Note 27: V
= 1V, R = 50Ω, driving voltage = 1.55V to 0.45V transition and 0.45V to 1.55V transition (at 1mA) or +2.5V to -0.5V
COM
S
transition and -0.5V to +2.5V transition (at 20mA). Settling time is measured from V
_ = 1V to I
/I
settling with-
DUT
SINK SOURCE
in specified tolerance.
t
DTF
90%
DHV_
DLV_
10%
90%
DTV_
10%
t
DTR
(A) DRIVE-TO-TERM RISE AND FALL TIME
t
TDR
90%
DHV_
10%
90%
DTV_
DLV_
TDF
10%
t
(B) TERM-TO-DRIVE RISE AND FALL TIME
Figure 1. Drive-to-Term and Term-to-Drive Rise and Fall Times
12 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
DRIVER LARGE-SIGNAL RESPONSE
DRIVER SMALL-SIGNAL RESPONSE
DRIVER LARGE-SIGNAL RESPONSE
INTO 500Ω
V
= 0
V
= 0
V
= 0
DLV_
R = 50Ω
L
DLV_
R = 50Ω
L
DLV_
R = 500Ω
L
V
= 5V
= 3V
= 1V
V
= 500mV
DHV_
V
= 5V
= 3V
= 1V
DHV_
C = 0.1pF
DHV_
L
V
V
DHV_
DHV_
DHV_
V
= 200mV
= 100mV
DHV_
DHV_
V
V
V
DHV_
0
0
0
t = 2.0ns/div
t = 2.0ns/div
t = 2.0ns/div
DRIVER 1V 600Mbps
SIGNAL RESPONSE
DRIVER 1V 1800Mbps
SIGNAL RESPONSE
DRIVER 3V 400Mbps
SIGNAL RESPONSE
V
= 0, V
= 1V, R = 50Ω
V
= 0, V
= 1V, R = 50Ω
V
V
= 0
DLV_
DHV_
L
DLV_
DHV_
L
DLV_
DLV_
L
= 3V
R = 50Ω
0
0
0
t = 500ps/div
t = 200ps/div
t = 1ns/div
DRIVER 3V TRAILING-EDGE TIMING
ERROR vs. PULSE WIDTH
DRIVER 3V 1200Mbps
SIGNAL RESPONSE
DRIVER DYNAMIC
CURRENT-LIMIT RESPONSE
40
20
POSITIVE PULSE
DRIVER SOURCING
DRIVER SINKING
0
-20
-40
-60
-80
-100
NEGATIVE PULSE
0
V
V
= 0
DLV_
DHV_
L
= 3V
NORMALIZED TO PW = 12.5ns
0
R = 50Ω
PERIOD = 25ns, V
= +3V, V
= 0
DHV_
DLV_
20
R = 10Ω
L
0
5
10
15
25
t = 250ps/div
t = 50ns/div
PULSE WIDTH (ns)
______________________________________________________________________________________ 13
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DRIVER 1V TRAILING-EDGE TIMING
DRIVER TIME DELAY
vs. COMMON-MODE VOLTAGE
ERROR vs. PULSE WIDTH
DRIVE-TO-TERM TRANSITION
30
50
40
30
20
10
0
20
DHV_ TO DTV_
POSITIVE PULSE
10
RISING EDGE
0
FALLING EDGE
-10
NEGATIVE PULSE
DLV_ TO DTV_
-20
-10
-20
NORMALIZED TO PW = 12.5ns
0
PERIOD = 25ns, V
= +1V, V
= 0
NORMALIZED AT V = 1.5V
CM
R = 50Ω
L
DHV_
DLV_
20
-30
0
5
10
15
25
t = 2.0ns/div
-1
0
1
2
3
4
5
6
PULSE WIDTH (ns)
COMMON-MODE VOLTAGE (V)
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
DRIVE TO
HIGH-IMPEDANCE TRANSITION
8
8
6
DUT_ = DHV_
DUT_ = DLV_
V
DLV_
V
DTV_
= -1.5V
= 0
V
V
= +6.5V
= 0
DLV_
DTV_
6
4
DHV_ TO HIGH IMPEDANCE
4
2
2
0
0
0
-2
-4
-6
-8
-2
-4
-6
-8
DLV_ TO HIGH IMPEDANCE
R = 50Ω
L
t = 2.0ns/div
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
DUT_
DUT_
DRIVER LINEARITY ERROR
vs. OUTPUT VOLTAGE
CROSSTALK TO DUT_ FROM
DLV_ WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM
DHV_ WITH DUT_ = DLV_
8
6
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
DUT_ = DTV_
V
V
= 5V
= 1.5V
V
V
= 0
= 1.5V
DHV_
DTV_
DLV_
DTV_
V
DLV_
V
DHV_
= -1.5V
= +6.5V
4
2
0
-2
-4
-6
-8
-0.5
-1.0
-1.5
-2.0
-0.5
-1.0
-1.5
-2.0
NORMALIZED AT V
= 0
NORMALIZED AT V
= 5V
DLV_
DHV_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
V
DHV_
DUT_
DLV_
14 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
CROSSTALK TO DUT_ FROM
DTV_ WITH DUT_ = DHV_
CROSSTALK TO DUT_ FROM
DTV_ WITH DUT_ = DLV_
CROSSTALK TO DUT_ FROM
DLV_ WITH DUT_ = DTV_
1.0
0.8
1.0
0.8
1.0
0.8
V
V
= 3V
= 0
V
V
= 0
= 6.5V
V
V
= 1.5V
= 6.5V
DHV_
DLV_
DLV_
DHV_
DTV_
DHV_
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
NORMALIZED AT V
= 1.5V
NORMALIZED AT V
= 1.5V
NORMALIZED AT V
= 0
DTV_
DTV_
DLV_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
V
V
DLV_
DTV_
DTV_
CROSSTALK TO DUT_ FROM
DHV_ WITH DUT_ = DTV_
DRIVER GAIN vs. TEMPERATURE
DRIVER OFFSET vs. TEMPERATURE
1.0
0.8
1.0015
1.0010
1.0005
1.0000
0.9995
0.9990
0.9985
5
V
V
= 1.5V
DTV_
DLV_
4
3
= -1.5V
0.6
0.4
2
0.2
1
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
-4
-5
NORMALIZED AT T = +85°C
NORMALIZED AT V
= 3V
J
DHV_
NORMALIZED AT T = +85°C
J
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
60 65 70 75 80 85 90 95 100
60 65 70 75 80 85 90 95 100
V
TEMPERATURE (°C)
TEMPERATURE (°C)
DHV_
COMPARATOR OFFSET
vs. COMMON-MODE VOLTAGE
COMPARATOR TIMING VARIATION
vs. COMMON-MODE VOLTAGE
COMPARATOR WAVEFORM TRACKING
2.0
1.5
1.0
0.5
0
10
0
30
25
20
15
10
5
OTHER COMPARATOR REFERENCE = 2.5V
-10
-20
-30
-40
-50
-60
-70
RISING EDGE
FALLING EDGE
FALLING EDGE
-0.5
-1.0
-1.5
-2.0
0
NORMALIZED AT 50% REFERENCE LEVEL
RISING EDGE
-5
-10
NORMALIZED AT V = 1.5V
CM
V
= 0 TO 1V PULSE
NORMALIZED AT V = 1.5V
CM
DUT_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
0
20
40
60
80
100
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
COMMON-MODE VOLTAGE (V)
REFERENCE LEVEL (%)
______________________________________________________________________________________ 15
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
COMPARATOR TRAILING-EDGE TIMING
VARIATION vs. PULSE WIDTH
COMPARATOR TIMING VARIATION
vs. INPUT SLEW RATE
COMPARATOR DIFFERENTIAL
OUTPUT RESPONSE
10
20
15
10
5
LOW PULSE
5
0
-5
HIGH PULSE
-10
V
FALLING
DUT_
0
0
-15
-20
-25
-5
-10
-15
-20
-25
V
RISING
DUT_
MAX9969_LCCQ
MAX9969_RCCQ
-30
NORMALIZED AT PW = 12.5ns
NORMALIZED AT SR = 4V/ns
-35
0
5
10
15
20
25
0
1
2
3
4
5
6
7
t = 2ns/div
= 0 TO 3V PULSE
PULSE WIDTH (ns)
SLEW RATE (V/ns)
V
V
DUT_
CHV_
= V
= 1.5V
CLV_
EXTERNAL LOAD = 50Ω
COMPARATOR OFFSET
vs. TEMPERATURE
COMPARATOR RESPONSE TO
HIGH SLEW RATE OVERDRIVE
CLAMP RESPONSE AT SOURCE
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
0
NORMALIZED AT T = +85°C
J
60 65 70 75 80 85 90 95 100
t = 10ns/div
t = 2ns/div
TEMPERATURE (°C)
V
R
V
= 0 TO 1V SQUARE WAVE
INPUT SLEW RATE = 4V/ns
HIGH IMPEDANCE
DUT_
= 10Ω
S
= -0.1V, V
= +1.1V
CPLV_
CPHV_
ACTIVE-LOAD CURRENT
vs. LOAD VOLTAGE
ACTIVE-LOAD COMMUTATION
SIGNAL RESPONSE
ACTIVE-LOAD ENABLE
SIGNAL RESPONSE
50
40
V
V
V
= 2.5V
= 3.5V
= 3.5V
COM_
LDH_
LDL_
V
V
= 2V
= 2V
V
V
= 2V
= 2V
LDH_
LDL_
LDH_
LDL_
30
20
I
LDH_
10
0
0
0
-10
-20
-30
-40
-50
I
LDL_
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
(V)
t = 5ns/div
t = 5ns/div
V
DUT_
16 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
ACTIVE-LOAD LINEARITY
ERROR I vs. V
ACTIVE-LOAD LINEARITY
ERROR I vs. V
HIGH-IMPEDANCE CURRENT
vs. DUT_ VOLTAGE
DUT_
CALIBRATION POINTS AT
LDH_
DUT_
CALIBRATION POINTS AT
LDL_
50
40
50
40
-0.30
-0.35
-0.40
-0.45
-0.50
-0.55
-0.60
-0.65
-0.70
-0.75
200mV, 2.0V, 2.5V, AND 3.5V
200mV, 2.0V, 2.5V, AND 3.5V
V
V
= 1.5V, V
= 0
V
V
= 1.5V, V
= 0
COM_
DUT
LDL_
COM_
DUT
LDH_
30
30
= 0
= 3V
20
20
10
10
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
0.01
0.1
1
10
0.01
0.1
1
10
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
V
(V)
V
(V)
V
(V)
DUT_
LDH_
LDL_
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
CLAMP CURRENT
vs. DIFFERENCE VOLTAGE
LOW-LEAKAGE CURRENT
vs. DUT_ VOLTAGE
1000
900
800
700
600
500
400
300
200
100
0
100
0
V
V
= 3V
= 0
4
DUT_
CPLV
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
2
0
-2
-4
-6
-8
V
V
= 0
CPHV_
DUT_
= 3V
-10
-100
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
(V)
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1
(V)
0
V
V
V
CPLV_
DUT_
CPHV_
DRIVE 1V TO
LOW-LEAKAGE TRANSITION
LOW-LEAKAGE TO
DRIVE 1V TRANSITION
DRIVER REFERENCE CURRENT
vs. DRIVER REFERENCE VOLTAGE
0.930
0.905
0.880
0.855
0.830
0.805
0.780
0.755
0.730
R = 100kΩ
L
L
C = 10pF
DHV_
DLV_
DTV_
R = 100kΩ
L
0
0
L
C = 10pF
0
t = 2µs/div
0
t = 50ns/div
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
INPUT VOLTAGE (V)
______________________________________________________________________________________ 17
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
COMPARATOR REFERENCE CURRENT
INPUT CURRENT
vs. INPUT VOLTAGE, CPHV_
INPUT CURRENT
vs. INPUT VOLTAGE, CPLV_
vs. INPUT VOLTAGE
100
625
600
575
550
525
500
475
450
-500
-550
-600
-650
-700
-750
-800
-850
V
= 6.5V
V
= -2.2V
CPLV_
V
= 7.2V
DUT_
CPHV_
CLV_
0
-100
-200
-300
-400
-500
CHV_
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
INPUT VOLTAGE (V)
0
1.5
3.0
V
4.5
(V)
6.0
7.5
-2.5
-1.0
0.5
V
2.0
(V)
3.5
5.0
CPHV_
CPLV_
LOAD REFERENCE INPUT CURRENT
vs. INPUT VOLTAGE
INPUT CURRENT
vs. INPUT VOLTAGE, COM_
200
100
0.90
0.88
0.86
0.84
0.82
0.80
0.78
0.76
0.74
0
LDH_
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
LDL_
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
INPUT VOLTAGE (V)
-1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5
(V)
V
COM_
18 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT I vs. V
CC
SUPPLY CURRENT I vs. V
EE
CC
EE
320
300
280
260
240
220
200
240
220
200
180
160
140
120
C
C
A
A
B
D
D
B
R = 10kΩ, C = 0.05pF, V = -4.75V
R = 10kΩ, C = 0.5pF, V = 9.75V
L
L
EE
L
L
CC
9.5
9.7
9.9
10.1
10.3
10.5
-5.25
-5.15
-5.05
-4.95
-4.85
-4.75
V
(V)
V (V)
EE
CC
A: V
V
= V
DTV_
= V
CLV_
= V
LDL_
= 1.5V, V
= 3V, V
= 0
A: V
V
= V
DTV_
= V
CLV_
= V
LDL_
= 1.5V, V
= 3V, V
= 0
DUT_
CHV_
LDH_
DHV_
= 7.2V, V
DLV_
DUT_
CHV_
LDH_
DHV_
= 7.2V, V
DLV_
= 0, V
= -2.2V
= 0, V
= -2.2V
CPHV_
CPLV_
CPHV_
CPLV_
V
= 0, I
= I
= 0
V
= 0, I
= I
= 0
SOURCE SINK
SOURCE SINK
B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z
AND LOAD ENABLED
B: SAME AS A EXCEPT DRIVER DISABLED HIGH-Z
AND LOAD ENABLED
C: SAME AS B EXCEPT I
= I
= 35mA,
C: SAME AS B EXCEPT I
= I
= 35mA,
SOURCE SINK
= 1.5V, RL = 0
SOURCE SINK
V
V
= -1V, R = 0
COM_ L
COM_
D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED
D: SAME AS C EXCEPT LOW-LEAKAGE MODE ASSERTED
I
vs. TEMPERATURE
I
vs. TEMPERATURE
EE
CC
234
233
232
231
230
229
228
165
164
163
162
161
160
V
V
V
= V
DTV_
= V
CLV_
= V
LDL_
= 1.5V, V
= 0, V
= 3V, V
= 0
V
V
V
= V
DTV_
= V
CLV_
= V
LDL_
= 1.5V, V
= 0, V
= 3V, V
= 0
DUT_
CHV_
LDH_
DHV_
DLV_
DUT_
CHV_
LDH_
DHV_
DLV_
= 7.2V, V
= -2.2V
= 7.2V, V
= -2.2V
CHV_
CPLV_
CHV_
CPLV_
= 0, V = 9.75, V = -5.25
= 0, V = 9.75, V = -5.25
CC
EE
CC
EE
60
70
80
90
100
110
60
70
80
90
100
110
TEMPERATURE (°C)
TEMPERATURE (°C)
______________________________________________________________________________________ 19
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Pin Description
PIN
NAME
FUNCTION
1
TEMP
Temperature Monitor Output
Negative Power-Supply Input
2, 9, 12, 14,
17, 24, 35,
45, 46, 60,
80, 81, 91
V
EE
3, 5, 10, 16,
21, 23, 25,
34, 43, 44,
82, 83, 92
GND
Ground Connection
4, 11, 15, 22,
33, 41, 42,
V
Positive Power-Supply Input
CC
66, 84, 85, 93
6, 8, 18,
20, 50, 76
N.C.
No Connection. Do not connect.
7
DUT1
GS
Channel 1 DUT Input/Output. Combined I/O for driver, comparator, clamp, and load.
Ground Sense. GS is the ground reference for LDH_ and LDL_.
Channel 2 DUT Input/Output. Combined I/O for driver, comparator, clamp, and load.
Channel 2 Low-Comparator Reference Input
13
19
26
27
28
29
30
31
32
36
37
DUT2
CLV2
CHV2
DLV2
DTV2
DHV2
CPLV2
CPHV2
NCH2
CH2
Channel 2 High-Comparator Reference Input
Channel 2 Driver-Low Reference Input
Channel 2 Driver-Termination Reference Input
Channel 2 Driver-High Reference Input
Channel 2 Low-Clamp Reference Input
Channel 2 High-Clamp Reference Input
Channel 2 High-Comparator Output. Differential output of channel 2 high comparator.
Channel 2 Collector Voltage Input. Voltage input for channel 2 comparator output termination
resistors. Provides pullup voltage and current for the output termination resistors. Not internally
connected for versions without internal termination resistors.
38
V
CCO2
39
40
47
NCL2
CL2
Channel 2 Comparator Low Output. Differential output of channel 2 low comparator.
Channel 2 Active-Load Commutation-Voltage Reference Input
COM2
20 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Pin Description (continued)
PIN
48
NAME
LDL2
FUNCTION
Channel 2 Active-Load Source-Current Reference Input
Channel 2 Active-Load Sink-Current Reference Input
49
LDH2
Channel 2 Data-Termination Voltage Input. Termination voltage input for the DATA2 and NDATA2
differential inputs. Not internally connected on versions without internal termination resistors.
51
TDATA2
Channel 2 Multiplexer Control Inputs. Differential controls DATA2 and NDATA2 select driver 2’s
input from DHV2 or DLV2. Drive DATA2 above NDATA2 to select DHV2. Drive NDATA2 above
DATA2 to select DLV2.
52
53
NDATA2
DATA2
Channel 2 RCV Termination Voltage Input. Termination voltage input for the RCV2 and NRCV2
differential inputs. Not internally connected on versions without internal termination resistors.
54
TRCV2
Channel 2 Multiplexer Control Inputs. Differential controls RCV2 and NRCV2 place channel 2 in
receive mode. Drive RCV2 above NRCV2 to place channel 2 into receive mode. Drive NRCV2
above RCV2 to place channel 2 into drive mode.
55
56
NRCV2
RCV2
Channel 2 Load-Enable Termination Voltage Input. Termination voltage input for the LDEN2 and
NLDEN2 differential inputs. Not internally connected on versions without internal termination resistors.
57
TLDEN2
Channel 2 Multiplexer Control Inputs. Differential controls LDEN2 and NLDEN2 enable/disable the
active load. Drive LDEN2 above NLDEN2 to enable the channel 2 active load. Drive NLDEN2
above LDEN2 to disable the channel 2 active load.
58
59
NLDEN2
LDEN2
61
62
RST
CS
Reset Input. Asynchronous reset input for the serial register. RST is active low.
Chip-Select Input. Serial port activation input. CS is active low.
Single-Ended Logic Threshold. Leave THR unconnected to set the threshold to +1.25V or force
THR to a desired threshold voltage.
63
THR
64
65
SCLK
DIN
Serial Clock Input. Clock for serial port.
Data Input. Serial port data input.
Channel 1 Multiplexer Control Inputs. Differential controls LDEN1 and NLDEN1 enable/disable the
active load. Drive LDEN1 above NLDEN1 to enable the channel 1 active load. Drive NLDEN1
above LDEN1 to disable the channel 1 active load.
67
68
LDEN1
NLDEN1
Channel 1 Load-Enable Termination Voltage Input. Termination voltage input for the LDEN1 and
NLDEN1 differential inputs. Not internally connected on versions without internal termination
resistors.
69
TLDEN1
______________________________________________________________________________________ 21
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Pin Description (continued)
PIN
NAME
FUNCTION
Channel 1 Multiplexer Control Inputs. Differential controls RCV1 and NRCV1 place channel 1 in
receive mode. Drive RCV1 above NRCV1 to place channel 1 into receive mode. Drive NRCV1
above RCV1 to place channel 1 into drive mode.
70
RCV1
71
72
NRCV1
TRCV1
Channel 1 RCV Termination Voltage Input. Termination voltage input for the RCV1 and NRCV1
differential inputs. Not internally connected on versions without internal termination resistors.
Channel 1 Multiplexer Control Inputs. Differential controls DATA1 and NDATA1 select driver 1’s
input from DHV1 or DLV1. Drive DATA1 above NDATA1 to select DHV1. Drive NDATA1 above
DATA1 to select DLV1.
73
74
DATA1
NDATA1
Channel 1 Data-Termination Voltage Input. Termination voltage input for the DATA1 and NDATA1
differential inputs. Not internally connected on versions without internal termination resistors.
75
TDATA1
77
78
79
86
87
LDH1
LDL1
COM1
CL1
Channel 1 Active-Load Sink-Current Reference Input
Channel 1 Active-Load Source-Current Reference Input
Channel 1 Active-Load Commutation-Voltage Reference Input
Channel 1 Low-Comparator Output. Differential output of channel 1 low comparator.
NCL1
Channel 1 Collector Voltage Input. Voltage input for channel 1 comparator output-termination
resistors. Provides pullup voltage and current for the output-termination resistors. Not internally
connected for versions without internal termination resistors.
88
V
CCO1
89
90
94
95
96
97
98
99
100
CH1
NCH1
CPHV1
CPLV1
DHV1
DTV1
DLV1
CHV1
CLV1
Channel 1 High-Comparator Output. Differential output of channel 1 high comparator.
Channel 1 High-Clamp Reference Input
Channel 1 Low-Clamp Reference Input
Channel 1 Driver-High Reference Input
Channel 1 Driver-Termination Reference Input
Channel 1 Driver-Low Reference Input
Channel 1 High-Comparator Reference Input
Channel 1 Low-Comparator Reference Input
22 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Functional Diagram
CH_ MODE BITS
V
V
CC
SC0
CS
SCLK
DIN
EE
SERIAL INTERFACE IS COMMON
TO BOTH CHANNELS.
MODE BITS INDEPENDENTLY
LATCHED FOR EACH CHANNEL.
SC1
TMSEL
LLEAK
LDDIS
CDIFF
SERIAL INTERFACE
TEMP
GND
RST
THR
DLV_
DHV_
DTV_
0
SLEW-RATE
CONTROL
MULTIPLEXER
BUFFER
50Ω
DUT_
0
1
LLEAK
OPTIONAL R
DATA
2 x 50Ω
SC0 SC1
TDATA_
DATA_
NDATA_
RCV_
MAX9969
HIGH IMPEDANCE
NRCV_
TMSEL
TRCV_
CPHV_
OPTIONAL R
RCV
CLAMPS
2 x 50Ω
FROM DUT_
OTHER CHANNEL
CPLV_
CHV_
0
1
CH_
NCH_
CDIFF
OPTIONAL R
CCO
V
CCO_
4 x 50Ω
COMPARATORS
CL_
NCL_
V
CC
SINK
(HIGH)
CURRENT
CLV_
LDH_
LLEAK
LDDIS
TLDEN_
1
ACTIVE
LOAD
CONTROL
OPTIONAL R
LDEN
2 x 50Ω
ACTIVE
LOAD
LDEN_
NLDEN_
COM_
LDL_
1
SOURCE
(LOW)
CURRENT
GS
V
EE
ONE OF TWO IDENTICAL CHANNELS SHOWN
______________________________________________________________________________________ 23
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
unconnected for 100Ω differential LVDS termination. In
Detailed Description
addition, flexible open-collector outputs with optional
internal pullup resistors are available for the compara-
tors. These features significantly reduce the discrete
component count on the circuit board.
The MAX9969 dual, low-power, high-speed, pin elec-
tronics DCL IC includes, for each channel, a three-level
pin driver, a dual comparator, variable clamps, and an
active load. An additional differential comparator allows
comparisons between the two channels. The driver fea-
tures a -1.5V to +6.5V operating range and high-speed
operation, includes high-impedance and active-termi-
nation (3rd-level drive) modes, and is highly linear even
at low-voltage swings. The dual comparator provides
low dispersion (timing variation) over a wide variety of
input conditions, and differential outputs. The clamps
provide damping of high-speed DUT waveforms when
the device is configured as a high-impedance receiver.
The programmable load supplies up to 35mA of source
and sink current. The load facilitates contact/continuity
testing, at-speed parametric test of IOH and IOL, and
pullup of high-output-impedance devices. The
MAX9969A features tighter matching of offset for the
drivers and the comparators.
A 3-wire, low-voltage CMOS-compatible serial interface
programs the low-leakage, load-disable, slew-rate, dif-
ferential/window comparator and tri-state/terminate
operational configurations of the MAX9969.
Output Driver
The driver input is a high-speed multiplexer that selects
one of three voltage inputs: DHV_, DLV_, or DTV_. This
switching is controlled by high-speed inputs DATA_
and RCV_ and mode-control bit TMSEL (Table 1). A
slew-rate circuit controls the slew rate of the buffer
input. Select to one of four possible slew rates accord-
ing to Table 2. The speed of the internal multiplexer
sets the 100% driver slew rate (see the Driver Large-
Signal Response graph in the Typical Operating
Characteristics).
Optional internal resistors at the high-speed inputs pro-
vide compatibility with LVPECL, LVDS, and GTL inter-
faces. Connect the termination voltage inputs (TDATA_,
TRCV_, TLDEN_) to the appropriate voltage for termi-
nating LV_PECL, GTL, or other logic. Leave the inputs
DUT_ can be toggled at high speed between the buffer
output and high-impedance mode, or it can be placed
into low-leakage mode (Figure 2, Table 1). In high-
impedance mode, the clamps are connected. High-
speed input RCV_ and mode-control bits TMSEL and
HIGH-SPEED
INPUTS
REFERENCE
INPUTS
0
1
DLV_
0
1
MAX9969
0
50Ω
BUFFER
SLEW RATE
DHV_
DTV_
0
DUT_
1
DATA_
RCV_
CPHV_
CPLV_
CLAMPS
COMPARATORS
AND
ACTIVE LOAD
4
MODE
Figure 2. Simplified Driver Channel
24 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Table 1. Driver Logic
Table 3a. Comparator Logic, CDIFF = 0
DUT_ > CHV_ DUT_ > CLV_ CL_, NCL_
CH_, NCH_
INTERNAL
CONTROL
REGISTER
EXTERNAL
CONNECTIONS
DRIVER
OUTPUT
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
DATA
RCV
TMSEL LLEAK
1
0
0
0
X
X
0
0
Drive to DHV_
Drive to DLV_
Table 3b. Comparator Logic, CDIFF = 1
Drive to DTV_
(term mode)
X
1
1
0
DUT1 > DUT2 DUT_ > CLV_
CL_, NCL_
CH_, NCH_
High-impedance mode
(high-Z)
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
X
X
1
X
0
X
0
1
Low-leakage mode
Table 2. Slew-Rate Logic
not desired, set the clamp voltages at least 0.7V out-
side the expected DUT_ voltage range; overvoltage
protection remains active without loading DUT_.
SC1
SC0
DRIVER SLEW RATE (%)
0
0
1
1
0
1
0
1
100
75
Comparators
The MAX9969 provides two independent high-speed
comparators for each channel. Each comparator has
one input connected internally to DUT_ and the other
input connected to either CHV_ or CLV_ (see the
Functional Diagram). Comparator outputs are a logical
result of the input conditions, as indicated in Tables 3a
and 3b.
50
25
LLEAK control the switching. In high-impedance mode,
the bias current at DUT_ is less than 3µA over the 0 to
3V range, while the node maintains its ability to track
high-speed signals. In low-leakage mode, the bias cur-
rent at DUT_ is further reduced to less than 15nA, and
signal tracking slows. See the Low-Leakage Mode,
LLEAK section for more details.
The comparator differential outputs are open-collector
outputs to ease interfacing with a wide variety of logic
families. Versions with and without internal termination
resistors switch an 8mA current source between the
two outputs (Figure 3). The optional termination resis-
The nominal driver output resistance is 50Ω. Contact
the factory for different resistance values within the
45Ω to 51Ω range.
tors connect the outputs to voltage input V
_. For
CCO
CCO
versions without internal termination, leave V
_
Clamps
Configure the voltage clamps (high and low) to limit the
voltage at DUT_ and to suppress reflections when the
channel is configured as a high-impedance receiver.
The clamps behave as diodes connected to the out-
puts of high-current buffers. Internal circuitry compen-
sates for the diode drop at 1mA clamp current. Set the
clamp voltages using the external connections CPHV_
and CPLV_. The clamps are enabled only when the dri-
ver is in high-impedance mode (Figure 2). For transient
suppression, set the clamp voltages to approximately
the minimum and maximum expected DUT_ voltage
range. The optimal clamp voltages are application spe-
cific and must be empirically determined. If clamping is
unconnected and add the required external resistors.
These resistors are typically 50Ω to the pullup voltage
at the receiving end of the output trace. Alternate con-
figurations can be used provided that the Absolute
Maximum Ratings are not exceeded. For versions with
internal termination, connect V
_ to the desired V
CCO
OH
P-P
voltage. Each output provides a nominal 400mV
swing and 50Ω source termination.
The upper comparators are configurable as differential
receivers for LVDS and other differential DUT_ signals.
When mode bit CDIFF is asserted, the upper compara-
tor inputs are routed from the DUT_ outputs for both
channels.
______________________________________________________________________________________ 25
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Table 4. Active Load Programming
FROM DUT_
OTHER CHANNEL
INTERNAL
CONTROL
REGISTER
CDIFF
EXTERNAL
CONNECTIONS
MAX9969
MODE
CH_
CHV_
DUT_
LDEN_
LDDIS LLEAK
Normal operating mode,
load disabled
NCH_
0
0
0
0
0
1Ω
1Ω
Normal operating mode,
load enabled
8mA
8mA
1
V
OPTIONAL
4 x 50Ω
CCO_
X
X
1
X
0
1
Load disabled
Low-leakage mode
V
EE
Low-Leakage Mode, LLEAK section for more detailed
information.
CL_
LDDIS
In some tester configurations, the load enable is driven
with the complement of the driver high-impedance sig-
nal (RCV_), so disabling the driver enables the load
and vice versa. The LDDIS signal allows the load to be
disabled independent of the state of LDEN_ (Table 4).
CLV_
NCL_
Figure 3. Open-Collector Comparator Outputs
GS Input
The GS input allows a single level-setting DAC, such as
the MAX5631 or MAX5734, to program the MAX9969’s
active load, driver, comparator, and clamps. Although
Active Load
The active load consists of linearly programmable,
class AB source and sink current sources, a commuta-
tion buffer, and a diode bridge (see the Functional
Diagram). Analog control inputs LDH_ and LDL_ pro-
gram the sink and source currents, respectively, within
the 0 to 35mA range. Analog reference input COM_
sets the commutation buffer output voltage. The source
and sink naming convention is referenced to the DUT.
Current out of the MAX9969 constitutes sink current
and current into the MAX9969 constitutes source cur-
rent. The class AB loads of the MAX9969 offer substan-
tial efficiency improvement over conventional
active-load circuitry.
all the DAC levels are typically offset by V , the oper-
GS
ation of the MAX9969’s ground-sense input nullifies this
offset with respect to the active-load current. Connect
GS to the ground reference used by the DAC. (V
_ -
LDL
V
V
) sets the source current by +10mA/V. (V
GS
) sets the sink current by -10mA/V.
GS
_ -
LDH
To maintain an 8V range in the presence of GS variations,
DHV_, DLV_, DTV_, CPHV_, CPLV_, and COM_ ranges
are offset by GS. Adequate supply headroom must be
maintained in the presence of GS variations. Ensure:
V
≥ 9.5V + Max(V
)
CC
GS
The programmed source (low) current loads the DUT
V
≤ -4.5V + Min(V
)
GS
EE
when V
_ > V
_. The programmed sink (high)
COM
DUT
Low-Leakage Mode, LLEAK
current loads the DUT when V
_ < V
_.
COM
DUT
Asserting LLEAK through the serial port or with RST
places the MAX9969 into a very low-leakage state (see
the Electrical Characteristics). With LLEAK asserted, the
comparators function at a reduced speed, and the dri-
ver, clamps, and active load are disabled. This mode is
convenient for making IDDQ and PMU measurements
without the need for an output disconnect relay. LLEAK
is programmed independently for each channel.
High-speed differential input LDEN_ and 2 bits of the
control word (LDDIS and LLEAK) control the load
(Table 4). When the load is enabled, the internal source
and sink current sources connect to the diode bridge.
When the load is disabled, the internal current sources
shunt to ground and the top and bottom of the bridge
float (see the Functional Diagram). LLEAK places the
load in low-leakage mode, and overrides LDEN_. See the
26 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
tion. The low-leakage recovery specification in the
Electrical Characteristics table indicates device behav-
SCLK
DIN
CS
ior under this condition.
SHIFT REGISTER
Serial Interface and Device Control
0
1
2
3
4
5
6
7
A CMOS-compatible serial interface controls the
MAX9969 modes (Figure 4 and Table 5). Control data
flow into an 8-bit shift register (MSB first) and are
latched when CS is taken high, as shown in Figure 5.
Latches contain 6 control bits for each channel of the
dual pin driver. Data from the shift register are loaded
to either or both of the latches as determined by bits D6
and D7. When CDIFF = 1, its effect is independent of
bits D6 and D7. The control bits, in conjunction with
external inputs DATA_ and RCV_, manage the features
of each channel, as shown in Tables 1 and 2. RST sets
LLEAK = 1 for both channels, forcing them into low-
leakage mode. All other bits are unaffected. At power-
ENABLE
F/F
F/F
5
7
5
6
Q
D
D
Q
ENABLE
SET
ENABLE
SET
RST
F/F
D
F/F
D
0 - 4
7
0 - 4
6
Q
Q
up, hold RST low until V
and V have stabilized.
EE
CC
ENABLE
ENABLE
Analog control input THR sets the threshold for the
input logic, allowing operation with CMOS logic as low
as 0.9V. Leaving THR unconnected results in a nominal
threshold of 1.25V from an internal reference, providing
compatibility with 2.5V to 3.3V logic.
5
1
1
5
20kΩ
V
= 1.25V
THR
THRINT
LDDIS,
TMSEL,
CDIFF,
LDDIS,
TMSEL,
CDIFF,
LLEAK
LLEAK
SC0, SC1
SC0, SC1
MAX9967 Compatibility
The MAX9969 is pin compatible with the MAX9967 with
minor changes.
MAX9969
CHANNEL 1 MODE BITS
CHANNEL 2 MODE BITS
• No PMU force/sense connection on the MAX9969
• Different common-mode ranges for control inputs
Figure 4. Serial Interface
• MAX9967 comparator outputs additionally support
When DUT_ is driven with a high-speed signal while
LLEAK is asserted, the leakage current momentarily
increases beyond the limits specified for normal opera-
open emitter
• Different serial interface bit structures
t
CH
SCLK
t
t
CSS0
t
CL
CSS1
t
CSH1
CS
t
t
CSWH
DH
t
DS
DIN
D6
D5
D4
D3
D2
D1
D0
Figure 5. Serial-Interface Timing
______________________________________________________________________________________ 27
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
and sink currents are programmed to 0mA. Maximum
dissipation occurs when the source and sink currents
are both at 35mA, the V _ is at an extreme of the
Table 5. Shift Register Functions
BIT NAME
DESCRIPTION
DUT
voltage range (-1.5V or +6.5V), and the diode bridge is
fully commutated. Under these conditions, the addition-
al power dissipated (per channel) is:
Channel 1 Write Enable. Set to 1 to update the
control byte for channel 1. Set to 0 to make no
changes to channel 1.
D7
D6
CH1
If DUT_ is sourcing current:
Channel 2 Write Enable. Set to 1 to update the
CH2 control byte for channel 2. Set to 0 to make no
changes to channel 2.
P
= (V
- V ) x I
DUT_ EE SOURCE
D
If DUT_ is sinking current:
= (V - V
P
D
) x I
SINK
CC
DUT_
Low-Leakage Select. Set to 1 to put driver,
load, and clamps in low-leakage mode.
D5 LLEAK Comparators remain active in low-leakage
mode, but at reduced speed. Set to 0 for
normal operation.
DUT_ sources the programmed (low) current when
> V . The path of the current is from DUT_
V
DUT_
COM_
through the outside of the diode bridge and the source
(low) current source to V . The programmed sink cur-
EE
rent is greatly reduced by the class AB load architecture.
Termination Select. Driver Termination Select
Bit. Set to 1 to force the driver output to the
D4 TMSEL DTV_ voltage when RCV_ = 1 (term mode). Set
to 0 to place the driver into high-impedance
DUT_ sinks the programmed (high) current when V
DUT_
through
< V
. The path of the current is from V
COM_
CC
the sink (high) current source and the outside of the
diode bridge to DUT_. The programmed source current
is greatly reduced by the class AB architecture.
mode when RCV_ = 1 (high-Z). See Table 1.
D3
D2
SC1
SC0
Driver Slew Rate Select. SC1 and SC0 set the
driver slew rate. See Table 2.
of the exposed-pad package is very low, approxi-
θ
JC
mately 1°C/W to 2°C/W. Die temperature is thus highly
dependent upon the heat removal techniques used in
the application. Maximum total power dissipation
occurs under the following conditions:
Differential Comparator Enable. Set to 1 to
enable the differential comparators and
disable the CH_ window comparators. Set to 0
to enable the CH_ window comparators and
disable the differential comparators. See
Tables 3a and 3b.
D1 CDIFF
D0 LDDIS
• V
= +10.5V
CC
• V = -5.25V
EE
• I
= I
= 35mA for both channels
SINK
SOURCE
Load Disable. Set LDDIS to 1 to disable the
load. Set to 0 for normal operation. See Table 4.
• Load enabled
• V
• V
= -1.5V
DUT_
= +0.5V
COM_
Temperature Monitor
Under these extreme conditions, the total power dissi-
pation is 3.9W typical and 4.4W maximum. If the die
temperature cannot be maintained at an acceptable
level under these conditions, use software clamping to
limit the load output currents to lower values and/or
reduce the supply voltages.
The MAX9969 supplies a temperature output signal,
TEMP, that asserts a 3.33V nominal output voltage at a
+70°C (343K) die temperature. The output voltage
changes proportionally with temperature at 10mV/°C.
Heat Removal
Under normal circumstances, the MAX9969 requires
heat removal through the exposed pad by use of an
external heat sink. The exposed pad is electrically at
EE
isolated.
Power-Supply Considerations
Bypass all V
and V power input pins with 0.01µF
EE
CC
capacitors, and use bulk bypassing of at least 10µF on
each supply.
V
potential, and must be either connected to V or
EE
Chip Information
TRANSISTOR COUNT: 5284
Power dissipation is highly dependent upon the appli-
cation. The Electrical Characteristics table indicates
power dissipation under the condition that the source
PROCESS: Bipolar
28 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Selector Guide
HIGH-SPEED DIGITAL
INPUT TERMINATION (Ω)
COMPARATOR
OUTPUT
TERMINATION
ACCURACY
GRADE
PART
HEAT EXTRACTION
RCV_
DATA_
None
100
LDEN_
MAX9969ADCCQ
MAX9969AGCCQ
MAX9969ALCCQ
MAX9969ARCCQ
MAX9969BDCCQ
MAX9969BGCCQ
MAX9969BLCCQ
MAX9969BRCCQ
A
A
A
A
B
B
B
B
None
None
None
100
None
100
Top
Top
Top
Top
Top
Top
Top
Top
50Ω to VCCO_
50Ω to VCCO_
None
100
100
100
None
None
100
100
100
None
100
None
100
None
50Ω to VCCO_
50Ω to VCCO_
100
100
100
None
100
100
Pin Configuration
TOP VIEW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
TEMP
1
2
3
4
5
6
7
8
9
75 TDATA1
74 NDATA1
73 DATA1
72 TRCV1
71 NRCV1
70 RCV1
V
EE
GND
V
CC
GND
N.C.
DUT1
N.C.
69 TLDEN1
68 NLDEN1
67 LDEN1
V
EE
GND 10
66
V
CC
V
11
12
65 DIN
64 SCLK
63 THR
62 CS
CC
V
EE
GS 13
MAX9969
V
14
15
EE
V
CC
61 RST
GND 16
17
60
V
EE
V
EE
59 LDEN2
58 NLDEN2
57 TLDEN2
56 RCV2
N.C. 18
DUT2 19
N.C. 20
GND 21
55 NRCV2
54 TRCV2
53 DATA2
52 NDATA2
51 TDATA2
V
CC
22
GND 23
24
V
EE
GND 25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
______________________________________________________________________________________ 29
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
30 ______________________________________________________________________________________
Dual, Low-Power, 1200Mbps ATE
Driver/Comparator with 35mA Load
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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